Shift Registers

Transcription

Shift Registers

EKT 121 / 4
ELEKTRONIK DIGIT 1
Chapter 3:
Sequential Logic Circuit
– Shift Register -
3.2 Shift Register
Basic
shift register function
Serial in / serial out shift registers
Serial in / parallel out shift registers
Parallel in / serial out shift registers
Parallel in / parallel out shift registers
Bidirectional shift registers
Shift register applications
© Copyright 2000 Indiana University Board of Trustees
Sequential Logic Circuits
Combinational
outputs
Memory outputs
Combinational
logic
Memory
elements
Inputs
Sequential circuit = Combinational logic + Memory Elements
Current State of A sequential Circuit:
Value stored in memory elements (value of state variables).
State transition:
A change in the stored values in memory elements thus changing
the sequential circuit from one state to another state.
Registers

A register is a memory device that can be
used to store more than one-bit information
A register is usually realized as several flipflops with common control signals that
control the movement of data to and from
the register
A register is a generalization of a flip-flop
where a flip-flop store one bit, a register
stores several bits
Registers

An n-bit register is a collection of n D flipflops with a common clock used to store n
related bits.
1D
74LS175
Q
D
CLR
2D
Q
Q
D
CLR
Q
1Q
Example:
74LS175 4-bit register
/1Q
74LS175
CLK
CLR
2Q
/2Q
1D
3D
Q
D
CLR
4D
CLK
Q
Q
D
CLR
Q
3Q
/3Q
4Q
/4Q
2D
3D
4D
/CLR
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
Shift Registers

Multi-bit register that moves stored data bits
left/right ( 1 bit position per clock cycle)
– Shift Left is towards MSB
Q3 Q2 Q1
Q0
0
1
1
1
Q3 Q2 Q1
LSI
1
1
1
Q0
LSI
– Shift Right (or Shift Up) is towards MSB
RSI
Q3 Q2 Q1
Q0
0
1
1
1
Q3 Q2 Q1
RSI
0
1
Q0
1
Basic Shift Register Functions

Consist of an arrangement of flip-flops
Important in applications involving
storage and transfer of data (data
movement) in digital system
Used for storing and shifting data (1s
and 0s) entered into it from an external
source and possesses no characteristic
internal sequence of states.
D flip-flops are use to store and move
data
The flip-flop as a storage element
When a 1 is on D, Q
becomes a 1 at
triggering edge of CLK or
remains a 1 if already in
the SET state
When a 0 is on D, Q
becomes a 0 at
triggering edge of CLK or
remains a 0 if already in
the RESET state
Basic data movement in shift
registers
(Four bits are used for illustration. The bits move in the
direction of the arrows.)
Types of Shift Register
1.
2.
3.
4.
Serial In / Serial Out Shift Registers
(SISO)
Serial In /Parallel Out Shift Registers
(SIPO)
Parallel In / Serial Out Shift Registers
(PISO)
Parallel In / Parallel Out Shift Registers
(PIPO)
Serial In, Serial Out Shift Register
(SISO)
SRG n
SERIN
CLOCK
D
>
SI
Q
CLK
D
SO
For a n-bit SRG:
Serial Out = Serial In delayed
by n clock period
Q
CLK
4-bit shift register example:
serin: 1 0 1 1 0 0 1 1 1 0
serout: - - - - 1 0 1 1 0 0
clock:
•
•
•
D
Q
SEROUT
CLK
(SISO)
(SISO)
(SISO)
(SISO)
Serial In, Parallel Out Shift register
(SIPO)
SERIN
CLOCK
D
Q
1Q
CLK
D
Q
SRG n
>
SI
2Q
CLK
CLK
(SO)
Serial to Parallel Converter
•
•
•
D
1Q
2Q
•
•
•
nQ
Q
nQ
Example: 4-bit shift register
serin: 1 0 1 1 0 0 1 1 1 0
1Q: - 1 0 1 1 0 0 1 1 1
2Q: - - 1 0 1 1 0 0 1 1
3Q: - - - 1 0 1 1 0 0 1
4Q: - - - - 1 0 1 1 0 0
clock:
Serial In, Parallel Out Shift register
(SIPO)
• Data bits entered serially (right-most bit first)
• Difference from SISO is the way data bits are taken
out of the register – in parallel.
• Output of each stage is available
Example :
The states of 4-bit register (SRG 4) for the data input
and clocks waveforms.
*** Assume the register initially contains all 1s
Parallel In, Serial Out Shift Register
(PISO)
CLOCK
LOAD/SHIFT
SERIN
1D
1Q
S
D
L
CLK
2Q
S
2D
Q
D
L
Q
CLK
Parallel to Serial
Converter
•
•
•
Load/Shift=1
Di Qi
Load/Shift=0
Qi Qi+1
S
ND
L
•
•
•
NQ
D
CLK
Q
SEROUT
4-bit parallel in/serial out shift register
(PISO)
Parallel In, Parallel Out Shift Register
(PIPO)
CLOCK
LOAD/SHIFT
SERIN
1D
S
D
L
D
L
General Purpose:
Makes any kind of
(left) shift register
Q
2Q
Q
NQ
CLK
•
•
•
S
ND
1Q
CLK
S
2D
Q
L
•
•
•
D
CLK
Parallel In, Parallel Out Shift Register
(PIPO)
Bi-directional Shift Registers
Data
can be shifted left
Data can be shifted right
A parallel load maybe possible
74HC194 is an bidirectional universal
shift register
Bi-directional Universal Shift Registers
11
1
10
Modes:
Hold
Load
Shift Right
Shift Left
9
7
6
5
4
3
2
CLK
CLR
S1
S0
LIN
D
C
B
A
RIN
74x194
R
QD
QC
QB
QA
L
12
13
14
15
4-bit Bi-directional Universal (4-bit) PIPO
Function
Hold
Shift right/up
Shift left/down
Load
Mode
S1 S0
0
0
0
1
1
0
1
1
Next state
QA* QB* QC*
QA QB QC
RIN QA QB
QB QC QD
A
B
C
QD*
QD
QC
LIN
D
Four-bit Johnson counters
Five-bit Johnson counters
A 10-bit ring counter
Shift Register Applications

State Registers
– Shift registers are often used as the state register in a
sequential device. Usually, the next state is determined by
shifting right and inserting a primary input or output into
the next position (i.e. a finite memory machine)
– Very effective for sequence detectors

Serial Interconnection of Systems
– keep interconnection cost low with serial interconnect

Bit Serial Operations
– Bit serial operations can be performed quickly through
device iteration
– Iteration (a purely combinational approach) is expensive (in
terms of # of transistors, chip area, power, etc).
– A sequential approach allows the reuse of combinational
functional units throughout the multi-cycle operation
Shift Register Applications Example:
Serial Interconnection of Systems
CLOCK
Transmitter
Control
Circuits
Parallel
Data from
A-to-D
converter
n
Parallelto-serial
converter
Control
/SYNC
Receiver
Circuits
Serial DATA
Serial-toparallel
converter
One bit
Parallel
Data to
D-to-A
converter
n
8-Bit Serial Adder
CTL
CLK
x7
x6
x5
7
6
5
y7
y6
y5
7
6
5
x0
...
Sequential Implementation of:
Z[7..0] = X[7..0] + Y[7..0]
0
>
y0
...
0
>
D
Q
Cin
A
FA
Cout
CLK
CLR
B
S
7
6
5
z7
z6
z5
...
0
>
CLEAR_C
V
...
z0
The shift register as a time-delay device
Simplified logic diagram of a
serial-to-parallel converter
Thank you