System-on-Chip Design with SystemC

Transcription

System-on-Chip Design
with SystemC
Joachim Gerlach <[email protected]>
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen
Department of
Computer
Engineering
Contents
q
Background & Basics
m System-on-Chip Design
m C/C++ Based System Design
m The SystemC Approach
m SystemC Licensing Model
m Open SystemC Community
q
Introduction to SystemC 1.0
m Modules & Hierarchie
m Processes
m Ports & Signals
m Data Types & Fixed Point Data Types
q
Design Example A
m Simple 2-Process Scenario
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
1
University of
Tübingen
Contents
Department of
Computer
Engineering
q
Design Example B
m JPEG Compression / Decompression Stream
q
Design Activities
m Modeling
m Simulation
m Debugging
q
Tool Support
m Synopsys: SystemC Compiler
m CoWare: N2C
m C-Level Design: System Compiler
m Frontier Design: AxRT Builder
q
Outlook to SystemC 1.1
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
2
SYSTEMC
TM
Background & Basics
University of
Tübingen
Productivity Gap
Department of
Computer
Engineering
complexity
[gates]
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
1G
256M
memory
processors
100M
16M
gates
10M
Tool
Support
Pentium II
Pentium (0,35 µm)
1M
1M
256K
1K
1K
1970
4K
8008
486DX
386DX
64K
16K
10K
/ chip
4M
100K
Design
Activities
higher
abstraction
level
64M
8080
(source: ICE)
1980
1990
SystemC 1.1
Wolfgang
Rosenstiel
(0,8 µm)
productivity
gap
8088
1980
1990
IP re-use
hardware
software
co-design
design
automation
2000
gates / day
2000
time
(source: MEDEA Design Automation Roadmap 1999)
Joachim Gerlach
4
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
System Level Design
q
System-on-Chips (SoC) designs
q
SoC designs contain
m
Multiple design domains: hardware, software, analog, ...
m
Multiple source components: DSPs, ASICs, IP-Cores, ...
m
Hard constraints: realtime, low power, ...
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
5
University of
Tübingen
System Level Design Flow
Department of
Computer
Engineering
specification
functional
validation
Background
& Basics
co-design
architectural
validation
SystemC 1.0
Design
Example B
software
implementation
software architecture
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
architectural
models
hw/sw
co-simulation
co-verification
hardware
implementation
device
driver
memory
map
RTOS
processor &
peripherals
user
software
application
specific
co-processor
hardware architecture
algorithmic
models
Design
Example A
6
University of
Tübingen
Department of
Computer
Engineering
Benefits of a C/C++ Based Design Flow
q
Background
& Basics
SystemC 1.0
Design
Example A
q
Design
Example B
Design
Activities
Tool
Support
q
SystemC 1.1
Productivity aspect
m
Specification between architect and implementer is executable
m
High speed and high level simulation and prototyping
m
Refinement, no translation into hardware (no “semantic gap”)
System level aspect
m
Tomorrow’s systems designers will be designing
mostly C/C++
software and less hardware !
m
Co-design, co-simulation, co-verification, co-debugging, ...
Re-use
m
System
aspect
Architect
SoC
Design
Marketing
& Sales
OptimumC/C++
re-use support by object-oriented techniques
HDL
Wolfgang
Rosenstiel
m
q
Efficient testbench re-use
Software
Hardware
Especially C/C++ is widespread
and
commonly used !
Joachim Gerlach
Designer
Designer
7
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Drawbacks of a C/C++ Based Design Flow
q
C/C++ is not created to design hardware !
q
C/C++ does not support
m
SystemC 1.0
Design
Example A
Design
Example B
l
m
m
SystemC 1.1
Wolfgang
Rosenstiel
Hardware is inherently concurrent, operates in parallel
Reactivity
l
m
Clocks, time sequenced operations
Concurrency
l
m
Signals, protocols
Notion of time
l
Design
Activities
Tool
Support
Hardware style communication
Hardware is inherently reactive, responds to stimuli,
interacts with its environment (→ requires handling of exceptions)
Hardware data types
l
Joachim Gerlach
Bit type, bit-vector type, multi-valued logic types,
signed and unsigned integer types, fixed-point types
8
University of
Tübingen
How to Get “Synthesizable C/C++” ?
Department of
Computer
Engineering
Background
& Basics
q
synthesizable
subset of C
restriction to
synthesizable subset
SystemC 1.0
Design
Example A
C
Step-1:
q
Design
Example B
Step-2:
C++
extension by
hardware-related
components
Design
Activities
Tool
Support
m
SystemC 1.1
m
Wolfgang
Rosenstiel
q
synthesizable
subset of C++
hardware type
communication
new language constructs
(HardwareC, C*)
library based approach
(SystemC, Cynlib)
notion
of time
hardware
data types
synthesizable
subset
reactivity
concurrency
Step-1 and step-2 can be swapped !
Joachim Gerlach
9
University of
Tübingen
Department of
Computer
Engineering
Why SystemC for System Design ?
q
The Gap
m
Background
& Basics
m
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
q
Tomorrow’s systems designers will be designing
mostly software and little hardware
A software language is not capable of describing
concurrency, clocks, hardware data types, reactivity
Requirements
m
m
m
m
Allow hardware/software co-design and co-verification
Fast simulation for validation and optimization
Smooth path to hardware and software
Support of design and architectural re-use
Joachim
Gerlach
Joachim Gerlach
10
University of
Tübingen
Department of
Computer
Engineering
What is SystemC ?
q
A library of C++ classes
m Processes (for concurrency)
m Clocks (for time)
m Modules, ports, signals (for hierarchy)
m Waiting, watching (for reactivity)
m Hardware data types
q
A modeling style
m ... for modeling systems consisting of multiple
design domains, abstraction levels, architectural
components, real-life constraints
q
A light-weight simulation kernel
m ... for high-speed cycle-accurate simulation
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
11
University of
Tübingen
How Does it Work ?
Department of
Computer
Engineering
System
Background
& Basics
C/C++ Testbench
C/C++ Software
Component
SystemC 1.0
Design
Example A
Design
Example B
Modeling
Constructs
C/C++ Hardware
Component
DSP
IP-Core
ASIC
Interface
Design
Activities
Tool
Support
SystemC
SystemC 1.1
Joachim
Gerlach
Standard
C++ Compiler
Executable = Simulator
Joachim Gerlach
12
University of
Tübingen
Department of
Computer
Engineering
Benefits of a SystemC-Based Design Flow
q
Classical HDL based design methodology
Background
& Basics
SystemC 1.0
Design
Example A
system
architect
C/C++
4. hand over
specification
document
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
1. conceptualize
2. simulate in C/C++
3. write specification
3. document
6. (re)implement in HDL
7. (re)validate HDL
7. implementation
HDL
8. synthesize from HDL
hardware
designer
Wolfgang
Rosenstiel
Joachim Gerlach
13
University of
Tübingen
Department of
Computer
Engineering
Benefits of a SystemC-Based Design Flow
q
C/C++ based design methodology
Background
& Basics
C/C++
SystemC 1.0
1. conceptualize
2. simulate in C/C++
3. write specification document
Design
Example A
Design
Example B
Design
Activities
system
architect
Tool
Support
4. hand over
• executable specification
• testbenches
• written specification
hardware
designer
C/C++
5. understand specification
6. refine in C/C++
7. validate re-using testbenches
8. synthesize from C/C++
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
14
University of
Tübingen
Department of
Computer
Engineering
The SystemC Approach
q
Background
& Basics
The requirements...
m
Fast system modeling containing multiple source components
m
Model once for multiple abstraction level, multiple users,
multiple purposes
SystemC 1.0
Design
Example A
q
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
The problem...
m
q
No common format for describing components
The approach...
m
Promote a standard C/C++ based modeling platform
... to model and exchange system level components and IP
... to build interoperable tools infrastructure
Wolfgang
Rosenstiel
Joachim Gerlach
15
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
The SystemC Approach
q
Why C/C++ based ?
m
Specification between architect and implementer is executable
m
High simulation speed at higher level of abstraction
m
Refinement, no translation into HDL (no “semantic gap”)
m
Efficient testbench re-use
Design
Example B
C/C++
Design
Activities
System
Architect
Tool
Support
SystemC 1.1
SoC
Design
C/C++
Wolfgang
Rosenstiel
HDL
Software
Designer
Joachim Gerlach
Marketing
& Sales
Hardware
Designer
16
University of
Tübingen
SystemC Modeling Platform
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
S Y S T E M
C
TM
is...
... a methodology for modeling SoC designs consisting of
... DSPs, ASICs, IP-Cores, Interfaces, ...
... a C++ library extending C/C++ by concurrency, timing,
... reactivity, communication, signal / data types, ...
Design
Activities
Tool
Support
... a cycle-accurate high-speed simulation
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
17
University of
Tübingen
SystemC Design Methodology
Department of
Computer
Engineering
your standard
C/C++ development
environment
header files
SystemC 1.0
linker
class library
and
simulation kernel
debugger
....
Design
Example B
IP-Core
compiler
libraries
Design
Example A
Design
Activities
„make“
Tool
Support
e
abl on “
t
u
ec icati
x
e
„ ecif
sp
SystemC 1.1
DSP
Interface
........
Background
& Basics
ASIC
source files
for system and
testbenches
a.out
executable = simulation
Wolfgang
Rosenstiel
Joachim Gerlach
18
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC Key Features
q
Concurrency
(Sync. and async. processes)
q
Notion of time
(Multiple clocks with arbitrary phase relation)
q
Data types
(Bit vectors, arbitrary precision integers, ...)
SystemC 1.0
Design
Example A
Design
Example B
v1.0: arbitrary precision fixed point data types
q
Communication
(Signals, channels)
v1.0: advanced communication protocols
q
Reactivity
(Watching for events)
Design
Activities
q
Debug support
(Waveform tracing)
Tool
Support
q
Simulation support
SystemC 1.1
q
Support of multiple abstraction levels and iterative refinement
q
Support of functional model creation
q
....
Wolfgang
Rosenstiel
Joachim Gerlach
19
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Open Community Licensing
q
How to get SystemC ?
Steering Group
SystemC v0.9
SystemC 1.0
including:
Design
Example A
download
Design
Example B
• Modeling specification
• Source code
(reference implementation)
• Reference manual
Design
Activities
Tool
Support
www.SystemC.org
SystemC 1.1
click-through web-based
license agreement
User
Wolfgang
Rosenstiel
Joachim Gerlach
20
University of
Tübingen
Department of
Computer
Engineering
Open SystemC Steering Group
q
ARM
q
Cadence
Background
& Basics
q
CoWare
SystemC 1.0
q
Ericsson
Design
Example A
q
Fujitsu Microelectronics
q
Infineon Technologies
q
Lucent Technologies
q
Motorola
q
NEC
q
Sony Corporation
q
STMicroelectronics
q
Synopsys
q
Texas Instruments
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
21
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Community Charter Members
Actel
Fujitsu Microelectronics
Sony Corporation
Alcatel
Genedax
Stellar Semiconductor
Altera Corporation
IKOS Systems
STMicroelectronics
American Applied Research
I-Logix
Summit Design
Aptix
Infineon Technologies
Sun Microsystems
Arcadia Design Systems
Integrated Silicon Systems
SynaptiCAD
ARC Cores
Intellectual Property
Synchronicity
Aristo Technology
Internet CAD
Synopsys
ARM
JTA Research
Tensilica
Billions of Operations Per Second
LogicVision
Texas Instruments
CAE Plus
Lucent Technologies
TransModeling
Chameleon Systems
Magma Design Automation
Ultima
Co-Design Automation
MIPS Technologies
Verplex
CoWare
Monterey Design Systems
Viewlogic
CSELT
Motorola
Virtio
Denali
Red Hat
Virtual Silicon Technologies
Ericsson
Seva Technologies (Intrinsix)
Willamette HDL
Frequency Technology
Sican Microelectronics
Wind River Systems
Frontier Design
Snaketech
Xilinx
Wolfgang
Rosenstiel
Joachim Gerlach
22
University of
Tübingen
Department of
Computer
Engineering
Open Community Licensing
q
Community members
m
No licensing fees, anybody / any company is free and welcome
to join the community
SystemC 1.0
m
Right and responsability to contribute enhancements
Design
Example A
m
Designers can create and share models with other companies,
EDA vendors can build SystemC based tools
Background
& Basics
Design
Example B
q
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
q
Steering Group
m
Drives convergence and interoperability
m
Ensures open evolution and structured innovation
Goal:
m
Make SystemC a de-facto-standard for system-level design
m
Provide a foundation to build a market upon
Joachim Gerlach
23
University of
Tübingen
Department of
Computer
Engineering
SystemC
q
Short History of SystemC
Background
& Basics
SystemC 1.0
Design
Example A
V0.9 launches
9/27/1999
Scenery
V1.0 release
3/28/2000
Design
Example B
Design
Activities
fixed point datatypes
1997 DAC Paper
Tool
Support
SystemC 1.1
HDL constructs
1997
1998
1999
2000
Wolfgang
Rosenstiel
Joachim Gerlach
24
University of
Tübingen
Department of
Computer
Engineering
SystemC
q
European SystemC Users Group
m
Background
& Basics
SystemC 1.0
Design
Example A
m
Communication platform for SystemC users
take a look at:
Information flow between SystemC users und Steering Group
www-ti.informatik.uni-tuebingen.de/~systemc
m
Acceleration of SystemC evolution and standardization
m
Events:
Design
Example B
Design
Activities
Tool
Support
FDL’2000
1st European SystemC™
Users Group Meeting
3rd European SystemC™
Users Group Meeting
SystemC™
Release 1.0
SystemC 1.1
Wolfgang
Rosenstiel
2nd European SystemC™
Users Group Meeting
European SystemC™
Users Group Conference
(with DATE’2001)
2000
January 31
2000
Joachim Gerlach
2001
March 28 June 30 September 4-8
2000
2000
2000
March 12-16
2001
25
SYSTEMC
TM
SystemC 1.0
University of
Tübingen
Department of
Computer
Engineering
Modules
q
q
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Modules are basic building blocks of a SystemC design
A module contains processes (Õ functionality)
and/or sub-modules (Õ hierarchical structure)
SC_MODULE( module_name ) {
// Declaration of module ports
// Declaration of module signals
// Declaration of processes
// Declaration of sub-modules
SC_CTOR( module_name ) {
// Module constructor
// Specification of process type and sensitivity
// Sub-module instantiation and port mapping
}
// Initialization of module signals
};
Joachim Gerlach
27
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Modules
q
A module correspond to a C++ class
class data members Ö ports
class member functions Ö processes
class constructor Ö process generation
.....
SC_MODULE( module_name ) {
.....
};
struct module_name : sc_module {
.....
};
Joachim
Gerlach
Joachim Gerlach
28
University of
Tübingen
Department of
Computer
Engineering
Ports
q
q
Background
& Basics
q
SystemC 1.0
q
Design
Example A
Design
Example B
// input port declaration
sc_in< type > in_port_name;
Design
Activities
// output port declaration
sc_out< type > out_port_name;
Tool
Support
// bidirectional port declaration
sc_inout< type > inout_port_name;
SystemC 1.1
Joachim
Gerlach
External interface of a module
Passing data from and to processes / sub-modules
Triggering of actions within the module
A ports has a mode (direction) and a type
mode: in, out, inout
type: C++ type, SystemC type, user-defined type
q
Vector port / port array:
sc_out< int > result [32];
Joachim Gerlach
29
University of
Tübingen
Department of
Computer
Engineering
Signals
q
q
Background
& Basics
q
SystemC 1.0
q
Design
Example A
Design
Example B
Design
Activities
Connects a port of one module to the port of another module
Local to a module
Signal semantics is the same as VHDL and Verilog
deferred assignment semantics
A signal has a type
type: C++ type, SystemC type, user-defined type
// signal declaration
sc_signal< type > signal_name;
q
Tool
Support
Vector signal / signal array:
sc_signal< double > a[4];
SystemC 1.1
q
Joachim
Gerlach
Internal data storage not by signals but by local variables
Local variable types: C++ types, SystemC types, user-defined types
Joachim Gerlach
30
University of
Tübingen
Department of
Computer
Engineering
Ports & Signals
q
Port and Signal Binding
m
Background
& Basics
m
SystemC 1.0
m
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
q
Ports and signals to be bound need to have the same type
A signal connects two ports
A port is bound to one signal (port-to-signal)
or to one sub-module port (port-to-port)
Resolution
m SystemC supports resolved ports and signals
m Resolved ports/signals have 4-valued logic type (0,1,Z,X)
m Resolved ports/signals allow multiple drivers
m Resolved vector ports/vector signals
sc_in_rv< n > x;
sc_signal_rv< n> y;
Joachim Gerlach
// n bits wide resolved input port
// n bits wide resolved signal
31
University of
Tübingen
Department of
Computer
Engineering
Clocks
Background
& Basics
q
SystemC provides a special object sc_clock
Clocks generate timing signals to synchronize events
Multiple clocks with arbitrary phase relations are supported
SystemC 1.0
q
Clock generation:
q
q
Design
Example A
sc_clock clock_name (“label”, period, duty_ratio, offset, start_value);
Design
Example B
Example:
sc_clock my_clk (“CLK”, 20, 0.5, 5, true);
true
Design
Activities
0
Tool
Support
q
20
5
false
5
15
25
35
45
55
Clock binding:
SystemC 1.1
Example:
my_module.clk( my_clk.signal() );
Joachim
Gerlach
Joachim Gerlach
32
University of
Tübingen
Department of
Computer
Engineering
Data Types
q
SystemC supports
m Native C/C++ types
m SystemC types
m User-defined types
q
SystemC types
m 2-value (‘0’, ‘1’) logic / logic vector
m 4-value (‘0’, ‘1’, ‘Z’, ‘X’) logic / logic vector
m Arbitrary sized integer (signed/unsigned)
m Fixed point types (signed/unsigned, templated/untemplated)
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
33
University of
Tübingen
Department of
Computer
Engineering
Native C/C++ Data Types
q
Integer types:
m char
m unsigned char
m short
m unsigned short
m int
m unsigned int
m long
m unsigned long
q
Floating point types
m float
m double
m long double
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
34
University of
Tübingen
SystemC Data Types
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Type
Description
sc_bit
2-value single bit
sc_logic
4-value single bit
sc_int
1 to 64 bit signed integer
sc_uint
1 to 64 bit unsigned integer
sc_bigint
arbitrary sized signed integer
sc_biguint
arbitrary sized unsigned integer
sc_bv
arbitrary length 2-value vector
sc_lv
arbitrary length 4-value vector
sc_fixed
templated signed fixed point
sc_ufixed
templated unsigned fixed point
sc_fix
untemplated signed fixed point
sc_ufix
untemplated unsigned fixed point
Joachim Gerlach
35
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
sc_bit / sc_logic
q
2-value single bit type: sc_bit
m ‘0’=false, ‘1’=true
q
4-value single bit type: sc_logic
m ‘0’=false, ‘1’=true, ‘X’=unknown/indeterminate value,
‘Z’=high-impedance/floating value
q
Features:
m Mixed use of operand types sc_bit and sc_logic
m Use of character literals for constant assignments
q
sc_bit / sc_logic operators
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Bitwise
& (and)
| (or)
^ (xor)
~ (not)
Assignment
=
&=
|=
^=
Equality
==
!=
Joachim Gerlach
36
University of
Tübingen
Department of
Computer
Engineering
sc_int / sc_uint / sc_bigint / sc_biguint
q
Fixed precision integer types
m Signed:
tsc_int<n> (n: word length, 1 ≤ n ≤ 64)
m Unsigned: sc_uint<n> (n: word length, 1 ≤ n ≤ 64)
q
Arbitrary precision integer types
m Signed:
tsc_bigint<n> (n: word length, n > 64)
m Unsigned: sc_biguint<n> (n: word length, n > 64)
q
Features:
m Mixed use of operand types sc_int, sc_uint, sc_bigint,
sc_biguint and C++ integer types
m Truncation and/or sign extension if required
m 2’s complement representation
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
37
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
sc_int / sc_uint / sc_bigint / sc_biguint
q
sc_int / sc_uint / sc_bigint / sc_biguint operators
Bitwise
Arithmetic
Assignment
Equality
Relational
Auto-Ink/Dek
Bit/Part Select
Concatenation
&
+
=
==
<
++
[]
(,)
|
^
*
+= -=
!=
<= >
-range()
~
/
*=
>>
%
/=
<<
%=
&=
|=
^=
>=
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
38
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
sc_bv / sc_lv
q
Arbitrary length bit vector:
jsc_bv<n> (n: vector length)
q
Arbitrary length logic vector: sc_lv<n> (n: vector length)
q
Features:
m Assignment between sc_bv and sc_lv
m Use of string literals for vector constant assignments
m Conversions between sc_bv/sc_lv and SystemC integer types
m No arithmetic operation available
q sc_bv / sc_lv
Bitwise
Assignment
Equality
Bit/Part Select
Concatenation
Reduction
Conversion
Joachim Gerlach
&
|
^
~
>>
<<
=
+= -= *= /=
%= &= |= ^=
==
!=
[]
range()
(,)
and_reduction() or_reduction() xor_reduction()
to_string()
39
University of
Tübingen
Department of
Computer
Engineering
sc_fixed / sc_ufixed / sc_fix / sc_ufix
q
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Joachim
Gerlach
templated
signed
unsigned
untemplated
q
templated
- static arguments (to be known at compile time)
untemplated - nonstatic arguments (to be configured during runtime)
q
signed
unsigned
q
Features:
m Operations performed using arbitrary precision
m Multiple quantization and overflow modes
Tool
Support
SystemC 1.1
Fixed point types
m sc_fixed
m sc_ufixed
m sc_fix
m sc_ufix
Joachim Gerlach
- 2’s complement representation
40
University of
Tübingen
Department of
Computer
Engineering
q
sc_fixed< wl, iwl, q_mode, o_mode, n_bits > var_name (init_val);
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Templated signed fixed point type: sc_fixed
q
Arguments:
m wl
m iwl
m q_mode
m o_mode
m n_bits
- total number of bits
- number of integer bits
- quantization mode
(optional)
- overflow_mode
(optional)
- number of bits for overflow mode (optional)
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
41
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
q
Example:
sc_fixed< 8, 4 > my_var (-1.75);
( 1.75 )10 = ( 0001.1100 )2
4
Design
Example A
Design
Example B
Design
Activities
Tool
Support
8
1’s complement of ( 0001.1100 )2 = ( 1110.0011 )2
2’s complement of ( 0001.1100 )2 = ( 1110.0100 )2
my_var:
sign bit
1
SystemC 1.1
1
1
integer bits
Joachim
Gerlach
Joachim Gerlach
0
0
1
0
0
fractional bits
42
University of
Tübingen
Department of
Computer
Engineering
q
Quantization and overflow modes
Background
& Basics
Quantization Mode
Overflow Mode
SystemC 1.0
Rounding to plus infinity
Saturation
Rounding to zero
Saturation to zero
Rounding to minus infinity
Symmetrical saturation
Convergent rounding
Wrap-around
Truncation
Sign-magnitude wrap-around
Design
Example A
Design
Example B
Design
Activities
Truncation to Zero
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
43
University of
Tübingen
Department of
Computer
Engineering
User-Defined Data Types
q
User-defined data types can be used for ports and signals
sc_signal< complex > c;
Background
& Basics
where
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
class complex {
private:
double re;
double im;
public:
complex ()
{`re=0.0; im=0.0; }
complex (double r, double i) {`re=r; im=i; }
void set(double r, double i) { re=r; im=i; }
double get_re()
{ return re; }
double get_im()
{ return im; }
int.....
int operator== (const complex &c) const {
};
if ( ( re == c.re ) && ( im == c.im() ) )
return 1;
else
return 0;
}
};
44
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Modules & Hierarchie
q
Modules may contain sub-modules (Õ hierarchical structure)
q
In SC_MODULE:
// sub-module declaration
module_type *my_module;
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
q
In the module constructor of SC_MODULE:
// sub-module instantiation and port mapping
Tool
Support
SystemC 1.1
Joachim
Gerlach
}
my_module = new module_type ( “label”);
my_module -> in1 (sig1);
my_module -> in2 (sig2);
my_module
my_module -> out1 (sig3);
sig1
in1
out1
in2
sig2
Joachim Gerlach
sig3
45
University of
Tübingen
Department of
Computer
Engineering
Modules & Hierarchie
Example:
q
SC_MODULE( plus ) {
sc_in<int> i1;
sc_in<int> i2;
sc_out<int> o1;
.....
alu
Background
& Basics
SystemC 1.0
plus
a
b
i1
o1
i2
Design
Example A
minus
Design
Example B
Design
Activities
Tool
Support
};
e
c
i1
o1
i2
d
SC_MODULE( alu ) {
sc_in<int> a;
sc_in<int> b;
sc_in<int> c;
sc_out<int> d;
plus *p;
minus *m;
SC_MODULE( minus ) {
sc_in<int> i1;
sc_in<int> i2;
sc_out<int> o1;
.....
};
sc_signal<int> e;
SC_CTOR( alu ) {
p = new plus ( "PLUS“ );
p->i1 (a);
p->i2 (b);
p->o1 (e);
d=(a+b)-c
SystemC 1.1
m = new minus ( "MINUS“ );
(*m) (e,c,d);
Joachim
Gerlach
}
};
Joachim Gerlach
46
University of
Tübingen
Department of
Computer
Engineering
Processes
q
Process Semantics
m Encapsulates functionality
m Basic unit of concurrent execution
m Not hierarchical
q
Process Activation
m Processes have sensitivity lists
m Pocesses are triggered by events on sensitive signals
q
Process Types
m Method (SC_METHOD)
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
asynchronous block, like a sequential function
SystemC 1.1
m
Joachim
Gerlach
Thread (SC_THREAD)
asynchronous process
m
Clocked Thread (SC_CTHREAD)
synchronous process
Joachim Gerlach
47
University of
Tübingen
Processes
Department of
Computer
Engineering
SC_METHOD
SC_THREAD
SC_CTHREAD
triggered
by signal events
by signal events
by clock edge
SystemC 1.0
infinite
loop
no
yes
yes
Design
Example A
execution
suspend
no
yes
yes
Design
Example B
suspend
& resume
-
wait()
wait()
wait_until()
SC_METHOD(p);
SC_THREAD(p);
sensitive(s);
sensitive_pos(s);
sensitive_neg(s);
sensitive(s);
sensitive_pos(s);
sensitive_neg(s);
Background
& Basics
Design
Activities
Tool
Support
construct
&
sentisize
method
SystemC 1.1
Joachim
Gerlach
modeling
combinational
example
logic
(hardware)
Joachim Gerlach
sequential logic
at RT level
(asynchronous
reset, etc.)
SC_CTHREAD
(p,clock.pos());
SC_CTHREAD
(p,clock.neg());
sequential logic
at higher design
levels
48
University of
Tübingen
Department of
Computer
Engineering
Processes
q
// process declaration
void my_process ();
Background
& Basics
SystemC 1.0
q
Design
Example A
Design
Activities
SystemC 1.1
Joachim
Gerlach
Instantiation (in module constructor of SC_MODULE)
// specification of process type and sensitivity
SC_METHOD( my_process );
sensitive << sig1 << sig2;
}
Design
Example B
Tool
Support
Declaration of member function (in SC_MODULE)
q
Definition of member function
(in SC_MODULE or somewhere else)
// process specification
void module_name::my_process () {
.....
}
Joachim Gerlach
plus
i1
o1
i2
o1 = i1 + i2
49
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Processes
q
Example: SC_METHOD
SC_MODULE( plus ) {
sc_in<int> i1;
sc_in<int> i2;
sc_out<int> o1;
void plus::do_plus() {
int arg1;
int arg2;
int sum;
void do_plus();
Design
Example B
SC_CTOR( plus ) {
SC_METHOD( do_plus );
sensitive << i1 << i2;
}
Design
Activities
Tool
Support
arg1 = i1.read();
arg2 = i2.read();
sum = arg1 + arg2;
o1.write(sum);
}
};
o1 = i1 + i2;
}
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
50
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Processes
q
Example: SC_THREAD
SC_MODULE( plus ) {
sc_in<int> i1;
sc_in<int> i2;
sc_out<int> o1;
int arg1;
int arg2;
int sum;
while ( true ) {
arg1 = i1.read();
arg2 = i2.read();
sum = arg1 + arg2;
o1.write(sum);
void do_plus();
Design
Example B
SC_CTOR( plus ) {
SC_THREAD( do_plus );
sensitive << i1 << i2;
}
Design
Activities
Tool
Support
};
wait();
}
SystemC 1.1
}
Joachim
Gerlach
Joachim Gerlach
51
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Processes
q
Example: SC_CTHREAD
SC_MODULE( plus ) {
sc_in_clk clk;
SystemC 1.0
sc_in<int> i1;
sc_in<int> i2;
sc_out<int> o1;
Design
Example A
Design
Example B
while ( true ) {
arg1 = i1.read();
arg2 = i2.read();
sum = arg1 + arg2;
o1.write(sum);
void do_plus();
Design
Activities
Tool
Support
void do_plus() {
int arg1;
int arg2;
int sum;
SC_CTOR( plus ) {
SC_CTHREAD( do_plus, clk.pos() );
}
wait();
};
SystemC 1.1
}
}
Joachim
Gerlach
Joachim Gerlach
52
University of
Tübingen
Department of
Computer
Engineering
Waiting and Watching
q
Suspend / reactivate process execution
(SC_THREAD, SC_CTHREAD)
m Suspension:
wait()
m Reactivation: event on a sensitive signal
q
Halt process execution until an event occurs
m wait_until ( my_bool_sig.delayed() == true )
q
Transfer control to a special code sequenze if a specified condition occurs
m watching ( reset.delayed() == true )
m Typical example: watching for reset signal
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
m
(SC_THREAD, SC_CTHREAD)
- watching condition specified in the module constructor
- control is transfered to the beginning of the process (to be handled there)
SystemC 1.1
m
Joachim
Gerlach
Global watching:
(SC_CTHREAD only)
Local watching:
(SC_CTHREAD only)
- allows to specifiy the process region to be watched
- using macros W_BEGIN, W_DO, W_ESCAPE, W_END
- can be nested and combined with global watching
Joachim Gerlach
53
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Cycle-Accurate Simulation Scheduler
Step 1:
All clock signals that change their valueat the current time are
assigned their new value.
Step2:
All SC_METHOD / SC_THREAD processes with inputs that have
changed are executed. The entire bodies of SC_METHOD
processes are executed. SC_THREAD processes are executed
until the next wait() statement suspends execution.
SC_METHOD / SC_THREAD processes are not executed in a
fixed order.
Step3:
All SC_CTHREAD processes that are triggered have their
outputs updated and are saved in a queue to be executed in
step 5. All outputs of SC_METHOD / SC_THREAD processes
that were executed in step 1 are also updated.
Step 4:
Step 2 and step 3 are repeated until no signal changes ist value.
Step 5:
All SC_CTHREAD processes that were triggered and queued in
step 3 are executed. There is no fixed execution order of these
processes. Their outputs are updated at the next active edge
(when step 3 is executed), and therefore are saved internally.
Step6:
Simulation time is advanced to the next clock edge and the
scheduler goes back to step 1.
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
54
SYSTEMC
TM
Design Example A
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC: Example-1
Example
Two processes (process_1 and process_2)
alternately incrementing an integer value
SystemC 1.0
Design
Example A
process_1
int
Design
Example B
a
bool
+5
b
ready_b
ready_a
Design
Activities
process_2
Tool
Support
b
SystemC 1.1
+3
ready_b
a
ready_a
int
bool
Wolfgang
Rosenstiel
Joachim Gerlach
56
University of
Tübingen
Source Code File Structure
Department of
Computer
Engineering
Background
& Basics
systemc.h
process_1.h
process_2.h
process_1.cc
process_2.cc
SystemC 1.0
Design
Example A
Design
Example B
main.cc
library
Design
Activities
Tool
Support
g++
SystemC 1.1
a.out
Wolfgang
Rosenstiel
executable = simulation
Joachim Gerlach
57
University of
Tübingen
Module: process_1
Department of
Computer
Engineering
// header file: process_1.h
SC_MODULE( process_1 ) {
Background
& Basics
Design
Example A
// Ports
sc_in_clk clk;
sc_in<int> a;
sc_in<bool> ready_a;
sc_out<int> b;
sc_out<bool> ready_b;
Design
Example B
// Process functionality
void do_process_1();
SystemC 1.0
// implementation file: process_1.cc
#include "systemc.h"
#include "process_1.h"
void process_1::do_process_1()
{
int v;
while ( true )
{
wait_until( ready_a.delayed() == true );
v = a.read();
v += 5;
cout << "P1: v = “ << v << endl;
b.write( v );
// Constructor
SC_CTOR( process_1 ) {
SC_CTHREAD( do_process_1 , clk.ps() );
}
Design
Activities
Tool
Support
};
SystemC 1.1
ready_b.write( true );
wait();
ready_b.write( false );
}
Wolfgang
Rosenstiel
}
Joachim Gerlach
58
University of
Tübingen
Module: process_2
Department of
Computer
Engineering
// header file: process_2.h
SC_MODULE( process_2 ) {
Background
& Basics
Design
Example A
// Ports
sc_in_clk clk;
sc_in<int> a;
sc_in<bool> ready_a;
sc_out<int> b;
sc_out<bool> ready_b;
Design
Example B
// Process functionality
void do_process_2();
SystemC 1.0
// implementation file: process_2.cc
void process_2::do_process_2()
{
int v;
while ( true )
{
wait_until( ready_a.delayed() == true );
v = a.read();
v += 3;
cout << "P2: v = “ << v << endl;
b.write( v );
// Constructor
SC_CTOR( process_2 ) {
SC_CTHREAD( do_process_2 , clk.ps() );
}
Design
Activities
Tool
Support
};
SystemC 1.1
ready_b.write( true );
wait();
ready_b.write( false );
}
Wolfgang
Rosenstiel
}
Joachim Gerlach
59
University of
Tübingen
Top-Level Module: main
Department of
Computer
Engineering
// implementation file: main.cc
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
int sc_main (int ac,char *av[])
{
sc_signal<int> s1 ( “Signal-1“ );
sc_signal<int> s2 ( “Signal-2“ );
sc_signal<bool> ready_s1 ( “Ready-1“ );
sc_signal<bool> ready_s2 ( “Ready-2“ );
sc_clock clock( "Clock“ , 20 , 0.5 , 0.0 );
process_1 p1 ( “P1“ );
p1.clk( clock );
p1.a( s1 );
p1.ready_a( ready_s1 );
p1.b( s2 );
p1.ready_b( ready_s2 );
process_2 p2 ( “P2“ );
p2.clk( clock );
p2.a( s2 );
p2.ready_a( ready_s2 );
p2.b( s1 );
p2.ready_b( ready_s1 );
s1.write(0);
s2.write(0);
ready_s1.write(true);
ready_s2.write(false);
SystemC 1.1
sc_start(100000);
Wolfgang
Rosenstiel
return 0;
}
Joachim Gerlach
60
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Simulation Results
q
Simulation output
SystemC (TM) Version 1.0 --- Apr 4 2000 10:12:32
ALL RIGHTS RESERVED
Copyright (c) 1988-2000 by Synopsys, Inc.
P1: v = 5
P2: v = 8
P1: v = 13
P2: v = 16
P1: v = 21
P2: v = 24
P1: v = 29
P2: v = 32
P1: v = 37
P2: v = 40
P1: v = 45
P2: v = 48
P1: v = 53
P2: v = 56
P1: v = 61
P2: v = 64
P1: v = 69
P2: v = 72
P1: v = 77
P2: v = 80
.....
Joachim Gerlach
simulation speed:
simulation of 100.000 cycles
takes about 0.08 seconds
on a Sun Ultra Sparc 5
(384 MByte main memory)
(output skipped) comparison to
simulation speed of SystemC 0.9:
simulation of 100.000 cycles
takes about 0.31 seconds
on the same machine
61
SYSTEMC
TM
Design Example B
University of
Tübingen
Department of
Computer
Engineering
SystemC Design Example
q
Background:
Background
& Basics
SystemC
C / C++
SystemC 1.0
Design
Example A
Design
Example B
„top-down“
„bottom-up“
Design
Activities
HDL
„non-coded“
Tool
Support
SystemC 1.1
Transforming HDL into SystemC
Creating new designs in SystemC
Joachim
Gerlach
Joachim Gerlach
SystemC
Transforming C/C++ into SystemC
• Many algorithms exist in C/C++
• Many standardization committees
• (e.g., ISO) use C specifications
63
University of
Tübingen
Department of
Computer
Engineering
q
Application:
JPEG compression and decompression stream
Background
& Basics
SystemC 1.0
Reader
Design
Example A
Input Picture
(pgm)
Design
Example B
Design
Activities
JPEG
Encoder
Compressed
data stream
JPEG
Decoder
Output Picture
(pgm)
Writer
Tool
Support
SystemC 1.1
Joachim
Gerlach
q
Reference implementation:
m 16 modules, approx. 950 lines of C++ code
m by T. Thissenhusen, TU Dresden, Germany
Joachim Gerlach
64
University of
Tübingen
Department of
Computer
Engineering
input pgm-file start
Reader
Background
& Basics
SystemC 1.0
DCT
Design
Example A
IRLEH
Encoder
Design
Example B
Design
Activities
Quant
IZigZag
ZigZag
IQuant
Decoder
Tool
Support
RLEH
SystemC 1.1
IDCT
Writer
Joachim
Gerlach
output pgm-file
Joachim Gerlach
65
University of
Tübingen
Department of
Computer
Engineering
Encoder
Background
& Basics
struct Block {
char data[8][8];
....
};
data_in start
ready
Coeff_8x8
bool
DCT
SystemC 1.0
Design
Example A
Design
Example B
struct Coeff_8x8 {
short data[8][8];
....
};
Quant
clk
ZigZag
Design
Activities
Tool
Support
SystemC 1.1
struct Matrix_64x12 {
short data[64];
....
};
ZigZag
Matrix_64x12 bool
RLEH
Joachim
Gerlach
char data;
Joachim Gerlach
bool
bool
data_out data data_ok
_out
_ready
66
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
input pgm-file start
data
data
SystemC 1.0
Design
Example A
DCT
data
data
ready ready
ready
IRLEH
data
ready
Quant
data
Design
Activities
data
ready
ready
data
ready
IZigZag
ready
data
data
ready
ready
data
ZigZag
data
data
ready
data
ready
ready
IQuant
Decoder
data
ready
RLEH
SystemC 1.1
Joachim
Gerlach
data
ready
data
ready
data
Encoder
Design
Example B
Tool
Support
Reader
data
ready ready
data data
ready
ready
data
data
ready
ready
IDCT
ready
Writer
data
ready
data data
ready
ready
output pgm-file
Joachim Gerlach
67
SYSTEMC
TM
Design Activities
University of
Tübingen
Design Activities
Department of
Computer
Engineering
q
Modeling
m Module for “zigzag”computation
q
Simulation
m Generation and run of an executable specification
q
Debugging
m Techniques for checking the functionality of the system
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
69
University of
Tübingen
Modeling
Department of
Computer
Engineering
void zigzag::do_zigzag() {
zigzag.h
#include <systemc.h>
#include "global.h"
Background
& Basics
Design
Example A
ready.write(true);
data_out_ready.write(false);
wait_until(start.delayed()==true);
ready.write(false);
sc_in_clk
clk;
sc_in<Coeff_8x8>
sc_in<bool>
sc_in<bool>
data_in;
start;
data_ok;
fuv = data_in.read();
// zigzag
u = 0; v = 0;
dir = 1; // dir == 1: upwards, dir == 0: downwards
sc_out<Matrix_64x12> data_out;
sc_out<bool>
ready;
sc_out<bool>
data_out_ready;
Design
Example B
zigzag.cc
fuv;
result;
u, v, a, dir;
while(true) {
SC_MODULE(zigzag) {
SystemC 1.0
Design
Activities
Coeff_8x8
Matrix_64x12
unsigned char
for ( a = 0; a < 64; a++ ) {
result.put ( a, (WORD) (fuv.get (v,u) ) );
void do_zigzag();
if ( v == 0 )
if ( dir ) { u++; dir = 0; }
else
{ u--; v++; }
else if ( v == 7 )
if ( !dir ) { u++; dir = 1; }
else
{ u++; v--; }
else if ( u == 0 )
if ( !dir ) { v++; dir = 1; }
else
{ u++; v--; }
else if ( u == 7 )
if ( dir ) { v++; dir = 0; }
else
{ u--; v++; }
else
if ( dir ) { u++; v--; }
else
{ u--; v++; }
SC_CTOR(zigzag) {
SC_CTHREAD(do_zigzag,clk.pos());
}
};
Tool
Support
SystemC 1.1
}
Joachim
Gerlach
data_out.write(result);
data_out_ready.write(true);
wait_until(data_ok.delayed()==true);
}
}
Joachim Gerlach
70
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Simulation
q
Generation of an executable specification
systemc.h
reader.h
......
writer.h
reader.cc
......
writer.cc
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
jpeg.cc
library
Tool
Support
g++
SystemC 1.1
Joachim
Gerlach
run
executable = simulator
Joachim Gerlach
71
University of
Tübingen
Department of
Computer
Engineering
Simulation
q
Simulation control
m
Simulation start:
sc_start() / sc_start(n) from the top-level function sc_main()
m
Simulation stop:
sc_stop() from within any process
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
q
Advanced simulation control:
“self-made” clock by sc_initialize() and sc_cycle(n)
sc_clock my_clock (“CLK”, 20, 0.5 );
true
false
0
sc_start(200);
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
10
20
30
40
sc_initialize();
for (int i=0; i<=200; i++) {
clock = 1;
sc_cycle(10);
clock = 0;
sc_cycle(10);
}
72
University of
Tübingen
Department of
Computer
Engineering
Simulation
q
Running the executable specification
Background
& Basics
> ./run motorbike.pgm motorbike2.pgm
SystemC 1.0
SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
SystemC: simulation stopped by user.
>
>
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
73
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Simulation
q
Results of an executable run
input picture
(motorbike.pgm)
compression
decompression
stream
output picture
(motorbike2.pgm)
SystemC 1.0
Reader
Design
Example A
Design
Example B
JPEG
Decoder
JPEG
Encoder
Writer
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
74
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Debugging
q
Observation of simulation results
q
Adding (C/C++) assertions/debug outputs to the source code
q
Using SystemC debugging features
q
Using standard debugging tools (gdb, Purify,...)
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
75
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Debugging
q
Adding debug outputs to the source code
zigzag.cc
.....
SystemC 1.0
static int no_of_zigzags = 0;
Design
Example A
while(true) {
.....
Design
Example B
// zigzag computation
.....
no_of_zigzags++;
cout << „number of zigzags:“ << no_of_zigzags << endl;
Design
Activities
Tool
Support
.....
}
}
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
76
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Debugging
q
ALL RIGHTS RESERVED
number of zigzags: 1
.....
>
>
Joachim Gerlach
77
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Debugging
q
Using SystemC debugging features: sc_time_stamp()
zigzag.cc
.....
SystemC 1.0
static int no_of_zigzags = 0;
Design
Example A
while(true) {
.....
Design
Example B
// zigzag computation
.....
no_of_zigzags++;
cout << „cycle: “ << sc_time_stamp();
cout << „ - number of zigzags:“ << no_of_zigzags << endl;
Design
Activities
Tool
Support
SystemC 1.1
.....
}
}
Joachim
Gerlach
Joachim Gerlach
78
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Debugging
q
ALL RIGHTS RESERVED
cycle: 5 - number of zigzags: 1
.....
>
>
Joachim Gerlach
79
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
Debugging
q
Using SystemC debugging features: waveform tracing
int sc_main( int argc, char *argv[] )
jpeg.cc
{
SystemC 1.0
.....
Design
Example A
// waveform tracing
if ( (argc == 4) && (strcmp(argv[3],"w") == 0) ) {
sc_trace_file* tf = sc_create_wif_trace_file( „wave“ );
Design
Example B
sc_trace( tf, clk.signal(), „clock“ );
sc_trace( tf, encoder_is_ready, „encoder_is_ready“ );
sc_trace( tf, orig_data_ready, „start_dct“ );
sc_trace( tf, e.data_out_ready_1, „start_quant“ );
sc_trace( tf, e.data_out_ready_2, „start_zigzag“ );
sc_trace( tf, e.data_out_ready_3, „start_rleh“ );
sc_trace( tf, decoder_is_ready, „decoder_is_ready“ );
sc_trace( tf, comp_data_ready, „start_idct“ );
sc_trace( tf, d.data_out_ready_1, „start_iquant“ );
sc_trace( tf, d.data_out_ready_2, „start_izigzag“ );
sc_trace( tf, d.data_out_ready_3, „start_irleh“ );
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
}
.....
}
Joachim Gerlach
80
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
Debugging
q
Running the executable specification (with “w” parameter)
> ./run motorbike.pgm motorbike2.pgm w
ALL RIGHTS RESERVED
WARNING: Default time step (1 s) is used for WIF tracing.
>
> viewer wave.awif &
>
>
SystemC 1.1
Joachim
Gerlach
Joachim Gerlach
81
SYSTEMC
TM
Tool Support
University of
Tübingen
Department of
Computer
Engineering
Synopsys SystemC Compiler
q
SystemC for system modeling
Background
& Basics
SystemC
SystemC 1.0
Modeling
Constructs
Design
Example A
C/C++ Testbench
Design
Example B
Design
Activities
C/C++ Software
C/C++ Hardware/System
System
Tool
Support
Standard
C++ Compiler
SystemC 1.1
Wolfgang
Rosenstiel
Executable = Simulator != Debugger
Joachim Gerlach
83
University of
Tübingen
Department of
Computer
Engineering
q
SystemC Compiler C++ synthesis in the HW flow
Background
& Basics
Model using SystemC
SystemC 1.0
Design
Example A
Design
Example B
SystemCTM Compiler
Tool
Support
db form
db form
Design
Activities
Behavioral synthesis
db or HDL
format
(This flow is not supported currently)
RTL synthesis
SystemC 1.1
Gate level netlist
Wolfgang
Rosenstiel
Joachim Gerlach
84
University of
Tübingen
Department of
Computer
Engineering
q
Refinement for implementation
System Specification
Background
& Basics
SystemC 1.0
Refine Structure
• Partition into blocks that will be
independently synthesized/refined
• Refine interfaces for communication
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Refine Control
• Specify I/O protocol
•Specify clock domains
• Specify latency, throughput
• Specify FSM & datapath for RTL
Refine Data
• Use bit-true types
• Select appropriate
bit widths
Wolfgang
Rosenstiel
System Implementation
Joachim Gerlach
85
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
q
Behavioral Level Flow
yes
Behavioral
Code
Code?
SystemC 1.0
Design
Example A
SystemC Compiler
Remove
Design
no
Timed DB File
Latency/Pipeline
Constraints
Schedule
Design
Example B
Initial Constraints
Design
Activities
Check Design
Tool
Support
Time/Area Estimates
no
OK?
yes
SystemC View
Reports
Cycle-Accurate
HDL
Cycle-Accurate DB
HDL
Co-Simulation
Compile
SystemC 1.1
Wolfgang
Rosenstiel
Timed DB File
Timed DB Generation
Joachim Gerlach
Gate Level Netlist
High-Level Synthesis
86
University of
Tübingen
Department of
Computer
Engineering
q
Hardware Implementation Flow
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Refinement
Functional
Design
IQ Block
(communication,
timing, memories)
Refinement
Architectural
Design
SystemC Compiler
Behavioral Flow
(resources, scheduling,
allocation, FSM design)
Tool
Support
Controller
RT Level
Design
SystemC 1.1
SystemC Compiler
RTL Flow
Wolfgang
Rosenstiel
Gate Level
Design
Joachim Gerlach
87
University of
Tübingen
Department of
Computer
Engineering
Background
& Basics
q
Benefits
m
Rapid time to market
– fast refinement from functional model behavioral model
SystemC 1.0
– accommodating late spec changes
Design
Example A
Design
Example B
Design
Activities
Tool
Support
m
Graphical analysis of design
m
High quality of results
– tight integration into Synopsys synthesis flow
– flexibility for datapath components
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
88
University of
Tübingen
Department of
Computer
Engineering
CoWare N2C
q
Gaps in System Design
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
89
University of
Tübingen
Department of
Computer
Engineering
CoWare N2C
q
System-Level Design with CoWare N2C
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
90
University of
Tübingen
Department of
Computer
Engineering
CoWare N2C
q
Background
& Basics
SystemC 1.0
N2C Workbench
m
Hierarchical design browser (architecture, functionality)
m
Source code editor (context sensitive)
m
Project manager (partition management)
Design
Example A
Design
Example B
q
CoWare Support
m
CoWare N2C supports a top-down design flow for HW/SW
co-design from UTF to RTL
m
Co-simulation of different languages
m
Fast design exploration and HW/SW partitioning
m
Allows for efficient IP reuse and delivery
m
Provides synthesis of communication
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Joachim Gerlach
91
University of
Tübingen
Department of
Computer
Engineering
System Compiler (C Level Design)
q
System Compiler
m
Background
& Basics
m
SystemC 1.0
Design
Example A
Design
Example B
m
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
q
supports full ANSI
C and C++
native
C/C++
Class-based C++
(System C++)
provides complex data
structures, static pointer
analysis, abstraction,
hierarchy
bit-accurate (fixed and floating)
simulation libraries
output is RT level HDL
(VHDL or Verilog)
native C/C++ CSim/System C++
simulation
simulation
CSim
m
executable specification
m
discrete event simulation
m
abstraction: temporal time,
data values, functionality
Joachim Gerlach
System Compiler
C/C++ synthesis
RTL
HDL
92
University of
Tübingen
Department of
Computer
Engineering
A|RT Builder (Frontier Design)
system specification
embedded software
datapath resources
(arithmetic, memory)
legacy HDL
Background
& Basics
ANSI
C
SystemC 1.0
Design
Example A
edit/compile
edit/compile
Design
Example B
HWhw
HW
Resource
resource
Resource
Library
Library
library
vendor HDL
create
createarchitecture
architecture
map
maptotoarchitecture
architecture
Design
Activities
source code
tuning
Tool
Support
schedule
scheduleoperations
operations
architecture
optimization
performance analysis
SystemC 1.1
build
buildRTL
RTLcode
code
logic synthesis
Wolfgang
Rosenstiel
FPGA
Joachim Gerlach
ASIC
93
SYSTEMC
TM
SystemC 1.1
Outlook
University of
Tübingen
SystemC 1.1 Design Flow
Department of
Computer
Engineering
Matlab
Background
& Basics
C++
SDL
functional
decomposition
SystemC
1.1
SystemC 1.0
UTF
Design
Example A
design exploration
performance analysis
hw/sw partitioning
Design
Example B
......
Esterel
untimed
functional
assign
„execution time“
TF
timed
functional
hw/sw partitioning
refine communication
Design
Activities
Tool
Support
task
partitioning
Abstr.
RTOS
bus cycle
accurate
BCA
refine
behavior
SystemC 1.1
target
RTOS/core
Joachim
Gerlach
RTOS
software
Joachim Gerlach
RTL
cycle
accurate
hardware
95
University of
Tübingen
Department of
Computer
Engineering
Design Levels in SystemC 1.1
q
UTF: UnTimed Functional
m
Background
& Basics
m
m
SystemC 1.0
m
Functional decomposition of a system
Architecture, timing, inter-block communication is abstracted
Maximally sequential form by RPC (Remote Procedure Call)
RPC: abstract (master/slave-)ports, multi-point link objects
Design
Example A
Design
Example B
Design
Activities
q
TF: Timed Functional
m
q
Tool
Support
RPC also, but processes may be assigned a run time
BCA: Bus Cycle Accurate
m
Abstract ports refined to bus ports with data, adress, control
terminals and communication protocols
SystemC 1.1
q
Joachim
Gerlach
CA: Cycle Accurate
m
SystemC 1.0 level
Joachim Gerlach
96
SYSTEMC
TM
Questions
& Answers

System-on-Chip Design with SystemC

Transcription

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