docPrometeusz Jasinski
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Prometeusz Jasinski
DAQ/DCS/Soda for the Luminosity Detector Prometeusz Jasinski on behalf of the PANDA PALUMA Group 31.03.2014 DAQ-workshop Boppard 31.03.2014 Prometeusz Jasinski 1 PANDA – Experiment at FAIR 31.03.2014 Prometeusz Jasinski Elastic Proton Anti-Proton scattering pp pp c.m.s. p t 31.03.2014 Prometeusz Jasinski p 3 Retractable Detector Halves 31.03.2014 Prometeusz Jasinski 4 Retractable Detector Halves 31.03.2014 Prometeusz Jasinski 5 Smart diodes 31.03.2014 Prometeusz Jasinski 7 Preliminary Layout of HV-MAPS 31.03.2014 Prometeusz Jasinski 8 DAQ HVMAPS detector (vacuum) @ detector m su od pp ule ly bo ar d mo d ule sid e plane side 31.03.2014 Prometeusz Jasinski 10 DAQ ule sid e plane side x5 @ detector m su od pp ule ly bo ar d mo d HVMAPS detector (vacuum) LVDS driver 4x in/out 31.03.2014 Prometeusz Jasinski 11 DAQ ule sid e plane side @ detector m su od pp ule ly bo ar d mo d HVMAPS detector (vacuum) x5 LVDS driver LVDS driver LVDS driver 4x in/out 4x in/out 4x in/out ... 31.03.2014 x13 Prometeusz Jasinski 12 DAQ ule sid e plane side mo d HVMAPS detector (vacuum) Xilinx Kintex/Artix-7 FPGA board m su od pp ule ly bo ar d x50 @ detector x5 LVDS driver LVDS driver LVDS driver 4x in/out 4x in/out 4x in/out ... x13 Current solution: TRB v3 boards with max 24 LVDS links on all SERDIS inputs 31.03.2014 Prometeusz Jasinski 13 DAQ ule sid e plane side mo d HVMAPS detector (vacuum) x50 Xilinx Kintex/Artix-7 FPGA board ... x16 m su od pp ule ly bo ar d x5 @ detector LVDS driver LVDS driver LVDS driver 4x in/out 4x in/out 4x in/out ... x13 ... 31.03.2014 Prometeusz Jasinski x16 14 DAQ ule sid e plane side mo d HVMAPS detector (vacuum) x50 PANDA data concentrator LVDS driver LVDS driver LVDS driver 4x in/out 4x in/out 4x in/out ... x13 ... 31.03.2014 Xilinx Kintex/Artix-7 FPGA board ... x16 m su od pp ule ly bo ar d x5 @ detector Prometeusz Jasinski x16 “event” builder 15 Clock distribution sheme sid e plane side mo d ule HVMAPS detector (vacuum) @ detector 40MHz CLK m su od pp ule ly bo ar d Xilinx Kintex/Artix-7 FPGA board x5 CLK driver 31.03.2014 Prometeusz Jasinski 16 Clock distribution sheme sid e plane side mo d ule HVMAPS detector (vacuum) @ detector 40MHz CLK reset fan-out m su od pp ule ly bo ar d Xilinx Kintex/Artix-7 FPGA board x5 CLK driver 31.03.2014 Prometeusz Jasinski 17 Clock distribution sheme sid e plane side mo d ule HVMAPS detector (vacuum) @ detector 40MHz CLK Xilinx Kintex/Artix-7 FPGA board ... x16 m su od pp ule ly bo ar d reset fan-out x5 CLK driver ... 31.03.2014 Prometeusz Jasinski x16 18 Clock distribution sheme sid e plane side mo d ule HVMAPS detector (vacuum) @ detector 40MHz CLK Xilinx Kintex/Artix-7 FPGA board ... x16 m su od pp ule ly bo ar d reset fan-out x5 PANDA data concentrator CLK driver ... 31.03.2014 Prometeusz Jasinski x16 SODA 19 DCS via SPI mo d u le sid e plane side HVMAPS detector (vacuum) CAN x1 @ detector SOC + FPGA board data x5 cs x5 x5 x4 m su od pp ule ly bo ar d x16 slow control µC 31.03.2014 Prometeusz Jasinski 20 DCS via SPI mo d u le sid e plane side HVMAPS detector (vacuum) CAN x1 @ detector SOC + FPGA board data x5 cs x5 x5 x4 m su od pp ule ly bo ar d x16 slow control µC ... x16 Slow Control via SODA might provide the option to migrate DCS on the DAQ FPGA boards 31.03.2014 Prometeusz Jasinski 21 Thank you 31.03.2014 Prometeusz Jasinski 22 Geometrical Acceptance Acceptance at 1.5 GeV/c beam momentum 31.03.2014 Prometeusz Jasinski 23 Material Budget of one Plane one side of a module flex cable Al Al resin < 15 µm polymide 10 µm resin < 15 µm Al layer 14 µm Poly-p-xylylen 5 µm resin < 15 µm HV-MAPS 50 µm resin < 15 µm CVD-diamond 200 µm 31.03.2014 Prometeusz Jasinski X/X0 (2 sides) = 0.37% ( eq. 350 µm thick silicon ) 24
