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The eGaN® FET Journey Continues Alex Lidow and Michael de Rooij Efficient Power Conversion Corporation EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Agenda • What happens when eGaN® FETs are paralleled? • What are the best solutions? • Introducing the Parallel Impact Figure (PIF) • Layout Do’s and Don’ts • Summary EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Half-Bridge topologies Q1a Q1b Q1n Gate Driver Q2a Q2b ... Q2n Gate Driver EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Switching Dynamics LG1 LG2 RG LCS1 LCS2 + VGateDrive EPC - The Leader in eGaN® FETs APEC 2012 Icirc www.epc-co.com Switching Dynamics – Turn On FET Turn-On LG1 LG2 RG Vdi/dt LCS1 LCS2 Vdi/dt + VGateDrive IDS VGS di/dt VTH EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Switching Dynamics – Turn Off FET Turn-off Idv/dt Idv/dt LG1 LG2 RG LCS1 LCS2 + VGateDrive VDS VGS dv/dt VTH EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com ° ° ° ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° ° ° ZZZZ ZZZZ ZZZZ ZZZZ ° YYYY YYYY YYYY YYYY ° XXXX XXXX XXXX XXXX XXXX XXXX YYYY ZZZZ ° XXXX YYYY ZZZZ ° XXXX YYYY ZZZZ ° XXXX ZZZZ YYYY ZZZZ ZZZZ YYYY XXXX XXXX YYYY ZZZZ ° XXXX ° XXXX ZZZZ YYYY XXXX ° XXXX ZZZZ YYYY ° YYYY ° ZZZZ ° YYYY ° YYYY XXXX YYYY ZZZZ ° XXXX ZZZZ YYYY ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX ° XXXX XXXX YYYY YYYY ° YYYY YYYY XXXX YYYY ° YYYY ZZZZ ° XXXX ZZZZ ° YYYY ° ° ZZZZ ° ° ° ZZZZ ZZZZ ° ° ° ZZZZ ZZZZ ° ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ XXXX XXXX YYYY YYYY ZZZZ ZZZZ ZZZZ www.epc-co.com APEC 2012 EPC - The Leader in eGaN® FETs E D C B A XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX Half Bridge Layout Evaluations Single Component Sided Double Component Sided Introducing the PIF • Based on dv/dt and di/dt immunity • Normalizes evaluations relative to a single FET • Can be used to predict switching performance EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com ZZZZ ° ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° ° ZZZZ ZZZZ YYYY YYYY XXXX XXXX XXXX YYYY ZZZZ ° XXXX ° XXXX ZZZZ YYYY YYYY ° XXXX XXXX YYYY YYYY ° ZZZZ ZZZZ ° YYYY ° ZZZZ ° XXXX XXXX YYYY ZZZZ ° ZZZZ YYYY ° XXXX XXXX ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° ° ZZZZ ZZZZ YYYY YYYY XXXX XXXX XXXX YYYY ZZZZ ° ZZZZ ° YYYY XXXX ZZZZ ° YYYY XXXX XXXX YYYY ZZZZ ° XXXX XXXX XXXX YYYY YYYY ZZZZ ZZZZ YYYY ° XXXX ZZZZ ° YYYY ° ° ° ZZZZ ° ° XXXX XXXX YYYY YYYY ° ZZZZ ZZZZ ° ° XXXX YYYY ZZZZ ° XXXX ZZZZ YYYY ° ° YYYY ° ZZZZ ° ZZZZ ° YYYY XXXX XXXX YYYY YYYY ZZZZ ZZZZ XXXX XXXX YYYY YYYY ZZZZ ZZZZ XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° www.epc-co.com APEC 2012 EPC - The Leader in eGaN® FETs E D C B A ° XXXX PIF for Half Bridge Layouts 2 Devices in Parallel 4 Devices in Parallel ° ° ° ZZZZ ZZZZ ZZZZ ZZZZ ° YYYY XXXX YYYY XXXX YYYY YYYY XXXX YYYY ZZZZ YYYY XXXX YYYY ZZZZ ° XXXX YYYY ZZZZ ° XXXX ZZZZ ° XXXX ° EPC - The Leader in eGaN® FETs XXXX Best Layout Configuration APEC 2012 www.epc-co.com +V G Half Bridge Layout To Minimize And Balance Source Inductance D S D S D S D S D B G D S D S D S D S D B Into The Drains Layout Recommendation Switch Node G D S D S D S D S D B G D S D S D S D S D B -V EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Layout Recommendation G Half Bridge Layout To Minimize And Balance Source Inductance D S D S D S D S D B G D S D S D S D S D B From Sources To The Drains +V Switch Node G D S D S D S D S D B G D S D S D S D S D B -V EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Layout Recommendation +V G B G D S D S D S D S D B Switch Node G D S D S D S D S D B G D S D S D S D S D B From Sources Half Bridge Layout To Minimize And Balance Source Inductance D S D S D S D S D -V EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Layout Recommendation +V Use Lots Of Vias Bridge To Stitch Half The Contacts Layout To To Inner Planes Minimize And Balance Source Inductance G D S D S D S D S D B G D S D S D S D S D B Switch Node G D S D S D S D S D B G D S D S D S D S D B -V EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com Layout Recommendation: Gates Gate Return Planes Connect To At Least First Set Of Source Vias +V G D S D S D S D S D B High Gate G D S D S D S D S D High Gate Return B Switch Node G D S D S D S D S D Low Gate B G D S D S D S D S D Low Gate Return EPC - The Leader in eGaN® FETs B APEC 2012 -V www.epc-co.com Layout Detail eGaN FET Gate Vias on both sides of the FET. Current exits pad in two directions EPC - The Leader in eGaN® FETs eGaN FET APEC 2012 www.epc-co.com XXXX ZZZZ YYYY XXXX ZZZZ YYYY XXXX ZZZZ ZZZZ YYYY XXXX ZZZZ ° YYYY ZZZZ YYYY XXXX ZZZZ YYYY XXXX ZZZZ ° YYYY ZZZZ YYYY XXXX YYYY XXXX ZZZZ YYYY XXXX XXXX ZZZZ ° ZZZZ YYYY XXXX XXXX YYYY ° XXXX YYYY XXXX ZZZZ ° YYYY ° ° XXXX ZZZZ XXXX XXXX ZZZZ YYYY ° ZZZZ YYYY XXXX XXXX ° YYYY ° ° XXXX ZZZZ ° YYYY ° YYYY ° XXXX YYYY YYYY ° ° ZZZZ ZZZZ XXXX ZZZZ YYYY ZZZZ ZZZZ ° ° ° ZZZZ ° YYYY ° ° ° XXXX ZZZZ YYYY ° www.epc-co.com APEC 2012 EPC - The Leader in eGaN® FETs B4 B3 B2long B2tall B1 XXXX PIF for Best Layout Parallel eGaN FET Buck Converter + XXXX YYYY + PWM Control YYYY ZZZZ Vout ° ° ZZZZ Vin ZZZZ ° XXXX YYYY XXXX - EPC - The Leader in eGaN® FETs - APEC 2012 www.epc-co.com Parallel eGaN® FET Buck Converter Efficiency at 1 MHz 12 VIN – 1.2 VOUT EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com 19 ° ° ° ° ° ° ° ° ° ° ° ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX YYYY XXXX ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ XXXX YYYY ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ ° XXXX YYYY ZZZZ ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ 8 6 4 20 www.epc-co.com APEC 2012 EPC - The Leader in eGaN® FETs ° YYYY ZZZZ ° ° ZZZZ ° ° ° XXXX XXXX YYYY YYYY ZZZZ ZZZZ Half Bridge Layout Best Practice Double Component Sided ° ° ZZZZ ZZZZ YYYY YYYY ZZZZ ZZZZ ° XXXX XXXX ° XXXX XXXX YYYY YYYY ° YYYY YYYY ° ZZZZ ZZZZ ° ZZZZ ZZZZ ° XXXX XXXX ° ZZZZ ° YYYY YYYY ZZZZ ° XXXX XXXX YYYY ZZZZ ° XXXX ZZZZ ° YYYY XXXX YYYY YYYY ZZZZ XXXX XXXX ZZZZ ° XXXX XXXX YYYY ZZZZ ° XXXX YYYY ZZZZ ° XXXX YYYY YYYY XXXX ZZZZ YYYY XXXX ZZZZ YYYY XXXX YYYY XXXX XXXX ZZZZ ° YYYY ° ZZZZ ° YYYY ° XXXX ZZZZ YYYY XXXX ZZZZ YYYY YYYY ZZZZ ° ZZZZ ° 21 www.epc-co.com APEC 2012 EPC - The Leader in eGaN® FETs ° ° XXXX Layout Don’ts Single Component Sided Double Component Sided Summary • eGaN FETs can be paralleled • Two devices can be paralleled without loss of performance • The PIF is a useful tool for comparing layouts and predicting switching performance EPC - The Leader in eGaN® FETs APEC 2012 www.epc-co.com The end of the road for silicon….. is the beginning of the eGaN FET journey! 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