PNX0103 - Forum MP3Store

Transcription

A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
FT
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
R
A
F
FT
FT
A
A
R
R
D
D
Preliminary Datasheet
D
R
FT
FT
A
A
R
R
D
D
D
Rev. 01.14 — 22 January 2007
R
R
R
R
R
NexperiaTM PNX0103 Personal Audio IC
D
D
D
D
D
PNX0103
D
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
1. General description
R
A
FOR GUIDANCE ONLY.
THE CONTENTS OF THIS DATASHEET ARE SUBJECT TO CHANGE AND THEIR
ACCURACY SHOULD NOT BE RELIED UPON.
TO ENSURE A DESIGN WITH THE PNX0103 IS BASED ON THE LATEST
INFORMATION, PLEASE CAREFULLY CHECK ALL SPECIFICATIONS /
FUNCTIONALITY PRIOR TO USE ONCE A VERSION OF THIS DATASHEET HAS
BEEN ISSUED THAT DOES NOT CONTAIN THIS NOTICE.
The Nexperia™ PNX0103 is a highly integrated System on Chip (SoC) for compressed
audio and simple multimedia applications that are using NAND flash as storage media.
The high level of integration, low power consumption and high processor performances
make the PNX0103 very suitable for portable hand held devices with a small form factor
and with a long battery life-time.
The PNX0103 is based on an ARM 926EJ-S CPU core with separate data and instruction
caches of 16 kBytes each. It has a dedicated NAND flash controller that allows for
effective and secure execution of program code as well as efficient writing and reading of
multimedia content for various types of NAND flash.
ARM926 EJ-S
MCI
SDMA
USB 2.0
HS OTG
2 Cache 16 Kbytes
S
M
M
M
M
AHB Multilayer Bus
S
NAND-flash
Controller
S
S
S
S
S
S
MPMC
VPB bridge 4
sync
Legend:
M = Master port
S = Slave port
VPB bridge 3
async
SAO1
SAI1
SAO2
SAI2
VPB bridge 2
async
UART
LCD int
SPI
S
S
ISRAM
2 x 256 Kbytes
VPB bridge 1
async
VPB bridge 0
async
I2C MS0
Timer 0
Timer 1
Timer 2
Timer 3
PWM
I2C MS1
1. IPINT (4 pins) and MCI (10 pins) multiplexed with DAO and GPIO
Fig 1. Block Diagram
S
IROM
64 Kbytes
S
S
Interrupt
Controller
Watchdog
Syscreg
CGU
IOCONF
10 bitADC
Event router
RNG
OTP
S
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
PNX0103 Multimedia IC
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
R
A
FT
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
2.1 General Features
D
R
FT
FT
A
A
R
R
D
D
D
2. Features
FT
FT
FT
FT
PNX0103 Personal Audio IC
D
D
Enables one chip solution for portable audio players using flash memory.
Requires very low power thereby maximizing battery life cycle.
Supports SLC and MLC NAND flash memory devices ranging in size between 128
MBytes - 16 GBytes.
Supports secure code execution from NAND flash.
Has built-in support for the power by a Lithium Ion cell and has an integrated charger.
Provides sufficient processing power for audio post processing features and audio
enhancement algorithms.
Supports FM radio input including low power audio bypass mode.
Is available in small footprint package TFBGA208 of 12 x 12 sqmm with 0.65 mm
pitch.
R
A
© NXP B.V. 2007. All rights reserved.
Rev. 01.14 — 22 January 2007
2 of 50
A
R
PNX0103
D
ARM926 EJ-S processor core with 16 kByte data cache and 16 kByte instruction
cache.
Embedded SRAM, 512 kBytes. Implemented as two separate slaves on the AHB bus
of 256 kBytes each.
Embedded ROM memory for storing the boot code, 64 kByte.
Integrated NAND flash controller with 5-symbol Error Correction (ECC) and AES
decryption support. This controller supports up to four NAND flash devices which can
be any combination of SLC type NAND flash and MLC type NAND flash up to a
capacity of 16 GBytes.
Supports up to 64 MByte of external SDRAM memory
Integrated USB 2.0 High Speed OTG interface.
Intelligent Configuration Power Management.
Embedded high efficiency Power Supply Unit powered from a Li-Ion battery.
Supports power optimization by optimizing supply voltages.
Embedded Li-Ion charger.
Embedded DMA controller with burst transfer support.
Digital interfaces:
Integrated 4/8/16-bit 6800/8080 compatible LCD interface with DMA support.
General-purpose IO pins (nearly all digital pins can be configured as GPIO pins).
Integrated Master/Slave SPI interface with DMA support.
Integrated IIS input (configurable for master/slave option) and output interfaces
(master options).
Integrated fast UART with DMA support, IrDA and hardware flow control.
Integrated Master/Slave I2C interface.
Pulse Code Modulation (PCM) & ISDN Oriented Modular (IOM) Interface (IPINT)
Memory Card Interface (MCI)
Analog Interfaces:
Built in 10-bit ADC for level measurement & control (3 inputs available on external
pins and 1 internal input to measure the battery level).
FT
2.2 Hardware Features
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
FT
FT
A
A
R
R
D
D
D
PNX0103
Rev. 01.14 — 22 January 2007
3 of 50
A
This section lists the possible software features that the PNX0103 is capable of
performing. Note that this does not imply that either the software itself or the required
licenses are included with the PNX0103.
MP3 decoding1, 2 => Support for MPEG 1 layer 3 and MPEG 2 layer 2.5 and layer 3
audio decoding.
WMA decoding1:
WMA7.
WMA9.
Low, mid and high bit rate profiles.
Unprotected files.
PD DRM protected files.
Windows DRM10 protected files.
AAC MPEG4 decoding (low complexity profile) and e-AAC+ decoding1.
ACELP decoding1.
Decoding of sound files protected by Audible’s DRM technology1.
Ogg Vorbis decoding, quality level up to Q101.
Stereo recording using MP3 encoding up to a sample rate of 48 KHz1.
Stereo recording using WMA8 encoding up to a sample rate of 48 KHz1.
Stereo recording using ADPCM up to a sample rate of 48 KHz1.
Decoding of JPEG images in QVGA resolution (in parallel to an audio codec)1.
Decoding of MJPEG1.
Decoding of MPEG4 streams of at least QCIF+ resolution1.
Decoding of WMV9 streams of at least QCIF+ resolution1.
Frame rate 25 fps.
USB Mass Storage Class.
USB Media Transfer Protocol.
USB Device Firmware Upgrade.
USB Picture Transfer Protocol.
D
2.3 Possible Software Features
FT

A

R

R
Integrated stereo ADC with programmable amplifier (microphone, line input and
tuner input).
Integrated Class AB headphone amplifier.
Integrated stereo DAC with Class AB headphone amplifier, for high quality audio
with increased driving capabilities and for use in tuner applications.
Four integrated general-purpose timers.
Supports secure code execution and advanced DRM schemes:
Integrated ultra low power Real Time Clock with optional backup capacitor.
Random Number Generator.
Secure one time programmable memory for storing a unique ID (128-bit, factory
pre programmed) and a cryptographic key (128-bit, customer programmed).
Integrated watchdog timer.
Low power tuner mode with direct connection between tuner input and Class AB
headphone amplifier with analog volume control.
JTAG interface with boundary scan and ARM debug access.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
Multimedia features that enhance the audio experience.
Intelligent power management software.
Audio post-processing features like bass, treble, volume control as well as equalizer
function.
Sound enhancement/post porocessing software, like equalizer, bass boost and 3D
sound.
Graphical Spectrum Analyzer.
Remark: (1) All encoder/decoders (audio, video, JPEG etc) mentioned here do require
appropriate licenses.
Remark: (2) Microsoft disclaimer.
D
FT
FT
A
A
R
R
D
D
D
R
A
Cost effective low power portable audio player (no SDRAM) using NAND flash storage
Portable audio player with multimedia features (with SDRAM) using NAND flash
storage.
4. Product Summary
4.1 ARM 926EJ-S
The processor embedded in the chip is the ARM926EJ-S. It is a member of the ARM9
family of the general-purpose microprocessors. The ARM926EJ-S is meant for
multi-tasking applications where full memory management, high performance and low
power are important.
PNX0103
Rev. 01.14 — 22 January 2007
4 of 50
A
3. Applications
R
THIS PRODUCT CONTAINS CERTAIN TECHNOLOGY PROTECTED BY THE
INTELLECTUAL PROPERTY RIGHTS OF MICROSOFT. THE MICROSOFT
TECHNOLOGY CANNOT BE USED IN ANY PRODUCT WITHOUT A LICENSE
FROM MICROSOFT.
D
Microsoft has issued Compliance and Robustness Rules for Windows Media DRM
Implementations (hereinafter referred to as the "Compliance and Robustness Rules"),
which are obtainable from Microsoft's public web site. They include robustness and
other device requirements. Microsoft may specify additional rights, restrictions or
parameters at any time, which may impact the use of the PNX0103 or of devices
containing the PNX0103 and may require upgrading thereof. Upgrading may be
subject to computer power and memory bandwidth. Microsoft's Compliance and
Robustness Rules must be taken into account and future amendments thereof must
be anticipated in the design of devices containing the PNX0103.
FT
The PNX0103 performs multimedia decode/encode functions including WMA9, WMV9
and WM-DRM. Decoding of WM-DRM is dependent upon continued availability of
applicable Microsoft's DRM Client Certificates. Microsoft may revoke DRM Client
Certificates in case of security breaches that cannot reasonably be remedied by
Microsoft or other material security problems. As a result thereof the device containing
the PNX0103 may no longer be able to perform some or all of its WM DRM decoding
functionality.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
D
FT
FT
A
decode, execute, memory and write stages. The processor supports both the 32-bit
ARM and 16-bit Thumb instruction sets, which allows a trade off between high
performance and high code density. The ARM926EJ-S also executes an extended
ARMv5TE instruction set which includes support for Java byte code execution.
A
R
R
D
• ARM926EJ-S processor core which uses a five-stage pipeline consisting of fetch,
FT
A
A
R
R
D
D
D
This module has the following features:
FT
FT
FT
FT
D
D
R
A
• Supports dynamic clock gating for power reduction.
• The processor core clock can be set equal to the AHB bus clock or to an integer
number times the AHB bus clock. The processor can be switched dynamically
between these settings.
• ARM stall support.
4.2 JTAG
The Joint Test Action Group (JTAG) interface allows the incorporation of the PNX0103 in a
JTAG scan chain.
• ARM926 debug access
• Boundary scan
• The ARM926 debug access can be permanently disabled through a bit in the one time
programmable memory (OTP) block.
4.3 NAND flash Controller
The NAND flash Controller is used as a dedicated interface to NAND flash devices.
Figure 2 shows a block diagram of the NAND flash controller module. The heart of the
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An error
correction encoder/decoder (ECC enc/dec) module allows for hardware error correction
for support of Multi-Level Cell (MLC) NAND flash devices. The AES decryption block
allows for hardware supported secure (encrypted) code execution.
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects errors.and/or the AES decryption module can
decrypt data.
PNX0103
Rev. 01.14 — 22 January 2007
5 of 50
A
to assist in both hardware and software debugging.
R
• Little Endian is supported.
• The ARM926EJ-S processor supports the ARM debug architecture and includes logic
D
length. The caches are organized using Harvard architecture.
FT
• Contains an AMBA BIU for both data accesses and instruction fetches.
• Memory Management Unit (MMU).
• 16 kByte instruction and 16 kByte data separate cache memories with an 8 word line
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
AHB
FT
FT
FT
FT
D
D
R
A
FT
Buffer
D
R
A
Controller
AES
dec
dma/irq
ECC
enc/dec
NAND i/f
Fig 2. NAND flash Controller
• Dedicated NAND flash interface with hardware controlled read and write accesses.
• Wear leveling support with 516 byte mode.
• Software controlled command and address transfers to support wide range of flash
devices.
•
•
•
•
•
•
•
Software control mode where the ARM is directly master of the flash device.
Support for 8 bit & 16 bit flash devices.
Support for any page size from 0.5 KB upwards.
Programmable NAND flash timing parameters.
Support for up to 4 NAND devices.
Hardware AES decryption.
Error Correction Module (ECC) for MLC NAND flash support:
– Reed-Solomon error correction encoding and decoding.
– Uses Reed-Solomon code words with 9-bit symbols over GF(29), a total codeword
length of 469 symbols, including 10 parity symbols, giving a minimum Hamming
distance of 11.
– Up to 5 symbol errors can be corrected per codeword.
– Error correction can be turned on and off to match the demands of the application.
– Parity generator for error correction encoding.
– Wear leveling information can be integrated into protected data.
PNX0103
Rev. 01.14 — 22 January 2007
6 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
– Interrupts generated after completion of error correction task with 3 interrupt
registers.
D
FT
D
D
– Interface is compatible with the ARM External Bus Interface (EBI).
FT
A
A
R
R
D
– Error correction statistics distributed to ARM using interrupt scheme.
FT
FT
FT
FT
R
A
FT
D
4.4 MPMC
R
A
The multi port memory controller supports the interface to a lot of memory types, for
example:
• SDRAM.
• LP-SDRAM.
•
•
•
•
Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM.
Address line supporting up to 64 MByte of dynamic memory.
Low transaction latency.
Read and write buffers to reduce latency and to improve performance, particularly for
un-cached processors.
• 1 AHB Memory interface for accessing external memory.
• 16-bit wide chip select Micron SyncFlash memory support.
• Static memory features include:
– asynchronous page mode read.
– programmable wait states.
– bus turnaround delay.
– output enable, and write enable delays.
– extended wait.
•
•
•
•
•
1 chip select for synchronous memory and 1 chip select for static memory devices.
Power-saving modes.
Dynamic memory self-refresh mode supported.
Controller supports 2K, 4K, and 8K row address synchronous memory parts
A separate AHB control interface to program the MPMC. This enables the MPMC
registers to be situated in memory with other system peripheral registers.
• Support for all AHB burst types.
• Little and big-endian support.
• Support for the External Bus Interface (EBI) that enables the memory controller pads
to be shared.
4.5 EBI
This chapter describes the EBI module, which acts as multiplexer with arbitration between
various external memory controllers and the externally connected memory devices. An
external memory controller is a piece of logic inside of the IC, which controls an externally
connected memory device, between the following:
PNX0103
Rev. 01.14 — 22 January 2007
7 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
• NAND flash
• SDRAM
FT
FT
FT
FT
D
FT
FT
A
A
R
R
D
Main purpose of using the EBI module is to save external pins. However only data and
address pins are multiplexed. Control signals towards and from the external memory
devices are not multiplexed.
D
D
R
A
FT
D
R
A
4.6 Internal ROM Memory
The internal ISROM (Internal Static Memory Controller) module is used as controller
between the AHB and the internal ROM memory. The internal ROM memory can be used
to store the boot code of this IC. After a reset, the ARM processor will start its code
execution from this memory.
• Capacity of 64 kBytes.
4.7 Internal RAM Memory
The ISRAM (Internal Static Memory Controller) module is used as controller between the
AHB bus and the internal RAM memory. The internal RAM memory can be used as
working memory for the ARM and as temporary storage to execute the code that is loaded
automatically from the NAND flash (code execution from NAND flash).
• Capacity of 512 kBytes.
• Implemented as two independent 256 kByte memory banks.
4.8 MCI (Memory Card Interface)
The MCI controller interface can be used to access memory cards according to the
Secure Digital (SD), Memory Card (MC) and Multi-Media Card (MMC) standards. The
host controller can be used to interface to small form factor expansion cards compliant to
the SDIO card standard as well. Finally, it will support CE ATA 1.1 compliant hard disk
drives.
•
•
•
•
•
•
•
•
•
•
One 8-bits wide interfaces.
Supports high-speed SD, versions 1.01, 1.10 and 2.0.
Supports SDIO version 1.10.
Supports MMCplus™, MMCmobile™ and MMCmicro™ cards based on MMC 4.1.
CRC generation and checking.
Supports 1/4-bit SD cards.
Card detection and write protection.
FIFO buffers of 16 bytes deep.
Host pull-up control.
SDIO suspend and resume.
PNX0103
Rev. 01.14 — 22 January 2007
8 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
R
A
FT
D
R
A
4.9 Universal Serial Bus 2.0 High Speed on the Go
The USB OTG module allows the PNX0103 to connect directly to a USB host such as a
PC (in device mode) or to a USB device in host mode. In addition, the PNX0103 has a
special, built-in mode in which it enumerates as a Device Firmware Upgrade (DFU) class,
which allows for a (factory) download of the device firmware through USB.
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
• Contains UTMI+ compliant transceiver (PHY).
• Supports Interrupts.
• This module has its own, integrated DMA engine.
4.10 DMA Controller
The DMA Controller (SDMA) can do DMA transfers on the AHB bus without using the
CPU.
• Supported transfer types:
Memory to Memory copy:
– Memory can be copied from the source address to the destination address with a
specified length, while incrementing the address for both the source and
destination.
Memory to peripheral:
– Data is transferred from incrementing memory to a fixed address of a peripheral,
The flow is controlled by the peripheral.
Peripheral to memory:
Rev. 01.14 — 22 January 2007
D
D
– Including ATA module.
F
D
D
Supports CE ATA 1.1:
PNX0103
A
FT
FT
A
A
R
R
D
D
R
Maximum clock speed of 52 MHz (MMC 4.1).
– 8 bit data width
•
•
•
•
•
•
•
R
FT
FT
D
Individual clock and power ON/OFF features to each card.
FT
SDIO Read-wait.
A
A
A
Suspend and resume operations.
R
R
R
1 to 65,535 bytes blocks.
D
D
D
•
•
•
•
•
•
FT
FT
FT
FT
9 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
D
FT
FT
A
A
R
R
D
• Supports single data transfers for all transfer types.
• Supports burst transfers for memory to memory transfers. A burst always consists of
F
FT
FT
A
A
R
R
D
D
– Data is transferred from a fixed address of a peripheral to incrementing memory.
The flow is controlled by the peripheral.
D
D
R
A
multiples of 4 (32 bit) words.
• Supports swapping in Endianess of the transported data, for file reading / MP3
decoding purposes.
Table 1:
Peripherals that support SDMA access
Peripheral name
Supported Transfer Types
NAND flash controller
Memory to memory
SPI
Memory to peripheral and peripheral to memory
MCI
LCD Interface
Memory to peripheral
UART
I2 C
M/S
SAI
Peripheral to Memory
SAO
Memory to peripheral
4.11 Interrupt Controller
The Interrupt Controller (INTC) collects interrupt requests from multiple devices, masks
interrupt requests, and forwards the combined requests to the processor (see Figure 3).
The interrupt controller also provides facilities to identify the interrupt requesting devices
to be served.
Interrupt
Controller
Interrupt
Requests
nIRQ
ARM 926
nFIQ
Fig 3. Interrupt Controller
• The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
PNX0103
Rev. 01.14 — 22 January 2007
10 of 50
A
(lsreq), terminal count info(tc) and dma clearing (clr).
R
• Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.
• Compatible with ARM flow control, for single requests (sreq), last single requests
D
different areas of memory. Two channels are needed per scatter gather action.
FT
• The SDMA controller has 12 channels.
• Scatter gather possibility. This method is used to gather data, which is located at
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
A
FT
R
FT
FT
A
A
R
D
D
R
A
FT
D
Support for nesting of interrupt service routines.
R
A
Interrupts routed to NIRQ and to NFIQ are vectored.
Level interrupt support.
NAND flash controller
USB 2.0 HS OTG
Event router
10 bit adc
UART
LCD int
MCI
SPI
I2C M/S 0 and I2C M/S 1
Timer0, Timer1, Timer2 and Timer3
SAO1 and SAO2
SAI1 and SAI2
SDMA.
IPINT.
4.12 AHB Multi layer Bus
The Multi layer AHB is an interconnection scheme, based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.
Multiple masters can have access to different slaves at the same time.
Figure 4 gives an overview of the AHB Multi layer Bus configuration in the PNX0103.
PNX0103
F
D
D
Visibility of interrupts request state before masking.
The following blocks can generate interrupts:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A
FT
FT
A
A
R
R
R
D
D
D
distinct levels of priority on all interrupt sources, NFIQ for high priority interrupts and
NIRQ for normal priority interrupts.
Software interrupt request capability associated with each request input.
R
R
FT
FT
A
A
R
R
D
D
D
• Two interrupt lines (NFIQ, NIRQ) to the ARM core. The ARM core supports two
•
•
•
•
•
FT
FT
FT
FT
Rev. 01.14 — 22 January 2007
11 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
R
A
FT
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
USB 2.0
HS OTG
2 Cache 16 Kbytes
D
R
FT
FT
A
A
R
R
D
D
D
ARM926 EJ-S
MCI
SDMA
FT
FT
FT
FT
M
M
R
S
S
S
S
VPB bridge 3
async
VPB bridge 2
async
SAO1
SAI1
SAO2
SAI2
Legend:
M = Master port
S = Slave port
UART
LCD int
SPI
S
VPB bridge 1
async
VPB bridge 0
async
I2C MS0
Timer 0
Timer 1
Timer 2
Timer 3
PWM
I2C MS1
S
S
A
VPB bridge 4
sync
S
ISRAM
2 x 256 Kbytes
R
MPMC
S
S
IROM
64 Kbytes
D
NAND-flash
Controller
S
FT
S
A
AHB Multilayer Bus
S
Interrupt
Controller
Watchdog
Syscreg
CGU
IOCONF
10 bitADC
Event router
RNG
OTP
Fig 4. AHB Multi Layer Block Diagram
• Supports all combinations of 32-bit masters and slaves (fully connected interconnect
matrix).
• Round-Robin priority mechanism for bus arbitration: all masters have the same
priority and get bus access in their natural order
• 5 devices on a master port (listed in their natural order for bus arbitration):
– SDMA.
– ARM926 Instruction port.
– ARM926 Data port.
– USB OTG.
– MCI.
• Devices on a slave port (some ports are shared between multiple devices):
– AHB to VPB Bridge 0.
– Interrupt Controller.
– USB 2.0 HS OTG.
– 256 kByte ISRAM.
– 256 kByte ISRAM.
– 64 kByte IROM.
– NAND flash Controller.
• Designed to work according to the Multi layer AMBA Advanced System Bus (AHB
Lite) concept.
PNX0103
Rev. 01.14 — 22 January 2007
D
M
D
S
M
12 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
The (AHB to) VPB Bridge is a bus bridge between AMBA Advanced High-performance
Bus (AHB) and the VLSI Peripheral Bus /Advanced Peripheral Bus (VPB / APB) interface.
F
FT
FT
A
A
R
R
D
D
D
4.13 VPB Bridge
FT
FT
FT
FT
D
D
The module supports two different architectures:
R
A
A
side and at the VPB side of the bridge.
4.14 Clock Generation Unit
The clock generation unit (CGU) generates all clock signals in the system and controls the
reset signals for all modules.
As shown in the block diagram of the CGU in Figure 5, the CGU has a very regular
structure. Each output clock generated by the CGU belongs to one of the system or audio
clock domains. Each clock domain is fed by a single base clock that originates from one of
the available clock sources. Within a clock domain, fractional dividers are available to
divide the base clock to a lower frequency.
Within most clock domains, the output clocks are again grouped into one or more sub
domains. All output clocks within one sub domain are either all generated by the same
fractional divider or they are connected directly to the base clock. Therefore all output
clocks within one sub domain have the same frequency and all output clocks within one
clock domain are synchronous because they originate from the same base clock
The CGU has a reference clock (generated by the 12 MHz external crystal used by the
reference oscillator to generate reference clock) and several external clock inputs
(dai_bck0, dai_ws0) Furthermore the CGU has several phase locked loop (PLL) circuits to
generate clock signals that can be used for system clocks and/or audio clocks. All clock
sources, except the output of the PLLs, can be used as reference input for the PLLs.
• Several advanced features to optimize the system for low power:
– All output clocks can be disabled individually for flexible power optimization
– Some modules have automatic clock gating: they are only active when (bus)
access to the module is required.
– Variable clock scaling for automatic power optimization of the AHB bus (high clock
frequency when the bus is active, low clock frequency when the bus is idle).
– Clock wake-up feature: when switched off, module clocks can be programmed to
be activated automatically on the basis of an (external) event detected by the
Event Router (see also Section 4.18). An example of the use of this feature would
be that all clocks (including the ARM / bus clocks) are off and activated
automatically when a button is pressed.
• Five Clock sources:
– Reference clock generated by the oscillator with an external 12 MHz crystal.
Rev. 01.14 — 22 January 2007
R
• Dual Clock Architecture, asynchronous bridge. Different clocks are used at the AHB
PNX0103
D
side and at the VPB side of the bridge.
FT
• Single Clock Architecture, synchronous bridge. The same clock is used at the AHB
13 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
– Pins DAI_BCK0, DAI_WS0, DAI_BCK1 and DAI_WS1 are used to input external
clock signals (used for generating audio frequencies in DAI / DAO slave mode, see
also Section 4.3).
D
FT
FT
A
A
R
R
D
– System PLL generates programmable system clock frequency from its reference
input .
D
D
R
A
– Each clock generated by the CGU is derived from one of the base clocks and
optionally divided by a fractional divider.
– Each base can be programmed to have any one of the clock sources as an input
clock.
– Fractional dividers can be used to divide a base clock by a fractional number to a
lower clock frequency.
– Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
output clock.
• Register interface to reset all modules under software control.
• Based on the input of the Watchdog timer (see also Section 4.15), the CGU can
generate a system-wide reset in the case of a system hang-up.
Clock resources
Oscillator
System PLL
Reference input
Audio PLL
DAI_WS0
DAI_BCK1
DAI_WS1
Base
Fractional
divider 0
Clock
outputs
Clock domain 0
4
Reference input
DAI_BCK0
Subdomain
clocks
Fractional
divider M
To modules
12 Mhz
crystal
(external)
Switchbox
1
Clock domain n
1
1
1
Fig 5. CGU Block Diagram
PNX0103
Rev. 01.14 — 22 January 2007
14 of 50
A
clocks.
R
• Highly flexible switchbox to distribute the signals from the clock sources to the module
D
Remark: Both the System PLL and the Audio PLL generate their frequencies
based on their (individual) reference clocks. The reference clocks can be
programmed to the oscillator clock or one of the external clock signals.
FT
– Audio PLL generates programmable audio clock frequency (typically 256·fs) from
its reference input.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
D
FT
FT
A
A
R
R
D
The Watchdog Timer (WDOG) can be used to generate a system reset if there is a
CPU/software crash. In addition the watchdog timer can be used as an ordinary timer.
Figure 6 shows how the Watchdog Timer module is connected in the system.
FT
A
A
R
R
D
D
D
4.15 Watchdog Timer
FT
FT
FT
FT
D
D
R
A
FT
watchdog generated reset.
• Watchdog timer can also be used as a normal timer in addition to the watchdog
functionality (output m0).
Watchdog Timer
m0
Event Router
I nterrupt
Controller
VPB
m1
CGU
FIQ
IRQ
Reset
Fig 6. Watchdog Timer
4.16 IO Configuration
Through the register interface provided in the Input/Output Configuration module
(IOCONF), the General Purpose Input/Output (GPIO) pins can be controlled. Next to
several dedicated GPIO pins, most digital IO pins can also be used as GPIO if not
required for their normal, dedicated function.
• Provides control for the digital pins that can double as GPIO (next to their normal
function). The pinning list in Table 7 indicates which pins can double as GPIO.
• Each controlled pin can be configured for 4 operational modes:
– Normal operation (i.e. controlled by a function block).
– Driven low.
– Driven high.
– High impedance / input.
• A GPIO pin can be observed (read) in any mode.
• The register interface provides ‘set’ and ‘clear’ access methods for choosing the
operational mode.
PNX0103
Rev. 01.14 — 22 January 2007
15 of 50
A
• Watchdog counter can be reset by a periodical software trigger.
• After a reset, a register will indicate whether a reset has occurred because of a
R
expired, in the event of a software or hardware failure (output m1).
D
• Generates a chip-wide reset request when its programmed time-out period has
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
This module is a 10-bit successive approximation Analog-to-Digital converter (ADC10B)
with an input multiplexer to allow for multiple analog signals on its input. A common use of
this module is to read out multiple keys on one input with a resistor network.
F
FT
FT
A
A
R
R
D
D
D
4.17 10 Bit Analog to Digital Converter
FT
FT
FT
FT
D
D
R
A
FT
Programmable ADC resolution from 2 to 10 bits.
Scan rate depends on the resolution chosen.
Single A/D conversion scan mode and continuous A/D conversion scan mode.
Power down mode available.
4.18 Event Router
The Event Router extends the interrupt capability of the system by offering a flexible and
versatile way of generating interrupts. Combined with the wake-up functionality of the
CGU, it also offers a way to wake-up the system from suspend mode (with all clocks
deactivated).
interrupt_0
interrupt_1
Input
Signals
Event
Router
interrupt_2
Interrupt
Controller
interrupt_3
cgu_wakeup
CGU
VPB
Fig 7. Event Router Block Diagram
The Event Router has four interrupt outputs that are connected to the interrupt controller
and one wake-up output connected to the CGU as shown in Figure 7. The output signals
are activated when an event (for instance a rising edge) is detected on one of the input
signals. The input signals of the Event Router are numerous and are connected to
relevant internal (control) signals in the system or to external signals through pins of the
IC.
• Provides programmable routing of input events to multiple outputs for use as
interrupts or wake up signals.
• Input events can come from internal signals (Table 2) or from the pins that can be
used as GPIO (also when they are in normal mode).
• Inputs can be used either directly or latched (edge detected) as an event source.
• The active level (polarity) of the input signal for triggering events is programmable.
• Direct events will disappear when the input becomes inactive.
PNX0103
Rev. 01.14 — 22 January 2007
16 of 50
A
•
•
•
•
R
available externally on a pin, one input is predefined (battery level divided by 2).
D
• Four analog input channels, selected by an analog multiplexer. Three inputs are
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
R
A
FT
D
R
Module can be used to generate a system wake-up from suspend mode.
A
Input signals of the Event Router
Signal name
Description
Internal Events
Following is the list of those internal signals.
ccp_ipint_int_fsi_ip
Event raised by IP_INT block when IP data is
available, per PCM/IOM frame.
ssa1_timer0_intct1
Event raised by Timer0 indicating Counter Time-out.
ssa1_timer1_intct1
ssa1_timer2_intct1
ssa1_timer3_intct1
ssa1_adc_int
Event raised by ADC.
wdog_m0
Event raised by Watchdog indicating a soft interrupt.
arm926_901616_lp_nfiq
Event raised by ARM9 indicating a fast interrupt.
arm926_901616_lp_nirq
Event raised by ARM9 indicating a normal interrupt.
usb_otg_ahb_needclk
Event raised by USB indicating that it needs clock to
be running.
usb_atx_pll_lock
Event raised by USB indicating a locked pll.
usb_otg_vbus_pwr_en
Event raised by USB indicating that it needs to
enable the power enabling on vpb-bus.
isram0_mrc_finished
Event raised by Memory Redundancy Controller of
ISRAM0, to indicate that the information transfer from
dedicated memory poly fuse box to Memory
Redundancy Register in bistshell has finished.
isram1_mrc_finished
Event raised by Memory Redundancy Controller of
ISRAM1, to indicate that the information transfer from
dedicated memory poly fuse box to Memory
Redundancy Register in bistshell has finished.
Note that they can be used to trigger events when in the normal, functional mode, but not in the
GPIO mode.
4.19 Random Number Generator
The Random Number Generator (RNG) generates true random numbers for use in
advanced security and Digital Rights Management (DRM) related schemes. These
schemes rely upon truly random, i.e. completely unpredictable numbers.
• True random number generator.
• The random number generated by the circuit, depends (among other things) on both
VLSI technology process spread and the temperature of the chip.
Rev. 01.14 — 22 January 2007
D
D
Event detection is fully asynchronous (no active clock required).
Remark: All pins that can be used as GPIO are connected to the Event Router (see Figure 14).
F
D
D
Event detect status can be read for each output separately.
PNX0103
A
FT
FT
A
A
R
R
R
Each input can be masked for each output individually.
Table 2:
R
FT
D
D
Each input can be masked globally for all inputs at once.
D
A
FT
FT
A
A
R
R
R
Latched events will remain active until they are explicitly cleared.
D
D
D
•
•
•
•
•
•
FT
FT
FT
FT
17 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
A
FT
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
D
D
4.20 Secure One-Time Programmable Memory
R
R
FT
FT
A
A
R
R
D
D
D
• The random number register does not rely on any kind of reset.
• The generators are free running in order to ensure randomness and security.
FT
FT
FT
FT
R
A
The Secure One-Time Programmable Memory (OTP) can be used for storing non-volatile
information like serial number, security bits, etc. It consists of a poly fuse array, embedded
data registers and control registers. One of the main features of the OTP is storing a
security key and a unique ID needed to support advanced Digital Rights Management
(DRM) schemes.
– 32 bits are used for security and other features, which are programmed at the
production line.
– 32 bits are available for customer use.
– 192 bits are reserved for future use.
•
•
•
•
Programmable at the customer production line.
Random read access via sixteen 32-bit registers.
Flexible read protection mechanism to hide security related data.
Flexible write protection mechanism.
4.21 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) module is used for synchronous serial data
communication with other devices which support the SPI/SSI protocol. Examples of the
devices that this SPI module can communicate with are memories, camera and WiFi-g.
The SPI/SSI-bus is a 5-wire interface and it is suitable for low, medium, and high data rate
transfers.
• Supports Motorola SPI frame format with a word size of 8/16 bits.
• Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size
of 4…16 bits.
•
•
•
•
•
•
•
•
Receive FIFO and transmit FIFO of 64 half-words each.
Serial clock rate master mode maximum 45 MHz.
Serial clock rate slave mode maximum 25 MHz.
Support for single data access DMA.
Full-Duplex operation.
Multiple slaves support (maximum is 3 slaves).
Supports maskable interrupts.
Supports DMA transfers.
PNX0103
Rev. 01.14 — 22 January 2007
18 of 50
A
– 128 bits are used for an AES key programmable at customer production line.
R
– 128 bits are used for an unique ID, which is pre-programmed in the wafer fab.
D
• 512-bit one-time programmable memory.
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
D
FT
FT
A
A
R
R
D
The Universal Asynchronous Receiver Transmitter (UART) module supports the industry
standard serial interface.
F
FT
FT
A
A
R
R
D
D
D
4.22 Universal Asynchronous Receiver Transmitter
FT
FT
FT
FT
D
D
R
A
FT
Programmable baud rate with a maximum of 1049 Kbaud.
D
R
A
•
•
•
•
•
•
•
•
•
•
•
•
Programmable data length (5-8 bits).
Implements only asynchronous UART.
Transmit break character length indication.
Programmable 1 to 2 stops bits in transmission.
Odd/Even/Force parity check/generation.
Frame error, overrun error and break detection.
Automatic hardware flow control.
Independent control of transmit, receive, line status, data set interrupts and FIFO’s.
SIR-IrDA encoder/decoder (from 2400 to 115 kbaud).
Supports maskable interrupts.
4.23 IP_INT Interface
The IP_INT interface supports the PCM and IOM interface.
• Four wire serial interface.
• Can function in both Master and Slave modes.
• Supports:
– PCM: Pulse code modulation. Single clocking physical format.
– MP PCM: Multi-Protocol PCM. Configurable directional per slot.
– IOM-2: Extended ISDN-Oriented modular. Double clocking physical format.
• Twelve eight bit slots in a frame with enabling control per slot.
• Internal frame clock generation in master mode.
• Receive (RX) and Transmit (TX) DMA handshaking using a request/clear protocol
Interrupt generation per frame.
• Interrupt generation per frame.
PCM (Pulse Code Modulation) is a very common method used for transmitting analog
data in digital format. Most common applications of PCM are Digital audio as in Audio CD
and computers, digital telephony and digital videos.
The IOM (ISDN Oriented Modular) interface is primarily used to interconnect
telecommunications IC’s providing ISDN compatibility. It delivers a symmetrical full-duplex
communication link containing user data, control/programming, and status channels.
PNX0103
Rev. 01.14 — 22 January 2007
19 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
The LCD interface (LCD Int) contains logic to interface to a 6800 (Motorola) / 8080 (Intel)
compatible LCD controller which supports 4/8/16 bit modes. This module also supports a
serial interface mode. The speed of the interface can be adjusted in software to match the
speed of the connected LCD display.
F
FT
FT
A
A
R
R
D
D
D
4.24 LCD Interface
FT
FT
FT
FT
D
D
R
A
FT
D
R
A
• 4/8/16 bit parallel interface mode: 6800-series, 8080-series.
• Serial interface mode.
• Supports multiple frequencies for the 6800/8080 bus, to support high and low speed
controllers.
• Supports polling the busy flag from LCD controller to off load the CPU from polling.
• Contains an 16 byte FIFO for sending control and data information to the LCD
controller.
• Supports maskable interrupts.
• Supports DMA transfers.
4.25 I2C Master / Slave Interface
The PNX0103 contains two I2C Master / Slave interfaces (I2C). I2C Master/Slave 0 of the
PNX0103 can be used for communicating directly with I2C compatible external devices.
I2C Master/Slave 1 is used for controlling some of the modules in the PNX0103 (as
indicated in Figure 1).
• Serial interface that meets the I2C bus specification
• Supports normal mode (100 kHz SCL)
• Fast mode (400 kHz SCL:: 24 MHz VPB_clock; 325 kHz :: 12 MHz VPB_clock;
175 kHz :: 6 MHz VPB_clock)
• Interrupt support
• Supports SDMA transfers (single).
• Four modes of operation:
– Master transmitter
– Master receiver
– Slave transmitter
– Slave receiver
• Supports DMA transfers
4.26 LCD/NF/SDRAM Interface
The PNX0103 contains a rich set of specialized hardware interfaces but the TFBGA
package does not contain enough pins to allow use of all signals of all interfaces
simultaneously. Therefore a pin-multiplexing scheme is created for the Storage, Video,
Audio and External Bus hardware interfaces, which allows the selection of the right
interface for the application.
PNX0103
Rev. 01.14 — 22 January 2007
20 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
A
FT
R
A
F
FT
FT
A
A
R
R
D
D
D
FT
FT
A
A
R
R
D
D
• Supports pin multiplexing between RAM-based LCD interface and External Bus
Interface.
R
R
FT
FT
A
A
R
R
D
D
D
FT
FT
FT
FT
D
D
• Supports pin multiplexing between NAND flash controller and Memory Card Interface.
• Supports pin multiplexing between Universal Asynchronous Receiver Transmitter and
R
A
D
R
The Pin Interface Multiplexing is subdivided into four categories: Storage, Video, Audio
and External Bus related pin multiplexing. Each category supports several modes, which
can be selected by programming the corresponding registers in the SysCReg.
4.26.1 Pin connections
Signals to pins of the IC for the Pin Interface Multiplexing
Pin Name
Default Signal
Alternate Signal
Description
mLCD_CSB
LCD_CSB
EBI_NSTCS_0
Video related pin multiplexing.
mLCD_DB_1
LCD_DB_1
EBI_NSTCS_1
mLCD_DB_0
LCD_DB_0
EBI_CLKOUT
mLCD_E_RD
LCD_E_RD
EBI_CKE
mLCD_RS
LCD_RS
EBI_NDYCS
mLCD_RW_WR
LCD_RW_WR
EBI_DQM_1
mLCD_DB_2
LCD_DB_2
EBI_A_2
mLCD_DB_3
LCD_DB_3
EBI_A_3
mLCD_DB_4
LCD_DB_4
EBI_A_4
mLCD_DB_5
LCD_DB_5
EBI_A_5
mLCD_DB_6
LCD_DB_6
EBI_A_6
mLCD_DB_7
LCD_DB_7
EBI_A_7
mLCD_DB_8
LCD_DB_8
EBI_A_8
mLCD_DB_9
LCD_DB_9
EBI_A_9
mLCD_DB_10
LCD_DB_10
EBI_A_10
LCD_DB_11
mLCD_DB_11
EBI_A_11
mLCD_DB_12
LCD_DB_12
EBI_A_12
mLCD_DB_13
LCD_DB_13
EBI_A_13
mLCD_DB_14
LCD_DB_14
EBI_A_14
mLCD_DB_15
LCD_DB_15
EBI_A_15
mGPIO5
GPIO5
MCI_CLK
Storage related pin multiplexing.
mGPIO6
GPIO6
MCI_CMD
mGPIO7
GPIO7
MCI_DAT_0
mGPIO8
GPIO8
MCI_DAT_1
mGPIO9
GPIO9
MCI_DAT_2
mGPIO10
GPIO10
MCI_DAT_3
mNAND_RYBN0
NAND_RYBN0
MCI_DAT_4
mNAND_RYBN1
NAND_RYBN1
MCI_DAT_5
PNX0103
Rev. 01.14 — 22 January 2007
21 of 50
A
• Supports pin multiplexing between Digital Audio Output and IOM/PCM Interface.
Table 3.
FT
Serial Peripheral Interface.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
FT
R
Alternate Signal
Description
mNAND_RYBN2
NAND_RYBN2
MCI_DAT_6
mNAND_RYBN3
NAND_RYBN3
MCI_DAT_7
mDAO_DATA0
DAO_DATA0
IPINT_DA
Digital Audio related pin
multiplexing.
mDAO_BCK0
DAO_BCK0
IPINT_FSC
multiplexing.
mDAO_WS0
DAO_WS0
IPINT_DCK
multiplexing.
mDAO_CLK0
DAO_CLK0
IPINT_DB
multiplexing.
mUART_CTS_N
UART_CTS_N
SPI_CS_OUT1
External Bus Interface related pin
multiplexing.
mUART_RTS_N
UART_RTS_N
SPI_CS_OUT2
External Bus Interface related pin
multiplexing.
D
FT
FT
A
A
R
R
D
R
A
FT
D
R
A
Figure 8 shows a simplified version of the LCD/NF/SDRAM interface.
MPMC
LCD Interface
control
data
EBI
control
MUX
SysReg
MUX
data
control
address data
LCD
(Static Interface)
control
SDRAM
data
control
LCD
(Dedicated Interface)
Fig 8. Simplified multiplexing diagram
With the muxing between LCD-Interface and MPMC the following two mode of operation
are possible:
• MPMC-mode: indicated by the curved dotted lines. (SDRAM + Static LCD-Interface).
• LCD-mode indicated by the curved solid lines. (Dedicated LCD-Interface.
PNX0103
Rev. 01.14 — 22 January 2007
D
D
4.26.2 Multiplexing between LCD and MPMC
address data
F
FT
FT
Default Signal
A
A
A
R
R
D
D
D
Pin Name
NandFlash
R
A
FT
FT
A
A
R
R
R
Signals to pins of the IC for the Pin Interface Multiplexing
D
D
D
Table 3.
FT
FT
FT
FT
22 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
The block diagram Figure 9 gives a high level overview of the modules in the chip that are
involved in the Pin Interface Multiplexing between the EBI, NAND flash controller, MPMC
and RAM-based LCD interface.
F
FT
FT
A
A
R
R
D
D
D
In both modes external NAND flash is accessible.
FT
FT
FT
FT
D
D
R
A
FT
D
R
A
NandFlash Interface
Ctrl
Ctrl
ALE
CLE
MPMC
Data
D(15:0)
Data
D(15:0)
Addr
LCD Interface
Ctrl
A(15:0)
Data
Ctrl
DB(15:2)
EBI
Data
Addr
EBI_A(1:0)
EBI_A(15:2)
SysReg
Control
This AND combines
signals from MPMC
interface itself
NCS0
NCS1
NCS2
NCS3
RYBN0 EBI_A_0_ALE
RYBN1 EBI_A_1_CLE
RYBN2
RYBN3
EBI_D(15:0)
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
EBI_DQM_0_NOE
EBI_A(15:2) MPMC_NSTCS_0/LCD_CSB
/LCD_DB(15:2) MPMC_NSTCS_1/LCD_DB(1)
MPMC_CLKOUT/LCD_DB(0)
MPMC_CKE/LCD_E_RD
MPMC_NDYCS/LCD_RS
MPMC_DQM_1/LCD_RW_WR
NOTE:
The supply of the LCD interface is on a seperate
power domain as the NandFlash and MPMC.
Fig 9. Muliplexing diagram of LCD and MPMC
Figure 9 only shows the signals that are involved in pad-muxing, so not all interface
signals are visible.
The EBI-unit between the NAND flash-Interface and MPMC contains an arbiter that
determines which Interface is muxed to the outside world. Both NAND flash and SDRAM
initiate a request to the EBI-unit. This request is granted using round-robin arbitration.
4.26.3 Supply domains
As is shown in Figure 9 the EBI-Interface (NAND flash/MPMC-address/data) is on a
different supply domain as the LCD-Interface (muxed with MPMC-control). The
EBI-Interface is supplied with 1.8 V or 3.3 V domain and the LCD-Interface (including
MPMC-control) can be supplied with 2.7 to 3.3 V.
Because of this the following limitation is applicable for external SDRAM: When SDRAM
is used then the external memory interface (SDRAM, NAND flash) should run on 3.3 V
domain and LCD should be connected as a static memory interface to the MPMC.
Remark: Due to the fact the USB is connected to the LCD supply there is the following
limitation:
PNX0103
Rev. 01.14 — 22 January 2007
23 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
A
A
R
F
Supply domain 3.3 V.
A
→
R
When using LCD together with USB
D
Supply domain 1.8 V or 3.3 V.
FT
→
R
A
When using only LCD
R
Supply domain 1.8 V or 3.3 V.
D
→
D
When using only NAND flash
D
R
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
D
When using SDRAM the NAND flash should use the same 3.3 V supply as for LCD
D
R
•
•
•
•
FT
FT
FT
FT
A
FT
D
4.27 Timer Module
R
A
The PNX0103 contains four fully independent Timer modules, which can be used to
generate interrupts after a pre-set time interval has elapsed.
• Each timer is a 32 bit wide down-counter with selectable pre-scale. The pre-scaler
allows either the module clock to be used directly, or the clock divided by 16 or 256
may be used.
• Two modes of operation:
– Free-running timer: the timer will restart counting from the value in the Load
register every time after reaching zero. An interrupt will be generated every time
the counter reaches zero. This effectively gives a repeated interrupt at a fixed
interval.
– Periodic timer: the timer will count down once from the value in the Load register
and generate an interrupt upon reaching zero.
• At any time the current timer value can be read.
• At any time the value in the Load register may be re-written, causing the timer to
restart.
4.28 Pulse Width Modulation Module
This pulse width modulation module (PWM) can be used to generate a pulse width
modulated or a pulse density modulated signal. With an external low pass filter, the
module can be used to generate a low frequent analog signal. A typical use of the output
of the module is to control the backlight of an LCD display.
• Supports Pulse Width Modulation (PWM) with software controlled duty cycle.
• Supports Pulse Density Modulation (PDM) with software controlled pulse density.
4.29 System Control Registers
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
PNX0103
Rev. 01.14 — 22 January 2007
24 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
4.30 ADSS
FT
FT
FT
FT
D
FT
R
A
D
SDC
PGA
SDC
MUX_R1
A
LNA
PGA
R
TUN_INR
HP_OUTR
SDAC
DMUX
DEC
CLASS
-AB
INT
MUX_L1
SDAC
HP_OUTC
HP_OUTL
MUX_L0
ADC_INL
PGA
SDC
TUN_INL
PNX0103-D
DAI0
DAO
DAI
DAI1
DAO1
SAI2
SAO2
SAI1
AHB
SAO1
DAO0
DAO
Fig 10. Audio Paths Block Diagram
The following 3 sub-chapters form the ADSS.
4.30.1 Digital Audio Input / Output
The Digital Audio Input (DAI) and Digital Audio Output (DAO) modules provide 3-wire
digital audio interface that comply with the I2S standard.
The DAI and DAO modules have the following features:
•
•
•
•
•
Audio interface compatible with the I2S standard.
DAI supports master mode and slave mode.
DAO support master mode.
Supports LSB justified words of 16, 18, 20 and 24 bits.
Supports a configurable number of bit clock periods per Word Select period (up to 128
bit clock periods).
4.30.2 Simple Audio Input / Output
The Simple Audio Input (SAI) and Simple Audio Output (SAO) modules provide a bridge
between the VPB bus and an audio stream (input / output). Using these modules together
with the SDMA module (see Section 4.10), uninterrupted audio streams from a buffer in
memory can be guaranteed with only a low overhead on the ARM core.
This module has the following features:.
PNX0103
FT
HP_FCR
MUX_R0
ADC_INR
DAI
D
D
AVC
ADC_MIC 1
FT
A
A
R
R
D
HP_FCL
PNX0103-A
Rev. 01.14 — 22 January 2007
25 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
F
D
FT
FT
A
A
R
R
D
D
D
Supports single 24 bit transfers to/from the left or right FIFO.
R
A
4.31 Stereo Digital to Analog Converter
The Stereo Digital to Analog Converter converts a digital audio signal into an analog audio
signal. The output of this module is connected to the input of the class-AB headphone
amplifier.
•
•
•
•
•
Stereo Digital-to-Analog converter with support for 24-bit audio samples.
•
•
•
•
•
Digital dB-linear volume control in 0.25 dB steps.
Supports sample rates from 8 kHz up to 96 kHz.
Filter implementations have a 24-bit data path with 16-bit coefficients.
Full FIR filter implementation for all of the up-sampling filters.
Controlled power down sequence comprising a raised cosine mute function followed
by a DC ramp down to zero to avoid audible plops or clicks.
Digital de-emphasis for 32 kHz, 44.1 kHz, 48 kHz and 96 kHz.
Selection for the up-sampling filter characteristics (sharp/slow-roll-off).
Support for 2 fs and 8 fs input signals:
Soft mute with a raised cosine function.
4.32 Class AB Headphone Amplifier
The Class AB headphone amplifier will amplify an analog input signal to levels appropriate
for a headphone output. Its input can be chosen to come from the Stereo Digital-to-analog
converter or from the analog by-pass from the tuner input (through the Aanalognalog
Volume Control block). The class-AB amplifier offers a solution in cases where high output
levels are required or when the headphone wire is also used as an antenna for tuner
reception.
• Stereo headphone amplifier.
• Three outputs: left, right and a common signal ground output.
• Common signal ground output enables DC coupling of headphone without electrolytic
capacitors.
• 16 Ω and higher output drive capability.
PNX0103
Rev. 01.14 — 22 January 2007
26 of 50
A
/ not empty for left and right channel separately).
R
• Provides maskable interrupts for audio status. (FIFO underrun / overrun / full / half_full
D
samples) to reduce busload.
FT
Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio
sample, and the higher 16 bits representing the right audio sample.
• Supports two 16-bit samples audio samples combined in a 32-bit word (2 left or 2 right
A
FT
FT
A
A
R
R
R
Supports single 16 bit transfers to/from the left or right FIFO.
R
FT
D
D
Transmit FIFO (SAO) or receive FIFO (SAI) of 4 stereo samples.
D
A
FT
FT
A
A
R
R
R
D
D
D
•
•
•
•
•
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
• Individual power down modes for each output.
• Programmable short-circuit current protection for each amplifier.
• Additional input with Analogue Volume Control (ANVC) directly connected to the tuner
D
FT
FT
A
A
R
R
D
D
D
input pins.
R
A
FT
D
4.33 Stereo Analog to Digital Converter for Audio
R
DIGITAL OUTPUTS
mic
PGA
LNA
SDC
MUX
ANALOGUE INPUTS
left_out
ADC
PGA
SDC
tuner_in_right
MUX
line_in_right
PGA
SDC
MUX
tuner_in_left
MUX
line_in_left
right_out
ADC
to AVC / class AB Amplifier
Fig 11. Analogue to Digital Converter for Audio
•
•
•
•
•
•
•
•
•
•
•
•
Three input options: line-in (stereo), tuner-in (stereo), microphone-in (mono).
Low Noise Amplifier (LNA) with a fixed 30 dB gain for the microphone input.
Programmable Gain Amplifier (PGA), gain can be set in steps of 3 dB up to 24 dB.
Single-to-differential converter (SDC).
Stereo Analogue-to-Digital converter (switched cap).
Supported audio sample frequencies 8 kHz to 55 kHz.
Over-sampling rate 128 times the sample frequency.
High dynamic range.
Digital dB-linear volume control in 0.5 dB steps.
DC blocking filter (optional).
Soft start-up.
Mute detection / overflow detection.
PNX0103
Rev. 01.14 — 22 January 2007
27 of 50
A
The Stereo Analogue to Digital Converter can convert analog audio input signals into
digital audio signals as shown in Figure 11. The module has three input signals: stereo
line-in, stereo tuner-in and mono microphone in. These signals can be pre-processed by a
Low Noise Amplifier (LNA, microphone input only), a Programmable Gain Amplifier (PGA)
and a Single to Differential Converter (SDC) before they arrive at the input of the actual
analog to digital converter.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
The Real Time Clock (RTC) module keeps track of the actual date and time, also when
the system is switched off. Advanced Digital Rights Management (DRM) schemes require
a secure and accurate real-time clock for managing rights such as time-limited playback
rights.
F
FT
FT
A
A
R
R
D
D
D
4.34 Real Time Clock
FT
FT
FT
FT
D
D
R
A
FT
D
R
A
•
•
•
•
•
•
•
Normal power supply directly from Li-ion battery (PSU is by-passed).
Backup power supply from (external) capacitor.
Automatic switching between normal power supply and backup power supply.
Signals power loss to indicate invalid real time clock readings.
Runs on a 32 kHz oscillator.
Ultra-low power consumption.
The clock is implemented as a counter of 32 bits counting at the rate of 1 Hz (derived
from the 32 kHz clock).
• Alarm timer that can generate an interrupt. This interrupt is available both as an
internal signal as well as a signal on an external pin.
• The external interrupt can be used to switch on the system by switching on the PSU
through the PSU_PLAY pin.
• The internal interrupt signal can be used to wake-up the system from suspend mode
through the Event Router.
• Dedicated permanent supply domain.
4.35 Power Supply Unit
The integrated Power Supply Unit (PSU) allows the system to run directly from the battery
voltage or the USB power supply (Vbus) voltage. It converts the battery voltage / USB
Vbus voltages into the supply voltage required for both the digital and analog blocks in the
rest of the system.
• Takes power from the Li-Ion battery or the USB power supply.
• Outputs in Li-Ion battery mode:
– Vout1 2.4 V – 3.2 V (software programmable in 8 levels), 100 mA
(analog power supply and IO).
– Vout2 0.9 V – 1.4 V (software programmable in 8 levels), 100 mA
(digital power supply).
– Vout3 1.4 V or 1.8 V (software selectable), 50 mA (digital power supply).
– Vout1 and Vout2 generated by two inductive dc/dc buck converters with internal
power switches
– Vout3 generated by an LDO from Vout1.
• Outputs in USB power supply mode.
– Vout1 3.2 V, 100 mA.
– Vout2 1.2 V, 100 mA.
PNX0103
Rev. 01.14 — 22 January 2007
28 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
D
A
F
FT
FT
A
A
R
R
R
D
FT
FT
A
A
R
R
D
– Vout2 and Vout3 are generated by an LDO from Vout1.
R
A
D
D
– Vout1 is generated by an LDO from the 5 V USB power supply.
D
R
FT
FT
A
A
R
R
D
D
D
– Vout3 1.4 V or 1.8 V (software selectable), 50 mA.
FT
FT
FT
FT
D
D
• ‘Supply_OK’ detection that is connected to the system reset signal.
R
A
FT
D
Figure 12 and Table 4 show IBAT Vers Efficiency Vout1.
R
A
Figure 13 and Table 5 show IBAT Vers Efficiency Vout2.
efficiency Vout1(=sup3=2.86V)
(sup1=1.071V, 0mA, sup2=1.396V 0mA)
100
90
Effiency (%)
80
70
eff Vout1(=sup3)
60
50
40
30
0
5
10
15
20
25
30
35
current (mA)
Fig 12. Efficiency Vout1 - 2.86 Volts
Table 4.
Efficiency Vout1 values @ 2.86 Volts
Ibat
Vbat
I sup 3
V sup 4
Efficiency (Vout1 = Sup 3)
2
3.602
1
2.8676
39.80566352
2.8
3.6016
2
2.864
56.80015231
3
2.8605
66.22816876
3.598
4.396
3.601
4
2.8569
72.18953182
5.195
3.6006
5
2.8533
76.27057345
5.994
3.6003
6
2.8498
79.23374865
6.793
3.5999
7
2.8462
81.47256753
7.59
3.5995
8
2.8426
83.23802841
8.388
3.5992
9
2.83991
84.63671469
9.231
3.5988
10
2.8542
85.9167695
13.32
3.597
15
2.8549
89.37941277
17.368
3.595
20
2.837
90.87420537
25.59
3.591
30
2.8198
92.056375145
PNX0103
Rev. 01.14 — 22 January 2007
29 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
A
FT
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
(sup2=1.398V, 0mA, sup3=2.912V, 0mA)
R
R
FT
FT
A
A
R
R
D
D
D
efficiency (Vout2=sup1=1.07V)
FT
FT
FT
FT
D
D
R
90
A
FT
D
80
R
A
Efficiency (%)
70
60
eff (Vout2=sup1)
50
40
30
20
0
5
10
15
20
25
30
35
Current (mA)
Fig 13. Efficiency Vout2 - 1.07 Volts
Table 5.
Efficiency Vout1 values @ 1.07Volts
Ibat
Vbat
I sup 1
V sup 1
Efficiency (Vout2 = Sup 1)
1.002
3.602
1
1.072
29.70184007
1.357
3.6022
2
1.069
43.7381119
1.71
3.6021
3
1.068
52.0164407
2.063
3.6019
4
1.067
57.43723586
2.415
3.6018
5
1.0664
61.29900313
2.77
3.6016
6
1.0655
64.08102616
3.122
3.6015
7
1.0647
66.28404084
3.472
3.6013
8
1.0638
68.06297931
3.822
3.6011
9
1.0628
69.49734136
4.172
3.601
10
1.0619
70.68319948
5.7
3.6003
15
1.0218
74.68675856
7.292
3.5997
20
1.0258
78.15913105
10.466
3.5983
30
1.0151
80.86339729
4.36 Li-ion Charger
The built-in charger allows a Li-Ion battery to be charged from the power supplied by a
USB connection or by an AC adapter.
• Monitors for battery voltage, charge current, battery temperature feedback (NTC) and
chip temperature (programmable temperature limits).
• Maximum charge current 250 mA.
PNX0103
Rev. 01.14 — 22 January 2007
30 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
FT
FT
A
A
R
R
D
D
• Uses a widespread method to charge a Li-Ion battery with the following stages:
F
FT
FT
A
A
R
R
D
D
• The nominal charge current is programmed with an external program-resistor. This
allows the charge current to be adapted to the USB enumeration.
FT
FT
FT
FT
D
D
– Trickle charging with a small current for an (almost) empty battery.
R
A
FT
D
– Fast charging in Constant Current mode (CC-mode) to the maximum battery
voltage of 4.2 V +/- 1%.
R
• Short circuit resistant.
• Charger state can be observed through a register.
5. Ordering information
Table 6:
Ordering information
Type number
Package
Name
PNX0103ET/N1
Description
Version
TFBGA208 Plastic thin fine pitch ball grid array package, 208 balls, body 12 x 12 x 0.7mm SOT 930.1
6. Block diagram
Refer to Figure 1
7. Pinning information
Table 7:
Data sheet Pinning Table
BGA Pin Name
BGA Digital Application
Ball I/O
Function
level
[1]
Pin
Cell Type Description
State [2]
After
Reset
Clock Generation Unit
FFAST_IN
A10
SUP1
AI
AIO2
12 MHz oscillator clock input
FFAST_OUT
B10
SUP1
AO
AIO2
12 MHz oscillator clock output
VDDA12
B11
SUP1
Supply
PS3
12 MHz oscillator/PLLs Analog supply
VSSA12
C11
Ground
CG1
12 MHz oscillator/PLLs Analog ground
RSTIN_N
E15
SUP3
DI
DIO2
System Reset Input (active low)
ADC10B_VDDA33
B13
SUP3
Supply
PS3
10-bit ADC Analog Supply
ADC10B_GNDA
A13
Ground
CG1
10-bit ADC Analog Ground
ADC10B_GPA0
B12
SUP3
AI
AIO1
10-bit ADC Analog Input
ADC10B_GPA1
C13
SUP3
AI
AIO1
ADC10B_GPA2
C12
SUP3
AI
AIO1
I
10-bit ADC
Audio ADC
ADC_MIC
R15
AI
AIO2
ADC Microphone input
ADC_VINL
T15
AI
AIO2
ADC Line Input Left
PNX0103
Rev. 01.14 — 22 January 2007
31 of 50
A
– Switch from CC-mode to Constant Voltage charging (CV-mode) keeping the
battery voltage at 4.2 V and monitor the current for ending the charge process.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
R
ADC Line Input Right
ADC_TINL
P13
AI
AIO2
ADC Tuner Input Left
ADC_TINR
P14
AI
AIO2
ADC Tuner Input Right
ADC_VREF
T16
AO
AIO2
ADC Reference Voltage output
ADC_VREFN
R16
AI
AIO2
ADC Negative Reference Voltage
ADC_VREFP
T17
AI
AIO2
ADC Positive Reference Voltage
ADC_VDDA18
N15
SUP2
Supply
CS1
ADC Digital Voltage supply
ADC_VDDA33
N14
SUP3
Supply
CS1
ADC Analog Voltage supply
ADC_GNDA
N16
Ground
CG1
ADC Analog ground
A
AIO2
FT
D
R
A
Audio DAC
DAC_VDDA33
C14
SUP3
Supply
CS1
SDAC Analog supply
DAC_VREFP
F16
SUP3
AI
AIO2
SDAC Positive Reference Voltage
DAC_VREFN
F15
AI
AIO2
SDAC Negative Reference Voltage
HP_OUTC
D14
AO
AIO2
Headphone Common Output Reference
Class-AB
HP_FCL
C16
AI
AIO2
Headphone Filter Capacitor Left
HP_FCR
B15
AI
AIO2
Headphone Filter Capacitor Right
HP_VREF
E14
AI
AIO2
Analog Reference Supply For Headphone And
DAC
-
-
Reserved
Class AB amplifier
Reserved
Class-AB
HP_OUTL
B17
AO
AIO2
Headphone Left Output
HP_OUTR
C15
AO
AIO2
Headphone Right Output
HP_VDDA33
A16
Supply
CS1
Headphone Analog supply Class-AB
HP_GNDA
B16
Ground
CG1
Headphone Analog ground
SUP3
USB HS 2.0 OTG
USB_VBUS
N3
SUP5
AI
AIO3
USB supply detection line
USB_ID
P3
SUP3
AI
AIO1
Indicates to the USB transceiver whether in
device (USB_ID high) or host (USB_ID low)
mode (contains internal pull-up resistor)
USB_RREF
N4
SUP3
AIO
AIO1
USB Connection for external reference resistor
(12 kΩ +/- 1%) to analog ground supply
USB_DP
T1
SUP3
AIO
AIO1
USB D+ connection with integrated 45 Ohm
termination resistor
USB_DM
R1
SUP3
AIO
AIO1
USB D- connection with integrated 45 Ohm
termination resistor
USB_VDDA12_PLL
N2
SUP1
Supply
PS3
USB PLL supply
USB_VDDA33_DRV
T3
SUP3
Supply
PS3
USB Analog supply for driver
PNX0103
Rev. 01.14 — 22 January 2007
D
D
AI
-
F
D
D
R14
-
A
FT
FT
ADC_VINR
Reserved
R
R
A
A
Pin
State [2]
After
Reset
D
R
R
[1]
FT
D
D
Ball I/O
Function
level
A
FT
FT
A
A
R
R
R
BGA Pin Name
D
D
D
Table 7:
FT
FT
FT
FT
32 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
R
A
FT
FT
A
R
CG1
USB Analog ground for clean reference for on
chip termination resistors
DIO1
JTAG selection ARM
JTAG
I
TDI
T10
SUP3
DI / GPIO
I
DIO1
JTAG Data Input
TRST_N
U11
SUP3
DI / GPIO
I
DIO1
JTAG Reset Input
TCK
U12
SUP3
DI / GPIO
I
DIO1
JTAG Clock Input
TMS
U9
SUP3
DI / GPIO
I
DIO1
JTAG Mode Select Input
TDO
F14
SUP3
DO
Z
DIO2
JTAG Data output
mUART_CTS_N
P11
SUP3
DI / GPIO
I
DIO1
UART Clear To Send (active low)
mUART_RTS_N
R11
SUP3
DO / GPIO
O
DIO1
UART Ready To Send (active low)
UART_RXD
R10
SUP3
DI / GPIO
I
DIO1
UART Serial Input
UART_TXD
P10
SUP3
DO / GPIO
O
DIO1
UART Serial Output
UART
I2C master/slave interface
I2C_SDA0
C10
SUP3
DIO
I
IICD
I2C Data Line
I2C_SCL0
A9
SUP3
DIO
I
IICC
I2C Clock line
Serial Peripheral Interface
SPI_CS_OUT0
D8
SUP3
DO
O
DIO4
SPI Chip Select Output (Master)
SPI_SCK
C8
SUP3
DIO
I
DIO4
SPI Clock Input (Slave) / Clock Output
(Master)
SPI_MISO
A8
SUP3
DIO
I
DIO4
SPI Data Input (Master) / Data Output (Slave)
SPI_MOSI
B8
SUP3
DIO
I
DIO4
SPI Data Output (Master) / Data Input (Slave)
SPI_CS_IN
D9
SUP3
DI
I
DIO4
SPI Chip Select Input (Slave)
VDDI_0
J1
SUP1
Supply
CS2
Digital Core Supply
VDDI_1
U13
SUP1
Supply
CS2
Digital Core Supply
VDDI_2
A6
SUP1
Supply
CS2
Digital Core Supply
VDDI_3
M14
SUP2
Supply
CS2
Digital Core Supply
VSSI_0
H1
Ground
CG2
Digital Core Ground
VSSI_1
U14
Ground
CG2
Digital Core Ground
VSSI_2
A7
Ground
CG2
Digital Core Ground
VSSI_3
M15
Ground
CG2
Digital Core Ground
Digital power supply
Peripheral power supply
VDDE_0
D1
SUP4
Supply
PS1
Peripheral Supply NAND flash controller
VDDE_1
M1
SUP4
Supply
PS1
Peripheral Supply NAND flash controller
PNX0103
Rev. 01.14 — 22 January 2007
33 of 50
A
USB Analog ground
USB Analog ground for clean reference
R
CG1
CG1
D
Ground
Ground
FT
T2
A
Ground
DI / GPIO
D
D
USB Analog supply for PHY
P2
SUP3
F
R
R
PS3
USB_VSSA_REF
U10
A
D
D
Supply
USB_GNDA
JTAGSEL_ARM
R
D
FT
FT
Pin
State [2]
After
Reset
D
FT
A
A
R2
R
R
USB_VSSA_TERM
SUP3
D
D
R3
FT
FT
[1]
A
A
A
Ball I/O
Function
level
USB_VDDA33
R
R
R
BGA Pin Name
D
D
D
Table 7:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
D
D
SUP8
Supply
PS1
Peripheral Supply LCD Interface / SDRAM
interface
VDDE_4
U15
SUP3
Supply
PS1
Peripheral Supply
VDDE_5
A15
SUP3
Supply
PS1
Peripheral Supply
VDDE_6
A4
SUP3
Supply
PS1
Peripheral Supply
VDDE_7
G15
SUP3
Supply
PS2
Peripheral Supply
VSSE_0
E1
Ground
PG1
Peripheral Ground NAND flash controller
VSSE_1
N1
Ground
PG1
Peripheral Ground NAND flash controller
VSSE_2
K1
Ground
PG1
Peripheral Ground LCD Interface / SDRAM
interface
VSSE_3
U8
Ground
PG1
Peripheral Ground LCD Interface / SDRAM
interface
VSSE_4
U16
Ground
PG1
Peripheral Ground
VSSE_5
A14
Ground
PG1
Peripheral Ground
VSSE_6
A5
Ground
PG1
Peripheral Ground
VSSE_7
L14
Ground
PG1
Peripheral Ground
LCD Interface
mLCD_CSB
R8
SUP8
DO
O
DIO4
LCD Chip Select (active low)
mLCD_E_RD
P7
SUP8
DO
O
DIO4
LCD, 6800 Enable, 8080 Read Enable (active
high)
mLCD_RS
R7
SUP8
DO
O
DIO4
LCD, Instruction Register ('low')/ Data Register
('high') select
mLCD_RW_WR
T8
SUP8
DO
O
DIO4
LCD, 6800 Read/write Select,8080 Write
Enable (active high)
mLCD_DB_0
T7
SUP8
DIO
O
DIO4
LCD Data 0
mLCD_DB_1
P8
SUP8
DIO
O
DIO4
LCD Data 1
mLCD_DB_2
T6
SUP8
DIO
O
DIO4
LCD Data 2
mLCD_DB_3
R6
SUP8
DIO
O
DIO4
LCD Data 3
mLCD_DB_4
U6
SUP8
DIO
O
DIO4
LCD Data 4
mLCD_DB_5
P6
SUP8
DIO
O
DIO4
LCD Data 5
mLCD_DB_6
R5
SUP8
DIO
O
DIO4
LCD Data 6
mLCD_DB_7
T5
SUP8
DIO
O
DIO4
LCD Data 7
mLCD_DB_8
U5
SUP8
DIO
O
DIO4
LCD Data 8 / 8-bit Data 0
mLCD_DB_9
P5
SUP8
DIO
O
DIO4
mLCD_DB_10
P4
SUP8
DIO
O
DIO4
mLCD_DB_11
U4
SUP8
DIO
O
DIO4
mLCD_DB_12
T4
SUP8
DIO
O
DIO4
LCD Data 12 / 8-bit Data 4 / 4-bit Data 0
mLCD_DB_13
U3
SUP8
DIO
O
DIO4
LCD Data 13 / 8-bit Data 5 / 4-bit Data 1 /
Serial Clock Output
34 of 50
A
U7
R
VDDE_3
D
Peripheral Supply LCD Interface / SDRAM
interface
FT
PS1
A
Supply
R
SUP8
Rev. 01.14 — 22 January 2007
F
D
D
L1
A
FT
FT
VDDE_2
PNX0103
R
R
A
A
Pin
State [2]
After
Reset
D
R
R
[1]
FT
D
D
Ball I/O
Function
level
A
FT
FT
A
A
R
R
R
BGA Pin Name
D
D
D
Table 7:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
SUP8
DIO
O
DIO4
Serial Data Output
DAI_DATA0
P9
SUP3
DI / GPIO
I
DIO1
DAI Serial Data Input
DAI_BCK0
T9
SUP3
DIO / GPIO
I
DIO1
DAI Bitclock
DAI_WS0
R9
SUP3
DIO / GPIO
I
DIO1
DAI Word select
mDAO_DATA0
T13
SUP3
DO / GPIO
O
DIO1
DAO Serial Data Output
mDAO_BCK0
T12
SUP3
DO / GPIO
O
DIO1
DAO Bitclock
Digital Audio Input
Digital Audio Output
SUP3
DO / GPIO
O
DIO1
DAO Word select
SUP3
DO / GPIO
O
DIO1
DAO Serial Clock
General Purpose IO (IOConf module)
GPIO0
R13
SUP3
GPIO
I
DIO1
General Purpose IO Pin 0 (Mode pin 0)
GPIO1
T14
SUP3
GPIO
I
DIO1
General Purpose IO Pin 1 (Mode pin 1)
GPIO2
P12
SUP3
GPIO
I
DIO1
General Purpose IO Pin 2 ('blinking LED')
GPIO3
D12
SUP3
GPIO
I
DIO1
General Purpose IO Pin 3 (PSU_Stop)
GPIO4
D11
SUP3
GPIO
I
DIO1
General Purpose Input Pin 4
mGPIO5
D7
SUP3
GPIO
I
DIO4
General Purpose IO Pin 5
mGPIO6
B7
SUP3
GPIO
I
DIO4
mGPIO7
C7
SUP3
GPIO
I
DIO4
mGPIO8
D6
SUP3
GPIO
I
DIO4
mGPIO9
B6
SUP3
GPIO
I
DIO4
mGPIO10
C6
SUP3
GPIO
I
DIO4
External Bus Interface (NAND flash controller)
EBI_A_0_ALE
C4
SUP4
DO
O
DIO4
EBI Address Latch Enable
EBI_A_1_CLE
A2
SUP4
DO
O
DIO4
EBI Command Latch Enable
EBI_D_0
J3
SUP4
DIO
I
DIO4
EBI Data I/O 0
EBI_D_1
H3
SUP4
DIO
I
DIO4
EBI Data I/O 1
EBI_D_2
H4
SUP4
DIO
I
DIO4
EBI Data I/O 2
EBI_D_3
G4
SUP4
DIO
I
DIO4
EBI Data I/O 3
EBI_D_4
F4
SUP4
DIO
I
DIO4
EBI Data I/O 4
EBI_D_5
F3
SUP4
DIO
I
DIO4
EBI Data I/O 5
EBI_D_6
E4
SUP4
DIO
I
DIO4
EBI Data I/O 6
EBI_D_7
E3
SUP4
DIO
I
DIO4
EBI Data I/O 7
EBI_D_8
D3
SUP4
DIO
I
DIO4
EBI Data I/O 8
EBI_D_9
A3
SUP4
DIO
I
DIO4
EBI Data I/O 9
EBI_D_10
C2
SUP4
DIO
I
DIO4
EBI Data I/O 10
PNX0103
Rev. 01.14 — 22 January 2007
35 of 50
A
R4
R
mLCD_DB_15
D
Serial Data Input
FT
DIO4
A
O
R
DIO
R12
D
D
SUP8
T11
F
D
D
U2
mDAO_CLK0
A
FT
FT
mLCD_DB_14
mDAO_WS0
R
R
A
A
Pin
State [2]
After
Reset
D
R
R
[1]
FT
D
D
Ball I/O
Function
level
A
FT
FT
A
A
R
R
R
BGA Pin Name
D
D
D
Table 7:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
R
I
DIO4
EBI Data I/O 11
EBI_D_12
E2
SUP4
DIO
I
DIO4
EBI Data I/O 12
EBI_D_13
F2
SUP4
DIO
I
DIO4
EBI Data I/O 13
EBI_D_14
G2
SUP4
DIO
I
DIO4
EBI Data I/O 14
EBI_D_15
H2
SUP4
DIO
I
DIO4
EBI Data I/O 15
EBI_DQM_0_NOE
K3
SUP4
DO
O
DIO4
EBI Read Enable (active low)
EBI_NWE
K4
SUP4
DO
O
DIO4
EBI Write Enable (active low)
NAND_NCS_0
L2
SUP4
DO
O
DIO4
EBI Chip Enable 0
NAND_NCS_1
L3
SUP4
DO
O
DIO4
EBI Chip Enable 1
NAND_NCS_2
L4
SUP4
DO
O
DIO4
EBI Chip Enable 2
NAND_NCS_3
M2
SUP4
DO
O
DIO4
EBI Chip Enable 3
mNAND_RYBN0
B5
SUP4
DI
I
DIO4
EBI NAND Ready/Busy 0
mNAND_RYBN1
C5
SUP4
DI
I
DIO4
mNAND_RYBN2
D5
SUP4
DI
I
DIO4
mNAND_RYBN3
D4
SUP4
DI
I
DIO4
CLOCK_OUT
M4
SUP4
DO
O
DIO4
Clock Output
EBI_NCAS_BLOUT_0
J2
SUP4
DO
O
DIO4
EBI Lower lane byte select (7:0)
EBI_NRAS_BLOUT_1
J4
SUP4
DO
O
DIO4
EBI Upper lane byte select (15:8)
A
DIO
FT
D
R
A
Secure one time programmable memory
C9
SUP1/
SUP3
Supply
PS3
Supply for Polyfuse programming
RTC_VDD36
L15
SUP6
Supply
CS1
RTC Supply connected to Vbat
RTC_VSS
M17
Ground
CG1
RTC Ground
FSLOW_OUT
L16
SUP7
AO
AIO2
RTC 32.768 kHz Clock output
FSLOW_IN
L17
SUP7
AI
AIO2
RTC 32.768 kHz Clock input
RTC_INT
M16
SUP6
DO
AIO2
RTC interrupt (high active)
RTC_BACKUP
K14
SUP7
Supply
CS1
RTC backup capacitor connection
PSU_VBUS
J16
SUP5
Supply
CS1
PSU USB supply voltage
PSU_VOUT1
H14
SUP3
AO
CS1
PSU Output1
Real Time Clock
Power Supply Unit
PSU_LX1
H15
AIO
CS1
PSU External coil terminal for Output1
PSU_LX2
G17
AIO
CS1
PSU External coil terminal for Output2
PSU_VSS1
H16
Ground
CG1
PSU Ground
PSU_VIN1
G16
AI
CS1
PSU Output1 input voltage
PSU_VOUT2
G14
SUP1
AO
CS1
PSU Output2
PSU_VOUT3
E17
SUP2
AO
CS1
PSU Output3
PSU_VSSA
D16
Ground
CG1
PSU Ground
PSU_VSSA_CLEAN
D17
Ground
CG1
PSU Reference circuit ground
Rev. 01.14 — 22 January 2007
D
D
SUP4
PNX0103
F
D
D
D2
O
A
FT
FT
EBI_D_11
VPP[4]
R
R
A
A
Pin
State [2]
After
Reset
D
R
R
[1]
FT
D
D
Ball I/O
Function
level
A
FT
FT
A
A
R
R
R
BGA Pin Name
D
D
D
Table 7:
FT
FT
FT
FT
36 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
FT
FT
A
A
R
SUP3
AIO
I
AIO2
PSU Stop signal input (active high)
PSU_VBAT1
H17
SUP6
Supply
CS1
PSU DCDC1 supply Input
PSU_VBAT2
F17
SUP6
Supply
CS1
PSU DCDC2 supply Input
PSU_VBAT
E16
SUP6
Supply
CS1
PSU Li-Ion battery input
A
D15
R
PSU_STOP
D
PSU Play button input (active high)
FT
AIO2
A
I
R
AI
Li-Ion charger
CHARGE_VNTC
J17
AI
AIO2
Charger NTC connection
CHARGE_VSS
J15
Ground
CG1
Charger ground LiIon
CHARGE_CC_REF
K15
AO
CS1
Charger Constant Current reference
CHARGE_VBUS
J14
Supply
CS1
Charger 5 V supply
CHARGE_BAT_SENSE
K17
AI
AIO2
Charger battery sense terminal
CHARGE_VBAT
K16
AO
CS1
Charger positive battery terminal connection
Reserved
Reserved
-
-
-
-
-
Reserved
Reserved
-
-
-
-
-
Reserved
Reserved
-
-
-
-
-
Reserved
Reserved
-
-
-
-
-
Reserved
Reserved
-
-
-
-
-
Reserved
DO / GPIO
O
DIO1
PWM Output
Pulse Width Modulation module
PWM_DATA
D10
SUP3
[1]
Digital IO levels are explained in Section 4.16
[2]
Cell types are explained in Table 9
[3]
The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if
these balls are not required for UART flow control, they can also be selected to be used for an alternative
function: SPI chip select signals (SPI_CS_OUT1 and SPI_CS_OUT2)
[4]
The poly-fuses get burned if the VPP is connected before the VDD is connected. Voltage needs to be at
least 2.3 V. When unintended writing is done via the VPP, this will program fuses at random. This will
destroy the sample, it can be locked (security) and the AES-keys can be corrupted.
PNX0103
Rev. 01.14 — 22 January 2007
D
D
SUP3
SUP6
F
D
D
C17
Reserved
A
FT
FT
PSU_PLAY
SUP5
R
R
A
A
Pin
State [2]
After
Reset
D
R
R
[1]
FT
D
D
Ball I/O
Function
level
A
FT
FT
A
A
R
R
R
BGA Pin Name
D
D
D
Table 7:
FT
FT
FT
FT
37 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
R
A
Fig 14. Pinning information
PNX0103
Rev. 01.14 — 22 January 2007
38 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
A
FT
SUP4
1.8 or 2.8
VDDE_0, VDDE_1
Peripheral supply for NAND flash interface
SUP5
4.5 – 5.5
PSU_VBUS, CHARGE_VBUS
USB VBUS voltage
SUP6
3.2 – 4.2
RTC_VDD36, PSU_VBAT1,
PSU_VBAT2, PSU_VBAT
Li-Ion Battery voltage
SUP7
1.8
RTC_BACKUP
Real Time Clock voltage domain (generated
internally from SUP6)
SUP8
2.8
VDDE_2, VDDE_3
Peripheral supply for SDRAM/LCD
D
Peripheral supply
R
A
Note: When the SDRAM is used, the supply voltage of the NAND flash, SDRAM and the LCD Interface
must be the same.
Cell Types
Cell name [1] Library Name [1] Function
Description
DIO1
bspts3chp
Digital Input/Output
Bi-directional Cell 3.3 V; Scan-able 3state Output; 3 ns Slew Rate
Control; SSO=16; Plain Input; CMOS with Hysteresis;
Programmable Pull Up, Pull Down, Repeater
DIO2
bpts5pcph
Bi-directional Pad; Plain Input; 3state Output; SSO control; CMOS
with Programmable Hysteresis; Programmable Pull Up, Pull
Down, Repeater
DIO3
bpts5pcph1v8
Bi-directional 1.8 V Pad; Plain Input; 3state Output; SSO control;
CMOS with Programmable Hysteresis; Programmable Pull Up,
Pull Down, Repeater
DIO4
mem1
bsptz40pchp
Bi-directional 1.8 V Pad; Plain Input; 3state Output; SSO control;
CMOS with Programmable Hysteresis; Programmable Pull Up,
Pull Down, Repeater
IICC
iic3m4scl
IIC Cell; Clock Signal; cell based ESD protection
IICD
iic3mvsda
IIC Cell; Data Signal; cell based ESD protection
AIO1
apio3v3
Analog Input/Output Analog Cell; Analog Input Output; Protection to external 3.3 V
Supply Rail
AIO2
apio
Analog Input/Output Analog Pad; Analog Input Output
AIO3
apiot5v
Analog Input/Output Analog Cell; Analog Input Output; 5 V Tolerant Pad-based ESD
Protection
CS1
vddco
Core Supply
-
CS2
vddi
Core Supply
-
PS1
vdde3v3
Peripheral Supply
-
PS2
vdde
Peripheral Supply
-
Rev. 01.14 — 22 January 2007
F
FT
D
Digital core supply
VDDE_4, VDDE_5, VDDE_6,
VDDE_7 ADC10B_VDDA33,
ADC_VDDA33, DAC_VDDA33,
HP_VDDA33, USB_VDDA33_DRV,
USB_VDDA33, VPP
A
A
FT
VDDI_3, ADC_VDDA18
2.7 – 3.3
PNX0103
R
R
A
1.4 or 1.8
SUP3
Table 9:
D
D
R
SUP2
[1]
R
FT
VDDI_0, VDDI_1, VDDI_2, VDDA12, Digital core supply
HP_VDDA10, USB_VDDA12_PLL,
USB_VDDA12_BG, VPP
D
1.0 – 1.3
A
Description
FT
SUP1
A
Related supply pins
D
R
R
Typical Voltage
(V)
FT
D
D
Supply
Domain
A
FT
FT
A
A
R
R
R
Supply Domains
D
D
D
Table 8:
FT
FT
FT
FT
39 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
-
R
FT
FT
A
A
R
R
A
FT
Parameter
Conditions
Min
Typ
Max
Unit
VI
DC input voltage
range
-
-0.5
-
3.6
V
VO
DC output voltage
range
-
-0.5
-
3.6
V
IO
Output current
VDDE =3.3 V
-
4
-
mA
All Digital I/Os
Temperature values
Tj
Junction temperature
-
0
-
125
DegC
Tstg
Storage temperature
-
-40
-
+85
DegC
Tamb
Operating ambient
temperature
-
-15
25
70
DegC
VESD
HBM
-
-500
-
+500
V
-
MM
-
-100
-
+100
V
-
CDM
-
-
500
-
V
Electrostatic handling
9. Static characteristics
This chapter gives an overview of the most important static characteristics of the
PNX0103. More detailed specifications will be given in future versions of this document.
Table 11:
Supply Voltages
Symbol
Parameter
VDDE_0_1
Conditions
Min
Typ
Max
Unit
Peripheral (I/O) supply of the
NAND flash controller pads
1.65
3.3
3.6
V
VDDE_<2..3>
Peripheral (I/O) supply, SUP8 of
the LCD and SDRAM interface
2.7
3.3
3.6
V
VDDE_<4..6>
Peripheral supply, others of the
system
2.7
3.3
3.6
V
VDDE_7
Peripheral supply of the analog
die
2.7
3.3
3.6
V
VDDI_<0..2>
Core supply voltage
1.0
1.2
1.3
V
VDDI_3
Core supply voltage
1.3
1.4
1.95
V
PNX0103
Rev. 01.14 — 22 January 2007
40 of 50
A
Symbol
R
In accordance with Absolute Maximum Rating System (IEC 134)
D
The library name is the official name of the cell in the CMOS library. To increase readability, nicknames for
the cells have been created for this document. Throughout this document, the nickname is used to refer to
a certain cell type instead of its official name.
8. Limiting values
Table 10:
D
D
[1]
F
Peripheral Ground
A
vsse
R
PG1
D
-
R
Core Ground
D
vssis
FT
CG2
A
-
D
Core Ground
FT
vssco
A
CG1
D
R
R
Description
FT
D
D
Cell name [1] Library Name [1] Function
A
FT
FT
A
A
R
R
R
Cell Types
D
D
D
Table 9:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
1.3
ADC10B_VDDA33
Analog supply voltage for 10-bit
ADC
2.7
3.3
3.6
V
VPP_W
OTP (Poly fuses) program
voltage (write)
2.7
3.3
3.6
V
VPP_R
OTP (Pelvises) program voltage
(read)
1.1
1.3
V
USB_VBUS
USB VBUS
USB_VDDA12_BG
Analog supply USB HS device
(band gap)
1.1
1.2
1.3
V
USB_VDDA33
3.0
3.3
3.6
V
USB_VDDA33_DRV
(driver)
2.7
3.3
3.6
V
USB_VDDA12_PLL
Analog supply USB PLL
1.1
1.2
1.3
V
Min
Typ
Max
Unit
4.0
5
5.5
V
FT
FT
A
A
R
R
V
R
A
FT
PSU_VBAT
Battery input
2.7
3.7
4.2
V
VOUT1_VBAT
VOUT1 output voltage range when
generated from PSU_VBAT
(programmable in 8 levels)
2.4
2.8
3.2
V
DVOUT1_VBAT
Deviation of VOUT1_VBAT from its
nominal (programmed) setting
-100
-
+100
mV
VOUT1_VBUS
VOUT1 output voltage when
generated from PSU_VBUS
3.1
3.3
3.5
V
VOUT2_VBAT
VOUT2 output voltage range when
generated from PSU_VBAT
(programmable in 8 levels)
0.9
1.04
1.4
V
DVOUT2_VBAT
Deviation of VOUT2_VBAT from its
nominal (programmed) setting
-50
+50
mV
VOUT2_VBUS
VOUT2 output voltage when
generated from PSU_VBUS
(LDO_on)
1.15
1.2
1.25
V
VOUT3
Nominal VOUT3 voltage when
generated from either PSU_VBAT
or PSU_VBUS (programmable in 2
levels)
1.4
1.8
V
IVOUT1 (DCDC)
Current supplied by VOUT1 output
100
mA
IVOUT2 (DCDC)
100
mA
IVOUT3 (LDO)
50
mA
ηDCDC
Efficiency of the two inductive dc/dc
buck converters in the PSU
85
%
FCLK_u
DC/DC digital controller clock
frequency
12
MHz
PNX0103
Rev. 01.14 — 22 January 2007
41 of 50
A
USB VBUS input
Conditions
R
V
D
PSU_VBUS
D
D
5.0
Power Supply Unit Static Characteristics
Parameter
F
1.2
A
1.0
D
Analog supply voltage for 12 MHz
XTAL osc / PLL
Symbol
R
R
Unit
FT
Max
FT
Typ
D
A
A
R
R
D
D
D
Min
Table 12:
D
FT
FT
FT
VDDA_12
Conditions
A
A
A
Parameter
R
R
R
Supply Voltages …continued
Symbol
D
D
D
Table 11:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
A
FT
1.4
1.45
V
VOUT3 (1.8 V)
Output voltage LDO3 in case of
1.8 V
1.75
1.8
1.85
V
IVOUT3 (LDO)
Max Load current LDO3
50
mA
DC characteristics: 10-bits ADC
Symbol
Parameter
Min
Typ
Max
Unit
Vin
input voltage
ADC10B_
GNDA
-
ADC10B_
VDDA33
V
n
Resolution
2
-
10
bits
INL
Integral non-linearity
+/- 1
LSB
DNL
Differential non-linearity
+/- 1
LSB
OSe
Offset error
FSe
Full Scale error
-20
-
20
mV
USB
VICM(HS)
Input common mode level in High
Speed mode
-50
200
500
mV
VICM(FS/LS)
Input common mode level in Full
Speed/Low Speed mode
800
-
2500
mV
VICM (chirp)
Input common mode level in chirp
mode
-50
-
600
mV
VID
Differential input signal amplitude
100
400
1100
mV
Min
Typ
Max
Unit
Analog In - Electrical parameters DC characteristics
Symbol
Parameter
IDDA33_ADC
Analog supply current (pd=’0’) per
mono ADC
IDDA18_ADC
Analog supply current (pd=’0’) per
mono ADC
IREFAD_POS
IREFAD_NEG
Analog reference current per mono
ADC
20
uA
IDDA_SDC
Analog supply current (pd=’0’) fper
SDC
0.4
mA
IDDA_PGA
Analog supply current per PGA
430
uA
Gsys_PGA
Systematic gain for PGA
-1.94
dB
IDDA_BIAS
Analog positive supply current
(pd_bias=’0’ and
pd_vcom_vref=’0’) for BIAS
190+N*10
uA
Idd_lna
Supply current for LNA
2.2
20
0.85
PNX0103
mA
1.2
uA
mA
Rev. 01.14 — 22 January 2007
42 of 50
A
1.35
R
Output voltage LDO3 in case of
1.4 V (Default)
D
VOUT3 (1.4 V)
FT
mA
A
mA
100
R
250
80
N = 13 for all
modules on
D
D
200
Conditions
F
R
FT
MHz
Table 14:
A
D
A
1
IVOUT1 (LDO)
Conditions
R
FT
MHz
IVOUT2 (LDO)
Table 13:
R
A
12
R
10
D
R
8
Unit
D
Max
FT
D
Typ
FT
DC/DC1/2 switching frequency
Min
A
FSW
R
Ring oscillator frequency
D
Fosc psu
FT
FT
Conditions
A
A
A
Parameter
R
R
R
Power Supply Unit Static Characteristics …continued
Symbol
D
D
D
Table 12:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
FT
D
R
dB
Min
Typ
Max
Unit
IBATL_1
battery cc-charging current in high
current mode
@ Rext=1.00kΩ
95
100
105
mA
IBATL_2
battery cc-charging current in high
current mode
@ Rext=400Ω
237.5
250
262.5
mA
INO5V
battery load current due to charger
when 5 V is disconnected
Important
Reversed
current spec For
3.2 V Vbat. (@
no USB & 100k
to gnd)
3
mA
VTTRR
trickle charge threshold voltage
threshold when
battery voltage is
rising
2.8
V
VTTRF
trickle charge threshold voltage
threshold when
battery voltage is
falling
2.7
V
VTCVX
Maximum default battery setting
cs_bits at 0000
VTCV
cv-charge threshold voltage
After
compensation
cs_bits
VTRC
recharge threshold voltage
4.158
4.2
4.25
V
4.242
V
4.1
V
10. Dynamic characteristics
This chapter shows the audio performance characteristics of the PNX0103. A more
extensive list of dynamic characteristics will be given in future versions of this document.
Timing and Other Characteristics
Conditions
Min
Typ
Max
Unit
KS/s
10-bit ADC dynamic characteristics
Fsmpl
Sampling rate
400
(10 bits)
-
1500
(2 bits)
tconv
Conversion time
3(2 bits)
-
11(10 bits) clk
cycles
12MHz Oscillator (XTALH)
fosc
Oscillator frequency
-
12
-
MHz
aosc
Duty cycle
-
50
-
%
Cosc_in
Input capacitance
2
pF
PNX0103
Rev. 01.14 — 22 January 2007
43 of 50
A
24
Conditions
D
A
0
Parameter
Parameter
F
R
kΩ
Li-Ion Charger Electrical Characteristics
Symbol
A
D
11.25
Symbol
Table 16:
R
FT
Gain settings (Stepsize = 3 dB)
A
Gain_GA
R
Output resistance reference output
voltage (vref, vcom)
D
RREF, RCOM
dB
FT
32
FT
30
A
28
A
In a bandwidth
between 300Hz
and 5kHz.
R
Gain for LNA
Unit
D
A_lna
FT
Max
A
Typ
R
R
R
Min
D
D
D
Conditions
FT
FT
FT
Parameter
A
A
A
Symbol
Table 15:
R
R
R
Analog In - Electrical parameters DC characteristics
D
D
D
Table 14:
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
F
FT
A
A
D
R
pF
FT
FT
A
A
R
A
FT
µW
R
500
D
us
D
500
100
Unit
D
0.74
D
R
Max
FT
D
Crystal level of drive
Typ
FT
Pdrive
Min
A
Start-up time
R
tstart
D
Output capacitance
FT
FT
Cosc_out
Conditions
A
A
A
Parameter
R
R
R
Timing and Other Characteristics
Symbol
D
D
D
Table 16:
FT
FT
FT
FT
D
R
Dynamic Characteristics of Class AB amplifier at 3.3V
A
Table 17:
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vout
Output Voltage
HP unloaded
-
800
-
mVrms
Pout
Output power per channel
RL=16 Ω
(THD+N)/S
Total harmonic distortion plus noise at 0 dBFS, fin=1
to signal ratio (measured with
kHz, RL=16 Ω
20kHz block filter)
23.5
-60
at -60 dBFS, fin=1
kHz, RL=16 Ω
SNR
Signal-to-noise ratio (measured
with 20 kHz block filter)
PSRP
Power supply ripple rejection
X-Talk
Cross talk between left and right
channel
[1]
Table 18:
mW
dB
-40
-30
dBA
-
100
-
dBA
-
6
-
dB
RL=16 Ω
-55
dB
Tamb = 25 degree C; unless otherwise specified
Analog In - Electrical parameters AC characteristics
Symbol
Parameter
Conditions
B
Bandwidth
(THD+N)/S
THD+N@0dBFS; fin=1kHz
Tuner, Line input
level = 1 V, PGA
setting +12 dB,
external resistor
of 36 kΩ
-83
(THD+N)/S
THD+N@0dBFS; fin=1kHz
Tuner, Line input
level = 1 V, PGA
setting 0 dB
-70
(THD+N)/S
THD+N@-60dBFS; fin=1kHz;
A-weighted
Tuner, Line
imputatively =
1mV, PGA setting
0dB
-34
SNR
Signal-to-Noise Ratio; A-weighted
Tuner, Line
90
imputatively = 1 V,
PGA setting 0 dB
94
dBA
Zin
Input impedance line In/ Tuner
mode
12
kΩ
THD_mic
THDlna1
Vin mic =20 mV
fin=1kHz
-70
-60
dB
THD_mic2
THDlna2
Vin mic =0.3 mV
fin=1 kHz
-90
-80
dB
Zin_mic
Input impedance mic mode
PNX0103
Min
Typ
5
Max
Unit
20
kHz
-80
dB
dB
-30
dBA
kΩ
Rev. 01.14 — 22 January 2007
44 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
11. Marking
FT
FT
FT
FT
D
FT
D
D
PNX0103 Marking
R
BASIC_TYPE
A
PNX0103ET/N1
R
A
D
Description
FT
Marking
A
Line
PNX0103
FT
A
A
R
R
D
Table 19.
Rev. 01.14 — 22 January 2007
45 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
12. Package outline
FT
FT
FT
FT
D
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
R
A
Fig 15. Package outline
PNX0103
Rev. 01.14 — 22 January 2007
46 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
D
R
FT
FT
A
A
R
Stereo Analogue to Digital Converter for Audio
Clock Generation Unit
Class AB
Class AB headphone Amplifier
DAI
Digital Audio Input
DAO
Digital Audio Output
ECC
Error Correction Code
Event Router
Event Router
I2C M/S
Inter IC Communication Master / Slave Interface
INTC
Interrupt Controller
IOCONFIG
Input Output Configuration
IROM
Internal ROM Memory
ISRAM
Internal Static RAM Memory
JTAG
Joint Test Action Group
LCD Int.
Liquid Crystal Display interface
OTP
One-Time Programmable Memory
PHY
Physical Layer
PLL
Phase Locked Loop
PSU
Power Supply Unit
PWM
Pulse Width Modulation
RNG
Random Number Generator
RTC
Real Time Clock
SAI
Simple Audio Input
SAO
Simple Audio Output
SDAC
Stereo Digital to Analogue Converter
SDMA
Direct Memory Access Controller
SPI
Serial Peripheral Interface
Syscreg
System Control Registers
Timer
Timer module
UART
Universal Asynchronous Receiver Transmitter
A
CGU
R
Analogue Volume Control
D
ANVC
FT
Advanced Encryption Standard
A
10 Bit Analogue to Digital Converter
AES
R
ADC10B
USB 2.0 HS OTG Universal Serial Bus 2.0 High Speed on the Go
AHB to VPB Bridge
Watchdog Timer
PNX0103
D
ADC
D
Description
Watchdog
F
D
D
Acronym
VPB Bridge
A
FT
FT
A
A
R
R
R
Abbreviations
R
A
D
D
Table 20:
D
R
FT
FT
A
A
R
R
D
D
D
13. Abbreviations
FT
FT
FT
FT
Rev. 01.14 — 22 January 2007
47 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
R
F
FT
FT
A
A
A
D
Supersedes
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.05
PNX0103 Nexperia
Personal Audio IC,
version 01.07
11-04-2006
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.06
PNX0103 Nexperia
Personal Audio IC,
version 01.08
13-04-2006
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.07
PNX0103 Nexperia
Personal Audio IC,
version 01.09
19-04-2006
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.08
PNX0103 Nexperia
Personal Audio IC,
version 01.10
21-04-2006
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.09
PNX0103 Nexperia
Personal Audio IC,
version 01.11
25-04-2006
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.10
PNX0103 Nexperia
Personal Audio IC,
version 01.12
31-10-2006
Draft
PNX0103 Nexperia
Personal Audio IC,
version 01.11
PNX0103 Nexperia
Personal Audio IC,
version 01.13
11-12-2006
Update including
review comments.
PNX0103 Nexperia
Personal Audio IC,
version 01.12
PNX0103 Nexperia
Personal Audio IC,
version 01.14
22-01-2007
Update including
review comments.
PNX0103 Nexperia
Personal Audio IC,
version 01.13
R
A
D
48 of 50
FT
Rev. 01.14 — 22 January 2007
A
10-04-2006
R
PNX0103 Nexperia
Personal Audio IC,
version 01.06
D
Data sheet status
D
Release date
PNX0103
Doc. number
FT
Change notice
FT
A
A
R
R
D
Document ID
D
R
R
Revision history
R
A
D
D
Table 21:
D
R
FT
FT
A
A
R
R
D
D
D
14. Revision history
FT
FT
FT
FT
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
15.1 Data sheet status
A
FT
FT
A
A
R
R
D
D
D
15. Legal information
FT
FT
FT
FT
D
D
R
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
A
Definition
FT
D
R
A
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
MicroSoft — is a trademark of © 2007 Microsoft Corporation.
Nexperia — is a trademark of NXP B.V.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PNX0103
Rev. 01.14 — 22 January 2007
49 of 50
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
FT
D
R
R
A
A
A
A
R
R
D
D
D
NXP Semiconductors
FT
R
F
FT
FT
D
FT
FT
A
A
R
30
31
32
33
33
33
42
42
45
46
47
48
49
50
50
50
50
50
50
50
50
51
R
D
D
D
R
A
R
A
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 January 2007
Document identifier: PNX0103
FT
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
D
Real Time Clock. . . . . . . . . . . . . . . . . . . . . . .
Power Supply Unit . . . . . . . . . . . . . . . . . . . . .
Li-ion Charger . . . . . . . . . . . . . . . . . . . . . . . .
Ordering information . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning information . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Patents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
© NXP B.V. 2007.
A
A
A
4.23
4.24
4.25
4.26
4.26.1
4.26.2
4.26.3
4.27
4.28
4.29
4.30
4.30.1
4.30.2
4.31
4.32
4.33
4.34
4.35
4.36
5
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
15.5
15.6
16
17
D
R
R
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Features . . . . . . . . . . . . . . . . . . . . . . . 2
Hardware Features . . . . . . . . . . . . . . . . . . . . . . 3
Possible Software Features . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Product Summary . . . . . . . . . . . . . . . . . . . . . . . 5
ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . 5
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
NAND flash Controller . . . . . . . . . . . . . . . . . . . 6
MPMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal ROM Memory . . . . . . . . . . . . . . . . . . . 9
Internal RAM Memory. . . . . . . . . . . . . . . . . . . . 9
MCI (Memory Card Interface) . . . . . . . . . . . . . . 9
Universal Serial Bus 2.0
High Speed on the Go . . . . . . . . . . . . . . . . . . 10
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . 10
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 11
AHB Multi layer Bus . . . . . . . . . . . . . . . . . . . . 12
VPB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Generation Unit . . . . . . . . . . . . . . . . . . 14
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . 16
IO Configuration . . . . . . . . . . . . . . . . . . . . . . . 16
10 Bit Analog to Digital Converter. . . . . . . . . . 17
Event Router. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Random Number Generator . . . . . . . . . . . . . . 18
Secure One-Time Programmable Memory. . . 19
Serial Peripheral Interface . . . . . . . . . . . . . . . 19
Universal Asynchronous
Receiver Transmitter . . . . . . . . . . . . . . . . . . . 20
IP_INT Interface . . . . . . . . . . . . . . . . . . . . . . . 20
LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C Master / Slave Interface . . . . . . . . . . . . . . 21
LCD/NF/SDRAM Interface . . . . . . . . . . . . . . . 22
Pin connections . . . . . . . . . . . . . . . . . . . . . . . 22
Multiplexing between LCD and MPMC . . . . . . 23
Supply domains . . . . . . . . . . . . . . . . . . . . . . . 25
Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pulse Width Modulation Module . . . . . . . . . . . 26
System Control Registers . . . . . . . . . . . . . . . . 26
ADSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Digital Audio Input / Output. . . . . . . . . . . . . . . 27
Simple Audio Input / Output . . . . . . . . . . . . . . 27
Stereo Digital to Analog Converter . . . . . . . . . 28
Class AB Headphone Amplifier . . . . . . . . . . . 28
Stereo Analog to Digital Converter for Audio . 29
R
A
D
D
1
2
2.1
2.2
2.3
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
D
R
FT
FT
A
A
R
R
D
D
D
17. Contents
FT
FT
FT
FT