Febex Data Acquisition System

Transcription

Experiment-Elektronik
GSI, Darmstadt
(FPGA Hit Finder and Energy Filter for the FEBEX Pipelining ADC)
Dr. Ivan Rusanov for CSEE, GSI - Darmstadt
CSEE meeting, GSI – 24.02.2014., Darmstadt
The Febex Data AcquisitionSystem is developed in CS Experiment-Electronics Department of GSI. The main component of the system is a Febex board,
which has 16 differential analog inputs, 16 differential LVDS I/Os (max. 8 outputs) and four serial multi-gigabit connections to backplane (2 Gbits per s.) .
The interface, implemented in the Febex broad, is designed to work with Multi Branch System (MBS) data acquisition system. Through the MBS system,
via the optical interface, the user has full control over all components of Febex board: configuration, testing, start/stop of data acquisition, data readout and
data logging. The MBS runs under the operating systems Linux and LynxOS and supports various hardware setups. Therefore, for each user defined
hardware setup, the MBS data acquisition software requires user input data, describing the hardware setup and configuration parameters.
Development: Dr. Ivan Rusanov – CSEE; Jan Hoffmann - CSEE ; Dr. Nikolaus Kurz – CSEE; Dr. Shizu Minami - CSEE ; Dr. Wolfgang Ott – CSEE.
GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt
Dr. Ivan Rusanov for CSEE-GSI
GSI, Darmstadt
Febex Data Acquisition System: Features
1. Triggering:
2. „Self Triggering“:
Yes. Acquisition (physics / Trigger Type 1) and Synchronization (Trigger Type 3) Triggers.
Yes. For each channel are implemented two methods:
# „ Programmable Fast Trapezoidal Filter“ for a leading edge selection with 12-bit threshold.
# 3-Steps comparator for a leading edge selection.
3. Double Hit Detection:
Yes.
4. Energy measurement:
Yes. For each channel is implemented a „Programmable Energy Trapezoidal Filter“ for a measurement of hits‘ energy.
5. Trigger window (Traces Length):
Programmable (up to 8000 ADC’s samples/traces).
• 
Pre-Trigger Window:
Programmable (up to 2000 ADC’s samples/traces).
• 
Post-Trigger Window:
[Trigger_Window] – [Pre-Trigger_Window].
6. Slow Control and Data Acquisition :
via Optical Link.
• 
Access to Configuration Registers:
Read/Write address mode (single access via Optical Link).
# Configuration of Febex’s DAC:
via Optical Link and I2C bus.
# Configuration of ADCs:
via Optical Link and SPI bus I.
# Configuration of FPGA‘s flash:
via Optical Link and SPI bus II.
• 
Data Readout / Data Buffering:
Block Transfer mode (via Optical Link) / Double Readout Buffer (one per channel + one for energy measurements).
• 
Data Readout is programmable:
from each Febex board can be sent out:
# summary data packet (Chanel Id, Number of hits, Hit’s time and Energy data /2 words per channel //one per Febex)
and ADCs traces with or without data from Energy Trapezoidal Filter, in case more than one hit is found in a single channel.
# summary data packet and traces (up to 8000 ADC‘s samples/traces // one traces’ packet per channel).
# summary data packet, traces and data from Energy Trapezoidal Filter (up to 2000 ADC‘s samples/traces).
# only traces (up to 8000 ADC‘s samples/traces).
# only traces and data from Energy Trapezoidal Filter (up to 2000 ADC‘s samples/traces).
• 
Readout Data Reduction:
Yes and Programmable. The channels’ data is sent out only if hit is found (for summary and traces data packets).
7. Up to 1216 channels in 4 crates:
16 channels per Febex board // up to 19 Febex boards + one Interface card in one carte.
8. In the system can be used Febex boards with 12-bit/60 MHz (12-bit/50 MHz) or 14-bit/50 MHz ADCs (can be used „mixed” in one or different crates).
9. Each Febex Board can be programmed to operate with negative or positive input signals (can be used „mixed” in one crate or different crates).
GSI, Darmstadt
Febex Data Acquisition System (one example for 1216 channels)
Master
Slave 1
Trigger Module
ECL_IN
Trigger 3
(external)
ANY_IN
LVDS_OUT
ECL_OUT
ECL_OUT
LEMO_IN 3
LEMO_IN 3
LEMO_IN 1
LEMO_IN 6
TRIGGER 1
TRIGGER 2
4 SFPs / Slow Control and DATA Readout
Self Trigger 1/2
LEMO_OUT 6
LEMO_IN 6
TRIGGER 1
TRIGGER 2
Trigg&Clock Bus 1
Trigg&Clock Bus 2
LEMO_OUT 6
FEBEX Crate 1
PEXOR
LVDS_OUT
LEMO_IN 1
FEBEX Crate 2
Self Trigger
(internal)
Trigg&Clock Bus 1
Trigger 1
(external)
ANY_IN
In one Febex Crate:
Max 19 Febex Boards.
16 Diff. Inputs per Febex Board.
4 SFPs
Detector:
Coded Trigger
Differential Analog Signals
(up to 304 Channels per Crate)
ECL_OUT
Trigger Module
Trigg&Clock Bus 3
Trigg&Clock Bus 2
TRIXOR_Busy
FEBEX Crate 3
TRIXOR
FEBEX Crate 4
PC
GSI, Darmstadt
Algorithms for Energy or Fast TF, implemented in FPGA
„history“
„current“
N+M+1
2N+M
N
1
ADC samples
B_Window
A_Window
Gap (not used)
( „N“ ADC samples )
( „M“ ADC samples )
A1
Input
Length of TF = A_Window + Gap + B_Window
N
TF
i=1
=
Σ
2N+M
Ai -
i=1
Filter's equation
Σ
Bi
i = N+M+1
( „N“ ADC samples )
Delay
AN+1
Delay
BN+M+1
Delay
B2N+M+1
+
+
Σ
Σ
+
-
-
TF1
Σ
Σ
-
Output
Σ
+
+
+
+
Implementation in FPGA (Delays = Block RAMs)
GSI, Darmstadt
The testing in the Lab of the Febex Data Acquisition System (Energy TF) with Go4
FPGA: ADC Samples / Traces and Data from Energy Trapezoidal Filter.
Counts
Counts
Counts
Go4: Calculated (inspected) reaction of the Energy Trapezoidal Filter (from received traces).
Energy Filter
Start point
(Go4)
Signal / Traces
Energy Filter (Go4)
Signal / Traces
Energy Filter
End point
(Go4)
ADC Samples (Traces)
FPGA Energy Filter
Counts
Counts
Calc. Energy
(FPGA)
Energy Filter (FPGA)
Energy
Note: The calculated reaction of the ETF (in Go4) and the data of the ETF, implemented in FPGA, are the same!
GSI, Darmstadt
The testing in the Lab of the Febex Data Acquisition System (Energy TF) with Go4
Data from Energy Trapezoidal Filter and Calculated (inspected) reaction of the Energy Trapezoidal Filter (from received traces).
The positive input signal
Counts
Counts
The negative input signal
Note: The calculated reaction of the ETF (in Go4) and the data of the ETF, implemented in FPGA, are the same!
GSI, Darmstadt
Testing of the Febex Data Acquisition System (Fast TF – Hit finder) with Go4
ADC Counts
Double Hits’ Detection
The Summary Data Packet (Hit’s time and energy)
Signal / Traces
Counts
Fast Trapezoidal Filter (FPGA)
0xff050134 0x00000090
GOSIP Header // 2 words
0xaf1983b1
Summary Packet Header // 1 words
0x00000008 0x73a0f5d7
Epoch/Global Time Stamp // 2 words
0x00000000 0x00000000
Data for Channel Id 0 // 2 words (no input signal)
0x10000000 0x10000000
0x20000000 0x20000000
0x30000000 0x30000000
0x40000000 0x40000000
0x50000000 0x50000000
0x60000000 0x60000000
0x70000000 0x70000000
…………………………………………………………………………………………...
0x8a4081cf 0x8eeeeee2
Data for Channel Id 8 // 2 words
The first word:
0x8 (bits [31:28])
Channel Id
0xa (bits [27:24])
Hit counter for the Channel
0x4 (bits [23:20]):
Bit (23) = 0
always 0
Bit (22) = 1
Flag “More than one Hit in the Trigger Window”
Bit (21) = 0
Flag “Only one Hit in the Trigger Window, but not Full Filter Window”
Bit (20) = 0
Flag “Only one Hit in the Trigger Window”
0x0 (bits [19:16])
always 0x0
0x81cf (bits [15:0])
Relative Hit’s Time (to Global Time Stamp)// MSB is a “sign” bit
The second word
Channel Id and Measured Energy
…………………………………………………………………………………………...
0x9a4081cf 0x9eeeeee2
0xaa4081cf 0xaeeeeee2
0xba4081cf 0xbeeeeee2
0xca4081cf 0xceeeeee2
0xda4081cf 0xdeeeeee2
0xea4081cf 0xeeeeeee2
0xfa4081cf 0xeeeeeee2
…………………………………………………………………………………………...
0xbf1983b1
Summary Packet Trailer // 1 words
Note: Due to the Data Reduction, the words, marked in red, are not sent out – no found hits, no data for these channels in the summary packet!
GSI, Darmstadt
Febex Data Acquisition System (test setup)
Accepted Trigger
Febex Module
Trigger&Clock Bus
Self Triggers
Input Signal
Fiber Optic
Accepted Trigger
Exploder Module
Self Triggers
Input Signal
GSI, Darmstadt
Counts
ADC Counts
The testing in the Lab of the Febex Data Acquisition System (“Low Signal with Noise”) with Go4
Febex 3a / 14-bit / 50 MHz (FPGA‘s Energy Filter (ETF))
Counts
ADC Counts
Febex 3a / 14-bit / 50 MHz (ADC’s traces of Ch0 ... Ch15)
Febex 3a / 14-bit / 50 MHz (ADC’s trace of Ch_Id0: U ~ 2 mV)
Febex 3a / 14-bit / 50 MHz (FPGA‘s Hit’s Energy)
GSI, Darmstadt
60
The testing of the Febex Data Acquisition System with radioactive source Co
Energy Resolution
of 2.5 ... 2.7 keV
GSI, Darmstadt
DC-DC convertor with a “Murata Filter”: Energy’s RMS for different ETF’s filter Lengths
ETF Length 64-32-64
Counts
of Measured Energy
ETF Length 450-32-450
RMS
Counts
Counts
Counts
Counts
ETF Length 40-20-40
ETF Filter Length (A or B Windows)
Note: The "RMS" is growing up with the length of the Energy Trapezoidal Filter (ETF).
Note: The problem - the low frequency "noise". This "noise" cannot be removed with a ETF.
GSI, Darmstadt
The base line of the ETF for different ETF’s filter Lengths
The moving average filter and Signal’s baseline instability
Signal
ETF Counts
Frequency response of the moving average filter
(Steven W. Smith. Digital Signal Processing)
ETF Length 1
ETF Counts
“Energy Trapezoidal Filter”
ETF Length 64-32-64
ETF Length 2
Low Frequency signal: Baseline instability
Note: For each length the responses of the ETF filter will be different. The longer ETF filter is more sensitive to the baseline instability!
Note: When A_Window, B_Window = N, then the fluctuations of 1 LSB will produce differences from -N to +N!
Note: Main problem – Low Frequency noise! The low frequency components are dominating!
GSI, Darmstadt
New Method: “High Pas Filter with a Moving Accumulating Window” (HPF & MAccW)
Reconstruction of the Input Signal
(MAccW = 256 ADC samples)
ADC samples (Traces)
Measured Amplitude of the Input Signal
Counts
Counts
Counts
Amplitude in ADC counts
ADC Counts
ADC Counts
ADC Counts
GSI, Darmstadt
DC-DC convertor with a “Murata Filter”: Measurement of the Amplitudes of the Input Signals
(using the new method: HPF & MAccW)
Amplitude, mV
ADC Counts
Measured Amplitudes (ADC’s Counts)
Measured Amplitudes (50 mV ... 400 mV)
Amplitude of Input Signal, mV (Febex 3a / 14-bit / 50 MHz)
Note: The Febex’s ADC sees about 50 % from the amplitude of the input signal!
GSI, Darmstadt
That is all!
Tank you!

Febex Data Acquisition System

Transcription

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