Quartus II Settings File Reference Manual

Transcription

Quartus II Settings File Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-Q21005-5.0
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
MNL-Q21005-5.0
Contents
About This Reference Manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assignment Value Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About–1
About–1
About–1
About–2
About–2
About–5
Chapter 1. Project-Wide Assignments
AHDL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
AHDL_TEXT_DESIGN_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
ASM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
AUTO_EXPORT_VER_COMPATIBLE_DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
BDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
BINARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
BSF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
CDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
COMMAND_MACRO_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
CPP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
CPP_INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
CUSP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
C_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13
DEPENDENCY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
DSPBUILDER_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
EDIF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
ELA_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
ELF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
ENABLE_REDUCED_MEMORY_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
EQUATION_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20
FLOW_DISABLE_ASSEMBLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
FLOW_ENABLE_HC_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–22
FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23
FLOW_ENABLE_RTL_VIEWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24
FLOW_HARDCOPY_DESIGN_READINESS_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25
GDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
HC_OUTPUT_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27
HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–28
HEX_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–29
HTML_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–30
HTML_REPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31
INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32
IPA_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–33
IP_TOOL_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–34
IP_TOOL_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–35
ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–36
JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–37
JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–38
LICENSE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–39
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LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–40
LOGIC_ANALYZER_INTERFACE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–41
MAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–42
MESSAGE_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–43
MESSAGE_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–44
MESSAGE_SUPPRESSION_RULE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–45
MIF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–46
MIGRATION_DIFFERENT_SOURCE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
MISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–48
NUM_PARALLEL_PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–49
OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–50
OCP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–51
PARTIAL_SRAM_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–52
PIN_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–53
POWER_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
PPF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–55
PROGRAMMER_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–56
PROJECT_OUTPUT_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–57
PROJECT_SHOW_ENTITY_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–58
PROJECT_USE_SIMPLIFIED_NAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–59
QARLOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–60
QAR_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–61
QIP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62
QUARTUS_PTF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63
QUARTUS_SBD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–64
QUARTUS_STANDARD_DELAY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–65
QXP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–66
RAW_BINARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–67
READ_OR_WRITE_IN_BYTE_ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–68
RUN_FULL_COMPILE_ON_DEVICE_CHANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–69
SAVE_MIGRATION_INFO_DURING_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–70
SBI_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–71
SDC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–72
SDF_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–73
SERIAL_BITSTREAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–74
SIGNALTAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–75
SMART_RECOMPILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–76
SMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–77
SOFTWARE_LIBRARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–78
SRAM_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–79
SRECORDS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–80
SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–81
SYM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–82
SYSTEMVERILOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–83
TCL_SCRIPT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–84
TEMPLATE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–85
TEXT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–86
TEXT_FORMAT_REPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–87
TIMING_ANALYSIS_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–88
VCD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–89
VECTOR_TABLE_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–90
VECTOR_TEXT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–91
VECTOR_WAVEFORM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–92
VERILOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–93
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VERILOG_INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–94
VERILOG_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–95
VERILOG_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–96
VER_COMPATIBLE_DB_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–97
VHDL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–98
VHDL_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–99
VHDL_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–100
VQM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–101
ZIP_VECTOR_WAVEFORM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–102
Chapter 2. Pin & Location Assignments
APEX20K_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
APEX20K_LOCAL_ROUTING_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
FAST_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
FAST_OCT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
FAST_OUTPUT_ENABLE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
FAST_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
FLEX10K_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
FLEX6K_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
FLEX6K_LOCAL_ROUTING_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
IP_DEBUG_VISIBLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
MAX7K_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
MEMBER_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
MERCURY_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
PIN_CONNECT_FROM_NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
RESERVE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
SUBCLIQUE_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
USE_CLK_FOR_VIRTUAL_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
VIRTUAL_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Chapter 3. Assignment Group Assignments
ASSIGNMENT_GROUP_EXCEPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
ASSIGNMENT_GROUP_MEMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Chapter 4. Analysis & Synthesis Assignments
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
ADV_NETLIST_OPT_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
ADV_NETLIST_OPT_RETIME_CORE_AND_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
ADV_NETLIST_OPT_SYNTH_GATE_RETIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
ALLOW_POWER_UP_DONT_CARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
ALLOW_SYNCH_CTRL_USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
ALLOW_XOR_GATE_USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
APEX20K_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
APEX20K_TECHNOLOGY_MAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
AUTO_CARRY_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
AUTO_CASCADE_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
AUTO_CLOCK_ENABLE_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
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Contents
AUTO_DSP_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
AUTO_ENABLE_SMART_COMPILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
AUTO_GLOBAL_CLOCK_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
AUTO_GLOBAL_OE_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
AUTO_IMPLEMENT_IN_ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
AUTO_LCELL_INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
AUTO_OPEN_DRAIN_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
AUTO_PARALLEL_EXPANDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
AUTO_RAM_BLOCK_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
AUTO_RAM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42
AUTO_RAM_TO_LCELL_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–44
AUTO_RESOURCE_SHARING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45
AUTO_ROM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46
AUTO_SHIFT_REGISTER_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48
BLOCK_DESIGN_NAMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–50
CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51
CASCADE_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52
CLKLOCKX1_INPUT_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53
CYCLONEII_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55
CYCLONE_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57
DEVICE_FILTER_PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–58
DEVICE_FILTER_PIN_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59
DEVICE_FILTER_SPEED_GRADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–60
DEVICE_FILTER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61
DISABLE_OCP_HW_EVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62
DONT_MERGE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63
DQS_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–64
DQS_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65
DQS_SHIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66
DQS_SYSTEM_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–67
DSE_SYNTH_EXTRA_EFFORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–68
DSP_BLOCK_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–69
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–71
EDA_INPUT_DATA_FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–72
EDA_INPUT_GND_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–73
EDA_INPUT_VCC_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–74
EDA_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–75
EDA_RUN_TOOL_AUTOMATICALLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–76
EDA_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–77
EDA_VHDL_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–78
ENABLE_IP_DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–79
ENABLE_M512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–80
EXTRACT_VERILOG_STATE_MACHINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–81
EXTRACT_VHDL_STATE_MACHINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–82
FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–83
FLEX10K_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–84
FLEX10K_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–85
FLEX6K_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–87
FLEX6K_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–88
FORCE_SYNCH_CLEAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–89
HDL_INITIAL_FANOUT_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–91
HDL_MESSAGE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–92
HDL_MESSAGE_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–93
HDL_MESSAGE_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–94
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IGNORE_CARRY_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–95
IGNORE_CASCADE_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–96
IGNORE_GLOBAL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–97
IGNORE_LCELL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–98
IGNORE_MAX_FANOUT_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–100
IGNORE_ROW_GLOBAL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–102
IGNORE_SOFT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–103
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–105
IGNORE_VERILOG_INITIAL_CONSTRUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–106
IMPLEMENT_AS_CLOCK_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–107
IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–108
LCELL_INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–109
LIMIT_AHDL_INTEGERS_TO_32_BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–110
MAX7000_FANIN_PER_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–111
MAX7000_IGNORE_LCELL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–112
MAX7000_IGNORE_SOFT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–113
MAX7000_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–114
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–116
MAXII_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–117
MAX_AUTO_GLOBAL_REGISTER_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–118
MAX_BALANCING_DSP_BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–120
MAX_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–122
MAX_RAM_BLOCKS_M4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–124
MAX_RAM_BLOCKS_M512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–126
MAX_RAM_BLOCKS_MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–128
MERCURY_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–130
MERCURY_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–131
MUX_RESTRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–132
NOT_GATE_PUSH_BACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–134
NUMBER_OF_INVERTED_REGISTERS_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–135
NUMBER_OF_REMOVED_REGISTERS_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–136
OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–137
OPTIMIZE_POWER_DURING_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–138
PARALLEL_EXPANDER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–140
PARAMETER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–141
POWER_UP_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–142
PRESERVE_FANOUT_FREE_NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–143
PRESERVE_HIERARCHICAL_BOUNDARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–144
PRESERVE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–145
PRE_MAPPING_RESYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–146
REMOVE_DUPLICATE_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–147
REMOVE_REDUNDANT_LOGIC_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–148
RESYNTHESIS_OPTIMIZATION_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–150
RESYNTHESIS_PHYSICAL_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–151
RESYNTHESIS_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–152
SAFE_STATE_MACHINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–153
SAVE_DISK_SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–154
SEARCH_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–155
SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT . . . . . . . . . . . . . . . . . . . . . . 4–156
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES . . . . . . . . . . . . . . . . . . . . . . . 4–157
STATE_MACHINE_PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–158
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELEC
T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–160
STRATIXII_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–161
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STRATIXII_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–162
STRATIX_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–164
STRATIX_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–165
STRICT_RAM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–167
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–169
SYNTHESIS_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–171
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER . . . . . . . . . . . . . . . . 4–172
SYNTH_CLOCK_MUX_PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–173
SYNTH_CRITICAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–174
SYNTH_GATED_CLOCK_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–175
SYNTH_MESSAGE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–176
SYNTH_PROTECT_SDC_CONSTRAINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–177
SYNTH_TIMING_DRIVEN_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–178
TOP_LEVEL_ENTITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–179
TRUE_WYSIWYG_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–180
USER_LIBRARIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–181
USE_GENERATED_PHYSICAL_CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–182
USE_HIGH_SPEED_ADDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–183
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–184
VERILOG_CONSTANT_LOOP_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–185
VERILOG_INPUT_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–186
VERILOG_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–187
VERILOG_MACRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–188
VERILOG_NON_CONSTANT_LOOP_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–189
VERILOG_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–190
VHDL_INPUT_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–191
VHDL_INPUT_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–192
VHDL_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–193
VHDL_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–194
Chapter 5. Incremental Compilation Assignments
AUTO_EXPORT_INCREMENTAL_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
INCREMENTAL_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
INCREMENTAL_COMPILATION_EXPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
INCREMENTAL_COMPILATION_EXPORT_ROUTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
PARTITION_FITTER_PRESERVATION_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
PARTITION_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
PARTITION_IMPORT_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
PARTITION_IMPORT_EXISTING_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
PARTITION_IMPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
PARTITION_IMPORT_PROMOTE_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
PARTITION_LAST_IMPORTED_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
PARTITION_NETLIST_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Chapter 6. Fitter Assignments
ACTIVE_SERIAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER . . . . . . . . . . . . . . 6–2
ALWAYS_ENABLE_INPUT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
APEX20KE_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
APEX20K_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
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APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
APEX20K_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
APEXII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
APEXII_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
ASYNC_PIPELINE_REG_REACH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
AUTO_DELAY_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
AUTO_GLOBAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
AUTO_GLOBAL_MEMORY_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
AUTO_GLOBAL_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
AUTO_GLOBAL_REGISTER_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
AUTO_MERGE_PLLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
AUTO_PACKED_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
AUTO_PACKED_REGISTERS_CYCLONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
AUTO_PACKED_REGISTERS_MAXII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
AUTO_PACKED_REGISTERS_STRATIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26
AUTO_PACKED_REGISTERS_STRATIXII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
AUTO_TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–30
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–31
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES . . . . . . . . . . . . . . . . 6–32
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS . . . . . . . . . . . . . . . . . . . . 6–33
BLOCK_RAM_TO_MLAB_CELL_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–34
CARRY_OUT_PINS_LCELL_INSERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
CKN_CK_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36
CLOCK_ENABLE_ROUTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
CLOCK_TO_OUTPUT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
CONFIGURATION_VCCIO_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–39
CRC_ERROR_CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–40
CRC_ERROR_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41
CURRENT_STRENGTH_NEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–42
CYCLONEIII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–43
CYCLONEII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–44
CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–45
CYCLONEII_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46
CYCLONE_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
D1_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–48
D2_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–49
D3_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–50
D4_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–51
D5_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–52
D5_OCT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–53
D6_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54
D6_OCT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–55
DATA0_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–56
DCLK_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–57
DC_CURRENT_FOR_ELECTROMIGRATION_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–58
DDIO_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59
DDIO_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–60
DDIO_OUTPUT_REGISTER_DISTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–61
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–62
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63
DELAY_SETTING_FROM_VIO_TO_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–64
DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–65
DEVICE_MIGRATION_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–66
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DEVICE_TECHNOLOGY_MIGRATION_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67
DPRIO_CHANNEL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–68
DPRIO_CRUCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–69
DPRIO_INTERFACE_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–70
DPRIO_QUAD_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–71
DPRIO_QUAD_PLL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72
DPRIO_TX_PLL0_REFCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–73
DPRIO_TX_PLL1_REFCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–74
DPRIO_TX_PLL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–75
DQSB_DQS_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–76
DQSOUT_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77
DQS_ENABLE_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–78
DQS_LOCAL_CLOCK_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–79
DQ_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–80
DQ_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–81
DUAL_PURPOSE_CLOCK_PIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–82
DUPLICATE_ATOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–83
DYNAMIC_OCT_CONTROL_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–84
ECO_ALLOW_ROUTING_CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–85
ECO_OPTIMIZE_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86
ECO_REGENERATE_REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–87
ENABLE_ASMI_FOR_FLASH_LOADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–88
ENABLE_BENEFICIAL_SKEW_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–89
ENABLE_BUS_HOLD_CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–90
ENABLE_DEVICE_WIDE_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
ENABLE_DEVICE_WIDE_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–94
ENABLE_HOLD_BACK_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–96
ENABLE_INIT_DONE_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97
ENABLE_JTAG_BST_SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–99
ENABLE_VREFA_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–100
ENABLE_VREFB_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–101
ERROR_CHECK_FREQUENCY_DIVISOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–102
FASTROW_INTERCONNECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–103
FINAL_PLACEMENT_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–106
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–108
FITTER_EARLY_TIMING_ESTIMATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–109
FITTER_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–110
FIT_ATTEMPTS_TO_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–111
FIT_ONLY_ONE_ATTEMPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112
FLEX10K_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–113
FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–114
FLEX10K_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–115
FLEX10K_ENABLE_LOCK_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
FLEX10K_MAX_PERIPHERAL_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–117
FLEX6K_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–118
FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–119
FLEX6K_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120
FORCE_CONFIGURATION_VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–121
FORCE_MERGE_PLL_FANOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–122
GENERATE_GXB_RECONFIG_MIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–123
GENERATE_GXB_RECONFIG_MIF_WITH_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–124
GLOBAL_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
GNDIO_CURRENT_1PT8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–126
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GNDIO_CURRENT_2PT5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–127
GNDIO_CURRENT_GTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–128
GNDIO_CURRENT_GTL_PLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129
GNDIO_CURRENT_LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–130
GNDIO_CURRENT_LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–131
GNDIO_CURRENT_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–132
GNDIO_CURRENT_SSTL2_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–133
GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–137
GXB_0PPM_CLOCK_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–138
GXB_0PPM_CLOCK_GROUP_DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–139
GXB_0PPM_CORE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140
GXB_CLOCK_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–141
GXB_CLOCK_GROUP_DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–142
GXB_RECONFIG_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–143
GXB_RECONFIG_MIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–144
GXB_RECONFIG_MIF_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–145
GXB_REFCLK_COUPLING_TERMINATION_SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–146
GXB_TX_PLL_RECONFIG_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–147
IGNORE_MODE_FOR_MERGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–148
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–149
INCREASE_DELAY_TO_OUTPUT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–150
INCREASE_INPUT_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–151
INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–152
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–153
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–154
INCREASE_TZX_DELAY_TO_OUTPUT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–155
INC_PLC_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–156
INPUT_REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–157
INPUT_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158
INSERT_ADDITIONAL_LOGIC_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–159
IO_MAXIMUM_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
IO_PLACEMENT_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–161
IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–162
LVDS_RX_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–164
MAX7000B_VCCIO_IOBANK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–165
MAX7000B_VCCIO_IOBANK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MAX7000_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–167
MAX7000_ENABLE_JTAG_BST_SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–168
MAX7000_INDIVIDUAL_TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–169
MAX_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–170
MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–171
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . 6–172
MAX_CURRENT_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–173
MAX_CURRENT_FOR_VIO_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MAX_GLOBAL_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–175
MAX_PERIPHERY_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–176
MAX_REGIONAL_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–177
MEMORY_INTERFACE_DATA_PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–178
MERCURY_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–179
MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180
MERCURY_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–181
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MIGRATION_CONSTRAIN_CORE_RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–182
MIGRATION_DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–183
NDQS_LOCAL_CLOCK_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
NORMAL_LCELL_INSERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–185
OPTIMIZE_FOR_METASTABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–186
OPTIMIZE_HOLD_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–187
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–188
OPTIMIZE_MULTI_CORNER_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–189
OPTIMIZE_POWER_DURING_FITTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–190
OPTIMIZE_SIGNAL_INTEGRITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–191
OPTIMIZE_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–192
OUTPUT_BUFFER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–194
OUTPUT_BUFFER_DELAY_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–195
OUTPUT_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–196
OUTPUT_ENABLE_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197
OUTPUT_ENABLE_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–199
OUTPUT_ENABLE_ROUTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–200
OUTPUT_PIN_LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201
OUTPUT_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–202
OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–203
PAD_TO_CORE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–204
PAD_TO_DDIO_REGISTER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205
PAD_TO_INPUT_REGISTER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–206
PCI_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–207
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING . . . . . . . . . . . . . . . . . . . . . . . 6–209
PHYSICAL_SYNTHESIS_COMBO_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–211
PHYSICAL_SYNTHESIS_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–212
PHYSICAL_SYNTHESIS_LOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–213
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA . . . . . . . . . . . . . . . . . . . . . . . . 6–214
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–215
PHYSICAL_SYNTHESIS_REGISTER_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–216
PLACEMENT_EFFORT_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–217
PLL_COMPENSATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–219
PLL_FORCE_OUTPUT_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–220
PLL_IGNORE_MIGRATION_DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–221
PRESERVE_PLL_COUNTER_ORDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–222
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES . 6–223
PROGRAMMABLE_POWER_TECHNOLOGY_SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–224
PROGRAMMABLE_PREEMPHASIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–225
PROGRAMMABLE_VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–226
QDR_D_PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227
RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–228
RESERVE_ALL_UNUSED_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–229
RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231
RESERVE_ASDO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–232
RESERVE_DATA0_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–233
RESERVE_DATA1_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–234
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 6–235
RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 6–237
RESERVE_DCLK_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–238
RESERVE_FLASH_NCE_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–239
RESERVE_NCEO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–240
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–241
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RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–242
RESERVE_RDYNBUSY_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–243
ROUTER_EFFORT_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–244
ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–246
ROUTER_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–247
ROUTER_TIMING_OPTIMIZATION_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248
ROUTING_BACK_ANNOTATION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–250
ROW_GLOBAL_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–251
SAVE_INTERMEDIATE_FITTING_RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–252
SCE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–253
SDO_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–254
SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–255
SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–256
SLOW_SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–257
STOP_AFTER_CONGESTION_MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–259
STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET . . . . . . . . . . . . . . . . . . . . . . . . 6–260
STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . 6–261
STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE . . . . . . . . . . . . . . . . . . . . . . . . 6–262
STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–263
STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER . . . . . . . . . . 6–264
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE . . . . . . . . . 6–265
STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . 6–266
STRATIXGX_ALLOW_POST8B10B_LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–267
STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–268
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_
WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–269
STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–270
STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . 6–271
STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER . . . . . . . . . 6–272
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE . . . . . . . . . 6–273
STRATIXGX_TERMINATION_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–274
STRATIXIIGX_TERMINATION_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–275
STRATIXIII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–276
STRATIXIII_MRAM_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–277
STRATIXIII_UPDATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–278
STRATIXII_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–279
STRATIXII_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280
STRATIX_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–281
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–282
STRATIX_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–283
STRATIX_UPDATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–284
SYNCHRONIZER_IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–285
SYNCHRONIZER_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–287
SYNCHRONOUS_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–288
T11_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–289
T4_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–290
T8_DELAY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–291
T8_DELAY1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–293
TERMINATION_CONTROL_BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–294
TREAT_BIDIR_AS_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–295
TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–296
USER_START_UP_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297
VCCIO_CURRENT_1PT8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–299
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VCCIO_CURRENT_2PT5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–300
VCCIO_CURRENT_GTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301
VCCIO_CURRENT_GTL_PLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–302
VCCIO_CURRENT_LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–303
VCCIO_CURRENT_LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–304
VCCIO_CURRENT_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–305
VCCIO_CURRENT_SSTL2_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–306
VCCPD_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–310
WEAK_PULL_UP_RESISTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–311
XSTL_INPUT_ALLOW_SE_BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–313
Chapter 7. Power Estimation Assignments
POWER_AUTO_COMPUTE_TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
POWER_BOARD_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
POWER_BOARD_THERMAL_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
POWER_DEFAULT_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
POWER_HSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
POWER_HSSI_LEFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
POWER_HSSI_RIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
POWER_HSSI_VCCHIP_LEFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
POWER_HSSI_VCCHIP_RIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11
POWER_INPUT_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
POWER_INPUT_FILE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13
POWER_INPUT_SAF_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14
POWER_INPUT_VCD_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15
POWER_OCS_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16
POWER_OJB_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17
POWER_OSA_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18
POWER_OUTPUT_SAF_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19
POWER_PRESET_COOLING_SOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20
POWER_READ_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21
POWER_REPORT_POWER_DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22
POWER_REPORT_SIGNAL_ACTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–23
POWER_SIGNAL_ACTIVITY_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24
POWER_SIGNAL_ACTIVITY_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25
POWER_STATIC_PROBABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26
POWER_TJ_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27
POWER_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–28
POWER_TOGGLE_RATE_PERCENTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29
POWER_USE_CUSTOM_COOLING_SOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–30
POWER_USE_DEVICE_CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–31
POWER_USE_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32
POWER_USE_INPUT_FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–33
POWER_USE_PVA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34
POWER_USE_TA_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35
POWER_VCCA_L_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36
POWER_VCCA_R_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37
POWER_VCCH_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38
POWER_VCCH_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39
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POWER_VCCH_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–40
POWER_VCCIO_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41
POWER_VCCL_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42
POWER_VCD_FILE_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43
POWER_VCD_FILE_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44
POWER_VCD_FILTER_GLITCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–45
VCCA_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46
VCCA_PLL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–47
VCCA_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48
VCCA_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49
VCCD_PLL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–50
VCCD_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–51
VCCHIP_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52
VCCHIP_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–53
VCCH_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54
VCCH_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–55
VCCH_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–56
VCCINT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–57
VCCIO_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–58
VCCL_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–59
VCCL_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–60
VCCL_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–61
VCCL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–62
VCCPT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–63
VCCR_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–64
VCCR_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–65
VCCT_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–66
VCCT_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–67
VCC_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–68
Chapter 8. EDA Netlist Writer Assignments
EDA_BOARD_BOUNDARY_SCAN_OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
EDA_BOARD_DESIGN_SYMBOL_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
EDA_BOARD_DESIGN_TIMING_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
EDA_BOARD_DESIGN_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
EDA_DESIGN_INSTANCE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
EDA_ENABLE_GLITCH_FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
EDA_FLATTEN_BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
EDA_FORMAL_VERIFICATION_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12
EDA_FV_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
EDA_GENERATE_FUNCTIONAL_NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
EDA_GENERATE_POWER_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
EDA_GENERATE_TIMING_CLOSURE_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16
EDA_IBIS_MODEL_SELECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
EDA_IBIS_MUTUAL_COUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18
EDA_IPFS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19
EDA_LAUNCH_CMD_LINE_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20
EDA_MAINTAIN_DESIGN_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–21
EDA_MAP_ILLEGAL_CHARACTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23
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EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–24
EDA_NATIVELINK_SIMULATION_TEST_BENCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25
EDA_NETLIST_WRITER_OUTPUT_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26
EDA_RESYNTHESIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27
EDA_RTL_SIMULATION_RUN_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–28
EDA_RTL_SIM_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–29
EDA_RTL_TEST_BENCH_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–30
EDA_RTL_TEST_BENCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31
EDA_RTL_TEST_BENCH_RUN_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–32
EDA_SDC_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED . . . . . . . . . . . . . 8–34
EDA_SIMULATION_RUN_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–35
EDA_SIMULATION_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–37
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–39
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–40
EDA_TEST_BENCH_ENABLE_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–41
EDA_TEST_BENCH_ENTITY_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–43
EDA_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–44
EDA_TEST_BENCH_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–45
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–46
EDA_TEST_BENCH_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–47
EDA_TEST_BENCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–48
EDA_TEST_BENCH_RUN_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–49
EDA_TEST_BENCH_RUN_SIM_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–50
EDA_TIME_SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–51
EDA_TIMING_ANALYSIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–52
EDA_TRUNCATE_LONG_HIERARCHY_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–53
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–54
EDA_VHDL_ARCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–55
EDA_WAIT_FOR_GUI_TOOL_COMPLETION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–56
EDA_WRITER_DONT_WRITE_TOP_ENTITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–57
EDA_WRITE_DEVICE_CONTROL_PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–58
EDA_WRITE_NODES_FOR_POWER_ESTIMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–59
Chapter 9. Assembler Assignments
APEX20K_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
APEX20K_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
AUTO_RESTART_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
CLOCK_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
COMPRESSION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
CONFIGURATION_CLOCK_DIVISOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9
CONFIGURATION_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
CYCLONEIII_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
CYCLONEII_M4K_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
CYCLONE_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15
ENABLE_OCT_DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16
EPROM_USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17
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Contents
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FLEX10K_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19
FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE . . . . . . . . . . . . . . . . . . . . . . . 9–20
FLEX10K_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21
FLEX6K_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22
FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . 9–23
GENERATE_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24
GENERATE_RBF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25
GENERATE_TTF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–26
HARDCOPYII_POWER_ON_EXTRA_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–27
HEXOUT_FILE_COUNT_DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28
HEXOUT_FILE_START_ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29
MAX7000S_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–30
MAX7000_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–31
MAX7000_USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–32
MERCURY_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–33
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–34
MERCURY_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–35
ON_CHIP_BITSTREAM_DECOMPRESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–36
RELEASE_CLEARS_BEFORE_TRI_STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–37
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–39
SECURITY_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–40
STRATIXII_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–41
STRATIXII_MRAM_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–42
STRATIX_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–43
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–44
STRATIX_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–45
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT . . . . . . . . . . . . . . . . . . . . . 9–46
USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–47
USE_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–49
Chapter 10. Simulator Assignments
ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . 10–2
ADD_TO_SIMULATION_OUTPUT_WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4
AUTO_USE_SIMULATION_PDB_NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
BREAKPOINT_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6
CHECK_OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7
END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–8
EXTERNAL_PIN_CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–9
GLITCH_DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–10
GLITCH_INTERVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–11
IMMEDIATE_ASSERTION_FAIL_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–12
IMMEDIATE_ASSERTION_FAIL_MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–13
IMMEDIATE_ASSERTION_PASS_MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–14
IMMEDIATE_ASSERTION_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–15
IMMEDIATE_ASSERTION_TEST_CONDITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–16
INCREMENTAL_VECTOR_INPUT_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–17
PASSIVE_RESISTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–18
SETUP_HOLD_DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–19
SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED . . . . . . . . . . . . . . . . . 10–20
SETUP_HOLD_TIME_VIOLATION_DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–21
SIMULATION_BUS_CHANNEL_GROUPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–22
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Contents
SIMULATION_CELL_DELAY_MODEL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–23
SIMULATION_COMPARE_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–24
SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–25
SIMULATION_COVERAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–26
SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–27
SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–28
SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL . . . . . . . . . . . . . . . . . . . . . . . . 10–29
SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL . . . . . . . . . . . . . . . . . . . . . . . . 10–30
SIMULATION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–31
SIMULATION_NETLIST_VIEWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32
SIMULATION_SIGNAL_COMPARE_TOLERANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–33
SIMULATION_VDB_RESULT_FLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–34
SIMULATION_VECTOR_COMPARE_BEGIN_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–35
SIMULATION_VECTOR_COMPARE_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–36
SIMULATION_VECTOR_COMPARE_RULE_FOR_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–37
SIMULATION_VECTOR_COMPARE_RULE_FOR_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–38
SIMULATION_VECTOR_COMPARE_RULE_FOR_DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–39
SIMULATION_VECTOR_COMPARE_RULE_FOR_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40
SIMULATION_VECTOR_COMPARE_RULE_FOR_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–41
SIMULATION_VECTOR_COMPARE_RULE_FOR_U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–42
SIMULATION_VECTOR_COMPARE_RULE_FOR_W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–43
SIMULATION_VECTOR_COMPARE_RULE_FOR_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–44
SIMULATION_VECTOR_COMPARE_RULE_FOR_Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–45
SIMULATION_WITH_AUTO_GLITCH_FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–46
SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . 10–47
SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF . . . . . . . . . . . . . . . . . . 10–48
SIMULATOR_GENERATE_POWERPLAY_VCD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–49
SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–50
SIMULATOR_POWERPLAY_VCD_FILE_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–51
SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION . . . . . . . . . . . . . . . . . . . . . . . . 10–52
SIMULATOR_POWERPLAY_VCD_FILE_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–53
SIMULATOR_PVT_TIMING_MODEL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–54
SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–55
SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION . . . . . . . . . . . . . . . . . . . . . . . . 10–56
SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–57
SIM_BEHAVIOR_SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–58
SIM_COMPILE_HDL_FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–59
SIM_HDL_TOP_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–60
SIM_OVERWRITE_WAVEFORM_INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–61
SIM_TAP_REGISTER_D_Q_PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–62
SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–63
SIM_VECTOR_COMPARED_CLOCK_OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–64
SIM_VECTOR_COMPARED_CLOCK_PERIOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–66
TRIGGER_EQUATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–67
TRIGGER_VECTOR_COMPARE_ON_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–68
USER_MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–69
VECTOR_COMPARE_TRIGGER_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–70
VECTOR_INPUT_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–71
VECTOR_OUTPUT_DESTINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–72
VECTOR_OUTPUT_FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–73
X_ON_VIOLATION_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–74
Chapter 11. Design Assistant Assignments
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ACLK_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
ACLK_RULE_IMSZER_ADOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
ACLK_RULE_NO_SZER_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
ACLK_RULE_SZER_BTW_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4
CLK_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5
CLK_RULE_CLKNET_CLKSPINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7
CLK_RULE_COMB_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8
CLK_RULE_GATED_CLK_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–9
CLK_RULE_GATING_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10
CLK_RULE_INPINS_CLKNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11
CLK_RULE_INV_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–12
CLK_RULE_MIX_EDGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13
DA_CUSTOM_RULE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–14
DISABLE_DA_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–15
DRC_DEADLOCK_STATE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–16
DRC_DETAIL_MESSAGE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–17
DRC_FANOUT_EXCEEDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–18
DRC_GATED_CLOCK_FEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–19
DRC_REPORT_FANOUT_EXCEEDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–20
DRC_REPORT_TOP_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–21
DRC_TOP_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–22
DRC_VIOLATION_MESSAGE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–23
ENABLE_DA_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–24
ENABLE_DRC_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–25
FSM_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–26
FSM_RULE_DEADLOCK_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–27
FSM_RULE_NO_RESET_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–28
FSM_RULE_NO_SZER_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–29
FSM_RULE_UNREACHABLE_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–30
FSM_RULE_UNUSED_TRANSITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–31
HARDCOPY_FLOW_AUTOMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–32
HARDCOPY_NEW_PROJECT_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–33
HCPY_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–34
HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–35
HCPY_VREF_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–36
NONSYNCHSTRUCT_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–37
NONSYNCHSTRUCT_RULE_ASYN_RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–38
NONSYNCHSTRUCT_RULE_COMBLOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–39
NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–40
NONSYNCHSTRUCT_RULE_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–41
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–42
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–43
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–44
NONSYNCHSTRUCT_RULE_REG_LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–45
NONSYNCHSTRUCT_RULE_RIPPLE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–46
NONSYNCHSTRUCT_RULE_SRLATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–47
RESET_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–48
RESET_RULE_COMB_ASYNCH_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–49
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–50
RESET_RULE_IMSYNCH_EXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–51
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–52
RESET_RULE_UNSYNCH_EXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–53
SIGNALRACE_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–54
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SIGNALRACE_RULE_CLK_PORT_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–55
SIGNALRACE_RULE_RESET_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–56
SIGNALRACE_RULE_SECOND_SIGNAL_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–57
SIGNALRACE_RULE_TRISTATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–58
TIMING_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–59
Chapter 12. Programmer Assignments
EXCALIBUR_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1
GENERATE_CONFIG_HEXOUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2
GENERATE_CONFIG_ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3
GENERATE_CONFIG_JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4
GENERATE_CONFIG_JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5
GENERATE_CONFIG_JBC_FILE_COMPRESSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6
GENERATE_CONFIG_SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7
GENERATE_ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–8
GENERATE_JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–9
GENERATE_JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–11
GENERATE_JBC_FILE_COMPRESSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–13
GENERATE_SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–15
ISP_CLAMP_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–17
ISP_CLAMP_STATE_DEFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–18
MERGE_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–19
Chapter 13. SignalProbe Assignments
SIGNALPROBE_ALLOW_OVERUSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1
SIGNALPROBE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
SIGNALPROBE_DURING_NORMAL_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3
SIGNALPROBE_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4
SIGNALPROBE_NUM_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5
SIGNALPROBE_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6
Chapter 14. SignalTap II Assignments
ENABLE_LOGIC_ANALYZER_INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1
ENABLE_SIGNALTAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–2
STP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3
USE_LOGIC_ANALYZER_INTERFACE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4
USE_SIGNALTAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–5
Chapter 15. LogicLock Region Assignments
LL_AUTO_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1
LL_ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–2
LL_EXCLUDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–3
LL_HEIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–4
LL_IMPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–5
LL_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–7
LL_MEMBER_EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–8
LL_MEMBER_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–9
LL_MEMBER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–10
LL_MEMBER_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–11
LL_NODE_LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–12
LL_ORIGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–13
LL_PARENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–14
LL_PATH_EXCLUDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–15
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LL_PRIORITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–16
LL_RCF_IMPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–17
LL_RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–18
LL_RESERVED_IS_LIMITED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–19
LL_ROOT_REGION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–20
LL_SOFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–21
LL_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–22
LL_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–23
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–24
LOGICLOCK_INCREMENTAL_COMPILE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–25
Chapter 16. Migration Assignments
MIGRATION_AUTO_PACKED_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1
MIGRATION_AUTO_PORT_SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–2
MIGRATION_RAM_INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3
Chapter 17. Netlist Viewer Assignments
RTLV_GROUP_COMB_LOGIC_IN_CLOUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1
RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–2
RTLV_GROUP_RELATED_NODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–3
RTLV_GROUP_RELATED_NODES_TMV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–4
RTLV_REMOVE_FANOUT_FREE_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–5
RTLV_SIMPLIFIED_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–6
Chapter 18. Advanced I/O Timing Assignments
BOARD_MODEL_FAR_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–1
BOARD_MODEL_FAR_DIFFERENTIAL_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–2
BOARD_MODEL_FAR_PULLDOWN_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–3
BOARD_MODEL_FAR_PULLUP_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–4
BOARD_MODEL_FAR_SERIES_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–5
BOARD_MODEL_NEAR_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–6
BOARD_MODEL_NEAR_DIFFERENTIAL_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–7
BOARD_MODEL_NEAR_PULLDOWN_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–8
BOARD_MODEL_NEAR_PULLUP_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–9
BOARD_MODEL_NEAR_SERIES_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–10
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–11
BOARD_MODEL_NEAR_TLINE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–12
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–13
BOARD_MODEL_TERMINATION_V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–14
BOARD_MODEL_TLINE_C_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–15
BOARD_MODEL_TLINE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–16
BOARD_MODEL_TLINE_L_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–17
ENABLE_ADVANCED_IO_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–18
OUTPUT_IO_TIMING_ENDPOINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–19
PCB_LAYER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–20
PCB_LAYERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–21
PCB_LAYER_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–22
Chapter 19. Classic Timing Assignments
ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–1
BASED_ON_CLOCK_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–2
CLOCK_ENABLE_MULTICYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–3
CLOCK_ENABLE_MULTICYCLE_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–4
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CLOCK_ENABLE_SOURCE_MULTICYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–5
CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–6
CLOCK_HOLD_UNCERTAINTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–7
CLOCK_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–8
CLOCK_SETUP_UNCERTAINTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–9
CUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–10
CUT_OFF_IO_PIN_FEEDBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–12
CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–13
CUT_OFF_READ_DURING_WRITE_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–14
DEFAULT_HOLD_MULTICYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–15
DIVIDE_BASE_CLOCK_PERIOD_BY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–16
DO_COMBINED_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–17
DO_MIN_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–18
DO_MIN_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–19
DUTY_CYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–20
EARLY_CLOCK_LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–21
ENABLE_CLOCK_LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–22
ENABLE_RECOVERY_REMOVAL_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–23
EXCLUDE_FMAX_PATHS_GREATER_THAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–24
EXCLUDE_SLACK_PATHS_GREATER_THAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–25
EXCLUDE_TCO_PATHS_LESS_THAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–26
EXCLUDE_TH_PATHS_LESS_THAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–27
EXCLUDE_TPD_PATHS_LESS_THAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–28
EXCLUDE_TSU_PATHS_LESS_THAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–29
FLOW_ENABLE_TIMING_CONSTRAINT_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–30
FMAX_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–31
HOLD_RELATIONSHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–32
IGNORE_CLOCK_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–33
INPUT_MAX_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–34
INPUT_MIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–35
INPUT_TRANSITION_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–36
INVERTED_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–37
INVERT_BASE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–38
LATE_CLOCK_LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–39
LVDS_FIXED_CLOCK_DATA_PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–40
MAX_CLOCK_ARRIVAL_SKEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–41
MAX_DATA_ARRIVAL_SKEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–42
MAX_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–43
MINIMUM_TPD_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–44
MIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–45
MIN_TCO_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–46
MULTICYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–47
MULTICYCLE_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–49
MULTIPLY_BASE_CLOCK_PERIOD_BY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–51
NOMINAL_CORE_SUPPLY_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–52
NOT_A_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–53
NUMBER_OF_DESTINATION_TO_REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–54
NUMBER_OF_PATHS_TO_REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–55
NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–56
OFFSET_FROM_BASE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–57
OUTPUT_MAX_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–58
OUTPUT_MIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–59
PHASE_FROM_BASE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–60
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–61
© November 2008
Altera Corporation
Contents
xxiii
REPORT_AS_DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–62
REPORT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–63
REPORT_IO_PATHS_SEPARATELY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–64
SETUP_RELATIONSHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–65
SOURCE_MULTICYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–66
SOURCE_MULTICYCLE_HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–68
TAO_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–70
TCO_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–71
TH_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–72
TIMEQUEST_DO_CCPP_REMOVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–73
TIMEQUEST_DO_REPORT_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–75
TIMEQUEST_MULTICORNER_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–76
TIMEQUEST_REPORT_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–78
TPD_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–79
TSU_REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–80
USE_TIMEQUEST_TIMING_ANALYZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–81
VIRTUAL_CLOCK_REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–83
© November 2008
Altera Corporation
xxiv
Contents
© November 2008
Altera Corporation
Introduction
The Quartus® II design software settings are made in the Quartus II Settings File
(QSF).
Revision History
The following table shows the revision history for this manual.
Date and
Document Version
November 2008, v5.0
Changes Made
Summary of Changes
—
■
Updated for Quartus II version 8.1
■
Undated new document template
■
Updated "Revision History" section
September 2008, v4.2
■
Minor editorial updates
—
September 2008, v4.1
■
Minor editorial updates
—
July 2008, v4.0
■
—
December 2007, v3.0
■
—
How to Contact Altera
For the most up-to-date information about Altera® products, see the following table.
Contact (Note 1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Product Literature
Website
www.altera.com/literature
Altera literature services
Email
[email protected]
(General)
Email
[email protected]
(Software Licensing)
Email
[email protected]
Non-technical support
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
© November 2008
Altera Corporation
About–2
Typographic Conventions
Visual Cue
Meaning
Bold Type with Initial Capital
Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names, file
names, file name extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file,
such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.
■ ■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
A caution calls attention to a condition or possible situation that can damage or
destroy the product or the user’s work.
w
A warning calls attention to a condition or possible situation that can cause injury to
the user.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
© November 2008
Altera Corporation
Assignment Value Syntax
About–3
There are rules for using certain characters in assignment values to ensure the value is
legal. An unquoted value with only alphabetic, numeric, underscore (_), period (.) or
forward slash (/) characters is legal. A value containing any of the following
characters must be enclosed in double quotation marks (" ") to be legal.
<tab> <space> { } ( ) ; : , < >= - # "
In addition, values containing any of the following characters must escape the
character with a backslash:
{}$"\
For example, the following values are legal:
■
“EPF10K10LC84-3”
■
MODE1
■
“ModelSim (VHDL output from Quartus II)”
Although it is not required, you can also enclose assignments containing only legal
characters in double quotation marks.
Assignment Types
Each Quartus II assignment has a required type that identifies legal values for the
assignment. This section describes the types and lists some examples of legal values.
bool
An assignment with type bool requires a boolean value of ON or OFF. Boolean
arguments are not case-sensitive. For example, ON, On, oN, and on are all legal.
int
An assignment with type int requires an integer value. The value must be an integer,
such as 1. Some assignment definitions may list a range of legal integers.
string
An assignment with type string requires an argument that is a string. If the string
contains any illegal characters, you must enclose the entire string argument in double
quotation marks.
filename
An assignment with type filename requires a value that is the name of a file. You can
specify directory separators with the forward slash character (/) or back slash
characters (\). For example, the following values are legal:
■
simulation/output.vho
■
“c:\design\top.edf”
All filename assignment values are case sensitive.
© November 2008
Altera Corporation
About–4
time
An assignment with type time requires a value that is a time. A time value consists of
a numeric value and text representing units of duration. The numeric value can
include a decimal point, and the numeric value and units of duration can be separated
by a single space. For example, the following values are legal:
■
“1 ps”
■
“-2ns”
■
10.0µs
Table About–1 shows abbreviations for units of time.
Table About–1. Abbreviations for Units of Time
Time Unit
s
Description
second(s)
ms
millisecond(s)
µs
microsecond(s)
ns
nanosecond(s)
ps
picosecond(s)
fs
femtosecond(s)
Hz
hertz
kHz
kilohertz
MHz
megahertz
GHz
gigahertz
enum
An assignment with type enum requires an value from the enumerated list included
with the assignment definition. Only values in the list are legal.
location
An assignment with type location requires a value that defines a physical resource
location in a device. For example, the following values are legal in certain devices:
■
LC_X1_Y20_N0
■
LAB_X1_Y1
■
M4K_X17_Y12
frequency
An assignment with type frequency requires a value that is a frequency. A frequency
value consists of a numeric value and text representing units of frequency. The
numeric value can include a decimal point, and the numeric value and units of
frequency can be separated by a single space. For example, the following values are
legal:
■
“50.5 MHz”
■
10kHz
© November 2008
Altera Corporation
Overview
About–5
Overview
Benefits of Command-Line Operation & Tcl Scripting Support
Each stage of the Quartus II software design flow corresponds to a command-line
executable file. Many of these executable files also support industry-standard Tcl
scripting for custom functionality or processing beyond the GUI design flow.
Quartus II design software offers the following scripting support benefits, also known
as CAR:
■
Custom Analysis
■
Automation
■
Reproducibility
Custom analysis allows you to build test procedures into the script and change design
processing based on the test results. Scripts can automate design flows to perform on
multiple computers simultaneously and easily archive and restore projects.
Reproducibility ensures that scripts use the same project setup and assignments for
every compile, even when you transfer a project from one engineer to another. In
other words, you can use scripts as another level of design quality assurance.
© November 2008
Altera Corporation
About–6
Overview
© November 2008
Altera Corporation
1. Project-Wide Assignments
AHDL_FILE
No description is available.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case-sensitive
Syntax
set_global_assignment -name AHDL_FILE <value>
© November 2008
Altera Corporation
1–2
Project-Wide Assignments
AHDL_TEXT_DESIGN_OUTPUT_FILE
AHDL_TEXT_DESIGN_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name AHDL_TEXT_DESIGN_OUTPUT_FILE <value>
© November 2008
Altera Corporation
ASM_FILE
1–3
ASM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name ASM_FILE <value>
© November 2008
Altera Corporation
1–4
AUTO_EXPORT_VER_COMPATIBLE_DB
AUTO_EXPORT_VER_COMPATIBLE_DB
Type
Boolean
Device Support
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB <value>
Default Value
Off
© November 2008
Altera Corporation
BDF_FILE
1–5
BDF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name BDF_FILE <value>
© November 2008
Altera Corporation
1–6
BINARY_FILE
BINARY_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name BINARY_FILE <value>
© November 2008
Altera Corporation
BSF_FILE
1–7
BSF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name BSF_FILE <value>
© November 2008
Altera Corporation
1–8
CDF_FILE
CDF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name CDF_FILE <value>
© November 2008
Altera Corporation
COMMAND_MACRO_FILE
1–9
COMMAND_MACRO_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name COMMAND_MACRO_FILE <value>
© November 2008
Altera Corporation
1–10
CPP_FILE
CPP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name CPP_FILE <value>
© November 2008
Altera Corporation
CPP_INCLUDE_FILE
1–11
CPP_INCLUDE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name CPP_INCLUDE_FILE <value>
© November 2008
Altera Corporation
1–12
CUSP_FILE
CUSP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name CUSP_FILE <value>
© November 2008
Altera Corporation
C_FILE
1–13
C_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name C_FILE <value>
© November 2008
Altera Corporation
1–14
DEPENDENCY_FILE
DEPENDENCY_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name DEPENDENCY_FILE <value>
© November 2008
Altera Corporation
DSPBUILDER_FILE
1–15
DSPBUILDER_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name DSPBUILDER_FILE <value>
© November 2008
Altera Corporation
1–16
EDIF_FILE
EDIF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDIF_FILE <value>
© November 2008
Altera Corporation
ELA_FILE
1–17
ELA_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name ELA_FILE <value>
© November 2008
Altera Corporation
1–18
ELF_FILE
ELF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name ELF_FILE <value>
© November 2008
Altera Corporation
ENABLE_REDUCED_MEMORY_MODE
1–19
ENABLE_REDUCED_MEMORY_MODE
Type
Boolean
Device Support
Syntax
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE <value>
Default Value
Off
© November 2008
Altera Corporation
1–20
EQUATION_FILE
EQUATION_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EQUATION_FILE <value>
© November 2008
Altera Corporation
FLOW_DISABLE_ASSEMBLER
1–21
FLOW_DISABLE_ASSEMBLER
Type
Boolean
Device Support
Syntax
set_global_assignment -name FLOW_DISABLE_ASSEMBLER <value>
Default Value
Off
© November 2008
Altera Corporation
1–22
FLOW_ENABLE_HC_COMPARE
FLOW_ENABLE_HC_COMPARE
Type
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■
HardCopy II
■
HardCopy III
Syntax
set_global_assignment -name FLOW_ENABLE_HC_COMPARE <value>
Default Value
Off
© November 2008
Altera Corporation
FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
1–23
FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
Type
Boolean
Device Support
Syntax
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS <value>
Default Value
Off
© November 2008
Altera Corporation
1–24
FLOW_ENABLE_RTL_VIEWER
FLOW_ENABLE_RTL_VIEWER
Type
Boolean
Device Support
Syntax
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER <value>
Default Value
Off
© November 2008
Altera Corporation
FLOW_HARDCOPY_DESIGN_READINESS_CHECK
1–25
FLOW_HARDCOPY_DESIGN_READINESS_CHECK
Type
Boolean
Device Support
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix III
Notes
Syntax
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK <value>
Default Value
On
© November 2008
Altera Corporation
1–26
GDF_FILE
GDF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name GDF_FILE <value>
© November 2008
Altera Corporation
HC_OUTPUT_DIR
1–27
HC_OUTPUT_DIR
Type
File name
Device Support
■
HardCopy II
■
HardCopy III
Notes
Syntax
set_global_assignment -name HC_OUTPUT_DIR <value>
Default Value
hc_output
© November 2008
Altera Corporation
1–28
HEX_FILE
HEX_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name HEX_FILE <value>
© November 2008
Altera Corporation
HEX_OUTPUT_FILE
1–29
HEX_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name HEX_OUTPUT_FILE <value>
© November 2008
Altera Corporation
1–30
HTML_FILE
HTML_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name HTML_FILE <value>
© November 2008
Altera Corporation
HTML_REPORT_FILE
1–31
HTML_REPORT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name HTML_REPORT_FILE <value>
© November 2008
Altera Corporation
1–32
INCLUDE_FILE
INCLUDE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name INCLUDE_FILE <value>
© November 2008
Altera Corporation
IPA_FILE
1–33
IPA_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name IPA_FILE <value>
© November 2008
Altera Corporation
1–34
IP_TOOL_NAME
IP_TOOL_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name IP_TOOL_NAME <value>
© November 2008
Altera Corporation
IP_TOOL_VERSION
1–35
IP_TOOL_VERSION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name IP_TOOL_VERSION <value>
© November 2008
Altera Corporation
1–36
ISC_FILE
ISC_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name ISC_FILE <value>
© November 2008
Altera Corporation
JAM_FILE
1–37
JAM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name JAM_FILE <value>
© November 2008
Altera Corporation
1–38
JBC_FILE
JBC_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name JBC_FILE <value>
© November 2008
Altera Corporation
LICENSE_FILE
1–39
LICENSE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name LICENSE_FILE <value>
© November 2008
Altera Corporation
1–40
LMF_FILE
LMF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name LMF_FILE <value>
© November 2008
Altera Corporation
LOGIC_ANALYZER_INTERFACE_FILE
1–41
LOGIC_ANALYZER_INTERFACE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name LOGIC_ANALYZER_INTERFACE_FILE <value>
© November 2008
Altera Corporation
1–42
MAP_FILE
MAP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name MAP_FILE <value>
© November 2008
Altera Corporation
MESSAGE_DISABLE
1–43
MESSAGE_DISABLE
Tells the compiler to suppress the specified user message(s).
Type
Integer
Device Support
Syntax
set_global_assignment -name MESSAGE_DISABLE <value>
set_global_assignment -name MESSAGE_DISABLE -entity <entity name> <value>
set_instance_assignment -name MESSAGE_DISABLE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
1–44
MESSAGE_ENABLE
MESSAGE_ENABLE
Tells the compiler to enable the specified user message(s).
Type
Integer
Device Support
Syntax
set_global_assignment -name MESSAGE_ENABLE <value>
set_global_assignment -name MESSAGE_ENABLE -entity <entity name> <value>
set_instance_assignment -name MESSAGE_ENABLE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
MESSAGE_SUPPRESSION_RULE_FILE
1–45
MESSAGE_SUPPRESSION_RULE_FILE
Type
File name
Device Support
Notes
The name of this file is based on the project revision name.
Syntax
set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE <value>
© November 2008
Altera Corporation
1–46
MIF_FILE
MIF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name MIF_FILE <value>
© November 2008
Altera Corporation
MIGRATION_DIFFERENT_SOURCE_FILE
1–47
MIGRATION_DIFFERENT_SOURCE_FILE
Type
File name
Device Support
■
HardCopy II
■
HardCopy III
■
Stratix II
Notes
Syntax
set_global_assignment -name MIGRATION_DIFFERENT_SOURCE_FILE <value>
© November 2008
Altera Corporation
1–48
MISC_FILE
MISC_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name MISC_FILE <value>
© November 2008
Altera Corporation
NUM_PARALLEL_PROCESSORS
1–49
NUM_PARALLEL_PROCESSORS
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy III
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name NUM_PARALLEL_PROCESSORS <value>
Old Names
This variable also has the following name(s) in some earlier versions of the Quartus II software:
MAX_PROCESSORS_USED_FOR_MULTITHREADING
© November 2008
Altera Corporation
1–50
OBJECT_FILE
OBJECT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name OBJECT_FILE <value>
© November 2008
Altera Corporation
OCP_FILE
1–51
OCP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name OCP_FILE <value>
© November 2008
Altera Corporation
1–52
PARTIAL_SRAM_OBJECT_FILE
PARTIAL_SRAM_OBJECT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name PARTIAL_SRAM_OBJECT_FILE <value>
© November 2008
Altera Corporation
PIN_FILE
1–53
PIN_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name PIN_FILE <value>
© November 2008
Altera Corporation
1–54
POWER_INPUT_FILE
POWER_INPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name POWER_INPUT_FILE <value>
© November 2008
Altera Corporation
PPF_FILE
1–55
PPF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name PPF_FILE <value>
© November 2008
Altera Corporation
1–56
PROGRAMMER_OBJECT_FILE
PROGRAMMER_OBJECT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name PROGRAMMER_OBJECT_FILE <value>
© November 2008
Altera Corporation
PROJECT_OUTPUT_DIRECTORY
1–57
PROJECT_OUTPUT_DIRECTORY
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY <value>
© November 2008
Altera Corporation
1–58
PROJECT_SHOW_ENTITY_NAME
PROJECT_SHOW_ENTITY_NAME
Type
Boolean
Device Support
Syntax
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME <value>
Default Value
On
© November 2008
Altera Corporation
PROJECT_USE_SIMPLIFIED_NAMES
1–59
PROJECT_USE_SIMPLIFIED_NAMES
Type
Boolean
Device Support
Syntax
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES <value>
Default Value
Off
© November 2008
Altera Corporation
1–60
QARLOG_FILE
QARLOG_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QARLOG_FILE <value>
© November 2008
Altera Corporation
QAR_FILE
1–61
QAR_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QAR_FILE <value>
© November 2008
Altera Corporation
1–62
QIP_FILE
QIP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QIP_FILE <value>
© November 2008
Altera Corporation
QUARTUS_PTF_FILE
1–63
QUARTUS_PTF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QUARTUS_PTF_FILE <value>
© November 2008
Altera Corporation
1–64
QUARTUS_SBD_FILE
QUARTUS_SBD_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QUARTUS_SBD_FILE <value>
© November 2008
Altera Corporation
QUARTUS_STANDARD_DELAY_FILE
1–65
QUARTUS_STANDARD_DELAY_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QUARTUS_STANDARD_DELAY_FILE <value>
© November 2008
Altera Corporation
1–66
QXP_FILE
QXP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name QXP_FILE <value>
© November 2008
Altera Corporation
RAW_BINARY_FILE
1–67
RAW_BINARY_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name RAW_BINARY_FILE <value>
© November 2008
Altera Corporation
1–68
READ_OR_WRITE_IN_BYTE_ADDRESS
READ_OR_WRITE_IN_BYTE_ADDRESS
Type
Enumeration
■
Off
■
On
■
Use global settings
Device Support
Syntax
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS <value>
Default Value
Use global settings
© November 2008
Altera Corporation
RUN_FULL_COMPILE_ON_DEVICE_CHANGE
1–69
RUN_FULL_COMPILE_ON_DEVICE_CHANGE
Type
Boolean
Device Support
Syntax
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE <value>
Default Value
On
© November 2008
Altera Corporation
1–70
SAVE_MIGRATION_INFO_DURING_COMPILATION
SAVE_MIGRATION_INFO_DURING_COMPILATION
Type
Boolean
Device Support
■
HardCopy II
■
HardCopy III
■
Stratix II
Syntax
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION <value>
Default Value
Off
Old Names
HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION
© November 2008
Altera Corporation
SBI_FILE
1–71
SBI_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SBI_FILE <value>
© November 2008
Altera Corporation
1–72
SDC_FILE
SDC_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SDC_FILE <value>
© November 2008
Altera Corporation
SDF_OUTPUT_FILE
1–73
SDF_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SDF_OUTPUT_FILE <value>
© November 2008
Altera Corporation
1–74
SERIAL_BITSTREAM_FILE
SERIAL_BITSTREAM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SERIAL_BITSTREAM_FILE <value>
© November 2008
Altera Corporation
SIGNALTAP_FILE
1–75
SIGNALTAP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SIGNALTAP_FILE <value>
© November 2008
Altera Corporation
1–76
SMART_RECOMPILE
SMART_RECOMPILE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name SMART_RECOMPILE <value>
Default Value
Off
Old Names
SPEED_DISK_USAGE_TRADEOFF
© November 2008
Altera Corporation
SMF_FILE
1–77
SMF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SMF_FILE <value>
© November 2008
Altera Corporation
1–78
SOFTWARE_LIBRARY_FILE
SOFTWARE_LIBRARY_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SOFTWARE_LIBRARY_FILE <value>
© November 2008
Altera Corporation
SRAM_OBJECT_FILE
1–79
SRAM_OBJECT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SRAM_OBJECT_FILE <value>
© November 2008
Altera Corporation
1–80
SRECORDS_FILE
SRECORDS_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SRECORDS_FILE <value>
© November 2008
Altera Corporation
SVF_FILE
1–81
SVF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SVF_FILE <value>
© November 2008
Altera Corporation
1–82
SYM_FILE
SYM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SYM_FILE <value>
© November 2008
Altera Corporation
SYSTEMVERILOG_FILE
1–83
SYSTEMVERILOG_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name SYSTEMVERILOG_FILE <value>
© November 2008
Altera Corporation
1–84
TCL_SCRIPT_FILE
TCL_SCRIPT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TCL_SCRIPT_FILE <value>
© November 2008
Altera Corporation
TEMPLATE_FILE
1–85
TEMPLATE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TEMPLATE_FILE <value>
© November 2008
Altera Corporation
1–86
TEXT_FILE
TEXT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TEXT_FILE <value>
© November 2008
Altera Corporation
TEXT_FORMAT_REPORT_FILE
1–87
TEXT_FORMAT_REPORT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TEXT_FORMAT_REPORT_FILE <value>
© November 2008
Altera Corporation
1–88
TIMING_ANALYSIS_OUTPUT_FILE
TIMING_ANALYSIS_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TIMING_ANALYSIS_OUTPUT_FILE <value>
© November 2008
Altera Corporation
VCD_FILE
1–89
VCD_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VCD_FILE <value>
© November 2008
Altera Corporation
1–90
VECTOR_TABLE_OUTPUT_FILE
VECTOR_TABLE_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VECTOR_TABLE_OUTPUT_FILE <value>
© November 2008
Altera Corporation
VECTOR_TEXT_FILE
1–91
VECTOR_TEXT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VECTOR_TEXT_FILE <value>
© November 2008
Altera Corporation
1–92
VECTOR_WAVEFORM_FILE
VECTOR_WAVEFORM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VECTOR_WAVEFORM_FILE <value>
© November 2008
Altera Corporation
VERILOG_FILE
1–93
VERILOG_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_FILE <value>
© November 2008
Altera Corporation
1–94
VERILOG_INCLUDE_FILE
VERILOG_INCLUDE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_INCLUDE_FILE <value>
Old Names
VERILOG_VH_FILE
© November 2008
Altera Corporation
VERILOG_OUTPUT_FILE
1–95
VERILOG_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_OUTPUT_FILE <value>
© November 2008
Altera Corporation
1–96
VERILOG_TEST_BENCH_FILE
VERILOG_TEST_BENCH_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_TEST_BENCH_FILE <value>
© November 2008
Altera Corporation
VER_COMPATIBLE_DB_DIR
1–97
VER_COMPATIBLE_DB_DIR
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VER_COMPATIBLE_DB_DIR <value>
Default Value
export_db
© November 2008
Altera Corporation
1–98
VHDL_FILE
VHDL_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VHDL_FILE <value>
© November 2008
Altera Corporation
VHDL_OUTPUT_FILE
1–99
VHDL_OUTPUT_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VHDL_OUTPUT_FILE <value>
© November 2008
Altera Corporation
1–100
VHDL_TEST_BENCH_FILE
VHDL_TEST_BENCH_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VHDL_TEST_BENCH_FILE <value>
© November 2008
Altera Corporation
VQM_FILE
1–101
VQM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VQM_FILE <value>
© November 2008
Altera Corporation
1–102
ZIP_VECTOR_WAVEFORM_FILE
ZIP_VECTOR_WAVEFORM_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE <value>
© November 2008
Altera Corporation
2. Pin & Location Assignments
APEX20K_CLIQUE_TYPE
Type
Enumeration
■
LAB
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_global_assignment -name APEX20K_CLIQUE_TYPE -entity <entity name> -section_id
<section identifier> <value>
Default Value
LAB, requires section identifier and entity name
Old Names
CLIQUE_TYPE
© November 2008
Altera Corporation
2–2
Pin & Location Assignments
APEX20K_LOCAL_ROUTING_SOURCE
APEX20K_LOCAL_ROUTING_SOURCE
Specifies that the fan-out(s) of an input pin connected to logic elements, or the fan-out(s) of a logic element
connected to output pin(s), should be fed via shared local interconnect lines. If the Local Routing Source
assignment is turned on for a pin, local routing occurs only for the cells placed in adjacent LABs to which
local routing is possible. If the Local Routing Source assignment is turned on for a logic element, local
routing occurs only for the output pins that are adjacent to the LAB containing the logic element. Altera
recommends that you make an explicit location assignment to the cells (input, output, logic element) to
guarantee they are placed in a suitable location for local routing. You can connect logic on a speed-critical
path using local routing to maximize the project performance.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name APEX20K_LOCAL_ROUTING_SOURCE -to <to> -entity <entity
name> <value>
Old Names
USE_LOCAL
© November 2008
Altera Corporation
FAST_INPUT_REGISTER
2–3
FAST_INPUT_REGISTER
Implements an input register in a cell that has a fast, direct connection from an I/O pin. If such a fast,
direct connection from the I/O pin is not available on the I/O cell hardware, this option instructs the Fitter
to lock the input register in the LAB adjacent to the I/O cell feeding it. Turning on the Fast Input Register
option can help maximize I/O timing performance, for example, by permitting fast setup times. Turning
this option off for a particular signal prevents the Fitter from implementing the signal automatically in an
I/O cell or locking down the input register in the LAB adjacent to the I/O cell. This option is ignored if it is
applied to anything other than a register or an input or bidirectional pin that feeds a register.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
© November 2008
Altera Corporation
2–4
FAST_INPUT_REGISTER
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name FAST_INPUT_REGISTER -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
FAST_OCT_REGISTER
2–5
FAST_OCT_REGISTER
Implements an OCT register in a cell that has a fast, direct connection to an I/O pin. Turning on the Fast
OCT Register option can help maximize I/O timing performance, for example, by permitting fast
clock-to-output times. Turning this option off for a particular signal prevents the Fitter from implementing
the signal automatically in an I/O cell. This option is ignored if it is applied to anything other than a
register or an output or bidirectional pin fed by a register.
Type
Boolean
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name FAST_OCT_REGISTER -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
2–6
FAST_OUTPUT_ENABLE_REGISTER
FAST_OUTPUT_ENABLE_REGISTER
Implements an output enable register in a cell that has a fast, direct connection to an I/O pin. If such a fast,
direct connection to the I/O pin is not available in the I/O cell hardware, this option instructs the Fitter to
lock the output enable register in the LAB adjacent to the I/O cell it is feeding.Turning on the Fast Output
Enable Register option can help maximize I/O timing performance, for example, by permitting fast
clock-to-output times. Turning this option off for a particular signal prevents the Fitter from implementing
the signal automatically in an I/O cell or locking down the output enable register in the LAB adjacent to
the I/O cell. This option is ignored if it is applied to anything other than a register or an output or
bidirectional pin fed by a register.
Type
Boolean
Device Support
■
APEX II
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
FAST_OUTPUT_REGISTER
2–7
Implements an output register in a cell that has a fast, direct connection to an I/O pin. If such a fast, direct
connection to the I/O pin is not available in the I/O cell hardware, this option instructs the Fitter to lock
the output register in the LAB adjacent to the I/O cell it is feeding.Turning on the Fast Output Register
option can help maximize I/O timing performance, for example, by permitting fast clock-to-output times.
Turning this option off for a particular signal prevents the Fitter from implementing the signal
automatically in an I/O cell or locking down the output register in the LAB adjacent to the I/O cell. This
option is ignored if it is applied to anything other than a register or an output or bidirectional pin fed by a
register.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
© November 2008
Altera Corporation
2–8
■
Stratix IV
Notes
Syntax
set_instance_assignment -name FAST_OUTPUT_REGISTER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
FLEX10K_CLIQUE_TYPE
2–9
FLEX10K_CLIQUE_TYPE
Type
Enumeration
■
LAB
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_global_assignment -name FLEX10K_CLIQUE_TYPE -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
2–10
FLEX6K_CLIQUE_TYPE
FLEX6K_CLIQUE_TYPE
Type
Enumeration
■
Best
■
Half Row
■
LAB
■
Row
Device Support
■
FLEX6000
Syntax
set_global_assignment -name FLEX6K_CLIQUE_TYPE -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
FLEX6K_LOCAL_ROUTING_SOURCE
2–11
FLEX6K_LOCAL_ROUTING_SOURCE
Specifies that the fan-out(s) of an input pin connected to logic elements, or the fan-out(s) of a logic element
connected to output pin(s), should be fed via shared local interconnect lines. If the Local Routing Source
assignment is turned on for a pin, local routing occurs only for the cells placed in adjacent LABs to which
local routing is possible. If the Local Routing Source assignment is turned on for a logic element, local
routing occurs only for the output pins that are adjacent to the LAB containing the logic element. Altera
recommends that you make an explicit location assignment to the cells (input, output, logic element) to
guarantee they are placed in a suitable location for local routing. You can connect logic on a speed-critical
path using local routing to maximize the project performance.
Type
Boolean
Device Support
■
FLEX6000
Syntax
set_instance_assignment -name FLEX6K_LOCAL_ROUTING_SOURCE -to <to> -entity <entity name>
<value>
Old Names
FLEX6K_LOCAL_ROUTING_DESTINATION
© November 2008
Altera Corporation
2–12
IP_DEBUG_VISIBLE
IP_DEBUG_VISIBLE
Type
Boolean
Device Support
Syntax
set_instance_assignment -name IP_DEBUG_VISIBLE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
LOCATION
2–13
LOCATION
Assigns a location on the device for the current node(s) and/or pin(s).
Type
Location
Device Support
Notes
Syntax
set_location_assignment -to <to> <value>
© November 2008
Altera Corporation
2–14
MAX7K_CLIQUE_TYPE
MAX7K_CLIQUE_TYPE
Type
Enumeration
■
LAB
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Syntax
set_global_assignment -name MAX7K_CLIQUE_TYPE -entity <entity name> -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
MEMBER_OF
2–15
MEMBER_OF
Assigns one or more currently selected nodes and/or entities to a clique, which is a group of functions that
the Compiler attempts to place together in the same area. You must also assign a name to the clique. A
clique assignment allows you to group all logic on a speed-critical path to help achieve optimum
performance.
Type
String
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
Notes
Syntax
set_instance_assignment -name MEMBER_OF -to <to> -entity <entity name> -section_id
© November 2008
Altera Corporation
2–16
MERCURY_CLIQUE_TYPE
MERCURY_CLIQUE_TYPE
Type
Enumeration
■
LAB
Device Support
■
Mercury
Syntax
set_global_assignment -name MERCURY_CLIQUE_TYPE -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
PIN_CONNECT_FROM_NODE
2–17
PIN_CONNECT_FROM_NODE
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name PIN_CONNECT_FROM_NODE -to <to> <value>
© November 2008
Altera Corporation
2–18
RESERVE_PIN
RESERVE_PIN
Reserves the pin in one of seven states: as an input that is tri-stated; as an output that drives ground; as an
output that drives VCC; as an output that drives an unspecified signal; as SignalProbe output; as a voltage
reference (VREF); or as bidirectional. Note: The 'As VREF' setting is not appropriate for all device families.
Please refer to the device data sheet for information on VREF support.
Type
Enumeration
■
As SignalProbe output
■
As VREF
■
As bidirectional
■
As input tri-stated
■
As output driving VCC
■
As output driving an unspecified signal
■
As output driving ground
Device Support
Syntax
set_instance_assignment -name RESERVE_PIN -to <to> <value>
set_global_assignment -name RESERVE_PIN <value>
Old Names
RESERVED_PIN
© November 2008
Altera Corporation
SUBCLIQUE_OF
2–19
SUBCLIQUE_OF
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name SUBCLIQUE_OF -to <to> -entity <entity name> -section_id
© November 2008
Altera Corporation
2–20
USE_CLK_FOR_VIRTUAL_PIN
USE_CLK_FOR_VIRTUAL_PIN
Specifies the name of the clock to be used for the I/O element specified with the Virtual Pin logic option.
During compilation, virtual pins are implemented as LUTs. You can use the Virtual Pin Clock option to
make clock assignments to the virtual pins, allowing you to analyze the timing as part of the correct clock
domain. The clock used for the virtual pin can be a pin or an internal node. If you turn on the Virtual Pin
logic option but do not specify a clock with the Virtual Pin Clock logic option or the clock you specified
does not exist, the Compiler finds a clock found by traversing the fan-in and fan-out of the I/O element. If
there are no clocks in the fan-in and fan-out of the I/O element, the clock is assigned to GND.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
The value of this assignment must be a node name.
Syntax
set_instance_assignment -name USE_CLK_FOR_VIRTUAL_PIN -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
VIRTUAL_PIN
2–21
VIRTUAL_PIN
Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic
element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option
should be specified only for I/O elements that become nodes when imported to the top-level design.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_instance_assignment -name VIRTUAL_PIN -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
2–22
VIRTUAL_PIN
© November 2008
Altera Corporation
3. Assignment Group Assignments
ASSIGNMENT_GROUP_EXCEPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name ASSIGNMENT_GROUP_EXCEPTION -section_id <section identifier>
<value>
© November 2008
Altera Corporation
3–2
Assignment Group Assignments
ASSIGNMENT_GROUP_MEMBER
ASSIGNMENT_GROUP_MEMBER
Type
String
Device Support
Notes
Syntax
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER -section_id <section identifier>
<value>
© November 2008
Altera Corporation
4. Analysis & Synthesis Assignments
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
Instructs the Compiler to add extra logic to inferred RAMs that require a read-after-write mode that isn't
supported by the RAM blocks in the target device. When a design both reads and writes to the same
memory address, this extra hardware guarantees that the read returns the new data being written to the
address. However, the extra logic will increase the area of the design and possibly reduce performance of
the inferred RAM is on the design's critical path.
A logic option that allows the Compiler to add extra logic to inferred RAMs requiring a read-after-write
mode that is not supported by RAM blocks in the current device. When a design reads and writes to the
same memory address, this extra hardware guarantees that the read returns the new data being written to
the address. However, the extra logic will increase the area of the design and possibly reduce its
performance if the design's critical path includes the inferred RAM.
This option can be used as a project-wide option, or assigned to a design entity.
This option defaults to On.
Type
Boolean
Device Support
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS <value>
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS -entity <entity
name> <value>
set_instance_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS -to <to> -entity
<entity name> <value>
Example
set_global_assignment -name add_pass_through_logic_to_inferred_rams off
set_instance_assignment -name add_pass_through_logic_to_inferred_rams off -to foo
Default Value
On
© November 2008
Altera Corporation
4–2
Analysis & Synthesis Assignments
ADV_NETLIST_OPT_ALLOWED
Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level
retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the Compiler
duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming during netlist
optimization, only if doing so does not negatively affect the timing or performance of the design. If this
option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so affects the timing
or performance of the design. Altera does not recommend using this setting. If this option is set to 'Never
Allow' the Compiler cannot alter the node or entity.
A logic option that specifies whether the Compiler should perform advanced netlist optimizations, such as
gate-level retiming or physical synthesis, on the specified node or entity.
You can choose one of the following settings: a) Always Allow: Allows the Compiler to alter the node or
entity, even if doing so affects the timing or performance of the design. Altera does not recommend using
this setting. b) Never Allow: Prevents the Compiler from altering the node or entity. 3) Default: Allows the
Compiler to duplicate, move, or change the synthesis of the node or entity, or allows register retiming
during netlist optimization, only if doing so does not negatively affect the timing or performance of the
design.
This option is useful for preserving I/O timing on specific pins and registers in a design where you want
to perform netlist optimization. This option is also useful for preserving the synthesis of a specific node or
entity, for example, preserving the name of a register.
This option can be assigned to individual nodes or design entities only.
Type
Enumeration
■
Always Allow
■
Default
■
Never Allow
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
© November 2008
Altera Corporation
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
4–3
Syntax
set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name> <value>
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg
© November 2008
Altera Corporation
4–4
ADV_NETLIST_OPT_RETIME_CORE_AND_IO
Specifies that the Quartus II software should move logic across registers associated with the I/O during
register retiming to effectively trade off Tco/Tsu with Fmax.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO <value>
set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO -entity <entity name>
<value>
set_instance_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO -to <to> -entity
© November 2008
Altera Corporation
4–5
Default Value
On
© November 2008
Altera Corporation
4–6
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
Specifies that the Quartus II software should perform gate-level register retiming during synthesis.
A logic option that specifies that the Quartus II software should perform gate-level register retiming
during synthesis.
You can use this option as a project-wide option, or assign this option to a design entity.
This option defaults to Off.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME <value>
© November 2008
Altera Corporation
4–7
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME -entity <entity name>
<value>
set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name adv_netlist_opt_synth_gate_retime on
set_instance_assignment -name adv_netlist_opt_synth_gate_retime on -to foo
Default Value
Off
© November 2008
Altera Corporation
4–8
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the
setting specified in the Optimization Technique logic option.
A logic option that specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This
option uses the setting specified in the Optimization Technique logic option.
This option is useful for resynthesizing some or all of the WYSIWYG primitives in the design for better
area or performance.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
4–9
Syntax
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP <value>
set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP -to <to> -entity
Example
set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on
set_instance_assignment -name adv_netlist_opt_synth_wysiwyg_remap on -to foo
Default Value
Off
© November 2008
Altera Corporation
4–10
ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
Specifies whether the Compiler is allowed to replace shift registers that use the asynchrnous clear signal
with the altshift_taps megafunction.
A logic option that allows the Compiler to also replace shift registers that use the asynchronous clear
signal with the altshift_taps megafunction.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION <value>
set_global_assignment -name ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION -entity <entity
name> <value>
set_instance_assignment -name ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION -to <to> -entity
Example
set_global_assignment -name allow_aclr_for_shift_register_recognition off
set_instance_assignment -name allow_aclr_for_shift_register_recognition off -to foo
Default Value
On
© November 2008
Altera Corporation
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
4–11
Allows the Compiler to infer RAMs of any size, even if they don't meet the current minimum
requirements.
A logic option that allows the Compiler to infer RAMs of any size even if the RAMs do not meet the
design's current minimum size requirements.
This option is useful for minimizing the area of a design that is close to the device limit.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
4–12
Notes
Syntax
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION <value>
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -entity <entity name>
<value>
set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to <to> -entity
Example
set_global_assignment -name allow_any_ram_size_for_recognition off
set_instance_assignment -name allow_any_ram_size_for_recognition off -to foo
Default Value
Off
© November 2008
Altera Corporation
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
4–13
Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's current
minimum size requirements.
A logic option that allows the Compiler to infer ROMs of any size even if the ROMs do not meet the
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
4–14
Notes
Syntax
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION <value>
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -entity <entity name>
<value>
set_instance_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -to <to> -entity
Example
set_global_assignment -name allow_any_rom_size_for_recognition off
set_instance_assignment -name allow_any_rom_size_for_recognition off -to foo
Default Value
Off
© November 2008
Altera Corporation
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
4–15
Allows the Compiler to infer shift registers of any size even if they do not meet the design's current
minimum size requirements.
A logic option that allows the Compiler to infer shift registers of any size even if they do not meet the
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION <value>
© November 2008
Altera Corporation
4–16
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -entity
set_instance_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -to <to>
-entity <entity name> <value>
Example
set_global_assignment -name allow_any_shift_register_size_for_recognition off
set_instance_assignment -name allow_any_shift_register_size_for_recognition off -to foo
Default Value
Off
© November 2008
Altera Corporation
ALLOW_POWER_UP_DONT_CARE
4–17
ALLOW_POWER_UP_DONT_CARE
A logic option that causes registers that do not have a Power-Up Level logic option setting to power up
with a don't care logic level (X).
This option is useful for allowing the Compiler to change the power-up level of a register to minimize the
area of the design.
This option can be used as a project-wide option only.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE <value>
Example
set_global_assignment -name allow_power_up_dont_care off
Default Value
On
See Also
■
"POWER_UP_LEVEL" on page 4–142
© November 2008
Altera Corporation
4–18
ALLOW_SYNCH_CTRL_USAGE
Allows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logic
cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might
negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
A logic option that allows the Compiler to utilize synchronous clear and/or synchronous load signals in
normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the
design, but might negatively impact the fitting since synchronous control signals are shared by all the logic
cells in a LAB.
This option is useful for finding areas of the design that can be implemented more efficiently with
synchronous clear and/or synchronous load signals in normal mode logic cells, and as a result, minimize
the number of logic cells used in the design.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE <value>
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity <entity name> <value>
© November 2008
Altera Corporation
4–19
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name allow_synch_ctrl_usage off
set_instance_assignment -name allow_synch_ctrl_usage off -to foo
Default Value
On
© November 2008
Altera Corporation
4–20
ALLOW_XOR_GATE_USAGE
Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an embedded cell within an
Embedded System Block [ESB] that is set to use Product Term mode). This option is ignored if you select
'LUT' or 'ROM' as the setting for the Technology Mapper option.
A logic option that allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an
embedded cell within an Embedded System Block (ESB) that is set to use Product Term mode).
This option is ignored if it is assigned to anything other than a design entity. The Allow XOR Gate Usage
option is also ignored if you select LUT or ROM as the setting for the Technology Mapper option. This
option can be set in the Assignment Editor (Assignments menu) or the Analysis & Synthesis Settings page
or the Fitter Settings page of the Settings dialog box (Assignments menu). This option is available for
APEX 20K, APEX 20KC, APEX 20KE, APEX II, Excalibur, MAX 3000, MAX 7000A, MAX 7000AE, MAX
7000B, and MAX 7000S devices.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name ALLOW_XOR_GATE_USAGE <value>
set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity <entity name> <value>
set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name allow_xor_gate_usage off -to clock
© November 2008
Altera Corporation
4–21
Default Value
On
© November 2008
Altera Corporation
4–22
APEX20K_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,
minimize logic usage, or balance high performance with minimal logic usage.
A logic option that specifies the overall goal for logic optimization, that is, whether to attempt to achieve
maximum speed performance, minimum area usage, or balance high performance with minimal logic
usage during compilation.
You can select one of the following settings: a) Area: The Compiler makes the design as small as possible in
order to minimize resource usage. b) Speed: The Compiler chooses a design implementation that has the
fastest fmax. c) Balanced: The Compiler chooses a design implementation that balances high performance
with minimal logic usage.
This option defaults to Balanced.
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name apex20k_optimization_technique speed
Default Value
Balanced
© November 2008
Altera Corporation
4–23
Old Names
Optimization Technique -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur
© November 2008
Altera Corporation
4–24
APEX20K_TECHNOLOGY_MAPPER
APEX20K_TECHNOLOGY_MAPPER
Specifies whether to target look-up table (LUT) or Product Term when implementing logic in the device.
The Technology Mapper option allows you to determine whether logic is implemented in LABs or ESBs.
Depending on the setting of this option, other logic options may be ignored. For example, because carry
and cascade chains can only be implemented in LUTs, the Auto Carry Chains and Auto Cascade Chains
options are ignored if the 'Product Term' setting is selected. Similarly, because parallel expanders can only
be implemented in product terms, the Auto Parallel Expander Chains option is ignored if the 'LUT' setting
is selected.
Type
Enumeration
■
LUT
■
Product Term
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER <value>
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER -entity <entity name> <value>
set_instance_assignment -name APEX20K_TECHNOLOGY_MAPPER -to <to> -entity <entity name>
<value>
Default Value
Lut
Old Names
TECHNOLOGY_MAPPER
Technology Mapper -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur
© November 2008
Altera Corporation
AUTO_CARRY_CHAINS
4–25
AUTO_CARRY_CHAINS
Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers into the
design. This option is also required to recognize carry chains in any design containing MAX+PLUS II-style
CARRY buffers. The length of the chains is controlled with the Carry Chain Length option. If this option is
turned off, CARRY buffers are ignored, but CARRY_SUM buffers are unaffected. The Auto Carry Chains
option is ignored if you select 'Product Term' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
4–26
AUTO_CARRY_CHAINS
Notes
Syntax
set_global_assignment -name AUTO_CARRY_CHAINS <value>
set_global_assignment -name AUTO_CARRY_CHAINS -entity <entity name> <value>
set_instance_assignment -name AUTO_CARRY_CHAINS -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
AUTO_CASCADE_CHAINS
4–27
AUTO_CASCADE_CHAINS
Allows the Compiler to create cascade chains automatically by inserting CASCADE buffers into the
design. The length of the chains is controlled with the Cascade Chain Length option. The Auto Cascade
Chains option is ignored if you select 'Product Term' or 'ROM' as the setting for the Technology Mapper
option.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
Syntax
set_global_assignment -name AUTO_CASCADE_CHAINS <value>
set_global_assignment -name AUTO_CASCADE_CHAINS -entity <entity name> <value>
set_instance_assignment -name AUTO_CASCADE_CHAINS -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
4–28
AUTO_CLOCK_ENABLE_RECOGNITION
Allows the Compiler to find logic that feeds a register and move the logic to the register's clock enable
input port.
A logic option that allows the Compiler to find logic that feeds a register and move the logic to the
register's clock enable input port.
This option can bet set to Off on individual registers or design entities to solve fitting and performance
issues with designs that have many clock enables generated by Analysis & Synthesis.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
© November 2008
Altera Corporation
■
4–29
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION <value>
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -entity <entity name> <value>
set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name auto_clock_enable_replacement off
set_instance_assignment -name auto_clock_enable_replacement off -to reg
Default Value
On
© November 2008
Altera Corporation
4–30
AUTO_DSP_RECOGNITION
Allows the Compiler to find a multiply-accumulate function or a multiply-add function that can be
replaced with the altmult_accum or the altmult_add megafunction.
A logic option that allows the Compiler to find a multiply-accumulate function or a multiply-add function
that can be replaced with the altmult_accum or the altmult_add megafunction.
This option is useful for finding areas of the design that can be implemented more efficiently, and as a
result, minimizing the area and maximizing the speed of the design.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_DSP_RECOGNITION <value>
set_global_assignment -name AUTO_DSP_RECOGNITION -entity <entity name> <value>
set_instance_assignment -name AUTO_DSP_RECOGNITION -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name auto_dsp_recognition off
set_instance_assignment -name auto_dsp_recognition off -to foo
© November 2008
Altera Corporation
4–31
Default Value
On
© November 2008
Altera Corporation
4–32
AUTO_ENABLE_SMART_COMPILE
AUTO_ENABLE_SMART_COMPILE
Type
Boolean
Device Support
Syntax
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE <value>
© November 2008
Altera Corporation
AUTO_GLOBAL_CLOCK_MAX
4–33
AUTO_GLOBAL_CLOCK_MAX
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock
signal that is made available throughout the device on the global routing paths. If you want to prevent the
Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to
'Off' on that signal.
A logic option that allows the Compiler to choose the signal that feeds the most clock inputs to registers as
a global clock signal that is made available throughout the device on the global routing paths.
If you want to prevent the Compiler from automatically selecting a particular signal as global clock, set the
Global Signal option to Off on that signal.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Syntax
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX <value>
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_CLOCK_MAX -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name auto_global_clock_max off
set_instance_assignment -name auto_global_clock_max off -to foo
Default Value
On
Old Names
Auto Global Clock -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
4–34
AUTO_GLOBAL_OE_MAX
AUTO_GLOBAL_OE_MAX
Allows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signal
that is made available throughout the device on the global routing paths. If you want to prevent the
Compiler from automatically selecting a particular signal as global output enable, set the Global Signal
option to 'Off' on that signal.
A logic option that allows the Compiler to choose the signal that feeds the most TRI buffers as a global
output enable signal that is made available throughout the device on the global routing paths.
This option is ignored if it is assigned to anything other than a design entity. If you want to prevent the
option to Off on that signal.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Syntax
set_global_assignment -name AUTO_GLOBAL_OE_MAX <value>
set_global_assignment -name AUTO_GLOBAL_OE_MAX -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_OE_MAX -to <to> -entity <entity name> <value>
Example
set_global_assignment -name auto_global_oe_max
set_instance_assignment -name auto_global_oe_max
off
off -to foo
Default Value
On
Old Names
Auto Global Output Enable -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
AUTO_IMPLEMENT_IN_ROM
4–35
AUTO_IMPLEMENT_IN_ROM
Allows the Compiler to automatically implement combinatorial logic in ROM (that is, in an embedded cell
within an Embedded System Block [ESB] or Embedded Array Block [EAB] that is set to use ROM mode),
to improve speed or area usage. Using ROM in this way can free up logic cells that would otherwise be
needed to implement the combinatorial logic. This option is ignored if you select 'Product Term' as the
setting for the Technology Mapper option.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
Mercury
Notes
Syntax
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM <value>
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM -entity <entity name> <value>
set_instance_assignment -name AUTO_IMPLEMENT_IN_ROM -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
4–36
AUTO_LCELL_INSERTION
AUTO_LCELL_INSERTION
Allows the Compiler to insert macrocells into the design. This option is ignored if it is assigned to anything
other than a design entity. If you want to prevent the Compiler from automatically inserting macrocells
into the design, set the Auto Logic Cell Insertion option to 'Off' on that signal.
A logic option that directs the Compiler to insert macrocells into the design.
If you want to prevent the Compiler from automatically inserting macrocells into the design, set the Auto
Logic Cell Insertion option to Off on that signal. This option is available for MAX 3000, MAX 7000AE,
MAX 7000B, and MAX 7000S devices.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name AUTO_LCELL_INSERTION <value>
set_global_assignment -name AUTO_LCELL_INSERTION -entity <entity name> <value>
set_instance_assignment -name AUTO_LCELL_INSERTION -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name auto_lcell_insertion off
set_instance_assignment -name auto_lcell_insertion off -to foo
Default Value
On
© November 2008
Altera Corporation
AUTO_OPEN_DRAIN_PINS
4–37
Allows the Compiler to automatically convert a tri-state buffer with a strong low data input into the
equivalent open-drain buffer.
A logic option that directs the Compiler to automatically convert a tri-state buffer with a strong low data
input into the equivalent open-drain buffer.
This option cannot be used with a netlists that are synthesized with third-party synthesis tools. To use this
option, you must turn on the Perform WYSIWYG Primitive Resynthesis logic option.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
© November 2008
Altera Corporation
4–38
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_OPEN_DRAIN_PINS <value>
set_global_assignment -name AUTO_OPEN_DRAIN_PINS -entity <entity name> <value>
set_instance_assignment -name AUTO_OPEN_DRAIN_PINS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name auto_open_drain_pins off
set_instance_assignment -name auto_open_drain_pins off -to foo
Default Value
On
© November 2008
Altera Corporation
AUTO_PARALLEL_EXPANDERS
4–39
Allows the Compiler to automatically create chains of parallel expander product terms. Parallel expanders
are available in macrocells, that is, embedded cells within an Embedded System Block [ESB] that is set to
use Product Term mode. The length of the chains is controlled with the Parallel Expander Chain Length
option. The Auto Parallel Expanders option is ignored if you select 'LUT' or 'ROM' as the setting for the
Technology Mapper option.
A logic option that allows the Compiler to automatically create chains of parallel expander product terms.
Parallel expanders are available in macrocells, that is, embedded cells within an Embedded System Block
(ESB) that is set to use Product Term mode. The length of the chains is controlled with the Parallel
Expander Chain Length option.
This option is ignored if it is assigned to anything other than a design entity. The Auto Parallel Expanders
option is also ignored if you select LUT or ROM as the setting for the Technology Mapper option. This
option can be set in the Assignment Editor (Assignments menu) or the Analysis & Synthesis Settings page
or the Fitter Settings page of the Settings dialog box (Assignments menu). This option is available for
APEX 20K, APEX 20KC, APEX 20KE, APEX II, Excalibur, MAX 3000, MAX 7000AE, MAX 7000B, and MAX
7000S devices.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name AUTO_PARALLEL_EXPANDERS <value>
set_global_assignment -name AUTO_PARALLEL_EXPANDERS -entity <entity name> <value>
set_instance_assignment -name AUTO_PARALLEL_EXPANDERS -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
4–40
Example
set_instance_assignment -name auto_parallel_expanders on -to clock
Default Value
On
© November 2008
Altera Corporation
AUTO_RAM_BLOCK_BALANCING
4–41
AUTO_RAM_BLOCK_BALANCING
A logic option that enables the Compiler to automatically use different memory types when using auto
RAM blocks and allows the Compiler to use different RAM partitions with the same memory types.
result, minimizing the area and maximizing the speed of the design. During design fitting, a megafunction
may use a RAM partition that cannot fit in the design due to unbalanced use of RAM resources. The logic
option allows the Compiler to dynamically change RAM partitions and balance resource usage when
using different RAM block types.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING <value>
Example
set_global_assignment -name auto_ram_block_balancing off
Default Value
On
© November 2008
Altera Corporation
4–42
AUTO_RAM_RECOGNITION
Allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the
lpm_ram_dp megafunction. Turning on this option may change the functionality of the design.
A logic option that allows the Compiler to find a set of registers and logic that can be replaced with the
altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the functionality of the
design.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
© November 2008
Altera Corporation
■
4–43
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_RAM_RECOGNITION <value>
set_global_assignment -name AUTO_RAM_RECOGNITION -entity <entity name> <value>
set_instance_assignment -name AUTO_RAM_RECOGNITION -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name auto_ram_recognition off
set_instance_assignment -name auto_ram_recognition off -to foo
Default Value
On
© November 2008
Altera Corporation
4–44
AUTO_RAM_TO_LCELL_CONVERSION
AUTO_RAM_TO_LCELL_CONVERSION
Allows the Compiler to convert small RAM blocks into logic cells.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION <value>
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -entity <entity name> <value>
set_instance_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -to <to> -entity <entity
name> <value>
Default Value
Off
© November 2008
Altera Corporation
AUTO_RESOURCE_SHARING
4–45
AUTO_RESOURCE_SHARING
Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations
in your HDL source code. If you enable this option, the Compiler will merge compatible addition,
subtraction, and multiplication operations. By merging operations, this may reduce the area required by
your design. Because resource sharing introduces extra muxing and control logic on each shared resource,
it may negatively impact the final fmax of your design.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name AUTO_RESOURCE_SHARING <value>
set_global_assignment -name AUTO_RESOURCE_SHARING -entity <entity name> <value>
set_instance_assignment -name AUTO_RESOURCE_SHARING -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
4–46
AUTO_ROM_RECOGNITION
Allows the Compiler to find logic that can be replaced with the altsyncram or the lpm_rom megafunction.
Turning on this option may change the power-up state of the design.
A logic option that allows the Compiler to find logic that can be replaced with the altsyncram or the
lpm_rom megafunction. Turning on this option may change the power-up state of the design.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
© November 2008
Altera Corporation
■
4–47
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_ROM_RECOGNITION <value>
set_global_assignment -name AUTO_ROM_RECOGNITION -entity <entity name> <value>
set_instance_assignment -name AUTO_ROM_RECOGNITION -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name auto_rom_recognition off
set_instance_assignment -name auto_rom_recognition off -to foo
Default Value
On
© November 2008
Altera Corporation
4–48
AUTO_SHIFT_REGISTER_RECOGNITION
Allows the Compiler to find a group of shift registers of the same length that can be replaced with the
altshift_taps megafunction. The shift registers must all use the same clock and clock enable signals, must
not have any other secondary signals, and must have equally spaced taps that are at least three registers
apart.
A logic option that allows the Compiler to find a group of shift registers of the same length that can be
replaced with the altshift_taps megafunction. The shift registers must all use the same clock and clock
enable signals, must not have any other secondary signals, and must have equally spaced taps that are at
least three registers apart.
Type
Enumeration
■
Always
■
Auto
■
Off
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
© November 2008
Altera Corporation
■
Stratix III
■
Stratix IV
4–49
Notes
Syntax
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION <value>
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -entity <entity name>
<value>
set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name auto_shift_register_recognition off
set_instance_assignment -name auto_shift_register_recognition off -to foo
Default Value
Auto
© November 2008
Altera Corporation
4–50
BLOCK_DESIGN_NAMING
BLOCK_DESIGN_NAMING
Specify the naming scheme used for the block design. This option is ignored if it is assigned to anything
other than a design entity.
An option that specifies which naming scheme should be used for the design entity.
The following three settings are available: a) MaxPlusII: This option specifies the naming scheme used in
previous versions of Quartus II software. b) QuartusII: This option specifies the new naming scheme on
block designs, when a bus is split, the resulted pins are named with base name followed by square
brackets, with indicies between the bracket pair. c) Auto: This option informs Quartus II software to use
the naming scheme that is specified by the source file.
This option is useful if your design contains design files that are generated by Quartus II 7.2 as well as by
previous versions of Quartus II software. You can use this option to specify which naming scheme you
want Quartus II software to use on the specified design entity.
This option can be used as a project-wide option, or assigned to a block design entity.
This option defaults to Auto.
Type
Enumeration
■
Auto
■
MaxPlusII
■
QuartusII
Device Support
Notes
Syntax
set_global_assignment -name BLOCK_DESIGN_NAMING -entity <entity name> <value>
set_instance_assignment -name BLOCK_DESIGN_NAMING -to <to> -entity <entity name> <value>
set_global_assignment -name BLOCK_DESIGN_NAMING <value>
Example
set_global_assignment -name block_design_naming MaxPlusII
set_instance_assignment -name block_design_naming MaxPlusII -to top
Default Value
Auto
© November 2008
Altera Corporation
CARRY_CHAIN_LENGTH
4–51
CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized
CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option
also applies to MAX+PLUS II-style CARRY buffers.)
Type
Integer
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name CARRY_CHAIN_LENGTH <value>
set_global_assignment -name CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name CARRY_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
48
© November 2008
Altera Corporation
4–52
CASCADE_CHAIN_LENGTH
CASCADE_CHAIN_LENGTH
CASCADE buffers. Cascade chains that exceed this length are broken into separate chains.
Type
Integer
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
Notes
Syntax
set_global_assignment -name CASCADE_CHAIN_LENGTH <value>
set_global_assignment -name CASCADE_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name CASCADE_CHAIN_LENGTH -to <to> -entity <entity name>
<value>
Default Value
2
© November 2008
Altera Corporation
CLKLOCKX1_INPUT_FREQ
4–53
Creates an internal ClockLock phase-locked loop (PLL) and specifies its frequency. Turning this option on
is equivalent to instantiating an altclklock megafunction with either of its ClockBoost parameters set to a
value of 1. The CLKLOCKx1 Input Frequency option is provided primarily for backward compatibility
with MAX+PLUS II designs. Altera recommends using the MegaWizard Plug-In Manager to instantiate
PLLs in new designs. This option is ignored if it is assigned to anything other than an input pin or to a
device that does not have the PLL feature.
Type
Frequency
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
4–54
Syntax
set_instance_assignment -name CLKLOCKX1_INPUT_FREQ -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
CYCLONEII_OPTIMIZATION_TECHNIQUE
4–55
This option is applicable to Cyclone II and Cyclone III devices.
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
Cyclone II
■
Cyclone III
Notes
Syntax
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -entity <entity name>
<value>
set_instance_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name cycloneii_optimization_technique speed
Default Value
Balanced
Old Names
© November 2008
Altera Corporation
4–56
Optimization Technique -- Cyclone II/Cyclone III
© November 2008
Altera Corporation
CYCLONE_OPTIMIZATION_TECHNIQUE
4–57
CYCLONE_OPTIMIZATION_TECHNIQUE
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
Cyclone
Notes
Syntax
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name cyclone_optimization_technique speed
Default Value
Balanced
Old Names
Optimization Technique -- Cyclone
© November 2008
Altera Corporation
4–58
DEVICE_FILTER_PACKAGE
DEVICE_FILTER_PACKAGE
Type
String
Device Support
Syntax
set_global_assignment -name DEVICE_FILTER_PACKAGE <value>
Default Value
Any
© November 2008
Altera Corporation
DEVICE_FILTER_PIN_COUNT
4–59
DEVICE_FILTER_PIN_COUNT
Type
String
Device Support
Syntax
set_global_assignment -name DEVICE_FILTER_PIN_COUNT <value>
Default Value
Any
© November 2008
Altera Corporation
4–60
DEVICE_FILTER_SPEED_GRADE
DEVICE_FILTER_SPEED_GRADE
Type
String
Device Support
Syntax
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE <value>
Default Value
Any
© November 2008
Altera Corporation
DEVICE_FILTER_VOLTAGE
4–61
DEVICE_FILTER_VOLTAGE
Type
String
Device Support
Syntax
set_global_assignment -name DEVICE_FILTER_VOLTAGE <value>
© November 2008
Altera Corporation
4–62
DISABLE_OCP_HW_EVAL
DISABLE_OCP_HW_EVAL
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name DISABLE_OCP_HW_EVAL <value>
Default Value
Off
© November 2008
Altera Corporation
DONT_MERGE_REGISTER
4–63
DONT_MERGE_REGISTER
When set to On, this option prevents the specified register from merging with other registers, and prevents
other registers from merging with the specified register.
A logic option that, when set to On, prevents the specified register from merging with other registers, and
prevents other registers from merging with the specified register. When applied to a design entity it
applies to all registers in the entity.
You can use this option to instruct the Compiler to use the user-specified timing constraints on the register
during synthesis. For example, if the register has a multicycle constraint, this option prevents the Compiler
from merging other registers into the specified register, avoiding unintended timing and functional effects.
This option is different from Preserve Register logic option because it does not prevent a register with
constant drivers or a redundant register from being removed. In addition, this option prevents other
registers from merging with the specified register.
This option is ignored if the register does not drive anything or if it has constant drivers, in which case the
register is removed during synthesis.
This option is ignored if it is applied to anything other than a register or a design entity containing
registers.
Type
Boolean
Device Support
Syntax
set_global_assignment -name DONT_MERGE_REGISTER -entity <entity name> <value>
set_instance_assignment -name DONT_MERGE_REGISTER -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name dont_merge_register on -to foo
© November 2008
Altera Corporation
4–64
DQS_DELAY
DQS_DELAY
Increases the propagation delay from a DQS I/O pin to the interior of the device. This option is used to
center-align the DQS signal to the DQ data signals and should be selected to ensure the desired setup and
hold margins across process, voltage, and temperature ranges.
Type
Time
Device Support
■
Cyclone
■
Cyclone III
Syntax
set_instance_assignment -name DQS_DELAY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
DQS_FREQUENCY
4–65
DQS_FREQUENCY
Specifies the DQS system clock frequency by which data is transferred between a device and an external
RAM that uses double data rate (DDR). You can specify the desired frequency setting.
Type
Frequency
Device Support
■
Cyclone
■
Cyclone II
■
Cyclone III
■
Stratix
■
Stratix GX
Syntax
set_instance_assignment -name DQS_FREQUENCY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
4–66
DQS_SHIFT
DQS_SHIFT
Specifies the interval of arrival between the DQ data signals and DQS signal during data transfer between
a device and an external RAM that uses double data rate (DDR). This option is ignored if it is applied to
anything other than pins intended for use with the dedicated DDR SDRAM interface.
Type
Enumeration
■
Phase of 0 degrees
■
Phase of 72 degrees
■
Phase of 90 degrees
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Syntax
set_instance_assignment -name DQS_SHIFT -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
DQS_SYSTEM_CLOCK
4–67
DQS_SYSTEM_CLOCK
Specifies the clock input used as a frequency reference for a DQS I/O pin. The clock is the pin that drives
the DDIO circuitry for the dedicated DDR SDRAM interface.
Type
String
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name DQS_SYSTEM_CLOCK -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
4–68
DSE_SYNTH_EXTRA_EFFORT_MODE
DSE_SYNTH_EXTRA_EFFORT_MODE
Type
Enumeration
■
MODE_1
■
MODE_2
■
MODE_3
■
MODE_4
■
MODE_5
■
MODE_DEFAULT
Device Support
■
HardCopy Stratix
■
MAX II
■
Stratix
Syntax
set_global_assignment -name DSE_SYNTH_EXTRA_EFFORT_MODE <value>
© November 2008
Altera Corporation
DSP_BLOCK_BALANCING
4–69
DSP_BLOCK_BALANCING
Allows you to control the conversion of certain DSP block slices during DSP block balancing.
A logic option that allows you to control the conversion of certain DSP block slices during DSP block
balancing.
This option is useful for controlling the DSP block balancer when it produces results that conflict with
your design, such as converting DSP block slices that you do not want to be converted.
You can select one of the following settings: Auto, Off, DSP blocks, Logic Elements, Simple Multipliers,
Width 18-bit Multipliers, Simple 18-bit Multipliers.
Type
Enumeration
■
Auto
■
DSP blocks
■
Logic Elements
■
Off
■
Simple 18-bit Multipliers
■
Simple Multipliers
■
Width 18-bit Multipliers
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
4–70
DSP_BLOCK_BALANCING
Syntax
set_global_assignment -name DSP_BLOCK_BALANCING -entity <entity name> <value>
set_instance_assignment -name DSP_BLOCK_BALANCING -to <to> -entity <entity name> <value>
set_global_assignment -name DSP_BLOCK_BALANCING <value>
Example
set_global_assignment -name dsp_block_balancing "dsp blocks"
set_instance_assignment -name dsp_block_balancing "logic elements" -to mult0
Default Value
Auto
© November 2008
Altera Corporation
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
4–71
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL <value>
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL -entity <entity name>
<value>
Default Value
<None>
© November 2008
Altera Corporation
4–72
EDA_INPUT_DATA_FORMAT
EDA_INPUT_DATA_FORMAT
Type
String
Device Support
Syntax
set_global_assignment -name EDA_INPUT_DATA_FORMAT -section_id <section identifier>
<value>
set_global_assignment -name EDA_INPUT_DATA_FORMAT -entity <entity name> -section_id
Default Value
NONE, requires section identifier
© November 2008
Altera Corporation
EDA_INPUT_GND_NAME
4–73
EDA_INPUT_GND_NAME
Type
String
Device Support
Syntax
set_global_assignment -name EDA_INPUT_GND_NAME -section_id <section identifier> <value>
set_global_assignment -name EDA_INPUT_GND_NAME -entity <entity name> -section_id
Default Value
GND, requires section identifier
© November 2008
Altera Corporation
4–74
EDA_INPUT_VCC_NAME
EDA_INPUT_VCC_NAME
Type
String
Device Support
Syntax
set_global_assignment -name EDA_INPUT_VCC_NAME -section_id <section identifier> <value>
set_global_assignment -name EDA_INPUT_VCC_NAME -entity <entity name> -section_id
Default Value
VCC, requires section identifier
© November 2008
Altera Corporation
EDA_LMF_FILE
4–75
EDA_LMF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_LMF_FILE -section_id <section identifier> <value>
set_global_assignment -name EDA_LMF_FILE -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
4–76
EDA_RUN_TOOL_AUTOMATICALLY
EDA_RUN_TOOL_AUTOMATICALLY
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -section_id <section identifier>
<value>
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -entity <entity name> -section_id
Default Value
Off, requires section identifier
© November 2008
Altera Corporation
EDA_SHOW_LMF_MAPPING_MESSAGES
4–77
EDA_SHOW_LMF_MAPPING_MESSAGES
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -section_id <section
identifier> <value>
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -entity <entity name>
-section_id <section identifier> <value>
Default Value
© November 2008
Altera Corporation
4–78
EDA_VHDL_LIBRARY
EDA_VHDL_LIBRARY
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -section_id <section identifier>
<value>
set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -entity <entity name>
© November 2008
Altera Corporation
ENABLE_IP_DEBUG
4–79
ENABLE_IP_DEBUG
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name ENABLE_IP_DEBUG <value>
Default Value
Off
© November 2008
Altera Corporation
4–80
ENABLE_M512
ENABLE_M512
A logic option that allows you to disable M512 memory blocks in a HardCopy II design.
Because HardCopy II designs do not support M512 memory blocks, this option is useful when you
migrate a compiled Stratix II design to a HardCopy II design.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name ENABLE_M512 <value>
Example
set_global_assignment -name enable_m512 off
© November 2008
Altera Corporation
EXTRACT_VERILOG_STATE_MACHINES
4–81
EXTRACT_VERILOG_STATE_MACHINES
A logic option that allows the Compiler to extract state machines from a Verilog Design File (.v). The
Compiler optimizes state machines using special techniques to reduce area and/or improve performance.
If this option is set to Off, the Compiler extracts and optimizes state machines in Verilog Design Files as
regular logic.
This option is useful for preventing automatic state machine optimizations to manually optimized logic.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES <value>
Example
set_global_assignment -name extract_verilog_state_machines off
Default Value
On
See Also
■
"STATE_MACHINE_PROCESSING" on page 4–158
■
"EXTRACT_VHDL_STATE_MACHINES" on page 4–82
© November 2008
Altera Corporation
4–82
EXTRACT_VHDL_STATE_MACHINES
EXTRACT_VHDL_STATE_MACHINES
A logic option that allows the Compiler to extract state machines from a VHDL Design File (.vhd). The
Compiler optimizes state machines using special techniques to reduce area and/or improve performance.
If this option is set to Off, the Compiler extracts and optimizes state machines in VHDL Design Files as
regular logic.
This option is useful for preventing automatic state machine optimizations to manually optimized logic.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES <value>
Example
set_global_assignment -name extract_vhdl_state_machines off
Default Value
On
See Also
■
■
"EXTRACT_VERILOG_STATE_MACHINES" on page 4–81
© November 2008
Altera Corporation
FAMILY
4–83
FAMILY
Type
String
Device Support
Notes
Syntax
set_global_assignment -name FAMILY <value>
Default Value
Stratix II
© November 2008
Altera Corporation
4–84
FLEX10K_CARRY_CHAIN_LENGTH
Type
Integer
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name FLEX10K_CARRY_CHAIN_LENGTH -to <to> -entity <entity name>
<value>
Default Value
32
Old Names
Carry Chain Length -- FLEX 10K
© November 2008
Altera Corporation
FLEX10K_OPTIMIZATION_TECHNIQUE
4–85
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or
minimize logic usage.
with minimal logic usage. This setting is available for APEX 20K, Cyclone, Cyclone II, MAX II, Stratix, and
Stratix II devices only.
This option defaults to Area.
Type
Enumeration
■
Area
■
Speed
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name flex10k_optimization_technique speed
Default Value
Area
Old Names
© November 2008
Altera Corporation
4–86
Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K
© November 2008
Altera Corporation
4–87
Type
Integer
Device Support
■
FLEX6000
Notes
Syntax
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name FLEX6K_CARRY_CHAIN_LENGTH -to <to> -entity <entity name>
<value>
Default Value
32
Old Names
Carry Chain Length -- FLEX 6000
© November 2008
Altera Corporation
4–88
Type
Enumeration
■
Area
■
Speed
Device Support
■
FLEX6000
Notes
Syntax
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name flex6k_optimization_technique speed
Default Value
Area
Old Names
Optimization Technique -- FLEX 6000
© November 2008
Altera Corporation
FORCE_SYNCH_CLEAR
4–89
FORCE_SYNCH_CLEAR
Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this option
helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting
since synchronous control signals are shared by all the logic cells in a LAB.
A logic option that forces the Compiler to utilize synchronous clear signals in normal mode logic cells.
Turning on this option helps to reduce the total number of logic cells used in the design, but might
negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name FORCE_SYNCH_CLEAR <value>
set_global_assignment -name FORCE_SYNCH_CLEAR -entity <entity name> <value>
set_instance_assignment -name FORCE_SYNCH_CLEAR -to <to> -entity <entity name> <value>
Example
set_global_assignment -name force_synch_clear on
set_instance_assignment -name force_synch_clear on -to foo
© November 2008
Altera Corporation
4–90
FORCE_SYNCH_CLEAR
Default Value
Off
See Also
■
"ALLOW_SYNCH_CTRL_USAGE" on page 4–18
© November 2008
Altera Corporation
HDL_INITIAL_FANOUT_LIMIT
4–91
HDL_INITIAL_FANOUT_LIMIT
Directs Integrated Synthesis to check the initial fan-out of each net in the netlist immediately after
elaboration but prior to any netlist optimizations. If the fan-out for a net exceeds the specified limit, then
Integrated Synthesis will issue a warning.
A logic option that directs Integrated Synthesis to issue warnings if a net in the post-elaboration netlist
exceeds the specified limit. The post-elaboration netlist is the initial netlist created by elaborating a single
entity in your HDL source. It is possible that the later synthesis and fitter optimizations may reduce (or
increase) the fan-out of the nets in the netlist.
This option is useful for identifying high-fanout signals early in the design process.
This option is ignored if applied to anything other than an entity or an instance of an entity.
Type
Integer
Device Support
Syntax
set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <entity name> <value>
set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo
© November 2008
Altera Corporation
4–92
HDL_MESSAGE_LEVEL
HDL_MESSAGE_LEVEL
Type
Enumeration
■
Level1
■
Level2
■
Level3
Device Support
Notes
Syntax
set_global_assignment -name HDL_MESSAGE_LEVEL <value>
Default Value
Level2
© November 2008
Altera Corporation
HDL_MESSAGE_OFF
4–93
HDL_MESSAGE_OFF
Type
Integer
The value must be between these two numbers, inclusive: 10000, 11000
Device Support
Notes
Syntax
set_global_assignment -name HDL_MESSAGE_OFF <value>
© November 2008
Altera Corporation
4–94
HDL_MESSAGE_ON
HDL_MESSAGE_ON
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name HDL_MESSAGE_ON <value>
© November 2008
Altera Corporation
IGNORE_CARRY_BUFFERS
4–95
IGNORE_CARRY_BUFFERS
Ignores CARRY_SUM buffers that are instantiated in the design. The Ignore CARRY Buffers option is
ignored if it is applied to anything other than an individual CARRY_SUM buffer or to a design entity
containing CARRY_SUM buffers. (This option also applies to MAX+PLUS II-style CARRY buffers.)
A logic option that ignores CARRY_SUM buffers that are instantiated in the design. (This option also
applies to MAX+PLUS II-style CARRY buffers.)
This option is ignored if it is applied to anything other than an individual CARRY_SUM buffer or to a
design entity containing CARRY_SUM buffers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name IGNORE_CARRY_BUFFERS <value>
set_global_assignment -name IGNORE_CARRY_BUFFERS -entity <entity name> <value>
set_instance_assignment -name IGNORE_CARRY_BUFFERS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name ignore_carry_buffers on
set_instance_assignment -name ignore_carry_buffers on -to foo
Default Value
Off
© November 2008
Altera Corporation
4–96
IGNORE_CASCADE_BUFFERS
IGNORE_CASCADE_BUFFERS
Ignores CASCADE buffers that are instantiated in the design. This option is ignored if it is applied to
anything other than an individual CASCADE buffer or a design entity containing CASCADE buffers.
A logic option that ignores CASCADE buffers that are instantiated in the design.
This option is ignored if it is applied to anything other than an individual CASCADE buffer or a design
entity containing CASCADE buffers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name IGNORE_CASCADE_BUFFERS <value>
set_global_assignment -name IGNORE_CASCADE_BUFFERS -entity <entity name> <value>
set_instance_assignment -name IGNORE_CASCADE_BUFFERS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name ignore_cascade_buffers on
set_instance_assignment -name ignore_cascade_buffers on -to foo
Default Value
Off
© November 2008
Altera Corporation
IGNORE_GLOBAL_BUFFERS
4–97
IGNORE_GLOBAL_BUFFERS
Ignores GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to
anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name IGNORE_GLOBAL_BUFFERS <value>
set_global_assignment -name IGNORE_GLOBAL_BUFFERS -entity <entity name> <value>
set_instance_assignment -name IGNORE_GLOBAL_BUFFERS -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
4–98
IGNORE_LCELL_BUFFERS
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anything
other than an individual LCELL buffer or a design entity containing LCELL buffers.
A logic option that ignores LCELL buffers that are instantiated in the design.
This option is ignored if it is applied to anything other than an individual LCELL buffer or a design entity
containing LCELL buffers.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
© November 2008
Altera Corporation
■
Stratix III
■
Stratix IV
4–99
Notes
Syntax
set_global_assignment -name IGNORE_LCELL_BUFFERS <value>
set_global_assignment -name IGNORE_LCELL_BUFFERS -entity <entity name> <value>
set_instance_assignment -name IGNORE_LCELL_BUFFERS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name ignore_lcell_buffers on
set_instance_assignment -name ignore_lcell_buffers on -to foo
Default Value
Off
© November 2008
Altera Corporation
4–100
IGNORE_MAX_FANOUT_ASSIGNMENTS
Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity, or the whole
design. For HCII migration, the Maximum Fan-Out assignments can cause mismatches in Revision
Compare. One can remove the Maximum Fan-Out assignments from the project but it is
inconvenient/impossible as some assignments are embedded in the HDL sources. One should turn on
this assignment to direct Quartus II to ignore the Maximum Fan-Out assignments.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS <value>
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -entity <entity name> <value>
© November 2008
Altera Corporation
4–101
set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -to <to> -entity <entity
name> <value>
Default Value
Off
© November 2008
Altera Corporation
4–102
IGNORE_ROW_GLOBAL_BUFFERS
IGNORE_ROW_GLOBAL_BUFFERS
Ignores ROW GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to
anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS <value>
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -entity <entity name> <value>
set_instance_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
IGNORE_SOFT_BUFFERS
4–103
IGNORE_SOFT_BUFFERS
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anything
other than an individual SOFT buffer or a design entity containing SOFT buffers.
A logic option that ignores SOFT buffers that are instantiated in the design.
This option is ignored if it is applied to anything other than an individual SOFT buffer or a design entity
containing SOFT buffers.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
© November 2008
Altera Corporation
4–104
■
Stratix III
■
Stratix IV
IGNORE_SOFT_BUFFERS
Notes
Syntax
set_global_assignment -name IGNORE_SOFT_BUFFERS <value>
set_global_assignment -name IGNORE_SOFT_BUFFERS -entity <entity name> <value>
set_instance_assignment -name IGNORE_SOFT_BUFFERS -to <to> -entity <entity name> <value>
Example
set_global_assignment -name ignore_soft_buffers off
set_instance_assignment -name ignore_soft_buffers off -to foo
Default Value
On
© November 2008
Altera Corporation
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
4–105
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
A logic option that instructs Analysis & Synthesis to ignore all translate_off and synthesis_off directives in
your Verilog and VHDL design files. You can use this option to disable these synthesis directives and
include previously ignored code during elaboration.
For example, you can use this option to compile code that was previously ignored by third-party synthesis
tools, e.g., megafunction declarations that were treated as black-boxes in other tools but that may be
compiled in the Quartus II software.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF <value>
Example
set_global_assignment -name ignore_translate_off_and_synthesis_off on
Default Value
Off
© November 2008
Altera Corporation
4–106
IGNORE_VERILOG_INITIAL_CONSTRUCTS
IGNORE_VERILOG_INITIAL_CONSTRUCTS
Instructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in your
Verilog HDL design files. By default, Analysis & Synthesis derives power-up conditions for your design
by elaborating these constructs. This option is provided for backwards compatibility with previous
versions of the Quartus II software that ignored these constructs by default. You can use this option to
restore the previous behavior of your design in the current version of the software.
A logic option that instructs Analysis & Synthesis to ignore initial constructs and variable declaration
assignments in your Verilog HDL design files. By default, Analysis & Synthesis derives power-up
conditions for your design by elaborating these constructs, ensuring that the power-up state of the
synthesized design matches the power-up state in simulation. This option is provided for backwards
compatibility with previous versions of the Quartus II software that ignored these constructs by default.
You can use this option to restore the previous behavior of your design in the current version of the
software.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS <value>
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -entity <entity name>
<value>
set_instance_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name ignore_verilog_initial_constructs off
Default Value
Off
© November 2008
Altera Corporation
IMPLEMENT_AS_CLOCK_ENABLE
4–107
IMPLEMENT_AS_CLOCK_ENABLE
Specifies that this node should function as a clock enable signal for one or more registers.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name IMPLEMENT_AS_CLOCK_ENABLE -to <to> -entity <entity name>
<value>
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IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
Implements the output of a primitive in a logic cell. You can apply this option to a logic function that
would not ordinarily be implemented in a logic cell, typically a combinatorial function such as an AND2
gate. Implementing the output of a primitive a logic cell makes it possible to observe its output in
simulation and timing analysis. However, because an additional logic cell is used, overall device
utilization will increase. This option does not insert an additional logic cell on a function that is already
implemented in a logic cell, such as a flipflop. This option is ignored if it is applied to anything other than
a primitive.
A logic option that implements the output of a primitive in a logic cell. You can apply this option to a logic
function that would not ordinarily be implemented in a logic cell, typically a combinational function such
as an AND2 gate. Implementing the output of a primitive a logic cell makes it possible to observe its
output in simulation and timing analysis. However, because an additional logic cell is used, overall device
utilization will increase. This option does not insert an additional logic cell on a function that is already
implemented in a logic cell, such as a register.
This option can be assigned to an individual node only.
Type
Boolean
Device Support
Syntax
set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL -to <to> -entity <entity
name> <value>
Example
set_instance_assignment -name implement_as_output_of_logic_cell on -to foo
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LCELL_INSERTION
4–109
LCELL_INSERTION
Allows you to insert one or more logic cells between two nodes without changing the design files. The
value you assign this option is the number of logic cells you want to insert. The inserted logic cell(s) act as
a simple buffer and do not alter the functionality of the design. For more detailed information, go to
Quartus II online help.
Type
Integer
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_instance_assignment -name LCELL_INSERTION -to <to> -entity <entity name> <value>
set_instance_assignment -name LCELL_INSERTION -from <from> -to <to> -entity <entity name>
<value>
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Altera Corporation
4–110
LIMIT_AHDL_INTEGERS_TO_32_BITS
LIMIT_AHDL_INTEGERS_TO_32_BITS
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS <value>
Default Value
Off
© November 2008
Altera Corporation
MAX7000_FANIN_PER_CELL
4–111
MAX7000_FANIN_PER_CELL
Specifies the maximum fan-in per macrocell. Legal integer values, in percentage terms, range from 20
through 100.
A logic option that specifies the maximum fan-in per macrocell. Legal integer values, in percentage terms,
range from 20 through 100.
This option is useful for improving a design's fitting. The Maximum Fan-in Per Macrocell option allows
you to spread routing resources and reduce congestion in a design.
This option defaults to 100.
Type
Integer
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_FANIN_PER_CELL <value>
set_global_assignment -name MAX7000_FANIN_PER_CELL -entity <entity name> <value>
set_instance_assignment -name MAX7000_FANIN_PER_CELL -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name max7000_fanin_per_cell 20
set_instance_assignment -name max7000_fanin_per_cell 20 -to foo
Default Value
100
Old Names
Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
4–112
MAX7000_IGNORE_LCELL_BUFFERS
MAX7000_IGNORE_LCELL_BUFFERS
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anything
other than an individual LCELL buffer or a design entity containing LCELL buffers.
A logic option that ignores LCELL buffers that are instantiated in the design.
This option is ignored if it is applied to anything other than an individual LCELL buffer or a design entity
containing LCELL buffers.
Type
Enumeration
■
Auto
■
Off
■
On
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS <value>
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -entity <entity name> <value>
set_instance_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name max7000_ignore_lcell_buffers
set_instance_assignment -name max7000_ignore_lcell_buffers
on
on -to foo
Default Value
AUTO
Old Names
Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
MAX7000_IGNORE_SOFT_BUFFERS
4–113
MAX7000_IGNORE_SOFT_BUFFERS
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anything
other than an individual SOFT buffer or a design entity containing SOFT buffers.
A logic option that ignores SOFT buffers that are instantiated in the design.
This option is ignored if it is applied to anything other than an individual SOFT buffer or a design entity
containing SOFT buffers.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS <value>
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -entity <entity name> <value>
set_instance_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name max7000_ignore_soft_buffers
on
set_instance_assignment -name max7000_ignore_soft_buffers
on -to foo
Default Value
Off
Old Names
Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A
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4–114
MAX7000_OPTIMIZATION_TECHNIQUE
This option defaults to Speed.
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name max7000_optimization_technique balanced
Default Value
Speed
© November 2008
Altera Corporation
4–115
Old Names
Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
4–116
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of Compiler-synthesized parallel expander product
terms.
A logic option that specifies the maximum allowable length of a chain of Compiler-synthesized parallel
expander product terms.
Type
Integer
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH <value>
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -entity <entity name>
<value>
set_instance_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -to <to> -entity
Example
set_global_assignment -name max7000_parallel_expander_chain_length
3
Default Value
4
Old Names
Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
MAXII_OPTIMIZATION_TECHNIQUE
4–117
MAXII_OPTIMIZATION_TECHNIQUE
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
MAX II
Notes
Syntax
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name MAXII_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name maxii_optimization_technique speed
Default Value
Balanced
Old Names
Optimization Technique -- MAX II
TSUNAMI_OPTIMIZATION_TECHNIQUE
© November 2008
Altera Corporation
4–118
MAX_AUTO_GLOBAL_REGISTER_CONTROLS
Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding
clock signals) as global signals that are made available throughout the device on the global routing paths.
Depending on the target device family, these control signals can include asynchronous clear and load,
synchronous clear and load, clock enable, and preset signals.If you want to prevent the Compiler from
automatically selecting a particular signal as global register control signal, set the Global Signal option to
A logic option that allows the Compiler to choose signals that feed the most control signal inputs to
registers (excluding clock signals) as global signals made available throughout the device on the global
routing paths. Depending on the device family, these control signals can include asynchronous clear,
synchronous clear, asynchronous load, synchronous load, preset, clock enable, and output enable signals.
This option is ignored if it is assigned to anything other than a design entity. If you want to prevent the
Compiler from automatically selecting a particular signal as a global register control signal, set the Global
Signal logic option to Off for that signal.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Syntax
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS <value>
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -entity <entity name>
<value>
set_instance_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name max_auto_global_register_controls
set_instance_assignment -name max_auto_global_register_controls
off
off -to foo
Default Value
On
Old Names
© November 2008
Altera Corporation
4–119
Auto Global Register Control Signals -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
4–120
MAX_BALANCING_DSP_BLOCKS
Allows you to specify the maximum number of DSP blocks that the DSP block balancer will assume exist
in the current device for each partition. This option overrides the usual method of using the maximum
number of DSP blocks the current device supports. For HardCopy II devices, the number of DSP blocks
represents the number of DSP blocks used in the equivalent Stratix II device. This option is useful for
HardCopy II device migration, where the number of DSP blocks that can be implemented in a HardCopy
II device is more than the number of DSP blocks that can be implemented in its equivalent Stratix II
device.This option is also useful in incremental compilation to set different DSP block usage limits for
different partitions.
A logic option that allows you to specify the maximum number of DSP blocks that the DSP block balancer
will assume exist in the current device for each partition. This option overrides the usual method of using
the maximum number of DSP blocks the current device supports. For HardCopy II devices, the number of
DSP blocks represents the number of DSP blocks used in the equivalent Stratix II device.
This option is useful for HardCopy II device migration, where the number of DSP blocks that can be
implemented in a HardCopy II device is more than the number of DSP blocks that can be implemented in
its equivalent Stratix II device.
This option is also useful in incremental compilation to set different DSP block usage limits for different
partitions.
This option can be used as a project-wide option or on a specific partition by setting the assignment on the
instance name of the partition root. The assignment on a partition overrides the global assignment (if any)
for that particular partition.
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
4–121
Notes
Syntax
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS <value>
set_instance_assignment -name MAX_BALANCING_DSP_BLOCKS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name max_balancing_dsp_blocks 4
set_instance_assignment -name max_balancing_dsp -to
"my_partition_root_entity:my_partition_root_entity_inst"
Default Value
-1 (Unlimited)
© November 2008
Altera Corporation
4–122
MAX_FANOUT
MAX_FANOUT
Directs the Compiler to control the number of destinations the specified node feeds so the fan-out count
does not exceed the value specified as the maximum number of fan-out allowed from the node.
A logic option that directs the Compiler to control the number of destinations the specified node feeds so
the fan-out count does not exceed the value specified as the maximum number of fan-out allowed from the
node.
This option is useful for reducing the load of critical signals, which improves performance.
This option is ignored if it is applied to anything other than a register or a logic cell buffer, or a design
entity that contains registers or logic cell buffers.
Type
Integer
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
MAX_FANOUT
4–123
Syntax
set_global_assignment -name MAX_FANOUT -entity <entity name> <value>
set_instance_assignment -name MAX_FANOUT -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name max_fanout 10 -to foo
© November 2008
Altera Corporation
4–124
MAX_RAM_BLOCKS_M4K
MAX_RAM_BLOCKS_M4K
Allows you to specify the maximum number of M4K/M9K memory blocks that the Compiler may utilize
for a device. This option overrides the usual method of using the maximum number of M4K/M9K
memory blocks the current device supports, when the value is non-negative and is less than the maximum
number of M4K/M9K memory blocks available on the current device.
A logic option that allows you to specify the maximum number of M4K/M9K memory blocks that the
Compiler may utilize for a device. This option overrides the usual method of using the maximum number
of M4K/M9K memory blocks the current device supports, when the value is non-negative and is less than
the maximum number of M4K/M9K memory blocks available on the current device.
This option is also useful in incremental compilation to set different M4K/M9K memory block usage
limits for different partitions.
This option is useful for device migration.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
MAX_RAM_BLOCKS_M4K
4–125
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_M4K <value>
set_instance_assignment -name MAX_RAM_BLOCKS_M4K -to <to> -entity <entity name> <value>
Example
set_global_assignment -name max_ram_blocks_m4k 4
Default Value
-1 (Unlimited)
See Also
■
"MAX_RAM_BLOCKS_M512" on page 4–126
■
"MAX_RAM_BLOCKS_MRAM" on page 4–128
© November 2008
Altera Corporation
4–126
MAX_RAM_BLOCKS_M512
MAX_RAM_BLOCKS_M512
Allows you to specify the maximum number of M512 memory blocks that the Compiler may utilize for a
device. This option overrides the usual method of using the maximum number of M512 memory blocks
the current device supports, when the value is non-negative and is less than the maximum number of
M512 memory blocks available on the current device.
A logic option that allows you to specify the maximum number of M512 memory blocks that the Compiler
may utilize for a device. This option overrides the usual method of using the maximum number of M512
memory blocks the current device supports, when the value is non-negative and is less than the maximum
number of M512 memory blocks available on the current device.
This option is also useful in incremental compilation to set different M512 memory block usage limits for
different partitions.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_M512 <value>
set_instance_assignment -name MAX_RAM_BLOCKS_M512 -to <to> -entity <entity name> <value>
Example
set_global_assignment -name max_ram_blocks_m512 4
© November 2008
Altera Corporation
MAX_RAM_BLOCKS_M512
4–127
Default Value
-1 (Unlimited)
See Also
■
"MAX_RAM_BLOCKS_M4K" on page 4–124
■
"MAX_RAM_BLOCKS_MRAM" on page 4–128
© November 2008
Altera Corporation
4–128
MAX_RAM_BLOCKS_MRAM
MAX_RAM_BLOCKS_MRAM
Allows you to specify the maximum number of M-RAM/M144K memory blocks that the Compiler may
utilize for a device. This option overrides the usual method of using the maximum number of
M-RAM/M144K memory blocks the selected device supports, when the value is non-negative and is less
than the maximum number of M-RAM/M144K memory blocks available on the current device.
A logic option that allows you to specify the maximum number of M-RAM/M144K memory blocks that
the Compiler may utilize for a device. This option overrides the usual method of using the maximum
number of M-RAM/M144K memory blocks the selected device supports, when the value is non-negative
and is less than the maximum number of M-RAM/M144K memory blocks available on the current device.
This option is also useful in incremental compilation to set different M-RAM/M144K memory block usage
limits for different partitions.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_MRAM <value>
set_instance_assignment -name MAX_RAM_BLOCKS_MRAM -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
MAX_RAM_BLOCKS_MRAM
4–129
Example
set_global_assignment -name max_ram_blocks_mram 4
Default Value
-1 (Unlimited)
See Also
■
"MAX_RAM_BLOCKS_M512" on page 4–126
■
"MAX_RAM_BLOCKS_M4K" on page 4–124
© November 2008
Altera Corporation
4–130
MERCURY_CARRY_CHAIN_LENGTH
MERCURY_CARRY_CHAIN_LENGTH
Type
Integer
Device Support
■
Mercury
Notes
Syntax
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name MERCURY_CARRY_CHAIN_LENGTH -to <to> -entity <entity name>
<value>
Default Value
48
Old Names
Carry Chain Length -- Mercury
© November 2008
Altera Corporation
MERCURY_OPTIMIZATION_TECHNIQUE
4–131
MERCURY_OPTIMIZATION_TECHNIQUE
Type
Enumeration
■
Area
■
Speed
Device Support
■
Mercury
Notes
Syntax
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name mercury_optimization_technique speed
Default Value
Area
Old Names
Optimization Technique -- Mercury
© November 2008
Altera Corporation
4–132
MUX_RESTRUCTURE
MUX_RESTRUCTURE
Allows the Compiler to reduce the number of logic elements required to implement multiplexers in a
design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks
multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced
number of logic elements. You can select the 'On' setting to minimize your design area; it will decrease
logic element usage but may negatively affect design clock speed (fMAX). You can select the 'Off' to
disable multiplexer restructuring; it does not decrease logic element usage and does not affect design clock
speed (fMAX). You may select 'Auto' setting to allow the Quartus II software to determine whether
multiplexer restructuring should be enabled. The Quartus II software uses other synthesis settings, for
example, the Optimization Technique option, to determine if multiplexer restructuring should be applied
to the design; the 'Auto' setting will decrease logic element usage but may negatively affect design clock
speed (fMAX).
A logic option that allows the Compiler to reduce the number of logic elements required to implement
multiplexers in a design.
The following three settings are available: a) On: Allows the Compiler to minimize your design area. This
setting will decrease logic element usage but may negatively affect design clock speed (fMAX). b) Off:
Multiplexer restructuring is disabled in the design. This setting does not decrease logic element usage and
does not affect design clock speed (fMAX). c) Auto: Allows the Quartus II software to determine whether
multiplexer restructuring should be enabled. The Quartus II software uses other synthesis settings, for
example, the Optimization Technique option, to determine if multiplexer restructuring should be applied
to the design. This setting will decrease logic element usage but may negatively affect design clock speed
(fMAX).
This option is useful if your design contains buses of fragmented multiplexers. This option restructures
multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced
number of logic elements. The Restructure Multiplexers option works on entire trees of multiplexers.
Multiplexers may arise in different parts of the design through VHDL or Verilog constructs such as "if",
"case", or "?:". When multiplexers from one part of the design feed multiplexers in another part of the
design, trees of multiplexers are formed. The Restructure Multiplexers option identifies buses of
multiplexer trees that have a similar structure. Multiplexer buses occur most often as a result of
multiplexing together vectors in Verilog, or array types such as STD_LOGIC_VECTOR in VHDL. When
turned on, the Restructure Multiplexers option optimizes the structure of each multiplexer bus for the
target device to reduce the overall number of logic elements used in the design.
Type
Enumeration
■
Auto
■
Off
■
On
Device Support
■
Arria GX
© November 2008
Altera Corporation
MUX_RESTRUCTURE
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
4–133
Notes
Syntax
set_global_assignment -name MUX_RESTRUCTURE <value>
set_global_assignment -name MUX_RESTRUCTURE -entity <entity name> <value>
set_instance_assignment -name MUX_RESTRUCTURE -to <to> -entity <entity name> <value>
Example
set_global_assignment -name mux_restructure off
set_instance_assignment -name mux_restructure on -to accel
Default Value
Auto
© November 2008
Altera Corporation
4–134
NOT_GATE_PUSH_BACK
NOT_GATE_PUSH_BACK
Allows the Compiler to push an inversion (that is, a NOT gate) back through a register and implement it
on that register's data input if it is necessary to implement the design. If this option is turned on, a register
may power up to an active-high state, so it may need to be explicitly cleared during initial operation of the
device. This option is ignored if it is applied to anything other than an individual register or a design
entity containing registers. If it is applied to an output pin that is directly fed by a register, it is
automatically transferred to that register.
A logic option that allows the Compiler to push an inversion (that is, a NOT gate) back through a register
and implement it on that register's data input if it is necessary to implement the design. If this option is
turned on, a register may power up to an active-high state, so it may need to be explicitly cleared during
initial operation of the device.
This option is ignored if it is applied to anything other than an individual register or a design entity
containing registers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name NOT_GATE_PUSH_BACK -entity <entity name> <value>
set_instance_assignment -name NOT_GATE_PUSH_BACK -to <to> -entity <entity name> <value>
set_global_assignment -name NOT_GATE_PUSH_BACK <value>
Example
set_global_assignment -name not_gate_push_back off
set_instance_assignment -name not_gate_push_back off -to reg
Default Value
On
© November 2008
Altera Corporation
NUMBER_OF_INVERTED_REGISTERS_REPORTED
4–135
NUMBER_OF_INVERTED_REGISTERS_REPORTED
This logic option Allows you to specify the maximum number of inverted registers that the Synthesis
Report should display.
Legal values are integers starting from 0. The value of 0 means that there will be no report panel about
inverted registers in the Synthesis report.
The default value is 100.
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED <value>
Example
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 200
Default Value
100
© November 2008
Altera Corporation
4–136
NUMBER_OF_REMOVED_REGISTERS_REPORTED
NUMBER_OF_REMOVED_REGISTERS_REPORTED
This logic option Allows you to specify the maximum number of removed registers that the Synthesis
Report should display.
Legal values are integers starting from 0. The value of 0 means that there will be no report panel about
removed registers in the Synthesis report.
The default value is 100.
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED <value>
Example
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 200
Default Value
100
© November 2008
Altera Corporation
OPTIMIZATION_TECHNIQUE
4–137
OPTIMIZATION_TECHNIQUE
This option is applicable to Stratix IV.
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
HardCopy III
■
Stratix IV
Notes
Syntax
set_global_assignment -name OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name optimization_technique speed
Default Value
Balanced
Old Names
Optimization Technique -- Stratix IV
© November 2008
Altera Corporation
4–138
OPTIMIZE_POWER_DURING_SYNTHESIS
Controls the power-driven compilation setting of Analysis & Synthesis. This option determines how
aggressively Analysis & Synthesis optimizes the design for power. If this option is set to 'Off', Analysis &
Synthesis does not perform any power optimizations. If this option is set to 'Normal compilation', Analysis
& Synthesis performs power optimizations as long as they are not expected to reduce design performance.
When this option is set to 'Extra effort', Analysis & Synthesis will perform additional power optimizations
which may reduce design performance.
A logic option that controls the power-driven compilation setting of Analysis & Synthesis. This option
determines how aggressively Analysis & Synthesis optimizes the design for power. If this option is set to
'Off', Analysis & Synthesis does not perform any power optimizations. If this option is set to 'Normal
compilation', Analysis & Synthesis performs power optimizations as long as they are not expected to
reduce design performance. When this option is set to 'Extra effort', Analysis & Synthesis will perform
additional power optimizations which may reduce design performance.
This option defaults to "Normal compilation".
Type
Enumeration
■
Extra effort
■
Normal compilation
■
Off
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
4–139
Notes
Syntax
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS <value>
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -entity <entity name>
<value>
set_instance_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name optimize_power_during_synthesis off
Default Value
Normal compilation
© November 2008
Altera Corporation
4–140
PARALLEL_EXPANDER_CHAIN_LENGTH
PARALLEL_EXPANDER_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of Compiler-synthesized parallel expander product
terms.
Type
Integer
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH <value>
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH -to <to> -entity <entity
name> <value>
Default Value
16
Old Names
Parallel Expander Chain Length -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur
© November 2008
Altera Corporation
PARAMETER
4–141
PARAMETER
Type
String
Device Support
Notes
Syntax
set_parameter <value>
set_parameter -entity <entity name> <value>
© November 2008
Altera Corporation
4–142
POWER_UP_LEVEL
POWER_UP_LEVEL
Causes a register to power up with the specified logic level, either High (1) or Low (0). If this option is
specified for an input pin, it is automatically transferred to the register that is driven by the pin if the
following conditions are present: (1) there is no intervening logic, other than inversion, between the pin
and the register; (2) the input pin drives the data input of the register; and (3) the input pin does not
fan-out to any other logic. If this option is specified for an output or bidirectional pin, it is automatically
transferred to the register that feeds the pin if: (1) there is no intervening logic, other than inversion,
between the register and the pin; and (2) the register does not fan-out to any other logic. You can assign
this option to any register, or to a pin with any logic configuration other than those described above. You
can also assign this option to a design entity containing registers if you want to set the power level for all
registers in the design entity. In order for the register to power up with the specified logic level, the
Compiler may perform NOT Gate Push-Back on the register.
A logic option that causes a register to power up with the specified logic level, either High (1) or Low (0).
If this option is specified for an input pin, it is automatically transferred to the register that is driven by the
pin if there is no intervening logic, other than inversion, between the pin and the register.
If this option is specified for an output or bidirectional pin, it is automatically transferred to the register
that feeds the pin if there is no intervening logic, other than inversion, between the register and the pin.
You can assign this option to any register, registered logic cell WYSIWYG primitive, or to a pin with any
logic configuration other than those described above. If this option is assigned to a registered logic cell
WYSIWYG primitive, you must turn on the Perform WYSIWYG Primitive Resynthesis logic option for it to
take effect. You can also assign this option to a design entity containing registers if you want to set the
power level for all registers in the design entity. In order for the register to power up with the specified
logic level, the Compiler may perform NOT Gate Push-Back on the register.
Type
Enumeration
■
High
■
Low
Device Support
Notes
Syntax
set_global_assignment -name POWER_UP_LEVEL -entity <entity name> <value>
set_instance_assignment -name POWER_UP_LEVEL -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name power_up_level low -to foo
See Also
■
"ALLOW_POWER_UP_DONT_CARE" on page 4–17
© November 2008
Altera Corporation
PRESERVE_FANOUT_FREE_NODE
4–143
PRESERVE_FANOUT_FREE_NODE
Prevents a register that has no fan-out from being removed during synthesis.
A logic option that specifies that the register should be preserved in the design even when it becomes
fan-out free.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name preserve_fanout_free_node on -to reg
© November 2008
Altera Corporation
4–144
PRESERVE_HIERARCHICAL_BOUNDARY
PRESERVE_HIERARCHICAL_BOUNDARY
Determines how strictly the hierarchical boundaries between design entities should be maintained during
logic synthesis. You can select the 'Relaxed' setting to allow only partial cross-boundary optimization. The
'Relaxed' setting also allows you to observe all of the entity's non-trivial inputs and outputs in simulation
and timing analysis; it may also reduce compilation time. You can select the 'Firm' setting to strictly
maintain hierarchical boundaries. This setting may increase compilation time, increase logic cell count,
and negatively affect design performance. You can select the 'Off' setting to completely ignore hierarchical
boundaries. The 'Off' setting allows unlimited optimization and yields the greatest logic minimization.
The Preserve Hierarchical Boundary option applies only to the design entity to which it is assigned;
lower-level entities do not inherit their parent entity's setting for this option.
A logic option that determines how strictly the hierarchical boundaries between design entities should be
maintained during logic synthesis.
You can choose one of the following settings: a) Off: Completely ignores boundaries and therefore allows
unlimited optimization. This setting provides the greatest logic minimization. b) Relaxed: Allows only
partial cross-boundary optimization, which may reduce the compilation time. Non-trivial inputs and
outputs of the entity are visible during simulation and timing analysis. c) Firm: Strictly maintains
hierarchical boundaries. This setting may increase compilation time, increase logic cell count, and
negatively affect design performance
This option applies only to the design entity to which it is assigned; lower-level entities do not inherit their
parent entity's setting for this option.
Type
Enumeration
■
Firm
■
Off
■
Relaxed
Device Support
Syntax
set_global_assignment -name PRESERVE_HIERARCHICAL_BOUNDARY -entity <entity name> <value>
set_instance_assignment -name PRESERVE_HIERARCHICAL_BOUNDARY -to <to> -entity <entity
name> <value>
Example
set_instance_assignment -name preserve_hierarchical_boundary firm -to foo
© November 2008
Altera Corporation
PRESERVE_REGISTER
4–145
PRESERVE_REGISTER
Prevents a register from minimizing away during synthesis and prevents sequential netlist optimizations.
Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers.
A logic option that prevents a register from minimizing away during synthesis and prevents sequential
netlist optimizations. Sequential netlist optimizations can eliminate redundant registers and registers with
constant drivers.
This option is useful for preserving a register so you can observe it during Simulation. It is also useful for
creating a preliminary version of the design in which secondary signals are not specified. This option is
ignored if the register does not drive anything, in which case, the register will be removed by the netlist
optimization.
This option is ignored if it is applied to anything other than a register or a design entity that contains
registers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name PRESERVE_REGISTER -entity <entity name> <value>
set_instance_assignment -name PRESERVE_REGISTER -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_register on -to foo
© November 2008
Altera Corporation
4–146
PRE_MAPPING_RESYNTHESIS
PRE_MAPPING_RESYNTHESIS
Specifies that the Quartus II software should perform a resynthesis optimization step immediately before
technology mapping. The 'On' setting increases design performance; it will increase design clock speed
(fMAX) but may also slightly increase logic element usage and compilation time. The 'Off' selection
disables this optimization.
Type
Boolean
Device Support
Syntax
set_global_assignment -name PRE_MAPPING_RESYNTHESIS <value>
Default Value
Off
© November 2008
Altera Corporation
REMOVE_DUPLICATE_REGISTERS
4–147
REMOVE_DUPLICATE_REGISTERS
Removes a register if it is identical to another register. If two registers generate the same logic, the second
one will be deleted and the first one will be made to fan out to the second one's destinations. Also, if the
deleted register has different logic option assignments, they will be ignored. This option is useful if you
wish to prevent the Compiler from removing duplicate registers that you have used deliberately. You can
do this by setting the option to Off. This option is ignored if it is applied to anything other than an
individual register or a design entity containing registers.
A logic option that removes a register if it is identical to another register. If two registers generate the same
logic, the second one will be deleted and the first one will be made to fan-out to the second one's
destinations. Also, if the deleted register has different logic option assignments, they will be ignored. This
option is useful if you wish to prevent the Compiler from removing duplicate registers that you used
deliberately.
This option is ignored if it is assigned to anything other than an individual register or a design entity
containing registers.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS <value>
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS -entity <entity name> <value>
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name remove_duplicate_registers off
set_instance_assignment -name remove_duplicate_registers off -to foo
Default Value
On
Old Names
DUPLICATE_REGISTER_EXTRACTION
© November 2008
Altera Corporation
4–148
REMOVE_REDUNDANT_LOGIC_CELLS
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a
circuit for area and speed. This option is ignored if it is applied to anything other than a design entity.
A logic option that removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on
optimizes a circuit for area and speed.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
© November 2008
Altera Corporation
■
4–149
Stratix IV
Notes
Syntax
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity <entity name> <value>
set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to <to> -entity <entity
name> <value>
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS <value>
Example
set_global_assignment -name remove_redundant_logic_cells on
set_instance_assignment -name remove_redundant_logic_cells on -to node
Default Value
Off
© November 2008
Altera Corporation
4–150
RESYNTHESIS_OPTIMIZATION_EFFORT
RESYNTHESIS_OPTIMIZATION_EFFORT
Type
Enumeration
■
Low
■
Normal
Device Support
Notes
Syntax
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT -section_id <section
identifier> <value>
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT -entity <entity name>
Default Value
Normal, requires section identifier
© November 2008
Altera Corporation
RESYNTHESIS_PHYSICAL_SYNTHESIS
4–151
RESYNTHESIS_PHYSICAL_SYNTHESIS
Type
Enumeration
■
ADVANCED
■
Normal
Device Support
Notes
Syntax
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -section_id <section
identifier> <value>
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -entity <entity name>
Default Value
Normal, requires section identifier
© November 2008
Altera Corporation
4–152
RESYNTHESIS_RETIMING
RESYNTHESIS_RETIMING
Type
Enumeration
■
CORE
■
Full
■
Off
Device Support
Notes
Syntax
set_global_assignment -name RESYNTHESIS_RETIMING -section_id <section identifier>
<value>
set_global_assignment -name RESYNTHESIS_RETIMING -entity <entity name> -section_id
Default Value
FULL, requires section identifier
© November 2008
Altera Corporation
SAFE_STATE_MACHINE
4–153
SAFE_STATE_MACHINE
Tells the compiler to implement state machines that can recover gracefully from an illegal state.
A logic option that controls whether or not the implemented state machine(s) can recover gracefully from
an illegal state.
This option can be applied globally or to a specific entity or node.
Implementation of such safe state machines can result in some area increase.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name SAFE_STATE_MACHINE -entity <entity name> <value>
set_instance_assignment -name SAFE_STATE_MACHINE -to <to> -entity <entity name> <value>
set_global_assignment -name SAFE_STATE_MACHINE <value>
Example
set_global_assignment -name safe_state_machine on
set_instance_assignment -name safe_state_machine on -to foo
Default Value
Off
See Also
■
■
■
© November 2008
Altera Corporation
4–154
SAVE_DISK_SPACE
SAVE_DISK_SPACE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name SAVE_DISK_SPACE <value>
Default Value
On
© November 2008
Altera Corporation
SEARCH_PATH
4–155
SEARCH_PATH
Type
String
Device Support
Notes
Syntax
set_global_assignment -name SEARCH_PATH <value>
© November 2008
Altera Corporation
4–156
SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT <value>
Default Value
On
© November 2008
Altera Corporation
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
4–157
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
Type
Boolean
Device Support
Syntax
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES <value>
Default Value
Off
© November 2008
Altera Corporation
4–158
STATE_MACHINE_PROCESSING
Specifies the processing style used to compile a state machine. You can use your own 'User-Encoded' style,
or select 'One-Hot', 'Minimal Bits', 'Gray', 'Johnson', 'Sequential' or 'Auto' (Compiler-selected) encoding.
A logic option that specifies the processing style used to compile a state machine.
The following settings are available: a) Auto: Allows the Compiler to choose the best encoding for the state
machine. b) Minimal Bits: Uses the minimal number of bits to encode the state machine. c) One-Hot:
Encodes the state machine in the one-hot style. d) User-Encoded: Encodes the state machine in the manner
specified by the user. e) Gray: Encodes the state machine in the Gray style. f) Johnson: Encodes the state
machine in the Johnson style. g) Sequential: Encode the state machine in the sequential binary style.
Type
Enumeration
■
Auto
■
Gray
■
Johnson
■
Minimal Bits
■
One-Hot
■
Sequential
■
User-Encoded
Device Support
Notes
Syntax
set_global_assignment -name STATE_MACHINE_PROCESSING -entity <entity name> <value>
set_instance_assignment -name STATE_MACHINE_PROCESSING -to <to> -entity <entity name>
<value>
set_global_assignment -name STATE_MACHINE_PROCESSING <value>
Example
set_global_assignment -name state_machine_processing "one-hot"
set_instance_assignment -name state_machine_processing "one-hot" -to foo
Default Value
Auto
See Also
■
© November 2008
Altera Corporation
■
4–159
© November 2008
Altera Corporation
4–160
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_
THRESHOLD_SELECT
Type
Boolean
Device Support
■
Arria GX
■
Stratix GX
■
Stratix II GX
Syntax
set_global_assignment -name
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT <value>
Default Value
Off
© November 2008
Altera Corporation
STRATIXII_CARRY_CHAIN_LENGTH
4–161
STRATIXII_CARRY_CHAIN_LENGTH
Type
Integer
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name STRATIXII_CARRY_CHAIN_LENGTH -to <to> -entity <entity
name> <value>
Default Value
70
Old Names
ARMSTRONG_CARRY_CHAIN_LENGTH
Carry Chain Length -- Stratix II/Stratix III
© November 2008
Altera Corporation
4–162
STRATIXII_OPTIMIZATION_TECHNIQUE
This option is applicable to Stratix II, Stratix III, HardCopy II, Stratix II GX, and Arria GX devices.
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
■
Stratix III
Notes
Syntax
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE -entity <entity name>
<value>
set_instance_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name stratixii_optimization_technique speed
© November 2008
Altera Corporation
4–163
Default Value
Balanced
Old Names
ARMSTRONG_OPTIMIZATION_TECHNIQUE
Optimization Technique -- Stratix II/III/HardCopy II/Stratix II GX/Arria GX
© November 2008
Altera Corporation
4–164
STRATIX_CARRY_CHAIN_LENGTH
STRATIX_CARRY_CHAIN_LENGTH
Type
Integer
Device Support
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
Notes
Syntax
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name STRATIX_CARRY_CHAIN_LENGTH -to <to> -entity <entity name>
<value>
Default Value
70
Old Names
Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III
© November 2008
Altera Corporation
STRATIX_OPTIMIZATION_TECHNIQUE
4–165
This option is applicable to Stratix and Stratix GX devices.
Type
Enumeration
■
Area
■
Balanced
■
Speed
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -entity <entity name> <value>
set_instance_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name stratix_optimization_technique speed
Default Value
Balanced
Old Names
© November 2008
Altera Corporation
4–166
Optimization Technique -- Stratix/Stratix GX
YEAGER_OPTIMIZATION_TECHNIQUE
© November 2008
Altera Corporation
STRICT_RAM_RECOGNITION
4–167
When this option is ON, the Compiler is only allowed to replace RAM if the hardware matches the design
exactly.
This option specifies the compiler is only allowed to replace RAM if the hardware matches the design
exactly.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
4–168
Syntax
set_global_assignment -name STRICT_RAM_RECOGNITION <value>
set_global_assignment -name STRICT_RAM_RECOGNITION -entity <entity name> <value>
set_instance_assignment -name STRICT_RAM_RECOGNITION -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name strict_ram_recognition on
set_global_assignment -name strict_ram_recognition on -to foo
Default Value
Off
© November 2008
Altera Corporation
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
4–169
This setting specifies the maximum number of registers in a row to be considered as a synchronization
chain. Synchronization chains are sequences of registers with the same clock, no fanout in between, such
that the first register is fed by a pin, or by logic in another clock domain. These registers will be considered
for metastability analysis (available for some families), and are also protected from optimizations such as
retiming. When gate-level retiming is turned on, these registers will not be moved. The default length is
set to two.
Type
Integer
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH <value>
© November 2008
Altera Corporation
4–170
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -entity <entity name>
<value>
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -to <to> -entity
Default Value
2
Old Names
ADV_NETLIST_OPT_METASTABLE_REGS
© November 2008
Altera Corporation
SYNTHESIS_EFFORT
4–171
SYNTHESIS_EFFORT
This logic option can be used to choose the synthesis effort level. The default value is "Auto", which means
synthesis will go through all its steps. When "Fast" is selected, synthesis will skip a number of steps which
makes it approximately 30% faster. This may be at the cost of performance and resources.
It is recommended to only use effort level "Fast" when the fitter early timing estimate flow is used. This is
because the "Fast" synthesis results produces a netlist that is slightly harder for the fitter to route, thus
making the fitter slower, which cancels out the speed-up of synthesis. The fitter early timing estimate
runtime will not be affected by the synthesis effort level.
Type
Enumeration
■
Auto
■
Fast
Device Support
Notes
Syntax
set_global_assignment -name SYNTHESIS_EFFORT <value>
Example
set_global_assignment -name synthesis_effort fast
Default Value
Auto
© November 2008
Altera Corporation
4–172
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
When this option is set to On, synthesis will keep the synchronous clear/preset behavior when remap I/O
wysiwyg primitives (from other device families) using DDIO INPUT feature to the targeted device family.
A logic option that, when set to On, will keep synthesis maintain the same synchronous clear/preset
behavior for DDIO INPUT feature when unmapping I/O WYSIWYG primitive
from other device family to the new targeted device family. When it's off, synthesis will simply use the
targeted family's DDIO INPUT feature for implementation. And that
might have slighly different behavior than the original targeted family of the wysiwyg primitive. For
example, Stratix III device family's DDIO INPUT will behave differently
than Stratix II when synchronous clear/preset is used. For Stratix III, the synchronous clear/preset will
affect all 3 registers while it only affects the two capture resigers
in Stratix II.
Type
Boolean
Device Support
Syntax
set_global_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
set_instance_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
-to <to> -entity <entity name> <value>
set_global_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
<value>
Example
set_global_assignment -name synthesis_keep_synch_clear_preset_behavior_in_unmapper on
set_instance_assignment -name synthesis_keep_synch_clear_preset_behavior_in_unmapper on
-to foo
© November 2008
Altera Corporation
SYNTH_CLOCK_MUX_PROTECTION
4–173
SYNTH_CLOCK_MUX_PROTECTION
A logic option that causes the multiplexers in the clock network to be decomposed to 2to1 multiplexer
trees, and protected from being merged with, or transferred to, other logic.
This option is important for the TimeQuest timing analyzer to understand clock behavior. Note that a
clock multiplexer can cause glitches. It is recommended to use a <A
HREF="reference.chm::/glossary/def_clk_ctrl_block.htm">clock control block</A> instead.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION <value>
Example
set_global_assignment -name synth_clock_mux_protection off
Default Value
On
© November 2008
Altera Corporation
4–174
SYNTH_CRITICAL_CLOCK
SYNTH_CRITICAL_CLOCK
Specifies that all combinational logic in the given clock domain, or between the given clock domains,
should be mapped with optimization technique speed
A logic option that specifies that all combinational logic in the given clock domain, or between the given
clock domains, should be mapped with optimization technique speed.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name SYNTH_CRITICAL_CLOCK -to <to> -entity <entity name>
<value>
set_instance_assignment -name SYNTH_CRITICAL_CLOCK -from <from> -to <to> -entity <entity
name> <value>
Example
set_instance_assignment -name synth_critical_clock on -to clock
set_instance_assignment -name synth_critical_clock on -from clk1 -to clk2
© November 2008
Altera Corporation
SYNTH_GATED_CLOCK_CONVERSION
4–175
SYNTH_GATED_CLOCK_CONVERSION
Causes gated clocks are converted to use clock enables if clock enables are not used in the original design.
This option is for ASIC prototyping flow on FPGA.
A logic option causes gated clocks are converted to use clock enables if clock enables are not used in the
original design. Clock gating logic can contain AND, OR, MUX and NOT gates.
This option is for ASIC prototyping flow on FPGA, and only works with TimeQuest. Please refer to
Quartus II Development Software Handbook v8.1.
This option may cause memory usage and run time increase.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <entity name> <value>
set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to <to> -entity <entity
name> <value>
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <value>
Example
set_global_assignment -name synth_gated_clock_conversion on
set_instance_assignment -name synth_gated_clock_conversion on -to foo
Default Value
Off
© November 2008
Altera Corporation
4–176
SYNTH_MESSAGE_LEVEL
SYNTH_MESSAGE_LEVEL
Type
Enumeration
■
High
■
Low
■
Medium
Device Support
Notes
Syntax
set_global_assignment -name SYNTH_MESSAGE_LEVEL <value>
Default Value
Medium
© November 2008
Altera Corporation
SYNTH_PROTECT_SDC_CONSTRAINT
4–177
SYNTH_PROTECT_SDC_CONSTRAINT
A logic option causes SDC constraint checking in register merging, so that registers with SDC constraints
keep their names, functionalities and connections.
This option is useful for maintaining the validity of SDC constraints through compilation.
This option may cause memory usage and run time increase.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT <value>
Example
set_global_assignment -name synth_protect_sdc_constraint on
Default Value
Off
© November 2008
Altera Corporation
4–178
SYNTH_TIMING_DRIVEN_SYNTHESIS
SYNTH_TIMING_DRIVEN_SYNTHESIS
A logic option that specifies whether Quartus II synthesis is allowed to use timing information to optimize
the design.
When this option is turned on, synthesis will run timing analysis to obtain timing information about the
netlist, and will optimize the netlist accordingly. It will also automatically apply the "SDC Constraint
Protection" logic option.
This option is useful when regular synthesis does not optimize the circuit well for the given timing
constraints. When Timing-Driven Synthesis is on you can expect synthesis to get better performance at the
cost of some ALUTs and/or registers. Runtime and peak memory will slightly increase as well.
This option can only be used for Stratix II, HardCopy II and Stratix III families. It will be ignored for other
families. It will also be ignored when the Synthesis Effort is set to Fast. It will also be ignored when
incremental compile is on and there are multiple partitions, or when hierarchical synthesis is on.
Appropriate warnings will be given when the option is ignored.
When this option is on it is recommended that a device is specified for the design. If no device is specified,
timing-driven synthesis will automatically use the smallest device in the family that satisfies design
constraints like speed grade and package.
Type
Boolean
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
■
Stratix III
Notes
Syntax
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS <value>
Example
set_global_assignment -name synth_timing_driven_synthesis on
Default Value
Off
© November 2008
Altera Corporation
TOP_LEVEL_ENTITY
4–179
TOP_LEVEL_ENTITY
Type
String
Device Support
Notes
Syntax
set_global_assignment -name TOP_LEVEL_ENTITY <value>
Old Names
FOCUS_ENTITY_NAME
© November 2008
Altera Corporation
4–180
TRUE_WYSIWYG_FLOW
TRUE_WYSIWYG_FLOW
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name TRUE_WYSIWYG_FLOW <value>
Default Value
Off
© November 2008
Altera Corporation
USER_LIBRARIES
4–181
USER_LIBRARIES
Type
String
Device Support
Notes
Syntax
set_global_assignment -name USER_LIBRARIES <value>
© November 2008
Altera Corporation
4–182
USE_GENERATED_PHYSICAL_CONSTRAINTS
USE_GENERATED_PHYSICAL_CONSTRAINTS
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS -section_id <section
identifier> <value>
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS -entity <entity name>
Default Value
On, requires section identifier
© November 2008
Altera Corporation
USE_HIGH_SPEED_ADDER
4–183
USE_HIGH_SPEED_ADDER
Tells the Compiler whether to use high speed adder circuitry to implement arithmetic functions or not.
This option is useful for improving the performance of the design when set to On and minimizing the total
number of HCells used in the design when set to Off. This option applies to HardCopy II only. It can only
be used as a project-wide option. This option defaults to Auto, which has the same behavior as On when
the Optimization Technique is set to Speed or Balanced, and as Off when the Optimization Technique is set
to Area.
A logic option that tells the Compiler whether to use high speed adder circuitry to implement arithmetic
functions or not.
This option is useful for improving the performance of the design when set to On and minimizing the total
number of HCells used in the design when set to Off.
This option applies to HardCopy II only.
This option defaults to Auto, which has the same behavior as On when the Optimization Technique is set
to Speed or Balanced, and as Off when the Optimization Technique is set to Area.
Type
Enumeration
■
Auto
■
Off
■
On
Device Support
■
HardCopy II
■
HardCopy III
Notes
Syntax
set_global_assignment -name USE_HIGH_SPEED_ADDER <value>
set_global_assignment -name USE_HIGH_SPEED_ADDER -entity <entity name> <value>
set_instance_assignment -name USE_HIGH_SPEED_ADDER -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name use_high_speed_adder off
Default Value
Auto
© November 2008
Altera Corporation
4–184
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
A logic option that allows you to use LogicLock contraints during DSP and RAM balancing. This helps the
balancer to make better balancing decisions.
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING <value>
Example
set_global_assignment -name use_logiclock_constraints_in_balancing on
Default Value
Off
© November 2008
Altera Corporation
VERILOG_CONSTANT_LOOP_LIMIT
4–185
VERILOG_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constants
on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust
memory or trap the software in an actual infinite loop.
A logic option that defines the iteration limit for Verilog loops with loop conditions that evaluate to
compile-time constants on each loop iteration. For example, such loops would have loop conditions that
dependended only on loop variables and constant expressions. If a loop condition refers to an input to the
current module or to another variable other than a loop-variable, then the loop condition is most likely a
non-constant loop condition, which has a separate limit in the Quartus II software. This logic option exists
primarily to catch potential infinite loops before they exhaust memory or trap the software in an actual
infinite loop. In general, you should only increase the value of this option, unless you are trying to
identify a loop that requires excessive amounts of logic and therefore exhausts the memory available to the
Quartus II software. If you decrease the value of this logic option, you may receive errors for loops that
previously passed synthesis.
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT <value>
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity <entity name> <value>
set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to <to> -entity <entity name>
<value>
Example
set_global_assignment -name verilog_constant_loop_limit 3000
Default Value
5000
© November 2008
Altera Corporation
4–186
VERILOG_INPUT_VERSION
VERILOG_INPUT_VERSION
Type
Enumeration
■
SystemVerilog_2005
■
Verilog_1995
■
Verilog_2001
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_INPUT_VERSION <value>
Default Value
Verilog_2001
© November 2008
Altera Corporation
VERILOG_LMF_FILE
4–187
VERILOG_LMF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_LMF_FILE <value>
© November 2008
Altera Corporation
4–188
VERILOG_MACRO
VERILOG_MACRO
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_MACRO <value>
© November 2008
Altera Corporation
VERILOG_NON_CONSTANT_LOOP_LIMIT
4–189
VERILOG_NON_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that do not evaluate to compile-time
constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they
exhaust memory or trap the software in an actual infinite loop.
A logic option that defines the iteration limit for Verilog loops with loop conditions that depend on inputs
to the current module or on non-loop variables. When the loop condition does not evaluate to a constant
true or false, the Quartus II software must create extra logic to account for the potential exit from the loop.
This logic may accumulate over a number of iterations and exhaust the available memory. Eventually, the
loop condition must evaluate to a constant false to terminate the loop. Otherwise, the Quartus II software
will exhaust the available memory or generate an error. This logic option exists primarily to catch
potential infinite loops before they exhaust memory or trap the software in an actual infinite loop. In
general, you should only increase the value of this option, unless you are trying to identify a loop that
requires excessive amounts of logic and therefore exhausts the memory available to the Quartus II
software. If you decrease the value of this logic option, you may receive errors for loops that previously
passed synthesis.
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT <value>
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -entity <entity name>
<value>
set_instance_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -to <to> -entity <entity
name> <value>
Example
set_global_assignment -name verilog_non_constant_loop_limit 3000
Default Value
250
© November 2008
Altera Corporation
4–190
VERILOG_SHOW_LMF_MAPPING_MESSAGES
VERILOG_SHOW_LMF_MAPPING_MESSAGES
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES <value>
© November 2008
Altera Corporation
VHDL_INPUT_LIBRARY
4–191
VHDL_INPUT_LIBRARY
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name VHDL_INPUT_LIBRARY -to <to> <value>
© November 2008
Altera Corporation
4–192
VHDL_INPUT_VERSION
VHDL_INPUT_VERSION
Type
Enumeration
■
VHDL87
■
VHDL93
Device Support
Notes
Syntax
set_global_assignment -name VHDL_INPUT_VERSION <value>
Default Value
VHDL93
© November 2008
Altera Corporation
VHDL_LMF_FILE
4–193
VHDL_LMF_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VHDL_LMF_FILE <value>
© November 2008
Altera Corporation
4–194
VHDL_SHOW_LMF_MAPPING_MESSAGES
VHDL_SHOW_LMF_MAPPING_MESSAGES
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES <value>
© November 2008
Altera Corporation
5. Incremental Compilation Assignments
AUTO_EXPORT_INCREMENTAL_COMPILATION
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION <value>
Default Value
Off
© November 2008
Altera Corporation
5–2
Incremental Compilation Assignments
INCREMENTAL_COMPILATION
INCREMENTAL_COMPILATION
Type
Enumeration
■
FULL_INCREMENTAL_COMPILATION
■
Off
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION <value>
Default Value
FULL_INCREMENTAL_COMPILATION
Old Names
ENABLE_INCREMENTAL_SYNTHESIS
© November 2008
Altera Corporation
INCREMENTAL_COMPILATION_EXPORT_FILE
5–3
INCREMENTAL_COMPILATION_EXPORT_FILE
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_FILE <value>
© November 2008
Altera Corporation
5–4
INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
Type
Enumeration
■
POST_FIT
■
POST_SYNTH
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE <value>
Default Value
POST_FIT
© November 2008
Altera Corporation
INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
5–5
INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME <value>
© November 2008
Altera Corporation
5–6
INCREMENTAL_COMPILATION_EXPORT_ROUTING
INCREMENTAL_COMPILATION_EXPORT_ROUTING
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_ROUTING <value>
© November 2008
Altera Corporation
PARTITION_FITTER_PRESERVATION_LEVEL
5–7
PARTITION_FITTER_PRESERVATION_LEVEL
Type
Enumeration
■
COMPATIBLE_PLACEMENT
■
COMPATIBLE_PLACEMENT_AND_ROUTING
■
NETLIST_ONLY
■
PLACEMENT
■
PLACEMENT_AND_ROUTING
■
PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL -entity <entity name>
set_instance_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL -to <to> -entity
<entity name> -section_id <section identifier> <value>
© November 2008
Altera Corporation
5–8
PARTITION_HIERARCHY
PARTITION_HIERARCHY
The target of the assignment specifies the hierarchy path of the entity instance for the partition. The value
of the assignment specifies the base output filename for writing intermediary atom netlists. It is strongly
recommended that you rely on the default output filenames generated by Quartus II. If you decide to
provide your own filenames, you must ensure their uniqueness among partitions.
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_HIERARCHY -entity <entity name> -section_id
set_instance_assignment -name PARTITION_HIERARCHY -to <to> -entity <entity name>
set_global_assignment -name PARTITION_HIERARCHY -entity <entity name> <value>
set_instance_assignment -name PARTITION_HIERARCHY -to <to> -entity <entity name> <value>
Old Names
INCREMENTAL_DESIGN_PARTITION
© November 2008
Altera Corporation
PARTITION_IMPORT_ASSIGNMENTS
5–9
PARTITION_IMPORT_ASSIGNMENTS
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS -entity <entity name>
set_instance_assignment -name PARTITION_IMPORT_ASSIGNMENTS -to <to> -entity <entity
name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
© November 2008
Altera Corporation
5–10
PARTITION_IMPORT_EXISTING_ASSIGNMENTS
PARTITION_IMPORT_EXISTING_ASSIGNMENTS
Type
Enumeration
■
REPLACE_CONFLICTING
■
SKIP_CONFLICTING
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS -entity <entity name>
set_instance_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS -to <to> -entity
Default Value
REPLACE_CONFLICTING, requires section identifier and entity name
© November 2008
Altera Corporation
PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
5–11
PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
Type
Enumeration
■
REPLACE_CONFLICTING
■
SKIP_CONFLICTING
■
UPDATE_CONFLICTING
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS -entity <entity
set_instance_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS -to <to>
-entity <entity name> -section_id <section identifier> <value>
Default Value
REPLACE_CONFLICTING, requires section identifier and entity name
© November 2008
Altera Corporation
5–12
PARTITION_IMPORT_FILE
PARTITION_IMPORT_FILE
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_IMPORT_FILE -entity <entity name> -section_id
set_instance_assignment -name PARTITION_IMPORT_FILE -to <to> -entity <entity name>
© November 2008
Altera Corporation
PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
5–13
PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS -entity <entity name>
set_instance_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS -to <to> -entity
Default Value
On, requires section identifier and entity name
© November 2008
Altera Corporation
5–14
PARTITION_LAST_IMPORTED_FILE
PARTITION_LAST_IMPORTED_FILE
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_LAST_IMPORTED_FILE -entity <entity name>
set_instance_assignment -name PARTITION_LAST_IMPORTED_FILE -to <to> -entity <entity
© November 2008
Altera Corporation
PARTITION_NETLIST_TYPE
5–15
Type
Enumeration
■
Auto
■
EMPTY
■
IMPORTED
■
IMPORT_BASED_POST_FIT
■
POST_FIT
■
POST_SYNTH
■
SOURCE
■
STRICT_POST_FIT
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name PARTITION_NETLIST_TYPE -entity <entity name> -section_id
set_instance_assignment -name PARTITION_NETLIST_TYPE -to <to> -entity <entity name>
© November 2008
Altera Corporation
5–16
© November 2008
Altera Corporation
6. Fitter Assignments
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
<value>
Default Value
Off
© November 2008
Altera Corporation
6–2
Fitter Assignments
ALWAYS_ENABLE_INPUT_BUFFERS
ALWAYS_ENABLE_INPUT_BUFFERS
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
HardCopy II
■
MAX II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
APEX20KE_DEVICE_IO_STANDARD
6–3
APEX20KE_DEVICE_IO_STANDARD
Type
String
Device Support
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name APEX20KE_DEVICE_IO_STANDARD <value>
© November 2008
Altera Corporation
6–4
Fitter Assignments
APEX20K_CONFIGURATION_SCHEME
APEX20K_CONFIGURATION_SCHEME
Type
Enumeration
■
Passive Parallel Asynchronous
■
Passive Parallel Synchronous
■
Passive Serial
Device Support
■
APEX20K
■
APEX20KC
■
APEX20KE
Syntax
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
Old Names
CONFIGURATION_SCHEME
© November 2008
Altera Corporation
Fitter Assignments
APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
6–5
APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
Decreases the propagation delay from an input or bidirectional pin to logic and embedded cells within the
device. This is an advanced option that should be used only after you have compiled a project, checked the
I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this
option, refer to the data sheet for the device family. This option is ignored if it is applied to anything other
than an input or bidirectional pin.
Type
Enumeration
■
Large
■
Medium
■
Off
■
On
■
Small
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to <to>
Old Names
DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
Decrease Input Delay to Internal Cells -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based
Excalibur
© November 2008
Altera Corporation
6–6
Fitter Assignments
APEX20K_DEVICE_IO_STANDARD
APEX20K_DEVICE_IO_STANDARD
Type
String
Device Support
■
APEX20K
Notes
Syntax
set_global_assignment -name APEX20K_DEVICE_IO_STANDARD <value>
Old Names
DEVICE_IO_STANDARD
© November 2008
Altera Corporation
Fitter Assignments
APEXII_CONFIGURATION_SCHEME
6–7
APEXII_CONFIGURATION_SCHEME
Type
Enumeration
■
Fast Passive Parallel
■
■
Passive Serial
Device Support
■
APEX II
Syntax
set_global_assignment -name APEXII_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
Old Names
APEX_II_CONFIGURATION_SCHEME
© November 2008
Altera Corporation
6–8
Fitter Assignments
APEXII_DEVICE_IO_STANDARD
APEXII_DEVICE_IO_STANDARD
Type
String
Device Support
■
APEX II
Notes
Syntax
set_global_assignment -name APEXII_DEVICE_IO_STANDARD <value>
Old Names
APEX20KF_DEVICE_IO_STANDARD
© November 2008
Altera Corporation
Fitter Assignments
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK
6–9
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK
Allows the Automatic Asynchronous Signal Pipelining algorithm to run on the specified asynchronous
signal even if it feeds synchronous inputs. However, turning this option ON can change circuit
functionality. This option is intended for advanced users
Type
Boolean
Device Support
Syntax
set_global_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -entity <entity
name> <value>
set_instance_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -to <to> -entity
© November 2008
Altera Corporation
6–10
Fitter Assignments
ASYNC_PIPELINE_REG_REACH
ASYNC_PIPELINE_REG_REACH
Specify the maximum number of LABs that the asynchronous signal sourcing at the To register can go
across before a new pipeline register is inserted. This requirement might not be met for all pipeline stages,
when, due to congestion or over-filled LABs, the register cannot be placed at the desired location
Type
Integer
Device Support
Syntax
set_global_assignment -name ASYNC_PIPELINE_REG_REACH -entity <entity name> <value>
set_instance_assignment -name ASYNC_PIPELINE_REG_REACH -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
AUTO_DELAY_CHAINS
6–11
AUTO_DELAY_CHAINS
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_DELAY_CHAINS <value>
Default Value
On
© November 2008
Altera Corporation
6–12
Fitter Assignments
AUTO_GLOBAL_CLOCK
AUTO_GLOBAL_CLOCK
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock
signal that is made available throughout the device on the global routing paths. If you want to prevent the
Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX9000
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
© November 2008
Altera Corporation
Fitter Assignments
AUTO_GLOBAL_CLOCK
■
Stratix II GX
■
Stratix III
■
Stratix IV
6–13
Notes
Syntax
set_global_assignment -name AUTO_GLOBAL_CLOCK <value>
set_global_assignment -name AUTO_GLOBAL_CLOCK -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_CLOCK -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
6–14
Fitter Assignments
AUTO_GLOBAL_MEMORY_CONTROLS
Allows the Compiler to choose the signals that feed the most write enable and read enable inputs to
memories as global write enable and read enable signals that are made available throughout the device on
the global routing paths. If you want to prevent the Compiler from automatically selecting a particular
signal as global memory control signal, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS <value>
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
6–15
Default Value
Off
© November 2008
Altera Corporation
6–16
Fitter Assignments
AUTO_GLOBAL_OE
AUTO_GLOBAL_OE
Allows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signal
that is made available throughout the device on the global routing paths. If you want to prevent the
option to 'Off' on that signal.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
Notes
Syntax
set_global_assignment -name AUTO_GLOBAL_OE <value>
set_global_assignment -name AUTO_GLOBAL_OE -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_OE -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
AUTO_GLOBAL_REGISTER_CONTROLS
6–17
Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding
clock signals) as global signals that are made available throughout the device on the global routing paths.
Depending on the target device family, these control signals can include asynchronous clear and load,
synchronous clear and load, clock enable, and preset signals.If you want to prevent the Compiler from
automatically selecting a particular signal as global register control signal, set the Global Signal option to
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX9000
■
Mercury
■
Stratix
■
Stratix GX
© November 2008
Altera Corporation
6–18
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Fitter Assignments
Notes
Syntax
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS <value>
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -to <to> -entity <entity
name> <value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
AUTO_MERGE_PLLS
6–19
AUTO_MERGE_PLLS
Allows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL)
driven by the same clock source, reducing the total number of PLLs used in a design.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_MERGE_PLLS <value>
set_global_assignment -name AUTO_MERGE_PLLS -entity <entity name> <value>
set_instance_assignment -name AUTO_MERGE_PLLS -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
6–20
Fitter Assignments
AUTO_PACKED_REGISTERS
AUTO_PACKED_REGISTERS
Allows the Compiler to automatically implement a register and a combinational function in the same logic
cell. This option controls how aggressively the Fitter combines registers with other function blocks in order
to reduce logic element count. If this option is set to 'Off', the Fitter does not attempt to place a pair of logic
functions in a single logic cell; however, logic cells specified during synthesis to perform both a
combinational and a sequential function are maintained. If this option is set to 'Normal', the Fitter places
both a combinational and a sequential operation in a logic cell when it is expected that the placement does
not affect design performance. When this option is set to 'Minimize Area', the Fitter aggressively combines
unrelated sequential and combinational functions into a single logic cell in order to reduce the logic cell
count, even at the expense of design performance.
Type
Enumeration
■
Minimize Area
■
Normal
■
Off
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
Mercury
Notes
Syntax
set_global_assignment -name AUTO_PACKED_REGISTERS <value>
set_global_assignment -name AUTO_PACKED_REGISTERS -entity <entity name> <value>
set_instance_assignment -name AUTO_PACKED_REGISTERS -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
AUTO_PACKED_REGISTERS_CYCLONE
6–21
cell, or to implement registers using I/O cells or RAM blocks instead of logic cells. This option controls
how aggressively the Fitter combines registers with other function blocks in order to reduce logic element
count. If this option is set to 'Off', the Fitter does not attempt to place a pair of logic functions in a single
logic cell; however, logic cells specified during synthesis to perform both a combinational and a sequential
function are maintained. If this option is set to 'Normal', the Fitter places both a combinational and a
sequential operation in a logic cell when it is expected that the placement does not affect design
performance. When this option is set to 'Minimize Area', the Fitter aggressively combines unrelated
sequential and combinational functions that are not part of an arithmetic or register cascade chain into a
single logic cell in order to reduce the logic cell count, even at the expense of design performance. When
this option is set to 'Minimize Area with Chains', the Fitter even more aggressively combines sequential
and combinational functions that are part of arithmetic or register cascade chains or that can be converted
to register cascade chains. When this setting is Auto, the fitter attempts to achieve the best performance
while maintaining a fit for the design in the specified device. The fitter will combine all combinational and
sequential functions that are deemed to benefit circuit speed. In addition, more aggressive combinations of
unrelated combinational and sequential functions are performed to the extent required to reduce the area
of the design in order to achieve a fit in the specified device. If this option is set to any value but 'Off',
registers are merged with I/O cells to improve I/O timing, and with RAM blocks to reduce logic cell count
or improve timing when possible.
Type
Enumeration
■
Auto
■
Minimize Area
■
Minimize Area with Chains
■
Normal
■
Off
Device Support
■
Cyclone
Notes
Syntax
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE <value>
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE -entity <entity name> <value>
set_instance_assignment -name AUTO_PACKED_REGISTERS_CYCLONE -to <to> -entity <entity
name> <value>
Default Value
Auto
© November 2008
Altera Corporation
6–22
Fitter Assignments
Old Names
AUTO_PACKED_REG_CYCLONE
Auto Packed Registers -- Cyclone
© November 2008
Altera Corporation
Fitter Assignments
AUTO_PACKED_REGISTERS_MAXII
6–23
cell. This option controls how aggressively the Fitter combines registers with other function blocks in order
to reduce logic element count. If this option is set to 'Off', the Fitter does not attempt to place a pair of logic
count, even at the expense of design performance. When this option is set to 'Minimize Area with Chains',
the Fitter even more aggressively combines sequential and combinational functions that are part of
arithmetic or register cascade chains or that can be converted to register cascade chains. When this setting
is Auto, the fitter attempts to achieve the best performance while maintaining a fit for the design in the
specified device. The fitter will combine all combinational and sequential functions that are deemed to
benefit circuit speed. In addition, more aggressive combinations of unrelated combinational and
sequential functions are performed to the extent required to reduce the area of the design in order to
achieve a fit in the specified device.
Type
Enumeration
■
Auto
■
Minimize Area
■
■
Normal
■
Off
Device Support
■
MAX II
Notes
Syntax
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII <value>
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII -entity <entity name> <value>
set_instance_assignment -name AUTO_PACKED_REGISTERS_MAXII -to <to> -entity <entity name>
<value>
Default Value
AUTO
Old Names
© November 2008
Altera Corporation
6–24
Fitter Assignments
AUTO_PACKED_REGISTERS_TSUNAMI
Auto Packed Registers -- MAX II
© November 2008
Altera Corporation
Fitter Assignments
AUTO_PACKED_REGISTERS_STRATIX
6–25
cell, or to implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This
option controls how aggressively the Fitter combines registers with other function blocks in order to
reduce logic element count. If this option is set to 'Off', the Fitter does not attempt to place a pair of logic
count, even at the expense of design performance. When this option is set to 'Minimize Area with Chains',
the Fitter even more aggressively combines sequential and combinational functions that are part of
arithmetic or register cascade chains or that can be converted to register cascade chains. When this setting
is Auto, the fitter attempts to achieve the best performance while maintaining a fit for the design in the
specified device. The fitter will combine all combinational and sequential functions that are deemed to
benefit circuit speed. In addition, more aggressive combinations of unrelated combinational and
sequential functions are performed to the extent required to reduce the area of the design in order to
achieve a fit in the specified device. If this option is set to any value but 'Off', registers are merged with I/O
cells to improve I/O timing, and with DSP blocks and RAM blocks to reduce logic cell count or improve
timing when possible.
Type
Enumeration
■
Auto
■
Minimize Area
■
■
Normal
■
Off
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX <value>
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX -entity <entity name> <value>
set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIX -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–26
Fitter Assignments
Default Value
AUTO
Old Names
AUTO_MODIFIED_PACKED_REGISTERS
Auto Packed Registers -- Stratix/Stratix GX
© November 2008
Altera Corporation
Fitter Assignments
AUTO_PACKED_REGISTERS_STRATIXII
6–27
Allows the Compiler to combine a register and a combinational function, or to implement registers using
I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option controls how aggressively the Fitter
combines registers with other function blocks to reduce the area of the design. Generally, the 'Auto' or
'Sparse Auto' settings should be used for this option. The other options limit the flexibility of the Fitter to
combine registers with other function blocks and can result in no fits. When 'Auto', the default setting is
selected, the Fitter attempts to achieve the best performance with good area. If necessary, additional logic
is combined to reduce the area of the design so that it can fit within the selected device. When this setting
is 'Sparse Auto', the Fitter attempts to achieve the highest performance with possibly increased area, but
without exceeding the logic capacity of the device. If this option is set to 'Off', the Fitter does not combine
registers with other functions. The 'Off' setting severely increases the area of the design and may cause a
no fit. If this option is set to 'Sparse', the Fitter combines functions in a way which improves performance
for many designs. If this option is set to 'Normal', the Fitter combines functions that are expected to
maximize design performance and reduce area. When this option is set to 'Minimize Area', the Fitter
aggressively combines unrelated functions to reduce the area required for placing the design, at the
expense of performance. When this option is set to 'Minimize Area with Chains', the Fitter even more
aggressively combines functions that are part of register cascade chains or can be converted to register
cascade chains. If this option is set to any value but 'Off', registers are combined with I/O cells to improve
I/O timing (as long as the Optimize IOC Register Placement For Timing option allows it), and with DSP
blocks and RAM blocks to reduce the area required for placing the design or to improve timing when
possible.
Type
Enumeration
■
Auto
■
Minimize Area
■
■
Normal
■
Off
■
Sparse
■
Sparse Auto
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
© November 2008
Altera Corporation
6–28
■
Fitter Assignments
Stratix IV
Notes
Syntax
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII <value>
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII -entity <entity name>
<value>
set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIXII -to <to> -entity <entity
name> <value>
Default Value
AUTO
Old Names
AUTO_PACKED_REGISTERS_ARMSTRONG
Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX
© November 2008
Altera Corporation
Fitter Assignments
AUTO_TURBO_BIT
6–29
AUTO_TURBO_BIT
Controls the speed vs. power usage trade-off for a macrocell. If the Turbo Bit is on, the macrocell's speed
increases; if it is off, its power consumption decreases; if you choose the 'Auto' setting, the Compiler
chooses the most appropriate setting for the design.
Type
Enumeration
■
Auto
■
Off
■
On
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name AUTO_TURBO_BIT <value>
set_global_assignment -name AUTO_TURBO_BIT -entity <entity name> <value>
set_instance_assignment -name AUTO_TURBO_BIT -to <to> -entity <entity name> <value>
Default Value
ON
© November 2008
Altera Corporation
6–30
Fitter Assignments
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
Type
Boolean
Device Support
Syntax
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
6–31
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
Controls whether RAMs implemented in MLAB cells must have equivalent pause read capabilities as
RAMs implemented in block RAM. Pausing a read is the ability to keep around the last read value when
reading is disabled. Allowing differences in paused read capabilities will provide the fitter more flexibility
in implementing RAMs using MLAB cells. If this option is set to 'Don't Care', the Fitter may convert RAMs
to MLAB cells even if they won't have equivalent paused read capabilities to a block RAM
implementation. The Fitter will also output an information message notifying the user of RAMs with
different paused read capabilities. If this option is set to 'Care', the Fitter will not convert RAMs to MLAB
cells unless they have the equivalent paused read capabilities to a block RAM implementation. To allow
the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option
to 'Don't Care'.
Type
Enumeration
■
Care
■
Dont Care
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
<value>
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
set_instance_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
-to <to> -entity <entity name> <value>
Default Value
Care
© November 2008
Altera Corporation
6–32
Fitter Assignments
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
Controls whether RAMs implemented in MLAB cells must have equivalent power up conditions as RAMs
implemented in block RAM. Power up conditions occur when the device is powered up or globally reset.
Allowing non-equivalent power up conditions will provide the fitter more flexibility in implementing
RAMs using MLAB cells. If this option is set to 'Auto', the Fitter may convert RAMs to MLAB cells even if
they won't have equivalent power up conditions to a block RAM implementation. The Fitter will also
output a warning message notifying the user of RAMs with non-equivalent power up conditions. If this
option is set to 'Don't Care', the same behavior as 'Auto' applies, but the warning message will instead be
an information message. If this option is set to 'Care', the Fitter will not convert RAMs to MLAB cells
unless they have equivalent power up conditions to a block RAM implementation. To allow the fitter the
most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to 'Auto' or
'Don't Care'.
Type
Enumeration
■
Auto
■
Care
■
Dont Care
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS <value>
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -entity
set_instance_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -to
<to> -entity <entity name> <value>
Default Value
Auto
© November 2008
Altera Corporation
Fitter Assignments
BLOCK_RAM_TO_MLAB_CELL_CONVERSION
6–33
BLOCK_RAM_TO_MLAB_CELL_CONVERSION
Controls whether the fitter is able to convert RAMs to use LAB locations when those RAMs use 'Auto' as
the selected block type. If this option is changed to 'Off' then only MLAB cells in the design or RAM cells
with a block type setting of 'MLAB' will use LAB locations to implement memory.
Type
Boolean
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION <value>
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -entity <entity name>
<value>
set_instance_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -to <to> -entity <entity
name> <value>
Default Value
On
© November 2008
Altera Corporation
6–34
Fitter Assignments
CARRY_OUT_PINS_LCELL_INSERT
CARRY_OUT_PINS_LCELL_INSERT
Type
Boolean
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT <value>
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT -entity <entity name> <value>
set_instance_assignment -name CARRY_OUT_PINS_LCELL_INSERT -to <to> -entity <entity name>
<value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
CKN_CK_PAIR
6–35
CKN_CK_PAIR
Specifies the pairing of a CKn pin to a CK pin. The I/O pin of a CK CKn pair must be placed on a
differential pin pair. This option is ignored if is assigned to anything other than an I/O pad, input buffer,
or output buffer.
Type
Boolean
Device Support
Notes
Syntax
set_instance_assignment -name CKN_CK_PAIR -from <from> -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–36
Fitter Assignments
CLOCK_ENABLE_ROUTING
CLOCK_ENABLE_ROUTING
Specifies whether a clock enable signal in an I/O cell should be driven by the peripheral bus or the
single-pin path. The Single-Pin setting drives the clock enable signal with the local interconnect shared by
the I/O cell and the adjacent LAB. The Peripheral setting drives the clock enable signal with a peripheral
control bus. This option is ignored if it is assigned to anything other than a logic function assigned to an
I/O cell or the signal that drives the clock enable of the I/O cell.
Type
Enumeration
■
Peripheral
■
Single-Pin
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_instance_assignment -name CLOCK_ENABLE_ROUTING -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
CLOCK_TO_OUTPUT_DELAY
6–37
CLOCK_TO_OUTPUT_DELAY
Specifies the propagation delay to the output or bidirectional pin from the output register implemented in
an I/O cell. This is an advanced option that should be used only after you have compiled a project,
checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how
to use this option, refer to the data sheet for the device family. This option is off by default. This option is
ignored if it is applied to anything other than an output or bidirectional pin.
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–38
Fitter Assignments
CONFIGURATION_VCCIO_LEVEL
CONFIGURATION_VCCIO_LEVEL
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL <value>
Default Value
Auto
© November 2008
Altera Corporation
Fitter Assignments
CRC_ERROR_CHECKING
6–39
CRC_ERROR_CHECKING
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name CRC_ERROR_CHECKING <value>
Default Value
Off
Old Names
STRATIX_CRC_ERROR_CHECKING
YEAGER_CRC_ERROR_CHECKING
© November 2008
Altera Corporation
6–40
Fitter Assignments
CRC_ERROR_OPEN_DRAIN
CRC_ERROR_OPEN_DRAIN
Turn on the Open-drain feature on the CRC ERROR pin.
Using this feature would decouple the voltage level of the CRCERROR pin from VCCIO.
A pull-up resistor must be connected to the pin when this feature is enabled.
Type
Boolean
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
Syntax
set_global_assignment -name CRC_ERROR_OPEN_DRAIN <value>
Example
set_global_assignment -name crc_error_open_drain on
set_global_assignment -name crc_error_open_drain off
Default Value
Off
See Also
■
"CRC_ERROR_CHECKING" on page 6-40
■
"ERROR_CHECK_FREQUENCY_DIVISOR" on page 6-102
© November 2008
Altera Corporation
Fitter Assignments
CURRENT_STRENGTH_NEW
6–41
CURRENT_STRENGTH_NEW
Sets the drive strength of a pin. Specify a number (in mA), MIN, or MAX for output or bidirectional pins
that support programmable drive strength. Please refer to the family data sheet for which drive strengths
are allowed for each I/O standard. This option is ignored if it is applied to anything other than an output
or bidirectional pin.
Type
String
Device Support
■
APEX II
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name CURRENT_STRENGTH_NEW -to <to> -entity <entity name>
<value>
Old Names
CURRENT_STRENGTH
© November 2008
Altera Corporation
6–42
Fitter Assignments
CYCLONEIII_CONFIGURATION_SCHEME
CYCLONEIII_CONFIGURATION_SCHEME
Type
Enumeration
■
Active Parallel
■
Active Serial
■
■
Passive Serial
Device Support
■
Cyclone III
Syntax
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME <value>
Default Value
Active Serial
© November 2008
Altera Corporation
Fitter Assignments
CYCLONEII_CONFIGURATION_SCHEME
6–43
CYCLONEII_CONFIGURATION_SCHEME
Type
Enumeration
■
Active Serial
■
Passive Serial
Device Support
■
Cyclone II
Syntax
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME <value>
Default Value
Active Serial
© November 2008
Altera Corporation
6–44
Fitter Assignments
CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
Type
Enumeration
■
Use as programming pin
■
Use as regular IO
Device Support
■
Cyclone II
■
Cyclone III
Syntax
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION <value>
Default Value
© November 2008
Altera Corporation
Fitter Assignments
CYCLONEII_TERMINATION
6–45
CYCLONEII_TERMINATION
Allows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/O pin.
OCT helps to prevent signal reflections and maintain signal integrity. This option is ignored if it is applied
to anything other than an I/O pin.
Type
Enumeration
■
Off
■
Series 25 Ohms
■
Series 50 Ohms
Device Support
■
Cyclone II
Notes
Syntax
set_instance_assignment -name CYCLONEII_TERMINATION -to <to> -entity <entity name>
<value>
Old Names
Termination -- CYCLONE II
© November 2008
Altera Corporation
6–46
Fitter Assignments
CYCLONE_CONFIGURATION_SCHEME
CYCLONE_CONFIGURATION_SCHEME
Type
Enumeration
■
Active Serial
■
Passive Serial
Device Support
■
Cyclone
Syntax
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME <value>
Default Value
Active Serial
© November 2008
Altera Corporation
Fitter Assignments
D1_DELAY
6–47
D1_DELAY
Specifies the propagation delay for D1 Delay Cell. This is an advanced option that should be used only
after you have compiled a project, checked the I/O timing, and determined that the timing is
unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device
family. This option is ignored if it is applied to anything other than an input or bidirectional pin.
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name D1_DELAY -to <to> -entity <entity name> <value>
Old Names
T1_DELAY
© November 2008
Altera Corporation
6–48
Fitter Assignments
D2_DELAY
D2_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
Old Names
T2_DELAY
© November 2008
Altera Corporation
Fitter Assignments
D3_DELAY
6–49
D3_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name D3_DELAY -from <from> -to <to> -entity <entity name>
<value>
Old Names
T3_DELAY
© November 2008
Altera Corporation
6–50
Fitter Assignments
D4_DELAY
D4_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
Old Names
T7_DELAY
© November 2008
Altera Corporation
Fitter Assignments
D5_DELAY
6–51
D5_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
Old Names
T9_DELAY
© November 2008
Altera Corporation
6–52
Fitter Assignments
D5_OCT_DELAY
D5_OCT_DELAY
Specifies the propagation delay for D5 OCT Delay Cell. This is an advanced option that should be used
only after you have compiled a project, checked the I/O timing, and determined that the timing is
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name D5_OCT_DELAY -to <to> -entity <entity name> <value>
Old Names
T9_OCT_DELAY
© November 2008
Altera Corporation
Fitter Assignments
D6_DELAY
6–53
D6_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
Old Names
T10_DELAY
© November 2008
Altera Corporation
6–54
Fitter Assignments
D6_OCT_DELAY
D6_OCT_DELAY
Specifies the propagation delay for D6 OCT Delay Cell. This is an advanced option that should be used
only after you have compiled a project, checked the I/O timing, and determined that the timing is
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name D6_OCT_DELAY -to <to> -entity <entity name> <value>
Old Names
T10_OCT_DELAY
© November 2008
Altera Corporation
Fitter Assignments
DATA0_PIN
6–55
DATA0_PIN
Specifies the Data[0] configuration pin.
Type
Boolean
Device Support
■
Cyclone III
Notes
Syntax
set_instance_assignment -name DATA0_PIN -to <to> <value>
© November 2008
Altera Corporation
6–56
Fitter Assignments
DCLK_PIN
DCLK_PIN
Specifies the DCLK configuration pin.
Type
Boolean
Device Support
■
Cyclone III
Notes
Syntax
set_instance_assignment -name DCLK_PIN -to <to> <value>
© November 2008
Altera Corporation
Fitter Assignments
DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
6–57
DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
Specifies the maximum amount of DC current, in mA, allowed when the Fitter checks for electromigration
violations.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_instance_assignment -name DC_CURRENT_FOR_ELECTROMIGRATION_CHECK -to <to> <value>
© November 2008
Altera Corporation
6–58
Fitter Assignments
DDIO_INPUT_REGISTER
DDIO_INPUT_REGISTER
Type
Enumeration
■
High
■
Low
■
Off
Device Support
■
Cyclone
■
Cyclone II
■
Cyclone III
Notes
Syntax
set_instance_assignment -name DDIO_INPUT_REGISTER -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DDIO_OUTPUT_REGISTER
6–59
DDIO_OUTPUT_REGISTER
Type
Enumeration
■
High
■
Low
■
Off
Device Support
■
Cyclone
■
Cyclone II
Notes
Syntax
set_instance_assignment -name DDIO_OUTPUT_REGISTER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–60
Fitter Assignments
DDIO_OUTPUT_REGISTER_DISTANCE
DDIO_OUTPUT_REGISTER_DISTANCE
Tells the Fitter to place the DDIO output registers (and output mux) that feed this I/O pin in a location
whose LAB distance is specified by this option. This option is ignored if applied to an input pin or if
applied to an output or bidir pin that is not fed by a DDIO Output configuration
Type
Integer
Device Support
■
Cyclone II
Notes
Syntax
set_instance_assignment -name DDIO_OUTPUT_REGISTER_DISTANCE -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
6–61
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
Decreases the propagation delay from an input pin to the data input of the input register implemented in
the I/O cell associated with the pin. This is an advanced option that should be used only after you have
compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed
information on how to use this option, refer to the data sheet for the device family. This option is ignored if
it is applied to anything other than an input or bidirectional pin.
Type
Enumeration
■
Off
■
On
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
MAX7000B
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER -to <to> -entity
© November 2008
Altera Corporation
6–62
Fitter Assignments
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
Decreases the propagation delay from the interior of the device to the data input of the output register
implemented in an I/O cell. This is an advanced option that should be used only after you have compiled
a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed
it is applied to anything other an output or bidirectional pin that is associated with an output register
implemented in an I/O cell.
Type
Enumeration
■
Off
■
On
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER -to <to> -entity
Old Names
DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER
© November 2008
Altera Corporation
Fitter Assignments
DELAY_SETTING_FROM_VIO_TO_CORE
6–63
DELAY_SETTING_FROM_VIO_TO_CORE
Increases the propagation delay from a vertical pin to the interior of the device when the vertical pin is
using the FastRow Interconnect option to route the fan-outs of an input or bidirectional pin. Both the pin
and its fan-out(s) must be assigned to the same Fast Region. The FastRow Interconnect and FastRow
Interconnect Delay options are ignored if they are applied to anything other than a column (vertical) pin
that is implemented as an input or bidirectional pin.
Type
Time
Device Support
■
APEX II
Syntax
set_instance_assignment -name DELAY_SETTING_FROM_VIO_TO_CORE -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–64
Fitter Assignments
DEVICE
DEVICE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name DEVICE <value>
Default Value
AUTO
© November 2008
Altera Corporation
Fitter Assignments
DEVICE_MIGRATION_LIST
6–65
DEVICE_MIGRATION_LIST
Type
String
Device Support
Notes
Syntax
set_global_assignment -name DEVICE_MIGRATION_LIST <value>
© November 2008
Altera Corporation
6–66
Fitter Assignments
DEVICE_TECHNOLOGY_MIGRATION_LIST
DEVICE_TECHNOLOGY_MIGRATION_LIST
Type
String
Device Support
Notes
Syntax
set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST <value>
© November 2008
Altera Corporation
Fitter Assignments
DPRIO_CHANNEL_NUM
6–67
DPRIO_CHANNEL_NUM
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_CHANNEL_NUM -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–68
Fitter Assignments
DPRIO_CRUCLK_NUM
DPRIO_CRUCLK_NUM
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_CRUCLK_NUM -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DPRIO_INTERFACE_REG
6–69
DPRIO_INTERFACE_REG
Type
Boolean
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_INTERFACE_REG -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–70
Fitter Assignments
DPRIO_QUAD_NUM
DPRIO_QUAD_NUM
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_QUAD_NUM -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DPRIO_QUAD_PLL_NUM
6–71
DPRIO_QUAD_PLL_NUM
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_QUAD_PLL_NUM -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–72
Fitter Assignments
DPRIO_TX_PLL0_REFCLK_NUM
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_TX_PLL0_REFCLK_NUM -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
6–73
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_TX_PLL1_REFCLK_NUM -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–74
Fitter Assignments
DPRIO_TX_PLL_NUM
DPRIO_TX_PLL_NUM
Type
Integer
Device Support
■
Stratix II GX
Syntax
set_instance_assignment -name DPRIO_TX_PLL_NUM -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DQSB_DQS_PAIR
6–75
DQSB_DQS_PAIR
Specifies the pairing of a DQSn pin to a DQS pin. The I/O pin of a DQS must be placed in the DQS pin
location of a DQS group; the I/O pin of a DQSn must be placed in the DQSn pin location of the same DQS
group. This option is ignored if is assigned to anything other than an I/O pad, input buffer, or output
buffer.
Type
Boolean
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name DQSB_DQS_PAIR -from <from> -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–76
Fitter Assignments
DQSOUT_DELAY_CHAIN
DQSOUT_DELAY_CHAIN
Type
Integer
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name DQSOUT_DELAY_CHAIN -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DQS_LOCAL_CLOCK_DELAY_CHAIN
6–77
DQS_LOCAL_CLOCK_DELAY_CHAIN
Set the propagation delay on the DQS signal to the input register of the target pin. This is an advanced
option that should be used only after you have compiled a project, checked the I/O timing, and
determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to
the data sheet for the device family. This option is ignored if it is applied to anything other than a DQ or
DQS pin.
Type
Integer
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name DQS_LOCAL_CLOCK_DELAY_CHAIN -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–78
Fitter Assignments
DQ_GROUP
DQ_GROUP
Specifies the grouping from a DQS pin to its associated DQ pins and the width (4, 9, 18, or 36) of the group.
Setting this option allows the Fitter to view the pins as a DQS/DQ pin group. I/O pins of a DQ pin group
must be placed in the DQ pin locations of a single DQS group. This option is ignored if is assigned to
anything other than an I/O pad, input buffer, or output buffer.
Type
Integer
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name DQ_GROUP -from <from> -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
DQ_PIN
6–79
DQ_PIN
Type
Boolean
Device Support
■
Cyclone II
Notes
Syntax
set_instance_assignment -name DQ_PIN -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–80
Fitter Assignments
DUAL_PURPOSE_CLOCK_PIN_DELAY
DUAL_PURPOSE_CLOCK_PIN_DELAY
Specifies the propagation delay from a dual-purpose clock pin to its fan-out destinations that are routed on
the global clock network. Legal integer values range from 0 through 63 for Cyclone and Cyclone II device
families and from 0 through 11 for Cyclone III, where 0 is the setting with the least delay and 63 is the
setting with the most delay. This is an advanced option that should be used only after you have compiled
it is applied to anything other than an input or bidirectional pin, or if the pin is user assigned to a
non-dual-purpose clock pin location.
Type
Integer
Device Support
■
Cyclone
■
Cyclone II
■
Cyclone III
Notes
Syntax
set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
Fitter Assignments
DUPLICATE_ATOM
6–81
DUPLICATE_ATOM
Directs the Compiler to duplicate the source node, and uses the new duplicate node to fan out to the
destination node; the original source node no longer fans out to the destination node. Use the 'Value' field
to specify the name of the duplicate node.
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name DUPLICATE_ATOM -from <from> -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–82
Fitter Assignments
DYNAMIC_OCT_CONTROL_GROUP
DYNAMIC_OCT_CONTROL_GROUP
Assigns a dynamic termination control group number for the specified node. Turning on this option
directs the Fitter to view the specified nodes as a dynamic termination control group so as to place them
next to each other to share the termination control routing resource. This is only applicable for
bidirectional pins.
Type
String
Device Support
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name DYNAMIC_OCT_CONTROL_GROUP -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
ECO_ALLOW_ROUTING_CHANGES
6–83
ECO_ALLOW_ROUTING_CHANGES
Type
Boolean
Device Support
■
Cyclone
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES <value>
Default Value
Off
© November 2008
Altera Corporation
6–84
Fitter Assignments
ECO_OPTIMIZE_TIMING
ECO_OPTIMIZE_TIMING
Type
Enumeration
■
Off
■
On
Device Support
Notes
Syntax
set_global_assignment -name ECO_OPTIMIZE_TIMING <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
ECO_REGENERATE_REPORT
6–85
ECO_REGENERATE_REPORT
Type
Enumeration
■
Off
■
On
Device Support
Notes
Syntax
set_global_assignment -name ECO_REGENERATE_REPORT <value>
Default Value
Off
© November 2008
Altera Corporation
6–86
Fitter Assignments
ENABLE_ASMI_FOR_FLASH_LOADER
ENABLE_ASMI_FOR_FLASH_LOADER
Type
Boolean
Device Support
■
Cyclone II
Syntax
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
6–87
ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
Allows the fitter to insert skew on globally routed clock signals to improve the performance of the design.
Type
Boolean
Device Support
■
Cyclone III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION <value>
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -to <to> -entity
Default Value
Off
© November 2008
Altera Corporation
6–88
Fitter Assignments
ENABLE_BUS_HOLD_CIRCUITRY
Enables bus-hold circuitry during device operation. If this option is turned on, a pin will retain its last logic
level when it is not driven, and will not go to a high impedance logic level. The 'Enable Bus-Hold
Circuitry' option should not be used at the same time as the 'Weak Pull-Up Resistor' option. This option is
ignored if it is applied to anything other than a pin.
Type
Boolean
Device Support
■
APEX II
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX7000B
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY <value>
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -entity <entity name> <value>
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
6–89
Default Value
Off
© November 2008
Altera Corporation
6–90
Fitter Assignments
ENABLE_DEVICE_WIDE_OE
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name ENABLE_DEVICE_WIDE_OE <value>
© November 2008
Altera Corporation
Fitter Assignments
6–91
Default Value
Off
Old Names
ENABLE_CHIP_WIDE_OE
© November 2008
Altera Corporation
6–92
Fitter Assignments
ENABLE_DEVICE_WIDE_RESET
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET <value>
© November 2008
Altera Corporation
Fitter Assignments
6–93
Default Value
Off
Old Names
ENABLE_CHIP_WIDE_RESET
© November 2008
Altera Corporation
6–94
Fitter Assignments
ENABLE_HOLD_BACK_OFF
ENABLE_HOLD_BACK_OFF
Type
Enumeration
■
Off
■
On
Device Support
■
HardCopy II
Syntax
set_global_assignment -name ENABLE_HOLD_BACK_OFF <value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
ENABLE_INIT_DONE_OUTPUT
6–95
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT <value>
Default Value
Off
© November 2008
Altera Corporation
6–96
Fitter Assignments
Old Names
Enable INIT_DONE Output
© November 2008
Altera Corporation
Fitter Assignments
ENABLE_JTAG_BST_SUPPORT
6–97
ENABLE_JTAG_BST_SUPPORT
Type
Boolean
Device Support
■
FLEX6000
Syntax
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT <value>
Default Value
Off
© November 2008
Altera Corporation
6–98
Fitter Assignments
ENABLE_VREFA_PIN
ENABLE_VREFA_PIN
Type
Boolean
Device Support
■
MAX7000B
Syntax
set_global_assignment -name ENABLE_VREFA_PIN <value>
Default Value
Off
Old Names
Enable VREFA pin
© November 2008
Altera Corporation
Fitter Assignments
ENABLE_VREFB_PIN
6–99
ENABLE_VREFB_PIN
Type
Boolean
Device Support
■
MAX7000B
Syntax
set_global_assignment -name ENABLE_VREFB_PIN <value>
Default Value
Off
Old Names
Enable VREFB pin
© November 2008
Altera Corporation
6–100
Fitter Assignments
ERROR_CHECK_FREQUENCY_DIVISOR
ERROR_CHECK_FREQUENCY_DIVISOR
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR <value>
© November 2008
Altera Corporation
Fitter Assignments
FASTROW_INTERCONNECT
6–101
FASTROW_INTERCONNECT
Uses FastRow interconnect to route the fan-outs of an input or bidirectional pin. Both the pin and its
fan-out(s) must also be assigned to the same Fast Region. The FastRow Interconnect option is ignored if it
is applied to anything other than a column (vertical) pin that is implemented as an input or bidirectional
pin.
Type
Boolean
Device Support
■
APEX II
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name FASTROW_INTERCONNECT -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–102
Fitter Assignments
FINAL_PLACEMENT_OPTIMIZATION
Type
Enumeration
■
Always
■
Automatically
■
Never
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
Fitter Assignments
6–103
Syntax
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION <value>
Default Value
Automatically
© November 2008
Altera Corporation
6–104
Fitter Assignments
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
Type
Enumeration
■
Always
■
Automatically
■
Never
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
Fitter Assignments
6–105
Syntax
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION <value>
Default Value
Automatically
© November 2008
Altera Corporation
6–106
Fitter Assignments
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN <value>
Default Value
0ns
© November 2008
Altera Corporation
Fitter Assignments
FITTER_EARLY_TIMING_ESTIMATE_MODE
6–107
FITTER_EARLY_TIMING_ESTIMATE_MODE
Type
Enumeration
■
Optimistic
■
Pessimistic
■
Realistic
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE <value>
Default Value
Realistic
© November 2008
Altera Corporation
6–108
Fitter Assignments
FITTER_EFFORT
FITTER_EFFORT
Type
Enumeration
■
Auto Fit
■
Fast Fit
■
Standard Fit
Device Support
Notes
Syntax
set_global_assignment -name FITTER_EFFORT <value>
Default Value
Auto Fit
Old Names
FAST_FIT_COMPILATION
© November 2008
Altera Corporation
Fitter Assignments
FIT_ATTEMPTS_TO_SKIP
6–109
FIT_ATTEMPTS_TO_SKIP
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP <value>
Default Value
0.0
© November 2008
Altera Corporation
6–110
Fitter Assignments
FIT_ONLY_ONE_ATTEMPT
FIT_ONLY_ONE_ATTEMPT
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
FLEX10K_CONFIGURATION_SCHEME
6–111
Type
Enumeration
■
■
■
Passive Serial
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
© November 2008
Altera Corporation
6–112
Fitter Assignments
FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
Type
Enumeration
■
Off
■
On
Device Support
■
ACEX1K
■
FLEX10KE
Syntax
set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to <to>
Old Names
Decrease Input Delay to Internal Cells -- FLEX 10KE/ACEX 1K
© November 2008
Altera Corporation
Fitter Assignments
FLEX10K_DEVICE_IO_STANDARD
6–113
Type
String
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD <value>
© November 2008
Altera Corporation
6–114
Fitter Assignments
FLEX10K_ENABLE_LOCK_OUTPUT
FLEX10K_ENABLE_LOCK_OUTPUT
Type
Boolean
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT <value>
Default Value
Off
Old Names
PLL lock
PLL_LOCK
© November 2008
Altera Corporation
Fitter Assignments
FLEX10K_MAX_PERIPHERAL_OE
6–115
FLEX10K_MAX_PERIPHERAL_OE
Type
Integer
Device Support
Syntax
set_global_assignment -name FLEX10K_MAX_PERIPHERAL_OE <value>
© November 2008
Altera Corporation
6–116
Fitter Assignments
Type
Enumeration
■
Passive Serial
■
Passive Serial Asynchronous
Device Support
■
FLEX6000
Syntax
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
Old Names
CONFIGURATION_SCHEME_FLEX6K
© November 2008
Altera Corporation
Fitter Assignments
6–117
Type
Enumeration
■
Off
■
On
Device Support
■
FLEX6000
Syntax
set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to <to>
Old Names
Decrease Input Delay to Internal Cells -- FLEX 6000
© November 2008
Altera Corporation
6–118
Fitter Assignments
Type
String
Device Support
■
FLEX6000
Notes
Syntax
set_global_assignment -name FLEX6K_DEVICE_IO_STANDARD <value>
© November 2008
Altera Corporation
Fitter Assignments
FORCE_CONFIGURATION_VCCIO
6–119
FORCE_CONFIGURATION_VCCIO
Type
Boolean
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name FORCE_CONFIGURATION_VCCIO <value>
Default Value
Off
© November 2008
Altera Corporation
6–120
Fitter Assignments
FORCE_MERGE_PLL_FANOUTS
FORCE_MERGE_PLL_FANOUTS
Forces the fanouts of the slave PLL clock output to be merged into the master PLL clock output. This
option should be used only for static PLL clock outputs.
Type
Boolean
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name FORCE_MERGE_PLL_FANOUTS -from <from> -to <to> -entity
© November 2008
Altera Corporation
Fitter Assignments
GENERATE_GXB_RECONFIG_MIF
6–121
GENERATE_GXB_RECONFIG_MIF
Type
Boolean
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF <value>
Default Value
Off
© November 2008
Altera Corporation
6–122
Fitter Assignments
GENERATE_GXB_RECONFIG_MIF_WITH_PLL
GENERATE_GXB_RECONFIG_MIF_WITH_PLL
Type
Boolean
Device Support
■
Stratix II GX
Notes
Syntax
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
GLOBAL_SIGNAL
6–123
GLOBAL_SIGNAL
Specifies whether the signal should be routed using global routing paths. Global signals can be both pinand logic-driven, and can be any signal in the design. Turning this option on for a pin or a single-output
logic function signal is equivalent to feeding the signal through a GLOBAL buffer. Turning this option off
for a particular signal will prevent any of the Auto Global options from using the signal as an automatic
global signal.
Type
Enumeration
■
Dual-Fast Regional Clock
■
Dual-Regional Clock
■
Fast Regional Clock
■
Global Clock
■
Off
■
On
■
Periphery Clock
■
Regional Clock
Device Support
Notes
Syntax
set_instance_assignment -name GLOBAL_SIGNAL -to <to> -entity <entity name> <value>
set_instance_assignment -name GLOBAL_SIGNAL -from <from> -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–124
Fitter Assignments
GNDIO_CURRENT_1PT8V
GNDIO_CURRENT_1PT8V
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_1PT8V <value>
© November 2008
Altera Corporation
Fitter Assignments
GNDIO_CURRENT_2PT5V
6–125
GNDIO_CURRENT_2PT5V
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_2PT5V <value>
© November 2008
Altera Corporation
6–126
Fitter Assignments
GNDIO_CURRENT_GTL
GNDIO_CURRENT_GTL
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_GTL <value>
© November 2008
Altera Corporation
Fitter Assignments
GNDIO_CURRENT_GTL_PLUS
6–127
GNDIO_CURRENT_GTL_PLUS
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_GTL_PLUS <value>
© November 2008
Altera Corporation
6–128
Fitter Assignments
GNDIO_CURRENT_LVCMOS
GNDIO_CURRENT_LVCMOS
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_LVCMOS <value>
© November 2008
Altera Corporation
Fitter Assignments
GNDIO_CURRENT_LVTTL
6–129
GNDIO_CURRENT_LVTTL
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_LVTTL <value>
© November 2008
Altera Corporation
6–130
Fitter Assignments
GNDIO_CURRENT_PCI
GNDIO_CURRENT_PCI
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_PCI <value>
© November 2008
Altera Corporation
Fitter Assignments
GNDIO_CURRENT_SSTL2_CLASS1
6–131
Type
Integer
Device Support
Syntax
set_global_assignment -name GNDIO_CURRENT_SSTL2_CLASS1 <value>
© November 2008
Altera Corporation
6–132
Fitter Assignments
Type
Integer
Device Support
Syntax
© November 2008
Altera Corporation
Fitter Assignments
6–133
Type
Integer
Device Support
Syntax
© November 2008
Altera Corporation
6–134
Fitter Assignments
Type
Integer
Device Support
Syntax
© November 2008
Altera Corporation
Fitter Assignments
GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
6–135
GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
Type
Enumeration
■
Off
■
On
■
When Tsu and Tpd Constraints Permit
Device Support
■
MAX II
Notes
Syntax
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME <value>
Default Value
On
© November 2008
Altera Corporation
6–136
Fitter Assignments
GXB_0PPM_CLOCK_GROUP
GXB_0PPM_CLOCK_GROUP
Specifies a group of GXB core clocks that have zero(0) PPM difference. The clock driver source specified in
the GXB 0 PPM clock group driver must have a difference of 0 PPM compared with all clocks specified in
the GXB 0 PPM clock group. You must connect the specified clock driver to all specified destinations in
the GXB 0 PPM clock group. Do not reconfigure the GXB 0 PPM clock group driver differently from other
clocks in the GXB 0 PPM clock group and do not bring down the GXB 0 PPM clock group driver source
when the destination GXB receiver or transmitter is listening to the signal. Follow the Altera High Speed
I/O Applications Technical Support recommendations.
Type
Integer
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_0PPM_CLOCK_GROUP -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
GXB_0PPM_CLOCK_GROUP_DRIVER
6–137
GXB_0PPM_CLOCK_GROUP_DRIVER
Specifies the GXB core clock driver that drives all core clocks in the GXB zero(0) PPM clock group. The
clock driver source specified in the GXB 0 PPM clock group driver must have a difference of 0 PPM
compared with all clocks specified in the GXB 0 PPM clock group. You must connect the specified clock
driver to all destinations specified in the GXB 0 PPM clock group. Do not reconfigure the GXB 0 PPM clock
group driver differently from other clocks in the GXB 0 PPM clock group and do not bring down the GXB
0 PPM clock group driver source when the destination GXB receiver or transmitter is listening to the
signal. Follow the Altera High Speed I/O Applications Technical Support recommendations.
Type
Integer
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_0PPM_CLOCK_GROUP_DRIVER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–138
Fitter Assignments
GXB_0PPM_CORE_CLOCK
GXB_0PPM_CORE_CLOCK
Specifies two GXB core clocks that have zero(0) PPM difference. The core clock driver for the assignment
source GXB must have a difference of 0 PPM compared with the core clock of the assignment destination
GXB. Do not reconfigure the GXB 0 PPM clock group driver differently from other clocks it is 0
PPM-linked to and do not bring down the GXB 0 PPM clock source when the destination GXB receiver or
transmitter is listening to the signal. Follow the Altera High Speed I/O Applications Technical Support
recommendations.
Type
Boolean
Device Support
■
Stratix IV
Notes
Syntax
set_instance_assignment -name GXB_0PPM_CORE_CLOCK -from <from> -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
Fitter Assignments
GXB_CLOCK_GROUP
6–139
GXB_CLOCK_GROUP
Specifies GXB core clock groups to be merged after compilation. All specified GXB transmitters in the GXB
shared clock group are driven by the clock source specified in the GXB shared clock group driver. All
clocks in the GXB shared clock group and GXB clock group driver must be configured in the same manner.
When the destination GXB transmitter is listening to a signal such as gxb_powerdown, do not bring down
the GXB shared clock group driver source. Follow the Altera High Speed I/O Applications Technical
Support recommendations.
Type
Integer
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_CLOCK_GROUP -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–140
Fitter Assignments
GXB_CLOCK_GROUP_DRIVER
GXB_CLOCK_GROUP_DRIVER
Specifies the GXB core clock driver that drives all core clocks in a GXB shared clock group after
compilation. All GXB transmitters specified in the GXB shared clock group are driven by the clock source
specified in the GXB shared clock group driver. Do not reconfigure the GXB shared clock group driver
differently from other clocks in the GXB shared clock group and do not bring down the GXB shared clock
group driver source when the destination GXB transmitter is listening to the signal. Follow the Altera
High Speed I/O Applications Technical Support recommendations.
Type
Integer
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_CLOCK_GROUP_DRIVER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
GXB_RECONFIG_GROUP
6–141
GXB_RECONFIG_GROUP
Specifies whether GXB transceiver channels with Dynamic Reconfiguration can be placed in the same
physical channel. GXB receivers and transmitters are not placed into the same physical channel when
Dynamic Reconfiguration setting is turned ON unless they are in the same reconfig group. GXB receivers
and transmitters can be assigned to the same group if the following conditions are met: GXB receiver and
transmitter will be dynamically reconfigured at the same time, and the GXB receiver and transmitter will
be kept in reset until the dynamic reconfiguration of both is complete.
Type
Integer
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_RECONFIG_GROUP -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–142
Fitter Assignments
GXB_RECONFIG_MIF
GXB_RECONFIG_MIF
Type
String
Device Support
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_RECONFIG_MIF -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
GXB_RECONFIG_MIF_PLL
6–143
GXB_RECONFIG_MIF_PLL
Type
Boolean
Device Support
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_RECONFIG_MIF_PLL -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–144
Fitter Assignments
GXB_REFCLK_COUPLING_TERMINATION_SETTING
GXB_REFCLK_COUPLING_TERMINATION_SETTING
Allows the Compiler to configure the AC/DC coupling and on-chip termination (OCT) for a Stratix II GX
gigabit transceiver block (GXB) REFCLK input pin. Use DC coupling external termination value only with
the HCSL IO standard on the PCI-Express protocol. This option is ignored if it is applied to anything other
than an input pin.
Type
Enumeration
■
DC coupling external termination
■
OCT 100 Ohms
■
Use as regular IO
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_REFCLK_COUPLING_TERMINATION_SETTING -to <to> -entity
© November 2008
Altera Corporation
Fitter Assignments
GXB_TX_PLL_RECONFIG_GROUP
6–145
GXB_TX_PLL_RECONFIG_GROUP
Specifies whether GXB transceiver channels with Dynamic TX PLL Reconfiguration can be placed in the
same physical GXB Quad. If the GXB transceivers have 2 dynamically reconfigured TX PLLs, the GXB
transceivers are not placed into the same physical Quad when Dynamic TX PLL Reconfiguration setting is
turned ON unless they are in the same TX PLL reconfig group. If the GXB transceivers have 1 dynamically
reconfigured TX PLLs, GXB transceivers from 2 TX PLL reconfig groups can be placed into the same
physical Quad if the logical number on the TX PLLs are different. GXB transceivers can be assigned to the
same group if the following conditions are met: (1) GXB transmitters in the same group can only listen to 2
TX PLLs at one time, (2) the user must maintain proper data rates on TX PLLs according to Altera user
guidelines, (3) the user must wait for pll_locked signal asserted for dynamic PLL reconfiguration
completion, and the GXB receiver and transmitter will be kept in reset until the dynamic reconfiguration of
both is complete.
Type
Integer
Device Support
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name GXB_TX_PLL_RECONFIG_GROUP -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–146
Fitter Assignments
IGNORE_MODE_FOR_MERGE
IGNORE_MODE_FOR_MERGE
Ignores the mode of the PLL when the Fitter attempts to merge PLLs, therefore allowing PLLs with
different modes to be merged.
Type
Boolean
Device Support
■
Cyclone II
Notes
Syntax
set_global_assignment -name IGNORE_MODE_FOR_MERGE <value>
set_global_assignment -name IGNORE_MODE_FOR_MERGE -entity <entity name> <value>
set_instance_assignment -name IGNORE_MODE_FOR_MERGE -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
6–147
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
Increases the propagation delay to the output enable pin from internal logic or the output enable register
it is applied to anything other than an output enable pin.
Type
Enumeration
■
Off
■
On
Device Support
■
APEX II
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN -to <to> -entity
© November 2008
Altera Corporation
6–148
Fitter Assignments
INCREASE_DELAY_TO_OUTPUT_PIN
INCREASE_DELAY_TO_OUTPUT_PIN
Increases the propagation delay to the output or bidirectional pin from the output register implemented in
an I/O cell. This is an advanced option that should be used only after you have compiled a project,
checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how
to use this option, refer to the data sheet for the device family. This option is off by default. This option is
ignored if it is applied to anything other than an output or bidirectional pin.
Type
Enumeration
■
Off
■
On
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
Fitter Assignments
INCREASE_INPUT_CLOCK_ENABLE_DELAY
6–149
INCREASE_INPUT_CLOCK_ENABLE_DELAY
Increases the propagation delay from the interior of the device to the clock enable input of an output
register. This is an advanced option that should be used only after you compile a project, check the I/O
timing, and determine that the timing is unsatisfactory. This option is ignored if it is applied to anything
other than an I/O cell that has an input register with a clock enable signal. For detailed information on
how to use this option, refer to the data sheet for the device family, which is available from the Literature
section of the Altera web site.
Type
Enumeration
■
Large
■
Off
■
On
■
Small
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name INCREASE_INPUT_CLOCK_ENABLE_DELAY -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–150
Fitter Assignments
INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
Increases the propagation delay from the interior of the device to the clock enable input of an I/O register.
This is an advanced option that should be used only after you have compiled a project, checked the I/O
timing, and determined that the timing is unsatisfactory. For detailed information on how to use this
than an I/O cell that has a register that has a clock enable signal.
Type
Enumeration
■
Large
■
Off
■
On
■
Small
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER -to <to> -entity
© November 2008
Altera Corporation
Fitter Assignments
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
6–151
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
register. This is an advanced option that should be used only after you compile a project, check the I/O
timing, and determine that the timing is unsatisfactory. This option is ignored if it is applied to anything
other than an I/O cell that has an output register with a clock enable signal. For detailed information on
how to use this option, refer to the data sheet for the device family, which is available from the Literature
section of the Altera web site.
Type
Enumeration
■
Large
■
Off
■
On
■
Small
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name INCREASE_OUTPUT_CLOCK_ENABLE_DELAY -to <to> -entity
© November 2008
Altera Corporation
6–152
Fitter Assignments
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
enable register. This is an advanced option that should be used only after you compile a project, check the
I/O timing, and determine that the timing is unsatisfactory. This option is ignored if it is applied to
anything other than an I/O cell that has an output enable register with a clock enable signal. For detailed
information on how to use this option, refer to the data sheet for the device family, which is available from
the Literature section of the Altera web site.
Type
Enumeration
■
Large
■
Off
■
On
■
Small
Device Support
■
HardCopy Stratix
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY -to <to> -entity
Old Names
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR
© November 2008
Altera Corporation
Fitter Assignments
INCREASE_TZX_DELAY_TO_OUTPUT_PIN
6–153
INCREASE_TZX_DELAY_TO_OUTPUT_PIN
Supports zero bus-turnaround (ZBT) by increasing the propagation delay of the falling edge of the output
enable signal. This option allows a device to quickly release control and slowly take control of a bus.
Turning the Increase tzx Delay to Output Pin option on prevents bus contention between ZBT SRAM
devices. This option is ignored if it is applied to anything other than an output or bidirectional pin.
Type
Enumeration
■
Off
■
On
Device Support
■
APEX II
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name INCREASE_TZX_DELAY_TO_OUTPUT_PIN -to <to> -entity <entity
name> <value>
Old Names
ZBT_OE_FALLING_EDGE_DELAY
© November 2008
Altera Corporation
6–154
Fitter Assignments
INC_PLC_MODE
INC_PLC_MODE
Type
Boolean
Device Support
■
Cyclone
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name INC_PLC_MODE <value>
© November 2008
Altera Corporation
Fitter Assignments
INPUT_REFERENCE
6–155
INPUT_REFERENCE
Allows you to specify the VREF pin for the I/O standard being used by an I/O pin. This option is ignored
if it is applied to anything other than the I/O standard being used by an I/O pin.
Type
Enumeration
■
As VREFA
■
As VREFB
■
Off
Device Support
■
MAX7000B
Syntax
set_instance_assignment -name INPUT_REFERENCE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–156
Fitter Assignments
INPUT_TERMINATION
INPUT_TERMINATION
to anything other than an I/O pad, input buffer, or output buffer.
Type
String
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name INPUT_TERMINATION -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
INSERT_ADDITIONAL_LOGIC_CELL
6–157
INSERT_ADDITIONAL_LOGIC_CELL
Allows the Compiler to insert an additional logic cell after the output(s) of the logic function to which it is
applied, provided that the function is implemented as one logic cell. This option allows you to insert logic
cells for routing purposes without adding LCELL primitives to the design. If this option is applied to a
mega- or macrofunction, it operates on all outputs of the function. This option is ignored if it is applied to
a logic function that is not already implemented in a macrocell(s). For example, if it is applied to an AND
gate, it does not force the AND gate to be the output of a logic cell.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Syntax
set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–158
Fitter Assignments
IO_MAXIMUM_TOGGLE_RATE
IO_MAXIMUM_TOGGLE_RATE
Specifies the toggle rate of this node. You can specify the desired frequency setting. This option is ignored
if it is applied to anything other than pins. This option can be used to direct the Fitter in its toggle-rate
checking while allowing a single-ended pin to be placed closer to a differential pin. This assignment is
used to analyze signal integrity under worst case conditions (highest possible toggle rate). A different
assignment, Power Toggle Rate, is used to specify the expected time-averaged toggle rate rather than
worst-case toggle rate, and is used by the Power Analyzer to estimate time-averaged power consumption.
Use the Synchronizer Toggle Rate if you want to configure the data rates used for Metastability Reporting
in the TimeQuest Timing Analyzer.
Type
Frequency
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE -to <to> -entity <entity name>
<value>
Old Names
TOGGLE RATE
TOGGLE_RATE
© November 2008
Altera Corporation
Fitter Assignments
IO_PLACEMENT_OPTIMIZATION
6–159
IO_PLACEMENT_OPTIMIZATION
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION <value>
Default Value
On
© November 2008
Altera Corporation
6–160
Fitter Assignments
IO_STANDARD
IO_STANDARD
Specifies the I/O standard of a pin. Different device families support different I/O standards, and
restrictions apply to placing pins with different I/O standards together. For detailed information, refer to
the device family data sheet and to Application Note 117 (Using Selectable I/O Standards in Altera
Devices). This option is ignored if it is applied to anything other than a pin or a top-level design entity.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX7000B
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name IO_STANDARD -to <to> <value>
© November 2008
Altera Corporation
Fitter Assignments
LVDS_RX_REGISTER
6–161
LVDS_RX_REGISTER
Type
Enumeration
■
High
■
Low
■
Off
Device Support
■
Cyclone III
Notes
Syntax
set_instance_assignment -name LVDS_RX_REGISTER -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–162
Fitter Assignments
MAX7000B_VCCIO_IOBANK1
Type
String
Device Support
■
MAX7000B
Notes
Syntax
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 <value>
© November 2008
Altera Corporation
Fitter Assignments
6–163
Type
String
Device Support
■
MAX7000B
Notes
Syntax
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 <value>
© November 2008
Altera Corporation
6–164
Fitter Assignments
MAX7000_DEVICE_IO_STANDARD
MAX7000_DEVICE_IO_STANDARD
Type
String
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD <value>
© November 2008
Altera Corporation
Fitter Assignments
MAX7000_ENABLE_JTAG_BST_SUPPORT
6–165
MAX7000_ENABLE_JTAG_BST_SUPPORT
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Syntax
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT <value>
Default Value
On
© November 2008
Altera Corporation
6–166
Fitter Assignments
MAX7000_INDIVIDUAL_TURBO_BIT
MAX7000_INDIVIDUAL_TURBO_BIT
Controls the speed vs. power usage trade-off for a macrocell. If the Turbo Bit is on, the macrocell's speed
increases; if it is off, its power consumption decreases.
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT -entity <entity name> <value>
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT -to <to> -entity <entity
name> <value>
Old Names
Turbo Bit -- MAX 7000B/7000AE/3000A/7000S/7000A
© November 2008
Altera Corporation
Fitter Assignments
MAX_CLOCKS_ALLOWED
6–167
MAX_CLOCKS_ALLOWED
Type
Integer
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name MAX_CLOCKS_ALLOWED <value>
Default Value
-1
© November 2008
Altera Corporation
6–168
Fitter Assignments
MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION <value>
© November 2008
Altera Corporation
Fitter Assignments
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
6–169
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION <value>
© November 2008
Altera Corporation
6–170
Fitter Assignments
MAX_CURRENT_FOR_ELECTROMIGRATION
MAX_CURRENT_FOR_ELECTROMIGRATION
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name MAX_CURRENT_FOR_ELECTROMIGRATION <value>
© November 2008
Altera Corporation
Fitter Assignments
MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
6–171
MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name MAX_CURRENT_FOR_VIO_ELECTROMIGRATION <value>
© November 2008
Altera Corporation
6–172
Fitter Assignments
MAX_GLOBAL_CLOCKS_ALLOWED
MAX_GLOBAL_CLOCKS_ALLOWED
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED <value>
Default Value
-1
© November 2008
Altera Corporation
Fitter Assignments
MAX_PERIPHERY_CLOCKS_ALLOWED
6–173
MAX_PERIPHERY_CLOCKS_ALLOWED
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED <value>
Default Value
-1
© November 2008
Altera Corporation
6–174
Fitter Assignments
MAX_REGIONAL_CLOCKS_ALLOWED
MAX_REGIONAL_CLOCKS_ALLOWED
Type
Integer
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED <value>
Default Value
-1
© November 2008
Altera Corporation
Fitter Assignments
MEMORY_INTERFACE_DATA_PIN_GROUP
6–175
MEMORY_INTERFACE_DATA_PIN_GROUP
Specifies the group width (4, 9, 18, or 36), and associates a pin with another pin. Turning on this option
allows the Fitter to view the pins as part of the same memory interface pin group. I/O pins of this pin
group must be placed in the DQ pin locations of a single DQS group. This option is ignored if is assigned
Type
Integer
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name MEMORY_INTERFACE_DATA_PIN_GROUP -from <from> -to <to>
© November 2008
Altera Corporation
6–176
Fitter Assignments
MERCURY_CONFIGURATION_SCHEME
MERCURY_CONFIGURATION_SCHEME
Type
Enumeration
■
■
■
Passive Serial
Device Support
■
Mercury
Syntax
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
Old Names
CONFIGURATION_SCHEME_DALI
© November 2008
Altera Corporation
Fitter Assignments
MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
6–177
MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
Type
Enumeration
■
Large
■
Medium
■
Off
■
On
■
Small
Device Support
■
Mercury
Syntax
set_instance_assignment -name MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to <to>
Old Names
Decrease Input Delay to Internal Cells -- Mercury
© November 2008
Altera Corporation
6–178
Fitter Assignments
MERCURY_DEVICE_IO_STANDARD
MERCURY_DEVICE_IO_STANDARD
Type
String
Device Support
■
Mercury
Notes
Syntax
set_global_assignment -name MERCURY_DEVICE_IO_STANDARD <value>
© November 2008
Altera Corporation
Fitter Assignments
MIGRATION_CONSTRAIN_CORE_RESOURCES
6–179
MIGRATION_CONSTRAIN_CORE_RESOURCES
Type
Boolean
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES <value>
Default Value
On
© November 2008
Altera Corporation
6–180
Fitter Assignments
MIGRATION_DEVICES
MIGRATION_DEVICES
Type
String
Device Support
Notes
Syntax
set_global_assignment -name MIGRATION_DEVICES <value>
© November 2008
Altera Corporation
Fitter Assignments
NDQS_LOCAL_CLOCK_DELAY_CHAIN
6–181
NDQS_LOCAL_CLOCK_DELAY_CHAIN
Type
Integer
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name NDQS_LOCAL_CLOCK_DELAY_CHAIN -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–182
Fitter Assignments
NORMAL_LCELL_INSERT
NORMAL_LCELL_INSERT
Type
Boolean
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name NORMAL_LCELL_INSERT <value>
set_global_assignment -name NORMAL_LCELL_INSERT -entity <entity name> <value>
set_instance_assignment -name NORMAL_LCELL_INSERT -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
OPTIMIZE_FOR_METASTABILITY
6–183
OPTIMIZE_FOR_METASTABILITY
Type
Enumeration
■
Off
■
On
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY <value>
Default Value
Off
© November 2008
Altera Corporation
6–184
Fitter Assignments
OPTIMIZE_HOLD_TIMING
OPTIMIZE_HOLD_TIMING
Type
Enumeration
■
All Paths
■
IO Paths and Minimum TPD Paths
■
Off
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name OPTIMIZE_HOLD_TIMING <value>
© November 2008
Altera Corporation
Fitter Assignments
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
6–185
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING <value>
Default Value
On
© November 2008
Altera Corporation
6–186
Fitter Assignments
OPTIMIZE_MULTI_CORNER_TIMING
OPTIMIZE_MULTI_CORNER_TIMING
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING <value>
Default Value
Off
Old Names
OPTIMIZE_FAST_CORNER_TIMING
© November 2008
Altera Corporation
Fitter Assignments
OPTIMIZE_POWER_DURING_FITTING
6–187
OPTIMIZE_POWER_DURING_FITTING
Type
Enumeration
■
Extra effort
■
Normal compilation
■
Off
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING <value>
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING -entity <entity name> <value>
set_instance_assignment -name OPTIMIZE_POWER_DURING_FITTING -to <to> -entity <entity
name> <value>
Default Value
Normal compilation
© November 2008
Altera Corporation
6–188
Fitter Assignments
OPTIMIZE_SIGNAL_INTEGRITY
OPTIMIZE_SIGNAL_INTEGRITY
Type
Enumeration
■
Extra effort
■
Normal compilation
■
Off
Device Support
■
Cyclone III
Notes
Syntax
set_global_assignment -name OPTIMIZE_SIGNAL_INTEGRITY <value>
set_global_assignment -name OPTIMIZE_SIGNAL_INTEGRITY -entity <entity name> <value>
set_instance_assignment -name OPTIMIZE_SIGNAL_INTEGRITY -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
OPTIMIZE_TIMING
6–189
OPTIMIZE_TIMING
Type
Enumeration
■
Extra effort
■
Normal compilation
■
Off
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
6–190
Fitter Assignments
OPTIMIZE_TIMING
Syntax
set_global_assignment -name OPTIMIZE_TIMING <value>
Default Value
Normal compilation
Old Names
OPTIMIZE_INTERNAL_TIMING
USE_TIMING_DRIVEN_COMPILATION
© November 2008
Altera Corporation
Fitter Assignments
OUTPUT_BUFFER_DELAY
6–191
OUTPUT_BUFFER_DELAY
Specifies the delay value (in ps) for the Programmable Output Buffer Delay. Turning on this feature should
improve the output duty cycle at the cost of worse timing across the output buffer.
Specifies the delay value (in ps) for the Programmable Output Buffer Delay. Turning on this feature should
improve the output duty cycle at the cost of worse timing across the output buffer.
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name OUTPUT_BUFFER_DELAY -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name OUTPUT_BUFFER_DELAY 50 -to pin
See Also
■
"OUTPUT_BUFFER_DELAY_CONTROL" on page 6-195
© November 2008
Altera Corporation
6–192
Fitter Assignments
OUTPUT_BUFFER_DELAY_CONTROL
OUTPUT_BUFFER_DELAY_CONTROL
Sets the Programmable Output Buffer Delay control. Turning on this feature should improve the output
duty cycle at the cost of worse timing across the output buffer.
Type
Enumeration
■
Both Edges
■
Negative Edge
■
Off
■
Positive Edge
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name OUTPUT_BUFFER_DELAY_CONTROL -to <to> -entity <entity name>
<value>
Old Names
STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL
© November 2008
Altera Corporation
Fitter Assignments
OUTPUT_ENABLE_DELAY
6–193
OUTPUT_ENABLE_DELAY
Specifies the propagation delay to the output enable pin from internal logic or the output enable register
it is applied to anything other than an output pin or bidirectional pin.
Type
Integer
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name OUTPUT_ENABLE_DELAY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–194
Fitter Assignments
OUTPUT_ENABLE_GROUP
OUTPUT_ENABLE_GROUP
Assigns an output enable group number for the specified node. Turning on this option directs the Fitter to
view the specified nodes as an output enable group so as not to violate the requirements for the maximum
number of pins driving out of a VREF group when a voltage-referenced input pin or bidirectional pin is
present. For bidirectional pins, the Fitter determines all possible pins that may potentially drive out when
any bidirectional pin is driving in by looking at the output enable of all the bidirectional pins in the VREF
group. This behavior can result in the VREF group exceeding the maximum number of outputs and result
in a no fit. Turning on the 'Output Enable Group' option allows you to specify an output enable group for
specific pins, thus allowing you to specify which pins in the design are driving in and out at the same time.
The Fitter only considers pins as potential outputs when they are in separate output enable groups or
when they are not in an output enable group; by specifying an output enable group, you can lower the
total number of outputs in the VREF group when any pin is driving in. As a result, the Fitter does not
count all of the potential outputs of the bidirectional pins and the number of outputs in the VREF group
remains in the legal range. You should turn on this option when the Fitter cannot detect the output enable
group of the pins in the VREF group, for example when the output enables come from a state machine or
complex logic. For detailed information on the number of outputs supported by a VREF group, refer to
the data sheet for the device family, which is available from the Literature section of the Altera web site.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
Fitter Assignments
OUTPUT_ENABLE_GROUP
6–195
Syntax
set_instance_assignment -name OUTPUT_ENABLE_GROUP -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–196
Fitter Assignments
OUTPUT_ENABLE_REGISTER_DUPLICATION
OUTPUT_ENABLE_REGISTER_DUPLICATION
Duplicates a register that feeds to the output enable port of an I/O cell. Turning on this option can help
maximize timing performance, for example, by permitting fast clock-to-output times. This option is
ignored if it is applied to anything other than an output enable register that feeds to the output enable port
of an I/O cell.
Type
Boolean
Device Support
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name OUTPUT_ENABLE_REGISTER_DUPLICATION -to <to> -entity
© November 2008
Altera Corporation
Fitter Assignments
OUTPUT_ENABLE_ROUTING
6–197
OUTPUT_ENABLE_ROUTING
Specifies whether an output enable signal in an I/O cell should be driven by the peripheral bus or the
single-pin path. The Single-Pin setting drives the output enable signal with the local interconnect shared
by the I/O cell and the adjacent LAB. The Peripheral setting drives the output enable signal with a
peripheral control bus. This option is ignored if it is assigned to anything other than a logic function
assigned to an I/O cell or the signal that drives the output enable of the I/O cell.
Type
Enumeration
■
Peripheral
■
Single-Pin
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_instance_assignment -name OUTPUT_ENABLE_ROUTING -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–198
Fitter Assignments
OUTPUT_PIN_LOAD
OUTPUT_PIN_LOAD
Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard. Note: These
settings affect FPGA pins only. To specify board trace, termination, and capacitive load parameters for use
with Advanced I/O Timing, use the Board Trace Model tab. Capacitive loading is ignored if applied to
anything other than an output or bidirectional pin, or if Advanced I/O Timing is enabled.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
This assignment is copied to any duplicated nodes
Syntax
set_instance_assignment -name OUTPUT_PIN_LOAD -to <to> -entity <entity name> <value>
set_global_assignment -name OUTPUT_PIN_LOAD -section_id <section identifier> <value>
© November 2008
Altera Corporation
Fitter Assignments
OUTPUT_TERMINATION
6–199
OUTPUT_TERMINATION
Type
String
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name OUTPUT_TERMINATION -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–200
Fitter Assignments
OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
PAD_TO_CORE_DELAY
6–201
PAD_TO_CORE_DELAY
Specifies the propagation delay from an input or bidirectional pin to logic and embedded cells within the
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name PAD_TO_CORE_DELAY -to <to> -entity <entity name> <value>
set_instance_assignment -name PAD_TO_CORE_DELAY -from <from> -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–202
Fitter Assignments
PAD_TO_INPUT_REGISTER_DELAY
PAD_TO_INPUT_REGISTER_DELAY
Specifies the propagation delay from an input pin to the data input of the input register implemented in
the I/O cell associated with the pin. This is an advanced option that should be used only after you have
compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed
it is applied to anything other than an input or bidirectional pin.
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name PAD_TO_INPUT_REGISTER_DELAY -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
PCI_IO
6–203
PCI_IO
Turns on Peripheral Component Interconnect (PCI) compatibility for a pin. For example, when the VCCIO
of an EP20K400 device operates at 3.3 V and PCI I/O is turned on for a pin, the Compiler clamps the pin's
signal to the VCCIO value, thus making the pin 3.3-V PCI-compliant. This option is ignored if it is applied
to anything other than a pin or a top-level design entity.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
6–204
Fitter Assignments
PCI_IO
Syntax
set_global_assignment -name PCI_IO -entity <entity name> <value>
set_instance_assignment -name PCI_IO -to <to> -entity <entity name> <value>
set_global_assignment -name PCI_IO <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
6–205
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
Specifies that Quartus II should perform automatic insertion of pipeline stages for asynchronous clear and
asynchronous load signals during fitting to increase circuit performance. This option is useful for
asynchronous signals that are failing recovery and removal timing because they feed registers using a
high-speed clock.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING -entity
set_instance_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING -to
<to> -entity <entity name> <value>
Default Value
Off
© November 2008
Altera Corporation
6–206
Fitter Assignments
PHYSICAL_SYNTHESIS_COMBO_LOGIC
PHYSICAL_SYNTHESIS_COMBO_LOGIC
Specifies that the Fitter should perform physical synthesis optimizations on combinational logic during
fitting to increase circuit performance.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC -entity <entity name> <value>
set_instance_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC -to <to> -entity <entity
name> <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
6–207
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
Specifies that the Fitter should perform physical synthesis optimizations on combinational logic during
fitting to achieve a fit.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA -entity <entity
name> <value>
set_instance_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA -to <to> -entity
Default Value
Off
© November 2008
Altera Corporation
6–208
Fitter Assignments
PHYSICAL_SYNTHESIS_EFFORT
PHYSICAL_SYNTHESIS_EFFORT
Type
Enumeration
■
Extra
■
Fast
■
Normal
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT <value>
Default Value
Normal
Old Names
PHYSICAL_SYNTHESIS_EXTRA_EFFORT
© November 2008
Altera Corporation
Fitter Assignments
PHYSICAL_SYNTHESIS_LOG_FILE
6–209
PHYSICAL_SYNTHESIS_LOG_FILE
Type
String
Device Support
■
HardCopy II
■
HardCopy III
■
Stratix III
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
6–210
Fitter Assignments
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
Specifies that the Fitter should perform physical synthesis optimizations on logic and registers, specifically
allowing the mapping of logic and registers into unused memory blocks during fitting to achieve a fit.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA -entity
set_instance_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA -to <to>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
6–211
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
Specifies that the Fitter should perform physical synthesis optimizations on registers, specifically allowing
register duplication, during fitting to increase circuit performance.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION -entity <entity
name> <value>
set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION -to <to> -entity
Default Value
Off
© November 2008
Altera Corporation
6–212
Fitter Assignments
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
Specifies that the Fitter should perform physical synthesis optimizations on registers, specifically allowing
register retiming, during fitting to increase circuit performance.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING -entity <entity name>
<value>
set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING -to <to> -entity
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
PLACEMENT_EFFORT_MULTIPLIER
6–213
Type
String
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX9000
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
6–214
Fitter Assignments
Notes
Syntax
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER <value>
Default Value
1.0
© November 2008
Altera Corporation
Fitter Assignments
PLL_COMPENSATE
6–215
PLL_COMPENSATE
Allows you to specify an output pin as a compensation target for a PLL in ZERO_DELAY_BUFFER or
EXTERNAL_FEEDBACK mode, or an input pin or a group of input pins as compensation targets for a PLL
in SOURCE_SYNCHRONOUS mode. If assigned to an output pin, the pin must be fed by the external
clock output port of a PLL in a Stratix, Hardcopy Stratix or Cyclone device, or the compensated clock
output port of a PLL in other devices. Any other output pins fed by the same PLL generally are not delay
compensated, especially if they have different I/O standards. If assigned to an input pin or a group of
input pins, the input pins must drive input registers that are clocked by the compensated clock output port
of a PLL in SOURCE_SYNCHRONOUS mode. This option is ignored if it is applied to anything other than
an output or input pin as described previously.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name PLL_COMPENSATE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–216
Fitter Assignments
PLL_FORCE_OUTPUT_COUNTER
PLL_FORCE_OUTPUT_COUNTER
Forces which counter to use for a particular PLL clock output. By default the compiler will automatically
determine the best counter to use based on clock usage and other routing conflicts, but can be overridden
with this option. Using this option can cause clock routing problems, as the clock router cannot rotate
counters to resolve conflicts. Also see option PRESERVE_PLL_COUNTER_ORDER.
Type
Enumeration
■
C0
■
C1
■
C2
■
C3
■
C4
■
C5
■
C6
■
C7
■
C8
■
C9
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name PLL_FORCE_OUTPUT_COUNTER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
PLL_IGNORE_MIGRATION_DEVICES
6–217
PLL_IGNORE_MIGRATION_DEVICES
Forces the compiler to ignore the migration devices when calculating the PLL settings. Normally the PLL
is configured to work for all migration devices in addition to the current device. When this option is
enabled, the compiler will ignore the PLL constraints for the migration devices, and will only consider the
PLL constraints from the current device.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name PLL_IGNORE_MIGRATION_DEVICES -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–218
Fitter Assignments
PRESERVE_PLL_COUNTER_ORDER
PRESERVE_PLL_COUNTER_ORDER
Preserves the order of PLL clock outputs used when selecting corresponding output counters. For
example, a clk0 output will use a C0 counter and a clk2 output will use a C2 counter. Turning this option
can cause clock routing problems, as the clock router cannot rotate counters to resolve conflicts.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
6–219
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USE
D_LAB_TILES
Type
String
Device Support
■
Stratix III
■
Stratix IV
Notes
Syntax
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES <value>
Default Value
1.0
© November 2008
Altera Corporation
6–220
Fitter Assignments
PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
Type
Enumeration
■
Automatic
■
Force All Tiles with Failing Timing Paths to High Speed
■
Minimize Power Only
Device Support
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING <value>
Default Value
Automatic
© November 2008
Altera Corporation
Fitter Assignments
PROGRAMMABLE_PREEMPHASIS
6–221
PROGRAMMABLE_PREEMPHASIS
Implements control of programmable pre-emphasis, which helps compensate for high frequency losses.
This option is ignored if it is applied to anything other than an output or bidirectional pin, or a top-level
design entity containing output or bidirectional pins.
Type
Integer
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PROGRAMMABLE_PREEMPHASIS -entity <entity name> <value>
set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS -to <to> -entity <entity name>
<value>
set_global_assignment -name PROGRAMMABLE_PREEMPHASIS <value>
© November 2008
Altera Corporation
6–222
Fitter Assignments
PROGRAMMABLE_VOD
PROGRAMMABLE_VOD
Implements control of programmable VOD. This option is ignored if it is applied to anything other than an
output or bidirectional pin, or a top-level design entity containing output or bidirectional pins.
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name PROGRAMMABLE_VOD -entity <entity name> <value>
set_instance_assignment -name PROGRAMMABLE_VOD -to <to> -entity <entity name> <value>
set_global_assignment -name PROGRAMMABLE_VOD <value>
© November 2008
Altera Corporation
Fitter Assignments
QDR_D_PIN_GROUP
6–223
QDR_D_PIN_GROUP
Assigns a quad data rate (QDR) D (data) output pin group number to a specified pin. Turning on this
option allows the Fitter to view pins as a QDR D output pin group. I/O pins of a QDR D output pin group
must be placed in the DQ pin locations of a single DQS group. This option is ignored if is assigned to
anything other than an I/O pin.
Type
Integer
Device Support
■
Cyclone II
Notes
Syntax
set_instance_assignment -name QDR_D_PIN_GROUP -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–224
Fitter Assignments
RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
Allows you to specify whether the M4K and M144K memory block read operations depend upon the read
clock's duty cycle. When M9K or M144K memory blocks are driven by a read clock with a very narrow
pulse, they can go into a locked, inactive state. Turning on this option allows the M9K and M144K memory
blocks to operate dependent upon the read clock's duty cycle to prevent the memory blocks from going
into to an inactive state; however, turning on this option may degrade the performance of the M9K or
M144K blocks.
Type
Enumeration
■
Off
■
On
Device Support
■
Stratix III
Notes
Syntax
set_global_assignment -name RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY -entity <entity
name> <value>
set_instance_assignment -name RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY -to <to>
set_global_assignment -name RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY <value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_ALL_UNUSED_PINS
6–225
Type
Enumeration
■
As input tri-stated
■
As input tri-stated with bus-hold
■
As input tri-stated with weak pull-up
■
■
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy Stratix
■
MAX II
■
MAX7000AE
■
MAX7000B
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
© November 2008
Altera Corporation
6–226
Fitter Assignments
Syntax
set_global_assignment -name RESERVE_ALL_UNUSED_PINS <value>
Default Value
Old Names
RESERVED_ALL_UNUSED_PINS
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
6–227
RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
Type
Enumeration
■
As input tri-stated
■
As input tri-stated with bus-hold
■
■
■
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP <value>
Default Value
© November 2008
Altera Corporation
6–228
Fitter Assignments
RESERVE_ASDO_AFTER_CONFIGURATION
RESERVE_ASDO_AFTER_CONFIGURATION
Type
Enumeration
■
As input tri-stated
■
Use as regular IO
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION <value>
Default Value
Use as regular IO
Old Names
RESERVE_SDO_AFTER_CONFIGURATION
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_DATA0_AFTER_CONFIGURATION
6–229
Type
Enumeration
■
As input tri-stated
■
■
■
Compiler configured
■
Use as regular IO
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION <value>
Default Value
As input tri-stated
© November 2008
Altera Corporation
6–230
Fitter Assignments
Type
Enumeration
■
As input tri-stated
■
■
■
Compiler configured
■
Use as regular IO
Device Support
■
Cyclone III
Syntax
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION <value>
Default Value
As input tri-stated
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
6–231
Type
Enumeration
■
As input tri-stated
■
■
■
Use as regular IO
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION <value>
© November 2008
Altera Corporation
6–232
Fitter Assignments
Default Value
Use as regular IO
© November 2008
Altera Corporation
Fitter Assignments
6–233
Type
Enumeration
■
As input tri-stated
■
■
■
Compiler configured
■
Use as regular IO
Device Support
■
Cyclone III
Syntax
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION <value>
Default Value
Use as regular IO
© November 2008
Altera Corporation
6–234
Fitter Assignments
RESERVE_DCLK_AFTER_CONFIGURATION
RESERVE_DCLK_AFTER_CONFIGURATION
Type
Enumeration
■
Compiler configured
■
■
Use as regular IO
Device Support
■
Cyclone III
Syntax
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION <value>
Default Value
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_FLASH_NCE_AFTER_CONFIGURATION
6–235
RESERVE_FLASH_NCE_AFTER_CONFIGURATION
Type
Enumeration
■
As input tri-stated
■
■
■
Compiler configured
■
Use as regular IO
Device Support
■
Cyclone III
Syntax
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION <value>
Default Value
As input tri-stated
© November 2008
Altera Corporation
6–236
Fitter Assignments
RESERVE_NCEO_AFTER_CONFIGURATION
RESERVE_NCEO_AFTER_CONFIGURATION
Type
Enumeration
■
■
■
Use as regular IO
Device Support
■
FLEX6000
Syntax
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION <value>
Default Value
Use as regular IO
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
6–237
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
Type
Enumeration
■
As input tri-stated
■
■
■
Use as regular IO
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION <value>
Default Value
Use as regular IO
© November 2008
Altera Corporation
6–238
Fitter Assignments
RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
Type
Enumeration
■
As input tri-stated
■
■
■
Compiler configured
■
Use as regular IO
Device Support
■
Cyclone III
Syntax
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION <value>
Default Value
Use as regular IO
Old Names
RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION
© November 2008
Altera Corporation
Fitter Assignments
RESERVE_RDYNBUSY_AFTER_CONFIGURATION
6–239
RESERVE_RDYNBUSY_AFTER_CONFIGURATION
Type
Enumeration
■
As input tri-stated
■
■
■
Use as regular IO
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION <value>
Default Value
Use as regular IO
© November 2008
Altera Corporation
6–240
Fitter Assignments
ROUTER_EFFORT_MULTIPLIER
Type
String
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX8000
■
HardCopy Stratix
■
MAX II
■
MAX9000
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
Fitter Assignments
6–241
Syntax
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER <value>
Default Value
1.0
© November 2008
Altera Corporation
6–242
Fitter Assignments
ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
Type
Enumeration
■
Auto
■
Off
■
On
Device Support
■
Arria GX
■
Cyclone
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION <value>
Default Value
AUTO
© November 2008
Altera Corporation
Fitter Assignments
ROUTER_REGISTER_DUPLICATION
6–243
ROUTER_REGISTER_DUPLICATION
Type
Enumeration
■
Auto
■
Off
■
On
Device Support
■
Arria GX
■
Cyclone
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ROUTER_REGISTER_DUPLICATION <value>
Default Value
AUTO
© November 2008
Altera Corporation
6–244
Fitter Assignments
ROUTER_TIMING_OPTIMIZATION_LEVEL
Type
Enumeration
■
MAXIMUM
■
MINIMUM
■
Normal
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX8000
■
HardCopy Stratix
■
MAX II
■
MAX9000
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
Fitter Assignments
6–245
Notes
Syntax
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL <value>
Default Value
Normal
© November 2008
Altera Corporation
6–246
Fitter Assignments
ROUTING_BACK_ANNOTATION_MODE
ROUTING_BACK_ANNOTATION_MODE
Type
Enumeration
■
ADVANCED
■
Normal
■
Off
Device Support
Notes
Syntax
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE <value>
© November 2008
Altera Corporation
Fitter Assignments
ROW_GLOBAL_SIGNAL
6–247
ROW_GLOBAL_SIGNAL
Specifies whether the signal should be available throughout the device on the global routing paths
available within each row. Row-global signals can be both pin- and logic-driven. Clock, output enable, and
register control signals can be row-global signals. Turning this option on for a pin or a single-output logic
function signal is equivalent to feeding the signal through a ROW_GLOBAL buffer.
Type
Boolean
Device Support
■
Mercury
Syntax
set_instance_assignment -name ROW_GLOBAL_SIGNAL -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–248
Fitter Assignments
SAVE_INTERMEDIATE_FITTING_RESULTS
SAVE_INTERMEDIATE_FITTING_RESULTS
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
SCE_PIN
6–249
SCE_PIN
Specifies the SCE configuration pin.
Type
Boolean
Device Support
■
Cyclone III
Notes
Syntax
set_instance_assignment -name SCE_PIN -to <to> <value>
© November 2008
Altera Corporation
6–250
Fitter Assignments
SDO_PIN
SDO_PIN
Specifies the SDO configuration pin.
Type
Boolean
Device Support
■
Cyclone III
Notes
Syntax
set_instance_assignment -name SDO_PIN -to <to> <value>
© November 2008
Altera Corporation
Fitter Assignments
SEED
6–251
SEED
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name SEED <value>
Default Value
1
Old Names
INITIAL_PLACEMENT_CONFIGURATION
© November 2008
Altera Corporation
6–252
Fitter Assignments
SLEW_RATE
SLEW_RATE
Implements control of low-to-high/high-to-low transitions on output pins to help reduce switching noise.
When a large number of output pins switch simultaneously, pins that use the lower Slew Rate option help
reduce switching noise. This option is ignored if it is applied to anything other than an output or
bidirectional pin, or a top-level design entity containing output or bidirectional pins. Note that using this
option may increase the delay for output or bidir pins, which can affect slack on Tco paths for the pins this
is applied to.
Type
Integer
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SLEW_RATE -entity <entity name> <value>
set_instance_assignment -name SLEW_RATE -to <to> -entity <entity name> <value>
set_global_assignment -name SLEW_RATE <value>
© November 2008
Altera Corporation
Fitter Assignments
SLOW_SLEW_RATE
6–253
SLOW_SLEW_RATE
Implements slow low-to-high/high-to-low transitions on output pins to help reduce switching noise.
When a large number of output pins switch simultaneously, pins that use the Slow Slew Rate option help
reduce switching noise. This option is ignored if it is applied to anything other than an output or
bidirectional pin, or a top-level design entity containing output or bidirectional pins. Note that using this
option increases the delay for output or bidir pins, which can affect slack on Tco paths for the pins this is
applied to.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
MAX9000
■
Mercury
■
Stratix
■
Stratix GX
© November 2008
Altera Corporation
6–254
Fitter Assignments
SLOW_SLEW_RATE
Notes
Syntax
set_global_assignment -name SLOW_SLEW_RATE -entity <entity name> <value>
set_instance_assignment -name SLOW_SLEW_RATE -to <to> -entity <entity name> <value>
set_global_assignment -name SLOW_SLEW_RATE <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STOP_AFTER_CONGESTION_MAP
6–255
STOP_AFTER_CONGESTION_MAP
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name STOP_AFTER_CONGESTION_MAP <value>
Default Value
Off
© November 2008
Altera Corporation
6–256
Fitter Assignments
STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
6–257
STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE <value>
Default Value
Off
© November 2008
Altera Corporation
6–258
Fitter Assignments
STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
6–259
STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B <value>
Default Value
Off
© November 2008
Altera Corporation
6–260
Fitter Assignments
STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCH
ER
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
<value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
6–261
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOU
RCE
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
<value>
Default Value
Off
© November 2008
Altera Corporation
6–262
Fitter Assignments
STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_M
ODE
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
<value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_POST8B10B_LOOPBACK
6–263
STRATIXGX_ALLOW_POST8B10B_LOOPBACK
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK <value>
Default Value
Off
© November 2008
Altera Corporation
6–264
Fitter Assignments
STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
6–265
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN
_DOUBLE_DATA_WIDTH_MODE
Type
Boolean
Device Support
■
Stratix GX
Syntax
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE <value>
Default Value
Off
© November 2008
Altera Corporation
6–266
Fitter Assignments
STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS <value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
6–267
STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE <value>
Default Value
Off
© November 2008
Altera Corporation
6–268
Fitter Assignments
STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCH
ER
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
<value>
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
6–269
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOU
RCE
Type
Boolean
Device Support
■
Stratix GX
Syntax
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
<value>
Default Value
Off
© November 2008
Altera Corporation
6–270
Fitter Assignments
STRATIXGX_TERMINATION_VALUE
STRATIXGX_TERMINATION_VALUE
Allows the Compiler to configure the on-chip termination (OCT) for a Stratix GX gigabit transceiver block
(GXB) receiver channel input pin, GXB transmitter channel output pin, GXB transmitter PLL clock input
pin, or GXB receiver channel clock input pin.
Type
Enumeration
■
OCT 100 Ohms
■
OCT 120 Ohms
■
OCT 150 Ohms
■
Off
Device Support
■
Stratix GX
Notes
Syntax
set_instance_assignment -name STRATIXGX_TERMINATION_VALUE -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
STRATIXIIGX_TERMINATION_VALUE
6–271
STRATIXIIGX_TERMINATION_VALUE
Allows the Compiler to configure the on-chip termination (OCT) for a Stratix II GX gigabit transceiver
block (GXB) receiver channel input pin or GXB transmitter channel output pin.
Type
Enumeration
■
OCT 100 Ohms
■
OCT 120 Ohms
■
OCT 150 Ohms
■
Off
Device Support
■
Arria GX
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name STRATIXIIGX_TERMINATION_VALUE -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
6–272
Fitter Assignments
STRATIXIII_CONFIGURATION_SCHEME
STRATIXIII_CONFIGURATION_SCHEME
Type
Enumeration
■
Active Serial
■
■
Passive Serial
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
© November 2008
Altera Corporation
Fitter Assignments
STRATIXIII_MRAM_COMPATIBILITY
6–273
STRATIXIII_MRAM_COMPATIBILITY
Type
Boolean
Device Support
■
Stratix III
Notes
Syntax
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY <value>
Default Value
On
© November 2008
Altera Corporation
6–274
Fitter Assignments
STRATIXIII_UPDATE_MODE
STRATIXIII_UPDATE_MODE
Type
Enumeration
■
Remote
■
Standard
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name STRATIXIII_UPDATE_MODE <value>
Default Value
Standard
© November 2008
Altera Corporation
Fitter Assignments
STRATIXII_CONFIGURATION_SCHEME
6–275
STRATIXII_CONFIGURATION_SCHEME
Type
Enumeration
■
Active Serial
■
■
■
Passive Serial
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
Old Names
STRATIX_II_CONFIGURATION_SCHEME
© November 2008
Altera Corporation
6–276
Fitter Assignments
STRATIXII_TERMINATION
STRATIXII_TERMINATION
Type
Enumeration
■
Differential
■
Off
■
Parallel 50 Ohms with Calibration
■
Series 25 Ohms with Calibration
■
Series 25 Ohms without Calibration
■
Series 50 Ohms with Calibration
■
Series 50 Ohms without Calibration
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name STRATIXII_TERMINATION -to <to> -entity <entity name>
<value>
Old Names
Termination -- Stratix II/Stratix II GX/HardCopy II
© November 2008
Altera Corporation
Fitter Assignments
STRATIX_CONFIGURATION_SCHEME
6–277
STRATIX_CONFIGURATION_SCHEME
Type
Enumeration
■
■
■
Passive Serial
Device Support
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME <value>
Default Value
Passive Serial
© November 2008
Altera Corporation
6–278
Fitter Assignments
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
Type
Enumeration
■
Large
■
Medium
■
Off
■
On
■
Small
Device Support
■
Cyclone
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to <to>
set_instance_assignment -name STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -from
<from> -to <to> -entity <entity name> <value>
Old Names
Decrease Input Delay to Internal Cells -- Stratix/Stratix GX/Cyclone
YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
© November 2008
Altera Corporation
Fitter Assignments
STRATIX_DEVICE_IO_STANDARD
6–279
STRATIX_DEVICE_IO_STANDARD
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD <value>
Old Names
YEAGER_DEVICE_IO_STANDARD
© November 2008
Altera Corporation
6–280
Fitter Assignments
STRATIX_UPDATE_MODE
STRATIX_UPDATE_MODE
Type
Enumeration
■
Local
■
Remote
■
Standard
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name STRATIX_UPDATE_MODE <value>
Default Value
Standard
Old Names
YEAGER_UPDATE_MODE
© November 2008
Altera Corporation
Fitter Assignments
SYNCHRONIZER_IDENTIFICATION
6–281
Specifies the level of synchronizer identification to perform during compilation. This option controls how
aggressively the TimeQuest Timing Analyzer will identify registers as being part of a synchronization
register chain. A synchronization register chain is a sequence of registers with the same clock with no
fanout in between, that is driven by a pin, or logic from another clock domain. If this option is set to 'Off',
the TimeQuest Timing Analyzer will not identify the specified nodes as synchronization registers. If the
option is set to 'Auto', the TimeQuest Timing Analyzer will check to see if this register is a valid
synchronization register, and will traverse the netlist from this register to identify a chain of back-to-back
registers that are functioning as a synchronization chain. If this option is set to 'Forced If Asynchronous',
the TimeQuest Timing Analyzer will look through the fanout of this register for a synchronization register
chain by traversing through combinational logic if necessary. If this setting is set to 'Forced', then the
specified register, or all registers within the specified entity, will be always be identified as the head of a
synchronizer chain. The 'Forced' setting should not be applied to the entire design, as this would identify
all registers in the design as synchronizers. If a synchronization register chain is found, then the
TimeQuest Timing Analyzer will report the Mean Time Between Failure (MTBF) for the chain.
Type
Enumeration
■
Auto
■
Forced
■
Forced If Asynchronous
■
Off
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION <value>
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION -entity <entity name> <value>
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION -to <to> -entity <entity name>
<value>
Default Value
Off
Old Names
© November 2008
Altera Corporation
6–282
Fitter Assignments
ANALYZE_METASTABILITY
© November 2008
Altera Corporation
Fitter Assignments
SYNCHRONIZER_TOGGLE_RATE
6–283
SYNCHRONIZER_TOGGLE_RATE
Specifies the toggle rate of this register. The units for this value are in transitions per second, and must be
positive. This is used when calculating the Mean Time Between Failures (MTBF) of a synchronizer chain in
the Metastability Report. This only applies when the TimeQuest Timing Analyzer is used. You can specify
the desired frequency setting on the first register of a synchronizer chain, and this will determine the data
rate used in the MTBF estimation. There are two other assignments associated with toggle rates. The I/O
Maximum Toggle Rate is only used for pins, and specifies the worst-case toggle rates used for signal
integrity purposes. The Power Toggle Rate assignment is used to specify the expected time-averaged
toggle rate, and is used by the Power Analyzer to estimate time-averaged power consumption.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name SYNCHRONIZER_TOGGLE_RATE -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–284
Fitter Assignments
SYNCHRONOUS_GROUP
SYNCHRONOUS_GROUP
Assigns a synchronous group number for the specified node. This option directs the SSN Analyzer to view
the specified nodes as a synchronous group so as not to have them aggress on each other during SSN
voltage noise analysis.
Type
Integer
Device Support
■
Cyclone III
Notes
Syntax
set_instance_assignment -name SYNCHRONOUS_GROUP -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
T11_DELAY
6–285
T11_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name T11_DELAY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–286
Fitter Assignments
T4_DELAY
T4_DELAY
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name T4_DELAY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
T8_DELAY0
6–287
T8_DELAY0
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name T8_DELAY0 -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
6–288
Fitter Assignments
T8_DELAY1
T8_DELAY1
Type
Integer
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name T8_DELAY1 -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
Fitter Assignments
TERMINATION
6–289
TERMINATION
Type
Enumeration
■
Differential
■
Off
Device Support
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name TERMINATION -to <to> -entity <entity name> <value>
Old Names
Termination -- Stratix / Stratix GX / HardCopy Stratix / Mercury
YEAGER_OCT_AND_IMPEDANCE_MATCHING
© November 2008
Altera Corporation
6–290
Fitter Assignments
TERMINATION_CONTROL_BLOCK
TERMINATION_CONTROL_BLOCK
Specifies the control block used for calibrated on-chip termination (OCT) and impedance matching for an
I/O pin. OCT helps to prevent signal reflections and maintain signal integrity. This option is ignored if it is
applied to anything other than an I/O pad, input buffer, or output buffer. This option should only be used
on I/O pins which have a calibrated termination assignment.
Type
String
Device Support
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name TERMINATION_CONTROL_BLOCK -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
Fitter Assignments
TREAT_BIDIR_AS_OUTPUT
6–291
TREAT_BIDIR_AS_OUTPUT
Directs the bidirectional pin to be essentially treated as an output pin meaning that the input path is used
for feedback from the output path.
Type
Boolean
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT <value>
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT -entity <entity name> <value>
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
6–292
Fitter Assignments
TURBO_BIT
TURBO_BIT
Controls the speed vs. power usage trade-off for a macrocell (that is, for an embedded cell within an
Embedded System Block [ESB] that is set to use Product Term mode). If the Turbo Bit is on, the macrocell's
speed increases; if it is off, its power consumption decreases. This option is ignored if you select 'ROM' or
'LUT' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
Mercury
Notes
Syntax
set_global_assignment -name TURBO_BIT <value>
set_global_assignment -name TURBO_BIT -entity <entity name> <value>
set_instance_assignment -name TURBO_BIT -to <to> -entity <entity name> <value>
Default Value
On
© November 2008
Altera Corporation
Fitter Assignments
USER_START_UP_CLOCK
6–293
USER_START_UP_CLOCK
This option allows user to select which clock source is used for initialization, either
the internal oscillator or external clocks provided on the CLKUSR pin. This clock can
synchronize the initialization of multiple devices.
The default setting is to make CLKUSR pin available as a user I/O pin.
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
© November 2008
Altera Corporation
6–294
Fitter Assignments
USER_START_UP_CLOCK
Syntax
set_global_assignment -name USER_START_UP_CLOCK <value>
Example
set_global_assignment -name USER_START_UP_CLOCK ON
set_global_assignment -name USER_START_UP_CLOCK OFF
Default Value
Off
Old Names
User Specified Start-up clock
See Also
■
"ACTIVE_SERIAL_CLOCK" on page 6-1
© November 2008
Altera Corporation
Fitter Assignments
VCCIO_CURRENT_1PT8V
6–295
VCCIO_CURRENT_1PT8V
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_1PT8V <value>
© November 2008
Altera Corporation
6–296
Fitter Assignments
VCCIO_CURRENT_2PT5V
VCCIO_CURRENT_2PT5V
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_2PT5V <value>
© November 2008
Altera Corporation
Fitter Assignments
VCCIO_CURRENT_GTL
6–297
VCCIO_CURRENT_GTL
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_GTL <value>
© November 2008
Altera Corporation
6–298
Fitter Assignments
VCCIO_CURRENT_GTL_PLUS
VCCIO_CURRENT_GTL_PLUS
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_GTL_PLUS <value>
© November 2008
Altera Corporation
Fitter Assignments
VCCIO_CURRENT_LVCMOS
6–299
VCCIO_CURRENT_LVCMOS
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_LVCMOS <value>
© November 2008
Altera Corporation
6–300
Fitter Assignments
VCCIO_CURRENT_LVTTL
VCCIO_CURRENT_LVTTL
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_LVTTL <value>
© November 2008
Altera Corporation
Fitter Assignments
VCCIO_CURRENT_PCI
6–301
VCCIO_CURRENT_PCI
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_PCI <value>
© November 2008
Altera Corporation
6–302
Fitter Assignments
VCCIO_CURRENT_SSTL2_CLASS1
Type
Integer
Device Support
Syntax
set_global_assignment -name VCCIO_CURRENT_SSTL2_CLASS1 <value>
© November 2008
Altera Corporation
Fitter Assignments
6–303
Type
Integer
Device Support
Syntax
© November 2008
Altera Corporation
6–304
Fitter Assignments
Type
Integer
Device Support
Syntax
© November 2008
Altera Corporation
Fitter Assignments
6–305
Type
Integer
Device Support
Syntax
© November 2008
Altera Corporation
6–306
Fitter Assignments
VCCPD_VOLTAGE
VCCPD_VOLTAGE
Type
String
Device Support
■
Arria GX
■
HardCopy II
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name VCCPD_VOLTAGE -section_id <section identifier> <value>
Default Value
3.3V, requires section identifier
© November 2008
Altera Corporation
Fitter Assignments
WEAK_PULL_UP_RESISTOR
6–307
Enables the weak pull-up resistor when the device is operating in user mode. This option pulls a
high-impedance bus signal to VCC. The Weak Pull-Up Resistor option should not be used at the same time
as the Enable Bus-Hold Circuitry option. This option is ignored if it is applied to anything other than a pin.
Type
Boolean
Device Support
■
APEX II
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX7000B
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name WEAK_PULL_UP_RESISTOR <value>
set_global_assignment -name WEAK_PULL_UP_RESISTOR -entity <entity name> <value>
set_instance_assignment -name WEAK_PULL_UP_RESISTOR -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
6–308
Fitter Assignments
Default Value
Off
© November 2008
Altera Corporation
Fitter Assignments
XSTL_INPUT_ALLOW_SE_BUFFER
6–309
Allows the pin with a Differential-XSTL IO-standard to be used with a single-ended input buffer.
Type
Boolean
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER <value>
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER -entity <entity name> <value>
set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER -to <to> -entity <entity name>
<value>
Default Value
Off
© November 2008
Altera Corporation
6–310
Fitter Assignments
© November 2008
Altera Corporation
7. Power Estimation Assignments
POWER_AUTO_COMPUTE_TJ
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_AUTO_COMPUTE_TJ <value>
Default Value
On
© November 2008
Altera Corporation
7–2
Power Estimation Assignments
POWER_BOARD_TEMPERATURE
POWER_BOARD_TEMPERATURE
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_BOARD_TEMPERATURE <value>
Default Value
25
© November 2008
Altera Corporation
POWER_BOARD_THERMAL_MODEL
7–3
POWER_BOARD_THERMAL_MODEL
Type
String
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_BOARD_THERMAL_MODEL <value>
© November 2008
Altera Corporation
7–4
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE <value>
Default Value
12.5%
© November 2008
Altera Corporation
POWER_DEFAULT_TOGGLE_RATE
7–5
POWER_DEFAULT_TOGGLE_RATE
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE <value>
Default Value
12.5%
© November 2008
Altera Corporation
7–6
POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR
POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR
Type
String
Device Support
■
MAX II
Notes
Syntax
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR <value>
© November 2008
Altera Corporation
POWER_HSSI
7–7
POWER_HSSI
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_HSSI <value>
© November 2008
Altera Corporation
7–8
POWER_HSSI_LEFT
POWER_HSSI_LEFT
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_HSSI_LEFT <value>
© November 2008
Altera Corporation
POWER_HSSI_RIGHT
7–9
POWER_HSSI_RIGHT
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_HSSI_RIGHT <value>
© November 2008
Altera Corporation
7–10
POWER_HSSI_VCCHIP_LEFT
POWER_HSSI_VCCHIP_LEFT
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_HSSI_VCCHIP_LEFT <value>
© November 2008
Altera Corporation
POWER_HSSI_VCCHIP_RIGHT
7–11
POWER_HSSI_VCCHIP_RIGHT
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_HSSI_VCCHIP_RIGHT <value>
© November 2008
Altera Corporation
7–12
POWER_INPUT_FILE_NAME
POWER_INPUT_FILE_NAME
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_INPUT_FILE_NAME -entity <entity name> -section_id
© November 2008
Altera Corporation
POWER_INPUT_FILE_TYPE
7–13
POWER_INPUT_FILE_TYPE
Type
Enumeration
■
SAF
■
VCD
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name POWER_INPUT_FILE_TYPE -entity <entity name> -section_id
© November 2008
Altera Corporation
7–14
POWER_INPUT_SAF_NAME
POWER_INPUT_SAF_NAME
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name POWER_INPUT_SAF_NAME <value>
© November 2008
Altera Corporation
POWER_INPUT_VCD_FILE_NAME
7–15
POWER_INPUT_VCD_FILE_NAME
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name POWER_INPUT_VCD_FILE_NAME <value>
© November 2008
Altera Corporation
7–16
POWER_OCS_VALUE
POWER_OCS_VALUE
Type
String
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_OCS_VALUE <value>
© November 2008
Altera Corporation
POWER_OJB_VALUE
7–17
POWER_OJB_VALUE
Type
String
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_OJB_VALUE <value>
© November 2008
Altera Corporation
7–18
POWER_OSA_VALUE
POWER_OSA_VALUE
Type
String
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_OSA_VALUE <value>
© November 2008
Altera Corporation
POWER_OUTPUT_SAF_NAME
7–19
POWER_OUTPUT_SAF_NAME
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_OUTPUT_SAF_NAME <value>
© November 2008
Altera Corporation
7–20
POWER_PRESET_COOLING_SOLUTION
POWER_PRESET_COOLING_SOLUTION
Type
String
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION <value>
© November 2008
Altera Corporation
POWER_READ_INPUT_FILE
7–21
POWER_READ_INPUT_FILE
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name POWER_READ_INPUT_FILE -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
7–22
POWER_REPORT_POWER_DISSIPATION
POWER_REPORT_POWER_DISSIPATION
Specifies whether the PowerPlay Power Analyzer should report the thermal power dissipation calculated
during power analysis in the Thermal Power Dissipation By Block report panel.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION <value>
set_instance_assignment -name POWER_REPORT_POWER_DISSIPATION -to <to> -entity <entity
name> <value>
Default Value
Off
© November 2008
Altera Corporation
POWER_REPORT_SIGNAL_ACTIVITY
7–23
POWER_REPORT_SIGNAL_ACTIVITY
Specifies whether the PowerPlay Power Analyzer should report the signal activities assumed for power
analysis, and the sources for those activities. Signal activity consists of both the static probability and the
toggle rate for the signals generated by the node or entity.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY <value>
set_instance_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -to <to> -entity <entity
name> <value>
Default Value
Off
© November 2008
Altera Corporation
7–24
POWER_SIGNAL_ACTIVITY_END_TIME
POWER_SIGNAL_ACTIVITY_END_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name POWER_SIGNAL_ACTIVITY_END_TIME <value>
© November 2008
Altera Corporation
POWER_SIGNAL_ACTIVITY_START_TIME
7–25
POWER_SIGNAL_ACTIVITY_START_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name POWER_SIGNAL_ACTIVITY_START_TIME <value>
© November 2008
Altera Corporation
7–26
POWER_STATIC_PROBABILITY
POWER_STATIC_PROBABILITY
Specifies the fraction of time the signals generated by the node or entity are expected to be at VCC.
Allowable values range from and include 0.0 through 1.0.
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_instance_assignment -name POWER_STATIC_PROBABILITY -to <to> <value>
© November 2008
Altera Corporation
POWER_TJ_VALUE
7–27
POWER_TJ_VALUE
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_TJ_VALUE <value>
Default Value
25
© November 2008
Altera Corporation
7–28
POWER_TOGGLE_RATE
POWER_TOGGLE_RATE
Specifies the toggle rate assumed by power estimation for the signals generated by this node or entity. The
units for this value are transitions per second and the value must be positive. The value provided should
be the expected time-averaged toggle rate, rather than worst case (highest possible) toggle rate. A
different assignment, Toggle Rate, applies to I/O pins only and is used by the Fitter and by I/O
Assignment Analysis to verify signal integrity under worst case conditions (highest possible toggle rate).
Use the Synchronizer Toggle Rate if you want to configure the data rates used for Metastability Reporting
in the TimeQuest Timing Analyzer.
Type
Integer
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_instance_assignment -name POWER_TOGGLE_RATE -to <to> <value>
© November 2008
Altera Corporation
POWER_TOGGLE_RATE_PERCENTAGE
7–29
POWER_TOGGLE_RATE_PERCENTAGE
Specifies the toggle rate, as a percentage of clock domain frequency, assumed by power estimation for the
signals generated by this node or entity. This percentage acts as a multiplier for the clock domain
frequency of the given node. For example, a toggle rate percentage of 12.5 on a node with a clock domain
frequency of 96 MHz would result in a toggle rate of 12 million transitions per second. The percentage
value must be positive and can take on values greater than 100. The value provided should be
representative of the expected time-averaged toggle rate, rather than worst case (highest possible) toggle
rate.
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_instance_assignment -name POWER_TOGGLE_RATE_PERCENTAGE -to <to> <value>
© November 2008
Altera Corporation
7–30
POWER_USE_CUSTOM_COOLING_SOLUTION
POWER_USE_CUSTOM_COOLING_SOLUTION
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION <value>
Default Value
Off
© November 2008
Altera Corporation
POWER_USE_DEVICE_CHARACTERISTICS
7–31
POWER_USE_DEVICE_CHARACTERISTICS
Type
Enumeration
■
MAXIMUM
■
TYPICAL
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS <value>
Default Value
TYPICAL
© November 2008
Altera Corporation
7–32
POWER_USE_INPUT_FILE
POWER_USE_INPUT_FILE
Type
Enumeration
■
No File
■
Signal Activity File
■
VCD File
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name POWER_USE_INPUT_FILE <value>
Default Value
No File
© November 2008
Altera Corporation
POWER_USE_INPUT_FILES
7–33
POWER_USE_INPUT_FILES
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_USE_INPUT_FILES <value>
Default Value
Off
© November 2008
Altera Corporation
7–34
POWER_USE_PVA
POWER_USE_PVA
Type
Boolean
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_USE_PVA <value>
Default Value
On
© November 2008
Altera Corporation
POWER_USE_TA_VALUE
7–35
POWER_USE_TA_VALUE
Type
Integer
Device Support
■
Arria GX
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_USE_TA_VALUE <value>
Default Value
25
© November 2008
Altera Corporation
7–36
POWER_VCCA_L_USER_OPTION
POWER_VCCA_L_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCA_L_USER_OPTION <value>
© November 2008
Altera Corporation
POWER_VCCA_R_USER_OPTION
7–37
POWER_VCCA_R_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCA_R_USER_OPTION <value>
© November 2008
Altera Corporation
7–38
POWER_VCCH_GXBL_USER_OPTION
POWER_VCCH_GXBL_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCH_GXBL_USER_OPTION <value>
© November 2008
Altera Corporation
POWER_VCCH_GXBR_USER_OPTION
7–39
POWER_VCCH_GXBR_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCH_GXBR_USER_OPTION <value>
© November 2008
Altera Corporation
7–40
POWER_VCCH_GXB_USER_OPTION
POWER_VCCH_GXB_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCH_GXB_USER_OPTION <value>
© November 2008
Altera Corporation
POWER_VCCIO_USER_OPTION
7–41
POWER_VCCIO_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCIO_USER_OPTION <value>
© November 2008
Altera Corporation
7–42
POWER_VCCL_GXB_USER_OPTION
POWER_VCCL_GXB_USER_OPTION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name POWER_VCCL_GXB_USER_OPTION <value>
© November 2008
Altera Corporation
POWER_VCD_FILE_END_TIME
7–43
POWER_VCD_FILE_END_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name POWER_VCD_FILE_END_TIME -entity <entity name> -section_id
© November 2008
Altera Corporation
7–44
POWER_VCD_FILE_START_TIME
POWER_VCD_FILE_START_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name POWER_VCD_FILE_START_TIME -entity <entity name> -section_id
© November 2008
Altera Corporation
POWER_VCD_FILTER_GLITCHES
7–45
POWER_VCD_FILTER_GLITCHES
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name POWER_VCD_FILTER_GLITCHES <value>
Default Value
On
© November 2008
Altera Corporation
7–46
VCCA_L_USER_VOLTAGE
VCCA_L_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCA_L_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCA_PLL_USER_VOLTAGE
7–47
VCCA_PLL_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCA_PLL_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–48
VCCA_R_USER_VOLTAGE
VCCA_R_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCA_R_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCA_USER_VOLTAGE
7–49
VCCA_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCA_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–50
VCCD_PLL_USER_VOLTAGE
VCCD_PLL_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCD_PLL_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCD_USER_VOLTAGE
7–51
VCCD_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCD_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–52
VCCHIP_L_USER_VOLTAGE
VCCHIP_L_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCHIP_L_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCHIP_R_USER_VOLTAGE
7–53
VCCHIP_R_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCHIP_R_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–54
VCCH_GXBL_USER_VOLTAGE
VCCH_GXBL_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCH_GXBL_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCH_GXBR_USER_VOLTAGE
7–55
VCCH_GXBR_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCH_GXBR_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–56
VCCH_GXB_USER_VOLTAGE
VCCH_GXB_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCH_GXB_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCINT_USER_VOLTAGE
7–57
VCCINT_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCINT_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–58
VCCIO_USER_VOLTAGE
VCCIO_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCIO_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCL_GXBL_USER_VOLTAGE
7–59
VCCL_GXBL_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCL_GXBL_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–60
VCCL_GXBR_USER_VOLTAGE
VCCL_GXBR_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCL_GXBR_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCL_GXB_USER_VOLTAGE
7–61
VCCL_GXB_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCL_GXB_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–62
VCCL_USER_VOLTAGE
VCCL_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCL_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCPT_USER_VOLTAGE
7–63
VCCPT_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCPT_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–64
VCCR_L_USER_VOLTAGE
VCCR_L_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCR_L_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCR_R_USER_VOLTAGE
7–65
VCCR_R_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCR_R_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–66
VCCT_L_USER_VOLTAGE
VCCT_L_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCT_L_USER_VOLTAGE <value>
© November 2008
Altera Corporation
VCCT_R_USER_VOLTAGE
7–67
VCCT_R_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCCT_R_USER_VOLTAGE <value>
© November 2008
Altera Corporation
7–68
VCC_USER_VOLTAGE
VCC_USER_VOLTAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name VCC_USER_VOLTAGE <value>
© November 2008
Altera Corporation
8. EDA Netlist Writer Assignments
EDA_BOARD_BOUNDARY_SCAN_OPERATION
Type
Enumeration
■
POST_CONFIG
■
PRE_CONFIG
Device Support
Syntax
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION -section_id <section
identifier> <value>
Default Value
PRE_CONFIG, requires section identifier
© November 2008
Altera Corporation
8–2
EDA Netlist Writer Assignments
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL <value>
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL -entity <entity name>
<value>
Default Value
<None>
© November 2008
Altera Corporation
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
8–3
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL <value>
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL -entity <entity name>
<value>
Default Value
<None>
© November 2008
Altera Corporation
8–4
EDA_BOARD_DESIGN_SYMBOL_TOOL
EDA_BOARD_DESIGN_SYMBOL_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL <value>
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
EDA_BOARD_DESIGN_TIMING_TOOL
8–5
EDA_BOARD_DESIGN_TIMING_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL <value>
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
8–6
EDA_BOARD_DESIGN_TOOL
EDA_BOARD_DESIGN_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_TOOL <value>
set_global_assignment -name EDA_BOARD_DESIGN_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
8–7
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_DESIGN_EXTRA_ALTERA_SIM_LIB -section_id <section
identifier> <value>
© November 2008
Altera Corporation
8–8
EDA_DESIGN_INSTANCE_NAME
EDA_DESIGN_INSTANCE_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME -section_id <section identifier>
<value>
© November 2008
Altera Corporation
EDA_ENABLE_GLITCH_FILTERING
8–9
EDA_ENABLE_GLITCH_FILTERING
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -section_id <section identifier>
<value>
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -entity <entity name>
Default Value
© November 2008
Altera Corporation
8–10
EDA_FLATTEN_BUSES
EDA_FLATTEN_BUSES
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_FLATTEN_BUSES -section_id <section identifier> <value>
set_global_assignment -name EDA_FLATTEN_BUSES -entity <entity name> -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
8–11
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -section_id <section
identifier> <value>
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -entity <entity name>
Default Value
© November 2008
Altera Corporation
8–12
EDA_FORMAL_VERIFICATION_TOOL
EDA_FORMAL_VERIFICATION_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL <value>
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
EDA_FV_HIERARCHY
8–13
EDA_FV_HIERARCHY
Determines how the hierarchy of design entities is to be processed during compilation. 'BLACKBOX'
setting causes the entity to be handled as a black-box in the EDA flow. 'NONE' setting is the default and
means no special handling to be done. The option applies only to the design entity to which it is assigned;
lower-level entities do not inherit their parent entity's setting for this option.
Type
Enumeration
■
BLACKBOX
■
Off
Device Support
Syntax
set_global_assignment -name EDA_FV_HIERARCHY -entity <entity name> <value>
set_instance_assignment -name EDA_FV_HIERARCHY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
8–14
EDA_GENERATE_FUNCTIONAL_NETLIST
EDA_GENERATE_FUNCTIONAL_NETLIST
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -section_id <section
identifier> <value>
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -entity <entity name>
Default Value
© November 2008
Altera Corporation
EDA_GENERATE_POWER_INPUT_FILE
8–15
EDA_GENERATE_POWER_INPUT_FILE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -section_id <section
identifier> <value>
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -entity <entity name>
Default Value
© November 2008
Altera Corporation
8–16
EDA_GENERATE_TIMING_CLOSURE_DATA
EDA_GENERATE_TIMING_CLOSURE_DATA
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -section_id <section
identifier> <value>
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -entity <entity name>
Default Value
© November 2008
Altera Corporation
EDA_IBIS_MODEL_SELECTOR
8–17
EDA_IBIS_MODEL_SELECTOR
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -section_id <section identifier>
<value>
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
8–18
EDA_IBIS_MUTUAL_COUPLING
EDA_IBIS_MUTUAL_COUPLING
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -section_id <section identifier>
<value>
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
EDA_IPFS_FILE
8–19
EDA_IPFS_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_IPFS_FILE -section_id <section identifier> <value>
© November 2008
Altera Corporation
8–20
EDA_LAUNCH_CMD_LINE_TOOL
EDA_LAUNCH_CMD_LINE_TOOL
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -section_id <section identifier>
<value>
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
EDA_MAINTAIN_DESIGN_HIERARCHY
8–21
EDA_MAINTAIN_DESIGN_HIERARCHY
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -section_id <section
identifier> <value>
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -entity <entity name>
Default Value
© November 2008
Altera Corporation
8–22
EDA_MAP_ILLEGAL_CHARACTERS
EDA_MAP_ILLEGAL_CHARACTERS
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -section_id <section identifier>
<value>
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -entity <entity name> -section_id
Default Value
© November 2008
Altera Corporation
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
8–23
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
8–24
EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT -section_id <section
identifier> <value>
© November 2008
Altera Corporation
EDA_NATIVELINK_SIMULATION_TEST_BENCH
8–25
EDA_NATIVELINK_SIMULATION_TEST_BENCH
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH -section_id <section
identifier> <value>
© November 2008
Altera Corporation
8–26
EDA_NETLIST_WRITER_OUTPUT_DIR
EDA_NETLIST_WRITER_OUTPUT_DIR
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR -section_id <section
identifier> <value>
© November 2008
Altera Corporation
EDA_RESYNTHESIS_TOOL
8–27
EDA_RESYNTHESIS_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_RESYNTHESIS_TOOL <value>
set_global_assignment -name EDA_RESYNTHESIS_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
8–28
EDA_RTL_SIMULATION_RUN_SCRIPT
EDA_RTL_SIMULATION_RUN_SCRIPT
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -section_id <section
identifier> <value>
set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -entity <entity name>
© November 2008
Altera Corporation
EDA_RTL_SIM_MODE
8–29
EDA_RTL_SIM_MODE
Type
Enumeration
■
COMMAND_MACRO_MODE
■
NOT_USED
■
TEST_BENCH_MODE
Device Support
Syntax
set_global_assignment -name EDA_RTL_SIM_MODE -section_id <section identifier> <value>
set_global_assignment -name EDA_RTL_SIM_MODE -entity <entity name> -section_id <section
identifier> <value>
Default Value
NOT_USED, requires section identifier
© November 2008
Altera Corporation
8–30
EDA_RTL_TEST_BENCH_FILE_NAME
EDA_RTL_TEST_BENCH_FILE_NAME
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id <section
identifier> <value>
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity <entity name>
© November 2008
Altera Corporation
EDA_RTL_TEST_BENCH_NAME
8–31
EDA_RTL_TEST_BENCH_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -section_id <section identifier>
<value>
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -entity <entity name> -section_id
© November 2008
Altera Corporation
8–32
EDA_RTL_TEST_BENCH_RUN_FOR
EDA_RTL_TEST_BENCH_RUN_FOR
Type
Time
Device Support
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -section_id <section identifier>
<value>
set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -entity <entity name> -section_id
© November 2008
Altera Corporation
EDA_SDC_FILE_NAME
8–33
EDA_SDC_FILE_NAME
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_SDC_FILE_NAME -section_id <section identifier> <value>
set_global_assignment -name EDA_SDC_FILE_NAME -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
8–34
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLE
D
Type
Boolean
Device Support
Notes
Syntax
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
EDA_SIMULATION_RUN_SCRIPT
8–35
EDA_SIMULATION_RUN_SCRIPT
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -section_id <section identifier>
<value>
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -entity <entity name> -section_id
© November 2008
Altera Corporation
8–36
EDA_SIMULATION_TOOL
EDA_SIMULATION_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_SIMULATION_TOOL <value>
set_global_assignment -name EDA_SIMULATION_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
8–37
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
Type
Enumeration
■
All
■
All Except Combinational Logic Element Outputs
Device Support
■
Arria GX
■
Cyclone
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE -section_id
Default Value
All Except Combinational Logic Element Outputs, requires section identifier
© November 2008
Altera Corporation
8–38
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
8–39
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME -section_id
© November 2008
Altera Corporation
8–40
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -section_id <section
identifier> <value>
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -entity <entity name>
© November 2008
Altera Corporation
EDA_TEST_BENCH_ENABLE_STATUS
8–41
EDA_TEST_BENCH_ENABLE_STATUS
Type
Enumeration
■
COMMAND_MACRO_MODE
■
NOT_USED
■
TEST_BENCH_MODE
Device Support
Syntax
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -section_id <section
identifier> <value>
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -entity <entity name>
Default Value
NOT_USED, requires section identifier
© November 2008
Altera Corporation
8–42
EDA_TEST_BENCH_ENTITY_MODULE_NAME
EDA_TEST_BENCH_ENTITY_MODULE_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -section_id <section
identifier> <value>
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -entity <entity name>
© November 2008
Altera Corporation
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
8–43
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB -section_id <section
identifier> <value>
© November 2008
Altera Corporation
8–44
EDA_TEST_BENCH_FILE
EDA_TEST_BENCH_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_FILE -section_id <section identifier> <value>
© November 2008
Altera Corporation
EDA_TEST_BENCH_FILE_NAME
8–45
EDA_TEST_BENCH_FILE_NAME
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -section_id <section identifier>
<value>
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -entity <entity name> -section_id
© November 2008
Altera Corporation
8–46
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY -section_id
© November 2008
Altera Corporation
EDA_TEST_BENCH_MODULE_NAME
8–47
EDA_TEST_BENCH_MODULE_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME -section_id <section identifier>
<value>
© November 2008
Altera Corporation
8–48
EDA_TEST_BENCH_NAME
EDA_TEST_BENCH_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TEST_BENCH_NAME -section_id <section identifier> <value>
© November 2008
Altera Corporation
EDA_TEST_BENCH_RUN_FOR
8–49
EDA_TEST_BENCH_RUN_FOR
Type
Time
Device Support
Syntax
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -section_id <section identifier>
<value>
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -entity <entity name> -section_id
© November 2008
Altera Corporation
8–50
EDA_TEST_BENCH_RUN_SIM_FOR
EDA_TEST_BENCH_RUN_SIM_FOR
Type
Time
Device Support
Syntax
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR -section_id <section identifier>
<value>
© November 2008
Altera Corporation
EDA_TIME_SCALE
8–51
EDA_TIME_SCALE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TIME_SCALE -section_id <section identifier> <value>
set_global_assignment -name EDA_TIME_SCALE -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
8–52
EDA_TIMING_ANALYSIS_TOOL
EDA_TIMING_ANALYSIS_TOOL
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL <value>
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL -entity <entity name> <value>
Default Value
<None>
© November 2008
Altera Corporation
EDA_TRUNCATE_LONG_HIERARCHY_PATHS
8–53
EDA_TRUNCATE_LONG_HIERARCHY_PATHS
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -section_id <section
identifier> <value>
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -entity <entity name>
Default Value
© November 2008
Altera Corporation
8–54
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY -section_id
Default Value
<None>, requires section identifier
© November 2008
Altera Corporation
EDA_VHDL_ARCH_NAME
8–55
EDA_VHDL_ARCH_NAME
Type
String
Device Support
Notes
Syntax
set_global_assignment -name EDA_VHDL_ARCH_NAME -section_id <section identifier> <value>
Default Value
structure, requires section identifier
© November 2008
Altera Corporation
8–56
EDA_WAIT_FOR_GUI_TOOL_COMPLETION
EDA_WAIT_FOR_GUI_TOOL_COMPLETION
Type
Boolean
Device Support
Syntax
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
EDA_WRITER_DONT_WRITE_TOP_ENTITY
8–57
EDA_WRITER_DONT_WRITE_TOP_ENTITY
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY -section_id <section
identifier> <value>
Default Value
© November 2008
Altera Corporation
8–58
EDA_WRITE_DEVICE_CONTROL_PORTS
EDA_WRITE_DEVICE_CONTROL_PORTS
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -section_id <section
identifier> <value>
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -entity <entity name>
Default Value
© November 2008
Altera Corporation
EDA_WRITE_NODES_FOR_POWER_ESTIMATION
8–59
Type
Enumeration
■
ALL_NODES
■
NO_COMBINATIONAL_OUTPUT
■
Off
Device Support
Notes
Syntax
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -section_id <section
identifier> <value>
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -entity <entity name>
Default Value
OFF, requires section identifier
© November 2008
Altera Corporation
8–60
© November 2008
Altera Corporation
9. Assembler Assignments
APEX20K_CONFIGURATION_DEVICE
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
Notes
Syntax
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE <value>
Default Value
Auto
Old Names
CONFIGURATION_DEVICE
© November 2008
Altera Corporation
9–2
Assembler Assignments
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
Old Names
CONFIG_DEVICE_JTAG_USER_CODE
© November 2008
Altera Corporation
APEX20K_JTAG_USER_CODE
9–3
APEX20K_JTAG_USER_CODE
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_global_assignment -name APEX20K_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
Old Names
JTAG_USER_CODE
© November 2008
Altera Corporation
9–4
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
On
Old Names
AUTO_INCREMENT_USER_JTAG_CODE
© November 2008
Altera Corporation
AUTO_RESTART_CONFIGURATION
9–5
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
© November 2008
Altera Corporation
9–6
Syntax
set_global_assignment -name AUTO_RESTART_CONFIGURATION <value>
Default Value
On
Old Names
Auto restart on configuration error
© November 2008
Altera Corporation
CLOCK_SOURCE
9–7
CLOCK_SOURCE
Type
Enumeration
■
External
■
Internal
Device Support
Notes
Syntax
set_global_assignment -name CLOCK_SOURCE <value>
Default Value
Internal
© November 2008
Altera Corporation
9–8
COMPRESSION_MODE
COMPRESSION_MODE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name COMPRESSION_MODE <value>
Default Value
Off
© November 2008
Altera Corporation
CONFIGURATION_CLOCK_DIVISOR
9–9
CONFIGURATION_CLOCK_DIVISOR
Type
String
Device Support
Notes
Syntax
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR <value>
Default Value
1
© November 2008
Altera Corporation
9–10
CONFIGURATION_CLOCK_FREQUENCY
CONFIGURATION_CLOCK_FREQUENCY
Type
String
Device Support
Notes
Syntax
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY <value>
Default Value
10 MHz
© November 2008
Altera Corporation
CYCLONEIII_CONFIGURATION_DEVICE
9–11
CYCLONEIII_CONFIGURATION_DEVICE
Type
String
Device Support
■
Cyclone III
Notes
Syntax
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE <value>
Default Value
Auto
© November 2008
Altera Corporation
9–12
CYCLONEII_M4K_COMPATIBILITY
CYCLONEII_M4K_COMPATIBILITY
Type
Boolean
Device Support
■
Cyclone II
Notes
Syntax
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY <value>
Default Value
On
© November 2008
Altera Corporation
CYCLONE_CONFIGURATION_DEVICE
9–13
CYCLONE_CONFIGURATION_DEVICE
Type
String
Device Support
■
Cyclone
Notes
Syntax
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE <value>
Default Value
Auto
© November 2008
Altera Corporation
9–14
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
■
FLEX10KE
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE <value>
Default Value
Off
Old Names
DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
© November 2008
Altera Corporation
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
9–15
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
Type
Boolean
Device Support
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE <value>
Default Value
On
© November 2008
Altera Corporation
9–16
ENABLE_OCT_DONE
ENABLE_OCT_DONE
Type
Boolean
Device Support
■
Cyclone III
Notes
Syntax
set_global_assignment -name ENABLE_OCT_DONE <value>
Default Value
Off
© November 2008
Altera Corporation
EPROM_USE_CHECKSUM_AS_USERCODE
9–17
EPROM_USE_CHECKSUM_AS_USERCODE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE <value>
Default Value
Off
© November 2008
Altera Corporation
9–18
FLEX10K_CONFIGURATION_DEVICE
Type
String
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE <value>
Default Value
Auto
© November 2008
Altera Corporation
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
9–19
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
Type
String
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
© November 2008
Altera Corporation
9–20
FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
Type
Boolean
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Notes
Syntax
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE <value>
Default Value
On
© November 2008
Altera Corporation
FLEX10K_JTAG_USER_CODE
9–21
FLEX10K_JTAG_USER_CODE
Type
String
Device Support
■
ACEX1K
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
Syntax
set_global_assignment -name FLEX10K_JTAG_USER_CODE <value>
Default Value
7F
© November 2008
Altera Corporation
9–22
Type
String
Device Support
■
FLEX6000
Notes
Syntax
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE <value>
Default Value
Auto
Old Names
CONFIGURATION_DEVICE_FLEX6K
© November 2008
Altera Corporation
9–23
Type
Boolean
Device Support
■
FLEX6000
Notes
Syntax
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE <value>
Default Value
Off
© November 2008
Altera Corporation
9–24
GENERATE_HEX_FILE
GENERATE_HEX_FILE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name GENERATE_HEX_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
GENERATE_RBF_FILE
9–25
GENERATE_RBF_FILE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name GENERATE_RBF_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
9–26
GENERATE_TTF_FILE
GENERATE_TTF_FILE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name GENERATE_TTF_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
HARDCOPYII_POWER_ON_EXTRA_DELAY
9–27
HARDCOPYII_POWER_ON_EXTRA_DELAY
Type
Enumeration
■
Off
■
Wait 1 ms
■
Wait 2 ms
■
Wait 4 ms
■
Wait 50 ms
■
Wait 8 ms
Device Support
■
HardCopy II
Notes
Syntax
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY <value>
Default Value
Off
© November 2008
Altera Corporation
9–28
HEXOUT_FILE_COUNT_DIRECTION
HEXOUT_FILE_COUNT_DIRECTION
Type
Enumeration
■
Down
■
Up
Device Support
Notes
Syntax
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION <value>
Default Value
Up
Old Names
HEX_FILE_COUNT_UP_DOWN
© November 2008
Altera Corporation
HEXOUT_FILE_START_ADDRESS
9–29
HEXOUT_FILE_START_ADDRESS
Type
String
Device Support
Notes
Syntax
set_global_assignment -name HEXOUT_FILE_START_ADDRESS <value>
Default Value
0
© November 2008
Altera Corporation
9–30
MAX7000S_JTAG_USER_CODE
MAX7000S_JTAG_USER_CODE
Type
String
Device Support
■
MAX7000A
■
MAX7000S
Syntax
set_global_assignment -name MAX7000S_JTAG_USER_CODE <value>
Default Value
FFFF
© November 2008
Altera Corporation
MAX7000_JTAG_USER_CODE
9–31
MAX7000_JTAG_USER_CODE
Type
String
Device Support
■
MAX3000A
■
MAX7000AE
■
MAX7000B
Syntax
set_global_assignment -name MAX7000_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
© November 2008
Altera Corporation
9–32
MAX7000_USE_CHECKSUM_AS_USERCODE
MAX7000_USE_CHECKSUM_AS_USERCODE
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE <value>
Default Value
Off
© November 2008
Altera Corporation
MERCURY_CONFIGURATION_DEVICE
9–33
MERCURY_CONFIGURATION_DEVICE
Type
String
Device Support
■
Mercury
Notes
Syntax
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE <value>
Default Value
Auto
Old Names
CONFIGURATION_DEVICE_DALI
© November 2008
Altera Corporation
9–34
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
Type
String
Device Support
■
Mercury
Syntax
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
Old Names
CONFIG_DEVICE_JTAG_USER_CODE_DALI
© November 2008
Altera Corporation
MERCURY_JTAG_USER_CODE
9–35
MERCURY_JTAG_USER_CODE
Type
String
Device Support
■
Mercury
Syntax
set_global_assignment -name MERCURY_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
Old Names
JTAG_USER_CODE_DALI
© November 2008
Altera Corporation
9–36
ON_CHIP_BITSTREAM_DECOMPRESSION
ON_CHIP_BITSTREAM_DECOMPRESSION
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION <value>
Default Value
On
© November 2008
Altera Corporation
RELEASE_CLEARS_BEFORE_TRI_STATES
9–37
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
FLEX6000
■
HardCopy II
■
HardCopy III
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES <value>
© November 2008
Altera Corporation
9–38
Default Value
Off
Old Names
Release clears before tri-states
© November 2008
Altera Corporation
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
9–39
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
Type
Enumeration
■
As input tri-stated
■
Device Support
■
MAX3000A
■
MAX7000A
■
MAX7000S
Syntax
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND <value>
Default Value
Old Names
RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
© November 2008
Altera Corporation
9–40
SECURITY_BIT
SECURITY_BIT
Type
Boolean
Device Support
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
Notes
Syntax
set_global_assignment -name SECURITY_BIT <value>
Default Value
Off
© November 2008
Altera Corporation
STRATIXII_CONFIGURATION_DEVICE
9–41
STRATIXII_CONFIGURATION_DEVICE
Type
String
Device Support
■
Arria GX
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE <value>
Default Value
Auto
Old Names
STRATIX_II_CONFIGURATION_DEVICE
© November 2008
Altera Corporation
9–42
STRATIXII_MRAM_COMPATIBILITY
STRATIXII_MRAM_COMPATIBILITY
Type
Boolean
Device Support
■
Stratix II
Notes
Syntax
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY <value>
Default Value
Off
Old Names
STRATIXII_SILICON_VERSION
© November 2008
Altera Corporation
STRATIX_CONFIGURATION_DEVICE
9–43
STRATIX_CONFIGURATION_DEVICE
Type
String
Device Support
■
Cyclone II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
Notes
Syntax
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE <value>
Default Value
Auto
Old Names
YEAGER_CONFIGURATION_DEVICE
© November 2008
Altera Corporation
9–44
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
© November 2008
Altera Corporation
STRATIX_JTAG_USER_CODE
9–45
STRATIX_JTAG_USER_CODE
Type
String
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name STRATIX_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
© November 2008
Altera Corporation
9–46
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
Type
Boolean
Device Support
■
Stratix
■
Stratix II
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT <value>
Default Value
Off
© November 2008
Altera Corporation
USE_CHECKSUM_AS_USERCODE
9–47
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name USE_CHECKSUM_AS_USERCODE <value>
© November 2008
Altera Corporation
9–48
Default Value
Off
© November 2008
Altera Corporation
USE_CONFIGURATION_DEVICE
9–49
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
MAX9000
■
Mercury
■
Stratix
© November 2008
Altera Corporation
9–50
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name USE_CONFIGURATION_DEVICE <value>
© November 2008
Altera Corporation
10. Simulator Assignments
ACTION
Type
Enumeration
■
Give Error
■
Give Info
■
Give Warning
■
Stop
Device Support
Syntax
set_global_assignment -name ACTION -section_id <section identifier> <value>
© November 2008
Altera Corporation
10–2
Simulator Assignments
ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
Type
Boolean
Device Support
Syntax
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS <value>
Default Value
On
© November 2008
Altera Corporation
ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
10–3
ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
Adds the signal to the list of signals for which output waveforms are shown in the simulation report. This
option makes a node observable during simulation.
Type
Boolean
Device Support
Syntax
set_instance_assignment -name ADD_TO_SIMULATION_OUTPUT_WAVEFORMS -to <to> -entity
© November 2008
Altera Corporation
10–4
ALIAS
ALIAS
Specifies an alias for the full hierarchical name of the node.
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name ALIAS -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
AUTO_USE_SIMULATION_PDB_NETLIST
10–5
AUTO_USE_SIMULATION_PDB_NETLIST
Type
Boolean
Device Support
Notes
This assignment is included in the Simulator report.
Syntax
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST <value>
Default Value
Off
© November 2008
Altera Corporation
10–6
BREAKPOINT_STATE
BREAKPOINT_STATE
Type
Enumeration
■
Disabled
■
Enabled
Device Support
Syntax
set_global_assignment -name BREAKPOINT_STATE -section_id <section identifier> <value>
© November 2008
Altera Corporation
CHECK_OUTPUTS
10–7
CHECK_OUTPUTS
Type
Boolean
Device Support
Syntax
set_global_assignment -name CHECK_OUTPUTS <value>
Default Value
Off
© November 2008
Altera Corporation
10–8
END_TIME
END_TIME
Type
Time
Device Support
Syntax
set_global_assignment -name END_TIME <value>
© November 2008
Altera Corporation
EXTERNAL_PIN_CONNECTION
10–9
EXTERNAL_PIN_CONNECTION
Specifies an external pin connection between an output pin and an input pin. This option is used during
simulations only.
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name EXTERNAL_PIN_CONNECTION -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
10–10
GLITCH_DETECTION
GLITCH_DETECTION
Type
Boolean
Device Support
Syntax
set_global_assignment -name GLITCH_DETECTION <value>
Default Value
Off
© November 2008
Altera Corporation
GLITCH_INTERVAL
10–11
GLITCH_INTERVAL
Type
Time
Device Support
Syntax
set_global_assignment -name GLITCH_INTERVAL <value>
Default Value
1ns
© November 2008
Altera Corporation
10–12
IMMEDIATE_ASSERTION_FAIL_ACTION
IMMEDIATE_ASSERTION_FAIL_ACTION
Type
Enumeration
■
Give Error
■
Give Info
■
Give Warning
■
Stop
Device Support
Syntax
set_global_assignment -name IMMEDIATE_ASSERTION_FAIL_ACTION -section_id <section
identifier> <value>
© November 2008
Altera Corporation
IMMEDIATE_ASSERTION_FAIL_MESSAGE
10–13
IMMEDIATE_ASSERTION_FAIL_MESSAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name IMMEDIATE_ASSERTION_FAIL_MESSAGE -section_id <section
identifier> <value>
© November 2008
Altera Corporation
10–14
IMMEDIATE_ASSERTION_PASS_MESSAGE
IMMEDIATE_ASSERTION_PASS_MESSAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name IMMEDIATE_ASSERTION_PASS_MESSAGE -section_id <section
identifier> <value>
© November 2008
Altera Corporation
IMMEDIATE_ASSERTION_STATE
10–15
IMMEDIATE_ASSERTION_STATE
Type
Enumeration
■
Disabled
■
Enabled
Device Support
Syntax
set_global_assignment -name IMMEDIATE_ASSERTION_STATE -section_id <section identifier>
<value>
© November 2008
Altera Corporation
10–16
IMMEDIATE_ASSERTION_TEST_CONDITION
IMMEDIATE_ASSERTION_TEST_CONDITION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name IMMEDIATE_ASSERTION_TEST_CONDITION -section_id <section
identifier> <value>
© November 2008
Altera Corporation
INCREMENTAL_VECTOR_INPUT_SOURCE
10–17
INCREMENTAL_VECTOR_INPUT_SOURCE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE <value>
© November 2008
Altera Corporation
10–18
PASSIVE_RESISTOR
PASSIVE_RESISTOR
Specifies whether an output or bidirectional pin has a pull-up or pull-down resistor. This option is used in
functional simulations only.
Type
Enumeration
■
Pull-down
■
Pull-up
Device Support
Syntax
set_instance_assignment -name PASSIVE_RESISTOR -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
SETUP_HOLD_DETECTION
10–19
SETUP_HOLD_DETECTION
Type
Boolean
Device Support
Syntax
set_global_assignment -name SETUP_HOLD_DETECTION <value>
Default Value
Off
© November 2008
Altera Corporation
10–20
SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
Type
Boolean
Device Support
Syntax
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
<value>
Default Value
Off
© November 2008
Altera Corporation
SETUP_HOLD_TIME_VIOLATION_DETECTION
10–21
SETUP_HOLD_TIME_VIOLATION_DETECTION
Enables setup and hold time violation detection during simulation.
Type
Boolean
Device Support
Syntax
set_instance_assignment -name SETUP_HOLD_TIME_VIOLATION_DETECTION -to <to> -entity
© November 2008
Altera Corporation
10–22
SIMULATION_BUS_CHANNEL_GROUPING
SIMULATION_BUS_CHANNEL_GROUPING
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING <value>
Default Value
Off
© November 2008
Altera Corporation
SIMULATION_CELL_DELAY_MODEL_TYPE
10–23
SIMULATION_CELL_DELAY_MODEL_TYPE
Type
Enumeration
■
Inertial
■
Transport
Device Support
■
Cyclone III
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE <value>
Default Value
TRANSPORT
© November 2008
Altera Corporation
10–24
SIMULATION_COMPARE_SIGNAL
SIMULATION_COMPARE_SIGNAL
Type
Boolean
Device Support
Syntax
set_instance_assignment -name SIMULATION_COMPARE_SIGNAL -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
10–25
SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL <value>
Default Value
On
© November 2008
Altera Corporation
10–26
SIMULATION_COVERAGE
SIMULATION_COVERAGE
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_COVERAGE <value>
Default Value
On
© November 2008
Altera Corporation
SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
10–27
SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
Type
Time
Device Support
Syntax
set_global_assignment -name SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE <value>
© November 2008
Altera Corporation
10–28
SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
Type
Enumeration
■
Inertial
■
Transport
Device Support
■
Cyclone III
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE <value>
Default Value
TRANSPORT
© November 2008
Altera Corporation
SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
10–29
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL <value>
Default Value
On
© November 2008
Altera Corporation
10–30
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL <value>
Default Value
On
© November 2008
Altera Corporation
SIMULATION_MODE
10–31
SIMULATION_MODE
Type
Enumeration
■
Functional
■
Timing
■
Timing using Fast Timing Model
Device Support
Syntax
set_global_assignment -name SIMULATION_MODE <value>
Default Value
TIMING
© November 2008
Altera Corporation
10–32
SIMULATION_NETLIST_VIEWER
SIMULATION_NETLIST_VIEWER
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_NETLIST_VIEWER <value>
Default Value
Off
© November 2008
Altera Corporation
SIMULATION_SIGNAL_COMPARE_TOLERANCE
10–33
SIMULATION_SIGNAL_COMPARE_TOLERANCE
Type
Time
Device Support
Syntax
set_instance_assignment -name SIMULATION_SIGNAL_COMPARE_TOLERANCE -to <to> -entity
© November 2008
Altera Corporation
10–34
SIMULATION_VDB_RESULT_FLUSH
SIMULATION_VDB_RESULT_FLUSH
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH <value>
Default Value
On
© November 2008
Altera Corporation
SIMULATION_VECTOR_COMPARE_BEGIN_TIME
10–35
SIMULATION_VECTOR_COMPARE_BEGIN_TIME
Type
Time
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_BEGIN_TIME <value>
© November 2008
Altera Corporation
10–36
SIMULATION_VECTOR_COMPARE_END_TIME
SIMULATION_VECTOR_COMPARE_END_TIME
Type
Time
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_END_TIME <value>
© November 2008
Altera Corporation
SIMULATION_VECTOR_COMPARE_RULE_FOR_0
10–37
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_0 <value>
© November 2008
Altera Corporation
10–38
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_1 <value>
© November 2008
Altera Corporation
SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
10–39
SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_DC <value>
© November 2008
Altera Corporation
10–40
SIMULATION_VECTOR_COMPARE_RULE_FOR_H
SIMULATION_VECTOR_COMPARE_RULE_FOR_H
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_H <value>
© November 2008
Altera Corporation
SIMULATION_VECTOR_COMPARE_RULE_FOR_L
10–41
SIMULATION_VECTOR_COMPARE_RULE_FOR_L
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_L <value>
© November 2008
Altera Corporation
10–42
SIMULATION_VECTOR_COMPARE_RULE_FOR_U
SIMULATION_VECTOR_COMPARE_RULE_FOR_U
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_U <value>
© November 2008
Altera Corporation
SIMULATION_VECTOR_COMPARE_RULE_FOR_W
10–43
SIMULATION_VECTOR_COMPARE_RULE_FOR_W
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_W <value>
© November 2008
Altera Corporation
10–44
SIMULATION_VECTOR_COMPARE_RULE_FOR_X
SIMULATION_VECTOR_COMPARE_RULE_FOR_X
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_X <value>
© November 2008
Altera Corporation
SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
10–45
SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
Type
String
Device Support
Syntax
set_global_assignment -name SIMULATION_VECTOR_COMPARE_RULE_FOR_Z <value>
© November 2008
Altera Corporation
10–46
SIMULATION_WITH_AUTO_GLITCH_FILTERING
SIMULATION_WITH_AUTO_GLITCH_FILTERING
Type
Enumeration
■
Always
■
Auto
■
Never
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING <value>
Default Value
AUTO
© November 2008
Altera Corporation
SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
10–47
SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW <value>
© November 2008
Altera Corporation
10–48
SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
<value>
Default Value
On
Old Names
SIMULATION_WITH_GLITCH_FILTERING
© November 2008
Altera Corporation
SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
10–49
SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
10–50
SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
10–51
SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_POWERPLAY_VCD_FILE_END_TIME <value>
© November 2008
Altera Corporation
10–52
SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION <value>
© November 2008
Altera Corporation
SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
10–53
SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_POWERPLAY_VCD_FILE_START_TIME <value>
© November 2008
Altera Corporation
10–54
SIMULATOR_PVT_TIMING_MODEL_TYPE
SIMULATOR_PVT_TIMING_MODEL_TYPE
Type
Enumeration
■
Auto
■
Model_1
■
Model_2
■
Model_3
Device Support
■
Cyclone III
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE <value>
Default Value
AUTO
© November 2008
Altera Corporation
SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
10–55
SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME <value>
© November 2008
Altera Corporation
10–56
SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION <value>
© November 2008
Altera Corporation
SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
10–57
SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
Type
Time
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
MAX II
■
MAX3000A
■
MAX7000AE
■
MAX7000B
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME <value>
© November 2008
Altera Corporation
10–58
SIM_BEHAVIOR_SIMULATION
SIM_BEHAVIOR_SIMULATION
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIM_BEHAVIOR_SIMULATION <value>
© November 2008
Altera Corporation
SIM_COMPILE_HDL_FILES
10–59
SIM_COMPILE_HDL_FILES
Type
String
Device Support
Syntax
set_global_assignment -name SIM_COMPILE_HDL_FILES <value>
© November 2008
Altera Corporation
10–60
SIM_HDL_TOP_MODULE_NAME
SIM_HDL_TOP_MODULE_NAME
Type
String
Device Support
Syntax
set_global_assignment -name SIM_HDL_TOP_MODULE_NAME <value>
© November 2008
Altera Corporation
SIM_OVERWRITE_WAVEFORM_INPUTS
10–61
SIM_OVERWRITE_WAVEFORM_INPUTS
Type
Boolean
Device Support
Syntax
set_global_assignment -name SIM_OVERWRITE_WAVEFORM_INPUTS <value>
© November 2008
Altera Corporation
10–62
SIM_TAP_REGISTER_D_Q_PORTS
SIM_TAP_REGISTER_D_Q_PORTS
Adds the D and Q ports of a register node to the list of signals for which output waveforms are shown in
the simulation report. This option makes the D and Q ports of a register node observable during
Functional Simulation.
Type
Boolean
Device Support
Syntax
set_instance_assignment -name SIM_TAP_REGISTER_D_Q_PORTS -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
10–63
SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
Type
Integer
Device Support
Syntax
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE -section_id <section
identifier> <value>
Default Value
50, requires section identifier
© November 2008
Altera Corporation
10–64
SIM_VECTOR_COMPARED_CLOCK_OFFSET
SIM_VECTOR_COMPARED_CLOCK_OFFSET
Type
Time
Device Support
Syntax
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET -section_id <section
identifier> <value>
Default Value
0ns, requires section identifier
© November 2008
Altera Corporation
SIM_VECTOR_COMPARED_CLOCK_PERIOD
10–65
SIM_VECTOR_COMPARED_CLOCK_PERIOD
Type
Time
Device Support
Syntax
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_PERIOD -section_id <section
identifier> <value>
© November 2008
Altera Corporation
10–66
START_TIME
START_TIME
Type
Time
Device Support
Syntax
set_global_assignment -name START_TIME <value>
Default Value
0ns
© November 2008
Altera Corporation
TRIGGER_EQUATION
10–67
TRIGGER_EQUATION
Type
String
Device Support
Notes
Syntax
set_global_assignment -name TRIGGER_EQUATION -section_id <section identifier> <value>
© November 2008
Altera Corporation
10–68
TRIGGER_VECTOR_COMPARE_ON_SIGNAL
TRIGGER_VECTOR_COMPARE_ON_SIGNAL
Type
Boolean
Device Support
Syntax
set_instance_assignment -name TRIGGER_VECTOR_COMPARE_ON_SIGNAL -to <to> -entity <entity
name> <value>
© November 2008
Altera Corporation
USER_MESSAGE
10–69
USER_MESSAGE
Type
String
Device Support
Notes
Syntax
set_global_assignment -name USER_MESSAGE -section_id <section identifier> <value>
© November 2008
Altera Corporation
10–70
VECTOR_COMPARE_TRIGGER_MODE
VECTOR_COMPARE_TRIGGER_MODE
Type
Enumeration
■
ALL_EDGE
■
INPUT_EDGE
■
SELECTED_EDGE
Device Support
Syntax
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE <value>
Default Value
INPUT_EDGE
© November 2008
Altera Corporation
VECTOR_INPUT_SOURCE
10–71
VECTOR_INPUT_SOURCE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name VECTOR_INPUT_SOURCE <value>
© November 2008
Altera Corporation
10–72
VECTOR_OUTPUT_DESTINATION
VECTOR_OUTPUT_DESTINATION
Type
File name
Device Support
Notes
This assignment is included in the Simulator report.
Syntax
set_global_assignment -name VECTOR_OUTPUT_DESTINATION <value>
© November 2008
Altera Corporation
VECTOR_OUTPUT_FORMAT
10–73
VECTOR_OUTPUT_FORMAT
Type
Enumeration
■
CVWF
■
VCD
■
VWF
Device Support
Syntax
set_global_assignment -name VECTOR_OUTPUT_FORMAT <value>
© November 2008
Altera Corporation
10–74
X_ON_VIOLATION_OPTION
X_ON_VIOLATION_OPTION
Gives user the option to see 'X' or valid data at the output of registers in the event of a timing violation
during simulation..
Type
Boolean
Device Support
Syntax
set_instance_assignment -name X_ON_VIOLATION_OPTION -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
11. Design Assistant Assignments
ACLK_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name ACLK_CAT <value>
© November 2008
Altera Corporation
11–2
Design Assistant Assignments
ACLK_RULE_IMSZER_ADOMAIN
ACLK_RULE_IMSZER_ADOMAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN <value>
© November 2008
Altera Corporation
ACLK_RULE_NO_SZER_ACLK_DOMAIN
11–3
ACLK_RULE_NO_SZER_ACLK_DOMAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN <value>
© November 2008
Altera Corporation
11–4
ACLK_RULE_SZER_BTW_ACLK_DOMAIN
ACLK_RULE_SZER_BTW_ACLK_DOMAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN <value>
© November 2008
Altera Corporation
CLK_CAT
11–5
CLK_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_CAT <value>
© November 2008
Altera Corporation
11–6
CLK_RULE_CLKNET_CLKSPINES
CLK_RULE_CLKNET_CLKSPINES
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES <value>
© November 2008
Altera Corporation
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
11–7
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
Type
Integer
Device Support
Syntax
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD <value>
Default Value
25
© November 2008
Altera Corporation
11–8
CLK_RULE_COMB_CLOCK
CLK_RULE_COMB_CLOCK
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_COMB_CLOCK <value>
© November 2008
Altera Corporation
CLK_RULE_GATED_CLK_FANOUT
11–9
CLK_RULE_GATED_CLK_FANOUT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_GATED_CLK_FANOUT <value>
© November 2008
Altera Corporation
11–10
CLK_RULE_GATING_SCHEME
CLK_RULE_GATING_SCHEME
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_GATING_SCHEME <value>
© November 2008
Altera Corporation
CLK_RULE_INPINS_CLKNET
11–11
CLK_RULE_INPINS_CLKNET
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_INPINS_CLKNET <value>
© November 2008
Altera Corporation
11–12
CLK_RULE_INV_CLOCK
CLK_RULE_INV_CLOCK
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_INV_CLOCK <value>
© November 2008
Altera Corporation
CLK_RULE_MIX_EDGES
11–13
CLK_RULE_MIX_EDGES
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name CLK_RULE_MIX_EDGES <value>
© November 2008
Altera Corporation
11–14
DA_CUSTOM_RULE_FILE
DA_CUSTOM_RULE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name DA_CUSTOM_RULE_FILE <value>
© November 2008
Altera Corporation
DISABLE_DA_RULE
11–15
DISABLE_DA_RULE
Suppress design assistant rule locally or turn off design assistant rule globally for general user
Type
String
Device Support
Syntax
set_global_assignment -name DISABLE_DA_RULE <value>
set_instance_assignment -name DISABLE_DA_RULE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
11–16
DRC_DEADLOCK_STATE_LIMIT
DRC_DEADLOCK_STATE_LIMIT
Type
Integer
Device Support
Syntax
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT <value>
Default Value
2
© November 2008
Altera Corporation
DRC_DETAIL_MESSAGE_LIMIT
11–17
DRC_DETAIL_MESSAGE_LIMIT
Type
Integer
Device Support
Syntax
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT <value>
Default Value
10
© November 2008
Altera Corporation
11–18
DRC_FANOUT_EXCEEDING
DRC_FANOUT_EXCEEDING
Type
Integer
Device Support
Syntax
set_global_assignment -name DRC_FANOUT_EXCEEDING <value>
Default Value
30
© November 2008
Altera Corporation
DRC_GATED_CLOCK_FEED
11–19
DRC_GATED_CLOCK_FEED
Type
Integer
Device Support
Syntax
set_global_assignment -name DRC_GATED_CLOCK_FEED <value>
Default Value
30
© November 2008
Altera Corporation
11–20
DRC_REPORT_FANOUT_EXCEEDING
DRC_REPORT_FANOUT_EXCEEDING
Type
Boolean
Device Support
Syntax
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING <value>
© November 2008
Altera Corporation
DRC_REPORT_TOP_FANOUT
11–21
DRC_REPORT_TOP_FANOUT
Type
Boolean
Device Support
Syntax
set_global_assignment -name DRC_REPORT_TOP_FANOUT <value>
© November 2008
Altera Corporation
11–22
DRC_TOP_FANOUT
DRC_TOP_FANOUT
Type
Integer
Device Support
Syntax
set_global_assignment -name DRC_TOP_FANOUT <value>
Default Value
50
© November 2008
Altera Corporation
DRC_VIOLATION_MESSAGE_LIMIT
11–23
DRC_VIOLATION_MESSAGE_LIMIT
Type
Integer
Device Support
Syntax
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT <value>
Default Value
30
© November 2008
Altera Corporation
11–24
ENABLE_DA_RULE
ENABLE_DA_RULE
Desuppress design assistant rule locally or turn on design assistant rule globally for general user
Type
String
Device Support
Syntax
set_global_assignment -name ENABLE_DA_RULE <value>
set_instance_assignment -name ENABLE_DA_RULE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
ENABLE_DRC_SETTINGS
11–25
ENABLE_DRC_SETTINGS
Type
Boolean
Device Support
Syntax
set_global_assignment -name ENABLE_DRC_SETTINGS <value>
Default Value
Off
© November 2008
Altera Corporation
11–26
FSM_CAT
FSM_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name FSM_CAT <value>
© November 2008
Altera Corporation
FSM_RULE_DEADLOCK_STATE
11–27
FSM_RULE_DEADLOCK_STATE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name FSM_RULE_DEADLOCK_STATE <value>
© November 2008
Altera Corporation
11–28
FSM_RULE_NO_RESET_STATE
FSM_RULE_NO_RESET_STATE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name FSM_RULE_NO_RESET_STATE <value>
© November 2008
Altera Corporation
FSM_RULE_NO_SZER_ACLK_DOMAIN
11–29
FSM_RULE_NO_SZER_ACLK_DOMAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name FSM_RULE_NO_SZER_ACLK_DOMAIN <value>
© November 2008
Altera Corporation
11–30
FSM_RULE_UNREACHABLE_STATE
FSM_RULE_UNREACHABLE_STATE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name FSM_RULE_UNREACHABLE_STATE <value>
© November 2008
Altera Corporation
FSM_RULE_UNUSED_TRANSITION
11–31
FSM_RULE_UNUSED_TRANSITION
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name FSM_RULE_UNUSED_TRANSITION <value>
© November 2008
Altera Corporation
11–32
HARDCOPY_FLOW_AUTOMATION
HARDCOPY_FLOW_AUTOMATION
Type
Enumeration
■
COMPILE_NEW_PROJECT
■
FULL_COMPILATION
■
MIGRATION_ONLY
Device Support
Syntax
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION <value>
Default Value
MIGRATION_ONLY
© November 2008
Altera Corporation
HARDCOPY_NEW_PROJECT_PATH
11–33
HARDCOPY_NEW_PROJECT_PATH
Type
String
Device Support
Notes
Syntax
set_global_assignment -name HARDCOPY_NEW_PROJECT_PATH <value>
© November 2008
Altera Corporation
11–34
HCPY_CAT
HCPY_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name HCPY_CAT <value>
© November 2008
Altera Corporation
HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
11–35
HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
Type
Boolean
Device Support
■
Cyclone
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES <value>
© November 2008
Altera Corporation
11–36
HCPY_VREF_PINS
HCPY_VREF_PINS
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name HCPY_VREF_PINS <value>
© November 2008
Altera Corporation
NONSYNCHSTRUCT_CAT
11–37
NONSYNCHSTRUCT_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_CAT <value>
© November 2008
Altera Corporation
11–38
NONSYNCHSTRUCT_RULE_ASYN_RAM
NONSYNCHSTRUCT_RULE_ASYN_RAM
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM <value>
© November 2008
Altera Corporation
NONSYNCHSTRUCT_RULE_COMBLOOP
11–39
NONSYNCHSTRUCT_RULE_COMBLOOP
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP <value>
© November 2008
Altera Corporation
11–40
NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE <value>
© November 2008
Altera Corporation
NONSYNCHSTRUCT_RULE_DELAY_CHAIN
11–41
NONSYNCHSTRUCT_RULE_DELAY_CHAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN <value>
© November 2008
Altera Corporation
11–42
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN <value>
© November 2008
Altera Corporation
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
11–43
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED <value>
© November 2008
Altera Corporation
11–44
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR <value>
© November 2008
Altera Corporation
NONSYNCHSTRUCT_RULE_REG_LOOP
11–45
NONSYNCHSTRUCT_RULE_REG_LOOP
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP <value>
© November 2008
Altera Corporation
11–46
NONSYNCHSTRUCT_RULE_RIPPLE_CLK
NONSYNCHSTRUCT_RULE_RIPPLE_CLK
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK <value>
© November 2008
Altera Corporation
NONSYNCHSTRUCT_RULE_SRLATCH
11–47
NONSYNCHSTRUCT_RULE_SRLATCH
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH <value>
© November 2008
Altera Corporation
11–48
RESET_CAT
RESET_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name RESET_CAT <value>
© November 2008
Altera Corporation
RESET_RULE_COMB_ASYNCH_RESET
11–49
RESET_RULE_COMB_ASYNCH_RESET
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET <value>
© November 2008
Altera Corporation
11–50
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN <value>
© November 2008
Altera Corporation
RESET_RULE_IMSYNCH_EXRESET
11–51
RESET_RULE_IMSYNCH_EXRESET
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET <value>
© November 2008
Altera Corporation
11–52
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN <value>
© November 2008
Altera Corporation
RESET_RULE_UNSYNCH_EXRESET
11–53
RESET_RULE_UNSYNCH_EXRESET
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET <value>
© November 2008
Altera Corporation
11–54
SIGNALRACE_CAT
SIGNALRACE_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name SIGNALRACE_CAT <value>
© November 2008
Altera Corporation
SIGNALRACE_RULE_CLK_PORT_RACE
11–55
SIGNALRACE_RULE_CLK_PORT_RACE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name SIGNALRACE_RULE_CLK_PORT_RACE <value>
© November 2008
Altera Corporation
11–56
SIGNALRACE_RULE_RESET_RACE
SIGNALRACE_RULE_RESET_RACE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name SIGNALRACE_RULE_RESET_RACE <value>
© November 2008
Altera Corporation
SIGNALRACE_RULE_SECOND_SIGNAL_RACE
11–57
SIGNALRACE_RULE_SECOND_SIGNAL_RACE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name SIGNALRACE_RULE_SECOND_SIGNAL_RACE <value>
© November 2008
Altera Corporation
11–58
SIGNALRACE_RULE_TRISTATE
SIGNALRACE_RULE_TRISTATE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name SIGNALRACE_RULE_TRISTATE <value>
© November 2008
Altera Corporation
TIMING_CAT
11–59
TIMING_CAT
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
FLEX10KE
■
FLEX6000
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
Syntax
set_global_assignment -name TIMING_CAT <value>
© November 2008
Altera Corporation
11–60
TIMING_CAT
© November 2008
Altera Corporation
12. Programmer Assignments
EXCALIBUR_HEX_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name EXCALIBUR_HEX_FILE <value>
© November 2008
Altera Corporation
12–2
Programmer Assignments
GENERATE_CONFIG_HEXOUT_FILE
GENERATE_CONFIG_HEXOUT_FILE
Type
Boolean
Device Support
■
Enhanced Configuration Devices
Notes
Syntax
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
GENERATE_CONFIG_ISC_FILE
12–3
GENERATE_CONFIG_ISC_FILE
Type
Boolean
Device Support
■
Notes
Syntax
set_global_assignment -name GENERATE_CONFIG_ISC_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
12–4
GENERATE_CONFIG_JAM_FILE
GENERATE_CONFIG_JAM_FILE
Type
Boolean
Device Support
■
EPC2
■
Notes
Syntax
set_global_assignment -name GENERATE_CONFIG_JAM_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
GENERATE_CONFIG_JBC_FILE
12–5
GENERATE_CONFIG_JBC_FILE
Type
Boolean
Device Support
■
EPC2
■
Notes
Syntax
set_global_assignment -name GENERATE_CONFIG_JBC_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
12–6
GENERATE_CONFIG_JBC_FILE_COMPRESSED
GENERATE_CONFIG_JBC_FILE_COMPRESSED
Type
Boolean
Device Support
■
EPC2
■
Notes
Syntax
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED <value>
Default Value
On
© November 2008
Altera Corporation
GENERATE_CONFIG_SVF_FILE
12–7
GENERATE_CONFIG_SVF_FILE
Type
Boolean
Device Support
■
EPC2
■
Notes
Syntax
set_global_assignment -name GENERATE_CONFIG_SVF_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
12–8
GENERATE_ISC_FILE
GENERATE_ISC_FILE
Type
Boolean
Device Support
■
MAX3000A
■
MAX7000AE
■
MAX7000B
Notes
Syntax
set_global_assignment -name GENERATE_ISC_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
GENERATE_JAM_FILE
12–9
GENERATE_JAM_FILE
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
Notes
Syntax
set_global_assignment -name GENERATE_JAM_FILE <value>
© November 2008
Altera Corporation
12–10
GENERATE_JAM_FILE
Default Value
Off
© November 2008
Altera Corporation
GENERATE_JBC_FILE
12–11
GENERATE_JBC_FILE
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
Notes
Syntax
set_global_assignment -name GENERATE_JBC_FILE <value>
© November 2008
Altera Corporation
12–12
GENERATE_JBC_FILE
Default Value
Off
© November 2008
Altera Corporation
GENERATE_JBC_FILE_COMPRESSED
12–13
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
Notes
Syntax
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED <value>
© November 2008
Altera Corporation
12–14
Default Value
On
© November 2008
Altera Corporation
GENERATE_SVF_FILE
12–15
GENERATE_SVF_FILE
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KE
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
Notes
Syntax
set_global_assignment -name GENERATE_SVF_FILE <value>
© November 2008
Altera Corporation
12–16
GENERATE_SVF_FILE
Default Value
Off
© November 2008
Altera Corporation
ISP_CLAMP_STATE
12–17
ISP_CLAMP_STATE
Specifies the pin state during in-system programming. This option is ignored if it is assigned to anything
other than pins.
Type
Enumeration
■
High
■
Low
■
Sample and Sustain
■
Tri-state
Device Support
■
MAX II
■
MAX7000B
Syntax
set_instance_assignment -name ISP_CLAMP_STATE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
12–18
ISP_CLAMP_STATE_DEFAULT
ISP_CLAMP_STATE_DEFAULT
Type
Enumeration
■
High
■
Low
■
Sample and Sustain
■
Tri-state
Device Support
■
MAX II
■
MAX7000B
Notes
Syntax
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT <value>
Default Value
Tri-state
© November 2008
Altera Corporation
MERGE_HEX_FILE
12–19
MERGE_HEX_FILE
Type
Boolean
Device Support
Syntax
set_global_assignment -name MERGE_HEX_FILE <value>
Default Value
Off
© November 2008
Altera Corporation
12–20
MERGE_HEX_FILE
© November 2008
Altera Corporation
13. SignalProbe Assignments
SIGNALPROBE_ALLOW_OVERUSE
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE <value>
Default Value
Off
© November 2008
Altera Corporation
13–2
SignalProbe Assignments
SIGNALPROBE_CLOCK
SIGNALPROBE_CLOCK
Registers the output of the SignalProbe node and assigns the specified clock to this register.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_instance_assignment -name SIGNALPROBE_CLOCK -to <to> <value>
© November 2008
Altera Corporation
SIGNALPROBE_DURING_NORMAL_COMPILATION
13–3
SIGNALPROBE_DURING_NORMAL_COMPILATION
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION <value>
Default Value
Off
© November 2008
Altera Corporation
13–4
SIGNALPROBE_ENABLE
SIGNALPROBE_ENABLE
Selects whether SignalProbe routing is enabled for current node.
Type
Boolean
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name SIGNALPROBE_ENABLE -to <to> <value>
© November 2008
Altera Corporation
SIGNALPROBE_NUM_REGISTERS
13–5
SIGNALPROBE_NUM_REGISTERS
Specifies the number of registers to insert before the output of the SignalProbe pin.
Type
Integer
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Syntax
set_instance_assignment -name SIGNALPROBE_NUM_REGISTERS -to <to> <value>
© November 2008
Altera Corporation
13–6
SIGNALPROBE_SOURCE
SIGNALPROBE_SOURCE
Assigns the source of the signal to be routed to the specified SignalProbe node.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
EXCALIBUR_ARM
Notes
Syntax
set_instance_assignment -name SIGNALPROBE_SOURCE -to <to> <value>
© November 2008
Altera Corporation
14. SignalTap II Assignments
ENABLE_LOGIC_ANALYZER_INTERFACE
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name ENABLE_LOGIC_ANALYZER_INTERFACE <value>
© November 2008
Altera Corporation
14–2
SignalTap II Assignments
ENABLE_SIGNALTAP
ENABLE_SIGNALTAP
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name ENABLE_SIGNALTAP <value>
© November 2008
Altera Corporation
STP_FILE
14–3
STP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name STP_FILE <value>
© November 2008
Altera Corporation
14–4
USE_LOGIC_ANALYZER_INTERFACE_FILE
USE_LOGIC_ANALYZER_INTERFACE_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name USE_LOGIC_ANALYZER_INTERFACE_FILE <value>
© November 2008
Altera Corporation
USE_SIGNALTAP_FILE
14–5
USE_SIGNALTAP_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name USE_SIGNALTAP_FILE <value>
© November 2008
Altera Corporation
14–6
USE_SIGNALTAP_FILE
© November 2008
Altera Corporation
15. LogicLock Region Assignments
LL_AUTO_SIZE
Type
Enumeration
■
Off
■
On
Device Support
Notes
Syntax
set_global_assignment -name LL_AUTO_SIZE -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
15–2
LogicLock Region Assignments
LL_ENABLED
LL_ENABLED
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LL_ENABLED -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
LL_EXCLUDE
15–3
LL_EXCLUDE
Prevents the current node or entity from being assigned to any LogicLock regions. You can use this option
to prevent specific sub-entities or nodes from inheriting the LogicLock region assignments on a
higher-level entity. Although turning on the Prevent Assignment to LogicLock Regions logic option for an
entity overrides LogicLock region assignments inherited from higher-level entities, this logic option does
not override explicit LogicLock region assignments on sub-entities or nodes contained in that entity. This
option is ignored if it is assigned to anything other than a node or design entity.
Type
Enumeration
■
On
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name LL_EXCLUDE -entity <entity name> <value>
set_instance_assignment -name LL_EXCLUDE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
15–4
LL_HEIGHT
LL_HEIGHT
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name LL_HEIGHT -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
LL_IMPORT_FILE
15–5
LL_IMPORT_FILE
Type
File name
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name LL_IMPORT_FILE <value>
set_global_assignment -name LL_IMPORT_FILE -entity <entity name> <value>
© November 2008
Altera Corporation
15–6
LL_IMPORT_FILE
set_instance_assignment -name LL_IMPORT_FILE -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
LL_IO_STANDARD
15–7
LL_IO_STANDARD
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Cyclone
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
Mercury
■
Stratix
■
Stratix GX
Notes
Syntax
set_instance_assignment -name LL_IO_STANDARD -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
15–8
LL_MEMBER_EXCEPTIONS
LL_MEMBER_EXCEPTIONS
If specified, the Fitter assigns all nodes under the target design entity or path to be members of the
LogicLock region, except for nodes of the specified types.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name LL_MEMBER_EXCEPTIONS -entity <entity name> -section_id
set_instance_assignment -name LL_MEMBER_EXCEPTIONS -to <to> -entity <entity name>
set_instance_assignment -name LL_MEMBER_EXCEPTIONS -from <from> -to <to> -entity <entity
Old Names
LL_MEMBER_RESOURCE_EXCLUDE
© November 2008
Altera Corporation
LL_MEMBER_OF
15–9
LL_MEMBER_OF
Assigns the current node(s) to a LogicLock region.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name LL_MEMBER_OF -entity <entity name> -section_id <section
identifier> <value>
set_instance_assignment -name LL_MEMBER_OF -to <to> -entity <entity name> -section_id
set_instance_assignment -name LL_MEMBER_OF -from <from> -to <to> -entity <entity name>
© November 2008
Altera Corporation
15–10
LL_MEMBER_OPTION
LL_MEMBER_OPTION
Options for LogicLock assignments.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name LL_MEMBER_OPTION -entity <entity name> -section_id <section
identifier> <value>
set_instance_assignment -name LL_MEMBER_OPTION -to <to> -entity <entity name>
set_instance_assignment -name LL_MEMBER_OPTION -from <from> -to <to> -entity <entity
© November 2008
Altera Corporation
LL_MEMBER_STATE
15–11
LL_MEMBER_STATE
Type
Enumeration
■
Floating
■
Locked
Device Support
Notes
Syntax
set_global_assignment -name LL_MEMBER_STATE -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
15–12
LL_NODE_LOCATION
LL_NODE_LOCATION
Specifies the location to which the target node is back-annotated. The location is specified as an absolute
location on the device. However, the Quartus II software interprets this location as a relative offset from
the LogicLock region's LL_ORIGIN setting. The target node must be assigned to the LogicLock region, and
this node's LL_MEMBER_STATE setting must be 'Locked.'
Type
Location
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name LL_NODE_LOCATION -to <to> -entity <entity name>
© November 2008
Altera Corporation
LL_ORIGIN
15–13
LL_ORIGIN
Type
Location
Device Support
Notes
Syntax
set_global_assignment -name LL_ORIGIN -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
15–14
LL_PARENT
LL_PARENT
Type
String
Device Support
Notes
Syntax
set_global_assignment -name LL_PARENT -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
LL_PATH_EXCLUDE
15–15
LL_PATH_EXCLUDE
Optionally exclude paths that go through the node named in the value field.
Type
String
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_global_assignment -name LL_PATH_EXCLUDE -entity <entity name> -section_id <section
identifier> <value>
set_instance_assignment -name LL_PATH_EXCLUDE -to <to> -entity <entity name> -section_id
set_instance_assignment -name LL_PATH_EXCLUDE -from <from> -to <to> -entity <entity name>
© November 2008
Altera Corporation
15–16
LL_PRIORITY
LL_PRIORITY
Indicates the priority of a wildcard or path-based LL_MEMBER_OF assignment relative to other wildcard
or path-based LL_MEMBER_OF assignments. If a node matches more than one wildcard or path-based
LL_MEMBER_OF assignment target, the assignment whose target has the highest LL_PRIORITY value
wins
Type
Integer
Device Support
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
EXCALIBUR_ARM
■
HardCopy Stratix
■
MAX II
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
Syntax
set_instance_assignment -name LL_PRIORITY -to <to> -entity <entity name> -section_id
set_instance_assignment -name LL_PRIORITY -from <from> -to <to> -entity <entity name>
© November 2008
Altera Corporation
LL_RCF_IMPORT_FILE
15–17
LL_RCF_IMPORT_FILE
Type
File name
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Notes
The name of this file is based on the project revision name.
Syntax
set_global_assignment -name LL_RCF_IMPORT_FILE -entity <entity name> <value>
set_instance_assignment -name LL_RCF_IMPORT_FILE -to <to> -entity <entity name> <value>
set_global_assignment -name LL_RCF_IMPORT_FILE <value>
© November 2008
Altera Corporation
15–18
LL_RESERVED
LL_RESERVED
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LL_RESERVED -entity <entity name> -section_id <section
identifier> <value>
Old Names
LL_RESERVE
© November 2008
Altera Corporation
LL_RESERVED_IS_LIMITED
15–19
LL_RESERVED_IS_LIMITED
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LL_RESERVED_IS_LIMITED -entity <entity name> -section_id
© November 2008
Altera Corporation
15–20
LL_ROOT_REGION
LL_ROOT_REGION
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LL_ROOT_REGION -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
LL_SOFT
15–21
LL_SOFT
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LL_SOFT -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
15–22
LL_STATE
LL_STATE
Type
Enumeration
■
Floating
■
Locked
■
Soft
Device Support
Notes
Syntax
set_global_assignment -name LL_STATE -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
LL_WIDTH
15–23
LL_WIDTH
Type
Integer
Device Support
Notes
Syntax
set_global_assignment -name LL_WIDTH -entity <entity name> -section_id <section
identifier> <value>
© November 2008
Altera Corporation
15–24
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
Type
Boolean
Device Support
Notes
Syntax
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT <value>
Default Value
Off
© November 2008
Altera Corporation
LOGICLOCK_INCREMENTAL_COMPILE_FILE
15–25
Type
File name
Device Support
Notes
This assignment is not copied when you create a new revision based on one that exists.
Syntax
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE <value>
© November 2008
Altera Corporation
15–26
© November 2008
Altera Corporation
16. Migration Assignments
MIGRATION_AUTO_PACKED_REGISTERS
Register Packings that have been performed on a prototype device and that must be reproduced on the
target migration device
Type
String
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
Notes
Syntax
set_instance_assignment -name MIGRATION_AUTO_PACKED_REGISTERS -to <to> -entity <entity
name> <value>
set_instance_assignment -name MIGRATION_AUTO_PACKED_REGISTERS -from <from> -to <to>
© November 2008
Altera Corporation
16–2
Migration Assignments
MIGRATION_AUTO_PORT_SWAP
MIGRATION_AUTO_PORT_SWAP
Port Swappings that have been performed on a prototype device and that must be reproduced on the
target migration device
Type
String
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
Notes
Syntax
set_instance_assignment -name MIGRATION_AUTO_PORT_SWAP -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
MIGRATION_RAM_INFORMATION
16–3
RAMs that have been created on a prototype device and that must be reproduced on the target migration
device
Type
String
Device Support
■
Arria GX
■
HardCopy II
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
Notes
Syntax
set_instance_assignment -name MIGRATION_RAM_INFORMATION -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
16–4
© November 2008
Altera Corporation
17. Netlist Viewer Assignments
RTLV_GROUP_COMB_LOGIC_IN_CLOUD
Type
Boolean
Device Support
Syntax
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD <value>
Default Value
Off
© November 2008
Altera Corporation
17–2
Netlist Viewer Assignments
RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
Type
Boolean
Device Support
Syntax
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV <value>
Default Value
Off
© November 2008
Altera Corporation
RTLV_GROUP_RELATED_NODES
17–3
RTLV_GROUP_RELATED_NODES
Type
Boolean
Device Support
Syntax
set_global_assignment -name RTLV_GROUP_RELATED_NODES <value>
Default Value
On
© November 2008
Altera Corporation
17–4
RTLV_GROUP_RELATED_NODES_TMV
RTLV_GROUP_RELATED_NODES_TMV
Type
Boolean
Device Support
Syntax
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV <value>
Default Value
On
© November 2008
Altera Corporation
RTLV_REMOVE_FANOUT_FREE_REGISTERS
17–5
RTLV_REMOVE_FANOUT_FREE_REGISTERS
Type
Boolean
Device Support
Syntax
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS <value>
Default Value
On
© November 2008
Altera Corporation
17–6
RTLV_SIMPLIFIED_LOGIC
RTLV_SIMPLIFIED_LOGIC
Type
Boolean
Device Support
Syntax
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC <value>
Default Value
On
© November 2008
Altera Corporation
18. Advanced I/O Timing Assignments
BOARD_MODEL_FAR_C
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_C -to <to> -entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_FAR_C -section_id <section identifier> <value>
© November 2008
Altera Corporation
18–2
Advanced I/O Timing Assignments
BOARD_MODEL_FAR_DIFFERENTIAL_R
BOARD_MODEL_FAR_DIFFERENTIAL_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id <section
identifier> <value>
© November 2008
Altera Corporation
BOARD_MODEL_FAR_PULLDOWN_R
18–3
BOARD_MODEL_FAR_PULLDOWN_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id <section identifier>
<value>
© November 2008
Altera Corporation
18–4
BOARD_MODEL_FAR_PULLUP_R
BOARD_MODEL_FAR_PULLUP_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id <section identifier>
<value>
© November 2008
Altera Corporation
BOARD_MODEL_FAR_SERIES_R
18–5
BOARD_MODEL_FAR_SERIES_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id <section identifier>
<value>
© November 2008
Altera Corporation
18–6
BOARD_MODEL_NEAR_C
BOARD_MODEL_NEAR_C
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_C -to <to> -entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_C -section_id <section identifier> <value>
© November 2008
Altera Corporation
BOARD_MODEL_NEAR_DIFFERENTIAL_R
18–7
BOARD_MODEL_NEAR_DIFFERENTIAL_R
Type
String
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id <section
identifier> <value>
© November 2008
Altera Corporation
18–8
BOARD_MODEL_NEAR_PULLDOWN_R
BOARD_MODEL_NEAR_PULLDOWN_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id <section identifier>
<value>
© November 2008
Altera Corporation
BOARD_MODEL_NEAR_PULLUP_R
18–9
BOARD_MODEL_NEAR_PULLUP_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id <section identifier>
<value>
© November 2008
Altera Corporation
18–10
BOARD_MODEL_NEAR_SERIES_R
BOARD_MODEL_NEAR_SERIES_R
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id <section identifier>
<value>
© November 2008
Altera Corporation
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
18–11
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
Type
String
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to <to> -entity
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -section_id <section
identifier> <value>
© November 2008
Altera Corporation
18–12
BOARD_MODEL_NEAR_TLINE_LENGTH
BOARD_MODEL_NEAR_TLINE_LENGTH
Type
String
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id <section
identifier> <value>
© November 2008
Altera Corporation
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
18–13
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
Type
String
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to <to> -entity
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -section_id <section
identifier> <value>
© November 2008
Altera Corporation
18–14
BOARD_MODEL_TERMINATION_V
BOARD_MODEL_TERMINATION_V
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id <section identifier>
<value>
© November 2008
Altera Corporation
BOARD_MODEL_TLINE_C_PER_LENGTH
18–15
BOARD_MODEL_TLINE_C_PER_LENGTH
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id <section
identifier> <value>
© November 2008
Altera Corporation
18–16
BOARD_MODEL_TLINE_LENGTH
BOARD_MODEL_TLINE_LENGTH
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to <to> -entity <entity name>
<value>
set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id <section identifier>
<value>
© November 2008
Altera Corporation
BOARD_MODEL_TLINE_L_PER_LENGTH
18–17
BOARD_MODEL_TLINE_L_PER_LENGTH
Type
String
Device Support
■
Arria GX
■
Cyclone III
■
HardCopy III
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id <section
identifier> <value>
© November 2008
Altera Corporation
18–18
ENABLE_ADVANCED_IO_TIMING
ENABLE_ADVANCED_IO_TIMING
Type
Boolean
Device Support
■
Arria GX
■
Stratix II
■
Stratix II GX
Syntax
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING <value>
© November 2008
Altera Corporation
OUTPUT_IO_TIMING_ENDPOINT
18–19
OUTPUT_IO_TIMING_ENDPOINT
Type
Enumeration
■
Far End
■
Near End
Device Support
■
Cyclone III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT <value>
Default Value
Near End
© November 2008
Altera Corporation
18–20
PCB_LAYER
PCB_LAYER
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name PCB_LAYER -to <to> -entity <entity name> <value>
set_global_assignment -name PCB_LAYER -section_id <section identifier> <value>
© November 2008
Altera Corporation
PCB_LAYERS
18–21
PCB_LAYERS
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name PCB_LAYERS -to <to> <value>
© November 2008
Altera Corporation
18–22
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name PCB_LAYER_THICKNESS -to <to> -entity <entity name> <value>
set_global_assignment -name PCB_LAYER_THICKNESS -section_id <section identifier> <value>
© November 2008
Altera Corporation
19. Classic Timing Assignments
ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
Type
Boolean
Device Support
Syntax
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS <value>
Default Value
On
© November 2008
Altera Corporation
19–2
Classic Timing Assignments
BASED_ON_CLOCK_SETTINGS
BASED_ON_CLOCK_SETTINGS
This assignment is part of a clock setting definition, and cannot be used on its own. It is recommended that
clock setting assignments are done either using the Quartus II GUI (using the Timing Settings dialog box)
or using the create_base_clock and create_relative_clock Tcl commands.
The Quartus II Timing Analyzer measures the delay of every design path and reports the performance of
the design in terms of maximum clock speed (fMAX). The Timing Analyzer supports both single-clock and
multiclock frequency analysis. To accurately analyze and constrain multiclock designs, you must define
the performance requirements and relationships of all clocks in your design by specifying clock settings.
Clock settings define which signals function as the absolute clocks (not dependent on other clocks) and
derived clocks (dependent on other clocks) in the design, as well as the desired frequency requirements
and other characteristics of each clock signal.
By default, the Timing Analyzer uses the most restrictive setup relationship and hold relationship when
analyzing paths between registers that are clocked by different clocks. However, you can instruct the
Timing Analyzer to relax its constraints by assigning other individual timing assignments to cut timing
paths, invert clocks, and assign various types of Multicycle paths that further optimize your design and
avoid incorrect set-up or hold time violations. In addition, you can direct the Timing Analyzer to analyze
the latency between related clocks, rather than the offset between clocks by turning on the Enable Clock
Latency option in the More Timing Settings dialog box.
Type
String
Device Support
Notes
Syntax
set_global_assignment -name BASED_ON_CLOCK_SETTINGS -section_id <section identifier>
<value>
See Also
■
create_base_clock and create_relative_clock Tcl commands
© November 2008
Altera Corporation
CLOCK_ENABLE_MULTICYCLE
19–3
CLOCK_ENABLE_MULTICYCLE
Specifies the number of clock cycles required before an enable-driven register latches a value. For more
detailed information, go to Quartus II online Help.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE -to <to> -entity <entity name>
<value>
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE -from <from> -to <to> -entity
© November 2008
Altera Corporation
19–4
CLOCK_ENABLE_MULTICYCLE_HOLD
CLOCK_ENABLE_MULTICYCLE_HOLD
Specifies the minimum number of clock cycles required before an enable-driven register latches a value.
For more detailed information, go to Quartus II online Help.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE_HOLD -to <to> -entity <entity
name> <value>
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE_HOLD -from <from> -to <to> -entity
Old Names
ENABLE_MULTICYCLE_HOLD
© November 2008
Altera Corporation
CLOCK_ENABLE_SOURCE_MULTICYCLE
19–5
CLOCK_ENABLE_SOURCE_MULTICYCLE
Specifies the maximum number of source clock cycles required before the enable-driven register latches a
value. For more detailed information, go to Quartus II online Help.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_ENABLE_SOURCE_MULTICYCLE -to <to> -entity <entity
name> <value>
set_instance_assignment -name CLOCK_ENABLE_SOURCE_MULTICYCLE -from <from> -to <to>
Old Names
ENABLE_SOURCE_MULTICYCLE
© November 2008
Altera Corporation
19–6
CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
Specifies the minimum number of source clock cycles required before an enable-driven register latches a
value. For more detailed information, go to Quartus II online Help.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD -to <to> -entity
set_instance_assignment -name CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD -from <from> -to <to>
Old Names
ENABLE_SOURCE_MULTICYCLE_HOLD
© November 2008
Altera Corporation
CLOCK_HOLD_UNCERTAINTY
19–7
CLOCK_HOLD_UNCERTAINTY
Specifies the clock uncertainty or clock jitter used when doing hold analysis
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_HOLD_UNCERTAINTY -to <to> -entity <entity name>
<value>
set_instance_assignment -name CLOCK_HOLD_UNCERTAINTY -from <from> -to <to> -entity
© November 2008
Altera Corporation
19–8
CLOCK_SETTINGS
CLOCK_SETTINGS
Assigns user-defined clock characteristics to a signal. To designate a particular signal as a clock, you must
define a named group of 'clock settings' and assign them to a signal with this option. You can create these
'clock settings' with the Timing Wizard (recommended) or the Timing Settings command (Assignments
menu).
Type
String
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_SETTINGS -to <to> -entity <entity name> <value>
Old Names
USE_CLOCK_SETTINGS
© November 2008
Altera Corporation
CLOCK_SETUP_UNCERTAINTY
19–9
CLOCK_SETUP_UNCERTAINTY
Specifies the clock uncertainty or clock jitter used when doing setup analysis
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name CLOCK_SETUP_UNCERTAINTY -to <to> -entity <entity name>
<value>
set_instance_assignment -name CLOCK_SETUP_UNCERTAINTY -from <from> -to <to> -entity
© November 2008
Altera Corporation
19–10
CUT
CUT
Excludes the node and its fan-out(s) from timing analysis when assigned to an input pin or an internal
register, or the node and its fan-in(s) when assigned to an output pin.
Directs the Timing Analyzer to exclude assigned paths from the timing analysis. For example, a
single-point Cut Timing Path assignment to a combinational node directs the Timing Analyzer to ignore
all paths through that node. The following guidelines apply when making this assignment:
- This assignment is only legal for observable node names (that is, nodes that are not synthesized away by
logic synthesis).
- Single-point Cut Timing Path assignments that include wildcards or time groups are expanded only to
registers or pins.
- In a single-point Cut Timing Path assignment to a register, the register is considered the assignment
source, even though a destination is required. In other words, a single-point Cut Timing Path assignment
represents a cut to a net, where a net is represented as the fan-out edges on a given node.
It is highly recommended that a point to point assignment is always use. This makes it less confusing.
Point to point assignments can be made between two registers, from a pin to a register, from a register to a
pin, or from a pin to a pin. Cut Timing Path Assignments can also be made between two clocks. A Cut
between two clocks is equivalent to cutting all paths from one clock domain to the second clock domain
Type
Boolean
Device Support
Notes
Syntax
set_instance_assignment -name CUT -to <to> -entity <entity name> <value>
set_instance_assignment -name CUT -from <from> -to <to> -entity <entity name> <value>
Example
# Basic src to dst path
set_instance_assignment -name cut on -from src -to dst
# From a src to all destinations
set_instance_assignment -name cut on -to src
set_instance_assignment -name cut on -from src -to *
# From all sources to dst
set_instance_assignment -name cut on -from * -to dst
# Cut all paths from one clock domain to another clock domain
set_instance_assignment -name cut on -from clk1 -to clk2
© November 2008
Altera Corporation
CUT
19–11
See Also
■
set_timing_cut_assignment Tcl function
© November 2008
Altera Corporation
19–12
CUT_OFF_IO_PIN_FEEDBACK
CUT_OFF_IO_PIN_FEEDBACK
Type
Boolean
Device Support
Syntax
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK <value>
Default Value
On
© November 2008
Altera Corporation
CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
19–13
CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
Type
Boolean
Device Support
Syntax
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS <value>
Default Value
On
© November 2008
Altera Corporation
19–14
CUT_OFF_READ_DURING_WRITE_PATHS
CUT_OFF_READ_DURING_WRITE_PATHS
Type
Boolean
Device Support
Syntax
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS <value>
Default Value
On
© November 2008
Altera Corporation
DEFAULT_HOLD_MULTICYCLE
19–15
DEFAULT_HOLD_MULTICYCLE
Specifies the default value for the Multicycle Hold requirement (that is, the minimum number of clock
cycles required before a register latches a value). The Default Multicycle Hold requirement is overridden
on specific nodes by any individual Multicycle Hold requirements. This is an advanced assignment that
can be changed by typing the following command at the Quartus II Tcl Console window:
set_global_assignment -name default_hold_multicycle <same as multicycle or one>
The following table describes the settings for this assignment:
* "Same as Multicycle" - Specifies that the Default Multicycle Hold requirement should match the value of
the Multicycle requirement. This setting is less restrictive than the One setting and generally produces
fewer hold time violation warnings. Same as Multicycle is the default value for this setting.
* "One" - Specifies that the signal should latch on the final edge. This setting is more restrictive than the
Same as Multicycle setting; however, it is the default setting used by the TimeQuest Timing Analyzer and
other timing analysis tools.
Type
Enumeration
■
One
■
Same as Multicycle
Device Support
Syntax
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE <value>
Example
set_global_assignment -name default_hold_multicycle "Same as Multicycle"
set_global_assignment -name default_hold_multicycle "One"
Default Value
Same as Multicycle
See Also
■
"MULTICYCLE" on page 19-47
■
"SOURCE_MULTICYCLE" on page 19-66
■
"MULTICYCLE_HOLD" on page 19-49
■
"SOURCE_MULTICYCLE_HOLD" on page 19-68
■
"SETUP_RELATIONSHIP" on page 19-65
■
"HOLD_RELATIONSHIP" on page 19-32
© November 2008
Altera Corporation
19–16
DIVIDE_BASE_CLOCK_PERIOD_BY
DIVIDE_BASE_CLOCK_PERIOD_BY
Type
Integer
Device Support
Syntax
set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY -section_id <section identifier>
<value>
Default Value
See Also
■
© November 2008
Altera Corporation
DO_COMBINED_ANALYSIS
19–17
DO_COMBINED_ANALYSIS
Directs the Timing Analyzer to run and report timing results using both the Fast timing model (best-case)
and slow timing model (worst-case). The results of each analysis are reported in the Fast Timing and Slow
Timing folders of the Timing Analyzer report. When you run a combined fast/slow analysis, the netlist is
annotated only with worst-case timing model results.
Type
Boolean
Device Support
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name DO_COMBINED_ANALYSIS <value>
Default Value
Off
© November 2008
Altera Corporation
19–18
DO_MIN_ANALYSIS
DO_MIN_ANALYSIS
Type
Boolean
Device Support
Syntax
set_global_assignment -name DO_MIN_ANALYSIS <value>
Default Value
Off
© November 2008
Altera Corporation
DO_MIN_TIMING
19–19
DO_MIN_TIMING
Type
Boolean
Device Support
Syntax
set_global_assignment -name DO_MIN_TIMING <value>
Default Value
Off
© November 2008
Altera Corporation
19–20
DUTY_CYCLE
DUTY_CYCLE
Type
Integer
Device Support
Syntax
set_global_assignment -name DUTY_CYCLE -section_id <section identifier> <value>
Default Value
See Also
■
© November 2008
Altera Corporation
EARLY_CLOCK_LATENCY
19–21
EARLY_CLOCK_LATENCY
Specifies additional delay in the clock network. This delay represents the external delay from an virtual (or
ideal) clock through the shortest path. The Timing Analyzer uses the more conservative latency value. For
setup analysis, it uses the early value for each destination register. For hold analysis, it uses the early value
for each of the source registers
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name EARLY_CLOCK_LATENCY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
19–22
ENABLE_CLOCK_LATENCY
ENABLE_CLOCK_LATENCY
Type
Boolean
Device Support
Syntax
set_global_assignment -name ENABLE_CLOCK_LATENCY <value>
Default Value
Off
© November 2008
Altera Corporation
ENABLE_RECOVERY_REMOVAL_ANALYSIS
19–23
ENABLE_RECOVERY_REMOVAL_ANALYSIS
Type
Boolean
Device Support
Syntax
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS <value>
Default Value
Off
© November 2008
Altera Corporation
19–24
EXCLUDE_FMAX_PATHS_GREATER_THAN
EXCLUDE_FMAX_PATHS_GREATER_THAN
Type
Time
Device Support
Syntax
set_global_assignment -name EXCLUDE_FMAX_PATHS_GREATER_THAN <value>
© November 2008
Altera Corporation
EXCLUDE_SLACK_PATHS_GREATER_THAN
19–25
EXCLUDE_SLACK_PATHS_GREATER_THAN
Type
Time
Device Support
Syntax
set_global_assignment -name EXCLUDE_SLACK_PATHS_GREATER_THAN <value>
© November 2008
Altera Corporation
19–26
EXCLUDE_TCO_PATHS_LESS_THAN
EXCLUDE_TCO_PATHS_LESS_THAN
Type
Time
Device Support
Syntax
set_global_assignment -name EXCLUDE_TCO_PATHS_LESS_THAN <value>
© November 2008
Altera Corporation
EXCLUDE_TH_PATHS_LESS_THAN
19–27
EXCLUDE_TH_PATHS_LESS_THAN
Type
Time
Device Support
Syntax
set_global_assignment -name EXCLUDE_TH_PATHS_LESS_THAN <value>
© November 2008
Altera Corporation
19–28
EXCLUDE_TPD_PATHS_LESS_THAN
EXCLUDE_TPD_PATHS_LESS_THAN
Type
Time
Device Support
Syntax
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN <value>
© November 2008
Altera Corporation
EXCLUDE_TSU_PATHS_LESS_THAN
19–29
EXCLUDE_TSU_PATHS_LESS_THAN
Type
Time
Device Support
Syntax
set_global_assignment -name EXCLUDE_TSU_PATHS_LESS_THAN <value>
© November 2008
Altera Corporation
19–30
FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
Type
Boolean
Device Support
Syntax
set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK <value>
Default Value
Off
© November 2008
Altera Corporation
FMAX_REQUIREMENT
19–31
FMAX_REQUIREMENT
Type
Frequency
Device Support
Syntax
set_global_assignment -name FMAX_REQUIREMENT <value>
set_global_assignment -name FMAX_REQUIREMENT -section_id <section identifier> <value>
© November 2008
Altera Corporation
19–32
HOLD_RELATIONSHIP
HOLD_RELATIONSHIP
Overwrites the hold relationship between two clocks. By default, the timing analyzer automatically
calculates the hold relationship based on the user's clock settings
Allows you to override the default hold relationship for assigned paths by specifying the minimum time
required before a register should latch a value. This assignment overrides any clock inversion, Multicycle
Hold, Source Multicycle Hold, Clock Enable Multicycle Hold, and Clock Enable Source Multicycle Hold
assignments, but takes into account any clock skew.
This assignment can be made between any two registers (where at least one path exist between them), but
it is most commonly used between two clock nodes. Making the assignment between two clocks is
equivalent to applying the constraint to all paths between one clock domain to the other.
Making a hold relationship assignment is equivalent to using an SDC set_min_delay command supported
by other timing analyzers.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name HOLD_RELATIONSHIP -from <from> -to <to> -entity <entity
name> <value>
See Also
■
"MULTICYCLE" on page 19-47
■
"MAX_DELAY" on page 19-43
■
"MIN_DELAY" on page 19-45
© November 2008
Altera Corporation
IGNORE_CLOCK_SETTINGS
19–33
IGNORE_CLOCK_SETTINGS
Type
Boolean
Device Support
Syntax
set_global_assignment -name IGNORE_CLOCK_SETTINGS <value>
set_global_assignment -name IGNORE_CLOCK_SETTINGS -section_id <section identifier>
<value>
Default Value
Off
© November 2008
Altera Corporation
19–34
INPUT_MAX_DELAY
INPUT_MAX_DELAY
Specifies the maximum external delay on the input (data) pin. It is the delay outside the chip before the
signal arrives to the input pin. Use the 'From' field to specify the clock reference name (i.e. the external
register's clock signal)
An individual timing assignment that specifies the maximum allowable delay of a signal from an external
register (outside the device) to the specified input or bidirectional pin. The value of this assignment
usually represents the tCO of the external register feeding the data input pin of the Altera device, plus the
actual board delay. The Timing Analyzer analyzes each pin with an input or output delay assignment as a
register. Therefore, the results for these paths are automatically reported in the corresponding Clock Setup
section of the Compilation Report.
In designs that use the LVDS I/O standard, you should specify the appropriate Input Maximum Delay to
the LVDS receiver megafunction. This input delay should equal the transmitter channel-to-channel skew
(TCCS) plus any board skew. If you assign the Input Minimum Delay assignment to a path, without
assigning a corresponding Input Maximum Delay assignment, the Timing Analyzer assumes the Input
Maximum Delay value is the same as the Input Minimum Delay assignment.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name INPUT_MAX_DELAY -from <from> -to <to> -entity <entity name>
<value>
Example
# Basic input delay from to pin from clock reference clk
set_instance_assignment -name input_max_delay 1ns -from clk -to pin
# Basic input delay from to all pin_bus* from clock reference clk
set_instance_assignment -name input_max_delay 1ns -from clk -to pin_bus*
# Using Tcl, the assignment can be done with
set_input_delay -max 1ns -clk_ref clk -to pin
Old Names
EXTERNAL_INPUT_DELAY
See Also
■
set_input_delay Tcl function
© November 2008
Altera Corporation
INPUT_MIN_DELAY
19–35
INPUT_MIN_DELAY
Specifies the minimum external delay on the input (data) pin. It is the delay outside the chip before the
signal arrives to the input pin. Use the 'From' field to specify the clock reference name (i.e. the external
register's clock signal)
An individual timing assignment that specifies the required minimum delay of a signal from an external
register (outside the device) to the specified input or bidirectional pin. The value of this assignment
usually represents the minimum tCO of the external register feeding the data input pin of the Altera
device, plus the actual board delay. The Timing Analyzer analyzes each pin with an input or output delay
assignment as a register. Therefore, the results for these paths are automatically reported in the
corresponding Clock Hold section of the Compilation Report. If you assign the Input Maximum Delay
assignment to a path, without assigning a corresponding Input Minimum Delay assignment, the Timing
Analyzer assumes the Input Minimum Delay value is the same as the Input Maximum Delay assignment.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name INPUT_MIN_DELAY -from <from> -to <to> -entity <entity name>
<value>
Example
# Basic input delay from to pin from clock reference clk
set_instance_assignment -name input_min_delay 1ns -from clk -to pin
# Basic input delay from to all pin_bus* from clock reference clk
set_instance_assignment -name input_min_delay 1ns -from clk -to pin_bus*
set_input_delay -min 1ns -clk_ref clk -to pin
See Also
■
set_input_delay Tcl function
© November 2008
Altera Corporation
19–36
INPUT_TRANSITION_TIME
INPUT_TRANSITION_TIME
Specifies the input transition time to be used for HardCopy designs. This assignment is used in Quartus to
adjust the timing of the I/O buffers. It is also used when generating the PrimeTime script that it is used by
the HardCopy back end. This assignment gets converted as a set_input_transition SDC command. If the
assignment does not exist, Quartus will generate a set_input_transition using 80% of VCCN * 1V/ns
where VCCN depends on the I/O Standard used
Type
Time
Device Support
■
APEX20KC
■
APEX20KE
■
Cyclone III
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Stratix
■
Stratix II
■
Stratix III
■
Stratix IV
Notes
Syntax
set_instance_assignment -name INPUT_TRANSITION_TIME -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
INVERTED_CLOCK
19–37
INVERTED_CLOCK
Specifies that a register has an inverted clock (the clock path contains a NOT gate). You can assign the
Inverted Clock assignment only as a single-point assignment. By default, the Timing Analyzer attempts to
automatically detect registers with inverted clocks. However, you can use this assignment in more
complex designs to designate inverted clocks the Timing Analyzer cannot auto-detect.
Type
Boolean
Device Support
Notes
Syntax
set_instance_assignment -name INVERTED_CLOCK -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
19–38
INVERT_BASE_CLOCK
INVERT_BASE_CLOCK
Type
Boolean
Device Support
Syntax
set_global_assignment -name INVERT_BASE_CLOCK -section_id <section identifier> <value>
Default Value
See Also
■
© November 2008
Altera Corporation
LATE_CLOCK_LATENCY
19–39
LATE_CLOCK_LATENCY
Specifies additional delay in the clock network. This delay represents the external delay from an virtual (or
ideal) clock through the longest path. The Timing Analyzer uses the more conservative latency value. For
setup analysis, it uses the late value for each source register. For hold analysis, it uses the late value for
each of the destination registers
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name LATE_CLOCK_LATENCY -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
19–40
LVDS_FIXED_CLOCK_DATA_PHASE
LVDS_FIXED_CLOCK_DATA_PHASE
Specifies exact skew compensation. When the fixed clock-to-data skew is known, clock data
synchronization (CDS) can be pre-programmed into the device during configuration. If CDS is
pre-programmed into the device, training patterns do not need to be transmitted to the receiver channels.
The resolution of each pre-programmed setting is 25% of the data period, to compensate for skew up to
50% of the data period. This option is applied only to input pins that drive the rx_in[] port of the altlvds_rx
megafunction. This option is available for APEX II devices only.
Type
Enumeration
■
Default
■
Negative 180
■
Negative 90
■
Positive 180
■
Positive 90
■
Zero
Device Support
■
APEX II
Syntax
set_instance_assignment -name LVDS_FIXED_CLOCK_DATA_PHASE -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
MAX_CLOCK_ARRIVAL_SKEW
19–41
MAX_CLOCK_ARRIVAL_SKEW
Specify the maximum clock skew between a set of registers. This assignment is specified between a clock
node name and a set of registers. The set of registers can be specified with either a wildcard or a timegroup
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name MAX_CLOCK_ARRIVAL_SKEW -from <from> -to <to> -entity
© November 2008
Altera Corporation
19–42
MAX_DATA_ARRIVAL_SKEW
MAX_DATA_ARRIVAL_SKEW
Specify the maximum data arrival skew between a set of registers and/or pins. In this case, the data arrival
delay represents the Tco from the clock to the given register and/or pin. This assignment is specified
between a clock node and a set of registers and/or pins. The set of registers and/or pins can be specified
with either a wildcard or a timegroup
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name MAX_DATA_ARRIVAL_SKEW -from <from> -to <to> -entity
© November 2008
Altera Corporation
MAX_DELAY
19–43
MAX_DELAY
Specifies the maximum required delay for paths between pins to registers, registers to registers and
register to pins. This requirement overwrites the requirement computed from the clock setup relationship
and clock skew.
Allows you to specify the maximum required delay for the assigned pin-to-register, register-to-register,
register-to-pin, and clock-to-clock path(s). This requirement overrides the delay requirement computed
from the clock setup relationship and clock skew.
Note that making a max delay assignment is NOT equivalent to using an SDC set_max_delay command
supported by other timing analyzers. For that, use the setup relationship timing assignment.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name MAX_DELAY -from <from> -to <to> -entity <entity name>
<value>
See Also
■
■
■
© November 2008
Altera Corporation
19–44
MINIMUM_TPD_REQUIREMENT
MINIMUM_TPD_REQUIREMENT
Specifies the minimum acceptable input to non-registered output delay, that is, the minimum time
required for a signal from an input pin to propagate through combinatorial logic and appear at an output
pin.
Specifies the minimum acceptable pin-to-pin delay (tPD), that is, the time required for a signal from an
input pin to propagate through combinational logic and appear at an external output pin. You can also use
this assignment to specify the minimum point-to-point delays within the device. You can assign the
Minimum tpd Requirement timing assignment between a specific source and destination, or to all valid
nodes included in a wildcard or time group assignment.
Type
Time
Device Support
Notes
Syntax
set_global_assignment -name MINIMUM_TPD_REQUIREMENT <value>
set_instance_assignment -name MINIMUM_TPD_REQUIREMENT -to <to> -entity <entity name>
<value>
set_instance_assignment -name MINIMUM_TPD_REQUIREMENT -from <from> -to <to> -entity
Example
set_instance_assignment -name min_tpd_requirement 2ns -from in_pin -to out_pin
set_instance_assignment -name min_tpd_requirement 2ns -to out_pin
set_instance_assignment -name min_tpd_requirement 2ns -from * -to out_pin
set_instance_assignment -name min_tpd_requirement 2ns -from in_pin -to *
Old Names
MINIMUM_DELAY_REQUIREMENT
See Also
■
"TPD_REQUIREMENT" on page 19-79
■
© November 2008
Altera Corporation
MIN_DELAY
19–45
MIN_DELAY
Specifies the minimum required delay for paths between pins to registers, registers to registers and
register to pins. This requirement overwrites the requirement computed from the clock hold relationship
and clock skew.
Allows you to specify the minimum required delay for the assigned pin-to-register, register-to-register,
register-to-pin, and clock-to-clock path(s). This requirement overrides the delay requirement computed
from the clock hold relationship and clock skew.
Note that making a min delay assignment is NOT equivalent to using an SDC set_min_delay command
supported by other timing analyzers. For that, use the hold relationship timing assignment.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name MIN_DELAY -from <from> -to <to> -entity <entity name>
<value>
See Also
■
■
■
© November 2008
Altera Corporation
19–46
MIN_TCO_REQUIREMENT
MIN_TCO_REQUIREMENT
Specifies the minimum acceptable clock to output delay to the output pin. The clock to output delay is the
time required to obtain a valid output at an output pin that is fed by a register after a clock signal
transition on an input pin that clocks the register. This time always represents an external pin-to-pin delay.
Specifies the minimum acceptable clock-to-output delay to the output pin. In other words, the minimum
You can assign the Minimum tco Requirement timing assignment between a specific source and
destination, or to all valid nodes included in a wildcard or time group assignment.
Type
Time
Device Support
Notes
Syntax
set_global_assignment -name MIN_TCO_REQUIREMENT <value>
set_instance_assignment -name MIN_TCO_REQUIREMENT -to <to> -entity <entity name> <value>
set_instance_assignment -name MIN_TCO_REQUIREMENT -from <from> -to <to> -entity <entity
name> <value>
Example
# Specific clk to pin path
set_instance_assignment -name min_tco_requirement 5ms -from clk -to pin
# From clk to any output pin
set_instance_assignment -name min_tco_requirement 5ms -to clk
set_instance_assignment -name min_tco_requirement 5ms -from clk -to *
# From any clock to pin
set_instance_assignment -name min_tco_requirement 5ms -to pin
set_instance_assignment -name min_tco_requirement 5ms -from * -to pin
See Also
■
"TCO_REQUIREMENT" on page 19-71
■
"OUTPUT_MAX_DELAY" on page 19-58
■
"OUTPUT_MIN_DELAY" on page 19-59
© November 2008
Altera Corporation
MULTICYCLE
19–47
MULTICYCLE
Specifies the number of clock cycles required before a register should latch a value. For example, setting
Multicycle to 2 on a clocked register overrides the default setup time relationship and delays the latch edge
by one clock cycle. You can assign a Multicycle timing assignment to a destination register, or as a
point-to-point assignment between two registers or two clocks. For more detailed information, go to
Quartus II online help.
Relaxes the setup relationship by allowing you to specify the number of destination clock cycles required
before a register latches a value. This assignment may be helpful in achieving timing requirements in
designs by adding destination clock cycles. For example, assigning a Multicycle value of 2 to a clocked
register delays the latch edge by one destination clock cycle.
You can assign the Multicycle timing assignment between a specific source and destination, or to all valid
nodes included in a wildcard or time group assignment. The value of this assignment must be a positive
number greater than zero. By default, the Timing Analyzer assumes that the Default Multicycle Hold
setting is the same as the Multicycle setting. Therefore, if you assign a Multicycle, Source Multicycle, Clock
Enable Multicycle, and/or Clock Enable Source Multicycle assignment, the corresponding hold
requirement is similarly changed unless you specify a specific value for the hold requirement.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name MULTICYCLE -to <to> -entity <entity name> <value>
set_instance_assignment -name MULTICYCLE -from <from> -to <to> -entity <entity name>
<value>
Example
# From a set of registers to another set of registers
set_instance_assignment -name multicycle 2 -from *src* -to *dst*
# From all registers to dst
set_instance_assignment -name multicycle 2 -to dst
set_instance_assignment -name multicycle 2 -from * -to dst
# Multicycle all paths from one clock domain to another clock domain
set_instance_assignment -name multicycle 2 -from clk1 -to clk2
# Assignment can easily be done in Tcl with
set_multicycle_assignment -setup 2 -end -from src -to dst
© November 2008
Altera Corporation
19–48
MULTICYCLE
See Also
■
set_multicycle_assignment Tcl function
© November 2008
Altera Corporation
MULTICYCLE_HOLD
19–49
MULTICYCLE_HOLD
Specifies the minimum number of clock cycles required before a register should latch a value. For example,
setting Multicycle Hold to 2 on a clocked register, forces the signal to travel from the source to the
destination register in no less than two clock cycles in order to meet the requirement. You can assign a
Multicycle Hold timing assignment to a destination register, or as a point-to-point assignment between
two registers or two clocks. For more detailed information, go to Quartus II online help.
Relaxes the hold relationship by allowing you to specify the minimum number of destination register
clock cycles required before a register latches a value. When the source and destination clocks have
different frequencies, this assignment allows you to increase the required hold delay by adding destination
clock cycles. For example, if you assign a Multicycle Hold requirement of 2 to a clocked register, the signal
must travel from the source to the destination register in no less than negative one clock cycle in order to
meet the requirement. This assignment may be helpful in correcting internal hold violations caused by
clock skew.
You can assign the Multicycle Hold timing assignment between a specific source and destination, or to all
valid nodes included in a wildcard or time group assignment. By default, the Timing Analyzer assumes
that the Default Multicycle Hold setting is the same as the Multicycle setting. Therefore, if you assign a
Multicycle, Source Multicycle, Clock Enable Multicycle, or Clock Enable Source Multicycle assignment,
the corresponding multicycle hold requirement is similarly changed unless you specify a specific value for
the hold requirement.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name MULTICYCLE_HOLD -to <to> -entity <entity name> <value>
set_instance_assignment -name MULTICYCLE_HOLD -from <from> -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name hold_multicycle 2 -from *src* -to *dst*
set_instance_assignment -name hold_multicycle 2 -to dst
set_instance_assignment -name hold_multicycle 2 -from * -to dst
set_instance_assignment -name hold_multicycle 2 -from clk1 -to clk2
© November 2008
Altera Corporation
19–50
MULTICYCLE_HOLD
set_multicycle_assignment -hold 2 -end -from src -to dst
See Also
■
© November 2008
Altera Corporation
MULTIPLY_BASE_CLOCK_PERIOD_BY
19–51
MULTIPLY_BASE_CLOCK_PERIOD_BY
Type
Integer
Device Support
Syntax
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY -section_id <section
identifier> <value>
Default Value
See Also
■
© November 2008
Altera Corporation
19–52
NOMINAL_CORE_SUPPLY_VOLTAGE
NOMINAL_CORE_SUPPLY_VOLTAGE
Type
String
Device Support
■
Cyclone III
■
HardCopy III
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE <value>
© November 2008
Altera Corporation
NOT_A_CLOCK
19–53
NOT_A_CLOCK
Specifies that this pin is not a clock and should not be included as a clock source in timing analysis.
Type
Boolean
Device Support
Notes
Syntax
set_instance_assignment -name NOT_A_CLOCK -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
19–54
NUMBER_OF_DESTINATION_TO_REPORT
NUMBER_OF_DESTINATION_TO_REPORT
Type
Integer
Device Support
Syntax
set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT <value>
Default Value
10
© November 2008
Altera Corporation
NUMBER_OF_PATHS_TO_REPORT
19–55
NUMBER_OF_PATHS_TO_REPORT
Type
Integer
Device Support
Syntax
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT <value>
Default Value
200
© November 2008
Altera Corporation
19–56
NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
Type
Integer
Device Support
Syntax
set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT <value>
Default Value
10
© November 2008
Altera Corporation
OFFSET_FROM_BASE_CLOCK
19–57
OFFSET_FROM_BASE_CLOCK
Type
Time
Device Support
Syntax
set_global_assignment -name OFFSET_FROM_BASE_CLOCK -section_id <section identifier>
<value>
See Also
■
© November 2008
Altera Corporation
19–58
OUTPUT_MAX_DELAY
OUTPUT_MAX_DELAY
Specifies the maximum delay of the logic outside the FPGA driven by the output (data) pin. Use the 'From'
field to specify the clock reference name (i.e. the external register's clock signal)
An individual timing assignment that specifies the maximum allowable delay of a signal from the
specified output pin of an Altera device to an external register (outside the device). The value of this
assignment usually represents the tSU of an external register fed by the data output pin of the Altera
device, plus the actual board delay. The Timing Analyzer analyzes each pin with an input or output delay
assignment as a register. Therefore, the results for these paths are automatically reported in the
corresponding Clock Setup section of the Compilation Report. If you assign the Output Minimum Delay
assignment to a path, without assigning a corresponding Output Maximum Delay assignment, the Timing
Analyzer assumes the Output Maximum Delay value is the same as the Output Minimum Delay
assignment.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name OUTPUT_MAX_DELAY -from <from> -to <to> -entity <entity
name> <value>
Example
# Basic output delay from from a pin with clock reference clk
set_instance_assignment -name output_max_delay 1ns -from clk -to pin
# Basic output delay from from all pin_bus* with clock reference clk
set_instance_assignment -name output_max_delay 1ns -from clk -to pin_bus*
set_output_delay -max 1ns -clk_ref clk -to pin
Old Names
EXTERNAL_OUTPUT_DELAY
See Also
■
set_output_delay Tcl function
© November 2008
Altera Corporation
OUTPUT_MIN_DELAY
19–59
OUTPUT_MIN_DELAY
Specifies the minimum delay of the logic outside the FPGA driven by the output (data) pin. Use the 'From'
field to specify the clock reference name (i.e. the external register's clock signal)
An individual timing assignment that specifies the required minimum delay of a signal from the specified
output pin of an Altera device to an external register (outside the device). The value of this assignment
usually represents the hold time of an external register fed by the data output pin of the Altera device, plus
the actual board delay. The Timing Analyzer analyzes each pin with an input or output delay assignment
as a register. Therefore, the results for these paths are automatically reported in the corresponding Clock
Hold section of the Compilation Report. If you assign the Output Maximum Delay assignment to a path,
without assigning a corresponding Output Minimum Delay assignment, the Timing Analyzer assumes the
Output Minimum Delay value is the same as the Output Maximum Delay assignment.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name OUTPUT_MIN_DELAY -from <from> -to <to> -entity <entity
name> <value>
Example
# Basic output delay from from a pin with clock reference clk
set_instance_assignment -name output_min_delay 1ns -from clk -to pin
# Basic output delay from from all pin_bus* with clock reference clk
set_instance_assignment -name output_min_delay 1ns -from clk -to pin_bus*
set_output_delay -min 1ns -clk_ref clk -to pin
See Also
■
set_output_delay Tcl function
© November 2008
Altera Corporation
19–60
PHASE_FROM_BASE_CLOCK
PHASE_FROM_BASE_CLOCK
Type
String
Device Support
Notes
Syntax
set_global_assignment -name PHASE_FROM_BASE_CLOCK -section_id <section identifier>
<value>
See Also
■
© November 2008
Altera Corporation
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
19–61
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
Specifies an external board delay between a feedback output pin and a feedback input pin (fbin) for a PLL
in external feedback mode. This option is ignored if it is assigned to anything other than the fbin pin of a
PLL.
Type
Time
Device Support
■
APEX II
■
APEX20KC
■
APEX20KE
■
Arria GX
■
EXCALIBUR_ARM
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
Mercury
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_instance_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY -to <to> -entity <entity
name> <value>
set_global_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY <value>
© November 2008
Altera Corporation
19–62
REPORT_AS_DQS
REPORT_AS_DQS
Type
Boolean
Device Support
■
Arria GX
■
HardCopy Stratix
■
Stratix
■
Stratix GX
■
Stratix II
■
Stratix II GX
Syntax
set_instance_assignment -name REPORT_AS_DQS -to <to> -entity <entity name> <value>
© November 2008
Altera Corporation
REPORT_DELAY
19–63
REPORT_DELAY
Directs the Timing Analyzer to analyze and report the delay for the specified pin-to-register,
register-to-register, or register-to-pin path
Type
Boolean
Device Support
Syntax
set_instance_assignment -name REPORT_DELAY -from <from> -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
19–64
REPORT_IO_PATHS_SEPARATELY
REPORT_IO_PATHS_SEPARATELY
Type
Boolean
Device Support
Syntax
set_global_assignment -name REPORT_IO_PATHS_SEPARATELY <value>
Default Value
Off
© November 2008
Altera Corporation
SETUP_RELATIONSHIP
19–65
SETUP_RELATIONSHIP
Overwrites the setup relationship between two clocks. By default, the timing analyzer automatically
calculates the setup relationship based on the user's clock settings
Allows you to override the default setup relationship for assigned paths by specifying the time required
before a register should latch a value. This assignment overrides any clock inversion, clock offsets,
Multicycle, Source Multicycle, Clock Enable Multicycle, and Clock Enable Source Multicycle assignments,
but takes into account any clock skew.
Making a setup relationship assignment is equivalent to using an SDC set_max_delay command
supported by other timing analyzers.
Type
Time
Device Support
Notes
Syntax
set_instance_assignment -name SETUP_RELATIONSHIP -from <from> -to <to> -entity <entity
name> <value>
See Also
■
"MULTICYCLE_HOLD" on page 19-49
■
■
© November 2008
Altera Corporation
19–66
SOURCE_MULTICYCLE
SOURCE_MULTICYCLE
Specifies the maximum number of source clock cycles required before a register latches a value. When the
source and destination clocks have different frequencies, this assignment allows you to increase the
required setup delay by adding source clock cycles. For example, setting Source Multicycle to 2 on a
clocked register overrides the default setup time relationship and delays the latch edge by one clock cycle.
You can assign a Source Multicycle timing assignment to a destination register, or as a point-to-point
assignment between two registers or two clocks. For more detailed information, go to Quartus II online
help.
Relaxes the setup relationship by allowing you to specify the number of source clock cycles required
before a register should latch a value. This assignment may be helpful in achieving timing requirements in
designs by adding source clock cycles. For example, assigning a Source Multicycle value of 2 to a clocked
register delays the latch edge by one clock cycle.
You can assign the Source Multicycle timing assignment between a specific source and destination, or to
all valid nodes included in a wildcard or time group assignment. The value of this assignment must be a
positive number greater than zero. By default, the Timing Analyzer assumes that the Default Multicycle
Hold setting is the same as the Multicycle setting. Therefore, if you assign a Multicycle, Source Multicycle,
Clock Enable Multicycle, or Clock Enable Source Multicycle assignment, the corresponding hold
requirement is similarly changed unless you specify a specific value for the hold requirement.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name SOURCE_MULTICYCLE -to <to> -entity <entity name> <value>
set_instance_assignment -name SOURCE_MULTICYCLE -from <from> -to <to> -entity <entity
name> <value>
Example
set_instance_assignment -name src_multicycle 2 -from *src* -to *dst*
set_instance_assignment -name src_multicycle 2 -to dst
set_instance_assignment -name src_multicycle 2 -from * -to dst
set_instance_assignment -name src_multicycle 2 -from clk1 -to clk2
© November 2008
Altera Corporation
SOURCE_MULTICYCLE
19–67
set_multicycle_assignment -start -setup 2 -from src -to dst
See Also
■
© November 2008
Altera Corporation
19–68
SOURCE_MULTICYCLE_HOLD
Specifies the minimum number of source clock cycles required before a register latches a value. When the
source and destination clocks have different frequencies, this assignment allows you to increase the
required hold delay by adding source clock cycles. You can assign a Source Multicycle Hold timing
assignment to a destination register, or as a point-to-point assignment between two registers or two clocks.
For more detailed information, go to Quartus II online help.
Relaxes the hold relationship by allowing you to specify the minimum number of source register clock
cycles required before a register latches a value. When the source and destination clocks have different
frequencies, this assignment allows you to increase the required hold delay by adding source clock cycles.
For example, if you assign a Source Multicycle Hold requirement of 2 to a clocked register, the signal must
travel from the source to the destination register in no less than negative one source clock cycle in order to
meet the requirement. This assignment may be helpful in correcting internal hold violations caused by
clock skew.
You can assign the Source Multicycle Hold timing assignment between a specific source and destination,
or to all valid nodes included in a wildcard or time group assignment. By default, the Timing Analyzer
assumes that the Default Multicycle Hold setting is the same as the Multicycle setting. Therefore, if you
assign a Multicycle, Source Multicycle, Clock Enable Multicycle, or Clock Enable Source Multicycle
assignment, the corresponding hold requirement is similarly changed unless you specify a specific value
for the hold requirement.
Type
Integer
Device Support
Notes
Syntax
set_instance_assignment -name SOURCE_MULTICYCLE_HOLD -to <to> -entity <entity name>
<value>
set_instance_assignment -name SOURCE_MULTICYCLE_HOLD -from <from> -to <to> -entity
Example
set_instance_assignment -name src_hold_multicycle 2 -from *src* -to *dst*
set_instance_assignment -name src_hold_multicycle 2 -to dst
set_instance_assignment -name src_hold_multicycle 2 -from * -to dst
set_instance_assignment -name src_hold_multicycle 2 -from clk1 -to clk2
© November 2008
Altera Corporation
19–69
set_multicycle_assignment -hold 2 -start -from src -to dst
See Also
■
© November 2008
Altera Corporation
19–70
TAO_FILE
TAO_FILE
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TAO_FILE <value>
© November 2008
Altera Corporation
TCO_REQUIREMENT
19–71
TCO_REQUIREMENT
Specifies the maximum acceptable clock to output delay to the output pin. The clock to output delay is the
Specifies the maximum acceptable clock-to-output delay to the output pin. The clock-to-output delay is
the time required to obtain a valid output at an output pin that is fed by a register after a clock signal
You can assign the tco Requirement timing assignment between a specific source and destination, or to all
valid nodes included in a wildcard or timegroup assignment.
Type
Time
Device Support
Notes
Syntax
set_global_assignment -name TCO_REQUIREMENT <value>
set_instance_assignment -name TCO_REQUIREMENT -to <to> -entity <entity name> <value>
set_instance_assignment -name TCO_REQUIREMENT -from <from> -to <to> -entity <entity name>
<value>
Example
# Specific clk to pin path
set_instance_assignment -name tco_requirement 5ms -from clk -to pin
# From clk to any output pin
set_instance_assignment -name tco_requirement 5ms -to clk
set_instance_assignment -name tco_requirement 5ms -from clk -to *
# From any clock to pin
set_instance_assignment -name tco_requirement 5ms -to pin
set_instance_assignment -name tco_requirement 5ms -from * -to pin
See Also
■
"MIN_TCO_REQUIREMENT" on page 19-46
■
"OUTPUT_MAX_DELAY" on page 19-58
■
"OUTPUT_MIN_DELAY" on page 19-59
© November 2008
Altera Corporation
19–72
TH_REQUIREMENT
TH_REQUIREMENT
Specifies the maximum acceptable clock hold time for the input (data) pin.
Specifies the maximum acceptable clock hold (tH) time for the input (data) pin. You can assign the th
Requirement timing assignment between a specific source and destination, or to all valid nodes included
in a wildcard or timegroup assignment.
Type
Time
Device Support
Notes
Syntax
set_global_assignment -name TH_REQUIREMENT <value>
set_instance_assignment -name TH_REQUIREMENT -to <to> -entity <entity name> <value>
set_instance_assignment -name TH_REQUIREMENT -from <from> -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name th_requirement 3ns -from pin -to reg
set_instance_assignment -name th_requirement 3ns -to pin
set_instance_assignment -name th_requirement 3ns -from clk -to pin
set_instance_assignment -name th_requirement 3ns -to pin_bus*
See Also
■
"TH_REQUIREMENT" on page 19-72
■
"INPUT_MAX_DELAY" on page 19-34
■
"INPUT_MIN_DELAY" on page 19-35
© November 2008
Altera Corporation
TIMEQUEST_DO_CCPP_REMOVAL
19–73
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
MAX9000
■
Mercury
■
Stratix
© November 2008
Altera Corporation
19–74
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Syntax
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL <value>
© November 2008
Altera Corporation
TIMEQUEST_DO_REPORT_TIMING
19–75
TIMEQUEST_DO_REPORT_TIMING
Type
Boolean
Device Support
Syntax
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING <value>
Default Value
Off
© November 2008
Altera Corporation
19–76
TIMEQUEST_MULTICORNER_ANALYSIS
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
MAX9000
■
Mercury
■
Stratix
© November 2008
Altera Corporation
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
19–77
Syntax
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS <value>
© November 2008
Altera Corporation
19–78
TIMEQUEST_REPORT_SCRIPT
TIMEQUEST_REPORT_SCRIPT
Type
File name
Device Support
Notes
Syntax
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT <value>
© November 2008
Altera Corporation
TPD_REQUIREMENT
19–79
TPD_REQUIREMENT
Specifies the maximum acceptable input to non-registered output delay, that is, the time required for a
signal from an input pin to propagate through combinatorial logic and appear at an output pin.
Specifies the maximum acceptable pin-to-pin delay (tPD), that is, the time required for a signal from an
input pin to propagate through combinational logic and appear at an external output pin. You can also use
this assignment to specify the maximum point-to-point delays within the device. You can assign the tpd
Type
Time
Device Support
Notes
Syntax
set_global_assignment -name TPD_REQUIREMENT <value>
set_instance_assignment -name TPD_REQUIREMENT -to <to> -entity <entity name> <value>
set_instance_assignment -name TPD_REQUIREMENT -from <from> -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name min_tpd_requirement 2ns -from in_pin -to out_pin
set_instance_assignment -name min_tpd_requirement 2ns -to out_pin
set_instance_assignment -name min_tpd_requirement 2ns -from * -to out_pin
set_instance_assignment -name min_tpd_requirement 2ns -from in_pin -to *
See Also
■
"MINIMUM_TPD_REQUIREMENT" on page 19-44
■
© November 2008
Altera Corporation
19–80
TSU_REQUIREMENT
TSU_REQUIREMENT
Specifies the maximum acceptable clock setup time for the input (data) pin. The setup time is the length of
time for which data that feeds a register via its data or enable input(s) must be present at an input pin
before the clock signal that clocks the register is asserted at the clock pin.
Specifies the maximum acceptable clock setup time (tSU) for the input (data) pin. The setup time is the
length of time that data that feeds a register via its data or enable input(s) must be present at an input pin
before the clock signal that clocks the register is asserted at the clock pin. You can assign the tsu
Type
Time
Device Support
Notes
Syntax
set_global_assignment -name TSU_REQUIREMENT <value>
set_instance_assignment -name TSU_REQUIREMENT -to <to> -entity <entity name> <value>
set_instance_assignment -name TSU_REQUIREMENT -from <from> -to <to> -entity <entity name>
<value>
Example
set_instance_assignment -name tsu_requirement 3ns -from pin -to reg
set_instance_assignment -name tsu_requirement 3ns -to pin
set_instance_assignment -name tsu_requirement 3ns -from clk -to pin
set_instance_assignment -name tsu_requirement 3ns -to pin_bus*
See Also
■
"TH_REQUIREMENT" on page 19-72
■
"INPUT_MAX_DELAY" on page 19-34
■
"INPUT_MIN_DELAY" on page 19-35
© November 2008
Altera Corporation
USE_TIMEQUEST_TIMING_ANALYZER
19–81
Type
Boolean
Device Support
■
ACEX1K
■
APEX II
■
APEX20K
■
APEX20KC
■
APEX20KE
■
Arria GX
■
Cyclone
■
Cyclone II
■
Cyclone III
■
EXCALIBUR_ARM
■
FLEX10K
■
FLEX10KA
■
FLEX10KB
■
FLEX10KE
■
FLEX6000
■
FLEX8000
■
HardCopy II
■
HardCopy III
■
HardCopy Stratix
■
MAX II
■
MAX3000A
■
MAX7000A
■
MAX7000AE
■
MAX7000B
■
MAX7000S
■
MAX9000
■
Mercury
■
Stratix
© November 2008
Altera Corporation
19–82
■
Stratix GX
■
Stratix II
■
Stratix II GX
■
Stratix III
■
Stratix IV
Notes
Syntax
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER <value>
© November 2008
Altera Corporation
VIRTUAL_CLOCK_REFERENCE
19–83
Creates virtual clock with the given name, this name should be unique
Type
Boolean
Device Support
Syntax
set_instance_assignment -name VIRTUAL_CLOCK_REFERENCE -to <to> -entity <entity name>
<value>
© November 2008
Altera Corporation
19–84
© November 2008
Altera Corporation

Quartus II Settings File Reference Manual

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