Compal LA-8391P - Schematics. www.s

Transcription

A
B
C
D
E
1
1
QFKAA
Yosemite 10FG
2
2
LA-8391P REV 1.0 Schematic
Intel Processor(Ivy Bridge / Sandy Bridge)
PCH(Panther Point)
2012-02-02 Rev 1.0
3
3
4
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
SCHEMATICS, MB A8391
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
B
4019HG
Thursday, February 16, 2012
Sheet
E
1
of
61
A
B
C
D
E
Intel CPU
Ivy Bridge
Sandy Bridge
PCI-Express 16X Gen3
1
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
rPGA-989
eDP Conn.
37.5mm*37.5mm
Dual Channel
page 11,12
BANK 0, 1, 2, 3
page 22
1
1.5V DDRIII 1066/1333/1600 MT/s
page 5,6,7,8,9,10
VGA (DDR3)
CRT
NVIDIA N13P-GS/GL, 128bit with 1GB/2GB
page 23
FDI X8
DMI X4
2.7GT/s
5GT/s
page 13,14,15,16,17,18,19,20,21
USB30 4x
USB Right
5V 5GT/s
USB20 port 2,3
USB30 port 3,4
page 34
USB20 4x
LVDS Conn.
USB Left
USB20 port 0,1
USB30 port 1,2
page 39
5V 480MHz
page 22
FingerPrinter
USB20 3x
2
5V 480MHz
EC SMBus
HDMI-CEC
page 24
page 40
Glasses Free 3D
USB port 11
page 22
2
USB port 13
page 22
HDMI Conn.
Intel PCH
Panther Point
page 24
RJ45
Int. Camera
USB port 8
page 38
RTL8105E-VD 10/100M
RTL8111F-VB 1G
5V 480MHz
PCIe Gen1 1x
PCIeMini Card
WiMax USB port 9
page 36
1.5V 5GT/s
PCIe Gen1 1x
SATA Gen3 port 1
1.5V 5GT/s
5V 6GHz(600MB/s)
page 40
PCIe port 1
USB20 3x
FCBGA-989
PCIeMini Card
WLAN PCIe port 2
PCIe port4
mSATA
page 36
25mm*25mm
Cardreader
RTS5229
PCIeMini Card
3G/TV#1
TV#2
PCIe Gen1 1x
SATA Gen3 port 0
5V 6GHz(600MB/s)
SATA port 2
SATA ODD
USB port 12
USB port 10
page 36
SATA port 1
page 36
B-CAS
page 35
SIM
page 36
1.5V 5GT/s
page 25,26,27,28,29,30,31,32,33
page 38
5V 3GHz(300MB/s)
3
SATA port 2
page 34
SATA HDD
SATA port 0
page 34
3
PCIe Gen2 2x
1.5V 5GT/s
LPC BUS
HD Audio
3.3V 33 MHz
3.3V 24MHz
HDA Codec
SPI ROM
(4MB
+ 2MB)
page 25
Debug Port
page 45
ALC280
ENE KB930/KB9012
USB3.0 Right-side
UPD720202
USB3.0 Left-side
UPD720202
PCIe port5
page 40
PCIe port6
page 41
page 42
page 44
RTC CKT.
page 25
SPK Conn
page 43
DC/DC Interface CKT.
Touch Pad
page 46
page 47
4
Int.KBD
page 45
EC ROM
(128KB)
page 45
CIR
page 44
G-Sensor
page 45
EC SMBus
Power Circuit DC/DC
page 48,49,50,51,52,
53,54,55,56,57,58,59
JPIO
(HP &page
MIC)
43
4
Finger Printer/B
page 35
Power On/Off CKT.
page 46
Power/B
Issued Date
Compal Secret Data
page 46
2011/12/14
2012/12/31
Deciphered Date
Title
Size
Date:
A
B
C
D
Document Number
Rev
B
4019HG
Sheet
E
2
of
61
5
4
3
DESIGN CURRENT 0.1A
2
1
+3VL
+5VL
DESIGN CURRENT 0.1A
B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7
DESIGN CURRENT 5A
+5VALW
DESIGN CURRENT 2A
+1.8VS
SUSP#
SY8033BDBC
SUSP
DESIGN CURRENT 4A
N-CHANNEL
D
+5VS
D
BCPWON
SI4800
DESIGN CURRENT 0.5A
+5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED
TPS51125
DESIGN CURRENT 400mA
+5VS_LED
+3VS_HDP
DESIGN CURRENT 1.6A
+5VS_ODD
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_EN#
P-CHANNEL
AO-3413
VCCPPWRGD
Ipeak=6A, Imax=4.A, Iocp min=8
DESIGN CURRENT 6A
+VCCSA
DESIGN CURRENT 0.3A
+16VS
DESIGN CURRENT 5A
+3VALW
SY8037
LNB EN
Imax=0.3A, Iocp min=0.8A
APW7137
Ipeak=5A, Imax=3.5A, Iocp min=6.2A
WOL_EN#
C
P-CHANNEL
AO-3413
C
+3V_LAN
SYSON
DESIGN CURRENT 0.2A
P-CHANNEL
AO-3413
SUSP
DESIGN CURRENT 4A
N-CHANNEL
+3V
+3VS
LCD_ENVDD
SI4800
P-CHANNEL
AO-3413
DESIGN CURRENT 1.5A
+LCD_VDD
DESIGN CURRENT 0.5A
+FLICA_VCC
DESIGN CURRENT 0.1A
+3VS_DGPU
FELICA_PWR
P-CHANNEL
AO-3413
DGPU_PWR_EN
P-CHANNEL
AO-3413
VR_ON
NCP6132A
DESIGN CURRENT 94A
+CPU_CORE
DESIGN CURRENT 50A
+GFX_CORE
B
B
SUSP#
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A
TPS51212
SYSON
DESIGN CURRENT 3A
N-CHANNEL
AO3416
Ipeak=15A, Imax=10.5A, Iocp min=18A
RT8207M
+1.05VS_VCCP
DESIGN CURRENT 15A
DGPU_PWR_EN#
DESIGN CURRENT 10A
+1.05VS_DGPU
+1.5V
SUSP
DESIGN CURRENT 2A
N-CHANNEL
+1.5V_CPU
FDS6676AS
SUSP
N-CHANNEL
DESIGN CURRENT 2A
+1.5VS
DESIGN CURRENT 1A
+1.05V
FDS6676AS
+3V
APL5930KAI-TRG
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A
+0.75VS
A
A
VGA_PWROK
N-CHANNEL
SUSP#
DESIGN CURRENT 11A
+VRAM_1.5VS
DESIGN CURRENT 30A
+VGA_CORE
FDS6676AS
Ipeak=59A, Imax=45.7A, Iocp min=70A
ADP3211A
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
5
4
3
2
Document Number
Rev
B
4019HG
1
Sheet
3
of
61
A
B
C
D
Platform
Voltage Rails
( O MEANS ON
+RTCVCC
CPU
PCH
VGA
X MEANS OFF )
B+
+5VL
+5VALW
+3VL
+3VALW
+1.5V
+5VS
Clarksfield/
Arrandale
Discrete
(DIS@)
Calpella
+3VS
Optimus
(OPT@)
+1.8VS
+VSB
power
plane
1
SKU
E
Arrandale
HM76@/HM77@
N13PGSR1@/N13PGLR1@
HM76@/HM77@
N13PGSR1@/N13PGLR1@
+1.5VS
1
+1.05VS
+0.75VS
BTO Option Table
+CPU_CORE
+VGA_CORE
HDMI
Function
+GFX_CORE
description
+VTT
State
+VRAM_1.5VS
explain
UMA
Discrete/
Optimus
BTO
IHDMI@
DHDMI@
+3VS_DGPU
+1.05VS_DGPU
O
O
O
O
O
O
S1
O
O
O
O
O
O
S3
O
O
O
O
O
X
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
SLOT2
description
3G
explain
O
O
X
X
O
O
O
X
X
X
explain
G-SENSOR
O
X
X
X
X
X
BTO
GSENSOR@
3
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
WLAN/WIMAX
+3VS
3G
TV@
4
+3VL
Smart Battery
+3VL
HDMI-CEC
Power
Device
+3VL
Cap. Sensor
Clarksfield
Clarksfield with
S3 Power Saving
M1@
M3@
PSM3@
LAN
Fingerprint
CIR
KB Light
LAN
Fingerprint
CIR
KB Light
Giga
Fingerprint
CIR
KB Light
8111E@
FP@
WIMAX
10/100M
WIMAX@
8105E@
KBL@
CIR@
DIS@
Camera & Mic
LVDS
SKU
Discrete
2D HD/FHD Panel
Optimus
OPT@
description
N13P-GS
N13P-GL
explain
N13PGS
N13PGL
N13PGSR1@
N13PGLR1@
Optimus
LVDS2D@
OPTFHD@
2D HD eDP
3D Panel
Camera & Mic
Optimus
Discrete
Camera & Mic
IEDP@
3D@
CAM@
3
SIGNAL
STATE
Device
Arrandale
GPU
BTO
EC SM Bus1 Address
Power
CEC@
SKU
description G-SENSOR
Function
Device
HDMI@
Clarksfield
2
O
Power
TV Tuner
G-SENSOR
Function
O
PCH SM Bus Address
CEC
COMMON
SLOT1
3G@
BTO
2
Arrandale
MINI PCI-E SLOT
Function
S0
CPU
HDMI
HEX
EC SM Bus2 Address
HIGH
HIGH
HIGH
Address
S1(Power On Suspend)
HIGH
HIGH
HIGH
96 H
1001 0110 b
S3 (Suspend to RAM)
LOW
HIGH
HIGH
9E H
1001 1010 b
40 H
0100 0000 b
S4 (Suspend to Disk)
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Address
Power
Device
HEX
16 H
0001 0110 b
+3VS
PCH
34 H
0011 0100 b
+3VS
NVIDIA GPU
+3VS
G-Sensor
HEX
Full ON
SLP_S3# SLP_S4# SLP_S5#
Address
Virtual I2C
Compal Secret Data
Issued Date
4
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
A
B
C
D
Sheet
E
4
of
61
5
4
3
2
1
JCPUB
100 MHz
<30> H_SNB_IVB#
C26
PROC_SELECT#
@
1 CC63
H_PWRGOOD_R
T1
D
T2
<44>
+1.05VS_VCCP
PAD
TP_SKTOCC#
PAD
H_PECI
AN34
SKTOCC#
H_CATERR#
AL33
CATERR#
H_PECI
AN33
PECI
AL32
PROCHOT#
THERMAL
1000P_0402_50V7K 2
RC159
RC44
H_PROCHOT#
1 62_0402_5%
2
2 H_PROCHOT#_R
56_0402_5%
1
<44,49> H_PROCHOT#
RC160
RC45
2
H_PWRGOOD
1 10K_0402_5%
<30> H_THERMTRIP#
2 H_THERMTRIP#_R AN32
0_0402_5%
1
THERMTRIP#
BCLK
BCLK#
CLOCKS
H_SNB_IVB#
A28
A27
CLK_CPU_DMI
CLK_CPU_DMI#
Stuff R41 and R42 if do not support eDP
CLK_CPU_DMI <26>
CLK_CPU_DMI# <26>
+1.05VS_VCCP
120 MHz
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
DDR3
MISC
PM_DRAM_PWRGD_R
1 CC62
MISC
@
1000P_0402_50V7K 2
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
A16
A15
CLK_CPU_EDP
CLK_CPU_EDP#
R8
H_DRAMRST#
AK1
A5
A4
SM_RCOMP_0 RC56
SM_RCOMP_1 RC59
SM_RCOMP_2 RC61
CLK_CPU_EDP <26>
CLK_CPU_EDP# <26>
CLK_CPU_EDP#
RC1571 LVDS@ 2 1K_0402_5%
CLK_CPU_EDP
RC1581 LVDS@ 2 1K_0402_5%
H_DRAMRST# <7>
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
2
2
2
DDR3 Compensation Signals
Layout Note:Place these
resistors near Processor
H_PM_SYNC
<27> H_PM_SYNC
H_PECI
1 CC70
@
1000P_0402_50V7K 2
AM34
PM_SYNC
RC183
1 CC67
H_PM_SYNC
1 CC66
BUF_CPU_RST#
1
<30> H_PWRGOOD
2 H_PWRGOOD_R
0_0402_5%
AP33
UNCOREPWRGOOD
@
1000P_0402_50V7K 2
PM_SYS_PWRGD_BUF 1
RC170
2 PM_DRAM_PWRGD_R
130_0402_5%
V8
SM_DRAMPWROK
C
Please place near JCPU
BUF_CPU_RST#
AR33
RESET#
+3VALW_PCH
+3VALW_PCH
1 DRAMPWROK
200_0402_5%
XDP_PRDY#_R
XDP_PREQ#_R
RC161
1
RC162
1
@
@
2 0_0402_5%
2 0_0402_5%
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
RC163
1
RC164
1
RC165
1
@
@
@
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
XDP_TCK
XDP_TMS
XDP_TRST#
TDI
TDO
AR28
AP26
XDP_TDI_R
XDP_TDO_R
RC166
1
RC167
1
@
@
2 0_0402_5%
2 0_0402_5%
XDP_TDI
XDP_TDO
DBR#
AL35
XDP_DBRESET#_R
RC169
1
@
2 0_0402_5%
XDP_DBRESET#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R
RC171
1
RC172
1
RC173
1
RC174
1
RC175
1
RC177
1
RC179
1
RC181
1
@
@
@
@
@
@
@
@
2
2
2
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
Routed as a single daisy chain
RC168
1
2
1K_0402_5%
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
C
RC176
1
RC178
1
RC180
1
RC182
1
@
@
@
@
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
CFG12
CFG13
CFG14
CFG15
<10>
<10>
<10>
<10>
Close to CPU side
1
@
PU/PD for JTAG signals
+1.05VS_VCCP
P
O
4
PM_SYS_PWRGD_BUF
1
RC25
39_0402_5%
@
2 0_0402_5%
1 2
@
SUSP
SUSP
D
2
G
3
<9,36,47>
+3VS
XDP_DBRESET# <27>
TYCO_2013620-2_IVY BRIDGE
RC14
200_0402_5%
3
1
RC184
@
1
2
CC34
180P_0402_50V8J
by ESD requestion and place near CPU
G
<27> DRAMPWROK
1
2
0_0402_5% B
2 A
1
0.1U_0402_10V7K
CC33
UC1
74AHC1G09GW_TSSOP5
5
10K_0402_5%
2 RC13
1
1
RC12 @
<27,44> PM_PWROK
AP29
AP27
+1.5V_CPU
2
+3VS
PRDY#
PREQ#
2
2
RC11
JTAG & BPM
@
PWR MANAGEMENT
H_DRAMRST#
1000P_0402_50V7K 2
D
QC2
2N7002_SOT23
@
S
XDP_PREQ#_R
RC48
2
XDP_TMS_R
RC46
2
1 51_0402_5%
XDP_TDI_R
RC47
2
1 51_0402_5%
XDP_TDO_R
RC49
2
1 51_0402_5%
XDP_TCK_R
RC53
2
1 51_0402_5%
XDP_TRST#_R
RC55
2
1 51_0402_5%
@
1 51_0402_5%
B
B
JXDP1 @
XDP_BPM#2
XDP_BPM#3
+3VS
<27,44> PBTN_OUT#
<10>
CFG0
<27,44,55> VGATE
<26> CLK_CPU_ITP
<26> CLK_CPU_ITP#
+1.05VS_VCCP
1 0.1U_0402_10V7K
CC36
+1.05VS_VCCP
PLT_RST# <29,36,37,38,40,44,45>
1
2
UC2
2
3
OE#
VCC
5
OUT
4
IN
GND
BUFO_CPU_RST#
RC35
43_0402_1%
1
2
BUF_CPU_RST#
74AHC1G125GW_SOT353-5
RC40
0_0402_5%
@
@
@
@
@
@
1
RC189
2
2
2
2
1K_0402_5%XDP_CPU_HOOK0
0_0402_5% XDP_CPU_HOOK1
1K_0402_5%XDP_CPU_HOOK2
0_0402_5% XDP_CPU_HOOK3
CLK_CPU_ITP
CLK_CPU_ITP#
XDP_CPU_HOOK6
2
1K_0402_5% XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
1
2
XDP_TCK
R1
1
2
C3
10U_0805_10V6K
@ 1
2
0_0603_5%
+FAN1
@
JFAN
C2
10K_0402_5%
6
5
4
3
2
1
<44>
<44> FAN_SPEED1
1
2
FANPWM
+FAN1
C4
0.01U_0402_25V7K
@
G2
G1
4
3
2
1
ACES_50278-00401-001
1
D1
BAS16_SOT23-3
27
28
1
C5
C6
2
2
10U_0603_6.3V6M 1000P_0402_50V7K
A
2
A
CC64
0.1U_0402_10V7K
@
RC1851
RC1861
RC1871
RC1881
PLT_RST#
RC38
75_0402_5%
1
1
2
PLT_RST#
H_PWRGOOD
PBTN_OUT#
CFG0
VGATE
+3VS
0.5A
1
XDP_BPM#0
XDP_BPM#1
2
Buffered Reset to CPU
FAN Control Circuit
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
XDP_PREQ#
XDP_PRDY#
2
XDP Connector
MOLEX 52435-2671
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
5
of
61
5
4
3
2
1
+1.05VS_VCCP
RC1
24.9_0402_1%
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
<27>
<27>
<27>
<27>
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
<27>
<27>
<27>
<27>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<27>
<27>
<27>
<27>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
B27
B25
A25
B24
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
C
FDI_FSYNC0
FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
<27> FDI_INT
FDI_INT
H20
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
C15
D15
eDP_AUX
eDP_AUX#
<22> H_EDP_TXP0
<22> H_EDP_TXP1
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
<22> H_EDP_TXN0
<22> H_EDP_TXN1
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_COMP signals should be <27>
<27>
shorted near balls and
routed with typical
impedance <25m ohm
+1.05VS_VCCP
FDI_LSYNC0
FDI_LSYNC1
RC2
1
2 24.9_0402_1%
EDP_COMP
H_EDP_HPD#
<22> H_EDP_AUXP
<22> H_EDP_AUXN
B
eDP
<27> FDI_FSYNC0
<27> FDI_FSYNC1
PCI EXPRESS* - GRAPHICS
<27>
<27>
<27>
<27>
Intel(R) FDI
D
DMI
2
JCPUA
PEG_COMP
1
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 m ohm (12 mils)
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N15
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15
CC8
CC11
CC16
CC20
CC27
CC30
CC1
CC4
CC15
CC18
CC22
CC24
CC29
CC26
CC3
CC32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15
CC10
CC5
CC6
CC7
CC12
CC9
CC19
CC14
CC13
CC17
CC21
CC23
CC28
CC25
CC2
CC31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15
D
PCIE_GTX_C_CRX_N[0..15] <13>
PCIE_GTX_C_CRX_P[0..15] <13>
C
PCIE_CTX_C_GRX_N[0..15] <13>
PCIE_CTX_C_GRX_P[0..15] <13>
B
@
PEG
2
+1.05VS_VCCP
Close to CPU
1
FDI_LSYNC1
H_EDP_HPD#
1
FDI_LSYNC0
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
D
3
FDI_FSYNC1
A
1 DIS@
RC191
1 DIS@
RC192
1 DIS@
RC193
1 DIS@
RC194
1 DIS@
RC195
S
2
G
<22> CPU_EDP_HPD
2
FDI_FSYNC0
Gen1/Gen2
75
Gen3
180 nF~265 nF
SANDY Bridge
Gen1/Gen2
180 nF~265 nF
NV N13X
Gen1/2/3
Suggest 220 nF
IVY Bridge
nF~265 nF
2N7002_SOT23-3
QC1
IEDP@
A
IEDP@
RC4
100K_0402_5%
1
FDI_INT
RC3
1K_0402_5%
DG suggest AC cap
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
6
of
61
5
4
3
2
JCPUC
<11> DDR_A_D[0..63]
1
JCPUD
C
B
<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AE10
AF10
V6
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
SA_CAS#
SA_RAS#
SA_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
AB6
AA6
V9
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
AA5
AB5
V10
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
AB4
AA4
W9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
AK3
AL3
AG1
AH1
DDRA_SCS0#
DDRA_SCS1#
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
AH3
AG3
AG2
AH2
DDRA_ODT0
DDRA_ODT1
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR_A_DQS#0
C4
G6 DDR_A_DQS#1
DDR_A_DQS#2
J3
M6 DDR_A_DQS#3
AL6 DDR_A_DQS#4
AM8 DDR_A_DQS#5
AR12 DDR_A_DQS#6
AM15 DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDRA_CLK0 <11>
DDRA_CLK0# <11>
DDRA_CKE0 <11>
DDRA_CLK1 <11>
DDRA_CLK1# <11>
DDRA_CKE1 <11>
DDRA_SCS0# <11>
DDRA_SCS1# <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
<11>
<11>
<11>
<12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AA9
AA7
R6
SB_BS[0]
SB_BS[1]
SB_BS[2]
AA10
AB8
AB9
SB_CAS#
SB_RAS#
SB_WE#
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_WE#
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR SYSTEM MEMORY B
D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR SYSTEM MEMORY A
<12> DDR_B_D[0..63]
@
@
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
AE2
AD2
R9
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
AD3
AE3
AD6
AE6
DDRB_SCS0#
DDRB_SCS1#
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
AE4
AD4
AD5
AE5
DDRB_ODT0
DDRB_ODT1
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDRB_CLK0 <12>
DDRB_CLK0# <12>
DDRB_CKE0 <12>
DDRB_CLK1 <12>
DDRB_CLK1# <12>
DDRB_CKE1 <12>
D
DDRB_SCS0# <12>
DDRB_SCS1# <12>
DDRB_ODT0 <12>
DDRB_ODT1 <12>
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
<12>
C
<12>
<12>
B
D
2
3
2
RC77
1K_0402_5%
2
1
SM_DRAMRST# <11,12>
BSS138_NL_SOT23-3
2
G
RC78
4.99K_0402_1%
A
1
A
RC76
1K_0402_5%
QC3
DDR3_DRAMRST#_R
1
S
H_DRAMRST#
<5> H_DRAMRST#
1
+1.5V
RC75
0_0402_5%
1
2
@
1
RC73
<11,26> DRAMRST_CNTRL_PCH
2 DRAMRST_CNTRL
0_0402_5%
1
Issued Date
Compal Secret Data
CC37
0.047U_0402_25V6K
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
2
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
7
of
61
5
PEG AND DDR
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
C
Reserve 0.1u to avoid noise
1
+1.05VS_VCCP
0.1U_0402_10V7K
1
2
CC49
@
1
+1.05VS_VCCP
0.1U_0402_10V7K
1
2
CC50
@
SVID
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
RC89
75_0402_5%
2
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
2
RC91
130_0402_5%
1
RC90 1
RC88 1
RC92
2
2 43_0402_1%
2 0_0402_5%
0_0402_5%
VR_SVID_ALRT# <55>
VR_SVID_CLK <55>
VR_SVID_DAT <55>
B
Pull high resistor on VR side
2
+CPU_CORE
to CPU
1
RC93
Close
100_0402_1%
AJ35 VCCSENSE_R RC94 1
AJ34 VSSSENSE_R RC95 1
2 0_0402_5%
2 0_0402_5%
VCCSENSE <55>
VSSSENSE <55>
1
VCC_SENSE
VSS_SENSE
B10
A10
VCCIO_SENSE
RC97
100_0402_1%
VCCIO_SENSE <53>
A
RC96
10_0402_1%
RC98
10_0402_1%
2
VCCIO_SENSE
VSS_SENSE_VCCIO
1
A
D
SENSE LINES
B
1
8.5A
CORE SUPPLY
C
2
+1.05VS_VCCP
97A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
3
2
D
POWER
1
JCPUF
2
+CPU_CORE
4
+1.05VS_VCCP
Compal Secret Data
Issued Date
Close to CPU
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
5
Rev
B
4019HG
@ TYCO_2013620-2_IVY BRIDGE
4
3
2
Sheet
1
8
of
61
5
4
3
2
1
1
+GFX_CORE
+GFX_CORE
JCPUG
POWER
RC105
10_0402_1%
OPT@
B
10U_0805_10V6K
+1.8VS_VCCPLL
1
@
+
CC58
2
1
2
330U_B2_2.5VM_R15M
CC59
1
CC60
2
1U_0402_6.3V6K
1
2
SENSE
LINES
VREF
VCC_AXG_SENSE_R
VSS_AXG_SENSE_R
RC1961 OPT@
RC1971 OPT@
2 0_0402_5%
2 0_0402_5%
+V_SM_VREF should
have 20 mil trace width
1 1K_0402_0.5%
2
RC109
1
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
B4
D1
+VREF_DQA_M3
+VREF_DQB_M3
DDR3 -1.5V RAILS
D
+1.5V_CPU
RC120
1 1K_0402_0.5%
2
+V_SM_VREF
AL1
VCC_AXG_SENSE <55>
VSS_AXG_SENSE <55>
OPT@
1 RC106 2
10_0402_1%
CC65
0.1U_0402_10V7K
2
+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U
5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
10U_0805_10V6K
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
10U_0805_10V6K
10U_0805_10V6K
1
CC57
1
1
CC51
2
CC52
2
10U_0805_10V6K
1
CC55
2
1
CC54
2
10U_0805_10V6K
1
2
CC56
1
+
2
2
ESR 6mohm
CC53
@
330U_D2_2VM_R6M
10U_0805_10V6K
C
+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U
+VCCSA
Bottom Socket Cavity
Co-lay for Cost Down Plan
VCCSA_VID0
VCCSA_VID1
+VCCSA
SA RAIL
6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
M27
M26
L26
J26
J25
J24
H26
H25
10U_0805_10V6K
CC42
1
CC41
10U_0805_10V6K
1
CC43
1
CC40
1
1 RC200
1
+
2
2
2
@
2
2
10U_0805_10V6K
2+VCCSA_SENSE
0_0402_5%
CC44
@
330U_D2_2VM_R6M
10U_0805_10V6K
0
0
0.90 V
0
1
0.80 V
1
0
0.725 V
1
1
0.675 V
For Sandy Bridge
Bottom Socket Edge
1.2A
RC119
2
1
0_0805_5%
AK35
AK34
+1.5V_CPU
B6
A6
A2
VCCPLL1
VCCPLL2
VCCPLL3
CC61
1U_0402_6.3V6K
VCCSA_SENSE
H23
+VCCSA_SENSE <54>
@
1
2
RC111 0_0402_5%
MISC
+1.8VS
VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
GRAPHICS
C
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
1.8V RAIL
2
1
RC198
0_0402_5%
DIS@
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
2
33A
D
Close to CPU
VCCSA_VID[0]
VCCSA_VID[1]
C22
C24
VCCIO_SEL
A19
H_VCCSA_VID0
H_VCCSA_VID1
H_VCCSA_VID0 <54>
Please
H_VCCSA_VID1 <54>
kindly check whether
there is pull-down resister
in PWR-side or HW-side
B
+1.5V_CPU
@
+1.5V_CPU
+1.5VS
PJ1
@
2
1
2
+1.5V
1
JUMP_43X118
Vgs=10V,Id=14.5A,Rds=6mohm
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CC45 1
2 0.1U_0402_10V7K
RC203
470_0805_5%
1
CC68
10U_0805_10V4K
1
QC5B
CC69
0.1U_0402_25V6
5
1
RC204
1
2
220K_0402_5%
RC205
820K_0402_5%
2
1
4
+VSB
QC5A
2
2
SUSP
D
D
D
D
1U_0402_6.3V6K
1
2
CC73
4.7U_0805_10V4Z
FDS6676AS_SO8
RUN_ON_CPU1.5VS3
2
2N7002DW-T/R7_SOT363-6
S
S
S
G
8
7
6
5
6
2 0.1U_0402_10V7K
CC48 1
3 1
CC47 1
CC72
1
2
+1.5V
QC4
1
2
3
4
2
CC46 1
CC71
4.7U_0805_10V4Z
1
2
SUSP
SUSP
<5,36,47>
2N7002DW-T/R7_SOT363-6
A
A
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
9
of
61
5
4
3
2
1
CFG Straps for Processor
B
CFG12
CFG13
CFG14
CFG15
T24 PAD
T25 PAD
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
VCC_DIE_SENSE
VSS_DIE_SENSE
PAD T3
AH27
AH26
CFG2
1
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RC79
1K_0402_1%
RSVD28
RSVD29
RSVD30
RSVD31
L7
AG7
AE7
AK2
RSVD32
W8
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
D
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
*
1: Normal Operation; Lane #
socket pin map definition
definition matches
0:Lane Reversed
AJ31
AH31
AJ33
AH33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ26
RSVD5
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
CFG4
RC82
1K_0402_1%
IEDP@
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
AR35
AT34
AT33
AP35
AR34
Embedded Display Port Presence Strap
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
B34
A33
A34
B35
C35
RSVD51
RSVD52
AJ32
AK32
BCLK_ITP
BCLK_ITP#
AN35
AM35
*
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
J20
B18
RSVD24
RSVD25
J15
RSVD27
C
CFG6
CFG5
CLK_RES_ITP <26>
CLK_RES_ITP# <26>
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
KEY
1
<5>
<5>
<5>
<5>
CFG0
T16 PAD
T4 PAD
T5 PAD
T6 PAD
T8 PAD
T9 PAD
T11 PAD
T19 PAD
T12 PAD
T14 PAD
T20 PAD
2
<5>
1
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
RC83
1K_0402_1%
@
RC84
1K_0402_1%
@
2
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
2
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
1
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
(CFG[17:0] internal pull high 5~15K to VCCIO)
2
C
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
JCPUE
RESERVED
D
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUI
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
CFG
JCPUH
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
AT2
AT1
AR1
PAD T64
B1
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: x8, x8 - Device 1 function 1 enabled ; function 2
CFG[6:5]
@
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B
@
@
1
CFG7
2
RC85
1K_0402_1%
@
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training
A
A
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
10
of
61
5
4
+1.5V
JDDR3L
DDR_A_BS2
<7> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDRA_CLK0
DDRA_CLK0#
<7> DDRA_CLK0
<7> DDRA_CLK0#
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_MA13
DDRA_SCS1#
<7> DDRA_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
B
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
CD25
2
2
1
1
1
CD26
+0.75VS
RD9
10K_0402_5%
2
+3VS
2.2U_0603_6.3V4Z
A
0.1U_0402_10V7K
DDR_A_D58
DDR_A_D59
RD8 1
2
10K_0402_5%
GND2
BOSS2
206
208
1
2
DDR_A_D20
DDR_A_D21
+VREF_DQA_M3
DDR_A_D22
DDR_A_D23
1
RD2
1K_0402_1%
BSS138_NL_SOT23-3
QC7
3
1
@
1 RC117 2
1K_0402_1%
DDR_A_D28
DDR_A_D29
2
GND1
BOSS1
+VREF_DQA
@ 1
2
0_0402_5%
RC115
+VREF_DQA
@
DRAMRST_CNTRL_PCH
DDR_A_DQS#3
DDR_A_DQS3
@
1 RC118 2
1K_0402_1%
DDR_A_D30
DDR_A_D31
<7,26>
+1.5V
@
1
3
+VREF_DQB_M3
1
205
207
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D14
DDR_A_D15
RD10
1K_0402_1%
+VREF_DQB
QC8
BSS138_NL_SOT23-3
DDRA_CKE1
DDRA_CKE1 <7>
@ 1
2
0_0402_5%
RC116
DDR_A_MA15
DDR_A_MA14
+VREF_DQB
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
+1.5V
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
2
33P_0402_50V8K
1
CD51
2
33P_0402_50V8K
1
CD52
2
33P_0402_50V8K
1
CD53
2
33P_0402_50V8K
1
CD54
2
33P_0402_50V8K
1
CD55
2
33P_0402_50V8K
+1.5V
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
RD6
1K_0402_1%
DDRA_ODT1 <7>
+VREF_CAA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_D44
DDR_A_D45
1
CD50
DDRA_CLK1 <7>
DDRA_CLK1# <7>
+VREF_CAA
DDR_A_D38
DDR_A_D39
C
RD11
1K_0402_1%
RD7
1K_0402_1%
CD15
1
2
CD16
1
please place these caps near the
reference power plane of CMD/AD
B
0.1U_0402_10V7K
DDR_A_D40
DDR_A_D41
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
D
RD1
1K_0402_1%
Intel DDR Vref M3
SM_DRAMRST# <7,12>
2.2U_0603_6.3V4Z
DDR_A_D34
DDR_A_D35
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
SM_DRAMRST#
D
C
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
+1.5V
DDR_A_D12
DDR_A_D13
S
DDRA_CKE0
<7> DDRA_CKE0
<7>
G
DDR_A_D26
DDR_A_D27
DDR_A_MA[0..15]
DDR_A_D6
DDR_A_D7
D
DDR_A_D24
DDR_A_D25
<7>
<7>
G
DDR_A_D18
DDR_A_D19
DDR_A_D[0..63]
S
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#0
DDR_A_DQS0
2
DDR_A_D16
DDR_A_D17
<7>
DDR_A_DQS#[0..7]
1
DDR_A_D10
DDR_A_D11
DDR_A_DQS[0..7]
2
DDR_A_DQS#1
DDR_A_DQS1
Close to JDDRL.1
DDR3 SO-DIMM A
Reverse Type
2
DDR_A_D8
DDR_A_D9
DDR_A_D4
DDR_A_D5
2
DDR_A_D2
DDR_A_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
Layout Note:
Place near JDDRL
close to JDDRL.126
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA
Layout Note:
Place near JDDRL1.203 and 204
+1.5V
+1.5V
DDR_A_D52
DDR_A_D53
CD7
CD8
DDR_A_D54
DDR_A_D55
CD9
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
1
+
2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
1
2
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
D
CD2
DDR_A_D0
DDR_A_D1
1
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
2
CD1
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
1
+VREF_DQA
3
2
+1.5V
+0.75VS
2 390U_2.5V_M_R10
1
2 10U_0603_6.3V6M
1
2 10U_0603_6.3V6M
CD10 1
2 10U_0603_6.3V6M
CD11 1
2 10U_0603_6.3V6M
CD12 1
2 10U_0603_6.3V6M
CD13 1
2 10U_0603_6.3V6M
CD20 1
2 0.1U_0402_10V7K
CD17 1
2 0.1U_0402_10V7K
CD18 1
2 0.1U_0402_10V7K
CD19 1
2 0.1U_0402_10V7K
CD56 1
2 10U_0603_6.3V6M
CD24 2
1 1U_0402_6.3V6K
CD21 2
1 1U_0402_6.3V6K
CD22 2
1 1U_0402_6.3V6K
CD23 2
1 1U_0402_6.3V6K
A
PM_SMBDATA
PM_SMBCLK
PM_SMBDATA <12,26,36,46>
PM_SMBCLK <12,26,36,46>
+0.75VS
Compal Secret Data
2011/12/14
Issued Date
LCN_DAN06-K4406-0103
@
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
11
of
61
A
B
+1.5V
C
D
E
+1.5V
JDDR3H
DDR_B_D2
DDR_B_D3
2
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
Close to JDDRH.1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDRB_CKE0
<7> DDRB_CKE0
2
DDR_B_BS2
<7> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDRB_CLK0
DDRB_CLK0#
<7> DDRB_CLK0
<7> DDRB_CLK0#
DDR_B_MA10
DDR_B_BS0
<7> DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
<7> DDR_B_WE#
<7> DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#
<7> DDRB_SCS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
3
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
RD14 1
2
10K_0402_5%
4
+3VS
2.2U_0603_6.3V4Z
1
@
CD48
2
1
1 RD15
2
10K_0402_5%
CD49
2
0.1U_0402_10V7K
+0.75VS
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_B_D6
DDR_B_D7
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_D12
DDR_B_D13
SM_DRAMRST#
DDR_B_D[0..63]
<7>
<7>
<7>
DDR_B_MA[0..15]
1
<7>
SM_DRAMRST# <7,11>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1
DDRB_CKE1 <7>
DDR_B_MA15
DDR_B_MA14
2
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1 <7>
DDRB_CLK1# <7>
+1.5V
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
RD12
1K_0402_1%
DDRB_ODT1 <7>
+VREF_CAB
+VREF_CAB_DIMMB
DDR_B_D36
DDR_B_D37
RD13
1K_0402_1%
CD46
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
1
2
CD47
0.1U_0402_10V7K
DDR_B_D40
DDR_B_D41
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_B_DQS#0
DDR_B_DQS0
2.2U_0603_6.3V4Z
DDR_B_D34
DDR_B_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Reverse Type
DDR3 SO-DIMM B
DDR_B_D4
DDR_B_D5
1
3
2
Layout Note:
Place near JDDRH
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB
Layout Note:
Place near JDDRH.203 and 204
Close to JDDRH.126
+1.5V
DDR_B_D52
DDR_B_D53
+1.5V
@
CD31 1
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+
2
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
CD27
0.1U_0402_10V7K
2.2U_0603_6.3V4Z
1
1
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
CD28
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
+VREF_DQB
+0.75VS
2 330U_B2_2.5VM_R15M
CD41 1
2 10U_0603_6.3V6M
CD36 1
2 10U_0603_6.3V6M
CD37 1
2 10U_0603_6.3V6M
CD38 1
2 10U_0603_6.3V6M
CD39 1
2 10U_0603_6.3V6M
CD40 1
2 10U_0603_6.3V6M
CD33 1
2 0.1U_0402_10V7K
CD29 1
2 0.1U_0402_10V7K
CD30 1
2 0.1U_0402_10V7K
CD32 1
2 0.1U_0402_10V7K
CD57 1
2 10U_0603_6.3V6M
CD45 2
1 1U_0402_6.3V6K
CD42 2
1 1U_0402_6.3V6K
CD43 2
1 1U_0402_6.3V6K
CD44 2
1 1U_0402_6.3V6K
4
PM_SMBDATA
PM_SMBCLK
PM_SMBDATA <11,26,36,46>
PM_SMBCLK <11,26,36,46>
+0.75VS
Compal Secret Data
2011/12/14
Issued Date
FOX_AS0A626-UASN-7F_204P
@
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HG
Date:
A
B
C
D
Sheet
E
12
of
61
A
B
C
D
E
PCIE_GTX_C_CRX_P[0..15]
<6> PCIE_GTX_C_CRX_P[0..15]
UV4A
2
1
OVERT#_VGA
HDCP_SCL
HDCP_SDA
HDMI_HPD <24,28,30>
0_0402_5%
DHDMI@
RV606
VGA_CRT_DATA
AJ26
AK26
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
DACA_HSYNC
DACA_VSYNC
AM9 VGA_CRT_HSYNC
AN9 VGA_CRT_VSYNC
0.1U_0402_10V7K
1
1
CV218
0.1U_0402_10V7K
DIS@
2
2
I2CC_SCL
I2CC_SDA
R2
R3
I2CS_SCL
I2CS_SDA
T4
T3
VGA_CRT_CLK
VGA_CRT_DATA
CV225
DIS@
2
1
CV224
DIS@
2
CV223
DIS@
110804 check with NV pull down 10k if DAC unused
VGA_ENBKL
HDCP_SCL
HDCP_SDA
VGA_BL_PWM
+PLLVDD
VGA_EDID_CLK <22>
VGA_EDID_DATA <22>
PLLVDD
AD8
SP_PLLVDD
AE8
45mA
VID_PLLVDD
AD7
PEX_RST_N
PEX_TERMP
XTAL_IN
XTAL_OUT
H3
H2
XTAL_OUTBUFF
XTAL_SSIN
J4
H1
1 DIS@ 2
RV20
150_0402_1%
1 DIS@ 2
RV21
150_0402_1%
DIS@
1
2
RV23
150_0402_1%
2
CV225
10K_0402_5%
OPT@
LVDS
1
SMB_CLK_GPU
SMB_DATA_GPU
2
CV1971 under GPU
close to ball : ADB
45mA
VGA_CRT_B
1
2
+3VS_DGPU
MBK1608221YZF_2P
DIS@
1
CV227
CV222
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DIS@
@
2
2
Internal Thermal Sensor
60mA
1
1
0.1U_0402_10V7K
VGA_CRT_CLK <23>
VGA_CRT_DATA <23>
VGA_EDID_CLK
VGA_EDID_DATA
1U_0402_6.3V6K
1
1
2
1
2
2 DIS@ 1
RV2
10K_0402_5%
2 DIS@ 1
RV3
10K_0402_5%
+1.05VS_DGPU
LV10
1
2
BLM18PG330SN1D_0603
1
2
CV53
10U_0603_6.3V6M
+DACA_VDD
+DACA_VREF
DACA_RSET
VGA_CRT_G
LV3
CV47
22U_0805_6.3V6M
I2CB_SCL
I2CB_SDA
R7
R6
120mA
CV109
4.7U_0603_6.3V6K
R4
R5
VGA_CRT_R
VGA_CRT_HSYNC <23>
VGA_CRT_VSYNC <23>
RV27
124_0402_1%
DIS@
I2CA_SCL
I2CA_SDA
2
2.2K_0402_5%
2
2.2K_0402_5%
1
Close to GPU
CV197
0.1U_0402_10V7K
AG10
AP9
AP8
VGA_CRT_R <23>
VGA_CRT_G <23>
VGA_CRT_B <23>
1
HDMI_HPD_VGA
2
RV608
1
100K_0402_5%
+PLLVDD
LV15
BLM18PG181SN1D_2P
1
2
+GPU_PLLVDD
1
XTALIN
XTAL_OUT
2
XTAL_OUTBUFF
XTAL_SSIN
N13P-PES-A2_FCBGA908
N13PGSR1@
1
2
1
2
1
2
1
2
+1.05VS_DGPU
1
2
CV44
10U_0603_6.3V6M
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
AK9
AL10
AL9
CV43
22U_0805_6.3V6M
AL13
AK13
AK12
PLTRST_VGA_R# AJ12
2
0_0402_5%
AP29
2
2.49K_0402_1%
HDMI_HPD_VGA
EC GPS_DOWN# must be OD\Low
to avoid leakage on OPT SKU.
CV42
4.7U_0603_6.3V6K
1
RV18
1
RV19
<29> PLTRST_VGA#
GPU_EVENT
GPS_DOWN# <44>
VGA_VID_5 <58>
CV41
0.1U_0402_10V7K
@
PEX_TSTCLK_OUT
1
2
RV16
200_0402_1% PEX_TSTCLK_OUT#
3
VGA_VID_0 <58>
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_VDD
DACA_VREF
DACA_RSET
1
RV13
1
RV14
RV7
GPS_DOWN#
VGA_VID_0
GPS_DOWN#
VGA_VID_5
CV40
0.1U_0402_10V7K
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
120mA
1
RV32
1
RV10
1
RV37
1
RV11
1
RV12
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
RV6
VGA_EDID_DATA
CV38
0.1U_0402_10V7K
PEX_WAKE_N
VGA_EDID_CLK
1
AJ11
PCIE_CTX_C_GRX_N[0..15]
<6> PCIE_CTX_C_GRX_N[0..15]
2
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
GPIO
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
PCIE_CTX_C_GRX_P[0..15]
<6> PCIE_CTX_C_GRX_P[0..15]
OVERT#_VGA
GPU_EVENT
RV45
10K_0402_5%
2
1
<26> CLK_PCIE_VGA
<26> CLK_PCIE_VGA#
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
VGA_VID_4 <58>
VGA_VID_3 <58>
VGA_BL_PWM <22>
VGA_ENVDD <22>
VGA_ENBKL <22>
VGA_VID_1 <58>
VGA_VID_2 <58>
RV52
10K_0402_5%
2
1
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
VGA_VID_4
VGA_VID_3
VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
VGA_VID_1
VGA_VID_2
VGA_CRT_CLK
DACs
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
+3VS_DGPU
PCIE_GTX_C_CRX_N[0..15]
<6> PCIE_GTX_C_CRX_N[0..15]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
I2C
CV35 1
CV37 1
CV39 1
CV45 1
CV93 1
CV98 1
CV94 1
CV99 1
CV107 1
CV105 1
CV199 1
CV108 1
CV200 1
CV202 1
CV201 1
CV204 1
CV203 1
CV205 1
CV207 1
CV206 1
CV209 1
CV208 1
CV210 1
CV212 1
CV211 1
CV214 1
CV213 1
CV215 1
CV217 1
CV216 1
CV219 1
CV220 1
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
Part 1 of 7
CLK
2
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
PCI EXPRESS
1
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
3
CV38,CV40, CV41 under GPU
close to ball : AE8,AD7
+3VS_DGPU
4
0_0402_5%
1 RV182 2
1
3
S
2
2
CLK_REQ_GPU#
GND
SMB_CLK_GPU
2
4
CV48
CV49
18P_0402_50V8J
18P_0402_50V8J
27MHZ_16PF_7V27000011
1
SMB_DATA_GPU
2
5
RV24
2.2K_0402_5%
OPT@
4
2
1
XTAL_OUT
OPT@
QV1A
1
OPT@
QV1B
3
EC_SMB_CK2 <26,44,45>
2N7002DW-T/R7_SOT363-6
6
EC_SMB_DA2 <26,44,45>
2N7002DW-T/R7_SOT363-6
+3VS_DGPU
4
CV46
0.1U_0402_10V7K
SMB_CLK_GPU
EC_SMB_CK2
1 DIS@ 2
RV35
0_0402_5%
SMB_DATA_GPU 1 DIS@ 2
EC_SMB_DA2
RV36
0_0402_5%
@
2
G
3
3
1
2
1
D
2N7002_SOT23-3
QV3
1
GND
RV179
10K_0402_5%
1
<26> CLK_REQ_VGA#
1
1
RV22
2.2K_0402_5%
OPT@
YV3
XTALIN
2
2
+3VS_DGPU
+3VS_DGPU
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
A
B
C
D
Rev
B
4019HG
Sheet
E
13
of
61
A
VRAM Interface
MDA[15..0]
<19> MDA[15..0]
<19> MDA[31..16]
<18> MDA[47..32]
<18> MDA[63..48]
MDA[31..16]
<20> MDC[15..0]
MDA[47..32]
<20> MDC[31..16]
MDA[63..48]
<21> MDC[47..32]
MDC[15..0]
MDC[31..16]
MDC[47..32]
MDC[63..48]
<21> MDC[63..48]
UV4C
<19> DQSA[3..0]
<18> DQSA[7..4]
<19> DQSA#[3..0]
<18> DQSA#[7..4]
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
M31
G31
E33
M33
AE31
AK30
AN33
AF33
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
M30
H30
E34
M34
AF30
AK31
AM34
AF32
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_CMD_RFU0
FBA_CMD_RFU1
R32
AC32
FBA_DEBUG0
FBA_DEBUG1
R28 FBA_DEBUG0
AC28 FBA_DEBUG1
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
R30
R31
AB31
AC31
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
RV57
@
2
@
2
RV59
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
+VRAM_1.5VS
60.4_0402_1%
1
1
60.4_0402_1%
CLKA0
CLKA0#
CLKA1
CLKA1#
<19>
<19>
<18>
<18>
<20> DQMC[3..0]
<21> DQMC[7..4]
10K_0402_1%
FB_CLAMP
35mA
E1
FB_DLL_AVDD
K27
66mA FBA_PLL_AVDD
U27
FB_CLAMP
1
RV74
1
+FB_AVDD
1
FB_VREF
<20> DQSC[3..0]
2
H26
2
2
CMDC[30..0]
Part 3 of 7
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
<21> DQSC[7..4]
<20> DQSC#[3..0]
<21> DQSC#[7..4]
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
E11
E3
A3
C9
F23
F27
C30
A24
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7
D10
D5
C3
B9
E23
E28
B30
A23
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7
D9
E4
B2
A9
D22
D28
A30
B23
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7
MEMORY INTERFACE B
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
FBB_CMD_RFU0
FBB_CMD_RFU1
C12
C20
FBB_DEBUG0
FBB_DEBUG1
G14
G20
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
D12
E12
E20
F20
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
F8
E8
A5
A6
D24
D25
B27
C27
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
D6
D7
C6
B6
F26
E26
A26
A27
+VRAM_1.5VS
RV58
FBB_DEBUG0 2
@
FBB_DEBUG1 2
@
RV60
60.4_0402_1%
1
1
60.4_0402_1%
1
CLKC0
CLKC0#
CLKC1
CLKC1#
66mA
FBB_PLL_AVDD
<20>
<20>
<21>
<21>
+FB_AVDD
H17
1
2
+1.05VS_DGPU
BLM18PG330SN1D_0603
LV5
1
2
1
2
N13PGSR1@
<20,21>
CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30
CV52
0.1U_0402_10V7K
<18> DQMA[7..4]
P30
F31
F34
M32
AD31
AL29
AM32
AF34
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
CV50
0.1U_0402_10V7K
<19> DQMA[3..0]
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
CV51
0.1U_0402_10V7K
1
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
MEMORY INTERFACE
A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
1
2
N13PGSR1@
12mil
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title
Date:
A
+FB_AVDD
Compal Secret Data
+FB_AVDD
100mA
CV233
22U_0805_6.3V6M
CMDA[30..0] <18,19>
Part 2 of 7
CV86
1U_0402_6.3V6K
UV4B
Rev
B
4019HG
Sheet
14
of
61
5
4
3
2
Physical
Strapping pin Power Rail
D
UV4D
ROM_SO
+3VS_DGPU
1
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit0
Logical
Strapping Bit1
XCLK_417 for GL FB_0_BAR_SIZE for GL SMB_ALT_ADDR
, FB[1]
, FB[0]
VGA_DEVICE
SLOT_CLK_CFG for GL PEX_PLLEN_TERM
PCI_DEVID[5]
RAMCFG[0]
RAMCFG[1]
ROM_SCLK
+3VS_DGPU
PCI_DEVID[4]
SUB_VENDOR
ROM_SI
+3VS_DGPU
RAMCFG[3]
RAMCFG[2]
STRAP0
STRAP1
+3VS_DGPU
USER[3]
USER[2]
USER[1]
USER[0]
+3VS_DGPU
3GIO_PADCFG[3]
3GIO_PADCFG[2]
3GIO_PADCFG[1]
3GIO_PADCFG[0]
D
Part 4 of 7
B
AG3
AG2
VGA_HDMI_CLK
VGA_HDMI_DATA
<24> VGA_HDMI_CLK
<24> VGA_HDMI_DATA
DHDMI@
VGA_HDMI_CLK
1
2
4.7K_0402_5%
RV151
DHDMI@
VGA_HDMI_DATA
1
2
RV152
4.7K_0402_5%
+VGA_CORE
N13P-GL ES2
0x0DE9
101001
N13P-GS ES1
0x0FDB
011011
Pull-down to Gnd
0000
10K
1001
0001
15K
1010
0010
20K
1011
0011
25K
1100
2
0_0402_5%
0100
30K
1101
0101
35K
1110
2
0_0402_5%
VGA_VSS_SENSE <58>
0110
45K
1111
0111
MULTI LEVEL STRAPS
RV17
100_0402_1%
Straps
C
+3VS_DGPU
+3VS_DGPU
TEST
TESTMODE
AK11
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
AM10
AM11
AP12
AP11
AN11
SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
AB3
AB4
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
H6
H4
H5
H7
ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO
1
RV84
BUFRST_N
L2
CEC
L3
MULTI_STRAP_REF0_GND
J1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
J2
J7
J6
J5
J3
THERMDP
THERMDN
K3
K4
2 10K_0402_5%
2
10K_0402_5%
RV85 @ 10K_0402_5%
1
2
PAD
PAD
PAD
PAD
TV4
TV1
TV2
TV3
@
@
@
@
STRAP0
STRAP1
STRAP2
+3VS_DGPU
RV73
4.99K_0402_1%
N13PGS@
GENERAL
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
RV82 1
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST
RV153
1
10K_0402_5%
2
RV86 1N13PGL@ 2 10K_0402_5%
MULTI_STRAP_REF0_GND
1
RV87
+3VS_DGPU
2
40.2K_0402_1%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
N13PGSR1@
For X76
Hynix (900MHZ)
64MX16 H5TQ1G63DFR-11C
SA000041S20
1GB
0010
Hynix (900MHZ)
128MX16 H5TQ2G63BFR-11C
SA00003YO00
2GB
0110
RV77 PD 34.8k
(SD034348280)
Hynix (900MHZ)
128MX16 H5TQ2G63DFR-11C
SA00003YO70
2GB
0101
RV77 PD 30k
(SD034300280)
Samsung (900MHZ)
64MX16 K4W1G1646G-BC11
SA00004GS00
1GB
0011
RV77 PD 20K
(SD034200280)
Samsung (900MHZ)
128M16 K4W2G1646C-HC11
SA000047Q00
2GB
0111
RV77 PD 45.3K
(SD034453280)
Samsung (900MHZ)
128M16 K4W2G1646E-HC11
SA000047QC0
RV77 PD 15K
2011/12/14
2012/12/31
Deciphered Date
Title
Date:
3
A
2GB
Custom
4
B
(SD034150280)
Compal Secret Data
Issued Date
ROM_SI
ROM_SO
ROM_SCLK
STRAP3
STRAP4
2
1
RV70
4.99K_0402_1%
N13PGS@
1
1
2
15K_0402_1%
RV53
N13PGL@
1
RV81
VGA_VCC_SENSE <58>
N13PGS@
2
1
RV78
10K_0402_1%
FB_GND_R
1
RV80
2N13PGL@ 1
RV89
10K_0402_1%
L5
GCORE_SEN_R
010010
@ 1
2
RV69
4.99K_0402_1%
L4
0x0FD2
N13P-GS QS
A
5
DP_PLL_VDD33V
Pull-up to +3VS
_DGPU
1000
Resistor Values
biit5 to bit0
5K
2
AK3
AK2
AF3
AF2
+3VS_DGPU
Device ID
SKU
PCIE_SPEED_CHANGE_GEN3 PCIE_MAX_SPEED
@ 1
2
RV77
34.8K_0402_1%
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
RESERVED
2
1
@
RV68
10K_0402_1%
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
+3VS_DGPU
2 RV76
1
45.3K_0402_1%
N13PGS@
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
STRAP4
2 RV98
1
4.99K_0402_1%
GSDIS@
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
PCI_DEVID[0]
SOR0_EXPOSED
N13PGL@
2
1
RV79
10K_0402_1%
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
PCI_DEVID[1]
SOR1_EXPOSED
2
RV75 1
4.99K_0402_1%
GSOPT@
VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-
<24> VGA_HDMI_TX2+
<24> VGA_HDMI_TX2<24> VGA_HDMI_TX1+
<24> VGA_HDMI_TX0<24> VGA_HDMI_CLK+
<24> VGA_HDMI_CLK-
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
GND_SENSE
LVDS/TMDS
C
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
PCI_DEVID[2]
SOR2_EXPOSED
RV15
100_0402_1%
VDD_SENSE
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
PCI_DEVID[3]
SOR3_EXPOSED
@ 1
2
RV65
4.99K_0402_1%
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
+3VS_DGPU
+3VS_DGPU
N13PGL@
2
1
RV73
45.3K_0402_1%
N13PGS@
1
2
15K_0402_1%
RV54
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
STRAP2
STRAP3
2
1
RV64
45.3K_0402_1%
VGA_TZCLK+
VGA_TZCLKVGA_TZOUT0+
VGA_TZOUT0VGA_TZOUT1+
VGA_TZOUT1VGA_TZOUT2+
VGA_TZOUT2-
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
@ 1
2
RV72
4.99K_0402_1%
<22> VGA_TZCLK+
<22> VGA_TZCLK<22> VGA_TZOUT0+
<22> VGA_TZOUT0<22> VGA_TZOUT1+
<22> VGA_TZOUT2-
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
N13P-GL/GS/GT/LP
ROM_SI
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
2
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
1
VGA_TXCLK+
VGA_TXCLKVGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2+
VGA_TXOUT2-
NC
<22> VGA_TXCLK+
<22> VGA_TXCLK<22> VGA_TXOUT0+
<22> VGA_TXOUT0<22> VGA_TXOUT1+
<22> VGA_TXOUT1<22> VGA_TXOUT2+
<22> VGA_TXOUT2-
2
Rev
B
4019HG
Sheet
1
15
of
61
2
1
125mA
FB_CAL_PD_VDDQ J27
1
40.2_0402_1%
1
RV605
FB_CAL_PU_GND H27
2
42.2_0402_1%
1
RV609
FB_CAL_TERM_GND H25
2
51.1_0402_1%
2
0.1U_0402_10V7K
AG12
CV56
4.7U_0603_6.3V6K
CV60
22U_0805_6.3V6M
CV68
22U_0805_6.3V6M
CV78
22U_0805_6.3V6M
CV67
10U_0603_6.3V6M
CV77
10U_0603_6.3V6M
CV82
4.7U_0603_6.3V6K
CV81
4.7U_0603_6.3V6K
N13PGS@
2
1
Near GPU
1
2
1
2
+1.05VS_DGPU
LV7
2
1
BLM18PG121SN1D_0603
N13PGL@
PCIE2.0
PCIE3.0
IFPA_IOVDD
IFPB_IOVDD
+IFPAB_IOVDD
100mA IFPC_PLLVDD
AF7
AF8
+IFPC_PLLVDD
IFPC_RSET
IFPC_IOVDD
AF6
+IFPC_IOVDD
IFPD_PLLVDD
IFPD_RSET
AG7
AN2
+IFPD_PLLVDD
IFPD_IOVDD
AG6
+IFPD_IOVDD
200mA IFPEF_PLVDD
AB8
AD6
+IFPEF_PLLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD
AC7
AC8
+IFPEF_IOVDD
RV90 1 @
1
2 1K_0402_5%
2
+3VS_DGPU
FB_CAL_TERM_GND
RV103 1
DHDMI@
2 1K_0402_5%
1
Near GPU
1
2
1
2
200mA
1
2
1
2
1
2
+IFPEF_PLLVDD
LV8
1
2
MMZ1608D301BT_0603
DHDMI@
CV236
DHDMI@
2
+IFPEF_PLLVDD
1
CV237
DHDMI@
2
1
CV235
DHDMI@
2
1
CV284
DHDMI@
2
1
CV285
DHDMI@
2
1
2
CV286
10K_0402_5%
IHDMI@
CV286
DHDMI@
B
+IFPEF_IOVDD
570mA
CV300
DHDMI@
2
1
2
CV299
DHDMI@
0.1U_0402_10V7K
CV287
DHDMI@
2
1
0.1U_0402_10V7K
CV282
DHDMI@
2
1
0.1U_0402_10V7K
1
0.1U_0402_10V7K
CV281
DHDMI@
2
1U_0402_6.3V6K
CV283
DHDMI@
2
+IFPEF_IOVDD
1
1
2
CV234
DHDMI@
RV297
10K_0402_5%
CV234
10K_0402_5%
IHDMI@
1
1
2
+IFPC_PLLVDD
1
2
MBK1608221YZF_2P
DHDMI@
4.7U_0603_6.3V6K
+IFPD_PLLVDD
4.7U_0603_6.3V6K
+IFPD_PLLVDD
+IFPC_PLLVDD
1
+IFPD_IOVDD
2
+IFPD_IOVDD
RV295
10K_0402_5%
A
RV296
10K_0402_5%
2
+IFPC_IOVDD
1
2
+IFPC_IOVDD
1
CV106
1
DIS@
2
+IFPAB_IOVDD
0.1U_0402_10V7K
CV232
1
DIS@
2
Under GPU
Issued Date
Compal Secret Data
CV104
10K_0402_5%
OPT@
2011/12/14
2012/12/31
Deciphered Date
Title
Date:
5
C
N13P-GL N13M-GS
N13P-GS/GT N13E-GE
+3VS_DGPU
N13PGSR1@
230mA
0.1U_0402_10V7K
CV104
1
DIS@
DIS@
2
2
Under GPU
RV298
10K_0402_5%
1U_0402_6.3V6K
CV103
1
A
2
85mA
+VDD33
J8
K8
L8
M8
1
LV9
1
4.7U_0603_6.3V6K
LV14
BLM18PG181SN1D_2P
Under GPU
1
2
CV102
DIS@
2
2
RV101
0_0603_5%
1
2
CV198 0.1U_0402_10V7K
+PEX_PLLVDD
AG26
+1.05VS_DGPU
0.1U_0402_10V7K
CV101
DIS@
2
1
Near GPU
DIS@
2
CV80,CV198 Under GPU
close to ball
FB_CAL_PD_VDDQ
CV101
10K_0402_5%
OPT@
+3VS_DGPU
420mA
+PEX_PLL_HVDD
AH12
+IFPAB_PLLVDD
144mA
CV76
4.7U_0603_6.3V6K
2
AG8
AG9
FB_CAL_PU_GND
CV75
1U_0402_6.3V6K
1
AH8
AJ8
72mA
2
1
CV97
4.7U_0603_6.3V6K
VDD33_0
VDD33_1
VDD33_2
VDD33_3
2
1
CV96
1U_0402_6.3V6K
85mA
2
1
+1.05VS_DGPU
+3VS_DGPU
125mA
1U_0402_6.3V6K
CV100
DIS@
2
1
2
Near GPU
+IFPAB_PLLVDD
1
4.7U_0603_6.3V6K
2
1
4.3_0603_5%
DIS@
2
1
CV95
0.1U_0402_10V7K
FB_GND_SENSE
Under GPU
LV6
1
0.1U_0402_10V7K
PEX_PLLVDD
2
1
CV89
4.7U_0603_6.3V6K
150mA
2
1
CV88
1U_0402_6.3V6K
PEX_SVDD_3V3
1
CV92
0.1U_0402_10V7K
F2
2
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
1
CV80
210mA
1
CV91
0.1U_0402_10V7K
FB_VDDQ_SENSE
B
Near GPU
2
0.1U_0402_10V7K
+VRAM_1.5VS
F1
total 6600mA
Design guide page.74
0.1U_0402_10V7K
210mA
PEX_PLL_HVDD
Near GPU
CV74
1U_0402_6.3V6K
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
115mA
+1.05VS_DGPU
1
midway between GPU
and Power supply
Under GPU
AG19
AG21
AG22
AG24
AH21
AH25
CV87
0.1U_0402_10V7K
2
3300mA
IFPAB_PLLVDD
IFPAB_RSET
2
RV96
2
CV90
0.1U_0402_10V7K
2
1
@ CV85
22U_0805_6.3V6M
2
1
@ CV231
22U_0805_6.3V6M
2
1
CV243
10U_0603_6.3V6M
2
1
CV244
10U_0603_6.3V6M
CV84
10U_0603_6.3V6M
C
CV83
10U_0603_6.3V6M
2
1
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
1U_0402_6.3V6K
2
Near GPU
1
2
1
D
3300 mA
4.7U_0603_6.3V6K
2
1
CV73
0.1U_0402_10V7K
2
1
CV72
0.1U_0402_10V7K
2
1
CV71
0.1U_0402_10V7K
2
1
CV79
0.1U_0402_10V7K
2
1
CV70
1U_0402_6.3V6K
1
CV69
4.7U_0603_6.3V6K
Under GPU
7200 mA
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
4.7U_0603_6.3V6K
2
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
POWER
2
1
CV66
0.1U_0402_10V7K
2
1
CV65
0.1U_0402_10V7K
2
1
CV64
0.1U_0402_10V7K
1
CV63
0.1U_0402_10V7K
2
CV62
1U_0402_6.3V6K
CV61
4.7U_0603_6.3V6K
2
1
2
1
Part 5 of 7
Under GPU
D
1
1
CV55
1U_0402_6.3V6K
2
UV4E
+VRAM_1.5VS
CV54
1U_0402_6.3V6K
Near GPU
1
+1.05VS_DGPU
midway between GPU
and Power supply
Under GPU
CV59
22U_0805_6.3V6M
3
CV58
10U_0603_6.3V6M
4
CV57
10U_0603_6.3V6M
5
4
3
2
Rev
B
4019HG
Sheet
1
16
of
61
5
4
3
2
1
+VGA_CORE
UV4F
+VGA_CORE
UV4G
B
A
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
Part 7 of 7
50A
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
POWER
C
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
VGA_CORE cap. ought to power pate
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
D
GND
Part 6 of 7
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
U1
U2
U3
U4
U5
U6
U7
U8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
V1
V2
V3
V4
V5
V6
V7
V8
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
W2
W3
W4
W5
W7
W8
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
D
C
B
N13PGSR1@
A
Issued Date
N13PGSR1@
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Date:
5
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
4
3
2
Rev
B
4019HG
Sheet
1
17
of
61
5
4
3
2
1
VRAM DDR3 chips (1GB)
Mode D
Address
64Mx16 DDR3 *8==>1GB
0..31
32..63
CS0_L#
CMD0
CMD1
D
@
UV10
2
CMDA12
CMDA27
CMDA26
+VRAM_1.5VS
BA0
BA1
BA2
J7
K7
K9
CK
CK
CKE/CKE0
2
CLKA1
CLKA1#
CMDA19
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
F3
C7
RV119
1K_0402_1%
1
+MEM_VREF_DQ1
1
RV108
1K_0402_1%
CV301
0.01U_0402_25V7K
DQSA#4
DQSA#7
E7
D3
G3
B7
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
DQSL
DQSU
2
2
CMDA5
T2
ZQ2
DQMA5
DQMA6
2
CLKA1
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
1
<14>
2
RV126
160_0402_1%
<14>
E7
D3
DQSA#5
DQSA#6
G3
B7
CMDA5
T2
ZQ3
L8
RV124
243_0402_1%
J1
L1
J9
L9
2
J1
L1
J9
L9
RV123
243_0402_1%
B
F3
C7
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
CLKA1#
CK
CK
CKE/CKE0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
B2
D9
G7
K2
K8
N1
N9
R1
R9
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CKE
D
CMD4
A14
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
CAS*
CS0_H#
CMD16
CMD17
+VRAM_1.5VS
CMD18
ODT_H
CMD19
CKE_H
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
C
Not Available
B
+VRAM_1.5VS
2
1
2
CV141
0.1U_0402_10V7K
2
1
CV139
0.1U_0402_10V7K
2
1
CV137
0.1U_0402_10V7K
2
1
CV138
0.1U_0402_10V7K
2
1
CV255
1U_0402_6.3V6K
2
1
CV256
1U_0402_6.3V6K
1
CV257
1U_0402_6.3V6K
CV238
10U_0603_6.3V6M
2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT_L
CMD3
96-BALL
SDRAM DDR3
+VRAM_1.5VS
1
BA0
BA1
BA2
1
ZQ/ZQ0
K1
L2
J3
K3
L3
DQSA5
DQSA6
1
L8
RESET
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
+VRAM_1.5VS
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CV278
1U_0402_6.3V6K
2
DQMA4
DQMA7
A1
A8
C1
C9
D2
E9
F1
H2
H9
J7
K7
K9
Group6
CV277
1U_0402_6.3V6K
1
DQSA4
DQSA7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
ODT/ODT0
CS/CS0
RAS
CAS
WE
CLKA1
CLKA1#
CMDA19
+VRAM_1.5VS
D7
C3
C8
C2
A7
A2
B8
A3
MDA53
MDA49
MDA55
MDA50
MDA52
MDA48
MDA54
MDA51
Group5
CV276
1U_0402_6.3V6K
+VRAM_1.5VS
K1
L2
J3
K3
L3
M2
N8
M3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44
MDA42
CV275
1U_0402_6.3V6K
CV230
0.01U_0402_25V7K
2
CMDA12
CMDA27
CMDA26
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
CV142
0.1U_0402_10V7K
1
RV106
1K_0402_1%
C
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
+MEM_VREF_CA1
M2
N8
M3
Group7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CV140
0.1U_0402_10V7K
RV107
1K_0402_1%
D7
C3
C8
C2
A7
A2
B8
A3
VREFCA
VREFDQ
CV143
0.1U_0402_10V7K
+VRAM_1.5VS
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
Group4
M8
H1
CV144
0.1U_0402_10V7K
<14,19> MDA[63..0]
MDA61
MDA59
MDA60
MDA57
MDA63
MDA56
MDA62
MDA58
+MEM_VREF_CA1
+MEM_VREF_DQ1
CV259
1U_0402_6.3V6K
MDA[63..0]
MDA39
MDA35
MDA37
MDA33
MDA38
MDA32
MDA36
MDA34
CV260
1U_0402_6.3V6K
DQSA[7..0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
CV258
1U_0402_6.3V6K
<14,19> DQSA[7..0]
DQSA#[7..0]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CV288
1U_0402_6.3V6K
<14,19> DQSA#[7..0]
CMDA[30..0]
VREFCA
VREFDQ
CMD2
1
2
1
2
CV280
1U_0402_6.3V6K
1
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
<14,19> CMDA[30..0]
M8
H1
@
CV279
1U_0402_6.3V6K
+MEM_VREF_CA1
+MEM_VREF_DQ1
DQMA[7..0]
<14,19> DQMA[7..0]
UV11
A
A
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
18
of
61
5
4
3
2
1
Mode D
Address
0..31
64Mx16 DDR3 *8==>1GB
D
UV8
DQMA[7..0]
<14,18> DQMA[7..0]
<14,18> CMDA[30..0]
CMDA[30..0]
1
+VRAM_1.5VS
2
RV62
1K_0402_1%
1
+MEM_VREF_CA0
1
RV63
1K_0402_1%
CV228
0.01U_0402_25V7K
2
2
1
+VRAM_1.5VS
2
RV105
1K_0402_1%
1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA17
MDA21
MDA18
MDA23
MDA19
MDA22
MDA16
MDA20
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA12
CMDA27
CMDA26
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CMDA3
J7
K7
K9
CK
CK
CKE/CKE0
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
F3
C7
CV229
0.01U_0402_25V7K
2
MDA12
MDA14
MDA8
MDA15
MDA9
MDA13
MDA10
MDA11
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
DQSA1
DQSA2
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
M8
H1
+MEM_VREF_DQ0
1
RV88
1K_0402_1%
DQMA1
DQMA2
E7
D3
DML
DMU
DQSA#1
DQSA#2
G3
B7
DQSL
DQSU
CMDA5
T2
B
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
Group2
+VRAM_1.5VS
2
RV110
243_0402_1%
2
<14>
MDA3
MDA4
MDA2
MDA7
MDA0
MDA5
MDA1
MDA6
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA27
MDA29
MDA25
MDA30
MDA24
MDA28
MDA26
MDA31
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFCA
VREFDQ
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA12
CMDA27
CMDA26
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CMDA3
J7
K7
K9
CK
CK
CKE/CKE0
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA0
DQSA3
F3
C7
DQSL
DQSU
DQMA0
DQMA3
E7
D3
DML
DMU
DQSA#0
DQSA#3
G3
B7
DQSL
DQSU
CMDA5
ZQ1
CLKA0#
RV111
243_0402_1%
2
1
CLKA0
RV114
160_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
M8
H1
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
Group0
Group3
+VRAM_1.5VS
CMD2
ODT_L
CMD3
CKE
CMD4
A14
CMD5
RST
A14
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
CAS*
CS0_H#
CMD16
C
CMD17
CMD18
ODT_H
CKE_H
CMD19
+VRAM_1.5VS
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
B
1
ZQ/ZQ0
Group1
+VRAM_1.5VS
RESET
L8
+MEM_VREF_CA0
+MEM_VREF_DQ0
1
ZQ0
<14>
@
swap 0329
+MEM_VREF_CA0
+MEM_VREF_DQ0
MDA[63..0]
<14,18> MDA[63..0]
C
UV9
@
DQSA#[7..0]
<14,18> DQSA#[7..0]
D
CMD1
DQSA[7..0]
<14,18> DQSA[7..0]
32..63
CS0_L#
CMD0
96-BALL
SDRAM DDR3
CMDA2
CMDA3
CMDA5
CMDA18
CMDA19
RV112 1
RV113 1
RV115 1
RV116 1
RV117 1
2
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Command Bit
Default Pull-down
ODTx
10k
10k
CKEx
DDR3
RST
10k
CS*
No Termination
96-BALL
SDRAM DDR3
+VRAM_1.5VS
1
2
1
2
1
2
1
2
CV150
0.1U_0402_10V7K
2
A
Compal Secret Data
Issued Date
1
CV149
0.1U_0402_10V7K
2
CV151
0.1U_0402_10V7K
1
CV152
0.1U_0402_10V7K
2
CV312
1U_0402_6.3V6K
1
CV313
1U_0402_6.3V6K
2
CV311
1U_0402_6.3V6K
2
1
CV241
10U_0603_6.3V6M
2
1
CV146
0.1U_0402_10V7K
2
1
CV145
0.1U_0402_10V7K
2
1
CV147
0.1U_0402_10V7K
2
1
CV148
0.1U_0402_10V7K
2
1
CV262
1U_0402_6.3V6K
A
2
1
CV310
1U_0402_6.3V6K
2
1
CV261
1U_0402_6.3V6K
1
CV240
10U_0603_6.3V6M
+VRAM_1.5VS
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
19
of
61
5
4
3
2
1
Mode D
Address
32..63
0..31
CS0_L#
CMD0
CMD1
64Mx16 DDR3 *8==>1GB
D
DQSC[7..0]
<14,21> DQSC[7..0]
DQSC#[7..0]
<14,21> DQSC#[7..0]
UV12
+MEM_VREF_CA2
+MEM_VREF_DQ2
<14,21> MDC[63..0]
CMDC[30..0]
1
+VRAM_1.5VS
2
RV121
1K_0402_1%
1
+MEM_VREF_CA2
1
2
1
+VRAM_1.5VS
RV128
1K_0402_1%
2
MDC8
MDC12
MDC11
MDC13
MDC9
MDC14
MDC10
MDC15
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC18
MDC20
MDC17
MDC22
MDC16
MDC23
MDC19
MDC21
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDC12
CMDC27
CMDC26
M2
N8
M3
BA0
BA1
BA2
CLKC0
CLKC0#
CMDC3
J7
K7
K9
CMDC2
CMDC0
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC1
DQSC2
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
Group1
Group2
+VRAM_1.5VS
CK
CK
CKE/CKE0
F3
C7
+MEM_VREF_CA2
+MEM_VREF_DQ2
+VRAM_1.5VS
1
DQMC1
DQMC2
E7
D3
CV303
0.01U_0402_25V7K
2
2
DML
DMU
DQSC#1
DQSC#2
G3
B7
CMDC5
T2
RESET
ZQ4
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
E3
F7
F2
F8
H3
H8
G2
H7
MDC3
MDC7
MDC1
MDC4
MDC2
MDC6
MDC0
MDC5
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC26
MDC31
MDC25
MDC30
MDC27
MDC28
MDC24
MDC29
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VREFCA
VREFDQ
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDC12
CMDC27
CMDC26
M2
N8
M3
BA0
BA1
BA2
CLKC0
CLKC0#
CMDC3
J7
K7
K9
CMDC2
CMDC0
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC0
DQSC3
F3
C7
Group0
Group3
ODT/ODT0
CS/CS0
RAS
CAS
WE
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
DQMC0
DQMC3
E7
D3
DQSC#0
DQSC#3
G3
B7
CMDC5
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
ZQ5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
DML
DMU
DQSL
DQSU
CKE
CMD4
A14
D
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
CAS*
CS0_H#
CMD16
+VRAM_1.5VS
CK
CK
CKE/CKE0
ODT_L
CMD3
CMD17
ODT_H
CMD18
+VRAM_1.5VS
CMDC2
CMDC3
CMDC5
CMDC18
CMDC19
RV134 1
RV135 1
RV136 1
RV137 1
RV138 1
2
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
C
CKE_H
CMD19
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
B
1
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
B
1
CLKC0
RV133
243_0402_1%
2
2
RV132
243_0402_1%
<14>
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
M8
H1
+MEM_VREF_DQ2
1
RV122
1K_0402_1%
E3
F7
F2
F8
H3
H8
G2
H7
VREFCA
VREFDQ
CV302
0.01U_0402_25V7K
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
M8
H1
MDC[63..0]
<14,21> CMDC[30..0]
RV120
1K_0402_1%
@
swap 0329
DQMC[7..0]
<14,21> DQMC[7..0]
C
UV13
@
CMD2
96-BALL
SDRAM DDR3
Default Pull-down
ODTx
DDR3
10k
10k
CKEx
RST
10k
CS*
No Termination
96-BALL
SDRAM DDR3
2
RV140
160_0402_1%
Command Bit
<14>
CLKC0#
+VRAM_1.5VS
+VRAM_1.5VS
2
1
2
1
CV158
0.1U_0402_10V7K
2
1
CV157
0.1U_0402_10V7K
2
1
CV159
0.1U_0402_10V7K
2
1
CV160
0.1U_0402_10V7K
2
1
CV267
1U_0402_6.3V6K
2
1
CV268
1U_0402_6.3V6K
2
1
CV266
1U_0402_6.3V6K
1
10U_0603_6.3V6M
2
CV246
2
1
CV154
0.1U_0402_10V7K
2
1
CV153
0.1U_0402_10V7K
2
1
CV155
0.1U_0402_10V7K
2
1
CV156
0.1U_0402_10V7K
2
1
CV264
1U_0402_6.3V6K
2
1
CV265
1U_0402_6.3V6K
2
1
CV263
1U_0402_6.3V6K
1
10U_0603_6.3V6M
CV245
+VRAM_1.5VS
+
1
@
CV131
330U_D2_2V_Y
2
+
CV344
330U_B2_2.5VM_R15M
2
A
A
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
20
of
61
5
4
3
2
1
64Mx16 DDR3 *8==>1GB
D
D
DQMC[7..0]
<14,20> DQMC[7..0]
CMDC[30..0]
<14,20> CMDC[30..0]
<14,20> DQSC#[7..0]
<14,20> DQSC[7..0]
<14,20> MDC[63..0]
DQSC#[7..0]
UV15
DQSC[7..0]
+MEM_VREF_CA3
+MEM_VREF_DQ3
MDC[63..0]
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
1
+VRAM_1.5VS
2
RV130
1K_0402_1%
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDC39
MDC33
MDC38
MDC32
MDC36
MDC34
MDC37
MDC35
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC44
MDC43
MDC47
MDC40
MDC45
MDC42
MDC46
MDC41
+MEM_VREF_CA3
+MEM_VREF_DQ3
Group4
Group5
+VRAM_1.5VS
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
Mode D
Address
@
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDC63
MDC58
MDC62
MDC59
MDC60
MDC61
MDC57
MDC56
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC54
MDC48
MDC52
MDC50
MDC53
MDC51
MDC55
MDC49
1
RV129
1K_0402_1%
CMDC12
CMDC27
CMDC26
CV304
0.01U_0402_25V7K
C
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
BA0
BA1
BA2
2
2
M2
N8
M3
CLKC1
CLKC1#
CMDC19
J7
K7
K9
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
CK
CK
CKE/CKE0
CMDC12
CMDC27
CMDC26
+VRAM_1.5VS
M2
N8
M3
CLKC1
CLKC1#
CMDC19
J7
K7
K9
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
CK
CK
CKE/CKE0
Group6
+VRAM_1.5VS
1
+VRAM_1.5VS
2
RV142
1K_0402_1%
DQSC4
DQSC5
1
+MEM_VREF_DQ3
1
RV131
1K_0402_1%
CV305
0.01U_0402_25V7K
F3
C7
DQMC4
DQMC5
2
2
E7
D3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSC#4
DQSC#5
G3
B7
CMDC5
CLKC1
ZQ6
L8
1
<14>
T2
RESET
ZQ/ZQ0
DQSC7
DQSC6
F3
C7
DQMC7
DQMC6
E7
D3
DQSC#7
DQSC#6
G3
B7
CMDC5
T2
ZQ7
L8
RV146
243_0402_1%
J1
L1
J9
L9
RV147
243_0402_1%
2
DQSL
DQSU
RESET
ZQ/ZQ0
96-BALL
SDRAM DDR3
A14
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
C
CAS*
CS0_H#
ODT_H
CKE_H
CMD19
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
B
Not Available
2
1
2
1
2
CV166
0.1U_0402_10V7K
2
1
CV165
0.1U_0402_10V7K
2
1
CV167
0.1U_0402_10V7K
2
1
CV168
0.1U_0402_10V7K
2
1
CV273
1U_0402_6.3V6K
2
1
CV274
1U_0402_6.3V6K
2
1
10U_0603_6.3V6M
2
1
CV248
2
1
CV162
0.1U_0402_10V7K
2
1
CV161
0.1U_0402_10V7K
2
1
CV163
0.1U_0402_10V7K
2
1
CV164
0.1U_0402_10V7K
2
1
CV270
1U_0402_6.3V6K
1
CV271
1U_0402_6.3V6K
+VRAM_1.5VS
CV269
1U_0402_6.3V6K
10U_0603_6.3V6M
CV247
2
A14
CMD5
96-BALL
SDRAM DDR3
+VRAM_1.5VS
1
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CV272
1U_0402_6.3V6K
CLKC1#
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
<14>
J1
L1
J9
L9
CKE
CMD4
CMD18
1
2
RV149
160_0402_1%
ODT_L
CMD3
CMD17
1
B
DQSL
DQSU
CMD2
CMD16
ODT/ODT0
CS/CS0
RAS
CAS
WE
32..63
CMD1
Group7
+VRAM_1.5VS
BA0
BA1
BA2
0..31
CS0_L#
CMD0
1
+MEM_VREF_CA3
UV14
@
A
A
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
21
of
61
A
B
C
D
E
F
G
H
OPTIMUS for 2D HD/FHD Panel
3D@
<13> VGA_EDID_CLK
3D@
<13> VGA_EDID_DATA
3D@
<13> VGA_ENVDD
<13> VGA_ENBKL
DIS@
DIS@
C890
<6> H_EDP_AUXN
C891
<6> H_EDP_TXP0
<6> H_EDP_TXN0
<6> H_EDP_TXP1
<6> H_EDP_TXN1
LVDS_EDID_CLK
41
42
43
44
45
46
LVDS_EDID_DATA
LCD_ENVDD
EC_ENBKL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
G1
G2
G3
G4
G5
G6
C913
C914
C915
LVDS_EDID_CLK
LVDS_EDID_DATA
LVDS_TXOUT0+
LVDS_TXOUT0LVDS_TXOUT1+
LVDS_TXOUT1-
DISCRETE for 3D Dual Chanel Panel
<15> VGA_TZOUT0+
<15> VGA_TZOUT2<15> VGA_TZCLK+
<15> VGA_TZCLK-
1 3D@
2
R500
0_0402_5%
1 3D@
2
R501
0_0402_5%
1 3D@
2
R502
0_0402_5%
1 3D@
2
R503
0_0402_5%
1 3D@
2
R504
0_0402_5%
1 3D@
2
R505
0_0402_5%
1 3D@
2
R507
0_0402_5%
1 3D@
2
R508
0_0402_5%
LVDS_TZOUT0+
LVDS_TZOUT0LVDS_TZOUT1+
1
2
10U_0603_6.3V6M
3
1
W=80mils
3
+3VS
USB20_N11 <29>
@
Q20
AO3413_SOT23
USB20_P11 <29>
2
LCDPWR_GATE2
+LCD_VDD
close to Q17
1
2
R96 CAM@ 0_0402_5%
2
AZ5125-02S.R7G_SOT23-3
for 3D with DCDC/B
INT_MIC_CLK <42>
INT_MIC_DATA <42>
+LCD_VDD
+PANEL_VDD
+LCD_VDD_R
+3VS_LVDSDDC
LVDS_EDID_CLK
LVDS_EDID_DATA
1
2
R78 CAM@ 0_0402_5%
L55 @
4
3 3
2
Reserve for EMI request
@
INT_MIC_CLK
INT_MIC_DATA
1
1
2
C226
0.1U_0402_10V7K
2
2A
C227
4.7U_0805_10V4Z
1 @
R361
LVDS_ENVDD
For RF
1
+LCD_VDD
@
C258 47P_0402_50V8J
2
2
R1442
2LCD_ENVDD
0_0402_5%
3D@ 1
0_0603_5%
+3VS
reserve for 3D w/o DCDC/B
GND_R
LVDS_TXCLKLVDS_TXCLK+
20MILS
1 IEDP@ 2 LCD_ENVDD_R
R62 0_0402_5%
R389
0_0603_5%
LVDS@
+LCD_VDD_R
40MILS
Prevent to use wrong interface panel.
LVDS_TZCLKLVDS_TZCLK+
1
R79 3D@
L57 @
USB20_N13_R
1
1
2
1 IEDP@
0_0603_5%
+LCD_VDD
2
R390
1 @
0_0603_5%
+5VS
1 IEDP@ 2
R360
0_0402_5%
+3VS_LVDSDDC
2
0_0402_5%
2
2
R392
For LVDS 3D only
USB for Glasses free 3D
USB20_N13_R
USB20_P13_R
CPU_EDP_HPD <6>
2 LVDS@ 1
R1440 0_0603_5%
+3VS
1
USB20_N13 <29>
2
LVDS_ENVDD
LED_PWM
BKOFF#_R
USB20_P13_R
4
4
3
3
LED_PWM
@
2
1
0_0402_5%
R347
1.5A
1
R97 3D@
+LCD_INV
1
2
@
C257 47P_0402_50V8J
3
C232
0.1U_0402_10V7K
USB20_P13 <29>
WCM-2012-900T_0805
LVDS_TZOUT2+
2
0_0402_5%
1
RB751V40_SC76-2
R131
47K_0402_5%
Reserve for EMI request
2
D17
2 OPT@ 1
0_0402_5%
R332
PCH_PWM <28>
2 DIS@ 1
0_0402_5%
R349
VGA_BL_PWM <13>
For RF
LVDS_TZOUT2LVDS_TZCLK+
LVDS_TZCLK-
3
D84
2
WCM-2012-900T_0805
1
USB20_N11_R
USB20_P11_R
E-T_0871K-F40N-00L
@
LVDS_TZOUT1-
1
+LCD_VDD
1
C393
2
3
C912
1
JLVDS4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
USB20_P11_R
CAM@
0.1U_0402_10V7K
1
2
C225
2
1 CAM@ 2 +3VS_LVDS_CAM
R388
0_0603_5%
+3VS
LVDS_TXCLK-
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
1
W=20mils
LVDS_TXCLK+
OPT for 2D HD eDP Panel
<6> H_EDP_AUXP
+LCD_VDD
LVDS_TXOUT2-
@
C256 47P_0402_50V8J
2
4
IEDP@
Q23
AO3413_SOT23
1
1LVDS@
2
R106
0_0805_5%
For RF
USB20_N11_R
2
Add F3 to prevent
burn on PVT
1.5A
+LCD_INV
1
C234
68P_0402_50V8J
2
F3
L2
3A_32V_S1206-F-3.0A
2
1
1
2
FBMA-L11-201209-221LMA30T_0805
1
B+
+3VS
Reserve for eDP panel
LVDS & eDP cable pine definition notice.
Prevent to use wrong interface panel.
LVDS cable
MB side
C235
0.1U_0402_25V6
2
Pin 22
C2521
IEDP@
1
D15
Pin 22
2
0.1U_0402_10V7K
IEDP@
U17
2
0_0402_5%
4
2
RB751V40_SC76-2
IN1
1
IN2
2
LVDS@
O
R113
10K_0402_5%
EC_ENBKL
BKOFF# <44>
SN74AHC1G08DCKR_SC70-5
GND
2
LVDS
BKOFF#_R
eDP cable
MB side
B+
4
IEDP@1
R103
5
<15> VGA_TXCLK-
+PANEL_VDD
2
due to NV request use 10K pull down for LCD_ENVDD,
we separate BOM for OPT/DIS SKU
+3VS
OPT@
R112
100K_0402_5%
1
C229
P
2
3D@
LVDS_TXOUT1+
only need for 3D with DCDC/B
,JLVDS Pin8 can connect to
2 @
1
+LCV_VDD directly for
R1441 0_0603_5%
3D w/o DCDC/B
R112
10K_0402_5%
DIS@
1
W=80mils
1
C233
G
<15> VGA_TXCLK+
3D@
LCD/PANEL BD. Conn.
LVDS_TXOUT0+
LVDS_TXOUT0-
R260
1K_0402_5%
DIS@
LCDPWR_GATE
W=80mils
+LCD_VDD
2
Q1B
2N7002DW-T/R7_SOT363-6
3
<15> VGA_TXOUT2-
3D@
5
1
<15> VGA_TXOUT2+
3D@
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
1
3
LCD_ENVDD_R
2 OPT@ 1
R260
2.2K_0402_5%
4
EC_ENBKL <44>
LVDS@
Q17
AO3413_SOT23
1
R110 2LCDPWR_GATE
1
2
47K_0402_5%
1
C230
0.01U_0402_25V7K
LCD_ENVDD
IEDP@ 2
C292
0.1U_0402_10V7K
W=80mils
1
<15> VGA_TXOUT1-
3D@
1
R331
1
R309
1
R317
1
R315
1
R308
1
R302
1
R305
1
R304
1
R314
1
R310
1
R356
1
R358
+5VS
2
2
LCD_ENVDD
2
<15> VGA_TXOUT1+
3D@
LVDS@
2
C228
0.1U_0402_10V7K
1
LVDS_EDID_DATA
EC_ENBKL
+3VS
1
Q1A
2N7002DW-T/R7_SOT363-6
1
<15> VGA_TXOUT0-
3D@
R120
100K_0402_5%
IEDP@
4.7U_0603_6.3V6K
LVDS_TZCLK-
LVDS_EDID_CLK
DISCRETE for 3D Dual Chanel Panel
<15> VGA_TXOUT0+
1
1
LVDS_TZCLK+
2
<28> UMA_ENBKL
R108
100K_0402_5%
LVDS@
0.1U_0402_10V7K
<28> LCD_TZCLK-
LVDS_TZOUT2-
3
<28> LCD_TZCLK+
LVDS_TXCLK-
R109
150_0603_5%
LVDS_TZOUT2+
1
LVDS_TXCLK+
1 OPT@ 2
R350
0_0402_5%
1 OPT@ 2
R357
0_0402_5%
<28> UMA_ENVDD
<28> LCD_TZOUT2-
+5VS
2
LVDS_TXOUT2-
LVDS_TZOUT1-
2
<28> LCD_TZOUT2+
+3VS
6
<28> LCD_TZOUT1-
LVDS_TXOUT2+
LVDS_TZOUT1+
G
<28> LCD_EDID_DATA
LVDS_TXOUT1-
+LCD_VDD
LVDS_TZOUT0-
D
<28> LCD_EDID_CLK
<28> LCD_TZOUT1+
LVDS_TZOUT0+
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
S
<28> LCD_TXCLK+
<28> LCD_TXCLK-
LVDS_TXOUT1+
OPTFHD@ 1
R270
OPTFHD@ 1
R267
OPTFHD@ 1
R269
OPTFHD@ 1
R268
OPTFHD@ 1
R337
OPTFHD@ 1
R283
OPTFHD@ 1
R333
OPTFHD@ 1
R329
G
1
<28> LCD_TZOUT0-
D
<28> LCD_TXOUT2-
<28> LCD_TZOUT0+
LVDS_TXOUT0-
D
<28> LCD_TXOUT2+
LVDS_TXOUT0+
S
<28> LCD_TXOUT1-
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
G
<28> LCD_TXOUT1+
LVDS2D@ 1
R262
LVDS2D@ 1
R263
LVDS2D@ 1
R265
LVDS2D@ 1
R264
LVDS2D@ 1
R298
LVDS2D@ 1
R277
LVDS2D@ 1
R297
LVDS2D@ 1
R296
LVDS2D@ 1
R300
LVDS2D@ 1
R299
S
<28> LCD_TXOUT0+
<28> LCD_TXOUT0-
eDP
For EMI
4
1
2
R147
0_0402_5%
LVDS@
NC
2
C489
@
2
1
C490
@
2
0.1U_0402_25V6
C268
@
1
0.1U_0402_25V6
2
1
0.1U_0402_25V6
C236
@
0.1U_0402_25V6
Reserve for LVDS panel
1
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
A
B
C
D
E
F
G
Sheet
22
H
of
61
A
B
C
D
E
D4
@
D5
1
@
1
1
CRT CONNECTOR
D3
@
+3VS
If=1A
+5VS
+CRT_VCC_R
+CRT_VCC
D6
F1
2
3
2
DAN217_SC59
3
DAN217_SC59
2
3
2
DAN217_SC59
1
RB491D_SOT23-3
3
1
CRT_R
1
R189
1
R190
1
R191
CRT_G
CRT_B
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
CRT_R_R
L3
1
2 NBQ100505T-800Y_0402
CRT_R_L
CRT_G_R
L4
1
2 NBQ100505T-800Y_0402
CRT_G_L
CRT_B_R
L5
1
2 NBQ100505T-800Y_0402
40 mils
1
2
1
0.5A_8V_KMC3S050RY
C237
0.1U_0402_10V7K
2
@
1
CRT_B_L
2
2
C241
2
1
C242
2
1
C243
2
2.2P_0402_50V8C
2
C240
1
2.2P_0402_50V8C
C239
1
2.2P_0402_50V8C
2
C238
1
2.2P_0402_50V8C
2
C249
@
1
2.2P_0402_50V8C
2
C248
@
1
2.2P_0402_50V8C
C247
@
1
2.2P_0402_50V8C
1
2.2P_0402_50V8C
2
1
150_0402_1%
2
1
150_0402_1%
2
1
150_0402_1%
R138 R139 R140
2.2P_0402_50V8C
JCRT
T65 PAD
CRT_R_L
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+CRT_VCC
VSYNC
T66 PAD
By EMI demand
CRT_DDC_CLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
C-H_13-12201513CP
OPTIMUS
2
5
1
2
R141
2
A
Y
4
U6
SN74AHCT1G125GW_SOT353-5
CRT_CLK
CRT_DATA
1
2
C250
0.1U_0402_10V7K
2
CRT_VSYNC
D_CRT_HSYNC
1
L6
2
10_0402_5%
D_CRT_VSYNC
1
L7
2
10_0402_5%
+CRT_VCC
HSYNC
A
4
Y
U7
SN74AHCT1G125GW_SOT353-5
3
C245
@
Close to CRT Connector
VSYNC
1
2
DISCRETE
<13> VGA_CRT_VSYNC
<13> VGA_CRT_CLK
<13> VGA_CRT_DATA
CRT_G
3
CRT_B
+CRT_VCC
CRT_HSYNC
+3VS
CRT_VSYNC
CRT_CLK
CRT_DATA
2
<13> VGA_CRT_HSYNC
2
CRT_R
2
<13> VGA_CRT_B
1 DIS@ 2
R178
0_0402_5%
1 DIS@ 2
R181
0_0402_5%
1 DIS@ 2
R167
0_0402_5%
1 DIS@ 2
R177
0_0402_5%
1 DIS@ 2
R179
0_0402_5%
DIS@
1
2
R193
0_0402_5%
1 DIS@ 2
R194
0_0402_5%
C246
@
R153
4.7K_0402_5%
2
Close to CRT Connector
Q205A
1
5
CRT_CLK
Q205B
4
CRT_DATA
1
C282
33P_0402_50V8K
2
@
1
R159
4.7K_0402_5%
1
<13> VGA_CRT_G
1
<13> VGA_CRT_R
3
1
10P_0402_50V8J
CRT_HSYNC
CRT_VSYNC
5
1
CRT_HSYNC
1
10K_0402_5%
10P_0402_50V8J
<28> UMA_CRT_DATA
CRT_B
P
OE#
<28> UMA_CRT_CLK
2
0.1U_0402_10V7K
G
<28> UMA_CRT_VSYNC
1
C244
CRT_G
P
OE#
<28> UMA_CRT_HSYNC
CRT_R
G
<28> UMA_CRT_B
1 OPT@ 2
R200
0_0402_5%
1 OPT@ 2
R204
0_0402_5%
1 OPT@ 2
R211
0_0402_5%
OPT@
1
2
R213
0_0402_5%
1 OPT@ 2
R235
0_0402_5%
1 OPT@ 2
R236
0_0402_5%
1 OPT@ 2
R261
0_0402_5%
3
<28> UMA_CRT_R
<28> UMA_CRT_G
2
@
+CRT_VCC
CRT_DDC_CLK
6
2N7002DW-T/R7_SOT363-6
CRT_DDC_DAT
3
2N7002DW-T/R7_SOT363-6
C285
33P_0402_50V8K
2 @
C284
470P_0402_50V8J
@
1
1
2
C283
470P_0402_50V8J
2 @
4
4
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
A
B
C
D
Document Number
Rev
B
4019HG
Sheet
E
23
of
61
HDMI CEC Controller
1
+3VL
U16
Address: 0011010X
<44,49,50> EC_SMB_CK1
+3VL
2
1
P1_6/CLK0/SSI01
11
CEC_INT#
P1_5/RXD0/CNTR01/INT11#
12
CEC_TEST
P1_4/TXD0
13
CEC_FSHUPD1 CEC@ 2
R170
4.7K_0402_5%
P1_3/KI3#/AN11/TZOUT
14
P3_5/SSCK/SCL/CMP1_2
7
VCC/AVCC
P1_1/KI1#/AN9/CMP0_1
17
2 CEC@ 1
R176
4.7K_0402_5%
8
MODE
18
HDMI_DATA
HDMI_CECIN
9
P4_5/INT0#/RXD1
P3_3/TCIN/INT3#/SSI00/CMP1_0
19
HDMI_HPD_R
P3_4/SCS#/SDA/CMP1_1
20
1 1
2
VSS/AVSS
6
XIN/P4_6
P1_2/KI2#/AN10/CMP0_2
15
P4_2/VREF
16
1
2
2
2
HDMI_DATA
3
1
C848
1
C263
3
3
HDMI_SCLK
1
HDMI_SDATA
1
D
Q48
BSH111_SOT23-3
CEC@
D
Q50
2N7002_SOT23-3
CEC@
2
G
1
3
D
1
HDMI_CLK
CEC_FSHUPD (Pin13)
Low= Force to update flash.
S
1 R163
2
27K_0402_5%
CEC@
Q47
BSH111_SOT23-3
CEC@
+3VL
CEC@
2
1U_0402_6.3V6K
2
0.1U_0402_10V7K
CEC@
HDMI_CLK
5
2 CEC@ 1CEC_XIN
R174
47K_0402_5%
HDMI_CEC
XOUT/P4_7
R164
4.7K_0402_5%
CEC@
D
2
G
RESET#
R166
4.7K_0402_5%
CEC@
S
HDMI_CECOUT
P3_7/CNTR0#/SSO/TXD1
S
D
3
2 CEC@ 1CEC_XOUT 4
R171
47K_0402_5%
R581
27K_0402_5%
CEC@
D
Q49
2N7002_SOT23-3
CEC@
2 CEC@ 1CEC_RST#
R169
4.7K_0402_5%
G
2
D9
CH751H-40PT_SOD323-2
CEC@
1 CEC@ 2
R168
4.7K_0402_5%
G
R162
10K_0402_5%
CEC@
HDMI_CECIN
2
2
1
+3VL
+3VL
CEC_INT# <44> +3VL
1
+3VL
3
2
4
1
5
S
C262
1
0.1U_0402_10V7K
CEC@
R165
100K_0402_5%
CEC@
HDMI_CECOUT
10
P1_7/CNTR00/INT10#
46@
RO0000003HM
EC_SMB_DA1 <44,49,50>
2
2
JHDMI1
HDMI Royalty
HDMI W/Logo + HDCP
R5F211A4C33SP-W4_LSSOP20
CEC@
HDMI W/O Logo: RO0000001HM
HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM
+3VS
+3VS_DGPU
2 0.1U_0402_10V7K IHDMI@
1
2 0.1U_0402_10V7K IHDMI@
CV341
1
2 0.1U_0402_10V7K IHDMI@
UMA_DVI_TXD1-
CV342
1
2 0.1U_0402_10V7K IHDMI@
UMA_DVI_TXD2+
1
2 0.1U_0402_10V7K IHDMI@
UMA_DVI_TXD2-
CV343
UMA_DVI_TXD0UMA_DVI_TXD1+
1
2 0.1U_0402_10V7K DHDMI@
VGA_DVI_TXD0+
CV331
1
2 0.1U_0402_10V7K DHDMI@
CV332
1
2 0.1U_0402_10V7K DHDMI@
CV333
1
2 0.1U_0402_10V7K DHDMI@
VGA_DVI_TXD1-
CV334
1
2 0.1U_0402_10V7K DHDMI@
VGA_DVI_TXD2+
1
2 0.1U_0402_10V7K DHDMI@
VGA_DVI_TXD2-
CV335
<15> VGA_HDMI_TX2-
2
1
CV330
IHDMI@
1
0_0402_5%
<28> UMA_HDMI_CLK
2
R435
<15> VGA_HDMI_CLK
DHDMI@
2
1
R391
0_0402_5%
VGA_DVI_TXD0VGA_DVI_TXD1+
2
R401
2
0_0402_5%
1
HDMI_R_CK-
VGA_DVI_TXC+
3
HDMI_R_CK+3VL
+HDMI_5V_OUT
3
1
2 2
WCM-2012-900T_4P
DHDMI@
@
1
R173
2
0_0402_5%
C264
0.1U_0402_10V7K
HDMI@
HDMI_R_CK+
1
4
2
4
3
VGA_DVI_TXD0+
2
3
WCM-2012-900T_4P
@
1
2
R210
0_0402_5%
UMA_DVI_TXD0+
HDMI_R_D0-
@
1
R175
L9
1 DHDMI@
1
4
HDMI_R_D0+
VGA_DVI_TXD0-
HDMI_R_D1+
VGA_DVI_TXD1-
2
0_0402_5%
2
4
3
G
2
0_0402_5%
HDMI_R_D0+
3
@
1
R208
L13
1 IHDMI@
1
A
U9
Y
4
HDMI_HPD_C
R186
100K_0402_5%
HDMI@
HDMI_HPD_R
74AHCT1G125GW_SOT353-5
HDMI@
@
1
R207
2
0_0402_5%
1
UMA_DVI_TXD2-
@
1
R192
L15
1 IHDMI@
1
2
0_0402_5%
1
HDMI_R_D1-
+5VL
2
2
@
1
R187
L11
1 DHDMI@
1
3
3
4
2
0_0402_5%
HDMI_R_D2-
VGA_DVI_TXD2+
2
0_0402_5%
2
2
4
3
3
UMA_DVI_TXD2+
4
WCM-2012-900T_4P
@
1
2
R209
0_0402_5%
HDMI_R_D2+
VGA_DVI_TXD2-
4
WCM-2012-900T_4P
@
1
2
R188
0_0402_5%
2
B
F2
1
+HDMI_5V_OUT_F
HDMI_R_D1-
R195
680_0402_5%
IHDMI@
R197
680_0402_5%
IHDMI@
R198
680_0402_5%
IHDMI@
R202
680_0402_5%
IHDMI@
R201
680_0402_5%
IHDMI@
R203
680_0402_5%
IHDMI@
HDMI_R_CK-
HDMI_R_D1+
HDMI_R_D0+
HDMI_R_D1+
HDMI_R_D0HDMI_R_D2-
R205
680_0402_5%
IHDMI@
HDMI_R_D2+
R206
680_0402_5%
IHDMI@
07/10/2010
Intel DG P.132
2
+HDMI_5V_OUT
0.5A_8V_KMC3S050RY
HDMI@
2
1
2
1
HDMI_R_D2+
1 DHDMI@2
R195
499_0402_1%
1 DHDMI@2
R197
499_0402_1%
1 DHDMI@2
R198
499_0402_1%
1 DHDMI@2
R202
499_0402_1%
1 DHDMI@2
R201
499_0402_1%
1 DHDMI@2
R203
499_0402_1%
DHDMI@
1
2
R205
499_0402_1%
DHDMI@
1
2
R206
499_0402_1%
C259
HDMI@
0.1U_0402_10V7K
+5VS
HDMI Connector
JHDMI
HDMI_HPD_C
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
HDMI_CEC
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-
D
2
G
S
Q24
2N7002_SOT23-3
HDMI@
HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
A
SUYIN_100042GR019M23DZL
@
HDMI_R_D2-
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
4
1
PMEG2010AEH_SOD123
CEC@
5
<13,28,30>
HDMI_R_D0-
3
2
0_0402_5%
HDMI_HPD
D54
1
2 2
WCM-2012-900T_4P
@
1
R183
VGA_DVI_TXD1+
3
2
HDMI@
D53
3
A
DHDMI@
4 L10
4
3
1
2 2
WCM-2012-900T_4P
@
1
R196
UMA_DVI_TXD1-
3
1
1
PMEG2010AEH_SOD123
HDMI_R_D1IHDMI@
4 L14
4
+3VS
HDMI@
3
2
0_0402_5%
HDMI@
2
1
R571
2.2K_0402_5%
HDMI_HPD_R
C265
0.1U_0402_10V7K
HDMI@
2
WCM-2012-900T_4P
@
1
2
R180
0_0402_5%
@
1
R182
2
+5VS
HDMI_R_CK+
UMA_DVI_TXD1+
HDMI@
2
1
R570
100K_0402_5%
D55
HDMI_HPD_U 1
2
1K_0402_5%
2
2
UMA_DVI_TXD0-
HDMI@
R145
2
2
0_0402_5%
1
UMA_DVI_TXCB
@
4 L8
4
3
1
2 2
WCM-2012-900T_4P
IHDMI@
@
1
R199
1
R157
HDMI_SDATA
IHDMI@
Q19
BSH111_SOT23-3
1
0_0402_5%
HDMI@
1
1
3
VGA_DVI_TXC-
5
4 L12
4
HDMI_R_CK+
1
2
0_0402_5%
P
@
OE#
1
R160
HDMI_SCLK
1
D
UMA_DVI_TXC+
R185
2.2K_0402_5%
HDMI@
Q18
BSH111_SOT23-3
HDMI@
1
1
3
0_0402_5%
S
2
R438
<28> UMA_HDMI_DATA
R184
2.2K_0402_5%
HDMI@
3
DHDMI@
<15> VGA_HDMI_DATA
C
1
1
CV340
<15> VGA_HDMI_TX0+
R453
R452
0_0402_5% 0_0402_5%
IHDMI@
DHDMI@
1
CV339
<15> VGA_HDMI_CLK-
VGA_DVI_TXC-
1
UMA_DVI_TXD0+
VGA_DVI_TXC+
2 0.1U_0402_10V7K DHDMI@
D
2 0.1U_0402_10V7K IHDMI@
2 0.1U_0402_10V7K DHDMI@
S
1
1
CV329
G
<28> UMA_HDMI_TX2-
CV338
CV328
<15> VGA_HDMI_CLK+
G
<28> UMA_HDMI_TX1<28> UMA_HDMI_TX2+
1
UMA_DVI_TXC-
2
<28> UMA_HDMI_TX0<28> UMA_HDMI_TX1+
UMA_DVI_TXC+
2 0.1U_0402_10V7K IHDMI@
2
<28> UMA_HDMI_TX0+
2 0.1U_0402_10V7K IHDMI@
2
<28> UMA_HDMI_TXC-
1
CV337
1
C
CV336
2
<28> UMA_HDMI_TXC+
For DISCRETE
2
+HDMI_5V_OUT
For Optimus
3
2
Document Number
Rev
B
4019HG
Sheet
1
24
of
61
5
4
3
2
1
UH1A
SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
RH33 1
+3VS
@
1
RH36
PCH_SPKR
2
1K_0402_5%
*
PCH_SPKR
High = Enabled "No Reboot Mode"
Low = Disabled (Default)
+3VALW_PCH
<42> AZ_SDOUT_HD
<44> PWRME_CTRL
2
RH272
RH32 1
RH25 1
@
ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)
HDA_BCLK
L34
HDA_SYNC
INT.PD 20K
PCH_SPKR
T10
SPKR
INT.PD 20K
AZ_RST#
K34
HDA_RST#
AZ_SDOUT
HDA_SDIN0
INT.PD 20K
G34
HDA_SDIN1
INT.PD 20K
C34
HDA_SDIN2
INT.PD 20K
A34
HDA_SDIN3
INT.PD 20K
A36
HDA_SDO
INT.PD 20K
E34
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
AZ_SYNC
1
1K_0402_5%
2
G
AZ_SYNC_R
2
33_0402_5%
1
RH56
2
1M_0402_5%
3
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
20K
JTAG_TMSINT.PH
20K
SATAICOMPO
Y11
T68 PAD
PCH_JTAG_TDI
K5
JTAG_TDI
INT.PH 20K
SATAICOMPI
Y10
T69 PAD
PCH_JTAG_TDO
H1
JTAG_TDO
1
10K_0402_5%
SATA_LED#
RH29 2
1 10K_0402_5%
PCH_GPIO21
RH34 2
1 10K_0402_5%
PCH_GPIO19
RH28 1
2 10K_0402_5%
m-SATA
ODD
+RTCBATT
1
2
@
DH7
RB751V-40_SOD323-2
+RTCBATT
SATAICOMP
AB12
SATA3COMPI
AB13
SATA3RBIAS
AH1
RBIAS_SATA3
D
+3VS
HDD
SATA_PRX_C_DTX_N1 <36>
SATA_PRX_C_DTX_P1 <36>
SATA_PTX_DRX_N1 <36>
SATA_PTX_DRX_P1 <36>
2
RH31
+RTCVCC
SATA3RCOMPO
1
RH43
2
37.4_0402_1%
+1.05VS_VCC_SATA
1
RH48
2
49.9_0402_1%
+1.05VS_SATA3
1
RH41
2
750_0402_1%
+3VL
If use GCLK, please delet DH1
C
SATA3_COMP
PCH_SPICLK
T3
SPI_CLK
PCH_SPICS0#
Y14
SPI_CS0#
PCH_SPICS1#
T1
SPI_CS1#
P3
SATA_LED#
PCH_SPIDI
V4
SPI_MOSI
INT.PD 20K
SATA0GP / GPIO21
V14
PCH_GPIO21
PCH_SPIDO
U3
SPI_MISO
INT.PH 20K
SATA1GP / GPIO19
P1
PCH_GPIO19
SATALED#
PCH_GPIO19 <29>
INT.PH 20K
BOOT BIOS Strap Bit 0
PANTHER-POINT_FCBGA989
HM76R3@
D
1
RH54
S
<42> AZ_SYNC_HD
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
JTAG_TCKINT.PD
Placement near to YH1
QH1
1
AM10
AM8
AP11
AP10
J3
RH26 GCLK@
PCH_RTCX1
1
2
0_0402_5%
+5VS
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
H7
SERIRQ
SERIRQ <44>
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
PCH_JTAG_TMS
SPI
2
RH55
+3VALW_PCH
<36> PCH_RTCX1_R
+3VS
SERIRQ
AM3
AM1
AP7
AP5
PCH_JTAG_TCK
down
LPC_FRAME# <44,45>
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
T67 PAD
HDA_SYNC
L=>On Die PLL is supplied by 1.8V
Need to pull high for Chief River Mobile platform
SERIRQ
V5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
C
signal has a weak internal pull
*This
H=>On Die PLL is supplied by 1.5V
LPC
N34
2 0_0402_5%
Change Net name due to
this function is high active
HDA_SDO
INTVRMEN
AZ_SYNC
1
1K_0402_5%
2 33_0402_5%
INTRUDER#
LPC_FRAME#
E36
K36
AZ_BITCLK
AZ_SDIN0_HD
<42> AZ_SDIN0_HD
RH12 1
C17
D36
1
+RTCVCC
2 33_0402_5%
PCH_INTVRMEN
FWH4 / LFRAME#
INT.PH 20K
LDRQ0#
INT.PH
20K
LDRQ1#
/ GPIO23
<44,45>
<44,45>
<44,45>
<44,45>
2
RH30 1
K22
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
1
<42> PCH_SPKR
<42> AZ_RST_HD#
SRTCRST#
SM_INTRUDER#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
DH1
<42> AZ_BITCLK_HD
Integrated SUS 1.05V VRM Enable
High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
2 33_0402_5%
RTCRST#
G22
C38
A38
B37
C37
2
RH27 1
D20
PCH_SRTCRST#
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
20K
20K
20K
20K
RB751V-40_SOD323-2
D
CH3
PCH_RTCRST#
INT.PH
INT.PH
INT.PH
INT.PH
CH8
2
2
CH101
10P_0402_50V8J
1 NOGCLK@
15P_0402_50V8J
RTCX2
0.1U_0402_10V7K
CH5 1
1U_0402_6.3V6K
@
2
RTCX1
C20
SATA 6G
@
2
A20
PCH_RTCX2
SATA
YH1
32.768KHZ_12.5P_1TJF125DP1A000D
NOGCLK@
1
PCH_RTCX1
RTC
2PCH_SRTCRST#
RH24 1
20K_0402_5%
1 NOGCLK@
15P_0402_50V8J
IHDA
JME
1
2
JTAG
iME Setting.
CH2
AZ_BITCLK_HD
2
NOGCLK@
CH4 1
1U_0402_6.3V6K
RH2
10M_0402_5%
2
1
JCMOS @
1
2
PCH_RTCRST#
2
2
1
CMOS Setting, near DDR Door
RH23 1
20K_0402_5%
+RTCVCC
BSS138_NL_SOT23-3
@
1
2
RH274
0_0402_5%
+3VS
2
1
SPI ROM for BIOS & ME (4MByte )
1
47P_0402_50V8J
CH19
CH6
@ 0.1U_0402_10V7K
For RF
PCH_SPICLK
PCH_SPIDI
UH3
2
B
PCH_SPICS0#
1
RH66
1
RH67
PCH_SPI0_CLK
2
33_0402_5%
PCH_SPI0_DI
2
33_0402_5%
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
VSS
Q
4MB ROM P/N:
SA00003K800
SA00004LI00
4
2
PCH_SPI0_DO
1
RH68
B
PCH_SPIDO
2
33_0402_5%
PCH_SPI0_CLK
1
for EMI
CH7
10P_0402_50V8J
1
2
1
1
2
1
PCH_JTAG_TDO
PCH_JTAG_TDI
RH40
100_0402_1%
RH39
100_0402_1%
A
PCH_SPI1_CLK
for EMI
RH69
10_0402_5%
WIN8@
2
RH65
10_0402_5%
2MB ROM P/N:
SA000041N00
SA00003FO10
PCH_JTAG_TMS
RH44
100_0402_1%
1
A
RH38
200_0402_5%
RH45
200_0402_5%
2
MX25L1606EM2I-12G_SO8
WIN8@
RH46
200_0402_5%
2
8
7
6
5
1
VCC
HOLD#
SCLK
SI
2
CS#
SO
WP#
GND
+3VALW_PCH
1
1
2
3
4
+3VALW_PCH
1
RH50
PCH_JTAG_TCK
2
51_0402_1%
2
UH4
PCH_SPICS1#
PCH_SPIDO 1 WIN8@ 2 PCH_SPI1_DO
RH269
33_0402_5% +3VS
47P_0402_50V8J
1
2
@ CH20
0.1U_0402_10V7K
1
2
CH100
WIN8@RH267 33_0402_5%
PCH_SPI1_CLK
PCH_SPICLK
1 WIN8@ 2
PCH_SPI1_DI
PCH_SPIDI
1
2
RH271 33_0402_5%
WIN8@
2
+3VALW_PCH
For RF
SPI ROM for Win8 (2MByte )
2
Socket: SP07000F500/SP07000H900
Please place U13 & U4 close to U2 PCH,
please place RH66, RH67, RH68 near UH3
Please place RH267 near RH66, Please place RH271 near RH67,
Please place RH269 near RH68.+3VS
1
MX25L3205DM2I-12G SO8
CH21
10P_0402_50V8J
WIN8@
1
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
2
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
25
of
61
2
BE34
BF34
BB32
AY32
PERN2
PERP2
PETN2
PETP2
BG36
BJ36
AV34
AU34
PERN3
PERP3
PETN3
PETP3
PCIE_PRX_C_CRTX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PTX_CRRX_N4
PCIE_PTX_CRRX_P4
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
PCIE_PRX_C_USBTX_N5
PCIE_PRX_C_USBTX_P5
PCIE_PTX_USBRX_N5
PCIE_PTX_USBRX_P5
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
D
Card Reader
EX-USB30
<38>
<38>
<38>
<38>
PCIE_PRX_C_CRTX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PTX_C_CRRX_P4
<40>
<40>
<40>
<40>
PCIE_PRX_C_USBTX_N5
PCIE_PRX_C_USBTX_P5
PCIE_PTX_C_USBRX_N5
PCIE_PTX_C_USBRX_P5
<36>
<36>
<36>
<36>
TV tuner
PCIE_PRX_C_TVTX_N6
PCIE_PRX_C_TVTX_P6
PCIE_PTX_C_TVRX_N6
PCIE_PTX_C_TVRX_P6
CH18 1
CH16 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CH12 1
CH9 1
EUSB30@
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
EUSB30@
PCIE_PRX_C_TVTX_N6
PCIE_PRX_C_TVTX_P6
PCIE_PTX_TVRX_N6
PCIE_PTX_TVRX_P6
TV@
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
TV@
CH10 1
CH1 1
+3VS
C
RH99 1
2 10K_0402_5% PCH_GPIO20
RH1041
2 10K_0402_5% CLKREQ_WLAN#
RH95 1
210K_0402_5%
CLKREQ_LAN#
Intel Spec:
PCIECLK_RQ0# is suspend well,
but we pull high to +3VS
for LAN en/disable function
LAN
<37>
<37>
CLK_LAN#
CLK_LAN
CLK_LAN#
CLK_LAN
WLAN
<36> CLK_WLAN#
<36> CLK_WLAN
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
J2
CLK_WLAN#
CLK_WLAN
AB49
AB47
CLKREQ_WLAN#
<36> CLKREQ_WLAN#
PERN7
PERP7
PETN7
PETP7
Y40
Y39
CLKREQ_LAN#
<37> CLKREQ_LAN#
BG40
BJ40
AY40
BB40
M1
AA48
AA47
<38>
Card Reader <38>
CLK_CR#
CLK_CR
EX-USB30
<40> CLKREQ_USBA30#
<36> CLK_TV#
<36> CLK_TV
EX-USB30
<36> CLKREQ_TV#
+3VALW_PCH
PCH_SMBDATA
SML0ALERT# / GPIO60
1 2.2K_0402_5%
2 RH70
1 2.2K_0402_5%
C8
PCH_SMLCLK0
G12
PCH_SMLDATA0
SML1ALERT# / PCHHOT# / GPIO74
C13
LAN_EN
SML1CLK / GPIO58
E14
PCH_SMLCLK1
SML1DATA / GPIO75
M16
PCH_SMLDATA1
SML0CLK
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CL_CLK1
3
QH3A
CL_RST1#
P10
CLK_TV#
CLK_TV
V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKREQ_TV#
L14
PM_SMBDATA <11,12,36,46>
6
1
PM_SMBCLK <11,12,36,46>
2N7002DW-T/R7_SOT363-6
DRAMRST_CNTRL_PCH <7,11>
+3VALW_PCH
LAN_EN <37>
2 RH78
1 2.2K_0402_5%
2 RH74
1 2.2K_0402_5%
+3VS
QH4B
PCH_SMLDATA1
3
QH4A
PCH_SMLCLK1
4
EC_SMB_DA2 <13,44,45>
2N7002DW-T/R7_SOT363-6
6
1
EC_SMB_CK2 <13,44,45>
M10
CLK_REQ_VGA#
AB37
AB38
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
CLKOUT_DP_N
CLKOUT_DP_P
AM12
AM13
CLK_CPU_EDP#
CLK_CPU_EDP
CLKIN_DMI_N
CLKIN_DMI_P
BF18
BE18
PCH_CLK_DMI#
PCH_CLK_DMI
CLKIN_GND1_N
CLKIN_GND1_P
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
CLKIN_DOT_96N
CLKIN_DOT_96P
G24
E24
CLK_DOT#
CLK_DOT
CLKIN_SATA_N
CLKIN_SATA_P
AK7
AK5
CLK_SATA#
CLK_SATA
REFCLK14IN
K45
CLK_14M_PCH
CLKIN_PCILOOPBACK
H45
CLK_PCILOOP
XTAL25_IN
XTAL25_OUT
V47
V49
PCH_X1
PCH_X2
XCLK_RCOMP
Y47
XCLK_RCOMP
1
RH115
CLKOUTFLEX0 / GPIO64
K43
CLK_FLEX0
F47
H47
K49
DGPU_PRSNT#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
INT. PH 20K
Control Link only for support Intel IAMT.
+3VALW_PCH
CLKOUT_PCIE4N
CLKOUT_PCIE4P
L12
4
2N7002DW-T/R7_SOT363-6
M7
CL_DATA1
CLKREQ_USBA30#
4.7K_0402_5%
4.7K_0402_5%
D
T11
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
RH102
RH103
2N7002DW-T/R7_SOT363-6
Y37
Y36
+3VS
QH3B
PCH_SMBDATA
A12 DRAMRST_CNTRL_PCH
SML0DATA
PEG_A_CLKRQ# / GPIO47
CLK_CR#
CLK_CR
Y43
Y45
PCH_SMBCLK
C9
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLK_USBA30#
CLK_USBA30
<40> CLK_USBA30#
<40> CLK_USBA30
H14
2 RH72
PCH_SMBCLK
V10
A8
SMBCLK
SMBDATA
PCH_GPIO20
CLKREQ_CR#
<38> CLKREQ_CR#
SMBALERT# / GPIO11
PCH_SMBALERT#
5
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
+3VALW_PCH
E12
Link
CH14 2
CH17 2
PERN1
PERP1
PETN1
PETP1
SMBUS
WLAN
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
BG34
BJ34
AV32
AU32
Controller
<36>
<36>
<36>
<36>
CH13 2
CH11 2
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
CLOCKS
LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
PCI-E*
<37>
<37>
<37>
<37>
1
5
3
UH1B
2
4
2
5
CLK_REQ_VGA# <13>
CLK_PCIE_VGA# <13>
CLK_PCIE_VGA <13>
PCH_SMBALERT#
RH2621
2 10K_0402_5%
DRAMRST_CNTRL_PCH
RH76 1
2 1K_0402_5%
LAN_EN
RH75 1
2 10K_0402_5%
PCH_SMLCLK0
RH73 2
1 2.2K_0402_5%
PCH_SMLDATA0
RH77 2
1 2.2K_0402_5%
+3VALW_PCH
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_CPU_EDP# <5>
CLK_CPU_EDP <5>
C
VGA
@
2
RH275
1 CLK_REQ_VGA#
2
10K_0402_5%
RH89
PCH_CLK_DMI#
PCH_CLK_DMI
RH79 1
RH82 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_GND1#
CLKIN_GND1
RH85 1
RH86 1
2 10K_0402_5%
2 10K_0402_5%
CLK_DOT#
CLK_DOT
RH80 1
RH81 1
2 10K_0402_5%
2 10K_0402_5%
CLK_SATA#
CLK_SATA
RH83 1
RH84 1
2 10K_0402_5%
2 10K_0402_5%
CLK_14M_PCH
RH87 1
2 10K_0402_5%
1
10K_0402_5%
120 MHz for eDP
From Clock Gen.
For EMI
CLK_PCILOOP
CLK_PCILOOP <29>
@
2
RH124
@
2
1
CH28
22P_0402_50V8J
1
10_0402_5%
B
B
210K_0402_5%
RH1121
210K_0402_5%
RH1191 LVDS@ 210K_0402_5%
RH1141
CLKREQ_CR#
PASSWORD_CLEAR#
CLKREQ_TV#
JPW
@
PANEL_SEL
210K_0402_5% PASSWORD_CLEAR#
RH122
RH121
<10> CLK_RES_ITP#
<10> CLK_RES_ITP
RH123
RH120
<5> CLK_CPU_ITP#
<5> CLK_CPU_ITP
E6
2
2
2
2
LVDS_SEL
@
@
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
1 0_0402_5%
1 0_0402_5%
PANEL_SEL
1 0_0402_5%
1 0_0402_5%
CLK_BCLK_ITP#
CLK_BCLK_ITP
V40
V42
CLKOUT_PCIE6N
CLKOUT_PCIE6P
T13
V38
V37
CLKOUT_PCIE7N
CLKOUT_PCIE7P
K12
AK14
AK13
INT. PH 20K
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
INT. PD 20K
INT. PD 20K
INT. PD 20K
HM76R3@ PANTHER-POINT_FCBGA989
+3VALW_PCH
LVDS_SEL
RH2761 IEDP@ 2 10K_0402_5%
PANEL_SEL
LVDS_SEL
Channel
A
RH2771 3D@
2 10K_0402_5%
+1.05VS_VCCDIFFCLKN
T72
PAD
CLK_FLEX1
T74
PAD
CLK_FLEX2
T73
PAD
PCH_X1
RH117
NOGCLK@
2
1 1M_0402_5%
NOGCLK@YH2 25MHZ_20PF_7V25000016
PCH_X1
CH26
Compal common design SW request to
add DGPU_Present on this GPIO67
1
1
1
3
GND
GND
2
4
3
PCH_X2
1
27P_0402_50V8J
NOGCLK@ 2
CH27
27P_0402_50V8J
2 NOGCLK@
DGPU_PRSNT#
H
L
PANEL_SEL
H
L
Single
(Default)
Dual
Channel
LVDS
EDP
DGPU_PRSNT#
H
L
UMA
DIS/OPT
DGPU_PRSNT#
1 @
RH227
2
10K_0402_5%
+3VS
A
LVDS_SEL
M/B SKU
RH277
10K_0402_5%
OPTFHD@
RH37
1
2
0_0402_5%
GCLK@
<36> PCH_X1_R
PANEL_SEL
LVDS_SEL
1
2 10K_0402_5%
RH116 OPTHD@
2
90.9_0402_1%
Placement near to YH2
INT. PD 20K
FLEX CLOCKS
RH1101
AB42
AB40
CLKREQ_USBA30#
1
210K_0402_5%
2
RH1071
2011/12/14
2
10K_0402_5%
Compal Secret Data
Issued Date
1
RH261
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
26
of
61
5
4
3
2
1
UH1C
2
RH163
2
RH279
2
RH280
@
PCH_SUSPWRDN#_R
RI#
PCH_LOW_BAT#
PCH_RSMRST#
1
10K_0402_5%
PM_PWROK
1
10K_0402_5%
SYS_PWROK
1
10K_0402_5%
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
<6>
<6>
<6>
<6>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
<6>
<6>
<6>
<6>
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
<6>
<6>
<6>
<6>
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
Reserve 0 ohm for cost down plan
2010/08/25
0_0402_5%
1
RH2812
PM_PWROK
IN1
2
IN2
FDI_INT
AW16
FDI_INT
BJ24
DMI_ZCOMP
FDI_FSYNC0
AV12
FDI_FSYNC0
BG25
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
BH21
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
DSWVREN
@
RH133
DPWROK
E22
PCH_DPWROK
WAKE#
B9
EC_SWI#
CLKRUN# / GPIO32
N3
PCH_GPIO32
G8
SUS_STAT#
SUSACK#_R
2
0_0402_5%
C12
XDP_DBRESET#
<5> XDP_DBRESET#
UH5
O
3
<5,44> PM_PWROK
1
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
K3
SYS_RESET#
SYS_PWROK
4
P12
SYS_PWROK
PM_PWROK
1
RH131
@
PM_PWROK_R
2
0_0402_5%
L22
PWROK
L10
<5> DRAMPWROK
SUSACK#_R
@
2
RH282
1 PCH_SUSPWRDN#_R
0_0402_5%
<44> PCH_RSMRST#
Stuff R137 if EC does not want to
involve in the handshake mechanism
for the DeepSX state entry and exit
1
<44> PCH_SUSPWRDN#
@
RH132
1
RH161
@
SYS_PWROK
2
0.01U_0402_25V7K
<44,50>
1
ACIN
D
PCH_DPWROK
FDI_FSYNC0
<6>
FDI_LSYNC0
<6>
FDI_LSYNC1
<6>
PM_SLP_S4#
SLP_S3#
F4
PM_SLP_S3#
20K
SLP_A#
G10
PM_SLP_A#
T77
PAD
SLP_SUS#
G16
PM_SLP_SUS#
T78
PAD
AP14
H_PM_SYNC
K14
PCH_GPIO29
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN# INT.PH
SLP_S5# / GPIO63
PCH_RSMRST#
2
0_0402_5%
<6>
FDI_FSYNC1
D10
RSMRST#
1
RH128
Stuff R222 if do not support DeepSX state
FDI_INT <6>
H4
DRAMPWROK
+RTCVCC
DSWVREN
RH150
2
RH151
2
1 330K_0402_5%
@
1 330K_0402_5%
DSWVREN must be always pulled high to +RTCVCC
*
EC_SWI# <37,40>
T76
N14
DSWVREN - Internal Deep Sleep 1.05V regulator
H：Enable
L：Disable
C
PAD
Follow EC check list demand,
but don't implement CLKRUN# this fuction
CLK_EC <44>
PM_SLP_S5# <44>
+3VS
PM_SLP_S4# <40,44>
PCH_GPIO32
INT.PD 20K
ACPRESENT / GPIO31
PCH_LOW_BAT#
E10
BATLOW# / GPIO72 INT.PH
RI#
A10
RI#
2
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
SLP_S4#
B13
H20
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
PM_SLP_S5#
C21
PCH_ACIN
DH2
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
32.768 KHz
SUSCLK / GPIO62
PCH_RSMRST#
PBTN_OUT#
2
330K_0402_5%
APWROK
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
SUS_STAT# / GPIO61
20K
DRAMPWROK
2 PCH_SUSPWRDN#_R
0_0402_5%
<5,44> PBTN_OUT#
+3VALW_PCH
1
CH23
INT.PH
SUSACK#
P
<5,44,55> VGATE
1
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AY24
AY20
AY18
AU18
Reserve this signal to EC by SW demand
2011/10/18a
<44> SUSACK#
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
G
C
5
+3VS
0.1U_0402_10V7K
1
2
CH103
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
RBIAS_CPY
2
750_0402_1%
1
RH127
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
AW24
AW20
BB18
AV18
DMI_COMP
2
49.9_0402_1%
1
RH126
+1.05VS_PCH
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
FDI
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
2
RH234
2
RH157
2
RH155
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
System Power Management
+3VALW_PCH
D
<6>
<6>
<6>
<6>
20K
PMSYNCH
SLP_LAN# / GPIO29
RH2561
@
2 8.2K_0402_5%
PM_SLP_S3# <44>
1
RH160
2
10K_0402_5%
+3VALW_PCH
H_PM_SYNC <5>
EC_SWI#
RH1591
2 10K_0402_5%
PCH_GPIO29
RH1621 @
2 10K_0402_5%
@
B
PCH_RSMRST#
2
0.01U_0402_25V7K
1
CH24
2011/10/18a
HM76R3@
B
@
1
CH25
PM_PWROK_R
2
0.01U_0402_25V7K
reserve for SW-node noise issue
place close to PCH 11/29
DH5
PM_PWROK
2
1
PCH_RSMRST#
DH6
<49,51>
1
POK
2
A
A
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
27
of
61
5
4
3
2
1
UH1D
OPT@
UMA_ENBKL
1
2
RH125
100K_0402_5%
OPT@
C
LCTL_CLK
2
1
RH145
2.2K_0402_5%
OPT@
LCTL_DATA
2
1
RH146
2.2K_0402_5%
OPT@
LCD_EDID_CLK
2
1
RH149
2.2K_0402_5%
OPT@
LCD_EDID_DATA
2
1
RH148
2.2K_0402_5%
OPT@
UMA_CRT_CLK
2
1
RH142
2.2K_0402_5%
OPT@
UMA_CRT_DATA
2
1
RH144
2.2K_0402_5%
OPT@
UMA_CRT_B
1
2
RH154
150_0402_1%
OPT@
UMA_CRT_G
1
2
RH156
150_0402_1%
OPT@
UMA_CRT_R
1
2
RH152
150_0402_1%
T45
P39
L_CTRL_CLK
L_CTRL_DATA
<22> LCD_TXOUT0<22> LCD_TXOUT1<22> LCD_TXOUT2<22> LCD_TXOUT0+
<22> LCD_TXOUT1+
<22> LCD_TXOUT2+
<22> LCD_TZCLK<22> LCD_TZCLK+
<22> LCD_TZOUT0<22> LCD_TZOUT1<22> LCD_TZOUT2<22> LCD_TZOUT0+
<22> LCD_TZOUT1+
<22> LCD_TZOUT2+
<23> UMA_CRT_B
<23> UMA_CRT_G
<23> UMA_CRT_R
<23> UMA_CRT_CLK
<23> UMA_CRT_DATA
<23> UMA_CRT_HSYNC
<23> UMA_CRT_VSYNC
INT.PD 50 SDVO_INTN
INT.PD 50 SDVO_INTP
AP39
AP40
RH140
2.2K_0402_5%
IHDMI@
RH139
2.2K_0402_5%
IHDMI@
D
INT.PD 20K
AF37
AF36
LVD_IBG
LVD_VBG
AE48
AE47
LVD_VREFH
LVD_VREFL
LCD_TXCLKLCD_TXCLK+
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
SDVO_CTRLCLK
SDVO_CTRLDATA
P38
M39
UMA_HDMI_CLK <24>
UMA_HDMI_DATA <24>
INT.PD 20K
RH283
IHDMI@
0_0402_5%
2
1
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
HDMI_HPD_UMA
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TXCUMA_HDMI_TXC+
DDPC_CTRLCLK
DDPC_CTRLDATA
HDMI_HPD
UMA_HDMI_TX2- <24>
UMA_HDMI_TX2+ <24>
UMA_HDMI_TX1- <24>
UMA_HDMI_TX1+ <24>
UMA_HDMI_TX0- <24>
UMA_HDMI_TX0+ <24>
UMA_HDMI_TXC- <24>
UMA_HDMI_TXC+ <24>
HDMI_HPD <13,24,30>
HDMI_HPD_UMA 2
1
100K_0402_5%
RH254
HDMI
P46
P42
INT.PD 20K
LCD_TZCLKLCD_TZCLK+
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
UMA_CRT_CLK
UMA_CRT_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
UMA_CRT_HSYNC
UMA_CRT_VSYNC
M47
M49
CRT_HSYNC
CRT_VSYNC
CRT_IREF
1
1K_0402_0.5%
T43
T42
DAC_IREF
CRT_IRTN
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
RH141
2
1 100K_0402_5%
C
M43
M36
INT.PD 20K
OPT@
2
RH138
+3VS
1
L_DDC_CLK
L_DDC_DATA
LCTL_CLK
LCTL_DATA
AM42
AM40
1
T40
K47
AP43
AP45
INT.PD 50SDVO_STALLN
INT.PD 50 SDVO_STALLP
2
L_BKLTCTL
LCD_EDID_CLK
LCD_EDID_DATA
INT.PD 50SDVO_TVCLKINN
INT.PD 50SDVO_TVCLKINP
2
P45
OPT@
LVDS_IBG
1
2
RH143
2.37K_0402_1%
T79 PAD
<22> LCD_TXCLK<22> LCD_TXCLK+
+3VS
PCH_PWM
L_BKLTEN
L_VDD_EN
Digital Display Interface
D
J47
M45
LVDS
<22> PCH_PWM
<22> LCD_EDID_CLK
<22> LCD_EDID_DATA
UMA_ENBKL
UMA_ENVDD
CRT
<22> UMA_ENBKL
<22> UMA_ENVDD
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
RH255
2
1 100K_0402_5%
B
B
HM76R3@
RH138
1K_0402_5%
DIS@
A
A
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
28
of
61
5
4
3
2
For Optimus
1
PLT_RST#
UH1E
RH299
RH305
1
PCH_GPIO52
PCH_GPIO2
PCH_GPIO53
RH324
2
RH323
2
RH325
2
RH322
2
RF_OFF#
PCI_PIRQA#
8.2K_0402_5%
1
PCH_GPIO5
PCI_PIRQD#
2
8.2K_0402_5%
DGPU_RST#
2
10K_0402_5%
DGPU_PWR_EN
2
10K_0402_5%
1
RH290
1
RH175
1
RH176
1 @
RH291
U3RXDN1_R
U3RXDN2_R
U3RXDN3_R
U3RXDN4_R
U3RXDP1_R
U3RXDP2_R
U3RXDP3_R
U3RXDP4_R
U3TXDN1
U3TXDN2
U3TXDN3
U3TXDN4
U3TXDP1
U3TXDP2
U3TXDP3
U3TXDP4
<39> U3RXDN1_R
<39> U3RXDN2_R
<34> U3RXDN3_R
<34> U3RXDN4_R
<39> U3RXDP1_R
<39> U3RXDP2_R
<34> U3RXDP3_R
<34> U3RXDP4_R
<39> U3TXDN1
<39> U3TXDN2
<34> U3TXDN3
<34> U3TXDN4
<39> U3TXDP1
<39> U3TXDP2
<34> U3TXDP3
<34> U3TXDP4
PCI_PIRQC#
C
RH326
2
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
PCI_PIRQB#
8.2K_0402_5%
PCH_GPIO55
1
8.2K_0402_5%
ODD_DA#
2
2
B21
M20
AY16
BG46
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD23
RSVD24
AV5
AV10
RSVD25
AT8
RSVD26
RSVD27
AY5
BA2
RSVD28
RSVD29
AT12
BF3
DGPU_PWR_EN
2
1K_0402_5%
For Optimus
<47,58> DGPU_PWR_EN
<36>
RF_OFF#
<34>
ODD_DA#
INT.PD 20K
T80 PAD
<5,36,37,38,40,44,45> PLT_RST#
1
1
1
1
2
5P_0402_50V8C
@ CH29
CH22
1
ODD_DA#
1
CH15
2
@
47P_0402_50V8J
22_0402_5%
22_0402_5%
22_0402_5%
<44> CLK_PCI_EC
<26> CLK_PCILOOP
<45> CLK_PCI_DDR
1 CH104
IN1
2
IN2
G
P
1
D
PLTRST_VGA# <13>
1
5
2
OPT@
3
2
1
RH285
0_0402_5%
DGPU_RST#
2
<30,47,58> VGA_PWROK
OPT@
1
2
CH30
0.1U_0402_10V7K
UH6
OPT@
2
1
O 4 RH286
0_0402_5%
RH288
100K_0402_5%
OPT@
2
RH287
1K_0402_5%
@
DIS@
PLT_RST#
2
RH170
NV_ALE
PLTRST_VGA#
1
0_0402_5%
RH173
100K_0402_5%
K40
K38
H38
G38
PIRQA#
PIRQB#
PIRQC#
PIRQD#
DGPU_RST#
PCH_GPIO52
DGPU_PWR_EN
C46
C44
E40
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
RF_OFF#
PCH_GPIO53
PCH_GPIO55
D47
E42
F46
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
USBRBIAS#
C33
USBBIAS
USBRBIAS
B33
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
EHCI 2
INT.PU 20K
INT.PU 20K
INT.PU 20K
PCI_PME#
PLT_RST#
C6
2 RH167 CLK_EC_R
2 RH166 CLK_PCH
2 RH292 CLK_SIO
H49
H43
J48
K42
H40
@
1 RH293
RF_OFF#
1K_0402_5% 2
@
1 RH294
PCH_GPIO19
PME# INT.PU
20K
PLTRST#
INT.PD
CLKOUT_PCI0
INT.PD
CLKOUT_PCI1
INT.PD
CLKOUT_PCI2
INT.PD
CLKOUT_PCI3
INT.PD
CLKOUT_PCI4
20K
20K
20K
20K
20K
<39>
<39>
<39>
<39>
<34>
<34>
<34>
<34>
USB-Left1
Intel Anti-Theft Techonlogy
USB-Left2
High=Endabled
Low=Disable(floating)
*
USB-RIGHT1
+1.8VS
1 @
RH164
NV_ALE
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13
USB20_N8 <35>
USB20_P8 <35>
USB20_N9 <36>
USB20_P9 <36>
USB20_N10 <36>
USB20_P10 <36>
USB20_N11 <22>
USB20_P11 <22>
USB20_N12 <36>
USB20_P12 <36>
USB20_N13 <22>
USB20_P13 <22>
1
RH165
C
NV_ALE
USB-RIGHT2
2
1K_0402_5%
Finger Printer
WiMax
TV Tuner #1
Int. Camera
3G/ TV tuner #2
Glasses free 3D Panel
2
22.6_0402_1%
Within 500 mils
USB_OC#0
USB_OC#1
USB_OC#2
SLP_CHG_M3
SLP_CHG_M4
USB_OC#5
USB30_SMI#
USBA30_SMI#
B
USB_OC#0 <39,44> USB-Right
USB_OC#1 <34,40,44>USB-Left
+3VALW_PCH
SLP_CHG_M3 <34>
SLP_CHG_M4 <34>
USBA30_SMI# <40>
HM76R3@
RF_OFF#
PLT_RST#
1K_0402_5% 2
K10
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB_OC#0
1
RH209
SLP_CHG_M3 1
RH196
SLP_CHG_M4 1
RH200
USB30_SMI# 1
RH192
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
USB_OC#1
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
Boot BIOS Strap
@
2
@
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
EHCI 1
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
by ESD requestion and place near CPU
0.1U_0402_10V7K
+3VS
RH284
0_0402_5%
OPT@
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
B
2
330P_0402_50V7K
1
RSVD5
RSVD6
AT10
BC8
1
8.2K_0402_5%
1
8.2K_0402_5%
1
8.2K_0402_5%
1
8.2K_0402_5%
1
PCH_GPIO4
USB
RH318
2
RH319
2
RH320
2
RH321
2
PCI
8.2K_0402_5%
1
8.2K_0402_5%
1
8.2K_0402_5%
1
8.2K_0402_5%
1
AY7
AV7
AU3
BG4
1
+3VS
RSVD1
RSVD2
RSVD3
RSVD4
2
D
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
PCH_GPIO19 <25>
PCH_GPIO19
0
0
1
1
0
1
0
1
Boot BIOS Loaction
1
RH177
1
RH183
USB_OC#5
1
RH186
USBA30_SMI# 1
RH188
LPC
USB_OC#2
Reserved
PCI
SPI
*
A
A
1K_0402_5% 2
@
1 RH295
PCH_GPIO55
A16 Swap Override Strap
WL_OFF#
Low= A16 swap override Enable
High= A16 swap override Disable
*
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
29
of
61
4
3
@
1 RH296 2
100K_0402_5%
<13,24,28> HDMI_HPD
EC_LID_OUT#
PCH_GPIO6
PCH_GPIO12
HDD2_DET#
1
RH178
1
RH197
1
RH179
1
RH303
1
RH194
@
1
RH181
1
RH195
1 DIS@
RH193
C
B
20K
E38
TACH3 / GPIO7INT.PH
C10
GPIO8
<36>
C40
TACH5 / GPIO69
B41
TACH6 / GPIO70
C41
TACH7 / GPIO71
A40
C4
LAN_PHY_PWR_CTRL / GPIO12
EC_LID_OUT#
G2
GPIO15 INT.PD
INT.PH 20K
20K
A20GATE
INT.PD 350
U2
VGA_PWROK
D40
BT_ON#
<34> ODD_DETECT#
<36> ISDBT_DET
PECI
SATA4GP / GPIO16
T5
SCLOCK / GPIO22
E8
GPIO24
20K
E16
GPIO27 INT.PH
20K
P8
GPIO28 INT.PH
20K
BT_ON#
K1
STP_PCI# / GPIO34
PCH_GPIO35
K4
GPIO35
P4
KB_RST#
AY11
H_PWRGOOD
THRMTRIP#
AY10
PCH_THRMTRIP# 1
RH191
AY1
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
TS_VSS4
AK10
PCH_GPIO37
M5
SATA3GP / GPIO37 INT.PD
OPTIMUS_EN#
N2
SLOAD / GPIO38
CIR_EN#
M3
SDATAOUT0 / GPIO39
V13
20K
GATEA20 <44>
P5
INT.PD 20K DF_TVS
SATA2GP / GPIO36 INT.PD 20K
GATEA20
AU16
T14
V8
NC_1
P37
SDATAOUT1 / GPIO48
VSS_NCTF_15
BG2
PCH_GPIO49
V3
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
BG48
HDD2_DET#
D6
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
L
3D_DET#
D
INIT3_3V#
ODD_DETECT#
3D_DET#
GATEA20
KB_RST#
PROCPWRGD
INT.PH 20K
PCH_GPIO28
Follow Compal ORB
and Intel Check list 460603 V1.5
H
INT.PH
TACH0 / GPIO17
PCH_GPIO27
ISDBT_DET
ODD_EN# <47>
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
INT.PH 20K
PCH_GPIO12
PCH_GPIO16
ODD_EN#
INT.PH 20K
RCIN#
T81 PAD
3D_DET#
TACH4 / GPIO68
INT.PH 20K
1
RH297
1
RH182
1
RH184
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
KB_RST# <44>
H_PWRGOOD <5>
2
390_0402_5%
H_THERMTRIP# <5>
RH203
10K_0402_5%
OPTHD@
This signal has weak internal
pull-up, can't be pulled low
NV_CLE
1
RH203
1
RH304
3D_DET#
+3VS
OPTFHD@
2
10K_0402_5%
2
3D@ 10K_0402_5%
C
DMI & FDI Termination Voltage
Set to VCC when HIGH
NV_CLE
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
Set to VSS when LOW
+1.8VS
B
RH187
2.2K_0402_5%
2
*
20K
EC_SMI#
BT_DET#
On-Die PLL Voltage Regulator
H: Enable
L: Disable
TACH2 / GPIO6INT.PH
EC_SCI#
GPIO28
20K
EC_SMI#
For Optimus
ODD_DETECT#
200K_0402_5%
PCH_GPIO6
2
10K_0402_5%
PCH_GPIO16
2
10K_0402_5%
EC_SCI#
2
10K_0402_5%
CIR_EN#
2
100K_0402_5%
ISDBT_DET
2
10K_0402_5%
PCH_GPIO49
2
10K_0402_5%
OPTIMUS_EN#
2
10K_0402_5%
TACH1 / GPIO1INT.PH
EC_SCI#
2
PCH_GPIO37
2
1
RH198
100K_0402_5%
@
PCH_GPIO27
2
1
RH199
10K_0402_5%
CIR_EN#
2 CIR@ 1
RH306
10K_0402_5%
ISDBT_DET
1
2
RH307
47K_0402_5%
OPTIMUS_EN#
2 OPT@ 1
RH201
10K_0402_5%
H36
BMBUSY# / GPIO0
<44>
BT_ON#
2
10K_0402_5%
HDMI_HPD
2
10K_0402_5%
PCH_GPIO1
2
10K_0402_5%
BT_DET#
2
10K_0402_5%
A42
<44>
<44> EC_LID_OUT#
@
T7
PCH_GPIO1
+3VS
1
RH180
1
RH301
1
RH190
1
RH185
HDMI_HPD
EC_SMI#
PCH_GPIO28
ODD_EN#
INT.PH 20K
CPU/MISC
D
1
1K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
+3VS
UH1F
GPIO
2
RH204
1
RH205
1
RH298
1
RH202
1
RH207
1
1
+3VALW_PCH
2
NCTF
5
RH206
1
@
2 1K_0402_5% PCH_GPIO28
SKU
Non3D
3D
NV_CLE
2
RH189
1
1K_0402_5%
H_SNB_IVB# <5>
HM76R3@
*
GPIO8
OPTIMUS_EN#
Integrated Clock Chip Enable (Removed)
H: Disable
L: Enable
OPTIMUS_EN#
H
L
HDD2_DET#
SKU
NonOPT
Optimus
SKU
RH308 1
A
@
2 1K_0402_5%
EC_SMI#
HDD2_DET#
H
L
ONE HDD
TWO HDD
A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
B
Date:
5
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
30
of
61
5
4
3
POWER
UH1G
+1.05VS_VCCP
1
CH34
1
10U_0603_6.3V6M
2
2
2
1U_0402_6.3V6K
2
1U_0402_6.3V6K
+1.05VS_PCH
PAD
C
+1.05VS_PCH
CH43
10U_0603_6.3V6M
1
CH45
2
1
CH46
2
1
CH47
2
1U_0402_6.3V6K
1
2
CH44
1
AN16
VCCIO[15]
AN17
VCCIO[16]
CH35
0.01U_0402_25V7K
2
1mA
VCCALVDS
AK36
VSSALVDS
AK37
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
VCCTX_LVDS[3]
AP36
RH3101 DIS@
+VCCTX_LVDS
1
AN26
VCCIO[18]
AN27
VCCIO[19] 3709mA
VCC3_3[6]
V33
VCC3_3[7]
V34
1
VCCIO[21]
VCCIO[22]
1
VCCIO[24]
+VCCAFDI_VRM
VCCDMI[1]
AT20
VCCCLKDMI
AB36
+1.05VS_VCC_DMI
1
AN33
VCCIO[25]
AN34
VCCIO[26]
VCCDFTERM[1]
AG16
VCC3_3[3]
VCCDFTERM[2]
AG17
+VCCAFDI_VRM
This pin can be left as NC if
On-Die VR is enabled (Default)
PAD
AP16
VccAFDIPLL
AP17
+1.05VS_PCH
VCCIO[27]
AU20
+VCCP_VCCDMI
B
VCCVRM[2]
BG6
T83
RH221
0_0603_5%
2
VCCDMI[2]
RH213 +1.05VS_VCCP
0_0603_5%
1
2
RH214
2
1
0_0805_5%
AJ16
VCCDFTERM[4]
AJ17
5
0.001
Vcc3_3
3.3
0.228
VccADAC
3.3
0.063
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.7
VccDMI
1.1
0.047
VccIO
1.05
3.711
VccASW
1.05
0.903
VccSPI
3.3
0.01
C
1
2
CH48
1U_0402_6.3V6K
VccDSW
3.3
0.001
VccDFTERM
1.8
0.002
VccRTC
3.3
N/A
VccSus3_3
3.3
0.095
VccSusHDA
3.3
0.01
VccVRM
1.5
0.167
VccCLKDMI
1.05
0.07
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
+1.8VS
1
VCCDFTERM[3]
0.001
CH49
1U_0402_6.3V6K
VCCDFTERM
190mA
5
+1.5VS
1
+VCCP_VCCDMI
2
CH50
0.1U_0402_10V7K
2
CH39
0_0402_5%
DIS@
+1.05VS_PCH
75mA
D
CH42
0.1U_0402_10V7K
1U_0402_6.3V6K
BH29
2
CH40
22U_0805_6.3V6M
OPT@
+VCCP_VCCDMI
VCCIO[23]
AT24
+3VS
CH39
OPT@
VCCIO[20]
AP24
0.001
V5REF_Sus
+1.8VS
LH2 OPT@
2
1
BLM18PG181SN1D_0603
+VCCAFDI_VRM
AT16
S0 Iccmax
Current (A)
1.05
V5REF
2
VCCVRM[3]
Voltage
2 0_0402_5%
0.01U_0402_25V7K
CH38
AP37 0.01U_0402_25V7K
OPT@
Voltage Rail
V_PROC_IO
RH208
1 0_0603_5%
2
OPT@
+VCCA_LVDS
PCH Power Rail Table
Refer to PCH EDS R1.0
2
+3VS
VCCIO[17]
AP23
LH1
2+VCCA_DAC_R2
1
1_0603_1%
BLM18PG181SN1D_0603
1
CH37
10U_0603_6.3V6M
1
+3VS
60mA
AN21
AP26
1U_0402_6.3V6K
2
U47
0.1U_0402_10V7K
1
CH36
+VCCA_DAC
VCCAPLLEXP
AP21
1U_0402_6.3V6K
VSSADAC
VCCIO[28]
BJ22
T82
VCCADAC
U48
VCCTX_LVDS[4]
AN19
CRT
CH31
LVDS
1
HVCMOS
CH33
D
DMI
JUMP_43X118
1
CH32
+3VS
1mA
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
DFT / SPI
1
VCC CORE
2
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
1
RH309
1300mA
+1.05VS_PCH
1U_0402_6.3V6K
1
VCCIO
2
@
FDI
PJ4
2
2
CH51
0.1U_0402_10V7K
+3VS
20mA
VCCSPI
V1
1
2
B
CH53
1U_0402_6.3V6K
HM76R3@
+3VALW to +3V_PCH
+3VALW
+3VALW_PCH
PJ2
2
@
2
1
1
JUMP_43X79
QH8
AO3413_SOT23
@
1
2
1
@
2
2
RH316
20K_0402_5%~D
1
1
CH98
0.1U_0402_10V7K~D
2
CH99
0.01U_0402_25V7K
2
CH102
0.1U_0402_10V7K~D
2
1
47K_0402_5%
1
0.1U_0402_25V6
PCH_PWR_EN#
<32,37,47> PCH_PWR_EN#
CH97
A
3
G
2
RH317
D
S
1
A
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
31
of
61
5
4
3
2
1
+5VALW
+5VALW_PCH
JUMP_43X39
@ PJ5
+3VS
2
QH6
DCPSUSBYP
T38
VCC3_3[5]
CH64
1
CH65
1
22U_0805_6.3V6M
2
2
22U_0805_6.3V6M
C
1U_0402_6.3V6K
1
1
1
CH67
CH68
CH69
+1.05VS_PCH
1U_0402_6.3V6K
2
2
1U_0402_6.3V6K
2
LH7
CH93
+1.05VS_VCCADPLLB
1
CH94
1
CH95
1
VCCIO[14]
1
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
+1.05VS_PCH
RH244
+VCCDIFFCLK
1
0_0603_5%
1
+VCCRTCEXT
CH79
1U_0402_6.3V6K
CH78
0.1U_0402_10V7K
2
B
VCCASW[11]
AD29
W23
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
+VCCAFDI_VRM
Y49
VCCSUS3_3[7]
119mA VCCSUS3_3[8]
T24
VCCSUS3_3[9]
V23
2
RH328
1
2
1
47K_0402_5%
<31,37,47> PCH_PWR_EN#
+3VALW_PCH
2
VCCSUS3_3[6]
VCCIO[34]
T26
V5REF_SUS
M26
+PCH_V5REF_SUS
DCPSUS[4]
AN23
+VCCA_USBSUS
VCCSUS3_3[1]
AN24
2
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
RH232
10_0402_5%
CH62 1
AA16
VCC3_3[8]
W16
VCC3_3[4]
T34
VCCIO[12]
AH13
VCCIO[13]
AH14
VCCVRM[4]
VCCIO[6]
AF14
2
2
+PCH_V5REF_SUS
CH63
0.1U_0402_10V7K
C
+5VS
+3VS
RH237
10_0402_5%
+3VS
1
+3VS
CH63 & CH71 are
different by Intel CRB.
DH4
CH72
0.1U_0402_10V7K
+PCH_V5REF_RUN
1
2
2
DCPRTC
1
CH70
1U_0402_6.3V6K
2
CH71
1U_0603_10V6K
+3VS
+1.05VS_SATA3
1
AF13
+3VALW_PCH
AJ2
VCCIO[5]
DH3
2
0.1U_0402_10V7K
+PCH_V5REF_RUN
1
2
CH75
0.1U_0402_10V7K
VCC3_3[2]
2 1U_0402_6.3V6K
+3VALW_PCH
1
VCC3_3[1]
+3VALW_PCH
+1.05VS_PCH
1
CH66
1mA V5REF
1
CH61
0.1U_0402_10V7K
@
P34
D
Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
1
V24
P24
1mA
@
+3VALW_PCH
CH60
0.1U_0402_10V7K
2
VCCSUS3_3[10]
1010mA
VCCASW[15]
W24
1
T29
2
1
+5VALW_PCH
AA24
CH96
1U_0402_6.3V6K
VCCIO[33]
VCCASW[1]
VCCASW[2]
1U_0402_6.3V6K
2
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
2
DCPSUS[3]
AA21
AC31
+1.05VS_VCCADPLLA
1
2
BLM18PG181SN1D_0603
LH8
1
2
BLM18PG181SN1D_0603
VCCAPLLDMI2
AL29
AA19
T27
1
CH56
1U_0402_6.3V6K
1
2
+1.05VS_PCH
BH23
AL24
CH54
1U_0402_6.3V6K
@
VCCIO[32]
1
2
+VCCSUS
1
VCCIO[31]
P28
T23
USB
T85
Clock and Miscellaneous
PAD
+1.05VS_PCH
P26
RH228
20K_0402_5%~D
V12
PCI/GPIO/LPC
+3VS_VCC_CLKF33
N26
VCCIO[30]
3mA
VCCDSW3_3
0.1U_0402_10V7K
VCCIO[29]
G
+PCH_VCCDSW
VCCACLK
2
AD49
T16
2
@
CH58
2
1
"@" Avoid leakage
T84
CH55
0.1U_0402_10V7K
CH80
0.1U_0402_10V7K~D
1
D
AO3413_SOT23
1
3
2
+1.05VS_PCH
CH59
0.1U_0402_10V7K~D
POWER
UH1J
PAD
2
+3VALW_PCH
1
CH74
1U_0402_6.3V6K
D
2
1
2
CH73
10U_0603_6.3V6M
S
2
1
1
1
2
2
+3VS_VCC_CLKF33
1
1
LH5
1
2
10UH_LB2012T100MR_20%
+1.05VS_PCH
RH242
CH76
0.1U_0402_10V7K
2
1
+1.05VS_SATA3
1
0_0805_5%
CH77
1U_0402_6.3V6K
2
B
+1.05VS_VCCADPLLA
BD47
VCCADPLLA
+1.05VS_VCCADPLLB
BF47
VCCADPLLB
RH247
+1.05VS_VCCDIFFCLKN
1
1
0_0603_5%
CH81
1U_0402_6.3V6K
+VCCDIFFCLK
2
+1.05VS_VCCDIFFCLKN
+1.05VS_PCH
CH84
1U_0402_6.3V6K
AF17
AF33
AF34
AG34
55mA
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
AG33
VCCSSC
1
1
2
2
80mA
80mA
+VCCSST
V16
DCPSST
0.1U_0402_10V7K
+1.05VM_VCCSUS
CH85
T17
V19
DCPSUS[1]
DCPSUS[2]
0_0603_5%
+1.05VM_VCCSUS
1
A
2
CH83
1U_0402_6.3V6K
@
0_0603_5%
CH86
4.7U_0603_6.3V6K
0.1U_0402_10V7K
1
CH87
2
1
2
1
CH88
1mA
+V_CPU_IO
BJ8
V_PROC_IO
+RTCVCC
+VCCAFDI_VRM
VCCVRM[1]
+VCCAFDI_VRM
VCCIO[2]
AC16
+1.05VS_VCC_SATA
VCCIO[3]
AC17
VCCIO[4]
AD17
+1.05VS_VCC_SATA
+1.05VS_PCH
RH246
2
1
0_0805_5%
1
CH82
1U_0402_6.3V6K
T21
+VCCME_22
RH3112
1 0_0402_5%
VCCASW[23]
V21
+VCCME_23
RH3122
1 0_0402_5%
VCCASW[21]
T19
+VCCME_21
RH3142
1 0_0402_5%
VCCASW[22]
CPU
RH313 @
2
1
RH249
2
T86
AF11
+1.05VS_PCH
+3VALW_PCH
0.1U_0402_10V7K
0.1U_0402_10V7K
2
CH89
1
1U_0402_6.3V6K
2
CH90
1
1
2
2
A22
VCCRTC
RTC
1
AK1
PAD
2
+1.05VS_VCCP
+1.05VS_PCH
VCCAPLLSATA
95mA
HDA
2
MISC
+1.05VS_VCCDIFFCLKN
SATA
2
+1.05VS_PCH
10mA
VCCSUSHDA
P32
1
HM76R3@
0.1U_0402_10V7K
CH91
A
CH92
0.1U_0402_10V7K
2
unmount CH83 by follow Compal ORB abd Intel CRB
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
32
of
61
5
4
3
2
1
UH1I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
UH1H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
D
C
B
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
HM76R3@
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
D
C
B
HM76R3@
A
A
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HG
Date:
5
4
3
2
Sheet
1
33
of
61
5
SATA HDD
Conn.
+5VS
2
Close to JHDD
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
C369 1
C367 1
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
15
14
GND
GND
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
C376 1
C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
C378 1
C375 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD_DETECT# <30>
+3VS
2
+5VALW
W=80mils
+USB_VCCA
OUT
OUT
OUT
OCB
6
7
8
5
2
C361
1
1000P_0402_50V7K
1
SY6288DCAC_MSOP8
C362
4.7U_0805_10V4Z
2 @
SA00004KB00
SA00003TV00
0
0
Pass-Through (USB) Mode:
Connect DP/DM to TDP/TDM
2
3
4
1
IN
IN
EN/ENB
GND
US20_P3
B
US20_P2
1 @
L56
Force Apple 2A Charger Mode: Apple 2A resistor dividers
R1458 0_0402_5% IUSB30@
USB20_N3
1
2
R1459 0_0402_5% IUSB30@
USB20_P3
1
2
USB20_N3 <29>
R1462 0_0402_5%
U2D_DN3
1EUSB30@ 2
R1463 0_0402_5%
U2D_DP3
1EUSB30@ 2
U2D_DN3 <40>
<29> U3RXDN4_R
R1460 0_0402_5% IUSB30@
USB20_N2
1
2
R1461 0_0402_5% IUSB30@
USB20_P2
1
2
USB20_N2 <29>
R1464 0_0402_5%
U2D_DN2
1EUSB30@ 2
R1465 0_0402_5%
U2D_DP2
1EUSB30@ 2
U2D_DN2 <40>
1
2
3
4
9
CEN
DM
DP
CB1
PGND
<29> U3TXDP4
U3TXDP4
1
C903
1
4
4
2U3TXDP4_C
0.1U_0402_10V7K
1 @
L60
USB20_P2 <29>
<29> U3TXDN4
U3TXDN4
1
C904
2U3TXDN4_C
0.1U_0402_10V7K
1
1
4
4
8
7
6
5
SLP_CHG_M4
US20_N3
US20_P3
1 @
SLP_CHG_M4 <29>
+5VALW
1
C892
MAX14600ETA+T_TDFN-EP8_2X2
14600@
0.1U_0402_10V7K
2
<29> U3RXDN3_R
U3TXDP3
1
C905
MAX14617ETA+T
U8
14617@
1
1
4
4
2U3TXDP3_C
0.1U_0402_10V7K
1 @
L59
IUSB30@
CB0
TDM
TDP
VCC
C364
4.7U_0805_10V4Z
2 @
2 R1448
0_0402_5%
IUSB30@
2 2
3
8
7
6
5
SLP_CHG_M4
US20_N2
US20_P2
+5VALW
1
C893
MAX14600ETA+T_TDFN-EP8_2X2
14600@
0.1U_0402_10V7K
2
<29> U3TXDN3
2 R1450
0_0402_5%
IUSB30@
2 2
3
C911
220U_6.3V_M_R15
U3RXDP4
U3TXDN3
1
C906
2U3TXDN3_C
0.1U_0402_10V7K
2
0_0603_5%
R1445
R1444
1
JUSBRF
U3TXDP3_C_L
1
C900
2
+USB_VCCC
1
C901
2
9
1
8
2
7
3
6
4
5
U3TXDN3_C_L
USB20_N2_S_R
USB20_P2_S_R
U3RXDP3
U3RXDN3
SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-
10
11
12
13
GND
GND
GND
GND
1000P_0402_50V7K
C
W=80mils
USB1_GND
OCTEK_USB-09EAEB
0_0603_5%
@
0_0603_5%
R1447
2
1
U3RXDP4 <40>
R73
1
0_0402_5%
2
@
L53
U3RXDN4
U3TXDP4_C_L
U3TXDP4_C_L <40>
D87
U3TXDP4_C_L 1 1
@
U3TXDN4_C_L 2 2
U3TXDN4_C_L
USB20_P3_S
3
USB20_N3_S
2
3
4
4
USB20_P3_S_R
1
1
USB20_N3_S_R
U3RXDN4 <40>
3
2 R1452
0_0402_5%
IUSB30@
2 2
3
109
U3TXDP4_C_L
98
U3TXDN4_C_L
U3RXDP4
4 4
77
U3RXDP4
U3RXDN4
5 5
66
U3RXDN4
U3TXDN4_C_L <40>
2
B
WCM-2012-900T_0805
1
R87
R77
1
3 3
1
1
4
4
3
U3RXDP3
@
2
0_0402_5%
0_0402_5%
2
@
L54
8
USB20_P2_S
3
3
4
4
USB20_P2_S_R
USB20_N2_S
2
2
1
1
USB20_N2_S_R
WCM-2012-900T_0805
U3RXDP3 <40>
D88
U3TXDP3_C_L 1 1
3
2 R1454
0_0402_5%
IUSB30@
2 2
U3RXDN3
U3TXDP3_C_L
U3RXDN3 <40>
1
R88
@
109
U3TXDP3_C_L
U3TXDN3_C_L 2 2
98
U3TXDN3_C_L
U3RXDP3
4 4
77
U3RXDP3
U3RXDN3
5 5
66
U3RXDN3
USB20_N3_S_R 3
3 3
U3TXDP3_C_L <40>
@
2
0_0402_5%
D85
USB20_P3_S_R 2
@
2
1
1
3
AZC199-02SPR7G_SOT23-3
8
YSCLAMP0524P_SLP2510P8-10-9
@D86
@
D86
USB20_P2_S_R 2
2
3
KINGCORE WCM-2012HS-670T
1
2 R1455
@
0_0402_5%
U3TXDN3_C_L
USB20_N2_S_R 3
U3TXDN3_C_L <40>
A
1
1
3
IUSB30@
Compal Secret Data
Issued Date
2011/12/14
2012/12/31
Deciphered Date
Title
Size
MAX14617ETA+T
Date:
5
USB0_GND
OCTEK_USB-09EAEB
0_0603_5%
@
3
1
2 R1453
@
0_0402_5%
U8
CEN
DM
DP
CB1
PGND
+
2
1
W=80mils
U2D_DP2 <40>
<29> U3TXDP3
1
2
3
4
9
1
1000P_0402_50V7K
10
11
12
13
GND
GND
GND
GND
1000P_0402_50V7K
IUSB30@
0_0402_5%
2 14617@ 1
R1471
SLP_CHG_CB2A
USB20_N2_S
USB20_P2_S
SLP_CHG_M3
A
U3RXDN4
2
0.1U_0402_10V7K
For EMI
USB_OC#1
1
2 R1451
@
0_0402_5%
L58
CB0
TDM
TDP
VCC
2
C363
1
2 R1449
@
0_0402_5%
USB20_P3 <29>
U2D_DP3 <40>
1
U5
14617@
USB20_P3_S_R
U3RXDP4
R1446
<29> U3RXDP3_R
SLP_CHG_CB2
USB20_N3_S
USB20_P3_S
SLP_CHG_M3
6
7
8
5
SA00004KB00
SA00003TV00
IUSB30@
US20_N2
OUT
OUT
OUT
OCB
SY6288DCAC_MSOP8
Pass-Through (USB) Mode with CDP Emulation:
Auto Connect DP/DM to TDP/TDM depending on CDP status
1
US20_N3
U5
C365
@
SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-
1
USB_CHG_EN#
Force Dedicated charger mode
(MODE3)
0
X
<29> SLP_CHG_M3
220U_6.3V_M_R15
2
1
1
<29> U3RXDP4_R
1 14617@ 2
R1470
0_0402_5%
2
C899
9
1
8
2
7
3
6
4
5
U3TXDN4_C_L
USB20_N3_S_R
2
1
X
2
1
C898
W=80mils
+USB_VCCC
U15
AUTO MODE
0
C360
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
C897
W=80mils
2.5A
2
1
C380
0.1U_0402_10V7K
C902
1
+5VALW
STATUS
1
0.1U_0402_10V7K
CB2
(14617 only)
0
0
1
C379
@
10U_0805_10V4Z 1U_0402_6.3V6K
2
2
C354
+USB_VCCC
CB1
SLP_CHG_M3
1
+
USB_OC#1 <29,40,44>
MAX14600 & MAX14617
0
4.7U_0805_10V4Z
1
IN
IN
EN/ENB
GND
10U_0805_10V4Z
C894
<40,44> USB_CHG_EN#
0.1U_0402_10V7K
For EMI
U14
2
3
4
1
C355
JUSBRR
W=80mils
2.5A
1
U3TXDP4_C_L
+USB_VCCA
+USB_VCCA
USB Sleep & Charge Auto-Mode/Mode3
0
1
USB Right-Side
+5VS
Place components closely ODD CONN.
1.1A
ODD_DA# <29>
SANTA_204901-1
@
SANTA_190501-1
@
CB0
SLP_CHG_M4
+5VS_ODD
+5VS_ODD
ODD_DA#
D
2
GND
A+
AGND
BB+
GND
JODD
C359
0.1U_0402_10V7K
1
2
1
2
C358
0.1U_0402_10V7K
1
2
1
2
C357
0.1U_0402_10V7K
JHDD
C
1
1
1
C356
10U_0805_10V4Z
D
GND
GND
2
Place closely JHDD SATA CONN.
2
23
24
3
SATA ODD Conn
1.2A
1
4
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
34
of
61
5
4
3
2
1
D
C
B-CAS Circuit
+5VS
1
+5VALW
2
4
1
5
current = 0A
QS1
AO3413_SOT23
BCAS@
+5VS_BCAS
+5VS_L_BCAS
1
2
3
BCPWON
1
RS7
10K_0402_5%
BCAS@
2
RS8
2.2K_0402_5%
BCAS@
2
CS3 BCAS@
4.7U_0603_6.3V6K
CS4
1
0.1U_0402_10V7K
BCAS@ 2
+5VS_L_BCAS
LS1 BCAS@
1
2
1 FBMA-L11-201209-221LMA30T_0805
2
CS5
BCAS@
1U_0402_6.3V6K
2
BCPWON
G
<36>
1
47K_0402_5%
1
BCAS@
QS2B
CS2
BCAS@
2
0.01U_0402_25V7K
BCAS@
2N7002DW-T/R7_SOT363-6
3
2
RS5
2
D
100K_0402_5%
1
Inrush
1 BCAS@
CS1
0.1U_0402_10V7K
BCAS@ RS2
S
C
D
+5VS_L_BCAS
B
5
B
BCRSTM
IN2
US1 BCAS@
Finger printer
P
IN1
O
4
G
<36>
1
BCRSTM 2
B_R_BCRST 1 BCAS@ 2
B_BCRST
RS9
100_0402_5%
B_BCRST
<36>
@
JFP
O
IN2
4
+3VS
B_R_XBCCLK1 BCAS@ 2
B_XBCCLK
RS11
100_0402_5%
B_XBCCLK <36>
USB20_N8
USB20_P8
D82
3
<29>
<29>
+3VS_FP
USB20_N8
USB20_P8
1
XBCLKM
IN1
1 R134
2
0_0603_5% 1
C480
FP@
0.1U_0402_10V7K
FP@
2
1
3
3
2
2
1
<36>
CPLGP1
CPLGP1
3
A
BCIO
BCIO
<36>
C
1
2
RS14
BCAS@
1.5K_0402_5%
QS2A
BCAS@
2
2N7002DW-T/R7_SOT363-6
2
1
2
RS13 BCAS@ B
10K_0402_5%
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
5
JOINT_F1017WR-S-04P
1
6
10K_0402_5%
1
2
RS12
BCAS@
10K_0402_5%
QS4 BCAS@
2SB1197K_SOT23-3
1
+5VS_L_BCAS
E
BCAS@
2
4
3
2
1
For ESD
+5VS_L_BCAS
RS1
1
GND
GND
4
3
2
1
R133
0_0603_5%
FP@
@
A
FP_GND
6
5
2
<36>
2
G
1
XBCLKM
US2 BCAS@
P
5
3
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
35
of
61
6
2
BT_CTRL
QM1B
2
5
BT_ON#
For SED
1
<5,9,47> SUSP
+3VS
1
0.1U_0402_10V7K
1
1
CM27
CM7
CM8
47P_0402_50V8J
2
2
2
@
4.7U_0805_10V4Z
0.01U_0402_25V7K
CM9
CM28
47P_0402_50V8J
2
2
@
4.7U_0805_10V4Z
<44> TMPTU2_SXP
+16VS
BT_CTRL
+1.5VS
+3V_WLAN
JWLAN
<26> PCIE_PRX_WLANTX_N2
<26> PCIE_PRX_WLANTX_P2
<26> PCIE_PTX_C_WLANRX_N2
<26> PCIE_PTX_C_WLANRX_P2
WLAN/ WiFi
+3V_WLAN
RM25
10_0402_5%2
1
2
0_0402_5%
RM26
<44,45> E51_TXD
<44,45> E51_RXD
E51_RXD_R
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
GNDGND
54
Debug card using
E51_RXD_R
1
For isolate Intel Rainbow Peak and
Compal Debug Card.
1
RM16 2
0_0603_5%
BCAS@
RM15 2
0_0603_5%
BCAS@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
GNDGND
54
1 BCAS@ 2
RM21
470_0402_5%
WLAN_OFF#
PLT_RST#
USB20_N9 <29>
USB20_P9 <29>
LED_WIMAX#
1
CM13
0.1U_0402_10V7K
3G@
WiMax
1
DM1
RLZ20A_LL34
3G@
LED_WIMAX#
CPLGP1
2
LED_WIMAX# <46>
1
1
2
2
USB20_P10 <29>
USB20_N10 <29>
USB--3G/TV#1
COMMON
BCIO
1 BCAS@ 2
RM7
0_0402_5%
2
0_0402_5%
1
+UIM_PWR
+UIM_PWR
RM2
4.7K_0402_5%
@
@
GND
VPP
I/O
4
5
6
NC
8
UIM_VPP
SIM_DATA
NC
1
2
CM16
10P_0402_50V8J
2 3G@
2
RM35
<35>
<35>
B_XBCCLK
B_XBCCLK
BCIO
TV@ 2 0_0402_5%
2 0_0402_5%
TV@
1 3G@
RM5
1 BCAS@
RM8
2
0_0402_5%
2
0_0402_5%
SIM_RESET
1 3G@
RM9
1 BCAS@
RM10
2
0_0402_5%
2 SIM_CLK
0_0402_5%
SIM_CLK
1 3G@
RM11
1 BCAS@
RM12
2
0_0402_5%
2
0_0402_5%
SIM_DATA
PCIE_PRX_C_TVTX_P6
PCIE_PRX_C_TVTX_N6
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
+VCC_SIM
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
PCIE_PRX_C_TVTX_P6 <26>
PCIE_PRX_C_TVTX_N6 <26>
TV@
1
10K_0402_5%
RM33 1
RM34 1
G
To avoid LED flashing
UIM_CLK
UIM_DATA
MSATA@
CM21 1
CM22 1
MSATA@
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
+3VS
+3VS
B_BCRST
B_BCRST
CM14
22P_0402_50V8J
@
RM31 1
RM32 1
RM29
200K_0402_5%
WIMAX@
UIM_RESET
<35>
MOLEX_47273-0001~D
1 @
2
+3VS
RM6
100K_0402_5%
1
2
+5VS
RM28
100K_0402_5%
WIMAX@
1 BCAS@ 2
RM4
0_0603_5%
1 3G@
2
RM1
0_0603_5%
+5VS_BCAS
2
0.1U_0402_25V4Z
BCIO
Close to J3GTV
ISDBT_DET <30>
CM10
@
VCC
RST
CLK
1
1
USB--TV#2
CPLGP1 <35>
TMPTU1_SXP <44>
please place near J3GTV
1
0_0402_5%
UIM_VPP
2
RM30
0_0402_5%
TV@
1 MSATA@2
RM14
0_0402_5%
0.01U_0402_50V7K
1
RM3
1 3G@
2 0_0402_5% PM_SMBCLK
2 0_0402_5% PM_SMBDATA
PLT_RST#
1 3G@
2
RM30
0_0402_5%
BCAS@
1 RM19 2 0_0402_5%
1 RM20 2 0_0402_5%
BCAS@
ISDBT_DET_R
1 TV@
RM13
7
CM15
10P_0402_50V8J
3G@ 2
RM17
1 3G@
1 3G@
RM18
CM20
47P_0402_50V8J
@
2
2
4.7U_0805_10V4Z
B-CAS
1
2
3
1
2
0.01U_0402_25V7K
<29>
USB20_N12 <29>
USB20_P12 <29>
+VCC_SIM
SIM_RESET
SIM_CLK
PM_SMBCLK <11,12,26,46>
PM_SMBDATA <11,12,26,46>
RF_OFF#
USB20_P10_TV
USB20_N10_TV
JSIM
PLT_RST# <5,29,37,38,40,44,45>
USB20_P10_TV
USB20_N10_TV
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
COMMON
ISDBT_DET_R
RF_OFF#
PLT_RST#_FULL
+16VS
Add BCCDET pull down
CM19
@
47P_0402_50V8J
2.75A
CM12 CM11
47P_0402_50V8J @
2
@
@
CLKREQ_Q_TV#
3
1
CLKREQ_TV# <26>
D
S
TV@
RCL8
0_0603_5%
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
ACES_51711-0520W-001
BCCDET
ACES_88914-5204
+3VALW
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1 RM27 2
1K_0402_5%
2
<26> CLK_WLAN#
<26> CLK_WLAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
BT_CTRL 10_0402_5%2BT_CTRL_R
@ RM24
<26> CLKREQ_WLAN#
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
4
1
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
CM3
<44> AOAC_WAKE#
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
2
0.01U_0402_25V7K
1
QM1A
2
CM2
For SED
1
0.1U_0402_10V7K
1
<30>
+1.5VS
2
1
CM1
2 0_0402_5%
<35> BCRSTM
<35> BCPWON
3
CM26
47P_0402_50V8J
@
@
3
1 RM23
H
<26> CLK_TV#
<26> CLK_TV
For RF
40 mils
L
BT_ON#
BCCDET
CLKREQ_Q_TV#
CM18
@
For SED
0.1U_0402_10V7K
1
1
1
CM4
CM5
CM6
1
<35> XBCLKM
1
4WLAN_OFF#
O
WL_OFF#
+3V_WLAN
L
1
IN2
H
BT_CRTL
47P_0402_50V8J
CM17
@
47P_0402_50V8J
+3VS
@
2
5
2
+1.5VS
P
IN1
G
1
WL_OFF#
<44>
1
Disable
120 mils
+1.5VS
For RF
JPCIF
+1.5VS
UM1
Enable
+3VS
Slot 2 Full PCIe Mini Card- 3G/ TV Tuner
2
+3V_WLAN
RM22
8.2K_0402_5%
<44,47> AOAC_EN#
CM25
47P_0402_50V8J
@
2
2
1
+3V_WLAN
BT
on module
2
Slot 1 Half PCIe Mini Card-WLAN/ WiMax
BT
on module
2
WLAN&BT Combo module circuits
+3V_WLAN
MSATA@
CM23 1
CM24 1
MSATA@
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
TV@ 2 0_0402_5%
2 0_0402_5%
TV@
PCIE_PTX_C_TVRX_N6
PCIE_PTX_C_TVRX_P6
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
PCIE_PTX_C_TVRX_N6 <26>
PCIE_PTX_C_TVRX_P6 <26>
QM2
2N7002_SOT23-3
2
1
1
2
RCL9
@
0_0603_5%
+3VALW_PCH
UCL1
+3VALW_GCLK
+3VL
8
3
+3V_LAN
+1.05VS_VCCP
CLK_X2
CLK_X1
0.1U_0402_10V7K
+3VL
0.1U_0402_10V7K
+1.05VS_VCCP
1
2
CCL3
GCLK@
1
2
2
15
CCL1
GCLK@
VDD
+V3.3A
VBAT
NC
VDDIO_25M_A
VDDIO_25M_B
1
16
XTAL_OUT
XTAL_IN
4
7
13
17
VSS
VSS
VSS
Thermal Pad
32K
NC
25M_B
25M_A
CCL11
22U_0805_6.3V6M
GCLK@
2
10
+RTCBATT
1 271@ 2
11
+3VS_280
RCL6
0_0402_5%
PCH_RTCX1_R
9
PCH_RTCX1_R <25>
OSC_IN_R_R
12
5
6
CCL10
5P_0402_50V8C
GCLK@
EMI request 11/06
VDD_RTC_OUT
14
SLG3NB271VTR TQFN 16P _2X3
GCLK@
+RTCVCC
OSC_IN_R_R
1 GCLK@ 2 OSC_IN_R
RCL3
33_0402_5%
1
SA000058Z00
OSC_IN_R
CCL6
2.2U_0603_6.3V6K
GCLK@
2
CCL12
4.7P_0402_50V8C
@
2
4
RCL7
271@ 2
1
47K_0402_5%
CLK_X2
1
2
CCL5
18P_0402_50V8J
GCLK@
<42> HWEQ_EN
HWEQ_EN
D
S
2
G
271@
2N7002_SOT23-3
QCL2
271@
CCL7
0.1U_0402_10V7K
2
2
1
271@
CCL8
0.01U_0402_25V7K
2
0_0402_5%
Reserved for Swing Level adjustment
( Close GCLK side )
3
2
3
1
1
GND
2
1
RCL4
10K_0402_5%
271@
3
3
GND
+3VALW
LAN_X1_R_R
1 @
RCL5
1
2
CCL2
GCLK@
GCLK@
25MHZ 20PF X3G025000DK1H-X
1
CCL4
18P_0402_50V8J
GCLK@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
EMI request 12/17
+3VALW
1
G
2
CCL13
GCLK@
<42>
1
D
2
LAN_X1_R <37>
1
2
S
1
PCH_X1_R <26>
+3V_LAN
1
YCL1
CLK_X1
LAN_X1_R_R
1 GCLK@ 2 LAN_X1_R
RCL2
33_0402_5%
PCH_X1_R_R
LAN_X1_R_R
2
+3VALW_GCLK
PCH_X1_R_R
1 GCLK@ 2 PCH_X1_R
RCL1
0_0402_5%
271@
AO3413_SOT23
QCL1
CCL9 0.1U_0402_10V7K
2
1
271@
+3VS_280
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HG
Sheet
36
of
61
A
B
C
D
+3V_LAN
UL1
CL1
<26> PCIE_PRX_C_LANTX_P1
CL2
<26> PCIE_PRX_C_LANTX_N1
HSOP
1
2 0.1U_0402_10V7K PCIE_PRX_LANTX_N1
23
HSON
PCIE_PTX_C_LANRX_P1 17
PCIE_PTX_C_LANRX_N1 18
D
2N7002_SOT23-3
LANCLK_REQ#
3
QL53
<5,29,36,38,40,44,45> PLT_RST#
1
18111FVB@ 2
RL28
0_0402_5%
<26>
<26>
CLK_LAN
CLK_LAN#
<27,40> EC_SWI#
+3VS
+3V_LAN
RL24 2
1 10K_0402_5%
8105ELDO@
LANCLK_REQ#
RL25 2 @
EC_SWI#
1 10K_0402_5%
RL22 1
+3V_LAN
CLKREQB
PLT_RST#
25
PERSTB
CLK_LAN
CLK_LAN#
19
20
REFCLK_P
REFCLK_N
LAN_X1
43
CKXTAL1
LAN_X2
44
CKXTAL2
28
LANWAKEB
ISOLATE#
26
ISOLATEB
ENSWREG
+3VS
18111FVB@ 2
RL26
0_0402_5%
+LAN_VDDREG
EECS
EEDI
30
32
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
33
ENSWREG
34
35
VDDREG
VDDREG
2
1
LAN_EN
31
37
40
46
2
2.49K_0402_1%
24
49
1
RL5
1K_0402_5%
RL6
@
ISOLATE#
1
RL433
2
LL1
8111FVB@
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
RL2 2
RL1 2
1 10K_0402_5%
1 10K_0402_5%
1
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
DVDD33
DVDD33
27
39
+3V_LAN
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
+3V_LAN
RSET
GND
PGND
1
CL3
1
CL4
1
CL5
1
CL6
1
8111FVB@ CL7
1
8111FVB@ CL8
1
Layout Note: LL1 must be
within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
8111FVB@ 2
+LAN_VDD10
EC_SWI#
8111FVB@
RL21 2
1 10K_0402_5%
2 1K_0402_5%
@
LED3/EEDO
LED1/EESK
LED0
HSIP
HSIN
16
S
8105ELDO@
CLKREQ_LAN#
1
<26> CLKREQ_LAN#
22
2
G
LAN_EN
<26> LAN_EN
2 0.1U_0402_10V7K PCIE_PRX_LANTX_P1
CL9
0.1U_0402_10V7K
2 8111FVB@
1
LL2
1
1
2
2
CL17
0.1U_0402_10V7K
Close to Pin 21
21
+LAN_EVDD10
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
REGOUT
36
+3V_LAN
8111FVB@
8111FVB@
+LAN_VDDREG
8111FVB@
1
8111FVB@ LL3
2
0_0603_5%
CL28
4.7U_0603_6.3V6K
8111FVB@
+LAN_REGOUT
8111FVB@
1
1
2
CL29
0.1U_0402_10V7K
2 8111FVB@
60 mils
RTL8111F-CGT_QFN48_6x6
8111FVB@
<36> LAN_X1_R
2
2
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
0.1U_0402_10V7K
CL19, CL20,CL21 close to pin 13,29,45, respectively
CL22 close to pin 3, respectively
CL23,CL24,CL25 close to pin 6,9,41, respectively
2
0_0603_5%
CL18
1U_0402_6.3V6K
EVDD10
2
+LAN_EVDD10
+LAN_VDD10
+LAN_VDD10
1
CL19
1
CL20
1
CL21
1
CL22
1
CL23
1
CL24
1
CL25
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
For P/N and footprint
Please place them to ISPD page
WOL_EN#
2
0_0402_5%
CL3 to CL6 close to Pin 27,39,47,48
CL7 to CL8 close to Pin 12,42
+LAN_VDD10
SA00004Y710
1
<26> PCIE_PTX_C_LANRX_P1
<26> PCIE_PTX_C_LANRX_N1
E
RL8 GCLK@
1
2
0_0402_5%
2
LAN_X2
UL1
RTL8105E
HIGH
NC
Pin14
NC
Pin15
NC
10K ohm PD
Pin38
NC
1K ohm PH
10PF_0402_50V9
2 1
2
RL29
22_0402_5%
GCLK@
GCLK@
+3V_LAN
EMI request 11/06 Placement near to YH2
HIGH
1
LOW
WOL_EN#
CL43
1
RTL8111E/F
S0
NOGCLK@ YL1 25MHZ_20PF_7V25000016
LAN_X1 1
1
+3VALW TO +3V_LAN
1
+3VALW
2
3
3
GND
2
CL26
27P_0402_50V8J
NOGCLK@
RL4
0_0402_5%
8111FVB@
LAN_X2
GND
4
CL27
27P_0402_50V8J
NOGCLK@
1
ENSWREG
8105E-VL/VD 8105E-VL/VD
8111F/F-VB
PWM Mode
LDO Mode
NC
RL4
0 ohm
(Pull High)
NC
RL23
8105E-VD 10/100M
8105ELDO@
0 ohm
(Pull Down)
1
Sx Enable Sx Disable
Wake up
Wake up
2
RL7
15K_0402_5%
RL23
0_0402_5%
8105ELDO@
2
1
2
+3VALW
1
8
PR4-
RJ45_MIDI3+
7
PR4+
RJ45_MIDI1-
6
PR2-
RJ45_MIDI2-
5
PR3-
RJ45_MIDI2+
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
UL4
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
LAN
WOL
LAN_EN
ISOLATEB
S0
Sx
S0
Sx
---------------------------------------------0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0*
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
LAN_MDI2LAN_MDI2+
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
LAN_MDI1LAN_MDI1+
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
LAN_MDI0LAN_MDI0+
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
LAN_MDI3LAN_MDI3+
CL39 1000P_0402_50V7K 8111FVB@
2
1
1
2
RL11
75_0402_1%
8111FVB@
CL40 1000P_0402_50V7K 8111FVB@
2
1
1
2
8111FVB@
RL12
75_0402_1%
CL41 1000P_0402_50V7K
2
1
1
2
RL13
75_0402_1%
CL42 1000P_0402_50V7K
2
1
1
2
RL15
75_0402_1%
RJ45_MIDI3RJ45_MIDI3+
RJ45_MIDI0+
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
2
CL34
0.1U_0402_25V6
14
13
LED_GREEN_B2
12
LED_GREEN_B1
11
LED_YELLOW_A2
10
LED_YELLOW_A1
9
DL2
@
For ESD
PR1+
@
SANTA_130451-F
RJ45_GND
1
4
1
GND
GND
1
CL36
2
1000P_1808_3KV7K
SUPERWORLD_SWG150401
8111FVB@
SP050007400
LANGND
1
2
1
CL37
220P_0402_50V6K
2
CL38
@
4.7U_0603_6.3V6K
4
Place CL34 colse
to LAN chip
Compal Secret Data
Issued Date
2011/12/14
2012/12/31
Deciphered Date
Title
Rev
B
4019HG
Date:
A
B
C
3
3
2
RJ45_MIDI3-
3
10/100M transformer_HD245
1
2
3
DL1
2
JRJ45
RJ45_MIDI1+
RJ45_MIDI1-
SP050007K00
2
For ESD
1
LAN Conn.
RJ45_MIDI0+
RJ45_MIDI0-
2
16
15
14
13
12
11
10
9
3
1
1
TX+
TXCT
NC
NC
CT
RX+
RX-
2
CL681
4.7U_0805_10V4Z
@
CL682
1U_0402_6.3V6K
TD+
TDCT
NC
NC
CT
RD+
RD-
3
2
3
2
2
LAN_MDI1+
LAN_MDI1-
2
1
1
2
3
4
5
6
7
8
1
1
@
CL482
0.01U_0402_25V7K
LAN_MDI0+
LAN_MDI0-
1
1,32,47> PCH_PWR_EN#
2
AO3413_SOT23
UL3 8105ELDO@
PJ29
JUMP_43X79
@
+3V_LAN
1
2
47K_0402_5%
RL435
@
1
2
0_0402_5%
@ QL51
2
Vgs=-4.5V,Id=3A,Rds<97mohm
1
3
@ RL432
1
CL483
@
0.1U_0402_10V7K
G
RL434
1 @
2
0_0402_5%
1
D
<44> WOL_EN#
2
S
RL147
100K_0402_5%
@
D
Sheet
E
37
of
61
5
4
3
2
1
D
D
All of cap. close to chip
+AV12
+3VS
20 mils
CW1
2.2U_0603_6.3V6K
1
1
2
2
+DV12
40 mils
CW2
0.1U_0402_16V4Z
CW3
4.7U_0603_6.3V6K
1
1
2
2
20 mils
CW4
0.1U_0402_16V4Z
CW5
2.2U_0603_6.3V6K
1
1
2
2
CW6
0.1U_0402_16V4Z
All of cap. close to chip
UW1
C
CW7
2
1 +DV33_18
20
1U_0402_6.3V6K
PCIE_PTX_C_CRRX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PRX_C_CRTX_N4
3V3_IN
DV33_18
AV12
DV12_S
+VCC_2IN1
10
Card_3V3
1
12mils,
6.2K_0402_5%
2
RW1
<26>
<26>
<26>
<26>
+AV12
+DV12
9
15
7
11
+3VS
mils
CW8 1
CW9 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
<26> CLK_CR
<26> CLK_CR#
lengths < 200mils8
1
2
5
6
HSIP
HSIN
HSOP
HSON
CLK_CR
CLK_CR#
3
4
REFCLKP
REFCLKN
<26> CLKREQ_CR#
+3VS
1
RW2
25
SP1
SP2
SP3
SP4
SP5
SP6
12
13
14
16
17
18
SD_DATA1_R
SD_DATA0_R
SDCLK_R
SDCMD_R
SD_DATA3_R
SD_DATA2_R
RW6
RW5
RW4
RW7
RW8
RW9
1
1
1
1
1
1
2
2
2
2
2
2
0_0402_5%
0_0402_5%
33_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SD_DATA1
SD_DATA0
SDCLK
SDCMD
SD_DATA3
SD_DATA2
1
colse to chip
23
PERST#
24
CLK_REQ#
19
2
10K_0402_5%
GND
RREF
PCIE_PTX_C_CRRX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PRX_CRTX_P4
PCIE_PRX_CRTX_N4
<5,29,36,37,40,44,45> PLT_RST#
C
GPIO
SD_WP
20
SDWP
SD_CD#
21
SDCD#
MS_INS#
22
CW10
5P_0402_50V8C
2
For EMI
RTS5229-GR_QFN24_4X4
SA00004Z900
B
B
< 2 in 1 Card Reader >
Connector on bottom side
JREAD
SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3
SDCMD
SDCLK
7
8
9
1
DAT0
DAT1
DAT2
DAT3
2
5
CMD
CLK
12
13
GND
GND
WP
CD
10
11
SDWP
SDCD#
VDD
4
+VCC_2IN1
VSS1
VSS2
3
6
+VCC_2IN1
40 mils
CW11
10U_0805_10V6K
2
1
1
2
CW12
0.1U_0402_16V4Z
TAITW_PSDBTD-09GLBS1N14N0
@
CW12, CW11 colse to socket VDD
A
A
Compal Secret Data
Issued Date
2011/12/14
2012/12/31
Deciphered Date
Title
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
38
of
61
5
4
3
2
1
+3VS
CR27
1
CR28
1
U3TXDP1
U3TXDN1
2 0.01U_0402_25V7K
IUSB30@
RR33
RR14
RR18
RR16
+3VS
A_INp
A_INn
9
8
B_INp
B_INn
PD#
REXT
TEST
I2C_EN
+3VS
CR36
1
CR37
1
22
23
U3TXDP1_U
U3TXDN1_U
GND
GND
GPAD
10
21
25
0
7
1127
1
15
U3TXDP2
U3TXDN2
IUSB30@
CR34 1
2 0.1U_0402_10V7K U3TXDP2_C
CR35 1
2 0.1U_0402_10V7K U3TXDN2_C
U3TXDP2
U3TXDN2
RR49
RR44
RR46
RR45
1
1
2
1
IUSB30@
@
2
PRUR@ 2
@
1
@
2
0_0402_5%
3.3K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
VDD
VDD
15
16
17
18
A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC
<29>
19
20
OSx = 0
OSx = 0
0 dB
0 dB
0 dB
9
8
5
7
14
24
0
-3.5 dB
-2.2 dB
-4.4 dB
1
-6.0 dB
-5.2 dB
-6.0 dB
Normal Operation
Sleep Mode
CM
B_INp
B_INn
B_OUTp
B_OUTn
22
23
GND
GND
GPAD
1 @
LR1
BOM Structure
4
1
1 @
LR2
DEVICE FUNCTION
Pericom
PCUR@
4
4
TI
TIUR@
1
1
Parade
PRUR@
USB3.0
USB30R@
U3TXDN1_U_C
L
L
H
H
adaptive EQ enable
Loss up to 7dB
Loss up to 14.5dB
Loss up to 11.5dB
L
H
L
H
U3RXDN2_U_C
4
1
1
@
2 RR42
0_0402_5%
IUSB30@
3 3
2
1 @
LR6
4
4
A_DE1(Pin18) A_DE0(Pin16)
L
L
H
H
B_DE1(Pin6) B_DE0(Pin3)
3.5dB
No de-emphasis
7dB
5dB with boost
output swing
L
H
L
H
L
L
H
H
3.5dB
No de-emphasis
7dB
5dB with boost
output swing
L
H
L
H
U3TXDN2_U_C
1
2
2
2
2
IUSB30@
0.1U_0402_10V7K
0.1U_0402_10V7K
IUSB30@
IUSB30@
0.1U_0402_10V7K
0.1U_0402_10V7K
IUSB30@
U3RXDP2_R
U3RXDN2_R
U3RXDP2_R <29>
U3RXDN2_R <29>
4
+USB_VCCB
U3TXDP2_U_C
U3TXDN2_U_C
2 RR43
0_0402_5%
IUSB30@
3 3
2
2
1
1
2
3
4
5
6
7
8
9
USB20_N1_L
USB20_P1_L
10
21
25
U3TXDN2_U_C_L
U3TXDP2_U_C_L
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
10
11
12
13
GND
GND
GND
GND
2
1
W=80mils
USB3_GND
LOTES_AUSB0015-P001A
0_0603_5%
0_0603_5%
RR36
U3RXDP1_U_C_L
<29>
USB20_P1
USB20_P1
1 @
LR4
2
2
3
3
2 RR39
0_0402_5%
IUSB30@
1 1
USB20_P1_L
U3RXDN1_U_C_L
<29>
B
4
WCM-2012-900T_0805
1
2 RR38
@
0_0402_5%
USB20_N1
USB20_N1
4
USB20_N1_L
U3TXDP1_U_C_L
DR7
U3TXDN1_U_C_L 1 1
DR1
USB20_P0_L
2
USB20_N0_L
3
U3TXDN1_U_C_L
@
2
1
1
3
@
109
U3TXDN1_U_C_L
U3TXDP1_U_C_L 2 2
98
U3TXDP1_U_C_L
U3RXDN1_U_C_L 4 4
7 7 U3RXDN1_U_C_L
U3RXDP1_U_C_L 5 5
66
U3RXDP1_U_C_L
3 3
U3RXDP2_U_C_L
8
Change ESD Diode for EMI request
2
DR8
U3TXDN2_U_C_L 1 1
U3RXDN2_U_C_L
DR4
U3TXDP2_U_C_L
USB20_P1_L
2
USB20_N1_L
3
@
2
1
1
3
@
109
U3TXDN2_U_C_L
U3TXDP2_U_C_L 2 2
98
U3TXDP2_U_C_L
U3RXDN2_U_C_L 4 4
7 7 U3RXDN2_U_C_L
U3RXDP2_U_C_L 5 5
66
U3RXDP2_U_C_L
A
3 3
2
1
2 RR41
@
0_0402_5%
8
U3TXDN2_U_C_L
Issued Date
Change ESD Diode for EMI request
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
3
USB2_GND
0_0603_5%
RR24
JUSBLF
Date:
5
W=80mils
LOTES_AUSB0015-P001A
0_0603_5%
1
C
10
11
12
13
GND
GND
GND
GND
RR23
CR31
U3RXDP2_R_R
1
U3RXDN2_R_R
1
CR30
CR32
U3TXDP2_U
1
U3TXDN2_U
1
CR33
2
1
2 RR40
@
0_0402_5%
U3TXDP2_U_C
USB20_N0_L
2
2 RR32
0_0402_5%
IUSB30@
3 3
2
1 @
4
USB20_P0_L
1
B2_EQ1
B2_DE0
B2_EQ0
B2_DE1
B_EQ1(Pin4) B_EQ0(Pin2)
adaptive EQ enable
Loss up to 7dB
Loss up to 14.5dB
Loss up to 11.5dB
2 RR19
0_0402_5%
IUSB30@
3 3
1
2 RR22
@
0_0402_5%
U3RXDP2_U_C
Compliance Test Mode
1000P_0402_50V7K
RR37
1
2 RR20
@
0_0402_5%
U3TXDP1_U_C
CR45
2
1
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
@
2
LR5
L
H
L
H
U3TXDN1_U_C_L
U3TXDP1_U_C_L
U3RXDN2_U_C_L
U3RXDP2_U_C_L
PD#
REXT
TEST
I2C_EN
4
Parade suggest EQ1(Pin2) & EQ2(Pin17) to pull High use 7dB. All control has internally pulled down at ~150Kohm,
If add ESD Diode A_DE0(Pin16) and B_DE0(Pin3) need pull high to 7dB otherwise 3dB
A_EQ1(Pin15) A_EQ0(Pin17)
U3RXDN1_U_C_L
U3RXDP1_U_C_L
SN65LVPE502CPRGER_VQFN24_4X4
TIUR@
12
11
1
2
3
4
5
6
7
8
9
USB20_N0_L
USB20_P0_L
2 0.01U_0402_25V7K
IUSB30@
4
3
2
6
2
JUSBLR
+USB_VCCB
A_OUTp
A_OUTn
U3RXDP1_U_C
0(default) Normal Operation
1
USB20_N0
1
PS8710BTQFN24GTR-A1_TQFN24_4X4
CONTROL PINS SETTINGS
DEVICE FUNCTION
<29>
2
WCM-2012-900T_0805
1
2 RR25
@
0_0402_5%
PRUR@
REXT - swing pin(2.5K~10K) SA00004VQ00
When test RX need add RR18
U3RXDN1_U_C
NC(default)
1 @
2 RR26
0_0402_5%
LR3 IUSB30@
3 3
4 4
USB20_N0
UR2
A_INp
A_INn
1
OSx = NC
USB20_P0
USB20_P0
2
1000P_0402_50V7K
PI3EQX7502IZDEX_TQFN 24P
PCUR@
IUSB30@
0.1U_0402_10V7K
2
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
2
220U_6.3V_M_R15
SA00004YI00
1
13
OUTPUT DE CONTROL (at 2.5GHZ)
B
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
908
1
2
1
CR44
0.1U_0402_10V7K
0
A2_EQ1
A2_DE0
A2_EQ0
A2_DE1
U3RXDP2_U_C
U3RXDN2_U_C
EQUALIZATION
(dB)
0
U3RXDP1_R <29> 2
U3RXDN1_R <29>
1
CR29
TI: A_DE1、B_DE1 need 0ohm to GND.
If use Parade and need control
A_DE1 & B_DE1 please use 4.7K
<29>
<29>
NC(default)
IUSB30@
2 0.1U_0402_10V7K U3RXDP1_R
2 0.1U_0402_10V7K U3RXDN1_R
IUSB30@
IUSB30@
2 0.1U_0402_10V7K U3TXDP1_U_C
2 0.1U_0402_10V7K U3TXDN1_U_C
IUSB30@
CR41
0.1U_0402_10V7K
1042
EQx
CR19
1
1
CR18
CR22
1
1
CR23
0.1U_0402_10V7K
1
CR26
0_0402_5%
RR50 TIUR@
0_0402_5%
RR53 @
0_0402_5%
RR64 TIUR@
4.7K_0402_5%
RR60 @
4.7K_0402_5%
RR54 @
4.7K_0402_5%
RR57 TIUR@
4.7K_0402_5%
RR59 @
4.7K_0402_5%
RR65 TIUR@
TRANSISTION BIT AMPLITUDE
(TYP mVpp)
NC(default)
L
L
H
H
B_OUTp
B_OUTn
UR2
+3VS
0
U3RXDP1_R_R
U3RXDN1_R_R
SA000056E00
OUTPUT SWING AND EQ CONTROL (at 2.5 GHZ)
1(default)
A_OUTp
A_OUTn
12
11
4.7U_0805_10V4Z
0.1U_0402_10V7K
4.7U_0805_10V4Z
1
1
1
1
+
CR46
CR42
CR40
CR43
UR2
RR50
0_0402_5%
PCUR@
TI suggest EQ1(Pin2) & EQ2(Pin17) to pull Down use 7dB
DE1(Pin3) & DE2(Pin16) NC use 0dB
OS1(Pin4) & OS2(Pin15) NC use 1042mV
EN_RXD
B1_EQ1
B1_DE0
B1_EQ0
B1_DE1
4
3
2
6
REXT - swing pin(2.5K~10K) SA00004VQ00
B2_DE0
B2_DE1
DEx
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
2
1
19
20
A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC
When test RX need add RR18
RR64
0_0402_5%
PCUR@
A2_DE0
A2_DE1
OSx
+USB_VCCB
W=80mils
2
B2_EQ0
B2_EQ1
C
D
U3RXDP1_U_C
U3RXDN1_U_C
5
7
14
24
USB_OC#0 <29,44>
CR39
4.7U_0805_10V4Z
2 @
SA00004YI00
PS8710BTQFN24GTR-A1_TQFN24_4X4
PRUR@
RR57
4.7K_0402_5%
PCUR@
2
1
2
1
2
1
2
1
2
1
2
1
2
2
4.7K_0402_5%
RR65
4.7K_0402_5%
PCUR@
RR52 @
4.7K_0402_5%
RR51 @
4.7K_0402_5%
RR61 @
4.7K_0402_5%
RR55 @
4.7K_0402_5%
RR62 @
4.7K_0402_5%
RR56 PRUR@
4.7K_0402_5%
A2_EQ0
A2_EQ1
RR63 @
4.7K_0402_5%
RR58 PRUR@
1
+3VS
1
1000P_0402_50V7K
1
SA00004KB00
SA00003TV00
SN65LVPE502CPRGER_VQFN24_4X4
TIUR@
15
16
17
18
IUSB30@
@
1
2 0_0402_5%
1 PRUR@ 2 3.3K_0402_5%
@
2
1 4.7K_0402_5%
@
1
2 4.7K_0402_5%
For EMI
2
CR38
SY6288DCAC_MSOP8
VDD
VDD
A1_EQ1
A1_DE0
A1_EQ0
A1_DE1
IUSB30@
CR24 1
2 0.1U_0402_10V7K U3TXDP1_C
CR25 1
2 0.1U_0402_10V7K U3TXDN1_C
U3TXDP1
U3TXDN1
6
7
8
5
OUT
OUT
OUT
OCB
1
<29>
<29>
USB_EN#
<44> USB_EN#
IN
IN
EN/ENB
GND
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0_0402_5%
RR34 TIUR@
0_0402_5%
RR35 @
0_0402_5%
RR21 TIUR@
4.7K_0402_5%
RR12 @
@
4.7K_0402_5%
RR8
TIUR@
4.7K_0402_5%
RR7
4.7K_0402_5%
RR11 @
4.7K_0402_5%
RR29 TIUR@
TI: A_DE1、B_DE1 need 0ohm to GND.
If use Parade and need control
A_DE1 & B_DE1 please use 4.7K
+USB_VCCB
2
1
13
2
3
4
1
UR1
UR1
A1_DE0
A1_DE1
B1_DE0
B1_DE1
A
0.1U_0402_10V7K
2 IUSB30@
W=60mils
2.5A
UR3
PI3EQX7502IZDEX_TQFN 24P
PCUR@
+3VS
RR34
0_0402_5%
PCUR@
B1_EQ0
B1_EQ1
D
+5VALW
1
RR21
0_0402_5%
PCUR@
UR1
SA000056E00
2
1
Note：
1) keep differential trace mismatch less than +/- 5mil
2) keep USB3 impedance follow Intel SPEC
3) Power / GND pin trace 10mil
RR7
4.7K_0402_5%
PCUR@
2
1
2
1
2
1
2
1
2
1
2
1
2
2
4.7K_0402_5%
RR28 @
4.7K_0402_5%
RR27 @
4.7K_0402_5%
RR13 @
@
4.7K_0402_5%
RR9
4.7K_0402_5%
RR15 @
PRUR@
4.7K_0402_5%
RR6
4.7K_0402_5%
A1_EQ0
A1_EQ1
RR17 @
4.7K_0402_5%
RR10 PRUR@
1
RR29
4.7K_0402_5%
PCUR@
2
Rev
B
4019HG
1
Sheet
39
of
61
A
B
+1.5V to +1.05V Transfer
+3V_USB
+1.5V
2
<26> CLK_USBA30
<26> CLK_USBA30#
EUSB30@
0.1U_0402_16V7K 2
<26> PCIE_PRX_C_USBTX_P5
0.1U_0402_16V7K 2
<26> PCIE_PRX_C_USBTX_N5
EUSB30@
EUSB30@
2
EUSB30@ CT42
CT40
0.1U_0402_16V4Z
0.1U_0402_16V7K
1
EUSB30@
QT3
1
2
2
RT13 47K_0402_5% 2
AO3413_SOT23
CT26
D
0.01U_0402_25V7K
EUSB30@
EUSB30@
1
+3V_USB
S 2N7002_SOT23-3
EUSB30@
1
<26> PCIE_PTX_C_USBRX_P5
<26> PCIE_PTX_C_USBRX_N5
47
48
10
EC_Q_SWIA#
CLKREQ_Q_USBA30#
3
25
AVDD33
AVDD33
39
33
30
21
9
6
42
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
U3TXDP2
37
TI_U3TX_C_DP3
PETXP
PETXN
U3TXDN2
U2DM2
38
45
TI_U3TX_C_DN3
U2D_DN2
PERXP
PERXN
U2DP2
U3RXDP2
44
40
U2D_DP2
TI_U3RXDP3_R
U3RXDN2
41
TI_U3RXDN3_R
OCI2B
OCI1B
17
19
PERSTB
PEWAKEB
PECREQB
2
1
1
46
11
1
RT651
RT671
RT681
RT69
2
210K_0402_5%
210K_0402_5%
210K_0402_5%
10K_0402_5%
SMIB
PPON2
PPON1
SA000051C10
15
14
16
13
SPISCK
SPICSB
SPISI
SPISO
24
23
XT1
XT2
27
IC(L)
EUSB30@EUSB30@EUSB30@EUSB30@EUSB30@
EUSB30@EUSB30@EUSB30@EUSB30@
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDP3
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDN3
U2D_DN2 <34>
U2D_DP2 <34>
OCL1#
@
18 USB30PWRON0 RT60 1
0_0402_5%
20
2
USB_CHG_EN# <34,44>
29
36
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDP4
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDN4
U2D_DN3 <34>
U2DP1
U3RXDP1
35
31
U2D_DP3
TI_U3RXDP4_R
U2D_DP3 <34>
U3RXDN1
32
TI_U3RXDN4_R
RREF
26
U3TXDP1
28
U3TXDN1
U2DM1
TI_U3TX_C_DP4
1
EUSB30@
YT2
1
2
CT61
1
CT87
1
CT65
1
CT71
TI_U3TX_C_DN4
1
U2D_DN3
PONRSTB
1
2
RT15 EUSB30@
2
1.6K_0402_1%
GND
1
2
CT67 0.01U_0402_25V7K
1
1
USBA30_SMI#_IC
RT14 1
2 10K_0402_5%
EUSB30@
1SS355TE-17_SOD323-2
1 1 2 2
DT2
EUSB30@
1
2
CT74
EUSB30@1U_0603_10V6K
2
2
CT63 0.01U_0402_25V7K
2
2
CT62 0.01U_0402_25V7K
1
2
CT68 0.1U_0402_16V7K
EUSB30@
EUSB30@
EUSB30@
2
1
CT60 0.01U_0402_25V7K
1
2
CT66 0.01U_0402_25V7K
EUSB30@
2
1
CT70 0.1U_0402_16V7K
EUSB30@EUSB30@EUSB30@EUSB30@EUSB30@
EUSB30@EUSB30@EUSB30@EUSB30@
1
2
CT69 0.01U_0402_25V7K
2
1
+1.05V_USB
CT64 0.1U_0402_16V7K
2
2
CT56 0.01U_0402_25V7K
2
1
Close to U32.25
CT52 0.1U_0402_16V7K
1
CT57 0.01U_0402_25V7K
1
CT55 0.1U_0402_16V7K
2
CT58 10U_0603_6.3V6M
1
1
CT54 0.1U_0402_16V7K
1
2
CT51 0.1U_0402_16V7K
1
2
CT44 0.01U_0402_25V7K
1
2
CT53 0.01U_0402_25V7K
1
2
CT47 0.01U_0402_25V7K
2
+3VA_USB Close to U32.3
CT48 0.01U_0402_25V7K
1
CT50 0.01U_0402_25V7K
CT49 0.01U_0402_25V7K
2
7
8
PECLKP
PECLKN
49
1
1
3
UPD720202:
SMIB Low active
+3V_USB
+3V_USB
4
5
UPD720202K8-701-BAA_QFN48_7X7
+3V & +1.05V has power sequence timing:
0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms
2
1
2
G
<5,29,36,37,38,44,45> PLT_RST#
D
2
G
QT5
<27,44> PM_SLP_S4#
CT41
1 PCIE_PRX_USBTX_P5
1 PCIE_PRX_USBTX_N5
CT81
S
3
RT12
EUSB30@ 100K_0402_5%
+3VA_USB
1
+3VALW
+3VALW
+1.05V_USB
UT6
EUSB30@
VDD10
+3VALW to +3V Transfer
+3V_USB
EUSB30@
10U_0603_6.3V6M 1
43
2
Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025
2
CT59
34
1
RT8
32.4K_0402_1%
EUSB30@
EUSB30@2
1
2
BLM18AG601SN1D_2P
VDD33
2 EUSB30@
1
RT6
10K_0402_1%
22
1
GND
VDD33
EN
VDD33
+3V_USB
+3VA_USB
EUSB30@
LT9
CT25
10U_0603_6.3V6M
2
8
+3V_USB
1A
3
4
12
EUSB30@USBA30_POK
EUSB30@
VIN
VOUT
VIN
VOUT
VCNTL
POK
FB
APL5930KAI-TRG_SO8
1
E
+1.05V_USB
UT3
5
9
6
7
1
2
CT43
10U_0603_6.3V6M
1
+3V_USB
D
VDD33
+1.5V
C
EUSB30@
1 RT5
2 USBA30_POK
4.7K_0402_5%
3
CLKREQ_Q_USBA30#
+3V_USB
2
EUSB30@
QT7B
4
3
2N7002KDWH_SOT363-6
EUSB30@
1
10K_0402_5%
2 RT61
1
EUSB30@
2
EUSB30@
EC_SWI# <27,37>
2
EC_Q_SWIA#
5
10K_0402_5%
2 RT62
1
EUSB30@
1
CT76
12P_0402_50V8J
+3V_USB
1
CT75
12P_0402_50V8J
24MHZ_12PF_X5H024000DC1H
+3V_USB
QT7A
6
3
CLKREQ_USBA30# <26>
2N7002KDWH_SOT363-6
EUSB30@
+3V_USB
TI_U3RXDN3_R
1 @
LT8
3
2N7002KDWH_SOT363-6
EUSB30@
1
OCL1#
+3V_USB
QT6B
4
10K_0402_5%
2 RT51
1
EUSB30@
USBA30_SMI# <29>
2
USBA30_SMI#_IC
5
+3V_USB
10K_0402_5%
2 RT54
1
EUSB30@
1
4
4
3
U3RXDN3
TI_U3RXDN4_R
U3RXDN3 <34>
1 @
LT12
3
1
2 RT38
@
0_0402_5%
TI_U3RXDP3_R
QT6A
6
1
2 RT52
0_0402_5%
EUSB30@
2 2
U3RXDP3
TI_U3RXDP4_R
U3RXDP3 <34>
1
1
4
4
2 RT40
0_0402_5%
EUSB30@
2 2
3
U3RXDN4
U3RXDN4 <34>
3
1
2 RT53
@
0_0402_5%
U3RXDP4
U3RXDP4 <34>
USB_OC#1 <29,34,44>
2N7002KDWH_SOT363-6
EUSB30@
TI_U3TXDN3
1 @
LT14
1
1
2 RT47
0_0402_5%
EUSB30@
2
U3TXDN3_C_L <34>
TI_U3TXDN4
1 @
LT10
2
4 4
3 3
1
2 RT50
@
0_0402_5%
TI_U3TXDP3
U3TXDN3_C_L
U3TXDP3_C_L
U3TXDP3_C_L <34>
TI_U3TXDP4
2 RT48
0_0402_5%
EUSB30@
1
1
2
2
4
4
3
3
U3TXDN4_C_L
1
2 RT39
@
0_0402_5%
U3TXDN4_C_L <34>
U3TXDP4_C_L
U3TXDP4_C_L <34>
4
4
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
A
B
C
D
Rev
4019HG
Sheet
E
B
40
of
61
A
B
C
D
E
1
1
2
2
3
3
4
4
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
A
B
C
D
Rev
4019HG
Sheet
E
B
41
of
61
3
2
1
2W 4ohm =40mil
1W 8ohm =20mil
+3VL
+DVDD_IN
+3VL
+5VALW
2
0_0603_5%
1
CA9
0.1U_0402_10V7K
SPKR+
2
0.1U_0402_10V7K
2
RA43
100K_0402_5%
CA14
CA15
2
CA16
For EMI
RA41
INT_MIC_CLK_R
FBMA-10-100505-301T
<22> INT_MIC_DATA
CAM@
1
0.1U_0402_10V7K
1
2
CA46
CA17
UA3
27
38
AVDD2
46
SPK_OUT_R+
SPK_OUT_R-
45
44
MIC1_L
MIC1_R
HP_OUT_L
HP_OUT_R
CBP
CBN
4
GPIO1/1st DMIC
2
GPIO0/DMIC-CLK
GPIO4
RESET#
MONO_IN
12
PCBEEP
13
SENSE A
SENSE_A
10K_0402_5%
1 RA42
2
2HWEQ_EN_D
4HWEQ_EN 1 RA19
1K_0402_5%
2
S
2N7002_SOT23-3
QA5
HWEQ_EN_D
OSC@
1
2
CA39
4
VDD
OUT
3
OSC_OUT 1 RA28
OSC_IN
2
1
VCOUNT GND
2
1
SYNC
10
BCLK
6
SDATA_OUT
5
SDATA_IN
8
EAPD+PD#
48
SPKR+
SPKR-
+5VALW
1
2
1
2
HP_L
HP_R
@
<43>
<43>
<43>
SPK_R1
<43>
SPK_R2
<43>
D
2
1
CA41
1U_0402_6.3V4Z
@
Beep sound
+3VALW
@
1
RA3
AZ_SDOUT_HD <25>
2
RA7
1
33_0402_5%
AZ_SDIN0_HD
EC_MUTE# Internal AMP
Enable
Hight
Disable
LOW
<25>
AZ_BITCLK_HD <25>
<25>
CA27
1
2
RA10
1
2
47K_0402_5%
MONO_IN
C
0.1U_0402_10V7K
RA11
4.7K_0402_5%
2
10K_0402_5%
EC_MUTE#
GPIO3/SPDIFO
EC_MUTE# <44>
1
MONO_OUT
37
@
AZ_BITCLK_HD 2
10_0402_5%
NC
30
21
18
NC
VREF
25
AC_VREF
47
AUX mode/GPIO2
JDREF
22
AC_JDREF
34
26
33
49
CPVEE
SENSE B
NC
NC
CPVEE
AVSS1
AVSS2
DVSS
AUX_CLK_In
+MIC1_VREFO
CA48
1
2 @
CA22
100P_0402_50V8J
To solve noise issue
1
RA27
10P_0402_50V8J
For EMI
please place near codec
close to pin 21
2
CA18
RA4
4.7K_0402_5%
1
10U_0603_6.3V6M
Ext.MIC/LINE IN JACK
RA13
2
1K_0402_5% RA15
2
1
close to pin 22
2 RA8
1 20K_0402_1%
1
2
CA19
1
2.2U_0603_10V6K
MIC1_R_R
1
CA20
2
2
0.1U_0402_10V7K
CA21
2.2U_0603_6.3V6K
@
MIC1_R_L
2
1
1K_0402_5%
RA14
ALC280Q-GR_QFN48_6X6
CA42
10P_0402_50V8J
12.288MHZ_15PF_SSW012288D3CH
OSC@
SPK_L2
CA40
1U_0402_6.3V4Z
@
PCI Beep
<25> PCH_SPKR
AZ_SYNC_HD
AZ_BITCLK_HD
AZ_SDIN0_HD_R
LA5
2
1
0_0603_1%
SPKR-
2
CA31
@
10U_0603_6.3V6M
1
<43>
For EMI
75_0402_1%
75_0402_1%
LINE1_VREFO
15
2
10_0402_5%
HWEQ_EN
31
32
2
@
RA5
RA6
AGPO/MIC1_VREFO
LDO_CAP
24
17
16
XA1
0.1U_0402_10V7K
@
SPKL+
SPKL-
23
14
D
2
G
3
CA47
0.1U_0402_25V6
1
1
G
LINE2_L
LINE2_R
11
+3VL
HWEQ_EN
39
40
AZ_RST_HD#
B
<36>
42
43
100P_0402_50V8J
P
5
INT_MIC_CLK_R
<25> AZ_RST_HD#
O
IN2
3
JACK_SENSE 2
SPK_OUT_L+
SPK_OUT_L-
7
+3VL
IN1
LINE1_L
LINE1_R
1
36
2.2U_0603_10V6K 35
CA49 CAM@
220P_0402_50V7K
2
28
29
19
20
CA13
2
CA30
@
10U_0603_6.3V6M
1
1
SPK_L1
2
<22> INT_MIC_CLK
1
MIC1_R_C_L
MIC1_R_C_R
CA12
2
CA29
@
10U_0603_6.3V6M
1
2
SA000051D00
<36> OSC_IN_R
1
2.2K_0402_5%
MIC1_R
<43>
MIC1_L
<43>
B
+MIC1_VREFO
OSC_OUT
QA1A
RA17
2N7002DW-T/R7_SOT363-6
Placement near to UA1.15
100K_0402_5%
2
1
SJ000001A00
2
RA16
+MIC1_VREFO
MIC_SENSE#
DGND AGND
RA26
1 271@ 2
0_0402_5%
1
2.2K_0402_5%
6
1
MIC1_R_L 4.7U_0603_6.3V6K
MIC1_R_R
4.7U_0603_6.3V6K
C
SM_EN
41
9
<44,47,53,54,58>
CA11
0.1U_0402_10V7K
1
1
1
2
1
2
10U_0603_6.3V6M 10U_0603_6.3V6M
4
SUSP#
AVDD1
5
UA1
PVDD2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
SM_EN
QA3B
1
4>
CA10
1
2
10U_0603_6.3V6M
+5VALW
RA2
1
2
0_0603_5%
close to pin 38
0.1U_0402_10V7K
2
1
2
close to pin 9
CA4
PVDD1
QA3A
1
+AVDD
3
3
6
2
CA3
+DVDD
DVDD
2
0_0603_5%
2
1
0_0603_1%
LA4
2
1
0_0603_1%
close to pin 46
DVDD_IO
1
RA12
LA3
SPKL-
close to pin 27
+DVDD_IN
2
10U_0805_10V4Z
close to pin 3
CA2
1
2
10U_0603_6.3V6M
CA45 0.1U_0402_10V7K
2
1
2
2
CA28
@
10U_0603_6.3V6M
1
1
CA44
0.01U_0402_25V7K
1
10U_0603_6.3V6M
0.1U_0402_10V7K
CA50
1
1
2
1
CA1
2
+DVDD_IO
CA52
G
47K_0402_5%
RA24
2
AO3413_SOT23
QA2
2
D
2
close to pin 41
0.1U_0402_10V7K
2
0_0603_5%
CA8
10U_0603_6.3V6M
S
1
1
RA1
CA7
10U_0603_6.3V6M
3
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CA6
@
1
1
CA5
+3VS
CA43
CA38
2
RA25
100K_0402_5%
placement near Audio Codec
LA2
2
1
0_0603_1%
LA1
1
2 0.1U_0402_10V7K
2 PBY160808T-601Y-N_2P
1
1
+PVDD
1
1
RA29
D
SPKL+
2
4
1
5
SENSE A
Impedance
Codec Signals
Function
39.2K
PORT-A (PIN 31, 32)
Headphone out
20K
PORT-B (PIN 19, 20)
Ext. MIC
10K
place close to chip
MIC_SENSE#
SENSE_A
NBA_PLUG
RA21
2 0.1U_0603_50V7K
CA24 1
2 0.1U_0603_50V7K
CA25 1
2 0.1U_0603_50V7K
CA26 1
2 0.1U_0603_50V7K
1
RA22
39.2K_0402_1%
+3VL
RA18
100K_0402_5%
EC
<44> SM_SENSE#
QA1B
2
10_0603_5%
5
2N7002DW-T/R7_SOT363-6
PORT-E
JACK_SENSE <43>
4
5.1K
1
20K_0402_1%
PORT-C (PIN 28, 29)
<43>
A
2
RA20
CA23 1
3
Sense Pin
A
39.2K
SENSE B
20K
2011/12/14
Issued Date
10K
Compal Secret Data
Deciphered Date
2012/12/31
Title
Size
Date:
5
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
42
of
61
HeadPhone/LINE OUT JACK
JLINE
6
5
4
<42> NBA_PLUG
<42>
HP_R
<42>
HP_L
LA6 1
2 HP_R_L
CHILISIN PBY100505T-121Y-N 0402
LA7 1
2 HP_L_L
3
2
1
1
3
1
2
CA32
100P_0402_50V8J
CA33
CA34 @
100P_0402_50V8J
2
0.1U_0402_10V7K
DA3 @
PJDLC05_SOT23-3
SINGA_2SJ-0960-D06
@
For EMI
EXT.MIC/LINE IN JACK
+3VL
RA23
4.7K_0402_5%
For EMI
JEXMIC
1
27P_0402_50V8J
2
CA51
4
<42> JACK_SENSE
<42>
MIC1_R
<42>
MIC1_L
6
5
LA8 1
2 MIC1_L_R
LA9 1
2 MIC1_L_L
3
2
1
3
SINGA_2SJ-0960-D06
@
1
1
CA35
100P_0402_50V8J
2
CA36
100P_0402_50V8J
DA4 @
PJDLC05_SOT23-3
CA37 @
2
0.1U_0402_10V7K
For EMI
SPK CONN.
@
DA5
PJDLC05_SOT23-3
3
1
2
JSPK
<42>
<42>
<42>
<42>
SPK_L1
SPK_L2
SPK_R1
SPK_R2
PJDLC05_SOT23-3
3
1
2
1
2
3
4
5
6
1
2
3
4
G1
G2
ACES_50278-00401-001
@
DA6
@
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HG
Sheet
43
of
61
4
3
1
2
<29> CLK_PCI_EC
<5,29,36,37,38,40,45> PLT_RST#
+3VL
RB2
47K_0402_5%
1
2
<30> EC_SCI#
<36,47> AOAC_EN#
EC_RST#
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
AOAC_EN#
12
13
37
20
38
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
1
2
CB12 0.1U_0402_10V7K
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
C
KSI[0..7]
<45,46> KSI[0..7]
KSO[0..17]
<45,46> KSO[0..17]
+3VL
RB12
1
1
RB13
2.2K_0402_5%
2 EC_SMB_CK1
2 EC_SMB_DA1
2.2K_0402_5%
+3VS
RB15
1
1
RB16
2.2K_0402_5%
2 EC_SMB_CK2
2 EC_SMB_DA2
2.2K_0402_5%
<24,49,50>
<24,49,50>
<13,26,45>
<13,26,45>
PM_SLP_S3#
SLP_S5#
EC_SMI#
CIR_IN
USB_OC#1
USB_CHG_EN#_R
SM_EN
KB_LED
FAN_SPEED1
WL_OFF#
E51_TXD
E51_RXD
PM_PWROK_EC
PWR_SUSP_LED#
NUM_LED#
<27> PM_SLP_S3#
RB17
0_0402_5%
1
2 USB_CHG_EN#_R
<34,40> USB_CHG_EN#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<30>
EC_SMI#
<29,34,40> USB_OC#1
PM_PWROK_EC
1 9012@ 2
RB32
0_0402_5%
<5,27> PM_PWROK
B
<42> SM_EN
<45>
KB_LED
<5> FAN_SPEED1
<36> WL_OFF#
<36,45> E51_TXD
<36,45> E51_RXD
<46> PWR_SUSP_LED#
<45> NUM_LED#
<27>
@
PLT_RST#
2
1U_0402_6.3V6K
122
123
1
RB22
100K_0402_5%
@
XCLKI/GPIO5D
XCLKO/GPIO5E
SUSP#
2
180P_0402_50V8J
CB16
20P_0402_50V8
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
63
64
65
66
75
76
BATT_TEMPA
TMPTU1_SXP
ADP_I
ADP_V
TMPTU2_SXP
PWRMOS_TEMP
AD Input
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
68
70
71
72
HDPINT
PCH_PWR_EN
PCH_SUSPWRDN#
SUSACK#
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
SM_SENSE#
HDPLOCK
TP_CLK
TP_DATA
FUNCTION_LED#
1
67
FUNCTION_LED#
EC_WL_BT_LED
FANPWM
PWR_GPS_DOWN#
S
SSM3K7002F_SC59-3 S
<46>
BATT_TEMPA <49>
TMPTU1_SXP <36>
ADP_I
<49,50>
ADP_V <50>
TMPTU2_SXP <36>
PWRMOS_TEMP <58>
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
119
120
126
128
LNB_OC#
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_ENBKL
CPSETIN
HDPACT
BATT_FULL_LED#
CAPS_LED#
PWR_ON_LED#
BATT_CHG_LOW_LED#
SYSON
VR_ON
USB_OC#0
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
EC_LID_OUT#
PROCHOT_IN
H_PROCHOT#_EC
VCOUT0_PH_L
BKOFF#
PBTN_OUT#
GPS_DOWN#
SA_PGOOD
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
110
112
114
115
116
117
118
ACIN_D
EC_ON_R
ON/OFFBTN#
LID_SW#
SUSP#
CEC_INT#
EC_PECI
V18R
124
+EC_V18R
VGATE
<5,27,55>
WOL_EN# <37>
PWRME_CTRL <25>
VCIN0_PH <49>
SPI Device Interface
SPI Flash ROM
GPIO
Bus
GPIO
3
BATT_TEMPA
1
CB9
ACIN_D
1
2
CB10 100P_0402_50V8J
D
2
100P_0402_50V8J
TV tuner
temperature
EC_MUTE# <42> 2011/10/18a
USB_EN# <39>
SM_SENSE# <42>
HDPLOCK <45>
TP_CLK <46>
TP_DATA <46>
VGATE
WOL_EN#
PWRME_CTRL
VCIN0_PH
CB8
47P_0402_50V8J
2
PU by each project
function decide
HDPINT <45>
PCH_PWR_EN <47>
PCH_SUSPWRDN# <27>
SUSACK# <27>
97
98
99
109
1
H_PROCHOT#_EC 2
G
FANPWM <5>
PWR_GPS_DOWN# <58>
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
1
QB1
PS2 Interface
H_PROCHOT# <5,49>
D
+3VS
TMPTU1_SXP
1
RB4
TMPTU2_SXP
1
RB5
+3VS
2
10K_0402_5%
2
10K_0402_5%
H_PROCHOT#_EC 1
RB6
@
2
10K_0402_5%
PWR_GPS_DOWN# 1
RB28
2
100K_0402_5%
CEC_INT#
1
RB7
2
100K_0402_5%
LID_SW#
1
RB35
2
47K_0402_5%
AOAC_WAKE#
1
RB29
2
10K_0402_5%
+3VL
RH327
10K_0402_5%
LNB_OC# <53>
VCIN0_PH connect to
power portion (9012 only)
C
+3VS
LNB_EN
LNB_EN <53>
AOAC_WAKE# <36>
EC_ENBKL <22>
2
1
RB8
2
4.7K_0402_5%
TP_DATA
1
RB9
2
4.7K_0402_5%
SYSON
1
RB10
2
4.7K_0402_5%
LNB_EN
1 BCAS@ 2
RB11
10K_0402_5%
EC_WL_BT_LED
1
RB14
CPSETIN <49>
HDPACT <45>
BATT_FULL_LED# <46>
CAPS_LED# <45>
PWR_ON_LED# <46>
BATT_CHG_LOW_LED# <46>
SYSON
<52>
VR_ON
<55>
USB_OC#0 <29,39>
PCH_RSMRST# <27>
EC_LID_OUT# <30>
PROCHOT_IN <49> PROCHOT_IN
connect
to power portion (9012 only)
BKOFF# <22>
PBTN_OUT# <5,27>
GPS_DOWN# <13>
SA_PGOOD <54>
VCOUT0_PH_L
2
10K_0402_5%
9012@
1
2
RB34
0_0402_5%
VS_ON
<49,51>
VCOUT0_PH connect to power portion (9012 only)
RB18
330K_0402_5%
2
1
NV-GPU GPS function control pin
ON/OFFBTN# <46>
LID_SW# <45>
SUSP#
<42,47,53,54,58>
CEC_INT# <24>
1
RB19
ACIN_D
H_PECI
2
43_0402_1%
H_PECI
<5>
1
KB9012QF-A3_LQFP128_14X14
TP_CLK
2
RB751V40_SC76-2
+3VL
1
DB1
SUSP#
1
RB21
2
10K_0402_5%
VR_ON
1
RB23
2
10K_0402_5%
CB15
4.7U_0805_10V4Z
ACIN
B
<27,50>
SA00004OB20
2
CIR
2
1
CB14
RB20
0_0402_5%
1
2
1
1
CB13
CLK_EC
21
23
26
27
PWM Output
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
D
RB1
0_0402_5%
1
2
VR_HOT#
2
CB11
10P_0402_50V8J
@
<55>
1
<30> GATEA20
<30> KB_RST#
<25> SERIRQ
<25,45> LPC_FRAME#
<25,45> LPC_AD3
<25,45> LPC_AD2
<25,45> LPC_AD1
<25,45> LPC_AD0
2
D
EC_VDD/AVCC
1
RB3
10_0402_5%
@
<46> WL_BT_LED#
EC_WL_BT_LED
2
QB2 G
2N7002_SOT23-3
AGND/AGND
2
0.1U_0402_10V7K
9
22
33
96
111
125
2
GND/GND
GND/GND
GND/GND
GND/GND
GND0
2
CLK_PCI_EC
CB6
2
2
2
1000P_0402_50V7K
UB1
1
PVT change RF LED control
pin from PCH to EC 12/14
CB3
0.1U_0402_10V7K
1
2
11
24
35
94
113
For EMI
CB4
1000P_0402_50V7K
1
CB7
1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
1
CB2
CB5
1
CB1
0.1U_0402_10V7K
2
+3VL
3
+3VL
69
5
+5VL
1
Close to EC
<27,40> PM_SLP_S4#
2
B
4
SLP_S5#
VCIN0 pin109
VCIN1 pin102
>1.2V
<1.2V
RB36
EC_ON_R
1
2
2.2K_0402_5%
EC_ON
TC7SH08FUF_SSOP5
VCOUT0 pin104
HIGH
LOW
LOW
HIGH
<51>
2
UB2
Y
A
RB24
10K_0402_5%
Voltage Comparator Pins FOR 9012 A3
1
G
1
3
<27> PM_SLP_S5#
CB17
0.1U_0402_10V7K
1
2
P
5
+3VALW
2
1U_0402_6.3V6K
CB50
+5VL
1
RB25
VCOUT1 pin103
UB3
2 +5VL_CIR
100_0805_5% 1
CB18
4.7U_0805_10V4Z
2
CIR@
A
@
CIR_IN
CIR@
1
RB26
CIR@
1
Vout
2
VCC
3
GND
4
A
GND
IRM-V538/TR1_3P
2
0_0402_5%
For KB9012 EC_ON low pulse work around
RB27
100K_0402_5%
1
2
Issued Date
Compal Secret Data
E51_TXD
2011/12/14
2012/12/31
Deciphered Date
Title
Size
Date:
5
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
44
of
61
SPI Flash (128KB)
18
17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
@ JDB
ACES_88512-1641
+3VL
VDD
VOUT
3
LID_SW#
C453
0.1U_0402_16V4Z
<44>
1
1
1
2
GND
U21
APX9132ATI-TRL_SOT23-3
2
Place the PAD under DDR DIMM.
LPC Debug Port
Lid SW
C452
10P_0402_50V8J
2
G18
G17
E51_RXD_DB
1
E51_TXD_DB R21 1
R23
@
@
2
2 0_0402_5%
0_0402_5%
E51_RXD <36,44>
E51_TXD <36,44>
PLT_RST# <5,29,36,37,38,40,44>
CLK_PCI_DDR <29>
LPC_AD0 <25,44>
LPC_AD1 <25,44>
LPC_AD2 <25,44>
LPC_AD3 <25,44>
LPC_FRAME# <25,44>
CLK_PCI_DDR
+3VS
+3VALW
1
C457
2 1
R393
2
22P_0402_50V8J
@
CLK_PCI_DDR
22_0402_5%
@
For EMI
Q38 KBL@
AO3413_SOT23-3
D
S
3
1
+5VS_LED
1
1
1
2
3
4
G1
G2
5
6
SELF_TEST
E-T_6905K-Q04N-00R
C836
@
0.1U_0402_10V7K
2 KBL@
+5VS
1
For EMI
KB_LED
Close to JKB
D
2
G
3
<44>
S
Q52
2N7002_SOT23-3
KBL@
KSO16
KSO17
KSO2
KSO1
KEYBOARD CONN.
KSO0
KSO4
KSI[0..7]
KSO[0..17]
KSI[0..7]
<44,46>
KSO[0..17] <44,46>
KSO3
KSO5
KSO14
36
35
KSO6
GND2
GND1
JKB34
KSO7
1
2
34
+3VS
34
KSO16
R372 300_0402_5%
33 33
KSO13
32 32
KSO17
31 31
KSO8
30 30
29 29
KSO2
KSO9
28 28
KSO1
27 27
KSO0
KSO10
26 26
KSO4
25 25
KSO3
KSO11
24 24
KSO5
23 23
KSO14
KSO12
22 22
KSO6
21 21
KSO7
KSO15
20 20
KSO13
19 19
KSO8
KSI7
18 18
KSO9
17 17
KSO10
KSI2
16 16
KSO11
15 15
KSO12
KSI3
14 14
KSO15
13 13
KSI7
KSI4
12 12
KSI2
11 11
KSI3
KSI0
10 10
KSI4
9 9
KSI0
KSI5
8
8
KSI5
7 7
KSI6
KSI6
6 6
KSI1
5 5
JKB4
KSI1
2
1
4
+3VS
4
CAPS_LED# R376 300_0402_5%
CAPS_LED# <44>
3 3
CAPS_LED#
2 2
NUM_LED#
NUM_LED# <44>
1 1
NUM_LED#
JKB
HB_A803419-SBHR21
@
1
C401
1
C402
1
C404
1
C405
1
C406
1
C407
1
C408
1
C409
1
C410
1
C411
1
C412
1
C413
1
C415
1
C416
1
C417
1
C418
1
C419
1
C420
1
C421
1
C422
1
C423
1
C424
1
C425
1
C427
1
C429
1
C431
1
C433
1
C435
2
12
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
CG12
1U_0402_6.3V6K
GSENSOR@
+3VS_HDP
2
UG3
1
VIN
2
GND
3
SHDN#
VOUT
5
BP
4
G9191-330T1U_SOT23-5
4
6
8
ST
PD
FS
9
Rev
Voutx
Vouty
Voutz
3
5
7
NC1
NC2
NC3
NC4
NC5
10
11
14
15
16
GND1
GND2
1
13
VOUTXCG1
VOUTYCG2
VOUTZCG3
GSENSOR@
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2GSENSOR@
GSENSOR@
TSH352TR LGA 16P
2
GSENSOR@
1
+3VS_HDP
GSENSOR@
Vdd1
Vdd2
+5VS_LED
2
2
G
R587
10K_0402_5%
KBL@
1
2
3
4
+3VS_HDP
CG13
1U_0402_6.3V6K
1 GSENSOR@
CG14
2
1
SA00004GB00
Place UG1 and UG4
on TOP Layer
@
0.22U_0402_10V4Z
UG5
1
<13,26,44> EC_SMB_CK2
P1_6/CLK0/SSI01
11
P1_5/RXD0/CNTR01/INT11#
12
P1_4/TXD0
13
P1_3/KI3#/AN11/TZOUT
14
P3_5/SSCK/SCL/CMP1_2
HDPACT
<44>
2
+5VS
UG1
G-Sensor
JBLG
SELF_TEST
+3VS_HDP
2
P3_7/CNTR0#/SSO/TXD1
RG3 2
GSENSOR@
1
4.7K_0402_5%
3
RESET#
RG4 2
GSENSOR@
1GXOUT
4.7K_0402_5%
4
XOUT/P4_7
5
RG5 2
GSENSOR@
<44>
HDPINT
HDPINT
1GXIN
4.7K_0402_5%
RG6
2
1 4.7K_0402_5%
GSENSOR@
RG7
2
1 1K_0402_5%
GSENSOR@
1
CG7
0.1U_0402_10V7K
GSENSOR@ 2
VSS/AVSS
P1_2/KI2#/AN10/CMP0_2
SA00003A600
2011/12/14
15
HDPLOCK <44>
VOUTZ
P4_2/VREF
16
VCC/AVCC
17
VOUTX
MODE
18
VOUTY
P3_3/TCIN/INT3#/SSI00/CMP1_0
19
P3_4/SCS#/SDA/CMP1_1
20
XIN/P4_6
7
8
9
P4_5/INT0#/RXD1
10
1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_10V7K
R5F211B4D34SP
2
Deciphered Date
RG10 47K_0402_5%
2
1
GSENSOR@
+3VS_HDP
1
2
CG6
0.1U_0402_10V7K
GSENSOR@
EC_SMB_DA2 <13,26,44>
GSENSOR@
Compal Secret Data
Issued Date
6
RG9
47K_0402_5%
GSENSOR@
1
Keyboard LED
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HG
Sheet
45
of
61
5
4
3
2
1
+3VL
2
Power Button
Touchpad Connector
R395
1
100K_0402_5%
1
For debug
2
JTP
ON/OFFBTN#
ON/OFFBTN# <44>
<44>
<44>
C458
0.1U_0402_25V6
@
+3VS
TP_DATA
TP_CLK
<11,12,26,36> PM_SMBCLK
<11,12,26,36> PM_SMBDATA
SW3
D
1
2
3
4
D83
ON/OFFBTN#
2
PWR_ON_LED#
3
For EMI request
1
2
3
4
5
6
1
2
3
4
5
6
7
8
GND
GND
D
ACES_88058-060N
1
G
G
NTC017-DA1J-D160T_4P
6
5
@
L30ESD24VC3-2_SOT23-3
@
@
JPOWER
GND
GND
5
6
PWR_ON_LED#
D89
1
R22
ON/OFFBTN#
2
390_0402_5%
+5VALW
TP_DATA
2
TP_CLK
3
1
YSDA0502C_SOT23-3
@
JOINT_F1017WR-S-04P
please place near JFUNCTION
BATT CHARGE /FULL LED & AC IN
Screw Hole
ESD solution
D21
White
CPU
BATT_CHG_LOW_LED# <44>
H4
H_4P2x4P7
@
H5
H_7P0N
@
PCH
H6
H_3P0
@
H7
H_3P7x3P0
@
H8
H_4P0N
@
1
1
VGA
H3
H_4P7
@
1
3
H2
H_4P2
@
1
1
+5VALW
H1
BATT_FULL_LED# <44>
1
2
390_0402_5%
R52
2
510_0402_5%
1
1
1
R48
2
H_7P0N
@
1
1
2
3
4
1
1
2
3
4
Amber
HT-210UD5/BP5-A1681 _AMBER-WHITE
C
C
White LED bright when AC-adaptor is plugged and a Battery is full charged
MINI CARD -- 3G
Amber LED bright when charging battery from AC-adaptor
MINI CARD -- WLAN
Amber LED blink during Critical Low battery
H28
H29
H_3P3
@
1
D22
White
1
H_3P3
@
POWER LED
R49
2
390_0402_5%
R53
2
510_0402_5%
PWR_ON_LED# <44>
NPTH
PWR_SUSP_LED# <44>
H_3P0
@
H20
H_3P0
@
H21
H_3P0
@
H23
H_3P0
@
H24
H_3P0
@
H30
H_3P0
@
H22
H_3P2x3P7N
@
H_3P2N
@
1
H_3P0
@
H16
1
H15
1
H_3P0
@
1
1
H_3P0
@
H14
1
Amber
HT-210UD5/BP5-A1681 _AMBER-WHITE
H13
1
H10
1
1
1
3
1
1
1
2
1
+5VALW
WiMAX LED
EMI solution
2
LED_WIMAX# <36>
3
HT-110UD5_AMBER
4
PCB Fedical Mark PAD
Q156A
2N7002DW-T/R7_SOT363-6
WIMAX@
FD1
Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@
FD2
@
@
FD3
@
FD4
B
@
1
A
1
1
2
1
1
1
2
R66
510_0402_5%
3
+5VALW
6
1
D23
B
R819
2
1
10K_0402_5%
WIMAX@
5
+3VS
WL_BT_LED# <44>
ISPD
UH1
FUNCTION/B Connector
UH1
Panther Point 82HM77 C-1 HM77
@
JFUN
GND
GND
6
5
4
3
2
1
4
3
2
1
R8
+5VS_FUNC
2
KSO0
KSIFUNCTION
2 R1467 KSI7
0_0402_5%
1 ECO@ 2 R1466 KSI6
0_0402_5%
1 3D@
HM76R1@
UV4
R1
SA00005FHA0
SLJ8E
Panther Point HM76 SLJ8E C1
N13PGLR1@
UV4
N13PGSR3@
KSIFUNCTION
KSI7
<44,45>
KSI6
<44,45>
Green LED
SC500009S00 VF=2.8V~3.15V, Isink<15mA
White LED
SC500004W00 VF=2.75V~3.15V, Isink<15mA
1
I/O1
I/O3
4
SA0000518C0
DAZ0OT00400
N13P-GL-A1
N13P-GS-A2
PCB LA-8391P
2
GND
VDD
5
R3
SA000051880
N13PGSR1@
DC30100AA00
3
I/O2
I/O4
6
KSO0
UV4
R3
SA00005FHE0
SLJ8E
HM76R3@
N13PGLR3@
SA000051A60
PJP1
N13P-GL-A1
45@
PJP1
FUNCTION_LED#
AZC099-04S.R7G_SOT23-6
A
please place near JFUNCTION
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
5
ZZZ
SA000051A00
D90
390_0402_5%
1
+5VS
FUNCTION_LED# <44>
KSO0
<44,45>
JOINT_F1017WR-S-04P
A
HM77R1@
R1
SA00005AGH0
SLJ8C
4
3
2
Document Number
Rev
B
4019HG
1
Sheet
46
of
61
A
B
C
+3VALW TO +3VS
Q11A
Q11B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
@
1
2
2
C821
<31,32,37> PCH_PWR_EN#
@
1 R5534 2
0_0402_5%
<44> PCH_PWR_EN
PCH_PWR_EN#
1
1
2
1
C822
D
Q190
SUSP
2
G
2N7002_SOT23-3
S
3
R413
820K_0402_5%
@
1
1
C468
2
2
D
3
C467
S SB570020110
2N7002E-T1-E3_SOT23-3
1
Q5527
2
G
R5529
100K_0402_5%
2
2
1
R407
R470
470_0805_5%
R5545
10K_0402_5%
1
2
2
1 R410
2
+VSB
200K_0402_5%
0.1U_0402_10V7K
1
470_0805_5%
2
For EMI
0.1U_0402_10V7K
Q10B
1
1U_0402_6.3V6K
3 1
3 1
Q10A
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
2
3
4
+5VALW
+5VS
4
R412
820K_0402_5%
2
S
S
S
G
SI4800BDY_SO8
4
C466
6
1
1
2
C465
2
R406
1
C461
D
D
D
D
6
2
1 R409
2
+VSB
120K_0402_5%
8
7
6
5
1
2
0.022U_0402_25V7K
4.7U_0805_10V4Z
1
Q30
1U_0402_6.3V6K
SI4800BDY_SO8
1
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C462
1
C460
2
1
2
3
4
S
S
S
G
+5VS
2
1
C459
D
D
D
D
4.7U_0805_10V4Z
Q29
8
7
6
5
+1.8VS
Vgs=10V,Id=9A,Rds=18.5mohm
+5VALW
Vgs=10V,Id=9A,Rds=18.5mohm
0.01U_0402_25V7K
+3VS
E
+5VALW TO +5VS
470_0805_5%
+3VALW
D
Q43
C473
FDS6676AS_SO8
4.7U_0805_10V4Z
OPT@
OPT@
C481
C478
0.1U_0402_25V6
1U_0402_6.3V6K
OPT@
OPT@
R430
C475
820K_0402_5%
4.7U_0805_10V4Z
OPT@
OPT@
R431
R146
220K_0402_5%
100K_0402_5%
OPT@
OPT@
R429
Q188
470_0805_5%
2N7002_SOT23-3
OPT@
OPT@
Q13
2N7002DW-T/R7_SOT363-6
OPT@
Q44
FDS6676AS_SO8
OPT@
2
1
3
S
2
G
2
2
2
1
R468
470_0805_5%
1
1
1
2
SUSP
SUSP
0.75VR_EN <52>
D
Q6A
2
<42,44,53,54,58> SUSP#
S
2N7002DW-T/R7_SOT363-6
SUSP
Q189
SUSP
2
G
2N7002_SOT23-3
D
S
2
G
Q60
2N7002_SOT23-3
2
5
2N7002DW-T/R7_SOT363-6
+5VALW
For reduce Rds‐on 12/05 PVT
+VRAM_1.5VS
+1.5V
0.75VR_EN
2
220K_0402_5%
Q6B
Q13B
2N7002DW-T/R7_SOT363-6
DIS@
5
1 DIS@ 2
100K_0402_5% R146
D
<5,9,36>
1
R158
<53,54> VCCP_PWRGOOD
R421
22_0805_5%
1
R430
Q13A
820K_0402_5%
DIS@
DIS@
2 VGA_PWROK#
2N7002DW-T/R7_SOT363-6
R422
100K_0402_5%
3
C481
DIS@
+1.05VS_VCCP
3
C473
DIS@
R429
DIS@
4
2
1
6
VRAM_1.5VS_GATE
1
0.1U_0402_25V6
2
4.7U_0805_10V4Z
FDS6676AS_SO8
2
DIS@
1 R431
2
+VSB
220K_0402_5%
+0.75VS
1
2
C475
DIS@
4.7U_0805_10V4Z
1
S
S
S
G
1
C478
DIS@
1U_0402_6.3V6K
1
D
D
D
D
1
2
3
4
3 1
1
DIS@
2
Q43
8
7
6
5
470_0805_5%
Vgs=10V,Id=14.5A,Rds=6mohm
+5VALW
6
+VRAM_1.5VS
4
+1.5V
For S3 CPU Power Saving
3
+1.5V to +VRAM_1.5VS
8
7
6
5
Q188
DIS@
2N7002_SOT23-3
Q44
DIS@
D
D
D
D
S
S
S
G
1
2
3
4
+5VS TO +5VS_ODD
VRAM_1.5VS_GATE
close to PU700
close to PL402
+5VALW
+5VALW
+5VS_ODD
+5VS
+3VS
+5VS
2
2
1
close to PU450
+3VS
ODD_EN#
@
2
@
1
C924
2
1
C918
1
2N7002DW-T/R7_SOT363-6
2
AO3413_SOT23
C217
0.01U_0402_25V7K
@
2
@
2
2
PJ28
JUMP_43X79
@
+5VS_ODD
1
1
C679
4.7U_0805_10V4Z
@
1
C925
10U_0603_6.3V6M
2
2
+1.5V
0.1U_0402_10V7K
Q207B
5
2N7002DW-T/R7_SOT363-6
OPT@
@
1
C919
10U_0603_6.3V6M
1
3
Q207A
VGA_PWROK#
2
2N7002DW-T/R7_SOT363-6
OPT@
2
1
C923
0.1U_0402_10V7K
1
C920
Q45
2
2
47K_0402_5%
1
1
1
3
3
4
2N7002DW-T/R7_SOT363-6
Q53B
1
2
ODD_EN#
C471
0.1U_0402_10V7K
1
R440
1
6 1
5
10U_0603_6.3V6M
0.1U_0402_10V7K
10U_0603_6.3V6M
0.1U_0402_10V7K
close to PU700
2
R441
10K_0402_5%
2
C680
1U_0402_6.3V6K
3
2
@
+3VALW TO +3V_WLAN
for AOAC and WOWL
C686
1U_0402_6.3V6K
OPT@
+3VALW
+3VALW
1
C685
4.7U_0603_6.3V6K
@
1
<30>
Q53A
4
+1.05VS_DGPU
6
2
2
C493
OPT@
1
1
0.1U_0402_25V6
S
AO3416_SOT23-3
OPT@
3
2
2
G
1
2
R457
470_0805_5%
@
2
R460
22_0805_5%
OPT@
10U_0603_6.3V6M
Q56
close to PL402
+5VS
2
1
+1.05VS_DGPU
R434
330K_0402_5%
OPT@
0.1U_0402_10V7K
1
1
D
1
C922
2
1
Vgs=4.5V,Id=3A,Rds<22mohm
PJ33
JUMP_43X118
@
2
@
+5VALW
+1.05VS_VCCP
3
2
1
C916
@
G
Short PJ33 for Discrete SKUs
2
1
C921
D
+1.05VS_VCCP to +1.05VS_DGPU
@
S
1
C917
2
FDS6676AS_SO8
Q206B
2N7002DW-T/R7_SOT363-6
OPT@
B
2
1
1
5
2N7002_SOT23-3
Q55
2
G
D
Issued Date
S
Compal Secret Data
DGPU_PWR_EN#
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
A
1
3
2
C684
1U_0402_6.3V6K
2 OPT@
4
2
1
1
4
R459
470_0805_5%
3 1
R458
470_0805_5%
OPT@
1
C683
4.7U_0805_10V4Z
@
need mount R105 if system
don't support AOAC or WOWL
2
2
+3VS_DGPU
+3V_WLAN
C908
0.01U_0402_25V7K
+VGA_CORE
3
1
2
AO3413_SOT23
OPT@
C492
0.01U_0402_25V7K
1
2
Q206A
OPT@
OPT@
1
2
2N7002DW-T/R7_SOT363-6
1
3
2
1
47K_0402_5%
OPT@
+3VS_DGPU
R104
0_0805_5%
DIS@
G
6
Q54
2
2
2
R105
0_0805_5%
@
AO3413_SOT23
Q210
2
1
D
<29,58> DGPU_PWR_EN
1
R426
1
0.1U_0402_10V7K
2
C491
0.1U_0402_10V7K
OPT@
S
DGPU_PWR_EN#
1
47K_0402_5%
R1457
2
C907
G
<36,44> AOAC_EN#
R433
100K_0402_5%
OPT@
4
1
D
+3VS
+3VALW
2
S
R1456
100K_0402_5%
+3VS to +3VS_DGPU
C
D
Document Number
Rev
B
4019HG
Sheet
E
47
of
61
A
B
C
D
VIN
@ PJP1
PL1
SMB3025500YA_2P
1
2
PF1
1
2
PC4
100P_0402_50V8J
1
2
2
SINGA_2DW-0005-B03
PC3
1000P_0402_50V7K
4
1
1
3
-
DC_IN_S2
2
10A_125V_451010MRL
PC2
100P_0402_50V8J
-
DC_IN_S1 1
2
+
2
1
1
PC1
1000P_0402_50V7K
+
1
RTC Battery
2
2
-
+
PBJ1
2
1
PR5
PR6
560_0603_5% 560_0603_5%
1
2 1
2 +RTCBATT
+RTCBATT
@ MAXEL_ML1220T10
SP093MX0000
@ PJ333
+3VLP
2
2
@
1
1
+3VL
+3VALWP
JUMP_43X39
2
2
PJ332
1 1
+3VALW
JUMP_43X118
(100mA,40mils ,Via NO.= 2)
(5A,200mils ,Via NO.= 10)
OCP=6.2A
@ PJ353
@ PJ352
3
3
VL
2
2
1
1
+5VL
+5VALWP
JUMP_43X39
2
2
1
1
+5VALW
@ PJ162
JUMP_43X118
(8.13A,200mils ,Via NO.= 16)
OCP=8.7A
+16VSP
2
2
1
1
+16VS
JUMP_43X79
@ PJ72
+VSBP
2
2
1
1
+VSB
@ PJ402
JUMP_43X39
(120mA,40mils ,Via NO.= 1)
2
2
1
1
JUMP_43X118
@ PJ182
+1.8VSP
2
2
1
1
@ PJ403
+1.8VS
+1.05VS_VCCPP
JUMP_43X118
2
2
1
1
+1.05VS_VCCP
JUMP_43X118
(1.54A,70mils ,Via NO.= 4)
OCP=4.2A
(17A,680mils ,Via NO.=34)
OCP=23.91A
ACIN
2
Precharge detector
Min.
typ.
Max.
H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V
@ PJ152
2
1 1
JUMP_43X118
@ PJ76
4
+0.75VSP
2
2
1
1
JUMP_43X79
(0.5A,40mils ,Via NO.= 1)
+0.75VS
+1.5VP
2
@ PJ153
1 1
+1.5V
2
JUMP_43X118
(15A, 600mils ,Via NO.= 30)
OCP=18A
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
A
B
C
Document Number
Rev
B
4019HG
D
Sheet
48
of
61
4
A
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 90 degree C
Recovery at 56 degree C
Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
1
VMB
SUYIN_200045MR009G171ZR
PF2
BATT_S1
9
8
7
6
5
4
3
2
1
1
2
1
2
2
@ PJP2
PC8
0.01U_0402_25V7K
PC7
1000P_0402_50V7K
@ PC15
.1U_0402_16V7K
2
PR14
1K_0402_1%
1
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
1
Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K
Rset = 3 * 7.87K = 23.61K ==> 23.7K
Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K
BATT+
15A_65V_451015MRL
1
1
1
1
930@ PC9
0.1U_0603_25V7K
930@ PR15
23.7K_0402_1%
2
+3VL
2
PR16
6.49K_0402_1%
2
1
9012@ PR17
10.7K_0402_1%
VL
1
1
3
1
BATT_TEMPA <44>
1
EC_SMB_DA1 <24,44,50>
1
1
1
<5,44> H_PROCHOT#
D
930@ PQ7
SSM3K7002FU_SC70-3
2
G
VCC TMSNS1
8
2
GND RHYST1
7
3
OT1 TMSNS2
6
OT2 RHYST2
5
4
1
1
100K_0402_1%_NCP15WF104F03RC
1
@PC17
@
PC17
.1U_0402_16V7K
1
2
2
PROCHOT_IN <44>
1
2
9012@ PR27
100K_0402_1%
D
2
PR24
1
PR25
100K_0402_1%
VL
1
2
1
9012@ PR30
110K_0402_1%
9012@ PR35
9012@PR35
100K_0402_1%
2
1
3
D
9012@ PQ8B
DMN66D0LDW-7_SOT363-6
G
2
1
9012@ PC16
.1U_0402_16V7K
PC11 @
0.1U_0603_25V7K
2
S
3
+VSBP
2
5
CPSETIN
<44>
S
4
@
2
1
2
PC10
0.22U_0603_25V7K
2
1
PR23
100K_0402_1%
VL
1
9012@ PQ8A
G
1
3
B+
3
2
9012@ PR32
0_0402_5%
<44,51> VS_ON
PQ5
TP0610K-T1-E3_SOT23-3
VCIN0_PH <44>
PH1
6
3
2
930@ PR28
30.9K_0402_1%
G718TM1U_SOT23-8
S
EC_SMB_CK1 <24,44,50>
1
930@ PU2
1
2
PR21
100_0402_1%
ADP_I
2
2
PR20
100_0402_1%
2
9012@ PR33
0_0402_5%
<44,50>
9012@ PR22
59K_0402_1%
+3VS
2
2
2
PR19
1K_0402_1%
930@ PR29
100K_0402_1%
2
930@ PR18
11.3K_0402_1%
1
2
1
2
+3VLP
PD6
PJSOT24C_SOT23-3
PD5
2
PJSOT24C_SOT23-3
3
2
9
8
7
6
5
4
3
2
1
2
GND
GND
GND
GND
1
13
12
11
10
PL2
SMB3025500YA_2P
1
2
2
1
D
3
1
22K_0402_1%
S
PR26
<27,51>
1
POK
2
PQ6
SSM3K7002FU_SC70-3
2
G
Adaptor protection
Adaptor
@ PC12
.1U_0402_16V7K
Throttling point ADP_I
Recovery point
ADP_I
90W
113.5W
1.783V
86.4W
1.357V
65W
71.8W
1.504V
62.5W
1.308V
2
1
0_0402_5%
4
4
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
A
B
C
Document Number
Rev
B
4019HG
D
Sheet
49
of
61
A
B
C
D
1
D
3
for reverse input protection
S
PQ206
SI1304BDL-T1-E3_SC70-3
2
G
1
2
1
2
1
1
B+
PQ201
SIS412DN-T1-GE3_POWERPAK8-5
5
PR217
2DH_CHG1 4
0_0402_5%
PC214
1
2
BQ24725_BATDRV
1
PR216
0_0402_5%
2
1
2
PC216
0.01U_0402_50V7K
4
@ PC231
220P_0402_25V8K
1
2
1
2
1
2
Remember to change PC124 from SE000006S80
to SE025104K80 (2011-02-22)
ILIM
SCL
9
PC209
0.1U_0603_16V7K
+3VALW
10
SDA
8
2
10K_0402_1%
IOUT
1
6
PR204
@ PC233
220P_0402_25V8K
11
@PC206
@
PC206
680P_0603_50V7K
@ PC232
68P_0402_50V8J
2
1
BATDRV
ACOK
7
<27,44> ACIN
PR219
@
PC201
10U_0805_25V6K
12
PC223
0.1U_0402_25V6
2
1
1
@
PC202
10U_0805_25V6K
SRN
ACDET
+3VL
BATT+
PC203
10U_0805_25V6K
ACDRV
1
4
2 BQ24725_ACOK 5
10K_0402_1%
3
2
SRP
BQ24725_ACDRV
PR218
10_0603_1%
SRP1
2 CSOP1
PR214
6.8_0603_5%
SRN1
2 CSON1
3
2
1
CMSRC
13
1
3
1
2
2
BQ24725_CMSRC
BQ24725RGRR_VQFN20_3P5X3P5
PR225
0.01_1206_1%
4
1 CSON1
14
1
2
GND
4
1 CSOP1
ACP
DL_CHG
2
2
CHG
2
PR206
4.7_1206_5%
15
1
2
LODRV
PL202
4.7UH_ETQP3W4R7WFN_5.5A_20%
PQ202
AO4468L_SO8
REGN
ACN
2
5
6
7
8
17
PAD
1
2BQ24725_BATDRV_1
1
@
PR203
4.12K_0603_1%
BQ24725_LX
16
BTST
HIDRV
18
19
PHASE
21
1
2
3
PC215
0.1U_0402_25V6
DH_CHG1
3
2
1
1 1
20
PU200
@ PC230
100P_0402_25V8K
2
1
1
2
1
PC220
0.1U_0402_25V6
2
2
1
PC219
0.1U_0402_25V6
1
2
PC227
10U_0805_25V6K
1
2
1
PC226
10U_0805_25V6K
1
PD202
RB751V-40_SOD323-2
BQ24725_REGN2
DH_CHG
BQ24725_LX
2
1U_0603_25V6K
VCC
BQ24725_ACP
1
PR222
4.12K_0603_1%
1U_0603_25V6K
PC205
1
8
7
6
5
BQ24725_BATDRV
0.047U_0402_25V7K
PR210
10_1206_1%
1
2
PD201
BAS40CW_SOT323-3
PC207
1
2
BQ24725_ACN
2
@
@ PC229
68P_0402_50V8J
2
1
PC212
0.1U_0402_25V6
2
3
2
2
1
2
2
VIN
1
2
PR221
4.12K_0603_1%
2
1
PC224
10U_0805_25V6K
3
PR205
0_0603_5%
BQ24725_BST 2
1
1
2
PC218
0.1U_0402_25V6
BQ24725_ACDRV_1
PQ205
MDS2659URH_SO8
PR215
0.01_2512_1%
1
4
PC217
0.1U_0603_25V7K
2
1
2
PC222
10U_0805_25V6K
1
8
7
6
5
PC221
10U_0805_25V6K
1
2
3
PL201
1UH_10.3A_20%
1
2
4
1
2
1
@ PR220
0_0402_5%
4
2
1
2
PC213
2200P_0402_50V7K
P2
PQ204
MDS2659URH_SO8
PC225
10U_0805_25V6K
P1
PQ203
TPCA8057-H 1N PPAK56-8
1
2
5
3
PC208
0.1U_0402_25V6
VIN
PR213
3M_0402_5%
BQ24725_VCC
2
PR212
1M_0402_5%
3
3
2
PC204
0.01U_0402_25V7K
PR201
100K_0402_1%
402K_0402_1%
1
1
2
VIN
1
2
2
2
PR208
270K_0402_1%
1
1
PR207
154K_0402_1%
VIN
BQ24725_ACDET
1
PR209
BQ24725_ILIM
ILIM and external DPM
3.97A
PR227
10K_0402_1%
1
2
2
EC_SMB_DA1 <24,44,49>
ADP_V
<44,49>
1
ADP_I
PR228
100P_0402_50V8J
PC228
.1U_0402_16V7K
2
2
47K_0402_1%
Please locate the RC
Near EC chip
2011-02-22
4
4
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
A
<44>
1
PC210
2
1
PR226
309K_0402_1%
EC_SMB_CK1 <24,44,49>
2
PR211
100_0402_5%
PC269
100P_0402_50V8J
2
1
1
Max.
PR202
66.5K_0402_1%
2
1
H-->L
L--> H
Typ
17.3V
17.8V
PC211
0.1U_0402_25V6
2
1
Vin Dectector
Min.
B
C
Document Number
Rev
B
4019HG
D
Sheet
50
of
61
5
4
3
2
1
2VREF_8205
D
2
PC363
1U_0603_10V6K
1
D
21
LX_3V
11
LL2
LL1
20
LX_5V
LG_3V
12
DRVL2
DRVL1
19
LG_5V
3
2
1
PQ352
FDMC7692S_MLP8-5
2
1 2
1
5
VCLK
TPS51125
4
3
2
1
18
VIN
VREG5
17
16
GND
SKIPSEL
PL352
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
1
2
1
VL
PC364
4.7U_0805_10V6K
3/5V _B+
1
S
+
2
2
PC365
0.1U_0603_25V7K
2VREF_8205
2
3
4
6
D
1
+
B
ENTRIP2
D
1
+5VALWP
Ipeak=8.13A
Imax=5.7A
F=245KHz
Total Capacitor 440uF
ESR 8.5mohm
2
1
2
PR361
1
1
@ PC240
220P_0402_25V8K
DRVH1
@ PC239
68P_0402_50V8J
2
1
DRVH2
PC352
220U_6.3V_M
2
1
10
PC351
220U_6.3V_M
UG_3V
PR355
BST_5V 1
2
0_0603_5%
UG_5V
17mohm
22
@ PR356
4.7_1206_5%
VBST1
<27,49>
PC355
2 0.1U_0603_25V7K
PR358
1
2
0_0603_5%
C
@ PC356
680P_0603_50V7K
VBST2
POK
PQ351
5
PC368
2200P_0402_25V7K
2
1
PC366
10U_0805_25V6K
2
1
1
ENTRIP1
3
2
VFB1
VREF
VFB2
TONSEL
9
BST_3V
2
PC362
1U_0402_6.3V6K
ENTRIP1
4
ENTRIP2
6
23
EN0
B+
5
24
PGOOD
PR360
499K_0402_1%
1
2
B
Ipeak=5A
Imax=3.5A
F=305KHz
Total Capacitor 330uF
ESR 15mohm
ENTRIP2
VO1
VREG3
15
1
2
3
5
15mohm
4
VO2
13
@ PC336
680P_0603_50V7K
2
2
4
PR357
130K_0402_1%
1
2
8
100K_0402_5%
+
PR335
1
2
0_0603_5%
2
0_0603_5%
PQ332
FDMC7692S_MLP8-5
1
1 2
@ PR336
4.7_1206_5%
P PAD
3/5V _B+
7
1
2
3
@ PC238
220P_0402_25V8K
PC331
330U_6.3V_M
1
2
@ PC237
68P_0402_50V8J
2
1
1
+3VALWP
25
PR338
1
PR337
100K_0402_1%
1
2
PU330
PC335
0.1U_0603_25V7K
1
2
PL332
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
1
2
PR365
19.1K_0402_1%
1
2
14
PC361
2
1
5
4
PR363
20K_0402_1%
1
2
4.7U_0805_10V6K
@ PC236
220P_0402_25V8K
PQ331
1
2
@ PC234
68P_0402_50V8J
2
1
PC360
4.7U_0805_25V6K
2
1
PC367
2200P_0402_25V7K
2
1
C
+3VLP
PR364
30K_0402_1%
1
2
ENTRIP1
B+
PL331
FBMA-L11-201209-121LMA50T_0805
2
1
@ PC235
100P_0402_25V8K
2
1
3/5V _B+
PR362
14K_0402_1%
1
2
PQ360A
G
2
5
G
PQ360B
1
S
SB00000EO00
1
VL
PR370
2
1
100K_0402_1%
<44,49>
VS_ON
9012@ PR373
0_0402_5%
PQ361
DTC115EUA_SC70-3
A
3
0.01U_0402_16V7K
2
@PC370
2
1
1
1
PR372
<44> EC_ON
2
A
42.2K_0402_1%
2
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
5
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
51
of
61
A
B
C
D
1
1
BST_1.5V-1
PR155
0_0603_5%
1
2
BST_1.5V
DH_1.5V-1
PR154
0_0603_5%
1
2
DH_1.5V
+1.5V
PGND
13
CS
12
VDDP
11
VDD
SYSON
2
GND
3
VTTREF
4
VDDQ
5
1
2
1
2
2
19
17
20
VTTSNS
PC161
10U_0805_6.3V6K
BOOT
VTT
1
@
2
VTTREF_1.5V
PR160
10.2K_0402_1%
2
1
PR164
0_0402_5%
2
1
<47> 0.75VR_EN
1
PC165
.1U_0402_16V7K
2
PR162
10K_0402_1%
EN_1.5V
@PC166
@
PC166
0.1U_0402_10V7K
+1.5VP
2
PR161
887K_0402_1%
1
2
1
1.5V_B+
PR163
0_0402_5%
1
2
PC163
0.033U_0402_16V7K
6
7
8
9
2
FB
S3
S5
1
+1.5VP
3
EN_0.75VSP
<44>
21
FB_1.5V
1
VTTREF_1.5V
off
on
on
2
+0.75VSP
off
off
on
+5VALW
@PC156
@
PC156
680P_0603_50V7K
2
Level
L
L
H
1
PC164
1U_0603_10V6K
PAD
VTTGND
RT8207MZQW_WQFN20_3X3
2
DIS
Ipeak=15A
Imax=10.5A
F=285KHz
Total Capacitor 1050uF,
ESR 3.6mohm
+5VALW
PU150
TON_1.5V
15mohm
VDD_1.5V
4
2
2
SNUB_+1.5VP 2
@PR156
@
PR156
4.7_1206_5%
1
3
FDMC7692S_MLP8-5
PQ152
+
18
1
14
TON
PC162
1U_0603_10V6K
1
2
PR159
5.1_0603_5%
1
2
1
2
3
1
1
1
PC157
330U_6.3V_M
1
2
@ PC244
220P_0402_25V8K
1
2
@ PC245
68P_0402_50V8J
HW side:
CD7 390uF 10m
VGA@ CV131 330uF 9m
Mode
S5
S3
S0
PR158
24.9K_0402_1%
1
2CS_1.5V
5
1
2
3
PL152
1UH_VMPI0703AR-1R0M-Z01_11A_20%
2
1
+1.5VP
PQ151
VLDOIN
LGATE
UGATE
15
2
PGOOD
4
PHASE
16
DL_1.5V
PC160
10U_0805_6.3V6K
+0.75VSP
SW_1.5V
PC159
10U_0805_6.3V6K
PC155
0.1U_0603_25V7K
1
2
5
1
2
PC154
10U_0805_25V6K
1
2
PC153
4.7U_0805_25V6-K
1
2
PC152
2200P_0402_50V7K
@ PC241
220P_0402_25V8K
1
2
@ PC243
100P_0402_25V8K
2
1
1.5V_B+
10
PL151
HCB1608KF-121T30_0603
1
2
@ PC242
68P_0402_50V8J
2
1
B+
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
PC167
0.1U_0402_10V7K
Note: S3 - sleep ; S5 - power off
4
4
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
A
B
C
Document Number
Rev
B
4019HG
D
Sheet
52
of
61
3
2
1
PL401
FBMA-L11-201209-121LMA50T_0805
2
1
+1.05VSP_B+
PR405
0_0603_5%
1
2
PC405
0.1U_0603_25V7K
BST1_+1.05VSP 1
2
4
1
@ PC248
100P_0402_25V8K
2
1
@ PC247
68P_0402_50V8J
2
1
PC411
2200P_0402_25V7K
2
1
PQ401
MDV1525URH
<47,54> VCCP_PWRGOOD
@ PC404
4.7U_0805_25V6-K
2
1
5
+5VALW
PR402
6.49K_0402_1%
2
1
PC403
10U_0805_25V6K
2
1
PC402
10U_0805_25V6K
2
1
D
PR401
3.4K_0402_1%
2
1
B+
2
4
DIS
Ipeak=20.53A
Imax=14.37A
F=300KHz
Total Capacitor 1320uF,
ESR 2.5mohm
@ PC246
220P_0402_25V8K
5
D
PU400
RF_+1.05VSP
5
TST
DRVL
6
1
1
TP
2
4
3
2
1
PR408
470K_0402_1%
PC407
1U_0603_10V6K
2
3D@ PC408
0.1U_0402_16V7K
11
TPS51212
2
OPTIMUS@ PR407
0_0402_5%
@ PC409
1000P_0402_50V7K
1
2
+1.05VSP1
@ PR409
1.2K_0402_1%
1
2
1
+
@ PC406
680P_0603_50V7K
2
C
2
C
1SNUB_+1.05VSP 2
+5VALW
LG_+1.05VSP
+1.05VS_VCCPP
1
7
@ PC249
220P_0402_25V8K
V5IN
2
VFB
1
4
PL402
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
2
@ PC250
68P_0402_50V8J
FB_+1.05VSP
UG_+1.05VSP1
2
SW
SW_+1.05VSP
PC401
330U_2.5V_M
EN
8
PC410
.1U_0402_16V7K
3
1
EN_+1.05VSP
PR403
0_0402_5%
1
2
2
UG_+1.05VSP
1
9
@ PR406
4.7_1206_5%
10
DRVH
3
2
1
VBST
TRIP
1
<42,44,47,54,58> SUSP#
PGOOD
2
PQ402
TPCA8059-H_PPAK56-8-5
3D@ PR407
301K_0402_1%
1
2
BST_+1.05VSP
1
TRIP_+1.05VSP
5
PR404
100K_0402_1%
1
2
+1.05VS_VCCPP
PR411
4.99K_0402_1%
2
1
PR413
100_0402_1%
2
1
VCCIO_SENSE <8>
2
VCCIO_SENSE1
1
PR410
10.2K_0402_1%
B
B
TV@PD203
TV@
PD203
TV@PR807
TV@
PR807
1
2
LNB_EN
A
2
@ PR808
100K_0402_1%
1
@ PC1039
0.1U_0402_10V7K
2
1
47K_0402_1%
<44>
LNB_OC#
2
1
1
1
1
2
A
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Date:
5
+16VSP
@ PC267
100P_0402_25V8K
3
APW7237BI-TRG_SOT23-5
2
FB
EN
@ PC266
100P_0402_25V8K
1
2
2
LX
GND
VIN
TV@ PC1037
10U_0805_25V6K
4
PU160
TV@ PC1036
10U_0805_25V6K
5
TV@PL162
TV@
PL162
MCK1608471YZF_0603
1
2
TV@ PR805
604K_0603_1%
TV@
TV@ PR810
47K_0402_1%
1
2
2
2
1
TV@ PR806
51.1K_0402_1%
APL3511CBI-TRG_SOT23-5
2
2
1
3
EN#
2
4
1
BAT43WS-7-F_SOD323-2
2
OCB
1
@ PC1040
0.1U_0402_10V7K
2
1
2
1
TV@ PC1035
2.2U_0603_16V6K
GND
VIN
TV@ PC964
22U_0805_6.3V6M
<44>
5
1
TV@ PC963
22U_0805_6.3V6M
+5VALW
VOUT
1
TV@ PL161
10UH_MLPS-5020-100M-E_1.5A_20%
LX_AVDD
1
2
TV@PU161
TV@
PU161
4
3
2
Rev
B
4019HG
Sheet
1
53
of
61
5
4
3
2
1
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
VID [0]
0
0
1
1
D
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
D
2
PC456
680P_0603_50V7K
1
output voltage adjustable network
2
SNUB_+VCCSA
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 8A
1
PR456
4.7_1206_5%
PVIN
LX
2
10
SVIN
LX
3
9
FB
PG
4
8
VOUT
EN
5
7
VID1
VID0
6
PR459
100K_0402_5%
2
1
SA_PGOOD <44>
+3VS
+VCCSA_EN
1
2
PR458
0_0402_5%
1
2
PR461
1K_0402_5%
1
2
PR460
1K_0402_5%
1
2
<47,53>
+VCCSA
PC454
22U_0805_6.3V6M
1
2
11
PL452
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
+VCCSA_PHASE
PC453
22U_0805_6.3V6M
1
2
1
1
PC452
22U_0805_6.3V6M
1
2
+VCCSAP_FB
2
LX
13
1
2
PC458
22U_0805_6.3VAM
1
2
1
PC459
22U_0805_6.3VAM
1
2
2
PC460
0.1U_0603_25V7K
C
PC461
2200P_0402_50V7K
PC457
68P_0402_50V8J
PU450
SY8037BDCC
12 PVIN
PC451
22U_0805_6.3V6M
1
2
+VCCSA_PWR_SRC
@ PC455
0.1U_0402_10V7K
PL451
HCB1608KF-121T30_0603
1
2
GND
+5VALW
C
PR455
100_0402_5%
2
1
VCCP_PWRGOOD
PR457
0_0402_5%
2
1
+VCCSA_SENSE <9>
H_VCCSA_VID0 <9>
H_VCCSA_VID1 <9>
B
B
PL182
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
1
@ PR182
499K_0402_1%
0.1U_0402_10V7K
PR184
10K_0402_1%
1
2
1
2
2
PC185
FB_1.8V
Ipeak=1.308A
ILIM = 4A
F=1MHz
PC183
22U_0805_6.3VAM
1
150K_0402_1%
PR183
20K_0402_1%
2
PR186
2
NC
TP
NC
1
EN_1.8V
1
2
7
PR181
PC186
1
2
SUSP#
11
<42,44,47,53,58>
FB=0.6Volt
PC182
22U_0805_6.3VAM
1
6
2
FB
1
EN
2
PC184
22U_0805_6.3VAM
+1.8VSP
2
SVIN
5
3
4.7_1206_5%
8
LX
LX_1.8V
680P_0603_50V7K
PVIN
2
1
9
LX
PC187
68P_0402_50V8J
2
1
4
PVIN
PG
10
1
+5VALW
PU180
SY8033BDBC_DFN10_3X3
PL181
HCB1608KF-121T30_0603
1
2
A
A
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title
Size
C
Date:
5
4
3
2
Document Number
Rev
B
4019HG
1
Sheet
54
of
61
5
4
3
2
DISABLE GFX function
3D@ PC554
0_0402_5%
3D@ PC549
0_0402_5%
3D@ PR549
0_0402_5%
3D@ PR552
0_0402_5%
DC/QC GFX SWITCH
QCG@ PR549
24K_0402_1%
QCG@ PR552
1.65K_0402_1%
QCG@ PR560
24K_0402_1%
QCG@ PR564
39K_0402_1%
3D@ PC560
0_0402_5%
1
3D@ PR571
0_0402_5%
DCG@ PR552
1K_0402_1%
1
2
CSCOMPA
GFX@ PC552
1000P_0402_50V7K
DROOPA
CSREFA
1
2
2
2
PH503
100K_0402_1%_TSM0B104F4251RZ
1
2 PR588 1
2
1
GFX@ PH502
100K_0402_1%_TSM0B104F4251RZ
GFX@ PR561
137K_0402_1%
2
1
2
1
137K_0402_1%
1
2
LG1
HG1
BST1
TSENSE
1
1
CSP1A
CSP3
SW1
<56>
<56>
1
2 BST1_1 1
2
PR505
PC505
2.2_0603_5%
0.22U_0402_10V6K
3P: 73.2K
2P: 41.2K
3P: install
2P: @
CSP2
3P: 21K
2P: 12.4K
CSREF
<56>
CSP1
CSREF
PC575
1000P_0402_50V7K
DC@ PR590
806_0402_1%
SWN3
<56>
SWN2
<56>
SWN1
<56>
2
B
1
CSREF
QC@ PR579
6.98K_0402_1%
1
2
QC@ PC569
0.047U_0402_16V7K
2
2
CSP3
1
DRVEN <56>
1
6132_PWM <56>
CSREF
CSP2A
DC@ PR577
0_0402_5%
<56>
Option for
2 phase CPU
2
SW2
3D@ PR600
0_0402_5%
<56>
DCG@ PR571
0_0402_5%
2
1
2
2
2
LG2
6132P_VCCP
<56>
1
2 BST2_1 1
2
PR515
PC515
<56>
2.2_0603_5%
0.22U_0402_10V6K
PC564
<56>
1
2
1
2
PR574
2.2U_0603_10V7K
PR5732
0_0402_5%
1
<56>
+5VS
0_0402_5%
.1U_0402_16V7K
CSP1
CSP2
CSP3
1
PR5832
6.98K_0402_1%
PC571
0.047U_0402_16V7K
PR5872
1
6.98K_0402_1%
PC576
0.047U_0402_16V7K
CSSUM
3P: 3.65K
2P: 9.53K
PC581
1000P_0402_50V7K
DROOP
1
2
1
CSREF
3P: 23.7K
2P: 24.9K
3P: 806
2P: 1K
2
3P: 1500p
.1U_0402_16V7K
CSCOMP
DC@ PR597
1K_0402_1%
1
2
1
PC579
1
2
DC@ PR589
8.06K_0402_1%
3P: 348
2P: 1.21K
FB_CPU2
3P: 2200p
2P: 3300p
DC@ PR592
24.9K_0402_1%
1
2
2
PC577
0.033U_0402_16V7K
2
1
1
2P: 4.32K
HG2
SW1A
2
2P: 1000p
LG1A
BST2
Option for
1 phase GFX
1
2 BST3_1 1
2
GFX@ PR525 GFX@ PC525
<56>
2.2_0603_5%
0.22U_0402_10V6K
PC568
1
2
CSCOMP
PR584
DC@ PC572
DC@ PR585
49.9_0402_1%
1000P_0402_50V7K 4.32K_0402_1%
PR586
PC574
1
2FB_CPU1 1
2
2
1COMP_CPU12
1
10_0402_1%
0.033U_0402_16V7K
DC@ PC573
1
2FB_CPU3 1
2
3P: 330p
3P: 6.04K
3300P_0402_50V7K
HG1A
@ PR605
0_0402_5%
DC@ PC570
10P_0402_50V8J
2
1
BST3
1
3P: 22p
2P: 10p
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DC@ PR576
41.2K_0402_1%
1
2
2
PR582
1K_0402_1%
1
2
B
TRBST#
PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
2
DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
CSCOMPA
CSSUMA
1
PC567
1000P_0402_50V7K
VSP
1
<8> VCCSENSE
VSN
1
PR580
0_0402_5%
1
2
2
<8> VSSSENSE
C
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PR578
0_0402_5%
1
2
<5,27,44> VGATE
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
NCP6132AMNR2G QFN 60P
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
TRBST#
FB_CPU
COMP_CPU
IMON
ILIM_CPU
1
2
DC@ PR581 12.4K_0402_1% DROOP
2
<44> VR_HOT#
<56>
+5VS
2
2
1
2
1
PR575
10K_0402_5%
SWN2A
6132_PWMA <56>
@ PR606
0_0402_5%
PR572
1K_0402_1%
+3VS
<56>
2P: 36K
1P: 26.1K
1
2
DCG@ PR564
26.1K_0402_1%
1
2
2
1
SWN1A
2P: install
1P: @
@ PR607
0_0402_5%
CPU_B+
PC566
47P_0402_50V8J
1
PR569
10K_0402_1%
1
2
PR570
95.3K_0402_1%
1
2
1
2
3
VR_ON_CPU
4
VR_SVID_DAT1 5
VR_SVID_ALRT# 6
VR_SVID_CLK
7
VBOOT
8
ROSC_CPU
9
VRMP
10
VR_HOT#
11
VGATE
12
13
14
DIFF_CPU
15
2
QCG@PC559
QCG@
PC559
0.047U_0402_16V7K
1
2
QCG@PR562
QCG@
PR562
6.98K_0402_1%
1
2VR_SVID_DAT1
0_0402_5%
1
PR568
VR_ON
PC565
0.01U_0402_25V7K
<44>
PR567
0_0402_5%
1
2
6132_VCC
GFX@ PR559 6.98K_0402_1%
1
2
GFX@ PC560
.1U_0402_16V7K
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PC563
.1U_0402_16V7K
PU500
CSP2A
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
1
2
2
PR566
1
PC561
2.2U_0603_10V7K
1
2
GFX@ PC556
0.047U_0402_16V7K
CSREFA
CSREFA <56>
1
TSENSE
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VS
54.9_0402_1%
1
2
1
130_0402_1%
1
2
PR565
<8> VR_SVID_DAT
<8> VR_SVID_ALRT#
<8> VR_SVID_CLK
2
PR563
2_0603_5%
1
2
C
PC562
.1U_0402_16V7K
3D@ PR601
0_0402_5%
1
3D@ PR602
0_0402_5%
2
+1.05VS_VCCPP
GFX@ PC558
1000P_0402_50V7K
CSP1A
GFX@ PC557
1000P_0402_50V7K
1
2
<9> VCC_AXG_SENSE
CSREFA
SWN1A
GFX@ PR558
63.4K_0603_1%
CSP2A
CSP1A
TSENSEA
1
2
DCG@ PR560
16.5K_0402_1%
2P: 21.5K
1P: 15.8K
2
2P: install
1P: @
1
1
<9> VSS_AXG_SENSE
2
1
2 SWN2A
QCG@PR557
QCG@
PR557
63.4K_0603_1%
2
GFX@ PC555
3300P_0402_25V7K
2
COMPA1 1
@ PR603
0_0402_5%
2
1
1
GFX@ PR556
5.11K_0402_1%
2
2
GFX@ PR555
1K_0402_1%
NTC_PH203
2
1
GFX@ PR553
165K_0402_1%
@ PR604
0_0402_5%
1
GFX@ PC554
10P_0402_50V8J
1
2
D
TSENSEA
GFX@ PH501
220K_0402_5%_ERTJ0EV224J
1
GFX@ PC553
330P_0402_50V7K
FBA2
1
2
1
1
DCG@ PR549
24.9K_0402_1%
GFX@ PR554
10_0402_1%
1
2
2
GFX@ PC551
0.033U_0402_16V7K
2
GFX@ PR551
75K_0402_1%
1
1
2
2P: 24K
1P: 24.9K
2
GFX@ PR550
806_0402_1%
1
2
FBA1
1
GFX@ PR548
8.06K_0402_1%
1
2
TRBSTA#
1
D
GFX@ PC584
180P_0402_50V7K
GFX@ PC548
.1U_0402_16V7K
1
2
GFX@ PC549
1200P_0402_50V7K
GFX@ PR547
GFX@ PC547
10_0402_1%
0.033U_0402_16V7K
1
2 FBA3 1
2
GFX@ PC550
330P_0402_50V7K
2P: 1.65K
1P: 1K
DC@ PC578
2P: 1200p
1200P_0402_50V7K
1
2
PC580
330P_0402_50V7K
1
2
1
2
PR594
PR595
75K_0402_1%
165K_0402_1%
2
PH504
1
PR5912
130K_0603_1%
SWN1
1
PR5932
130K_0603_1%
SWN2
1
2
QC@ PR596
130K_0603_1%
SWN3
3P: install
2P: @
1
220K_0402_5%_ERTJ0EV224J
A
A
DC/QC CPU SWITCH
QC@ PR576
73.2K_0402_1%
QC@ PR581
21K_0402_1%
QC@ PC578
1500P_0402_50V7K
QC@ PR592
23.7K_0402_1%
QC@ PC573
2200P_0402_50V7K
QC@ PR585
6.04K_0402_1%
QC@ PC570
22P_0402_50V8J
QC@ PR590
806_0402_1%
QC@ PC572
330P_0402_50V7K
QC@ PR597
806_0402_1%
Compal Secret Data
Issued Date
QC@ PR589
8.06K_0402_1%
2011/12/14
2012/12/31
Deciphered Date
Title
Date:
5
Custom
4
3
2
Rev
B
4019HG
Sheet
1
55
of
61
3
1
CSREF <55>
<55>
LG2
5
4
10_0402_1%
<55>
2
2
3
2
1
SWN1
HG3
SW
7
SW3
GND
6
5
NCP5911MNTBG_DFN8_2X2
4
2
DRVL
LG3
2
1
SNUB_CPU3
VCC
3
SH00000HD00
PR599
V2N_CPU 2
SWN2
C
1
4
2
3
SH00000HD00
QC@ PR519
10_0402_1%
V3N_CPU 2
1
CSREF
SWN3
<55>
CPU_B+
CPU_B+
7
4
VCC
GND
6
DRVL
5
HG2A
4
2
1
3
2
1
LG2A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title
Size
C
Date:
5
4
3
2
QCG@ PC521
10U_0805_25V6K
2
1
QCG@ PQ519
MDV1525URH
5
@ PQ517
MDV1525URH
2
A
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
QCG@ PL506
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
SW2A
NCP5911MNTBG_DFN8_2X2
+GFX_CORE
SH00000HD00
3
V2N_GFX
8
SW
PR546
4.7_1206_5%
DRVH
EN
3
2
1
PWM
3
4
1
VCC_GFX2
2
4
QCG@ PR544
2.2_0603_1%
2
1
B
QCG@ PR523
<55>
10_0402_1%
2
1
CSREFA
PC546
680P_0402_50V7K
2
PC526
680P_0402_50V7K
SWN1A <55>
1
QCG@ PR528
0_0402_5%
9
SNUB_GFX2 2
2
FLAG
QCG@ PQ510
1
2K_0402_1%
1 EN_GFX2
BST
5
2
QCG@ PR521
0_0402_5%
1
+5VS
QCG@ PR520
2
1
3
2
1
1
2
DRVEN
QCG@ PC583
2.2U_0603_10V7K
@ PC260
220P_0402_25V8K
@ PC259
68P_0402_50V8J
2
1
1
GFX@ PR522
10_0402_1%
2
1CSREFA
2
SH00000HD00
BSTA2_1
QCG@ PC545
0.22U_0402_10V6K
@ PC257
220P_0402_25V8K
@ PC256
68P_0402_50V8J
2
1
1
2
GFX@ PC519
10U_0805_25V6K
2
1
@ PC258
100P_0402_25V8K
2
1
<55> 6132_PWMA
3
V1N_GFX
PR526
4.7_1206_5%
2
QCG@ PR545
2.2_0603_5%
1
2
QCG@ PU502
+GFX_CORE
GFX@ PL505
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
2
2
1
3
2
1
4
SNUB_GFX1
LG1A
GFX@ PQ508
5
<55>
GFX@ PC518
10U_0805_25V6K
2
1
@ PQ515
MDV1525URH
5
SW1A
1
<55>
4
3
2
1
GFX@ PQ513
MDV1525URH
5
4
3
2
1
HG1A
BSTA2
5
2Phase: install
1Phase:: @
<55>
<55>
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=33A
R_LL=1.9m ohm
OCP~65A
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=56A
R_LL=1.9m ohm
OCP~110A
B
GFX@ PR524
2.2_0603_1%
2
1
CSREF
1
10_0402_1%
QC@ PC511
10U_0805_25V6K
2
1
@ PQ511
MDV1525URH
5
QC@ PQ509
MDV1525URH
5
1
EN
2
+CPU_CORE
QC@ PL504
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
QC@ PQ506
QC@ PR527
0_0402_5%
D
QCG@ PC522
10U_0805_25V6K
2
1
8
PR536
4.7_1206_5%
DRVH
PC536
680P_0402_50V7K
PWM
4
3
2
1
2
4
QC@ PR534
2.2_0603_1%
2
1
3
2
1
9
3
2
1
2
1
1
QC@ PR518
0_0402_5%
FLAG
QC@ PR517
2
1EN_VCORE3 3
2K_0402_1%
2
1VCC_VCORE3 4
DRVEN
2
BST
QC@ PC582
2.2U_0603_10V7K
<55>
+5VS
1
5
<55> 6132_PWM
QC@ PC535
0.22U_0402_10V6K
2
1
BSTA1_1
QC@ PU501
C
QC@ PC510
10U_0805_25V6K
2
1
CPU_B+
QC@ PR535
2.2_0603_5%
BSTA1 1
2
PC508
10U_0805_25V6K
2
1
PC507
10U_0805_25V6K
2
1
1
SW2
PR516
4.7_1206_5%
3
2
1
<55>
+CPU_CORE
PL503
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
SNUB_CPU2
PR598
2
4
1
V1N_CPU
1
3
SH00000HD00
2
2
4
+CPU_CORE
@ PC255
220P_0402_25V8K
4
PR514
2.2_0603_1%
2
1
HG2
3
2
1
<55>
PQ507
MDV1525URH
5
2
1
1
@ PQ505
MDV1525URH
PC520
68U_25V_M
PC517
100U_25V_M
PC513
100U_25V_M
@ PC251
220P_0402_25V8K
@ PC253
100P_0402_25V8K
2
1
2
1
@ PC252
68P_0402_50V8J
2
1
2
PC516
680P_0402_50V7K
2
1SNUB_CPU1
2
PQ502
5
3
2
1
4
1
2
LG1
2
B+
+
@ PC254
68P_0402_50V8J
<55>
PR506
4.7_1206_5%
SW1
1
+
PL502
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
<55>
PC502
10U_0805_25V6K
2
1
4
1
+
1
CPU_B+
PL501
HCB4532KF-800T90_1812
2
1
PC506
680P_0402_50V7K
D
PC501
10U_0805_25V6K
2
1
PQ503
MDV1525URH
5
4
3
2
1
HG1
3
2
1
<55>
PR504
2.2_0603_1%
2
1
@ PQ501
MDV1525URH
5
CPU_B+
2
5
4
PQ504
5
SWN2A <55>
A
Document Number
Rev
B
4019HG
1
Sheet
56
of
61
5
4
3
2
PC910
10U_0805_6.3V6M
2
2
2
1
+
PC950
2
1
+
2
330U_D2_2V_Y
+
1
1
PC962
22U_0805_6.3V6M
2
1
+
2
@ PC949
+
1
1
330U_D2_2V_Y
2
2
2
2
1
1
1
1
2
1
2
1
2
PC948
2
PC931
22U_0805_6.3V6M
+
1
2
330U_D2_2V_Y
1
PC930
22U_0805_6.3V6M
1
2
1
PC961
22U_0805_6.3V6M
2
PC960
22U_0805_6.3V6M
2
1
PC959
22U_0805_6.3V6M
2
PC951
2
2
1
22U_0805_6.3V6M
2
2
2
1
PC925
22U_0805_6.3V6M
1
PC929
22U_0805_6.3V6M
2
1
@ PC935
330U_D2_2V_Y
2
1
PC928
22U_0805_6.3V6M
2
1
PC934 GFX@
330U_D2_2V_Y
2
1
PC927
22U_0805_6.3V6M
2
PC924
22U_0805_6.3V6M
2
PC933 GFX@
330U_D2_2V_Y
2
1
PC926
22U_0805_6.3V6M
PC923
22U_0805_6.3V6M
1
PC932 GFX@
330U_D2_2V_Y
1
2
1
1
1
PC958
22U_0805_6.3V6M
2
1
1
PC957
22U_0805_6.3V6M
PC920
22U_0805_6.3V6M
1
PC956
22U_0805_6.3V6M
2
1
PC955
22U_0805_6.3V6M
2
PC922
22U_0805_6.3V6M
1
PC954
22U_0805_6.3V6M
2
PC921
22U_0805_6.3V6M
1
+1.05VS_VCCP
PC953
22U_0805_6.3V6M
C
1
2
PC952
22U_0805_6.3V6M
PC919
22U_0805_6.3V6M
2
1
2
1
PC939 GFX@
22U_0805_6.3V6M
2
2
1
PC947 GFX@
22U_0805_6.3V6M
PC918
22U_0805_6.3V6M
PC938 GFX@
22U_0805_6.3V6M
2
2
1
PC946 GFX@
22U_0805_6.3V6M
PC917
22U_0805_6.3V6M
2
1
1
PC937 GFX@
22U_0805_6.3V6M
2
1
2
1
PC945 GFX@
22U_0805_6.3V6M
PC916
22U_0805_6.3V6M
1
PC936 GFX@
22U_0805_6.3V6M
2
1
2
1
PC944 GFX@
22U_0805_6.3V6M
2
1
PC943 GFX@
22U_0805_6.3V6M
1
PC915
10U_0805_6.3V6M
+CPU_CORE
1
Socket Top
7 x 22 µF (0805)
2 x (0805) no-stuff
sites
D
PC942 GFX@
22U_0805_6.3V6M
PC914
10U_0805_6.3V6M
PC941 GFX@
22U_0805_6.3V6M
PC913
10U_0805_6.3V6M
PC940 GFX@
22U_0805_6.3V6M
PC912
10U_0805_6.3V6M
5 x 22 µF (0805)
5 x (0805) no-stuff
sites
+GFX_CORE
D
PC911
10U_0805_6.3V6M
Socket Bottom
1
PC909
10U_0805_6.3V6M
2
PC908
10U_0805_6.3V6M
2
2
PC907
10U_0805_6.3V6M
2
2
PC906
10U_0805_6.3V6M
1
1
Below is 458544_CRV_PDDG_0.5 Table 5-8.
1
1
+CPU_CORE
1
2
C
+
2
+CPU_CORE
Chief River
1
+
1
+
PC901
330U_D2_2V_Y
2
2
1
PC902
330U_D2_2V_Y
+
2
1
PC903
330U_D2_2V_Y
+
330uF*9m
470uF*4.5m
22uF
10uF
16
10
1
PC904
330U_D2_2V_Y
2
+
PC905
330U_D2_2V_Y
8layer for DC CPU
2
4
B
B
8layer for QC CPU
5
16
10
6layer for DC CPU
5
16
10
6layer for QC CPU
4
16
10
1
GFX_CORE DC
2
12
GFX_CORE QC
3
12
1.05V_VCCP
2
12
A
A
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
5
4
3
2
Document Number
Rev
B
4019HG
Sheet
1
57
of
61
A
B
C
D
E
F
G
H
2
VGA_VID_2 2
1 PR703 1K_0402_1%
1K_0402_1% PR713 @
1
2
VGA_VID_3 2
1 PR704 1K_0402_1%
1K_0402_1% PR714
1
2
VGA_VID_4 2
1@ PR707 1K_0402_1%
2
VGA_VID_5 2
1 PR708 1K_0402_1%
1K_0402_1% PR715 @ 1
1
<13>
1@ PR702 1K_0402_1%
1K_0402_1% PR712 @ 1
<13>
1@ PR701 1K_0402_1%
VGA_VID_1 2
<13>
VGA_VID_0 2
2
VGA_VID_1
2
1
VGA_VID_2
<42,44,47,53,54>
VGA_VID_3
<13>
VGA_VID_4
<13>
VGA_VID_5
<13>
1
1K_0402_1% PR711
SUSP#
1K_0402_1% PR710
VGA_VID_0
<29,47>
1
DGPU_PWR_EN
3D@ PR737
10K_0402_1%
0_0402_5%
2
3
1
2
2
PC708
1000P_0402_50V7K
2
PWRMOS_TEMP <44>
PR749
0_0402_5%
1
2
2
GND RHYST1
7
3
OT1 TMSNS2
6
OT2 RHYST2
5
2
G718TM1U_SOT23-8
GPU Skin temperature protection:
1
2
PR743
7.68K_0402_1%
Protection at 90 degree C
2
4
<44> PWR_GPS_DOWN#
Requlator temperature protection:
1
Recoveyr at 90 degree C
Protection at 125 degree C
Recoveyr at 105 degree C
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
A
B
C
D
E
F
4
Compal Secret Data
+3VL
@ PH703
100K_0402_1%_NCP15WF104F03RC
8
1
VCC TMSNS1
1
PU701
1
PR744
8.66K_0402_1%
PH702
100K_0402_1%_NCP15WF104F03RC
2
1
PC716
0.1U_0603_25V7K
2
PR741
8.66K_0402_1%
PR742
7.68K_0402_1%
1
+3VL
@ PR736
0_0402_5%
2
PR735
0_0402_5%
1
2
@ PC807
22U_0805_6.3V6M
PC806
47U_0805_4V6
PC811
4.7U_0603_6.3V6M
2
1
2
@ PC265
220P_0402_25V8K
1
PR739
133K_0603_1%
PC812
4.7U_0603_6.3V6M
PC805
22U_0805_6.3V6M
2
1
2
1
1
PR750
0_0402_5%
VGA_CSCOMP
PC810
4.7U_0603_6.3V6M
2
1
@ PC804
22U_0805_6.3V6M
2
1
PC809
4.7U_0603_6.3V6M
2
1
1
2
@ PC835
0.1U_0402_10V7K
@ PC834
0.1U_0402_10V7K
2
1
@ PC833
0.1U_0402_10V7K
2
1
@ PC832
0.1U_0402_10V7K
2
1
PC831
0.1U_0402_10V7K
2
1
PC830
0.1U_0402_10V7K
2
1
PC829
0.1U_0402_10V7K
2
1
1
2
PC828
0.1U_0402_10V7K
2
1
4
@ PC803
22U_0805_6.3V6M
2
1
PC808
4.7U_0603_6.3V6M
2
1
PC827
4.7U_0603_6.3V6M
PC826
4.7U_0603_6.3V6M
2
1
PC825
4.7U_0603_6.3V6M
2
1
PC824
4.7U_0603_6.3V6M
2
1
PC823
4.7U_0603_6.3V6M
2
1
PC822
4.7U_0603_6.3V6M
2
1
1
2
PC821
4.7U_0603_6.3V6M
2
1
1
2
2
PC710
560P_0402_50V7K
2
2
+
2
PC802
330U_D2_2V_Y
+
2
Ipeak=59A
Imax=45.7A
F=300kHZ
Total capacitor
1460u
ESR=1.8m ohm
1
1
1
PC709
1000P_0402_50V7K
1
PC801
330U_D2_2V_Y
PC800
330U_D2_2V_Y
PC820
4.7U_0603_6.3V6M
+
2
1
@ PC264
68P_0402_50V8J
2
1
PC715
330U_D2_2V_Y
3
2
1
1
@ PR706
4.7_1206_5%
2
Near VGA Core
1
@ PC262
220P_0402_25V8K
@ PC263
100P_0402_25V8K
2
1
2
1
@ PC261
68P_0402_50V8J
2
1
PC718
10U_0805_25V6K
2
1
PC717
10U_0805_25V6K
2
1
PC713
10U_0805_25V6K
2
1
PQ703
MDV1525URH
5
PQ701
MDV1525URH
5
3
2
1
2
3
2
1
CSCOMP
16
CSREF
LLINE
RAMP
RT
CSFB
15
14
13
12
+
PR738
220K_0402_1%
1
2
1
+VGA_CORE
PC819
4.7U_0603_6.3V6M
2
1
PC818
4.7U_0603_6.3V6M
2
1
PC817
4.7U_0603_6.3V6M
2
1
PC816
4.7U_0603_6.3V6M
2
1
PC815
4.7U_0603_6.3V6M
2
1
1
1
Under VGA Core
PC814
4.7U_0603_6.3V6M
2
1
1
2
4
2
+VGA_CORE
@ PH505
220K_0402_5%_ERTJ0EV224J
1
PC813
4.7U_0603_6.3V6M
2
1
1
PL702
0.36UH_PCMC104T-R36MN1R105_30A_20%
1
2
@ PC706
680P_0603_50V8J
33
2
PC711
2.2U_0603_10V6K
4
2
17
AGND
+5VS
1
AGND
VGA_DRVL
2
1
0_0603_5%
2
18
2
1
0_0603_5%
PR748
PQ704
19
4
3
2
1
DRVL
PGND
5
1
1
VGA_VCC
20
2
PR731
237K_0402_1%
1
2
VGA_RPM
VGA_IREF
PR730
80.6K_0402_1%
1
2
VGA_RAMP
2
VGA_CSCOMP 1
PVCC
4
PR745
VGA_RAMP-1
PC707
1000P_0402_50V7K
+VGA_CORE
VGA_SW
VGA_CSCOMP
PR734
1K_0402_1%
2
1
+VGA_B+
VGA_CSFB
Connect to input caps
3
VGA_DRVH
21
2
1
PR733 422K_0402_1%
ILIM
11
VGA_ILIM 8
PR726
20K_0402_1%
VGA_RT
GPU
PR729
7.15K_0402_1%
22
SW
COMP
VGA_VCC 7
RPM
2
PU700
DRVH
PR705
PC705
0_0603_5%
0.22U_0603_25V7K
2VGA_BOOST-1
1
2
PC714
10U_0805_25V6K
2
1
2
0_0402_5%
0_0402_5%
PR724
2
VID6
27
26
VID5
VID4
VID3
28
29
VID2
VID1
30
FB
VGA_COMP 6
23 VGA_BOOST 1
PQ702
5
ADP3211AMNR2G_QFN32_5X5
24
BST
5
FBRTN
VCC
B+
1
CLKEN#
4
PC712
1U_0603_10V6K
2
3
IREF
1
PC702
470P_0402_50V8J
IMON
9
2
PR725
1K_0402_1%
2VGA_COMP-1
1
PWRGD
2
10
1
PC701
47P_0402_50V8J
1
PR732
301K_0402_1%
1
2
<15> VGA_VCC_SENSE
VGA_FB
2
1
1
PC703
220P_0402_50V7K
PR728
0_0402_5%
2
1
2
<15> VGA_VSS_SENSE
PR747
24.9K_0402_1%
1
2
2
PR727
0_0402_5%
2
1
2
1
PC704
1000P_0402_50V7K
PL701
FBMA-L11-201209-121LMA50T_0805
2
1
PR740
10_0603_1%
1
0_0402_5%
+VGA_B+
25
PR723
2
2
PR721
PR722
1
1
0_0402_5%
0_0402_5%
2
2
PR720
PR719
1
1
0_0402_5%
2
2
PR718
1
1
+5VS
2
EN
PR709
1K_0402_1%
31
32 VGA_EN
1
+3VS
VID0
3D@ PR717
40.2K_0402_1%
1
2
OPTIMUS@ PR746
330K_0402_1%
1
2
PC268
0.1U_0402_16V7K
1
2
OPTIMUS@ PR737
80.6K_0402_1%
1
2
+3VS
G
Document Number
Rev
B
4019HG
Sheet
58
H
of
61
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------1.
2.
3.
4.
5.
6.
7.
8.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
P51-PWR_+3VALWP/+5VALWP
P53-PWR_ +1.05VS_VCCP/+16VSP
P54-PWR_+VCCSAP/1.8VSP
P57-PWR +CPU_CORE DECOUPLING
P53-PWR_ +1.05VS_VCCP/+16VSP
P49-PWR_BATTERY CONN / OTP
P58-PWR_VGA_CORE
P58-PWR_VGA_CORE
Change PU330 to RT8205L
Change PU400 to RT8237C
Change PU450 to SY8037B
Change HMOS to MDV1525
Change HMOS to MDV1525
Change PD5,PD6 to SCA00001G00
Change PR589 from 348 to 8.06k
Change PR590 from 3.65k to 806
Change PC574 from 680P to 0.033u
Change PR548 from 1.21k to 8.06k
Change PR550 from 10.7k to 806
Add snubber and boost resistor
Add PR22 120k,PR27 100k, PR32 0 Ohm
Remove PC803, PC804 add PC806 47u
Change PC360 to SE000006R80
Change PC702 to SE00000H180
Add PR17 14k, PR33 0 Ohm
Add PR373 0 Ohm
Change source
Change source
Change source
Change source
Change source
ESD team request
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
For 3x3 H-MOS solution
For 120W adapter protect(9012)
For Nvidia suggestion
Change source
Change source
For CPU temperature protect(9012)
For 3/5 V always power on(9012)
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Date:
Rev
B
4019HG
Sheet
59
of
61
5
4
3
2
1
HW PIR (Product Improve Record)
QFKAA LA-8391P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2011/11/11
D
C
B
----------------------------------------------------------------------------------------------------------------------------------Item
Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1)
44
2011/9/27
in order to add one AD channel for PWR VR
change PWR_GPS_DOWN# to EC GPIO43.
protect of GPU GPS
change HDPACT to EC_GPIO50
2)
44
2011/9/27
in order to reduce BOM
change CB50 to SE000000K80
3)
15
2011/9/27
for N13PGL strap pin by NV review
modify VRAM Table
change RV77 to @ due to it is for X76
change RV98 to @ for N13PGL
change RV76 to @ for N13PGL
change RV73 to 45.3k (SD034453280) for N13PGL
change RV89 to 34.8k (SD034348280) for N13PGL
4)
15
2011/9/28
for N13PGL strap pin by NV review
change RV89 to 30k (SD034300280) for N13PGL
5)
15
2011/9/28
for N13PGS strap pin by NV review
change RV73 BOM sstructure to N13PGS@(34.8K) & N13PGL@(45.3K)
change RV54 to @
change RV79 BOM sstructure to N13PGS@(20K) & N13PGL@(10K)
change RV76 to 10K and N13PGS@
change RV98 to GSDIS@
change RV75 to GSOPT@
6)
22
2011/9/29B
by ESD demand
change D84 to SCA00001L00
7)
35
2011/9/29B
by ESD demand
8)
37
2011/9/29B
by ESD demand
9)
05
2011/10/05A
follow HW4 check list
reserve decoupling cap CC66, CC67, CC70 for H_PM_SYNC & H_PECI, BUF_CPU_RST#
11)
28
2011/10/05A
by Customer demand
add LVDS dual channel signal
12)
22
2011/10/05A
by Customer demand
add LVDS dual channel signal and 0ohm: R267 R268 R269 R270 R283 R329 R333 R337 (OPTFHD@)
and R500 R501 R502 R503 R504 R505 R507 R508 (3D@)
13)
26
2011/10/05A
by Customer demand
add RH277 BOM structure : OPTFHD@
14)
47
2011/10/05A
follow HW4 check list
add unused Dual MOS: Q7B,Q6B
15)
15
2011/10/18a
by NV demaend
change RV89 to 10k (SD034100280) for N13PGL
16)
10
2011/10/18a
for PEG reversal
change RC79 from @ to always mount
17)
44
2011/10/18a
discuss with EC
change Function_LED from EC_GPIO4D, PIN86 to EC_GPIO11, PIN25
change HDPLOCK from EC_GPIO11, PIN25 to EC_GPIO4D, PIN86
add GPUPWR_SKIN# on EC_GPIO13, pin27
change PWRMOS_TEMP from EC_GPIO50, PIN89 to EC_GPIO43, PIN76
change HDPACT from EC_GPIO43, PIN76 to EC_GPIO50, PIN89
change RB28 pin1 from PWR_GPS_DOWN# to GPUPWR_SKIN#
reserve SUSACK# and PCH_SUSPWRDN# by SW demand
18)
27
2011/10/18a
by SW ME demand
change PCH_SUSPWRDN_R to PCH_SUSPWRDN#_R
add PCH_SUSPWRDN# to EC and RH132
remove T75
change SUSACK# to SUSACK#_R
add RH133 and SUSACK# to EC
19)
46
2011/11/1
new touch pad add new function
add JTP connector Pin 5 (PM_SMBCLK) , Pin6 (PM_SMBDATA)
20)
36
2011/11/1
TV tuner(BCAS) 16V reserve
add RM15 and RM16 reserve for TV tuner (BCAS)
21)
42
2011/11/1
avoid SM_EN floating
reserve RA43 for SM_EN 100K pull down reserve
22)
42
2011/11/1
for vendor request
exchange location of RA28 and CA42
23)
42
2011/11/1
for vendor request
RA26 pin2 change name from OSC_IN to OSC_OUT
24)
42
2011/11/1
for vendor request, S&M HP need shut down
delete DA1. add RA19 ,QA5 ,RA42 ,
25)
32
2011/11/2
for lot6 0.5W power consumption
delete CH57 ,PJ3 then add PJ5, QH6, CH59, RH228
26)
47
2011/11/2
add R5545, Q5527, R5529, R5534
27)
47
2011/11/3
for NV power sequence
R434 change from 220K to 330K
28)
47
2011/11/3
for NV power sequence
change net name from DGPU_PWR_EN# to VGA_PWROK#
29)
32
2011/11/3
reserve RH228
30)
46
2011/11/3
change D21 power from +5VL to +5VALW
31)
44
2011/11/7
add EC pin 70 for PCH_PWR_EN
32)
29
2011/11/7
for NV sequence
delete RH287 for NV sequence
33)
29
2011/11/7
for NV sequence
RH175 change to always mount
34)
29
2011/11/7
for TV tuner 16VS over current Pin
delete RH174 and RH1
35)
29
2011/11/7
change PCH D44 ball trace name to LNB_OC#
36)
29
2011/11/7
add RH326 for LNB_OC# pull high
37)
42
2011/11/9
for vendor request
exchange CA42 and RA28 location
38)
40
2011/11/9
for vendor request
add RT67 RT68 RT69 RT70 RT72 RT73
39)
36
2011/11/9
for EMI request
reserve CCL10 for EMI request
40)
37
2011/11/9
for EMI request
reserver RL29 CL43 for EMI request
41)
29
2011/11/9
EC common core for WL_OFF#
PCH pin F46 and RH299 chagne net name from WL_OFF# to PCH_GPIO55
42)
44
2011/11/9
change EC pin 29 net name from CPSETIN to WL_OFF#
43)
36
2011/11/9
add R5546 for WL_OFF# pull high to +3V_WLAN
44)
44
2011/11/9
CPSETIN signal change from EC pin 29 to EC pin 74
45)
44
2011/11/9
LNB_OC# change from PCH pin D44 to EC pin 119
add RH327 pull high to +3VS for LNB_OC#
46)
36
2011/11/15
for vendor demand
change YCL1 from SJ10000CU00 to SJ10000EF00, CCL4 and CCL5 from 30pF to 15pF
47)
15
2011/11/15
for NV recommend
change BOM structure of RV54 from @ to N13PGS@
48)
47
2011/11/15c
for NV DG demand
change R460 from 470ohm to 22ohm
49)
36
2011/11/15d
by EMI demand
change BOM structure of CCL10 from @ to GCLK@
50)
37
2011/11/15d
by EMI demand
change BOM structure of RL29, CL43 from @ to GCLK@
D
C
B
A
A
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
60
of
61
5
4
3
2
1
HW PIR (Product Improve Record)
D
----------------------------------------------------------------------------------------------------------------------------------Item
Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1)
27
2011/11/29a
For DVT hang
Add CH23 CH24 CH25 for SW-node noise.
2)
13
2011/11/29a
For ME request
Change location from JLVDS to JLVDS4
3)
47
2011/12/05a
For reduce Rds-on of +VRAM_1.5VS
Add Q44
4)
05
2011/12/07a
For leakage
Change from +3VALW to +3VALW_PCH of UC1
5)
44
2011/12/13a
For design change
Change LNB_EN from PCH to EC and delte RH315, add RB11
6)
24
2011/12/13a
For HDMI leakage
Change Pin 5 of U9 from +5VL to +HDMI_5V_OUT
7)
44
2011/12/13a
For design change RF LED control pin
Change RF LED control pin from PCH to EC.
8)
35
2011/12/15a
For ME request
Change JFP/JPOWER/JFUN from zif to non-zif
9)
40
2011/12/15a
For adjust EXT USB3.0 sequence
Change +3V to +3V_USB control pin from syson to PM_SLP_S4#
10)
41
2011/12/15a
For adjust EXT USB3.0 sequence
Change +3V to +3V_USB control pin from syson to PM_SLP_S4#
11)
22
2011/12/17a
For prevent LVDS burn issue
Add F3 (Poly fuse to prevent burn)
12)
46
2011/12/19a
For ME delete stand-off
Delete H25,H26,H27
13)
46
2011/12/19a
For Wimax flash issue
Change +5VS to +3VS of Wimax LED
14)
46
2011/12/19a
For layout request
Add net name +5VS_FUNC with Function conn power pin
15)
15
2011/12/20a
For NV request
Change RV76 from 10K to 20K
16)
46
2011/12/21a
For power rail change
Change WiMAX LED power rail from +5VS to +5VALW
17)
16
2011/12/22a
For NV request
Change LV6 from bead to 4.3ohm resistor
18)
29
2011/12/22a
For EMI request
Add CH29 for EMI request
D
C
----------------------------------------------------------------------------------------------------------------------------------Item
Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1)
36
2012/01/12a
For GCLK
Add CCL13(0.1u) for +3VALW
2)
15
2012/01/12a
For NV suggestion
Change RV 76 from 20K to 45K(Support GEN3)
3)
36
2012/01/12a
For MSATA pin define.
Add RM30 (MSATA define that Pin22 is reserve, so other function need to add PLT_RST#).
4)
36
2012/01/18a
For GLCK
Change CCL13 from +3VLAW to +3VALW_GCLK
5)
41
2012/01/30a
For TV tuner use PCIE interface
Add RM31~RM35 and QM2
6)
26
2012/01/30a
Change PCIE 6 from USB to TV tuner
7)
26
2012/01/30a
Change CLK_USB30 to CLK_TV and CLKREQ_USB30# to CLKREQ_TV#
8)
11
2012/01/30a
For M1 only
Unmount RC117/RC118/QC7/QC8
9)
46
2012/01/30a
For MP
Unmount SW3
10)
15
2012/01/30a
For NV suggestion
Change RV 73 to 5K
11)
43
2012/01/30a
For EMI request
Add CA51
12)
41
2012/01/30a
For Internal USB30 only
Delete Page 41
C
B
B
A
A
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Date:
5
4
3
2
Rev
B
4019HG
Sheet
1
61
of
61
www.s-manuals.com

Compal LA-8391P - Schematics. www.s

Transcription

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