Paper

Transcription

Paper

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
A 128
128 CMOS Biosensor Array for Extracellular
Recording of Neural Activity
Björn Eversmann, Martin Jenkner, Franz Hofmann, Christian Paulus, Ralf Brederlow, Birgit Holzapfl,
Peter Fromherz, Matthias Merz, Markus Brenner, Matthias Schreiter, Reinhard Gabl, Kurt Plehnert,
Michael Steinhauser, Gerald Eckstein, Doris Schmitt-Landsiedel, and Roland Thewes
Abstract—Sensor arrays are a key tool in the field of neuroscience for noninvasive recording of the activity of biological networks, such as dissociated neurons or neural tissue. A high-density
sensor array complementary metal–oxide–semiconductor chip is
presented with 16 K pixels, a frame rate of 2 kiloframes per second,
and a pitch of 7.8 m 7.8 m for imaging of neural activity. The
related circuit and system issues as well as process aspects are discussed. A mismatch-canceling calibration circuitry with current
mode signal representation is used. Results from first biological experiments are presented, which prove full functionality of the chip.
Index Terms—Bioelectric potentials, biological cells, biological
tissues, biomedical transducers, image sensors, multi-electrode
array (MEA), nervous system.
I. INTRODUCTION
N
EURONS ARE biological cells specialized in transmission and processing of information. The elementary neural
signals are action potentials, which are transient changes of the
voltage drop across the cell membrane with a typical shape. The
related peak-to-peak amplitudes of this transmembrane voltage
approximately amount to 70 mV .
Today’s standard tools used to characterize this parameter are
patch pipettes [1] or microelectrodes [2]. An example setup is
schematically sketched in Fig. 1(a). The patch pipette (or microelectrode) penetrates the cell membrane in order to contact
the intracellular volume of the cell. The cell is situated within
a grounded nutrition electrolyte. These techniques have led to
great achievements in the field of neural cell monitoring, but
they also suffer from a couple of disadvantages. They require
a elaborate mechanical setup, which allows monitoring very
few cells in parallel only. Thus, they are generally not suitable
to fulfill high-throughput requirements. Moreover, long-term
recording is restricted, due to the invasive type of contact, reducing the lifetime of the cell.
Manuscript received May 14, 2003; revised June 5, 2003.
B. Eversmann is with Infineon Technologies AG, Corporate Research,
D-81730 Munich, Germany, and also with the Technical University of Munich,
Munich, Germany (e-mail: [email protected]).
M. Jenkner, F. Hofmann, C. Paulus, R. Brederlow, B. Holzapfl, and R.
Thewes are with Infineon Technologies AG, Corporate Research, D-81730
Munich, Germany.
P. Fromherz and M. Merz are with the Max Planck Institute for Biochemistry,
D-82152 Martinsried, Germany.
M. Brenner, M. Schreiter, R. Gabl, K. Plehnert, M. Steinhauser, and G. Eckstein are with Siemens AG, D-81730 Munich, Germany.
D. Schmitt-Landsiedel is with the Technical University of Munich, D-80290
Munich, Germany.
Digital Object Identifier 10.1109/JSSC.2003.819174
Fig. 1. Schematic presentation of recording techniques used to characterize
neural activity. (a) Invasive patch pipette. (b) Oxide–semiconductor field-effect
transistor (OSFET).
Extracellular, and therefore, noninvasive, recording techniques open a way to circumvent these drawbacks. They are
based on the fact that the action potentials to be considered
correspond to sodium and potassium ion currents through ion
channels in the cell membrane. Consequently, the idea behind
these approaches is to monitor these ion currents instead of the
transmembrane voltage.
For this purpose, the neuron can be cultured in a nutrition
electrolyte upon a planar sensor. A cleft of approximately 50 nm
is formed between cell and sensor surface due to the topology of
the cell membrane. Membrane currents through the ion channels
located above the sensor area flow through the cleft and lead to
a voltage drop due to the resistance of the electrolyte within the
cleft [Fig. 1(b)].
The magnitude of this extracellular signal depends on the
membrane currents and on the cleft resistance. The transmembrane currents depend on type and number of contributing ion
channels, which are a function of the size of the cell and of the
spatial distribution of the ion channels. The cleft resistance is
a function of the contact area, of the thickness of the cleft, and
of the resistance of the electrolyte. In a first-order approximation, the ion channels through the membrane can be modeled
as lumped capacitance and conductance driven by the intracellular voltage with respect to action potential [3]. Membrane
capacitance and cleft resistance result in a high-pass transfer
function which attenuates the low frequency spectrum of the
voltage signal in the cleft. Peak-to-peak values of the action-potential-induced cleft voltage are of order 100 V to 5 mV .
Using an oxide–semiconductor field-effect transistor
(OSFET), depicted in Fig. 1(b), as transducer, a modulation
0018-9200/03$17.00 © 2003 IEEE
EVERSMANN et al.: A 128
128 CMOS BIOSENSOR ARRAY FOR EXTRACELLULAR RECORDING OF NEURAL ACTIVITY
of the cleft potential is translated into a modulation of the
transistor’s drain current. In the literature, this principle has
been successfully demonstrated using OSFETs consisting of
bulk silicon with diffused junctions and channel areas directly
covered by a sensor dielectric [4]–[6].
Recording the activity of neural networks has always been a
central goal in neurobiology and is gaining importance in cellbased pharma screening. However, the tools discussed so far are
suitable for single-cell characterization only. Arrays of sensors
are thus advantageous in all cases where several neurons must
be monitored in parallel.
Linear arrangements with 96 OSFETs with a pitch of 3.6 m
have been suggested in the literature [7] using the same technological approach as in [4] and [5]. However, an extension of this
approach to provide two-dimensional sensor arrays with similar
pitch is impossible, due to the fact that only one layer (diffusion
lines) can be used for interconnect purposes. Consequently, the
realization of an architecture which allows row and column selection is impossible.
A commercially available sensor array approach for noninvasive measurements of neural activity of neural tissue is the
multielectrode array (MEA) [8]–[11]. MEAs typically consist
of less than 100 planar metal electrodes on an insulating glass
m and a pitch
m. In case
substrate with a diameter
of commercially available MEAs [10], [11], measurement circuitry is usually realized by discrete off-chip components. However, from the literature, approaches for low-density arrays with
active on-chip circuity are also known [12]–[14].
Considering the dimensions of neurons, which range from
below 10 m for vertebrates up to 100 m for invertebrates,
the need for high-density arrays is apparent to explore a maximum amount of information from cell-based biological experiments. In particular, such sensor arrays open the way for fast and
statistically significant cell-based pharma screening and neural
network characterization. In order to significantly increase the
number and density of sensors, the integration of active circuitry is mandatory to overcome interconnect restrictions by
multiplexed readout techniques, and to ensure signal integrity
by signal preamplification. In this paper, a CMOS sensor array
with 128 rows and 128 columns and a sensor pitch of 7.8 m is
described [15].
The paper is organized as follows. In Section II, the specification of the sensor array is derived from application-related biological boundary conditions. Process and technology aspects
are briefly discussed in Section III. System and circuit design
are considered in Sections IV and V, respectively. Experimental
results are revealed in Section VI. Finally, in Section VII, the
paper is summarized and future perspectives are projected.
II. SPECIFICATION
The most prominent in vitro applications for high-density
sensor arrays are fire-rate analysis of sparse neuron networks
and imaging of brain slice activity. These two application cases
are schematically sketched in Fig. 2.
In the case of fire-rate analysis [Fig. 2(a)], dissociated cells
cultured upon the sensor surface reestablish neural networks by
the outgrowth of dendrites. For rat neurons (vertebrates) with a
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Fig. 2. Schematic plot describing the most prominent application cases.
(a) Networks of dissociated neurons. (b) Brain slices.
diameter of about 10 m, the resulting extracellular signals in
the cleft have a bandwidth of approximately 10 Hz–1 kHz and an
amplitude of approximately 100 V . Another suitable model
system for such applications is given by snail neurons (invertebrates). Snail cells with diameters of approximately 50 m provide signals of below 3 mV . Bandwidth is 10 Hz–1 kHz. In
fire-rate analysis applications, e.g., for pharma-screening purposes, it is mandatory to acquire statistically significant data.
This is required to operate thousands of sensors in parallel.
Slice imaging requires detecting signals from a dense organotypic layer of cells [Fig. 2(b)]. The high density of cells in the
tissue translates into an increased cleft resistance, as compared
with the first application case. As a result, field potentials up to
5 mV appear between tissue and sensor surface. Bandwidth
requirements are the same as in the case of fire-rate monitoring.
Slice imaging requires monitoring signals within a total sensor
mm .
area
A universal sensor array platform thus requires a frame rate
2 kiloframes per second (kfps), a resolution of the cleft voltage
better than 50 V, a maximum cleft voltage range of 5 mV, a
m in both directions, and a total sensor area
sensor pitch
of at least 1 mm 1 mm.
III. EXTENDED CMOS PROCESS
For our sensor array, we use a CMOS process compatible
adaptation of the OSFET sensor principle from Fig. 1(b). A
schematic cross section of the resulting sensor is shown in
Fig. 3(a). A sensor electrode coated with a biocompatible dielectric layer is connected to the polysilicon gate of a MOSFET
fabricated in a standard CMOS process.
Fig. 3(b) shows the corresponding lumped equivalent circuit
, membrane
diagram consisting of membrane conductance
, and cleft resistance
. Compared to the
capacitance
simple OSFET sensor from Fig. 1(b), the transistor gate signal
and MOSFET
is lowered here, since sensor capacitance
gate oxide capacitance form a voltage divider.
Concerning the properties of the sensor dielectric, there are
biological, process related, and circuit design related requirements. During the cultivation of cells on the sensor surface for
up to several weeks, the dielectric layer is in intimate contact
with the cells and the nutrition electrolyte. Despite the fact that
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Fig. 3. Schematic cross section of the sensor principle used in this paper. (a)
Cross section neuron/sensor. (b) Lumped equivalent circuit diagram.
Fig. 5. SEM photo of sensor cross section.
As sensor dielectric, a 40-nm-thick stack of 10-nm TiO ,
5-nm ZrO , 10-nm TiO , 5-nm ZrO , and 10-nm TiO layers
is sputtered [Fig. 4(b)]. The measured effective relative dielectric constant approximately equals 45. The dielectric layers are
sputtered at a temperature below 400 C to avoid damage of the
metallization layers below. On the adhesion layer of the bond
pads, the dielectric is removed by a reactive ion etch [Fig. 4(c)].
A 400-nm-thick Au layer is vapor deposited on the Pt pad and
structured using a liftoff process [Figs. 4(d) and (e)].
A scanning electron microscope (SEM) photo of a cross section of the complete sensor with dielectric, electrode, and transistor after completion of the process is shown in Fig. 5.
IV. SYSTEM SETUP AND CHIP ARCHITECTURE
Fig. 4. Schematic process flow.
the dielectric must be suitable for cell cultivation, i.e., biocompatible, it must be chemically inert and leakproof to avoid corrosion of the sensor electrode or of the subjacent layers of the
CMOS chip. Moreover, it is obvious that the signal-to-noise
ratio (SNR) of the structure in Fig. 3 improves with increasing
electrode capacitance, so that a high dielectric constant and relatively low thickness of the sensor dielectric are demanded.
The process flow of the extended CMOS process is schematically sketched in Fig. 4 [15], [16]. We start with a two-metallayer n-well epi CMOS process optimized for analog applicam, gate oxide thicktions with minimum gate length
nm, supply voltage
V, LATID-n-MOS and
ness
LDD-pMOS devices, poly–poly capacitors, and different types
of polysilicon resistors. After this standard process (devices, two
metal layers, nitride passivation, and tungsten via) is completed,
the extra sensor process starts. First, the surface is planarized by
a CMP step. An approximately 50-nm-thick Ti/Pt stack is vapor
deposited and structured in a liftoff process. This metal stack is
used to provide the sensor electrodes and the adhesion layer for
the contact pads.
In Fig. 6, system setup and chip architecture are depicted. The
monolithically integrated sensor array consists of 128 128
pixels. The column decoder periodically selects one of the
128 columns of the pixel array. Moreover, control signals are
provided by this decoder, which determine whether the pixels
within the selected column are operated in the readout mode
or in a calibration mode. Calibration of all pixels is performed
before they are operated in readout mode, and periodically
repeated after a number of readout frames (typically, 100).
Circuit design aspects of calibration and readout are discussed
in detail in Section V.
The full frame readout rate is 2 kfps. Each of the 128 rows
is connected to a separate readout amplifier. The outputs of
these amplifiers are connected to the chip’s output drivers or
to dummy loads via 16 8-to-1 multiplexers. The 16 output
drivers force an output current into / converters arranged on
an off-chip printed circuit board (PCB). Finally, the buffered
output voltages of the / converters are converted by 16
analog-to-digital converters (ADCs) with an effective resolution above 8 bit, which are part of a Gage [17] PC-based
measurement system.
The resulting data rate amounts to 32 MS/s. A user interface
program sorts and represents the acquired data. Moreover, this
interface allows controlling timing of the applied control signals, the number of frames per calibration, and the power-up and
Fig. 6.
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Architecture of sensor array with complete system.
power-down routines of the sensor array, by generating the corresponding control patterns. The latter are provided to the chip
via magneto couplers which drive the chip’s logic interface.
Specific areas of interest can also be selected. In this case, the
decreased number of pixels read out translates into an increased
frame rate for the considered area.
Biological processes such as neural activity are strongly influenced by the environment temperature, so that this parameter
must be precisely controlled and regulated. For this purpose, a
resistive temperature sensor is realized on chip, and a regulation
loop controls the chip’s temperature utilizing a peltier element
located underneath the sensor chip.
In order to control the voltage of the nutrition electrolyte,
an off-chip potentiostat circuit is operated in the measurement
system. For test and debugging purposes, test patterns (e.g.,
small AC signals) are applicable to the potentiostat’s input,
which allows modulation of the electrolyte potential. An
electrophysiological setup for measurement and stimulation of
a single cell is added as well for reference purposes, concerning
the biological activity of the selected cell.
V. CIRCUIT DESIGN AND OPERATION
A. Sensor Design
The small signal amplitudes achieved using extracellular
recording techniques, as well as the area-dependent noise
contributions produced by the sensor transistor itself, demand optimizing electrode and transistor dimensions. The
low-frequency noise of the sensor transistor can be reduced
by increasing its area. However, the action-potential-induced
modulation of its gate voltage decreases when its gate area is
enlarged, due to the capacitive voltage divider formed by the
sensor electrode capacitance
and the transistor’s increased
gate capacitance. To compensate for this effect, the sensor capacitance could be enlarged by increasing the electrode area.
However, if the electrode area becomes larger than the contact
area of the cell, the capacitance between the sensor electrode
and the electrolyte beneath the cleft increases. Consequently,
the gate voltage modulation of the sensor transistor drops
again.
As a consequence of these qualitative considerations, the
need for an algorithmic approach to optimize transistor and
electrode area is obvious. For this purpose, signal and noise
are referred to the same node, the gate of the preamplifying
and the SNR is investigated for different combitransistor
nations of transistor and electrode area.
is determined on the
The gate-related signal energy
basis of the known behavior of the intracellular potential
during an action potential. In order to calculate the
, which relates the intracellular potential
transfer function
to the gate voltage of
, the electrical characteristics
of the system consisting of membrane, cleft, electrolyte,
dielectric, and electrode has to be modeled.
We start with the assumption that the neuron is located in
the center above the sensor electrode. Cell and electrode are
assumed to be rotationally symmetric. We chose a cylindrical
coordinate system whose axis coincides with the symmetry
axis of cell and electrode. Moreover, uniform and time-independent distribution of conductivity and capacitance per area
are assumed. In the next step, the radial variation of voltages
and currents in the cleft is modeled. An equivalent circuit
within the cleft
[Fig. 7(a)] related to a radius increment
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Fig. 7.
Illustration. (a) Radial incremental equivalent circuit of neuron, cleft, and electrode. (b) Corresponding matrix description.
Fig. 8.
(a) Schematic overview of signal path, transfer functions, and noise contributions. (b) Gate-referred equivalent schematic.
is derived as a function of the distance of the center, i.e., the
radius . The conductivity of the membrane within the radius
, the product of the
increment is
, and
area of the membrane within the radius increment,
. Same relations hold for memthe conductivity per area,
brane and electrode capacitance within the radius increment,
and
, with
and
being the capacitances of the cell membrane and
electrode per area, respectively. The resistance of the electrolyte
is
in the cleft
, and from
derived from the resistance of the electrolyte,
. The values of conductivity and
the thickness of the cleft
capacitances per area are calculated on the basis of the values
, and
[Fig. 3(b)] given
for the lumped parameters
in [18].
of sections
The cleft is divided in a discrete number
. Applying matrix-based
according to the radius increment
descriptions
for the equivalent circuit of
, a description of
each radius increment
the cleft is calculated as matrix product.
With this model of the cleft and the boundary conditions concerning the grounded electrolyte outside the cleft and the gate
as depicted in Fig. 7(b), the transfer function
capacity of
is approximated so that the gate-related signal energy
of an action potential can be estimated.
To model the gate-related noise, the different noise contributions have to be taken into account, as well as the consequences
of readout architecture and multiplexed readout on noise propagation. Fig. 8(a) depicts the signal and noise contributions, the
transfer functions, the corresponding bandwidths of the individual stages, and the multiplexing units within the signal path.
has already been derived. The noise
The transfer function
to the gate voltage of
is
noise.
contribution
These signals are transformed via the transfer function
Fig. 9.
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Operation modes of pixel circuits. (a) Calibration. (b) Readout.
into transistor drain current within bandwidth
. The tranconsist of
sistor’s drain current noise contributions
thermal and flicker noise. The sum of these signals is connected
to the input of a readout amplifier via a 1-to-128 multiplexer. In
order to guarantee that the signal settles to 8 bits in the available time slot of 50% of (2 kS/s 128 columns) , the bandneeds to be at least 2.8 MHz. Noise contributions
width
, from the output
from the readout amplifier,
and
, are sigdrivers and from the ADCs,
nificantly smaller and can be neglected in the optimization procedure. The sum of signal and noise is amplified by the transfer
, which describes signal propagation from the
function
readout amplifier’s input to the output driver’s input, within a
. The line drivers input current is multiplexed
bandwidth
eight times. The input current of the output driver is amplified by
the output driver, the / converter, and buffer, and the transfer
is
.
function with required bandwidth
Due to the eightfold multiplexing, the settling time is 1/8
. Consequently,
of the settling time of the drain current of
and
needs to be at least
the overall bandwidth of
22.8 MHz. At the ADC input, the weighted sum of signal and
noise is sampled for one pixel with the sampling frequency of
2 kS/s. The crucial point is that the sampling frequency is sigand
.
nificantly smaller than the bandwidths
Therefore, high-frequency noise contributes to the noise in the
signal frequency domain. For the sum of noise energy contributions related to the gate, we obtain
Using these approximations for the gate-related signal and
noise energies, a high SNR is used as optimization goal in a
MathLab-based program. For the chosen parameters, an optimum gate area of 11 m is obtained and an optimum electrode area of 16 m . Due to the layout of the pixels, this translates into a pitch of 7.8 m. Circular sensor electrodes are used
with a diameter of 4.5 m. For comparison, note that typical cell
diameters are between 10 and 50 m.
B. Pixel Circuit
The purpose of the pixel circuit is to preamplify and to buffer
the extracellular signal. To ensure signal integrity within the
whole array, mismatch and settling behavior have to be taken
into account, as well as noise aspects.
The threshold voltage mismatch of the sensor transistors
is by far higher, compared with the signals to be detected.
With a matching constant of 14 mV m for this process
[19] and a gate area of 11 m , a one-sigma value of
mV m
m
mV is obtained. In order
to compensate for such mismatch effects, every pixel within
the array is periodically calibrated so that all pixels provide the
same signal-transmission properties.
The calibration technique used is schematically illustrated in
Fig. 9(a). The pixel in column is selected by closing the related
(controlled by the column decoder). For calibration
switch
is closed, so that the associated sensor transistor
switch
is operated in a diode configuration. A constant current
forces a current through the row line and the selected
source
.
transistor
is opened again and a voltage related to the caliThen,
. The charge
bration current is stored on the gate node of
injected at the gate node of the sensor transistor during the
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Fig. 10. (a) Circuit diagram of complete signal path with details in (b) and (c). (b) Quasi-differential stage in readout amplifier. (c) Output driver and I /V
conversion.
switch-off process is approximately equal for all pixels. Moreover, the effect of the charge injection on the gate voltage
is alleviated due to the large capacitance of the electrode,
so that this effect can be neglected in our discussion. The
procedure is performed for all rows in parallel, columns are
selected subsequently. As result, all sensor transistors within
a row provide the same current when selected for readout
open) independently of their individual device
(i.e., with
parameters.
In the readout mode [Fig. 9(b)], a constant voltage source
is connected in parallel to current source
by closing switch
. Action-potential-induced changes of the drain current of a
and
selected sensor transistor flow through voltage source
are further amplified as symbolized by the current-controlled
in Fig. 9(b).
current source providing the current
This compensation technique has been motivated here by
considering threshold voltage mismatch only. This is reasonable, since for low and medium gate voltages, the total
transistor drain current mismatch is dominated by threshold
voltage mismatch [19]. However, at this point, we like to
mention that the applied compensation technique compensates
for the variations of all sensor transistor parameters which
contribute to its drain current mismatch.
The discussion above also reveals that a current mode readout
technique is applied. This is mandatory to meet the required
pixel bandwidth, since the influence of the parasitic capaciis by far lower in curtances of row signal line and switches
rent mode, as in the case of a signal representation in voltage
mode. The bandwidth is now a function of the input resistance
of , rather than of the properties of the pixel circuit elements.
C. Complete Signal Path
In Fig. 10, all subcircuits of the complete signal path are depicted. The current source
in Fig. 9 is realized by transistor
in the readout amplifier block. This device is used to force
the calibration with respect to bias current through the selected
in calibration with respect to readout mode. The
transistor
current is controlled by voltage , which is applied to all 128
in parallel.
devices
It can be shown that the chosen compensation technique reby
duces the drain current mismatch of the sensor transistors
. Compared to the mismatch
the factor
without calibration, a reduction of more than two decades is
achieved for the technology and bias conditions used. Since the
voltages stored on the gate nodes of the sensor transistors differ
only slightly after calibration, and since the threshold voltage
is negligible,
mismatch of the transistors used as switches
the amount of charge injection is very similar for all sensor tranare opened.
sistors when switches
In the readout mode, the voltage of the row signal line is kept
constant by the (closed) negative feedback loop composed of
and
. There, the desired value
amplifier and devices
of the row-line potential (i.e., ) is applied to the inverting input
of amplifier via an external voltage source.
–
in
A fast pseudodifferential input stage [
is chosen
Fig. 10(b)] with a small low-frequency gain
to achieve stability by sufficient phase margin and the required
settling time of the loop. The corresponding corner frequency of
,
the loop is
is the parasitic capacitance of the drain-diffusion
where
and of the interconnect row line itself.
areas of the switches
Fig. 12.
Fig. 11.
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Schematic measurement setup.
Chip microphotograph.
The difference current of
and
is copied and amplified
by a factor of 100. Transistor
is used to provide a
by
. This
common-mode bias current through the branch
branch is also calibrated before operated in readout mode. In the
is closed so that
is operated in
calibration phase, switch
diode configuration. After opening , a voltage is stored on the
gate node of this transistor, which is operated as a current source
. This procedure is
providing the same current as transistor
similar to the calibration procedure applied to sensor transistor
.
and
is either forced
The output difference current of
(in parallel with the contribuinto the dummy load
tions from six further readout amplifiers) or into the output stage
. The drain current of
drives a pMOS current mirror followed by a cascoded nMOS current mirror, with
–
in Fig. 10(c)].
an overall current gain of 8 [(
An off-chip current source with high output resistance
and low input capacitance provides a common-mode current
of the output current mirror. The
through the branch
difference current is converted into a voltage by the resistor
in the feedback loop of an off-chip discrete operational
amplifier, whose output voltage is buffered again and applied
to the input of the off-chip ADC.
VI. EXPERIMENTAL RESULTS
A microphotograph of the fabricated active sensor chip is
shown in Fig. 11. The total area is 6.5 mm 5.2 mm. After
sawing, the chips are die bonded with a heat-conducting adhesive into a ceramic CPGA package and bonded with aluminum wire. The cultivation chamber is glued with silicone to
the package and the interspace volume with the bond wires is
filled with epoxy resin.
In Fig. 12, the schematic setup of sensor chip with data acquisition system, electrolyte, potentiostat, and electrophysiological
reference setup is illustrated. The potentiostat is used to adjust
the potential of the electrolyte to the value of a programmable
. Low-pass filtering minimized
off-chip reference voltage
Fig. 13. (a) Photograph of measurement setup including micromanipulator
for (1) microelectrode, (2) off-chip electronic components (I /V converters,
buffers, magnetocouplers, temperature control, heat sink), (3) microscope, and
(4) potentiostat. (b) (5) Blow-up with microelectrode, (6) ceramic package,
(7) culture chamber, (8) ZIF socket, and (9) potentiostat contacts.
crosstalk from off-chip noise sources. The value of
is
chosen so that the voltage drop across the sensor dielectric is
low, in order not to avoid electrical stress. The electrolyte can
be AC modulated with a test signal to allow electrical testing of
the sensors of the array.
The electrophysiological setup allows the creation of an intracellular contact for cell stimulation purposes and for intracellular measurements. This option is provided for reference purposes to compare extracellular and intracellular activity.
Photos of the complete setup, the package, and neurons in
culture are presented in Fig. 13.
A. Electrical Testing
For electrical tests of the chip, the electrolyte on top of the
sensor array is sinusoidally modulated with an amplitude of approximately 5 mV at a frequency of 200 Hz. All sensor spots
are recorded with a sampling frequency of 2 kHz. Fig. 14 depicts
output signals of 12 different randomly chosen pixels within a
column. The plot proves full system functionality. Mismatch,
noise, nonlinearity, crosstalk, switching artifacts, and drift are
sufficiently low to meet the biological requirements.
B. Proof-of-Principle With Biological Samples
The extracellular recording capabilities are tested with neurons from a pond snail, lymnaea stagnalis. Before cultivation,
the chips are cleaned, sterilized, and coated with a cell-adhesive
layer of poly-l-lysine. Then, the neurons are extracted from the
animals, placed on the sensor chip, and cultured for one day. The
2314
TABLE I
EXTRACELLULAR RECORDING SENSOR CHARACTERISTICS
Fig. 14. Measured signals of different pixels within a column during test
modulation of the electrolyte with 2 mV
at 200 Hz. The figure shows the
signals obtained at the ADC inputs.
is recorded with the same microelectrode. Bursts of four actions potentials with an amplitude of 60 mV are obtained.
The change of the intracellular potential at the beginning and
the end of the current injection is a measurement artifact due
to the voltage drop, which occurs at the microelectrode’s resisin Fig. 12(b)].
tance [parameter
An area of 32 40 pixels of the sensor array is selected for
readout with a sample rate of 8 kHz. Data of the extracellular
potential recorded from one pixel beyond the neuron is shown
in Fig. 16. As expected, due to the high-pass transfer function
of the cleft, the extracellular signal represents the derivate of
the intracellular signal. More detailed experimental results will
be published in forthcoming papers with a more biology-related
focus.
VII. CONCLUSION AND FUTURE PERSPECTIVE
Fig. 15.
Snail neuron on sensor chip in culture.
A biosensor array chip based on an extended 5-V 0.5- m
CMOS process has been presented which allows high-resolution imaging of extracellular signals from neural cells or tissue.
The chip provides 128 128 capacitive sensors with a pitch of
7.8 m 7.8 m on an area of 1 mm 1 mm. Signals to be
detected are of order 100 V to 5 mV peak to peak; full-frame
sample rate per pixel is 2 kS/s; maximum internal bandwidth
equals 32 MHz; output data rate is 32 MS/s. The detection circuitry is based on a sensor-MOSFET mismatch-compensated
current-mode technique. Data of the first biological measurements reveal successful operation of the chip. A summary of
the sensor’s significant properties is given in Table I.
In the next generation, the functionality of the sensor array
will be increased. A bidirectional sensor/actuator interface,
which allows recording as well as capacitively stimulating
neural activity, will be realized and on-chip analog-to-digital
conversion will be implemented.
REFERENCES
Fig. 16. Measured data from a snail neuron. The neuron is stimulated and
monitored for reference purposes with a microelectrode. Stimulation current
I
, intracellular potential V
, and extracellular potential V
recorded with sensor array.
biocompatibility of the sensor surface is proven by the growth of
neurites and of the cell cultured upon the sensor chip, as shown
in Fig. 15.
Fig. 16 shows the result of a neuron tapped by a microelectrode and stimulated by the injection of a constant current of
0.1 nA forced into the cell for 500 ms. The intracellular voltage
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2
2315
Franz Hofmann joined the Corporate Research
Laboratories of Siemens AG in Munich in 1986. He
worked on degradation effects in MOS transistors
focusing on the spatial resolution of defects at the
silicon/oxide interface using advanced measurement
methods. Since 1989, he was involved in R&D
projects concerning the on optimization of the
trench capacitance of the 16 Mbit and the 64 Mbit
DRAM technologies. Since 1993, he worked on
advanced semiconductor devices like strained SiGe
MOSFET, and novel devices and memory cells
using vertical transistors. Since 1999, he has been with Infineon Technologies
AG, Corporate Research, where he worked on surrounding gate transistors for
DRAM generations with feature sizes below 100 nm. Since 2001, he has been
active in the field of extended CMOS process development for novel biosensor
purposes. He holds more than 50 patents.
Christian Paulus received the diploma degree in
physics at the University of Bayreuth, Bayreuth,
Germany, in 1997. He is currently working toward
the Ph.D. degree at the University of Magdeburg.
Since 1997, he has been with Siemens AG, Corporate Technology, Munich, Germany, and Infineon
Technologies AG, Corporate Research, Munich. He
is working in the field of CMOS-based biosensors
and advanced analog circuits.
Björn Eversmann (M’03) was born in Kiel in 1972.
He received the Dipl. Ing. degree in electrical engineering from the Technical University of Munich,
Germany, in 2000. Since then, he worked towards
the Ph.D. degree in a cooperative project between
the Max-Planck-Institute Institute for Biochemistry,
Martinsried, Germany, the Technical University
of Munich, and Corporate Research of Infineon
Technologies AG, Munich, on the development of
CMOS-based bio-sensor arrays to monitor the electrical signals of nerve cells and neural tissue. Since
2003, he has been with the Research Laboratory of Infineon Technologies.
Ralf Brederlow received the Dipl.-Phys. degree
from the Technical University of Munich, Munich,
Germany, in 1996 and the Dr.-Ing. degree from the
Technical University of Berlin, Berlin, Germany, in
1999.
From 1995 until 1996, he was with the Walter
Schottky Institute, Garching, Germany working
in the field of Si/SiGe intersubband detectors and
Si/SiGe-MBE. In 1996, he joined a cooperative
program between Siemens Corporate Research,
Munich, and the Technical Universities of Munich
and Berlin, where he worked on the characterization, modeling, and reliability
of analog circuits. Since 1999, he has been with the Corporate Research Department of Infineon Technologies, Munich. There, he is a Senior Staff Engineer
for technology-related circuit design. His current work includes noise-sensitive
analog circuitry, polymer electronics, and sensors for biochemical applications.
He has authored or coauthored some 20 technical publications. He is a member
of the program committee of the International Electron Device Meeting
(IEDM) and chairs the European Design Technical Working Group of the
International Technology Roadmap for Semiconductors (ITRS).
Dr. Brederlow is a member of the Association of German Physicists (DPG)
and the German Association of Electrical Engineers (VDE).
Martin Jenkner was born in Aalen, Germany, in
1968. He received the Dipl.-Phys. degree in physics
from the University of Ulm, Ulm, Germany, in 1995,
and the Ph.D. degree from the Technical University
of Munich, Munich, Germany in 1999.
From 1995 to 2000, he worked in the Department
of Membrane and Neurophysics, Max Planck
Institute for Biochemistry, Martinsried/Munich,
Germany, on interfacing of neural cells with active
semiconductor devices. Since 2001, he has been with
Infineon Technologies AG, Munich, Germany, where
he currently focuses on the development and applications of CMOS-based
chips for recording and stimulation of neural tissue.
Birgit Holzapfl graduated from the Engineering
School of Siemens AG, Munich, Germany.
In 1983, she joined the Siemens Research Laboratory. From 1983 to 1985 she worked on the development of surface wave filters, from 1986 to 1998 on research projects concerning GaAs hetereostructure devices and on the evaluation of the matching behavior
of Silicon devices, respectively. Since 1999, she has
been with Corporate Research at Infineon, where she
is involved in the design of CMOS-based biosensors.
2316
Peter Fromherz received the Ph.D. degree in physical chemistry in 1969 from the University Marburg,
Marburg, Germany.
He was a Postdoctoral Fellow at the Max Planck
Institute for Biophysical Chemistry at Goettingen,
Germany. He became a full Professor for Experimental Physics at the University of Ulm, Ulm,
Germany, in 1981. In 1994, he was elected as a
Scientific Member of the Max Planck Society and
joined the Max Planck Institute for Biochemistry
in Martinsried/Munich. Currently, he is Director at
the Max Planck Institute for Biochemistry and Professor for Biophysics at the
Technical University Munich, Munich, Germany.
Dr. Fromherz is a member of the Academy of Sciences of Berlin and Heidelberg, Germany.
Matthias Merz received the degree in physics
(Diplom) from the University of Ulm, Ulm, Germany in 1999. He is currently working toward
the Ph.D. degree at the Max Planck Institute for
Biochemistry, Martinsried, Germany, where he
studies the growth of topologically defined neuronal
networks that are controlled by silicon chips.
Markus Brenner received the Master of Physics degree from the University of Ulm, Ulm, Germany, in
1996 and the Ph.D. degree from the Technical University of Munich, Munich, Germany, in 2001, both
for work done at the Membrane and Neurophysics
department of the Max Planck Institute for Biochemistry, Martinsried, on interfacing neurons with industrially made neurochip-arrays of 2048 sensors.
He is currently working as an Embedded Software
Architect for Siemens Corporate Technology,
Munich.
Kurt Plehnert received the Dipl.Ing. degree in mechanical and production engineering from the University of Dortmund, Dortmund, Germany, in 1972.
Since then, he has been with Siemens Corporate
Technology, Munich, Germany. He works in the
field of process development with emphasis on
photo lithography and thin film technology.
Michael Steinhauser received the Dipl.-Chem. degree and the Dr.rer.nat. degree from the Ludwig Maximilian University of Munich, Munich, Germany, in
1980 and 1987, respectively.
He joined Siemens, Munich, in October 1986,
where he is working on the development of thin
film modules and sensors. Currently, he is with
Siemens Corporate Technology, Design to Prototype
Department, where he is engaged in the development
of plasmaetch, wetetch, and electroplating processes.
Gerald Eckstein received the diploma degree
in solid state chemistry from the University of
Siegen, Siegen, Germany, in 1996, and the Ph.D.
degree in materials science from the University of
Erlangen-Nuremberg, Erlangen, Germany, in 2001.
He joined the Corporate Technology Department
of Siemens AG, Munich, Germany, in 2001, where
he has been involved in back-end processes and packaging technologies of biosensors.
Matthias Schreiter received the degree in electrical
engineering from Dresden University of Technology,
Dresden, Germany, in 1996.
He joined the Corporate Research Department
of Siemens, Munich, Germany, in 1996, where he
worked on material and process development of
functional thin films for integrated piezoelectric and
pyroelectric devices.
Reinhard Gabl received the M.S. and Ph.D. degrees
in physics from the University of Innsbruck, Innsbruck, Austria, in 1995 and 1999, respectively.
From 1999 to 2001, he was with Infineon
Technologies AG, Munich, Germany, working on
simulations, modeling, design, and technology
development of various silicon devices, including
RF-PIN, varactor and Schottky diodes, MOS transistors, and high-power RF-transistors. Since 1991, he
has been with the Corporate Technology Department
of Siemens AG, Munich, leading a project team
specializing in functional thin films on silicon. His current interests cover the
combination of silicon devices, particularly MEMS with new materials, as well
as the research and development of novel MEMS sensors and sensor arrays for
utilization in gas and biodetection.
Doris Schmitt-Landsiedel received the Dipl.Ing.
degree in electrical engineering from the Technical
University of Karlsruhe, Karlsruhe, Germany, the
diploma in physics from the University of Freiburg,
Freiburg, Germany, and the Dr.rer.nat. degree
from the Technical University of Munich, Munich,
Germany.
Following some research projects on semiconductor lasers and nonlinear optics, she joined the
Corporate Research and Development Department
of Siemens AG, Munich, in 1981. There she worked
on scaling problems in MOS devices and on the design of high-speed logic
and SRAM circuits. From 1989, she was Section Manager of a group of
projects in future generation memory design, analog and digital CMOS and
BICMOS circuits, and design-based yield analysis. Since 1996, she has been a
Professor of electrical engineering and Director of the Institute for Technical
Electronics at the Technical University of Munich. Her research interests are
in mixed signal and low-power circuits design, failure analysis and design for
manufacturability, and sensors on silicon.
Roland Thewes was born in Marl, Germany, in 1962.
He received the Dipl.-Ing. degree and the Dr.-Ing. degree in electrical engineering from the University of
Dortmund, Dortmund, Germany, in 1990 and 1995,
respectively.
From 1990 to 1995, he worked in a cooperative
program between the Siemens Research Laboratories
in Munich, Germany, and the University of Dortmund in the field of hot-carrier degradation in analog
CMOS circuits. Since 1994, he has been with the
Research Laboratories of Siemens AG and Infineon
Technologies, where he was active in the design of nonvolatile memories and in
the field of reliability and yield of analog CMOS circuits. From 1997 to 1999,
he managed projects in the fields of design for manufacturability, reliability,
analog device performance, and analog circuit design. Since 2000, he is
responsible for the Laboratory on Few Electron Circuits of Corporate Research
of Infineon Technologies. His current interests include electronic biosensors
on CMOS, device physics-related circuit design, and advanced analog CMOS
circuit design. He has authored or coauthored some 80 publications.
Dr. Thewes is a member of the German Association of Electrical Engineers
(VDE). He served as a member of the technical program committees of
the International Electron Device Meeting (IEDM) and of the European
Symposium on Reliability of Electron Devices, Failure Physics and Analysis
(ESREF). He is a member of the technical program committees of the IEEE
International Solid-State Circuits Conference (ISSCC), of the International
Reliability Physics Symposium (IRPS), and of the European Solid State Device
Research Conference (ESSDERC). In February 2003, he received the ISSCC
Jack Raper Outstanding Technology Directions Paper Award for his work on
fully electronic DNA sensor chips presented at the ISSCC 2002.
2317

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