Lecture Notes Session 23

Transcription

EE247
Lecture 23
• Oversampled ADCs
– 1-Bit quantization
• Quantization error spectrum
• SQNR analysis
• Limit cycle oscillations
– 2nd order Σ∆ modulator
• Dynamic range
• Practical implementation
– Effect of various nonidealities on the Σ∆ performance
EECS 247 Lecture 23: Oversampling Data Converters
© 2004 H. K. Page 1
Oversampled ADCs
Last Lecture
•
•
•
Why Oversampling?
– Allows trading speed for resolution
– Relaxed transition band requirements for analog antialiasing filters
– Reduced baseband quantization noise power
– Utilizes low cost, low power digital filtering
– Issue of limit cycle oscillation (spurious inband tones)
By simply increasing oversampling ratio: 2X increase in
sampling ratio à 0.5-bit increase in resolution
To achieve greater improvement in resolution:
– Embed quantizer in a feedback loop
à Predictive (delta modulation)
à Noise shaping (sigma delta modulation)
© 2004 H. K. Page 2
Oversampling A/D Conversion
Signal
BW=fs/2M
1-bit
@ fs
n-bit
@ fs/M
• Analog front-end à oversampled noise-shaping modulator
•Converts original signal to a 1-bit digital output at the high rate of
(2MX fsignal)
• Digital back-end à digital filter
•Removes out-of-band quantization noise
•Provides anti-aliasing to allow re-sampling @ lower sampling rate
© 2004 H. K. Page 3
Oversampled ADC
Predictive Coding
+
vIN
ADC
_
dOUT
Predictor
•
•
•
•
•
Quantize the difference signal rather than the signal itself
Smaller input to ADC à Buy dynamic range
Only works if combined with oversampling
1-Bit digital output
Digital filter computes “average” àn-Bit output
© 2004 H. K. Page 4
Oversampled ADC
f =Mf
s1
N
Signal
“wide”
transition
Freq
B
Analog
AA-Filter
f = Mf
s
N
E.g.
Pulse-Count
Modulator
Sampler
Modulator
Decimator
“narrow”
transition
Digital
AA-Filter
1-Bit Digital
f = f +δ
s2 N
DSP
N-Bit
Digital
Decimator:
•
•
•
•
•
Digital (low-pass) filter
Removes quantization error for f > B
Provides most anti-alias filtering
Narrow transition band, high-order
1-Bit input, N-Bit output (essentially computes “average”)
© 2004 H. K. Page 5
Modulator
• Objectives:
– Convert analog input to 1-Bit pulse density stream
– Move quantization error to high frequencies f >>B
– Operates at high frequency fs >> fN
• M = 8 … 256 (typical)….1024
• Better be “simple”
à Σ∆ = ∆Σ Modulator
© 2004 H. K. Page 6
Sigma- Delta Modulators
Analog 1-Bit Σ∆ modulators convert a continuous time
analog input vIN into a 1-Bit sequence dOUT
fs
+
vIN
H(z)
dOUT
_
DAC
1b Quantizer (a comparator)
Loop filter
© 2004 H. K. Page 7
Sigma-Delta Modulators
• The loop filter H can be either a switched-capacitor or continuous time
• Switched-capacitor filters are “easier” to implement and scale with the
clock rate
• Continuous time filters provide anti-aliasing protection
• Can be realized with passive LC’s at very high frequencies
fs
vIN
+
H(z)
_
dOUT
DAC
© 2004 H. K. Page 8
1st Order Σ∆ Modulator
In a 1st order modulator, simplest loop filter à an integrator
H(z) =
+
vIN
z-1
1 – z-1
∫
_
dOUT
DAC
© 2004 H. K. Page 9
Switched-capacitor implementation
φ1
φ2
φ2
-
Vi
dOUT
1,0
+
+∆/2
-∆/2
© 2004 H. K. Page 10
1st Order ∆Σ Modulator
+
vIN
-∆/2≤vIN≤+∆/2
_
∫
dOUT
-∆/2 or +∆/2
•
DAC
Properties of the first-order modulator:
– Analog input range is equal to the DAC reference
– The average value of dOUT must equal the average value of vIN
– +1’s (or –1’s) density in dOUT is an inherently monotonic function of vIN
à linearity is not dependent on component matching
– Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error
but loose this inherent monotonicity
© 2004 H. K. Page 11
Tally of
quantization error
Analog input
-∆/2≤Vin≤+∆/2
1-Bit
quantizer
1
2
3
X
Q
Y
z-1
1-z-1
Sine Wave
Integrator
Comparator
Instantaneous
quantization error
1-Bit digital
output stream,
-1, +1
Implicit 1-Bit DAC
+∆/2, -∆/2
(∆ = 2)
© 2004 H. K. Page 12
1st Order Modulator Signals
1st Order Sigma-Delta
X
Q
Y
1.5
X analog input
Q tally of q-error
Y digital/DAC output
Amplitude
1
0.5
Mean of Y approximates X
0
-0.5
T = 1/fs = 1/ (M fN)
-1
-1.5
0
10
20
30
40
50
60
Time [ t/T ]
© 2004 H. K. Page 13
Σ∆ Modulator Characteristics
• Quantization noise and thermal noise (KT/C)
distributed over –fs/2 to +fs/2
à Total noise reduced by 1/M
• Very high SQNR achievable (> 20 Bits!)
• Inherently linear for 1-Bit DAC
• Quantization error independent of component
matching
• Limited to moderate to low speed
© 2004 H. K. Page 14
Output Spectrum
First order sigma-delta, A=0.79, fx=0.0628319, offset=0.020944, N=1024, K=30
30
• Definitely not white!
Input
20
• Skewed towards
higher frequencies
Amplitude [ dBWN ]
10
• Tones
0
-10
-20
• dBWN (dB White
Noise) scale sets
the 0dB line at the
noise per bin of a
random -1, +1
sequence
-30
-40
-50
0
0.1
0.2
0.3
Frequency [ f/f
s ]
0.4
0.5
sigma_delta_L1_sin.m
© 2004 H. K. Page 15
Quantization Noise Analysis
Integrator
x(kT)
Σ
H( z ) =
z −1
1 + z −1
Quantization
Error e(kT)
Σ
y(kT)
Quantizer
Model
• Sigma-Delta modulators are nonlinear systems with memory
à very difficult to analyze directly
• Representing the quantizer as an additive noise source
linearizes the system
© 2004 H. K. Page 16
Signal Transfer Function
z −1
H( z ) =
x(kT)
−1
1+ z
ω
H ( jω ) = 0
jω
H Sig ( jω ) =
1
1+ s
Integrator
H(z)
-
y(kT)
Magnitude
Signal transfer function
à low pass function:
Σ
ω0
Y ( z)
H ( z)
H Sig ( z ) =
=
= z −1
X ( z) 1 + H ( z)
⇒
f0
Delay
Frequency
© 2004 H. K. Page 17
Noise Transfer Function
Qualitative Analysis
vn2
vi
Σ
vi
ω0
jω
-
vn2 ×  f 
 f0 
Σ
-
2
veq
= vn2 ×  f 
 f0 
vi
Σ
-
vo
2
veq
2
veq
= vn2 ×  f 
 f0 
2
ω0
jω
vo
f0
2
ω0
jω
Frequency
vo
© 2004 H. K. Page 18
STF and NTF
Quantization
Error e(kT)
Integrator
x(kT)
H( z ) =
Σ
z −1
1 + z −1
Σ
y(kT)
Quantizer
Model
Signal transfer function:
Y (z)
H ( z)
STF =
=
= z −1
X ( z) 1 + H ( z)
⇒
Delay
Noise transfer function:
NTF =
Y ( z)
1
=
= 1 − z −1
E ( z) 1 + H ( z)
⇒
Differentiator
© 2004 H. K. Page 19
Noise Transfer Function
NTF =
1
Y ( z)
=
= 1 − z −1
E ( z ) 1 + H ( z)
 e jωT / 2 − e − jωT / 2 
NTF ( jω ) = (1 − e − jωT )=2e − jωT / 2 

2


= 2e − jωT / 2 j sin ( ωT / 2 )
= 2e − jωT / 2 × e − jπ / 2 sin (ωT / 2 ) 
− j ωT −π ) / 2
=  2sin (ωT / 2 )  e (
where
T = 1/ f s
Thus:
NTF ( f ) =2 sin ( ωT / 2 ) =2 sin (π f / f s )
2
N y ( f ) = NTF ( f ) N e ( f )
© 2004 H. K. Page 20
First Order Σ∆ Modulator
Noise Transfer Characteristics
2
N y ( f ) = NTF ( f ) N e ( f )
= 4 sin (π f / f s )
2
© 2004 H. K. Page 21
First Order Σ∆ Modulator
Simulated Noise Transfer Characteristic
Sin input, A=0.79, fx=0.0628319, offset=0.020944, N=1024, K=30
30
Amplitude [ dBWN ]
20
output spectrum
NTF
Signal
10
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
Frequency [f/fs]
© 2004 H. K. Page 22
Quantizer Error
•
For quantizers with many bits
e2 (kT ) =
∆2
12
•
Let’s use the same expression for the 1-Bit case
•
Only simulation can tell if the result is useful
Experience:
Often sufficiently accurate to be useful, with enough
exceptions to be very careful
© 2004 H. K. Page 23
In-Band Quantization Noise
z −1
H (z) =
1 − z −1
NTF ( z ) = 1 − z −1
NTF ( f ) = 4 sin (π f / f s )
2
B
SY =
2
for M >> 1
∫ SQ ( f ) NTF ( z ) z =e
2
2 π jfT
df
−B
fs
≅
2M
∫
− fs
≈
2M
1 ∆2
2
( 2sin π fT ) df
f s 12
π 1 ∆2
3 M 3 12
2
© 2004 H. K. Page 24
Dynamic Range
 SX 
 peak signal power 
DR = 10log 

 = 10log 
peak
noise
power


 SY 
1∆
SX =  
2 2 
2
sinusoidal input, STF = 1
π 2 1 ∆2
3 M 3 12
SX
9
=
M3
SY 2π 2
SY =
M
DR
16
32
1024
33 dB
42 dB
87 dB
 9

 9 
DR = 10log  2 M 3  = 10log  2  + 30log M
2
π


 2π 
DR = −3.4dB + +30log M
2X increase in Mè9dB (1.5-bit) increase in DR
© 2004 H. K. Page 25
Oversampling and Noise Shaping
•
Σ∆ modulators have interesting characteristics
– Unity gain for input signal VIN
– Large attenuation of quantization noise injected at quatizer input
– Performance significantly better than 1-Bit noise performance possible
for frequencies << fs
•
Oversampling (M = fs/fN > 1) improves SQNR considerably
– 1st-Order Σ∆: DR increases 9dB for each doubling of M
– SQNR independent of circuit complexity and accuracy
•
Analysis assumes that the quantizer noise is “white”
– Not true in practice, especially for low-order modulators
– Practical modulators suffer from other noise sources also
(e.g. thermal noise)
© 2004 H. K. Page 26
DC Input
• DC input A = 1/11
First order sigma-delta, DC input, offset=0.0909091, N=1024, K=30
30
Amplitude [ dBWN ]
20
• Doesn’t look like spectrum
of DC at all
10
0
• Tones frequency shape
the same as quantization
noise
à more prominent at
higher frequencies
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
à Quantization “noise”
is periodic
0.5
Frequency [ f/fs]
© 2004 H. K. Page 27
Limit Cycle
DC input 1/11 à
Periodic sequence:
First order sigma-delta, DC input
0.6
Output
0.4
1
+1
2
+1
3
-1
4
+1
0.2
5
-1
0
6
+1
7
-1
8
+1
9
-1
10
+1
11
-1
-0.2
-0.4
0
10
20
30
Time [t/T]
40
50
© 2004 H. K. Page 28
Limit Cycle
In-band spurious tone
with f ~ DC input
• Problem: quantization noise is periodic
•Solution:
ØDither: randomizes quantization noise
- thermal noise à dither
ØSecond order loop
© 2004 H. K. Page 29
(
)
Y ( z ) = z −1 X ( z ) + 1 − z −1 E ( z )
© 2004 H. K. Page 30
2nd Order Σ∆ Modulator
•Two integrators
•1st integrator non-delaying
•Feedback from output to both integrators
•Tones less prominent compared to 1st order
© 2004 H. K. Page 31
Yn = X n −1 + ( En − 2 En −1 + En −2 )
(
Y ( z ) = z −1 X ( z ) + 1 − z −1
)
2
E( z)
© 2004 H. K. Page 32
In-Band Quantization Noise
z −1
1 − z −1
G =1
H (z) =
(
NTF ( z ) = 1 − z −1
NTF ( f
)
2
)
2
=
= 2 4 sin (π f / f s )
B
SY =
4
for M >> 1
∫ SQ ( f ) NTF ( z ) z =e
2
2 π jfT
df
−B
fs
≅
2M
∫
− fs
2M
1 ∆2
( 2sin π fT )4 df
f s 12
π 4 1 ∆2
≈
5 M 5 12
© 2004 H. K. Page 33
Quantization Noise
© 2004 H. K. Page 34
Dynamic Range
 SX 
 peak signal power 
DR = 10log 

 = 10log 
peak
noise
power


 SY 
1∆
SX =  
2 2 
2
π 4 1 ∆2
5 M 5 12
SX
15
=
M5
SY 2π 4
SY =
M
DR
16
32
1024
49 dB
64 dB
139 dB
 15

 15 
DR = 10log  4 M 5  = 10log  4  + 50log M
2
π


 2π 
DR = −11.1dB + +50log M
2X increase in Mè15dB (2.5-bit) increase in DR
© 2004 H. K. Page 35
Example
•Digital audio application
•Signal bandwidth 20kHz
•Resolution 16-bit
16 − bit → 98dB Dynamic Range
DR = −11.1dB + +50log M
M min = 153
Mè256 to allow some margin
à Sampling rate (2x20kHz + 5kHz)M = 12MHz
© 2004 H. K. Page 36
Higher Order Σ∆ Modulator
Dynamic Range
(
Y ( z ) = z −1 X ( z ) + 1 − z −1
1∆
SX =  
2 2 
)
L
E( z)
,
L → Σ∆ order
2
1 ∆2
π 2L
2 L +1
2L + 1 M
12
S X 3 ( 2 L + 1) 2 L +1
M
=
2π 2 L
SY
SY =
 3 ( 2 L + 1) 2 L +1 
DR = 10log 
M

2L
 2π

 3 ( 2 L + 1) 
DR = 10log 
+ 2 L + 1) × 10 × log M
2L  (
 2π

2X increase in Mè(6L+3)dB or (L+0.5)-bit increase in DR
© 2004 H. K. Page 37
Σ∆ Modulator Dynamic Range
As a Function of Modulator Order
• Stability issues for L>2
© 2004 H. K. Page 38
Tones in 1st Order & 2nd Order Σ∆ Modulator
•Higher oversampling
ratio à lower tones
6dB
•2nd order much
lower tones
compared to 1st
•2X increase in M
decreases the tones
by 6dB for 1st order
loop and 12dB for 2nd
order loop
12dB
Ref:
B. P. Brandt, D. E. Wingard, and B. A. Wooley, "Second-order sigma-delta modulation for digital-audio signal
acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.
R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator with dc input,” IEEE
Trans. Commun., vol. 37, pp. 588–599, June 1989.
© 2004 H. K. Page 39
Switched-Capacitor Implementation
© 2004 H. K. Page 40
Switched-Capacitor Implementation 2nd Order Σ∆
Phase 1
•Sample inputs
•Compare output of 2nd integrator
•At the end of phase1 S3 opens prior to S1
© 2004 H. K. Page 41
Phase 2
•Enable feedback
•Integrate
•Reset comparator
•At the end of phase2 S4 opens before S2
© 2004 H. K. Page 42
Practical Design Considerations
for Σ∆ Implementation
•Internal nodes scaling & clipping
•Finite opamp gain & linearity
•Capacitor ratio errors
•KT/C noise
•Opamp noise
•Power dissipation considerations
© 2004 H. K. Page 43
Nodes Scaled for Maximum Dynamic Range
•Modification (gain of ½ in front of integrators) reduce & optimize
required signal range at the integrator outputs ~ 1.7x input full-scale
(∆)
Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State
Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.
© 2004 H. K. Page 44
Switched-Capacitor Implementation
C2=2C1
© 2004 H. K. Page 45
2nd Order Σ∆
Effect of Integrator Maximum Signal Handling Capability on SNR
•Effect of 1st Integrator maximum signal handling capability on converter SNR
© 2004 H. K. Page 46
2nd Order Σ∆
Effect of Integrator Maximum Signal Handling Capability on SNR
•Effect of 2nd Integrator maximum signal handling capability on SNR
© 2004 H. K. Page 47
2nd Order Σ∆
Effect of Integrator Finite DC Gain
φ1
Cs
Vi
CI
φ2
H ( z )ideal =
-
a
+
Vo
H ( z ) Finit DC Gain
Cs
z −1
×
CI 1 − z −1



 −1
a
z

Cs 
1+ a +

Cs
CI 
=
× 
CI


 1 + a  −1
1− 
z
Cs 
1+ a +

CI 

© 2004 H. K. Page 48
2nd Order Σ∆
Max signal level
a
f0 /a
•Low integrator DC gain à degrades noise performance
•If a>M (oversampling ratio) à Insignificant degradation in SNR
•Normally DC gain designed to be >> M in order to suppress nonlinearities
© 2004 H. K. Page 49
2nd Order Σ∆
•Simulation results
•H0=a à finite DC gain
• a> M à no degradation in SNR
© 2004 H. K. Page 50
2nd Order Σ∆
Effect of Integrator Overall Integrator Gain Inaccuracy
• Gain of ½ in front of integrators is a function of C1/C2 of the
integrator
•The effect of C1/C2 inaccuracy inspected by simulation
© 2004 H. K. Page 51
2nd Order Σ∆
Effect of Integrator Overall Gain Inaccuracy
• Simulation show gain can vary by 20% w/o loss in performance
à Confirms insensitivity of Σ∆ to component variations
•Note that for gain >0.65 system becomes unstable & SNR drops rapidly
© 2004 H. K. Page 52
2nd Order Σ∆
Effect of Integrator Nonlinearities
© 2004 H. K. Page 53
2nd Order Σ∆
• Simulation for single-ended topology
•Even order nonlinearities can be significantly attenuated by using differential
circuit topologies
© 2004 H. K. Page 54
2nd Order Σ∆
• Simulation for single-ended topology
•Odd order nonlinearities (3rd in this case)
© 2004 H. K. Page 55
2nd Order Σ∆
Effect of KT/C noise
KT
Cs
kT
1
kT
2
v n/ f =2
×
=4
Cs fs / 2
Cs × fs
Total in-band noise:
v 2n = 2
φ1
Cs
Vi
CI
φ2
-
a
+
Vo
kT
× f0
Cs × fs
2kT
=
Cs × M
v 2n input = 4
•For the example of digital audio with 16-bit (100dB) & M=256
à Cs=1pF à 6µVrms noise
àIf FS=4Vp-p-d then noise is -107dB à almost no degradation in overall SNR
àCs=1pF, CI=2pF à small cap area compared to Nyquist ADC caps
àSince thermal noise provides some level of dithering à better not choose
much larger capacitors!
© 2004 H. K. Page 56
2nd Order Σ∆
Effect of Finite Opamp Bandwidth
φ1
Vo
CI
φ2
settling
error
Cs
Vi+
Vi-
+
Vo
Unity-gain-freq.
Input/Output z-transform
= fu =1/τ
φ2
time
T=1/fs
AssumptionOpamp à does not slew
Opamp has only one pole à exponential settling
© 2004 H. K. Page 57
2nd Order Σ∆
Effect of Finite Opamp Bandwidth
à Σ∆ does not require high opamp bandwidth fu ~ 2fs adequate
© 2004 H. K. Page 58
2nd Order Σ∆
Effect of Slew Limited Settling
φ1
Clock
φ2
Vo-ideal
Vo-real
Slewing
Slewing
© 2004 H. K. Page 59
2nd Order Σ∆
Effect of Slew Limited Settling
AssumptionOpamp settling à slew limited
àMinimum slew rate of 1.2 (∆ x fs) required
àLow slew rate degrade SNR rapidly
© 2004 H. K. Page 60
2nd Order Σ∆
Comparator Hysteresis
Assumption1-bit A/D à Comparator has hysteresis
Comparator offset similar effect
© 2004 H. K. Page 61
2nd Order Σ∆
Comparator Hysteresis
à Comparator hysteresis < ∆/40 does not affect SNR
à E.g. ∆=1V, comparator offset up to 25mV tolerable
© 2004 H. K. Page 62

Lecture Notes Session 23

Transcription

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