Gen3 Multi-lead Probe with SRIS Support User

Gen3 Midbus Probe with SRIS
Support
Quick Start Guide
Before Starting
Use this document for quick installation and setup. If you
experience problems or need more information, see the product
manuals available at the Teledyne LeCroy web site or in the
documents folder in the PCIe Protocol Suite installation DVD.
1
Introduction
Teledyne LeCroy's PCIe® 3.0 (Gen3) Midbus probe with SRIS support provides quick and easy probing through a simple
probe footprint designed into the PCB.
Midbus probes are used by system designers to probe serial data buses that run between chips on a single circuit board or
simply as a convenient means to access bus signals with a probe connector. The probe is easily attached to an anchor
connector mounted on top of a Midbus footprint that is laid out on the target test system board.
The Teledyne LeCroy Midbus probe uses a full-width retention connector that supports bidirectional PCIe x8 link or 16
unidirectional lanes at data rates up to 8 GT/s, the probe was designed to use with any of Teledyne LeCroy Gen3 capable
analyzers such as Summit T3-16, Summit T3-8 or Summit T34.
Optionally, a half-width retention connector allows probing for bidirectional PCIe x4 links or 8 lanes of unidirectional traffic.
This probe can be used in conjunction with the unique lane swizzling feature on the Summit Analyzer (see To Configure
Swizzling for details), which allows probed signals to be reorganized logically, to give developers additional flexibility in
PCB layout.
Analyzer
Probe
Pod
Figure 1: Gen3 Midbus half-size probe and components.
2
Components
The Teledyne LeCroy Gen3 Midbus full-size probe kit can be used with Summit Analyzers and includes the following
components:
• Midbus Pod
• iPass Y x8 cable
• x8 probe head cable assembly
• Optional x4 probe head cable assembly
•
•
•
•
Two reference clock cables
Two daisy chain cables
Power supply
Two pod mounting brackets and four screws with lock washers
• Full-width Midbus retention module (for bidirectional x8 or unidirectional x16 footprints)
• Optional half-width Midbus retention module (for bidirectional x4 or unidirectional x8)
• Gen3 Midbus Probe with SRIS Support Quick Start Guide
3
Hardware Installation
The following installation steps assume that a x8 bidirectional Midbus footprint will be used. For other connection
configurations refer to the corresponding Summit Analyzer User’s Manual.
To Install the Components
1. Install the retention module in the Midbus footprint. Exercise caution not to over-tighten the retention module to the PCB.
• For further details, review the PCI Express Midbus Probe for Summit Analyzer manual on the Teledyne LeCroy website,
or the Summit Analyzer installation DVD.
2. Attach the probe head to the retention module and secure it by tightening the thumbscrews on the probe head. See
Figure 2.
Thumbscrews
Probe head cable assembly
Retention module
Figure 2. Attaching the Probe Head.
2
3. Connect the blue cables from the probe head to the Pod, making sure the "A" and "B" labels in the cable match the
labels in the Pod. See Figure 3.
• The cable connectors to the Pod are keyed; do not use force, as they may become damaged.
B
A
A
Pod
B
B
A
B
A
Cables
Figure 3. Installing cables.
4. Connect the iPass cable assembly to the Pod first (Figure 4), and then to the Summit Analyzer (Figure 5).
Figure 4. Plugging iPass cable into the Midbus Pod.
Figure 5. Plugging iPass cable into Analyzer.
3
5. If an external clock is required, connect the provided reference clock cable to the DS_Clk/Ref_Clk input port on the Pod
and the clock supply from the DUT. See Figure 6.
• The reference clock cable is configured at one end to attach to a two-pin header on the DUT, and the other end has a
connector that clips into the Ref Clk In port on the Pod.
• The DIP switch in the Pod controls clock routing to the iPass cable and to the Analyzer. Make sure they are properly
set up according to the table in the Clock Configuration section.
• Use the Common Clock Reference Input with an external reference clock for single-clock applications. See Figure 7.
Figure 6. Clock cable connection.
• The external reference clock also allows the Analyzer to obtain lock more quickly when a link is returning from a low
power state. If the DUT does not supply a reference clock, then the internal reference clock in the Analyzer can be used
instead, and the reference clock cables are not required.
• Select the external reference clock or the internal Analyzer clock in the Recording Options dialog of the Analyzer
software. (See the Software Configuration section.)
Common Clock
Reference Input
Figure 7. Common Clock Reference Input on the Pod.
4
• Reference clock cables are provided with each Probe Pod (Figure 7) to be used when recording PCIe traffic with an
external clock. If the PCI Express link under analysis uses spread-spectrum clocking, then the external reference clock
from the Device Under Test (DUT) must be used.
• When using the Gen3 Midbus probe with SRIS, you must connect the DUT's Upstream and Downstream clocks to the
US_Clk In and DS_Clk/Ref_Clk In ports on the Pod.
6. Connect power supply to the Pod. See Figure 8.
• This is optional when using Summit T3-16 and Summit T3-8 analyzers.
Figure 8. Connecting power cable.
7. Power on the Analyzer.
• The Pod and the Analyzer are ready to begin analysis.
4
Clock Configuration
Use the tables below to configure switches for clock selection for each direction in the Analyzer.
1
2
Selected clock for cable A
(Downstream Direction)
3
4
Selected clock for cable B
(Upstream Direction)
ON ON Reserved.
ON
ON Reserved.
OFF ON DS_Clk/Ref_Clk Downstream clock for SRIS
or Reference Clock for common clock
configuration.
OFF ON DS_Clk/Ref_Clk Downstream clock for SRIS
or Reference Clock for common clock configuration.
ON OFF US_Clk Upstream clock used for SRIS.
ON OFF US_Clk Upstream clock used for SRIS.
OFF OFF Reserved.
OFF OFF Reserved.
Note: Factory defaults: 1 = Off, 2 = On, 3 = Off, 4 = On.
5
5
Optional Bracket Installation: Horizontal
The components included with the Gen3 MidBus Probe include two mounting brackets and four screws with lock washers
for the Probe Pod to keep it securely attached to your work area. The Probe Pod can be mounted horizontally or vertically.
The method is basically the same only the orientation of the bracket differs for vertical mounting (rotated 90 degrees).
WARNING: Use only the screws provided, as longer screws may go deeper in the probe pod and damage
internal components.
See figures below for PCI Express MidBus Probe Pod Horizontal Installation:
Step 1: Align the screws, washers and brackets with the holes on both sides of the PCI Express MidBus Probe Pod.
Step 2: Tighten the screws to secure the brackets to the sides of the PCI Express MidBus Probe Pod.
6
Software Configuration
The default configuration of the Gen3 Midbus Probe Assembly is the x8 width configuration.
To properly analyze the PCIe link using Summit Analyzers, you must first create the correct mapping between the Midbus
footprint and the connected lanes for the Analyzer. This is done in the Swizzling Configuration (see figure below) setup in
the Recording Options dialog.
Figure 9. Recording options.
• If necessary, check the External Clock option in the Recording Options main dialog.
To Configure Swizzling
1. Open the PCIe Protocol Suite application on the host machine.
2. Open the Recording Options dialog.
3. The Analyzer type connected is displayed under Recording Type (top left in Figure 9).
4. In the Link section (on the right), select the appropriate link width (up to x8 uses a single probe Pod).
5. At the bottom of the Link section, select Swizzling Config to display the Swizzling Configuration dialog. See Figure 10.
• You can drag and drop lane numbers to change lane order and match the actual connection.
6. Make sure Master Lane is dragged to an appropriate location. The Master Lane is the location of Lane 0. If you do not
know the location of Lane 0, any other active lane will work.
:
Configuration Note
• When you use the Midbus Pod with 8.0 GT/s traffic, tune the probe settings in the PCIe Protocol Suite Recording Options:
1. Manually set the 8.0 GT/s DC Gain to 3 dB for all lanes.
2. If this does not result in Gen3 error-free traces, set the DC Gain back to 0 db and try running Auto Configure.
3. Refer to the Probe Settings section in the Analyzer manual for more information.
Master Lane
Auto-Configure lane swizzle is
supported by Summit T3-16 and
T3-8.
Figure 10. Swizzling configuration.
7
Recording Traffic
Once you have set up the hardware and software, you can begin to record traffic.
For instructions on setting up and implementing a recording, please refer to the Summit PCI Express Multi-Lane Protocol
Analyzer User Manual.
8
Environmental Conditions
•
•
•
Temperature: Operating 32 °F to 122 °F (0 °C to 50 °C)
Temperature: Non-Operating 14 °F to 176 °F (-10 °C to 80 °C)
Humidity: Operating 10% to 90% RH (non-condensing)
Teledyne LeCroy Customer Support
Online Download
Periodically check the Teledyne LeCroy Protocol Solutions Group
web site for software updates and other support related to this
product. Software updates are available to users with a current
maintenance agreement.
Mail:
3385 Scott Blvd., Santa Clara, CA 95054-3115
Web:
teledynelecroy.com/Support/SoftwareDownload/
E-mail: [email protected]
Tel:
(800) 909-7112 (USA and Canada)
Tel:
(408) 653-1260 (worldwide)
Fax:
(408) 727-6622 (worldwide)
Trademarks and Servicemarks
Changes
Teledyne LeCroy and Summit T3-16, Summit T3-8 and Summit
T34 are trademarks of Teledyne LeCroy. Microsoft and Windows
are registered trademarks of Microsoft Inc. All other trademarks
are property of their respective companies.
Product specifications are subject to change without notice.
Teledyne LeCroy reserves the right to revise the information
in this document without notice or penalty.
Copyright
© 2014 Teledyne LeCroy, Inc. All rights reserved.
Part Number: 925054-00 Rev B
This document may be printed and reproduced without additional permission, but all copies should contain this copyright notice.