Phase Noise and Jitter in

Transcription

2014 IFCS, Taipei, Taiwan, 19–22 May 2014
Phase Noise and Jitter in
Digital Electronic Components
Claudio E. Calosso∇ and Enrico Rubiola
∇ INRIM, Torino, Italy
CNRS FEMTO-ST Institute, Besancon, France
Outline
•
•
•
•
Noise mechanisms
Phase noise in selected devices
Some facts related to phase and noise
Phase noise in microwave devices
home page http://rubiola.org
Motivations
• Low-noise frequency synthesis
• Started with the Λ dividers on a CPLD (10 phases)
• Successful, and ridiculously simple
• Hoped a 1 GHz –> 5 MHz divider (200 phases) on FPGA
kills the noise, and compete with the analog dividers
• No way!
• The world goes digital
• IC manufacturers / users only care about total jitter
• We all want
• Phase noise,
• ADEV
• Stability of the delay
2
3
Noise Mechanisms
Phase and phase-time
S (f )
𝞅
random phase
'(t)
b
–1 /ƒ
b0
σx(τ )
2
x
2
x
b0
=
2⌧
f
phase-time
(fluctuation)
'(t)
x(t) =
2⇡⌫0
= 2 ln(2) b–1
τ
TDEV σx(τ)
same as ADEV,
but we use
x(t) instead of y(t)
You may be more familiar to σy2(τ) = h0/2τ + 2ln(2)h–1
4
Phase noise in the input stage
in
threshold noise
v(t)
𝞅-type noise
out
Σ
5
SV (f )
S' (f ) =
V02
phase noise
𝞅(t)
constant vs ⌫0
Threshold fluctuation
vin
threshold
error V
actual threshold
nominal threshold
slope
SR = dv/dt
t
error x =
V /SR
vout
t
mechanism
( V )(t)
x(t) =
(SR)(t)
2⇡⌫0 ( V )(t)
'(t) =
(SR)(t)
Threshold-noise measurement
logic circuit
out
Σ
threshold
noise v(t)
FFT analyzer
idle in
Vdd
in
Gnd
integrator
threshold
–
+
(VOH+VOL)/2
• Keep the logic at the threshold, where it shows analog gain
• Measure the voltage (current) fluctuation needed to
stabilise at the threshold
• Works only on simple (old) circuits
• Threshold-mismatched cascade –> gain not accessible
• FPGAs complexity make the analog gain inaccessible
out
6
Internal delay fluctuation
x-type noise
internal stage
fluctuating delay
x(t)
sharp edge
jittered edge
• The internal delay fluctuates by an amount x(t)
• This has nothing to do with the threshold and to
the frequency – if any
7
8
Full noise mechanism
in
𝞅-type noise
x-type noise
comparator
complex distribution
out
Σ
noise v(t)
high ν0
SR >> noise SR
random delay
full SR
and BW
x(t) = ∑i xi(t)
• The 𝞅-type noise noise may show up or not, depending
on input noise and SR
• At the comparator out, the edges attain full SR and
bandwidth of the technology
• Complex distribution –> independent fluctuations add up
x(t) = ∑i xi(t)
and
<x2(t)> = ∑i <xi2(t)>
9
Aliasing mechanism
analog gain
squarewave
clock
t
equivalent sampling function
input sampling frequency 2⌫0
aliasing
jittering edges, variance σ2 = <x2(t)>
White S𝞅(f ) = b0
t
low-freq
sin input
e
t
i
wh ise
no
squarewave
clock
high-freq
sin input
aliasing
saturated
! noise bandwidth B = ⌫0
Flicker and slow noise types
White noise
• Too low power at high
frequency
• The variance σ2 is independent
of frequency
• Parseval theorem applies
• No aliasing
σ2 = b0 B = b0 ν0
• Aliasing –> higher phase noise
at lower carrier frequency
gure 1 shows an example of phase noise measured on a
of the
noise
cloneSummary
III FPGA programmed
to replicate
the types
clock to the
tput. Thus, the input is a 10 dBm sinusoidal signal, and
10
TAB I: BASIC NOISE TYPES
Noise type
3 Pure x-type
4 Aliased x-type
1 Pure φ-type
2 Aliased φ-type
Dependence on ν0
Sφ(ƒ)
Sx(ƒ)
2
ν0
C vs. ν0
ν0
1/ν0
2
C vs. ν0
1/ν0
3
1/ν0
1/ν0
1/ƒ
seldom
1/ƒ
white
11
Phase Noise in
Selected Devices
Measurements are performed with the Symmetricom
(Microsemi) DS 5125 and 5120 dual-channel phase meter
MAX 3000 CPLD [300 nm] (1)
Π divider
÷ 10
b
–1
D-type register
in
=–
out
÷ 10
b
–1
D
shift register
in
out
÷ 10
shift register
D
12
0d
B
=–
13
–1
16
–1
0.5
ar
28
.5
.5
dB
dB
dB
tif
ac
ts?
nt
cie ?
uffi ing
ins erag
av
Λ divider
Λ and Π dividers
(multibuffer Π config)
b–1 ≈ –156 dB
b0 ≈ –165 dB
experimental problems still present
• Flicker region –> Negligible aliasing
• The Π divider is still not well explained
• The Λ divider exhibits low 1/ƒ and low white noise
12
MAX 3000 CPLD [300 nm] (2)
• Slope 1/τ, typical of white and flicker PM noise
• The Λ divider performs 2×10–14 at τ = 1 s, 10 MHz output
13
Max V CPLD [180 mn]
14
• Two lambda dividers
• output-to-output
and common clock,
• low ƒ, emphasizes
the 1/f noise
• Same, only output-tooutput and common
clock
Max V CPLD [180 nm]
15
• Two lambda
dividers
• output-to-output
and common
clock,
• low ƒ, emphasizes
the 1/f noise
• Clock, difference
between the two
outputs
16
Cyclone Λ divider [90 nm]
!
Cyclone II Clock Buffer [90 nm]
17
Cyclone III Clock Buffer
18
Flicker
–>
φ
as
ali
bu
m
p
ed
-φ
x-t
yp
e
• High ν0 –> scales
as ν0 (x-type)
• Low ν0
e
p
y
-t
tends to 𝞅-type
bumps 0.1–10 Hz
White
• Aliasing shows up
at low ν0
Zynq (28 nm) , Λ divider
100 –> 10 MHz
• File ZedBoard.doc
• One phase noise spectrum
19
φ-
ty
pe
x-
ty
pe
74S140 – Old TTL 50 Ω driver
20
aliased-φ
Flicker coefficient b–1
unfortunate
outcome?
Const
21
V
1/
w
La
3)
/L
(1
22
Some Facts
Related to Phase and Noise
Cyclone III, voltage supply
I/O 3.3 V
PLL 2.5 V (unused)
Core 1.2 V 1
Digital PLL 1.2 V 2
• All but one low-noise voltage supplies
• The noise is critical only in the core supply
23
24
Input Chatter (1/3)
Chatter occurs when the RMS Slew Rate of noise
exceeds the slew rate of the pure signal
chatter
region
Pure signal
x(t) = V0 cos(2⇡⌫0 t)
SR = 2⇡⌫0 V0
Wide band noise
⌦
SR
↵
2
Z
B
= 4⇡ 2
4⇡ 2
=
3
f 2 SV (f ) df
0
2
V
B2
(rms)
Chatter threshold
Example
• 200 mVp signal
• 10 nV/√Hz noise
• 1 GHz max –> 3 GHz noise BW
• Chatter threshold 𝝼 = 4.7 MHz
3
1
S
B
v
2
⌫0 =
3 V02
With high-speed devices,
chatter can occur at
unexpectedly high frequencies
Simulation of Chatter (2/3)
= 2.0 Hz, Noise = 10.0 mVrms
1.0 B
E. Rubiola, 18 oct 2011
= 64.0 Hz, Noise = 10.0 mVrms
1.0 B
= 2048.0 Hz, Noise = 10.0 mVrms
1.0 B
0.5
0.5
0.5
0.0
threshold
0.0
threshold
0.0
0.5
0.5
0.5
1.0
1.0
1.0
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.2
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.2
B = 1.0 Hz, Noise = 10.0 mVrms
0.1
threshold
0.0
0.1
0.1
0.1
0.2
0.48
0.49
0.50
0.51
0.2
0.47
0.2
0.48
0.49
0.50
0.51
time
0.52
0.53
0.2
0.47
0.2
0.1
0.0
0.1
0.1
0.1
0.2
0.49
0.50
0.51
0.52
time
0.53
0.2
0.47
0.2
0.48
0.49
0.50
0.51
0.52
time
0.53
0.2
threshold
0.0
0.1
0.1
0.1
0.2
0.48
0.49
0.50
0.51
0.2
0.47
0.2
0.48
0.49
0.50
0.51
time
0.52
0.53
0.2
B = 1024.0 Hz, Noise = 10.0 mVrms
0.0
0.1
0.1
0.1
0.49
0.50
0.51
0.52
time
0.53
0.48
0.49
0.50
0.51
time
0.52
0.53
B = 2048.0 Hz, Noise = 10.0 mVrms
threshold
0.0
0.48
time
0.53
0.1
threshold
0.0
0.2
0.47
0.52
0.1
threshold
0.51
0.2
0.47
0.1
0.50
threshold
0.0
time
0.52
0.53
0.49
0.1
0.0
0.2
0.47
0.48
0.1
threshold
0.2
0.47
0.1
0.51
threshold
0.0
0.48
0.50
0.1
threshold
0.0
0.2
0.47
0.49
time
0.52
0.53
0.1
threshold
0.48
0.2
0.47
0.48
0.49
0.50
0.51
0.52
time
0.53
0.2
0.47
0.48
0.49
0.50
0.51
V0 = 1 Vpeak
√<v02> = 10 mV
rms noise
threshold
0.0
time
0.52
0.53
0.1
0.0
0.2
0.47
ν0 = 1 Hz,
0.1
threshold
threshold
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.2
Conditions
0.52
time
0.53
Noise BW
increases in
powers of 2
De-normalize for
your needs
25
Input chatter – Example (3/3)
Fairly good agreement with theory
Experiment
• Cyclone III FPGA
• Estimated noise 10 nV/√Hz
• Estimated BW 2 GHz
2V0 = 100 mVpp
ν0 = 4.7 MHz
2V0 = 200 mVpp
ν0 = 4.7 MHz
Asymmetry shows up
Explanation takes a detailed
electrical model, which we
have not
26
Cyclone III Internal PLL (1/3)
PL
L FPGA
10
MHz
Input
Symmetricom
5120A (30 MHz max)
Phasemeter
10
MHz
Reference
PL
L
10
Λ
MHz
Div.FPGA
10
MHz
Input
Phasemeter
Reference
• A Λ divider (inside the FPGA) enables the measurement
• The divider noise is low enough
• A trick to work at low frequency
27
1/ƒ
28
PLL used as a
multiplier
!
10 MHz input
!
N x 10 MHz out
Stability
1.5x10–12 @ 1 s
(fH = 500 Hz)
• 1/ƒ phase noise is dominant
• Scales as xN2 –> gear work
PLL used as a
buffer
φ
-ty
pe
x-t
yp
e
!
• 𝞅-type 16 µrad/√Hz @ 1 Hz
• x-type 220 fs/√Hz @ 1 Hz
Same
frequency at
input and
output
Crossover between
phi-type and x-type
at 20 MHz
29
Thermal effects (1/3)
Principle
30
C
• FPGA dissipation change ∆P by acting on frequency
• Energy E = CV2 dissipated by the gate capacitor in a cycle
Conditions
1
• Cyclone III used as a clock buffer
• Environment temperature fluctuations are filtered out with a
small blanket (necessary)
≈400 s
• Two separate measurements (phase rift
meter and counter) –> trusted result
1 fs/s d
Outcome (Left to right)
2
Cyclone III clock buffer
50 MHz –> 25 MHz
transient
(1) Thermal transient, due to the
change of the FPGA dissipation
(2) Overall effect of ∆P
(3) Slow thermal drift, due to the
environment
3
12 ps
31
e
P
∆
f
o
ffect
–15 drift
10
400 s time
constant
Phase time, ps
Cyclone III clock buffer
e
m
ti
s
n
co
t
n
ta
–15 drift
0
1
environm.
drift
–15 drift
0
1
–15 drift
0
1
5
10–1 drift
Warning: In real applications, other parts of the same FPGA
impact on the temperature, thus on phase – drift is possible
32
1 H dead time
after changing ν0
Measurement starts
immediately after changing ν0
10–13
10–14
thermal drift
no or
low dr
if
t
10–15
33
Phase Noise in
Microwave Dividers
NB7L32M ÷2 µwave divider
10 GHz ÷ 2 = 5 GHz
ck
cl
oc
–100
k
ou
to
–119
tp
u
ts
ta
ou
• Use 5.01 GHz as a
common oscillator,
and beat
tp
u
• Digital PM noise
measurement at 10
MHz
on
• O-I: Two equal
dividers
t
ge
Method
• Compare two
dividers
+out
–out
÷2
34
ly
–139
–144
!NB7L32M_OOvsOI_04_spectrum.png
• O-O: Two outputs of
the same divider
• Shown: spectrum of
one divider
x-
ty
pe
Phase noise vs input frequency
φ-
ty
pe
too large ∆
ou
tp
ut
st
ag
!NB7L32M_O-I_04_spectrum.png
e,
5
GH
z
35
36
Works fairy well even at low input power (useful)
Notes
–9
–1
• At –16 dBm the
white noise
increases by 3 dB
6
00
• The critical power
where (b0)ᵩ = (b0)x
is –16 dBm
–134.5
–139
–140
!NB7L32M_OI_Pscan_04_spectrum.png
• Hence (b0)x-type ≈ –140 dB
37
NBSG53A SiGe ÷2 µwave divider
Method
–9
–1
03
.5
6.
• Use 5.01 (2.51) GHz
as a pivot oscillator,
and mixers
5
• Digital PM noise
measurement at 10
MHz
7 dB
• One divider shown
4 dB
–136
–140
File !NBSG-freq_O-I_04_spectrum.png
• 1/ƒ –> pure gearbox model (as expected)
• White –> aliased gearbox model (as expected)
Debugged:
–97.5 and –137• Likely, 1 dB discrepancy in w and 1/f (mixer response)
38
–8
–9
5
7.5
f
e
i
l
e
b
ƒ
/
n
1
o
w
m
o
l
m
o
s
a
C
h
e
G
i
S–125.5
NB
7L
32
M
–9
5
–135.5
!NBSG53A_OI_Pscan_04_spectrum.png
NB7L32M
–137
• Compares unfavourably to the NB7L32M
• More noise and less tolerance to low power
39
di
vi
de
r
Output vs Output gives info about the output stage
–1
17
–1
18
–1
15
–132.5
–139
–140
!NBSG53A_OO_Pscan_04_spectrum.png
The problem seems in the gear box, rather in the output stage
Hittite HMC-C040, ÷10 divider
2 Hittite divider by 10 HMC−C040, Fin=10GHz
−100
2 dividers by 10, input power: −9 dBm
2 dividers by 10, input power: −3 dBm
2 dividers by 10, input power: 5 dBm
SSB PPSD (dBrad2/Hz)
−110
Courtesy of
S. Grop
−120
−130
−140
−150
Take away 3 dB for one divider
1
10
100
1000
Fourier frequency (Hz)
10000
100000
40
Microwave dividers compared
10 GHz ÷2
NB7L32M
NBSG53A
HMC-C040
HMC705LP4
–100
97.5
5 GHz ÷2 2.5 GHz ÷2
–109
–103.5
–109
lower
–109
–104
–113
–121
600 MHz
1.2 GHz ÷2
800 MHz
1.6 GHz ÷2
1 GHz
10 GHz ÷10
0.5 GHz
2.5 GHz ÷5
41
Conclusions
• Two main noise types, x-type and 𝞅-type
• Observed on a few logic devices and gate arrays
• Also in microwave dividers
• The 1/Volume law describes 1/ƒ (few cases)
• Other effects (chatter, temperature, etc.)
• The choice of devices is independent of this work No expressed/implied endorsement on these device
• Funds
• ANR Oscillator IMP and First-TF
• Region Franche Comte
• EMRP Project IND 55 Mclocks
A special thanks to all members of the
Go Digital working group, at FEMTO-ST and INRIM
All slides {are | will be}
on my home page
http://rubiola.org
42

Phase Noise and Jitter in

Transcription

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