The Phase Change Memories

A Step Ahead in
Phase Change Memory
Technology
Roberto Bez
Process R&D
Agrate Brianza (Milan), Italy
29 June 2011
©2010 Micron Technology, Inc.
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Outline
• Non Volatile Memories Status
• The Phase Change Memories
• An Outlook to the Next Steps
29 June 2011
©2010 Micron Technology, Inc.
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100
1000
10
100
1
10
0.1
1
0.01
0.1
2000
2002
2004
2006
2008
2010
Year
NAND Eb
DRAM Eb
NAND $/Gb
DRAM $/Gb
This triggered the use of NVM in
a wide spectrum of applications
Intel-Micron 64Gbit NAND
20nm NAND MLC technology
29 June 2011
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Price ($/Gb)
In the last years volume of NVM increased
exponentially (with a clear cost reduction..)
Total Volume (Eb)
Non Volatile Memory Market
Flash Cell Scaling Challenges
NAND
Cell basic structure unchanged
through the different generations
Cell area scaling through:
L
y-pitch
1. Active device scaling (W/L)
2. Passive elements scaling
W
x-pitch
Main scaling issues:
Number of stored electrons
Cell proximity interference
Tunnel and interpoly dielectric thickness
Isolation spacing and WL voltage increase
Random Telegraph Noise
Trapping/detrapping, SILC
Retention after cycling
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CG
CONO
CFG
FG
CTUN
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Key Requirements of an Alternative NVM
• Readiness for beyond leading edge technology node
• Scalability
• Cost structure
▶
MLC capable
▶
3D stackable
• Performance
▶
High Program and Read Throughput
▶
Low power
▶
Flexibility
• Reliability
▶
Non-volatility with long retention (e.g. > 10 years)
▶
Extended number of read cycles
▶
High program endurance
29 June 2011
©2010 Micron Technology, Inc.
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5
Outline
• Non Volatile Memories Status
• The Phase Change Memories
• An Outlook to the Next Steps
29 June 2011
©2010 Micron Technology, Inc.
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6
Key Messages
• Significant Innovation Takes Time
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NVM Technology Development
Storage Element
Memory Cell
Memory Cell
Array (Test Chip)
1st Product
Concept
Demonstration
Technology
Validation
29 June 2011
Manufacturability
Product Reliability
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Non-Volatile Memory History
1967 First Floating Gate Structure
1971 FAMOS
1977 EPROM
1980 EEPROM
1985 1T EEPROM (Flash)
1988 NOR Flash
1989 NAND Flash
1995 MLC NOR
2005 MLC NAND
2010 Intel-Micron 64Gb MLC NAND
in 25nm technology
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History of PCM Development
F. Pellizzer et al.,
VLSI 2004
180nm
S. Lai and T. Lowrey,
IEDM 2001
180nm
G. Servalli,
IEDM 2009
45nm
F. Pellizzer et al.,
VLSI 2006
90nm
PCM
cell
G. Casagrande et al.,
VLSI 2004
180nm
M. Gill et al.,
ISSCC 2002
180nm
C. Villa et al.,
ISSCC 2010
45nm 1Gb
Bedeschi et al.,
ISSCC 2008
90nm 128Mb (256Mb MLC)
PCM array
& chip
2001
2003
Concept
Demonstration
29 June 2011
2005
2007
Technology Validation
Product Reliability
2009
2011
Manufacturing
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Key Messages
• Significant Innovation Takes Time
• A NVM Concept/Technology Must Have a
Wide Spectrum of Application
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Phase Change Memory Key Attributes
•
Non Volatility
•
Flexibility
▶
Attributes
No Erase, Bit
alterable, Continuous
Writing
•
Lower power
consumption than RAM
•
Fast Writes
•
Read bandwidth and
writing throughput
•
eXecution in Place
•
Extended endurance
PCM
EEPROM
NOR
NAND
DRAM
Non-Volatile
Yes
Yes
Yes
Yes
No
Scaling
sub-2x nm
n.a.
3x nm
2x nm
3x nm
Granularity
Small/Byte
Small/Byte
Large
Large
Small/Byte
Erase
No
No
Yes
Yes
No
Software
Easy
Easy
Moderate
Hard
Easy
Power
~Flash
~Flash
~Flash
~Flash
High
Write Bandwidth
1- 15+
13-30
0.5-2
10+
100+
MB/s
KB/s
MB/s
MB/s
MB/s
Read Latency
50 - 100 ns
200-200 ns
70-100 ns
15 - 50 us
20 - 80 ns
Endurance
106+
105 -106
105
104-5
Unlimited
PCM provides an new set of features combining
components of NVM with DRAM
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Selectors and PCM Array Architectures
MOSFET
BJT/Diode
Dedicated steps for the
OTS
Process
No mask overhead for
Complexity
the selector
Cell Size
Larger (~20F2)
Smaller (~5F2)
3D cross-point (~4F2/n)
Conventional
Innovative
Ground-breaking
Memory Array
Organization
Application
Embedded memory
High density/
High Performance
Very high density
WL
Schematic Cell
Cross-section
BEOL
integration
BL
Structure
p-n-p junction
Dedicated steps in the
BL
GND
BL
OTS
WL
n+
OUM
n+
p-substrate
29 June 2011
STI
p+
n+
n-well
p-substrate
WL
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Embedded PCM (ePCM)
IMW 2010
IEDM 2009
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Stand-Alone NVM TAM Expansion
($K)
}
Cost,
Reliability, &
Performance
}
Cost, Cost
& Cost!!!
Wireless
SSD
Industrial / CE
Bulk NAND
Source: iSuppli Application Market Forecast Tool , June 2010
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PCM Application Opportunities
PCM feature can be exploited by all the memory system, especially the
ones resulting from the convergence of consumer, computer and
communication electronics
• Wireless System to store of XiP, semi-static data and files
▶ Bit alterability allows direct-write memory
• Solid State Storage Subsystem to store frequently accessed pages
and elements easily managed when manipulated in place
▶
Caching with PCM will improve performance and reliability
• Computing Platforms taking advantage of non-volatility to reduce
the power
▶
PCM offers endurance and write latency that are compelling for a number of
novel solutions
S.Eilert et al., “PCM: a new memory enables new memory usage models”, IMW, 2009
29 June 2011
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MLC Capability
“Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory”
IBM/Macronix, IEDM 2007
“A Multi-Level-Cell Bipolar Selected Phase Change Memory”
Numonyx, ISSCC 2008
“Drift-Tolerant Multileve Phase Change Memory”
IBM, IMW 2011
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Key Messages
• Significant Innovation Takes Time
• A NVM Concept Must Have a Wide
Spectrum of Application
• A New NVM Must Be Scalable
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Ultimate Scalability of PCM
Y. C. Chen et al., IEDM 2006
P.Wong, EPCOS 2010
•
Device functionality demonstrated
on 60 nm2 active area
•
Reset current <10uA
•
Phase change mechanism appears
scalable to at least ~5nm
C. Lam, SRC NVM Forum 2004
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Outline
• Non Volatile Memories Status
• The Phase Change Memories
• An Outlook to the Next Steps
29 June 2011
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An Outlook to the Future…
• Scaling the existing architecture,
providing the smallest cell size,
following the lithography roadmap
Ge or M (at %)
• Exploring new chalcogenide alloys
which may open new application
fields
0 100
10
90
GeSbTe(GST) 20
80
30
70
GeTe 40
50
DVD+RAM
60
70
80
90
100
225
124
Doped SbTe
60
DVD+RW
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
Sb2Te3 Sb2Te
Te (at %)
Sb (at %)
147
M-Sb2Te
• Exploiting a true cross-point array
which will allow vertical stacking of
more than one memory layer
DerChang Kau et al., IEDM 2009
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PCM Active Material
Despite Ge2Sb2Te5 has been demonstrated a good material for PCM
fabrication, many other chalcogenide materials are available for use in solid
state memories, exploiting the experience of optical disk research
• But other requirements must be satisfied:
Ge or M (at %)
0 100
90
10
GeSbTe(GST) 20
80
30
70
GeTe 40
50
DVD+RAM
60
70
80
90
100
225
124
Doped SbTe
60
DVD+RW
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
Sb2Te3 Sb2Te
Te (at %)
Sb (at %)
147
M-Sb2Te
• Electronic switching capability with reasonable
switching voltage
• Sufficiently low set resistance for reading
performances
• Sufficiently low melting temperature for
program performances
• Stability under million of cycles
• Higher crystallization temperature for better
retention
From optical disk experience Ge, Sb, Te, In, Si compounds are most
suitable materials for employment in solid state devices
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GST Ternary Diagram
Goal: improve the
cell performances
•
GeSbTe ternary
compound system
•
GeTe – Sb2Te3
pseudo-binary line
M. Boniardi et al., IMW 2010
• Sb – rich region exploration is done to electrically study new compounds
in the fast growth Sb69Te31 direction
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Electrical Characteristics
•
•
Decrease of the reset resistance with the increase in the Sb
concentration
Convergence of the set level to the minimum set
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Higher-Temperature Chalcogenide
“N-doped GeTe as Performance Booster for
Embedded Phase-Change Memories”
CEA-LETI/ST, IEDM 2010
“On Carbon doping to improve GeTe-based
Phase-Change Memory data retention at
high temperature”
CEA-LETI/ST, IMW 2010
“Electrical Performances of Tellurium-rich Gex-Te1-x
Phase Change Memory”
CEA-LETI/ST, IMW 2011
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Further Key Materials
•
Other key issue of the PCM cell engineering are:
▶
Role of thermal environment: thermal conductivity of the
surrounding dielectrics
▶
Role of thermal interfaces between materials
▶
Role of electrical interface between materials
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PCM Self-Heating Cell Structure
Planar
structures
Vertical self-heating structure
with fully confined GST very conformal chalcogenide
deposition required (e.g. ALD)
29 June 2011
2010 Symp. On VLSI Tech.
Samsung
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3D Integration Cross-Point Memory
• Crossbar memory attracts great interests
▶
“simple” structure and minimum cell size (4F2)
low cost
▶
suitable for 3D stacking cell size (4/n)F2
▶
array over circuitry better array efficiency
• The basic cell architecture requires a
Vprog/2
Vprog
Vprog/2
selector structure to be integrated in the
BEOL
Vprog/2
▶
Parasitic paths exist through neighbouring cells
▶
Programming (and also reading) can perturb
the array
0V
Vprog/2
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A Wide Range of Material Choices
Selector device
Storing device
• Homojunctions polySi p/n junctions
• Heterojunctions p-CuO/n-InZnO
• Schottky diode Ag/n-ZnO
• Chalcogenide Ovonic Threshold
Switching (OTS) materials
• STTRAM
• RRAM or CBRAM
• PCM
• Mixed Ionic Electronic Conduction
(MIEC) materials
For the selector structure few
concepts have been proposed so
far, all in the “path finding” phase
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Cross-Point Switch Requirements
• Very high forward bias current
▶
greater than the switching current
• Low reverse bias current
▶
Prevent loss of signal by cross talk
▶
Leakage may set the block size
• Composition compatible with memory material
• Low temperature process
• Bipolar operation
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PCMS Memory Cell Cross-Bar Architecture
Ovonic Threshold Switch, OTS, is a two-terminal switch
Colu
mn
w
Ro
Met
al
Si-S
u
bst r
1
et
M
2
al
l
Po
at e
Intel-Numonyx, IEDM 2009
Chalcogenide materials can be used both for the memory and for
the selector (OTS) to form stackable cross point PCM (PCMS)
•True high density cross-bar
•Possible multilayer vertical stacking
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y
Conclusions
• The mainstream Non-Volatile Memory (Flash) is today
approaching its scaling limitation
• Several other alternative concepts have been proposed but
few of them are really appealing from a cost stand point
• Among those technology, PCM is today in a privileged
position, having already demonstrated functionality and
reliability at 90 nm and 45 nm nodes on large products
• Large room for chalcogenide material and cell engineering
• Crossbar 3D approach has been identified as a viable way
to further reduce the cost/bit
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July 11