How To Prepare Designs for 65 nm MirrorBit GL and Eclipse

How To Prepare Designs for 65 nm MirrorBit® GL and
65 nm MirrorBit® EclipseTM GL Product Families
Application Note
By: Doug Kearns
1. Introduction
Spansion continues to extend the MirrorBit® GL family of 3V NOR Flash and in 2008 and 2009 will introduce
two new GL families based on 65 nm MirrorBit technology. The S29GL-R family will be a close copy of the
existing 90nm S29GL-P family and the S29GL-S family will incorporate the MirrorBit® EclipseTM architecture
to the GL Flash portfolio. Spansion is developing these families with migration in mind and customers can
readily prepare current projects in development to allow use of these new families as they become available.
This document will outline the product differences that will require attention to facilitate the migration in the
future.
2. GL Family Feature Comparison
Table 2.1 provides an overview of the differences between the various high density MirrorBit GL families. The
65 nm MirrorBit Eclipse GL family will bring improved program and erase performance to high density
MirrorBit NOR applications while maintaining basic hardware and software compatibility to allow use on
existing designs. The feature differences will be discussed individually in Section 3.
One underlying difference between the current MirrorBit GL and future 65 nm products is the use of a static
micro controller to manage internal flash activities instead of a hard-wired state machine. The benefit of this
approach is significant efficiencies gained during wafer level production test. The trade off with this approach
is an increase in the time required for the device to self-configure when power is applied. The differences in
Power On Reset timing will be discussed in detail in Section 4. The differences in AC & DC specifications are
detailed in Section 5.
Table 2.1 GL Family Feature Comparison
Family
S29GL-N
S29GL-P
S29GL-R
S29GL-S
Process Node
110 nm
90 nm
65 nm
65 nm
Introduction
2005
2007
2008
2009
128 Mbit
√
√
256 Mbit
√
√
512 Mbit
√
√
√
√
1024 Mbit
√
√
√
2048 Mbit
√(multi-die)
Density:
√
√
√
Sector Size:
128KB
√
√
√
√
Data Size:
Bus Width
x8/x16
x8/x16
x8/x16
x16
Read Page
16 Byte
16 Byte
16 Byte
32 Byte
Write Buffer
32 Byte
64 Byte
64 Byte
512 Byte
56-TSOP
√
√
√
√
64-BGA
√
√
√
√
√
√
√
√
Packaging:
Other:
Asynchronous
Publication Number Designs_for_GL_Products_AN
Revision 03
Issue Date December 18, 2008
A pplication
Note
Table 2.1 GL Family Feature Comparison
Family
S29GL-N
S29GL-P
S29GL-R
S29GL-S
OTP Area
256 Byte
256 Byte
512 Byte
1024 Byte
Write Protect
√
√
√
√
√
√
√
√
√
√
Read Protect
Unlock Bypass
√
√
Multi-Sector Erase
√
√
Data Polling
√
√
Status Register
Note
Data polling likely will not be supported in GL products introduced after 65nm MirrorBit Eclipse
3. Feature Difference Discussion
3.1
Density
The S29GL-R family will be available in monolithic 512 and 1024 Mbit densities only.
The S29GL-S family will be available in monolithic 128, 256, 512, 1024, and 2048 Mbit densities only.
Customers currently using the S29GL128P, S29GL256P, S70GL02GP should continue to use these products
while preparing for migration to the S29GL-S equivalent density device starting in 2009.
3.2
Sector Size
The S29GL-R family will have 128 KB uniform sectors, consistent with the existing S29GL-P.
The S29GL-S family will have 128 KB uniform sectors, consistent with the existing S29GL-P.
3.3
Data Size
The S29GL-R will have x8/x16 selectable data bus width, consistent with the existing S29GL-P. When the
BYTE# input is pulled high, the device will operate with a 16-bit wide data bus. When BYTE# is pulled low, the
device will operate with an 8-bit data bus. When BYTE# is pulled low, all unused data bus IO, DQ[15:8],
should be pulled low.
The S29GL-S will only support x16 data bus width. The BYTE# input on previous generations of MirrorBit GL
devices (pin 53 on 56-TSOP and pad F7 on 64-BGA) will be reserved for optional features on the S29GL-S.
The BYTE# input on existing designs should be pulled high to force operation in x16 data mode to enable
future migration to the S29GL-S.
3.4
Read Page Size
The S29GL-R will have 16-byte (8 word) read page buffer, consistent with the existing S29GL-P.
The S29GL-S will have 32-byte (16 word) read page buffer, which is double the depth of the existing S29GLP to facilitate larger processor cache line fill operations. No software modifications are required to operate
with 16-byte maximum page transfers supported by the existing S29GL-P family.
Software can be modified to take advantage of the deeper read page buffer on the S29GL-S by querying the
CFI programming buffer depth register at address 4Ch (x16 address bus reference) and configuring software
to perform additional page read cycles.
3.5
Write Buffer Size
The S29GL-R will have 64-byte (32 word) write buffer, the same depth as the existing S29GL-P and double
the depth of the existing S29GL-N. No software modifications are required to operate with up to a 32-byte
maximum write buffer fill supported by the existing S29GL-N family.
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The S29GL-S will have 512-byte (256 word) write buffer, eight times the depth of the existing S29GL-P and
sixteen times the depth of the existing S29GL-N. No software modifications are required to operate with up to
a 64-byte or 32-byte maximum write buffer fill supported by the existing S29GL families.
Software can be modified to take advantage of the deeper write buffers by querying the CFI programming
buffer depth register at address 2Ah (x16 address bus reference) and configuring software to perform large
buffer fills.
3.6
Device ID
The 512 Mbit and 1024 Mbit S29GL-R devices will have the same Device ID register values as the monolithic
density versions of the existing S29GL-N and S29GL-P families. Table 3.1 contains the Device ID values for
the GL families.
The 128 Mbit, 256 Mbit, 512 Mbit and 1024 Mbit S29GL-S devices will have the same Device ID register
values as the monolithic density versions of the existing S29GL-N and S29GL-P families. Table 3.1 contains
the Device ID values for the GL families.
Existing software that utilizes Device ID to set up software command support will require no modification to
enable basic functionality of the new MirrorBit GL and MirrorBit Eclipse GL families. Use of specific CFI
register reads should be employed to take advantage of new superset features such as wider read page
buffers and write buffers. CFI Process register bits at address 45h (x16 address bus reference) provide insystem determination of the unique GL family (e.g. GL-N: 0010h, GL-P: 0014h, GL-R: 0018h, GL-S: 001Bh).
Table 3.2 provides details of the CFI register values for each GL family.
Table 3.1 Device IDs
Device ID
Density
S29GL-N
S29/GL-P
S29GL-R
S29GL-S
128 Mb
7Eh / 21h / 01h
7Eh / 21h / 01h
7Eh / 21h / 01h
256 Mbit
7Eh / 22h / 01h
7Eh / 22h / 01h
7Eh / 22h / 01h
512 Mbit
7Eh / 23h / 01h
1 Gbit
7Eh / 23h / 01h
7Eh / 23h / 01h
7Eh / 23h / 01h
7Eh / 28h / 01h
7Eh / 28h / 01h
7Eh / 28h / 01h
2 Gbit
7Eh / 48h / 01h
Note:
In x16 mode, DQ[15:8] = 22h for standard S29GL devices.
Table 3.2 CFI Registers (Sheet 1 of 3)
December 18, 2008
CFI Register
x16 Address
S29GL-N
S29GL-P
S29GL-R
S29GL-S
“QRY” query
unique ASCII
string
10h
11h
12h
0051h
0052h
0059h
0051h
0052h
0059h
0051h
0052h
0059h
0051h
0052h
0059h
Primary OEM
Command Set
13h
14h
0002h
0000h
0002h
0000h
0002h
0000h
0002h
0000h
Address for
Primary Extended
Table
15h
16h
0040h
0000h
0040h
0000h
0040h
0000h
0040h
0000h
Alternate OEM
Command Set
17h
18h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Address for
Alternate OEM
Extended Table
19h
1Ah
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
VCC Min
1Bh
1Ch
0027h
0036h
0027h
0036h
0027h
0036h
0027h
0036h
VPP Min
1Dh
1Eh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Designs_for_GL_Products
3
A pplication
Note
Table 3.2 CFI Registers (Sheet 2 of 3)
CFI Register
x16 Address
S29GL-N
S29GL-P
S29GL-R
S29GL-S
Typical timeout
per single write
1Fh
0007h
0006h
0007h
0007h
Typical timeout
per buffer write
20h
0007h
0006h
0007h
0007h
Typical timeout
per block erase
21h
000Ah
0009h
000Ah
000Ah
Typical timeout for
full chip erase
22h
0000h
0013h
0000h
0000h
Max timeout per
single write
23h
0003h
0003h
0001h
0001h
Max timeout per
buffer write
24h
0005h
0005h
0005h
0005h
Max timeout per
block erase
25h
0004h
0003h
0004h
0004h
Max timeout for
full chip erase
26h
0000h
0002h
0000h
0000h
Device size = 2^N
27h
001Ah (512 Mb),
0019h (256 Mb),
0018h (128 Mb)
001Bh (1 Gb),
001Ah (512 Mb),
0019h (256 Mb),
0018h (128 Mb)
001Bh (1 Gb),
001Ah (512 Mb)
001Ch (2 Gb),
001Bh (1 Gb),
001Ah (512 Mb),
0019h (256 Mb),
0018h (128 Mb)
Flash Device
Interface
description
28h
29h
0002h
0000h
0002h
0000h
0002h
0000h
0001h
0000h
Max Buffer Write
Size = 2^N
2Ah
2Bh
0005h
0000h
0006h
0000h
0006h
0000h
0009h
0000h
Number of Erase
Block Regions
2Ch
0001h
0001h
0001h
0001h
2Dh
00FFh (512 Mb),
00FFh (256 Mb),
007Fh (128 Mb)
00FFh (1 Gb),
00FFh (512 Mb),
00FFh (256 Mb),
007Fh (128 Mb)
00FFh (1 Gb),
00FFh (512 Mb)
00FFh (2 Gb),
00FFh (1 Gb),
00FFh (512 Mb),
00FFh (256 Mb),
007Fh (128 Mb)
2Eh
0001h (512 Mb),
0000h (256 Mb),
0000h (128 Mb)
0003h (1 Gb),
0001h (512 Mb),
0000h (256 Mb),
0000h (128 Mb)
0003h (1 Gb),
0001h (512 Mb)
0007h (2 Gb),
0003h (1 Gb),
0001h (512 Mb),
0000h (256 Mb),
0000h (128 Mb)
2Fh
0000h (512 Mb),
0000h (256 Mb),
0000h (128 Mb)
0000h (1 Gb),
0000h (512 Mb),
0000h (256 Mb),
0000h (128 Mb)
0000h (1 Gb),
0000h (512 Mb)
0000h (2 Gb),
0000h (1 Gb),
0000h (512 Mb),
0000h (256 Mb),
0000h (128 Mb)
Erase Block
Region 1 Info (4)
30h
0002h (512 Mb),
0002h (256 Mb),
0002h (128 Mb)
0002h (1 Gb),
0002h (512 Mb),
0002h (256 Mb),
0002h (128 Mb)
0002h (1 Gb),
0002h (512 Mb)
0002h (2 Gb),
0002h (1 Gb),
0002h (512 Mb),
0002h (256 Mb),
0002h (128 Mb)
Erase Block
Region 2 Info
31h
32h
33h
34h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Erase Block
Region 3 Info
35h
36h
37h
38h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Erase Block
Region 1 Info (1)
Erase Block
Region 1 Info (2)
Erase Block
Region 1 Info (3)
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Table 3.2 CFI Registers (Sheet 3 of 3)
3.7
CFI Register
x16 Address
S29GL-N
S29GL-P
S29GL-R
S29GL-S
Erase Block
Region 4 Info
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
"PRI" query
unique ASCII
string
40h
41h
42h
0050h
0052h
0049h
0050h
0052h
0049h
0050h
0052h
0049h
0050h
0052h
0049h
Major version
number
43h
0031h
0031h
0031h
0031h
Minor version
number
44h
0033h
0033h
0033h
0033h
Address Unlock /
Process bits
45h
0010h
0014h
0018h
001Bh
Erase Suspend
46h
0002h
0002h
0002h
0002h
Sector Protect
47h
0001h
0001h
0001h
0001h
Sector Temporary
Unprotect
48h
0000h
0000h
0000h
0000h
Sector Protection
Scheme
49h
0008h
0008h
0008h
0008h
Simul-Op
4Ah
0000h
0000h
0000h
0000h
Burst Mode
4Bh
0000h
0000h
0000h
0000h
Page Mode Type
4Ch
0002h
0002h
0002h
0003h
ACC Supply Min
4Dh
00B5h
00B5h
00B5h
00B5h
ACC Supply Max
4Eh
00C5h
00C5h
00C5h
00C5h
WP# Protection
4Fh
0004h (Bottom)
0005h (Top)
0004h (Bottom)
0005h (Top)
0004h (Bottom)
0005h (Top)
0004h (Bottom)
0005h (Top)
Program Suspend
50h
0001h
0001h
0001h
0001h
Packaging
The S29GL-R will be available in 56-TSOP and 64-BGA and will have asynchronous operation signal pin out
consistent with the existing S29GL-P. The outer dimensions of the 64-ball BGA packaged will be reduced to 9
x 9 mm from 11 x 13 mm which will mandate changes to the surface mount placement program but not to the
printed circuit board layout.
The S29GL-S will be available in 56-TSOP and 64-BGA and will have asynchronous operation signal pin out
consistent with the existing S29GL-P (see Notes attached to Figures 3.1 and 3.2 for specific pin connection
requirements). The 128, 256, and 512 Mbit density S29GL-S devices will use the LAE064 package, which
has outer dimensions of 9 x 9 mm, smaller than the 10 x 13 mm outer dimensions of the LAA064 package
used by the S29GL-P devices. This dimensional change will mandate modification to the surface mount
placement program but not to the printed circuit board layout. The 1 Gbit and 2 Gbit densities will use the
10 x 13 mm LAA064 package, consistent with the S29GL-P.
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A pplication
Note
Figure 3.1 GL 64-ball Fortified BGA Signal Land Pattern
Notes:
1. Pads A1, A8, H1 & H8 are Not Connected (internally) and should be left floating.
2. Pads D1, E1 & G1 are Reserved for Future Use and should be left floating.
3. For GL-S, pad F7 is Reserved for Future Use and should be pulled high.
4. For GL-S, pad G7 is DQ15 (only).
5. All active address inputs for a given density device must be controlled, e.g. A[25:0] for x16 S29GL512S. Unused higher order address
inputs can be controlled or left floating. Unused data I/O should be pulled low.
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Figure 3.2 GL 56-TSOP Signal Pin Out
Notes:
1. Pins -28 & -30 are Reserved for Future Use and should be left floating.
2. For GL-S, pin -51 is DQ15 (only).
3. For GL-S, pin -53 is Reserved for Future Use and should be pulled high.
4. All active address inputs for a given density device must be controlled, e.g. A[25:0] for x16 S29GL512S. Unused higher order address
inputs can be controlled or left floating. Unused data I/O should be pulled low.
3.8
Asynchronous Mode
The S29GL-R supports asynchronous single and page read modes, consistent with the existing S29GL-P.
The S29GL-S supports asynchronous single and page read modes, consistent with the existing S29GL-P.
Software can be modified to take advantage of the wider read page buffer on the S29GL-S by querying the
CFI programming buffer depth register at address 98h (x8 address bus reference) or 4Ch (x16 address bus
reference) and configuring software to perform additional page read cycles.
3.9
OTP Area
The S29GL-R supports two 256 byte one time programmable Secure Silicon areas, double the available OTP
space on the existing S29GL-P.
The S29GL-S supports two 512 byte one time programmable Secure Silicon areas, quadruple the available
OTP space on the existing S29GL-P.
3.10
Write Protection
The S29GL-R supports Advanced Sector Protection (ASP) program and erase protection via single voltage
password, non-volatile and volatile control, consistent with the existing S29GL-P.
The S29GL-S supports Advanced Sector Protection (ASP) program and erase protection via single voltage
password, non-volatile and volatile control, consistent with the existing S29GL-P.
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A pplication
Note
Details of ASP program and erase protection implementations can be found in the S29GL-P, S29GL-R and
S29GL-S data sheets.
3.11
Read Protection
The S29GL-R supports Advanced Sector Protection (ASP) read protection via a single voltage password
mechanism, unlike the existing S29GL-P.
The S29GL-S supports Advanced Sector Protection (ASP) read protection via a single voltage password
mechanism, unlike the existing S29GL-P.
Details of ASP read protection implementation can be found in the S29GL-R and S29GL-S data sheets.
3.12
Unlock Bypass
The S29GL-R does not support Unlock Bypass mode programming, unlike the existing S29GL-P.
The S29GL-S does not support Unlock Bypass mode programming, unlike the existing S29GL-P.
Unlock Bypass mode programming is a legacy feature used to decrease the command overhead by 50%
when performing single byte or word programming using the Single byte or word programming command.
Applications using high density GL devices rely on multi-word write buffer programming to maximize
programming throughput. Write buffer programming supports single byte/word programming and has
inherently low effective command overhead. Since Unlock Bypass mode programming is rarely used in GL
Flash applications, removal of this legacy feature should not prevent migration to 65 nm GL devices on
existing designs. Those applications that do support Unlock Bypass programming will require modification to
use standard single byte/word programming or write buffer programming commands.
3.13
Multi-sector Erase
The S29GL-R does not support multi-sector erase, unlike the existing S29GL-P.
The S29GL-S does not support multi-sector erase, unlike the existing S29GL-P.
Multi-sector erase is a legacy feature that allowed spooling of multiple sector erase operations within one
command string to minimize command overhead. This is a rarely used function so removal of this feature
should not prevent migration to 65 nm GL devices on existing designs. Those applications that do support
multi-sector erase will require modification to limit sector erase operations to individual sectors only.
3.14
Data Polling
The S29GL-R supports data polling to determine the status of embedded programming and erase operations,
consistent with the existing S29GL-P.
The S29GL-S supports data polling to determine the status of embedded programming and erase operations,
consistent with the existing S29GL-P.
Data polling will likely not be supported on future smaller process geometry MirrorBit GL and/or MirrorBit
Eclipse GL families. Status Register reads will be required to determine the status of embedded program and
erase operations.
3.15
Status Register
The S29GL-R will support Status Register reads to determine embedded program and erase operation
status, unlike the existing S29GL-P.
The S29GL-S will support Status Register reads to determine embedded program and erase operation
status, unlike the existing S29GL-P.
The status of program and erase operations is provided by a single 16-bit status register. The Status Register
Read command is written followed by one read access of the status register information. The contents of the
status register overlays the sector selected by the Status Register Read command and this overlay is in effect
for one read access only. Subsequent read access to the sector selected by the Status Register Read
command will return array data, as will reads to any address outside of the targeted sector.
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Unlike legacy data polling, use of the status register does not require comparison of sequential polling read
values or to targeted program data to determine embedded algorithm status. The lower byte of the status
register contains bits related to the results - success or failure - of the most recently completed. A Clear
Status Register command is provided to reset the last completed embedded operation portion of the status
register. The upper byte of the status register contains bits that indicate dynamic embedded operation
progress relevant during factory troubleshooting. It is recommended that user software enable capture of the
entire status word to enable failure diagnosis.
Status Register usage is optional and its presence will not inhibit migration to 65 nm MirrorBit GL or MirrorBit
Eclipse GL devices on existing designs. Spansion recommends software modification to take advantage of
this feature by querying the Lower Software Bits at offset xCh in Autoselect mode. If bit 0 is set, Status
Register functionality is supported.
Details of the Status Register implementation can be found in the S29GL-R and S29GL-S data sheets. The
Status Register bit definitions are provided in Table 3.3. Status determination methodology using the Status
Register is illustrated in the flow diagram in Figure 3.3. Provided below is a C source code excerpt from
Spansion's Low Level Driver software (LLD rev 7.2.0) that illustrates how to augment existing drivers to also
support Status Register usage. The Status Register provided a simplified and robust method for status
determination and reduces code required for status determination by ~70%.
Figure 3.3 Status Register Usage Flow Diagram
Write
Status Read
Command
Embedded
Operation
Started
Actively
Programming
or Erasing
Yes
D7 = 0 ?
Read
No
No
Operation =
Erase Suspend?
Yes
Erase in
Suspension
Yes
Yes
D6 = 0 ?
No
Operation =
Program Suspend?
Yes
Yes
D5 = 0 ?
No Erase in
Suspension
No
Operation =
Program?
Yes
Yes
No
No
Operation =
Erase?
D4 = 0 ?
No
Erase
Successful
Program
Failed
Erase
Failed
Yes
D2 = 0 ?
Program
Successful
No
No Program
In Suspension
Program in
Suspension
Yes
DQ2 = 0?
No
Sector Not
Locked
Sector
Locked
Error
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9
A pplication
Note
Table 3.3 Status Register Definition
3.15.1
SR Bit
Name
Validity
At Reset
“1”
“0”
DQ15:8
Reserved
n/a
n/a
n/a
n/a
Active program or
erase operation
DQ7
Device Ready Bit
Always valid
“1”
No active
embedded
operation
DQ6
Erase Suspend
Status Bit
DQ7 = “1”
“0”
Erase in
suspension
No erase in
suspension
DQ5
Erase Status Bit
DQ7 = “1”
“0”
Erase failed
Erase successful
DQ4
Program Status
Bit
DQ7 = “1”
“0”
Program failed
Program
successful
DQ3
Reserved
n/a
n/a
n/a
n/a
DQ2
Program Suspend
Status Bit
DQ7 = “1”
“0”
Program in
suspension
No program in
suspension
DQ1
Sector Lock
Status Bit
DQ7 = “1”
“0”
Sector locked
error
Sector not locked
DQ0
Reserved
n/a
n/a
n/a
n/a
Status Register Read C Source Example from LLD rev 7.2.0
/****************************************************************
*
* wlld_StatusRegReadCmd - Status register read command
*
* This function sends the status register read command before
* actualy read it.
*
* RETURNS: void
*
* ERRNO:
*/
#ifndef REMOVE_LLD_STATUS_REG_READ_CMD
void wlld_StatusRegReadCmd
(
FLASHDATA * base_addr,
/* device base address in system */
ADDRESS offset
/* address offset from base address */
)
{
FLASH_WR(base_addr, (offset & SA_OFFSET_MASK) + LLD_UNLOCK_ADDR1,
NOR_STATUS_REG_READ_CMD);
}
/****************************************************************
*
* lld_StatusGet - Determines Flash Status for GL-R device
*
* Note: This routine implements both (1) read status and check
* toggles (2) use read status command(GL-R device). The
* enable_status_cmd_g flag switch between these two status get
* methods. When calling this function, the WriteBufferProgramming
* flag needs to be set to 1 if the caller wants to check DQ1 for
* WriteBuffer abort. Then the flag needs to be set back to 0. See
* lld_poll for example of how to use the WriteBufferProgramming
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* flag.
*
* RETURNS: DEVSTATUS
*
*/
#define DQ1_MASK
(0x02
#define DQ2_MASK
(0x04
#define DQ5_MASK
(0x20
#define DQ6_MASK
(0x40
*
*
*
*
No t e
LLD_DEV_MULTIPLIER)
LLD_DEV_MULTIPLIER)
LLD_DEV_MULTIPLIER)
LLD_DEV_MULTIPLIER)
/*
/*
/*
/*
DQ1
DQ2
DQ5
DQ6
mask
mask
mask
mask
for
for
for
for
all
all
all
all
interleave
interleave
interleave
interleave
devices
devices
devices
devices
*/
*/
*/
*/
#define DQ6_TGL_DQ1_MASK (dq6_toggles >> 5) /* Mask for DQ1 when device DQ6 toggling */
#define DQ6_TGL_DQ5_MASK (dq6_toggles >> 1) /* Mask for DQ5 when device DQ6 toggling */
DEVSTATUS lld_StatusGet
(
FLASHDATA * base_addr,
ADDRESS
offset
)
{
FLASHDATA
FLASHDATA
FLASHDATA
FLASHDATA
/* device base address in system */
/* address offset from base address */
dq6_toggles;
status_read_1;
status_read_2;
status_read_3;
if( enable_status_cmd_g == 0 )
/* Do not use Read Status */
/* Command */
{
status_read_1 = FLASH_RD(base_addr, offset);
status_read_2 = FLASH_RD(base_addr, offset);
status_read_3 = FLASH_RD(base_addr, offset);
/* Any DQ6 toggles */
dq6_toggles = ((status_read_1 ^ status_read_2) &
Toggles between read1 and read2 */
(status_read_2 ^ status_read_3) &
/* Toggles between read2 and read3 */
DQ6_MASK );
/* Check for DQ6 only */
/*
if (dq6_toggles)
{
/* Checking WriteBuffer Abort condition: Check for all devices */
/* that have DQ6 toggling also have Write Buffer Abort DQ1 set */
if (WriteBufferProgramming &&
((DQ6_TGL_DQ1_MASK & status_read_1) == DQ6_TGL_DQ1_MASK) )
return DEV_WRITE_BUFFER_ABORT;
/* Checking Timeout condition: Check for all devices that have */
/* DQ6 toggling also have Time Out DQ5 set. */
if ((DQ6_TGL_DQ5_MASK & status_read_1) == DQ6_TGL_DQ5_MASK )
return DEV_EXCEEDED_TIME_LIMITS;
/* No timeout, no WB error */
return DEV_BUSY;
}
else
{
/* no DQ6 toggles on all devices */
/* Checking Erase Suspend condition */
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status_read_1 = FLASH_RD(base_addr, offset);
status_read_2 = FLASH_RD(base_addr, offset);
/* Checking Erase Suspend condition */
if ( ((status_read_1 ^ status_read_2) & DQ2_MASK) == 0)
return DEV_NOT_BUSY;
/* All devices DQ2 not toggling */
if (((status_read_1 ^ status_read_2) & DQ2_MASK) == DQ2_MASK)
return DEV_SUSPEND;
/* All devices DQ2 toggling */
else
return DEV_BUSY;
/* Wait for all devices DQ2 toggling */
}
}
else
{
/*............................................................*/
/* Use Status Register Read command to read the status
*/
/* register. This is for GL-R/S devices only
*/
/*............................................................*/
#ifdef STATUS_REG
volatile FLASHDATA status_reg;
wlld_StatusRegReadCmd( base_addr, offset );
Issue status register read command */
status_reg = FLASH_RD(base_addr, offset);
/* read the status register */
/*
if ( (status_reg & DEV_RDY_MASK) != DEV_RDY_MASK
) /* Are all devices done bit 7 is
1 */
return DEV_BUSY ;
if ( status_reg & DEV_ERASE_MASK )
return DEV_ERASE_ERROR;
/* Any erase error */
if ( status_reg & DEV_PROGRAM_MASK )/* Any program error */
return DEV_PROGRAM_ERROR;
if ( status_reg & DEV_SEC_LOCK_MASK )/* Any sector lock error */
return DEV_SECTOR_LOCK;
return DEV_NOT_BUSY ;
#endif
return DEV_STATUS_UNKNOWN;
/* should never get here */
}
}
4. Power On Reset Timing
The use of a static micro controller to control internal mode transitions within 65 nm GL Flash requires
asymmetric reset timing. At power on, the flash requires more time in reset to self configure than it does
during a warm reset. Table 4.1 and Figure 4.1 detail the power on reset timing requirements for existing and
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No t e
future GL Flash Table 4.2 and Figure 4.2 detail the warm reset timing requirements for existing and future GL
Flash.
Table 4.1 Power On Reset Timing Requirements
Parameter
Description
GL-N
GL-P
GL-R
GL-S
tVCS
VCC Setup Time to first access (min)
50 µs
35 µs
300 µs
300 µs
tVIOS
VIO Setup Time to first access (min)
35 µs
35 µs
300 µs
300 µs
tRPH
RESET# Low to CE# Low (min)
550 ns
35 µs
35 µs
35 µs
tRP
RESET# Low to RESET# High (min)
500 ns
35 µs
200 ns
200 ns
tRH
RESET# High to CE# Low (min)
50 ns
200 ns
200 ns
200 ns
Note:
For GL-R & GL-S, tRP + tRH must be not be less than tRPH
Figure 4.1 Power-Up Reset Timing
VCC
tVIOS
tVCS
VIO
tRP
RESET#
tRH
tRPH
CE#
Note
The sum of tRP & tRH must be equal to or greater than tRPH
Table 4.2 Warm Reset Timing Requirements
Parameter
Description
GL-N
GL-P
GL-R
GL-S
tRPH
RESET# Low to CE# Low (min)
20 µs*
35 µs
35 µs
35 µs
tRP
RESET# Low to RESET# High (min)
500 ns
35 µs
200 ns
200 ns
tRH
RESET# High to CE# Low (min)
50 ns
200 ns
200 ns
200 ns
Notes:
1. For GL-N, tRP = 20µs during embedded operation and 500ns not during embedded operation.
2. For GL-R & GL-S, tRP + tRH must be not be less than tRPH.
Figure 4.2 Warm Reset Timing
tRP
RESET#
tRH
tRPH
CE#
Note:
The sum of tRP & tRH must be equal to or greater than tRPH
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Note
5. Specification Parameter Comparison
Table 5.1 provides a side by side reference of various AC and DC specification differences between GL
families (less reset timing requirements). All parameters should be reviewed against actual application
implementations to ensure successful migration. Special detail should be placed on review of control signal
relationships during write cycles as well as software suspend & resume timing when evaluating migration to
the S29GL-S family.
Table 5.1 AC & DC Specification Differences
Parameter
Description
GL-N
GL-P
GL-R
GL-S
tACC / tCE
Read Cycle Time (512 Mbit, Full VCC)
100 ns
110 ns
100 ns
90 ns
tPACC
Intra-Page Access Time
25 ns
25 ns
20 ns
15 ns
tOE
OE# to data
25 ns
25 ns
15 ns
15 ns
tDF
Control negate to data high-Z
20 ns
20 ns
15 ns
15 ns
tWC
Write Cycle Time (512 Mbit, Full VCC)
100 ns
110 ns
100 ns
90 ns
tWP
WE# Enable to Disable
35 ns
35 ns
35 ns
25 ns
tWPH
WE# Disable to Enable
30 ns
30 ns
30 ns
20 ns
Async Read
Async Write
tAS
Address Setup to WE# Enable
0 ns
0 ns
0 ns
3.5 ns
tAH
Address Hold from WE# Enable
45 ns
45 ns
45 ns
3 ns
tCS
CE# Setup to WE# Enable
0 ns
0 ns
0 ns
4 ns
tCH
CE# Hold from WE# Disable
0 ns
0 ns
0 ns
0 ns
tDS
Data Setup to WE# Disable
45 ns
30 ns
45 ns
40 ns
tWEH
OE# Disable to WE# Enable
0 ns
0 ns
0 ns
4 ns
tSR/W
WE# Disable to Address if CE# tied low
0 ns
0 ns
30 ns
0 ns
Suspend Resume
tESL
Erase - Suspend to Resume
0 ns
20 µs
30 µs
20 µs
tERS
Erase - Resume to Suspend
0 ns
0 ns
0 µs
400 µs
tPSL
Program - Suspend to Resume
0 ns
15 µs
30 µs
20 µs
tPRS
Program - Resume to Suspend
0 ns
0 ns
0 µs
30 µs
x16 Async Read (max)
20 MB/s
18 MB/s
20 MB/s
22 MB/s
Throughput
x16 Page Read (max)
58 MB/s
56 MB/s
67 MB/s
102 MB/s
Programming (typical)
133 KB/s
133 KB/s
133 KB/s
2 MB/s
Erase (typical)
256 KB/s
256 KB/s
256 KB/s
1.3 MB/s
ICC1
Active VCC Read (5 MHz, max)
50 mA
55 mA
45 mA
55 mA
ICC4
Active Program or Erase (max)
90 mA
90 mA
90 mA
80 mA
Power Usage
ICC5/6
Reset Current (max)
5 µA
500 µA
500 µA
500 µA
IACC
Accelerate Prgm Current_VCC (max)
90 mA
80 mA
90 mA
90 mA
IACC
Accelerate Prgm Current_ACC (max)
20 mA
20 mA
30 mA
30 mA
VHH
Acclerated Programming Voltage (max)
12.5 V
12.5 V
9.5 V
9.5 V
Note:
The GL-R specific tSR/W timing parameter only applies in the usage case where CE# is maintained low between a write cycle and a
subsequent read cycle. In this case, an Address change must be delayed for 30 ns minimum from the rising edge of WE# or the data output
on the subsequent read cycle may be incorrect.
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6. Revision History
Section
Description
Revision 01 (February 14, 2008)
Initial Release
Revision 02 (May 22, 2008)
Updated Table 2.1; Added Sections 3.2 and 3.3
Revision 03 (December 18, 2008)
Removed sections Automatic Cache Line and Bit Field Programming; Updated Packaging section;
Updated Table 5.1
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A pplication
Note
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2008 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, ORNAND2™,
HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for
informational purposes only and may be trademarks of their respective owners.
16
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December 18, 2008