56Gb/s Serial – Why, What, When March 12, 2014

March 12, 2014
56Gb/s Serial – Why, What, When
56G Electrical Interfaces; the Ecosystem
• See the OIF’s Next Generation Interconnect Framework White
Paper, OIF-FD-Client-400G/1T-01.0
OIF 56G Started and Anticipated Projects
Projects started in 2012:
•
USR: 3D Chip Stacks
or multichip module
•
XSR: 2.5D Chip-to-chip
or pkg to pkg
•
VSR: Chip-to-module
CEI-56G-USR
3D Chip Stack (1 cm)
CEI-56G-XSR
Chip
Chip
Optics
Optics
Chip-to-Optics
Chip
CEI-56G-MR
CEI-56G-VSR
2.5D Chip-to-Chip over substrate (5 cm)
Chip
Chip-to-Chip
Chip
Chip
Chip
Chip
Backplane or
Passive Copper Cable
Anticipated
Low loss Backplane
Projects started in 2014:
•
MR: Chip-to-chip
Anticipated Project
Starts:
•
LR: Backplane
Challenges / Decision Points
• Electrical Reaches or Optical architecture?
– 1 cm to 1 m
– Is there an advantage to having the same
solution for all reaches?
• Example, NRZ for all reaches?
– Bandwidth density, must be significantly
better than 16x25Gb/s channels
– 8x50G or 10x40G?
– 4x100G?
– Channel assumptions (improvements)
• Balancing NRZ channels with higher order
modulation power/complexity
CDFP: 12 Total Ports @ 400G each,
Yields 4.8Tb/s throughput
Optical Architectures?
• Optical IO
• Optical backplane
• Electrical chip to
chip
• Avoid forklift
upgrades
• Higher aggregate
bandwidth/density
page 5
Challenges / Decision Points
• Electrical Reaches or Optical architecture?
– 1 cm to 1 m
– Is there an advantage to having the same
solution for all reaches?
• Example, NRZ for all reaches?
– Bandwidth density, must be significantly
better than 16x25Gb/s channels
– 8x50G or 10x40G?
– 4x100G?
– Channel assumptions (improvements)
• Balancing NRZ channels with higher order
modulation power/complexity
Improved Electrical Channels
• Replace the PCB with low loss media
Cable attachment
ASIC
TE and LSI paper at DesignCon showed
that cabled backplane shows promise at
56Gb/s
page 7
Panelists
• Ed Frlan, Semtech
• Brian Holden, Kandou
• Tom Palkert, Luxtera
page 8