designcon 2012

Technical Papers
Electrical Design and Modeling Challenges for 3D System Integration
Madhavan Swaminathan
Power Grid Parasitic Impact on System Level Power Delivery
Thao Pham, Vishram Pandit, Almario F. Delos Angeles
Vertical Noise Coupling from On-chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3DIC
Kyoungchoul Koo, Myunghoi Kim, Joungho Kim
A New Technique for Efficient Side Channel Security Testing
Luke Teyssier
Full System Channel Co-optimization for 28Gb/s SerDes FPGA Applications with Stacked Silicon
Interconnect Technology
Namhoon Kim, Zhaoyin Daniel Wu, Jack Carrel, Joong-ho Kim, Paul Wu
S-Parameter Modeling and Simulation for Signal Integrity Analysis
Amir H. Motamedi
Channel Eye Diagram Generation, Pre-Hardware
Donald Tellan
A Practical and Reliable Methodology for Hierarchical Signal Planning
Bob Eisenstadt
Analysis of HighStability Controlled Oscillators for LowBandwidth PLLs
Sassan Tabatabaei
Revolutionary Embedded Silicon MEMS Resonators Obsoletes Bulky External 32 kHz Crystals in the
System
Markus Lutz
An Improved Co-Simulation Approach to Rapidly Prototype, Verify, and Implement Dynamic
FPGA-based Embedded Control Systems
Muris Mujagic, Oleg Stepanov, Brian MacCleery
FPGA Based Implementation of Floating Point Matrix Inversion
Michael Parker
What, If Anything, In SystemVerilog Will Help Me With FPGA-based Designs?
Stuart Sutherland
System Performance as a Function of Common Mode Metrics
Michael Rowlands, Pravin Patel, Patrick Casher
Optical Technologies for Off-Chip and On-Chip Interconnects
Philipp Schindler, Halmo Fischer, Hansjorg Haisch, Nicole Lindenmann, Luca Alloatti, Robert Palmer,
Dietmar
Korn, David Hillerkuss, Rene Schmogrow, Andreas Gerster, Wolfgang Freude, Juerg Leuthold, Christian
Koos
Performance Challenge and Opportunity of TSV Silicon Interposer in 3D System
Hong Shi, Zhe Li, Yuan Li, Xiaohong Jiang, John Xie, Arif Rahman, Karthik Chandrasekara
Design and Characterization of the Power Supply System for a High Speed 1600 Mbps DDR3
Interface in Wirebond Package
Ralf Schmitt, Hai Lan
Effects of Microstrip/Strip line Dependent BGA Distribution and DECAP Optimizations on the Noise
Performance of IC Package Systems
Om P. Mandhana, Jon Burnett, Sam Chitwood
Comprehensive Analysis of Flexible Circuit Materials Performance in Frequency and Time Domains
Glenn Oliver, Jim Nadolny, Deepukumar Nair
Understanding and Mitigation of Fiber Weave Effects in Striplines
Martin Schauer, Gerardo Romo Luevano, Reydezel Torres-Torres, Chudy Nwachukwu, Seung-Won Baek
Understanding and Balancing the Trade-offs Between Power Integrity and Signal Integrity Concerns
for Interfacing to Multi-lane, >25Gb/s Devices
Thomas P. Warwick, Albert Seier
Measurement And Modeling Of The Effect Of Laminate Thermal Conductivity And Dielectric Loss
On The Temperature Rise Of HF Transmission Lines And Active Devices
Allen F. Horn III, Chris Caisse, James R. Willhite
EM Modeling of Board Surface Finish Effect on High-Speed PCB Performance
Yuming Tao, Frank H. Scharf Time-domain
Electrical Design Checker for Print Circuit Board Design Layout
Kai Xiao, Xiaoning Ye, Yanjie Zhu, Wenjing Kang, Thonas Su, Yuan-Liang Li
Embedded DC Blocking Capacitors in Connectors - Study of Impacts on PCB Design and High Speed
Serial Link Performance
Jeremy Buan, Toshi Takada, Fernando Cheng, Jonathan Weng, Clement Luk, Tats Arai, Ching-Chao
Huang, Douglas Yanagawa, Phillip I-Chyau Li, Yaochao Yang
Design, Analysis, and Characterization of Tri-Modal 12.8 Gbps Single-Ended and 20 Gbps
Differential Memory Interfaces
Wendem T. Beyene, Amir Amirkhany, Chris Madden, Kambiz Kaviani, Ralf Schmitt, Hai Lan, Keisuke Saito,
Ling
Yang, Dave Secker, Deborah Dressler
A Zero Sum Signaling Method for High Speed, Dense Parallel Bus Communications
Chad M. Smutzer, Robert W. Techentin, Michael J. Degerstrom, Barry K. Gilbert, Erik S. Daniel
Complete Analysis and Design of Power Integrity for Advanced Memory Technology (DDR4)
Brian Wang, Vishram S. Pandit
Low Cost/Ultra High Density and High Performance Wirebond Package Design and SI/PI Analysis
for FPGA with Embedded Dual Core ARM CPU and Dedicated DDR3 Memory Channel
Namhoon Kim, Joong-Ho Kim, Chris Wyland, Paul Wu
State of the Art Multi-Gigabit Printed Flex Cable Alternative to Traditional Coax and Wire Based
Cabling
Jamal S. Izadian, Heidi Barnes
Algorithmic Memory Brings an Order of Magnitude Performance Increase to Next Generation SoC
Memories
Sundar Iyer, Da Chuang
Next Generation Embedded Memory Performance
Sundar Iyer
Extending GDDR5 Data Rate Beyond 6 Gbps
Sanku Mukherjee, Dan Oh, Arun Vaidyanath, Deborah Dressler, Dave Secker, Arul Sendhil
Rigorous Breakdown of Crosstalk in Single-Ended High-Speed Memory Interface
Daehyun Chung, Sunil Sudhakaran, Venkat Satagopan, Seunghyun Hwang
Salz SNR Modification for High Speed Serial Link System Performance Estimation
Henry Wong, Xiaoqing Dong, Francois Tremblay, Geoffrey Zhang
AMI Models: How to tell a Peach from a Lemon
Michael Steinberger, Todd Westerhoff
A 12.5-Gbps TX FFE with Floating Taps in 28-nm CMOS
Weichi Ding, Mengchi Liu, Sergey Shumarayev, Mike Peng Li
Backplane Channel Design Optimization: Recasting a 3Gb/s Link to Operate at 25Gb/s and Above
Xiaoxiong Gu, Young H. Kwark, Dazhao Liu, Yaojiang Zhang, Jun Fan, Renato Rimolo-Donadio, Sebastian
Muller, Christian Schuster, Francesco De Paulis
A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane
Channels
Adam Healey, Chad Morgan
Building on the OIF CEI-28GVSR Implementation Agreement to Address Several New Applications
Edward Frlan, David Brown, Francois Tremblay
Design Optimization for Minimal Crosstalk in Differential Interconnect
Beomtaek Lee, Xiaoning Ye, Raul Enriquez, Kai Xiao, Ted Ballou, Jimmy A. Johansson
Efficient End-to-end Simulations of 25G Optical Links
Sanjeev Gupta, Fangyi Rao, Jing-tao Liu, Amolak Badesha
Unified Multi-Standard Clocking Implementation for High-Speed SerDes Link of 20-28Gbps
Yikui Jen Dong, Freeman Zhong
Measurement and Analysis of Shielding Effectiveness and Transfer Impedance of High Speed Data
Cables
Joseph C. Diepenbrock, Bruce Archambeault, Samuel Connor
Vias Structural Details and their Effect on System Performance
Roger Dame, Gustavo Blando, Istvan Novak, Jason Miller, Kevin Kinckley
Simulating Large Systems with Thousands of Serial
Donald Telian, Sergio Camerlo, Michael Steinberger, Barry Katz, Walter Katz
Temperature and Moisture Dependence of PCB and Package Traces and the Impact on Signal
Performance
Jason R. Miller, Ying Li, Kevin Hinckley, Gustavo Blando, Bruce Guenin, Istvan Novak, Aykut Dengi, Ashley
Rebelo, Scott McMorrow
Managing Timing Jitter in High-Speed Interface Design
Dan Oh, Ralf Schmitt, Chuck Yuan
The Case of the Closing Eye - De-mystifying the Measurement Complexity
N/A
Power Supply Noise Induced Jitter in a 6.4Gbps/Link Memory Interface System
Hai Lan, Ravi Killipara, Sam Chang, Ling Yang, Lei Luo, Kashinath Prabhu, John Eble, Ralf Schmitt
Characterizing Power Supply Noise and Its Impact on High Speed IO Link Performance
Tao Liang, Vishnuraj V. Gunasekaran, Victor Jesus Zuniga Marquez
Fast, Precise and Broadband Modeling of Induced Clock Jitter by SSN Coupling
Yujeong Shim, Junwoo Lee, Joungho Kim
Worst-Case Patterns for High-Speed Simulation and Measurement
Masashi Shimanouchi, Mike Peng Li, Daniel Chow
Accurate Analytical Model of Bounded Uncorrelated Jitter and Noise Improves the Accuracy of
Crosstalk Impaired Link Evaluation: Theory, Validation, Practical Results
Maria Agoston, Pavel Zivny
Robust Method for Addressing 12 Gbps Interoperability for High-Loss and Crosstalk-Aggressed
Channels
Al Neves, Alan Blankman, Eric Bogatin, George Noh, James Bell, Martin Spadaro
Non-Linear Time-Invariant Link Model Based on Separation of Random and Correlated Jitter and
Noise by combine Response and DDJ Extraction
Maria Agoston, Vladimir Dmitriev-Zdorov, Pavel Zivny
TX Back Channel Adaptation Algorithm And Protocol Emulation With Application To PCIe, SAS,
FC, And 10GBASE-KR
Mohammad S. Mobin, Amaresh Malipatil, Pervez Aziz, Adam Healey
Mostly Digital SerDes: A Comprehensive Low Power Receiver Architecture
Erik Chmelar, Choshu Ito
Error Signature Analysis: A Receiver Architecture for Data Communication
Erik Chmelar
Correlation Methodology for Generating IBIS-AMI Receiver Models for Multi-Gigabit SerDes
Devices
Ryan Coutts, Antonis Orphanou, Daniel Lin, Manuel Luschas
Enhanced Equalization and Forward Correction Coding Technologies for 25+Gb/s Serial Link
System
Cathy Liu, Pervez Aziz, Adam Healey
Design Methodology for Optimized Power Distribution Networks using PDN Resonances
Woopoung Kim, Angel Park, Xiaonan Zhang
Experimental Optimization of Decoupling Capacitors in FPGA Designs by On-Die Measurements of
Power Distribution Impedance Frequency Profile
Cosmin Iorga
Design Methodology for Optimized Power Distribution Networks using PDN Resonances
Woopoung Kim, Angel Park, Xiaonan Zhang
PDN Resonance Calculator for Chip, Package and Board
Larry D. Smith, Mayra Sarmiento, Yuri Tretiakov, Shishuang Sun, Zhe Li, Sunitha Chandra
Analysis and Characterization of Supply Noise and Its Jitter Impact in a 12.8Gbps Single-Ended
Signaling Memory Interface
Hai Lan, Minghui Han, Wendem Beyene, Chris Madden, Chuck Yuan, Ralf Schmitt
PDN-Noise-to-Jitter Transfer in High-Speed Transceivers
Shishuang Sun, Kaiyu Ren, Weichi Ding, Daniel Chow, Tim Hoang, Sergey Shumarayev, Ken Daxer, Mike
Peng Li
Are Power Planes Necessary for High Speed Signaling?
Suzanne L. Huh, Madhavan Swaminathan
Plane Bounce in High-Speed Single-Ended Signaling I/O Interfaces
Dan Oh
On-chip Jitter and System Power Integrity
Iliya Zamek Experimental Optimization of Decoupling Capacitors in FPGA Designs by On-Die Measurement
of
Power Distribution Impedance Frequency Profile
Cosmin Iorga
Investigation of High Speed Serdes Induced EMI and Its Suppressing with Novel Heatsink Design
Zhenggang Cheng, Mike Sapozhnikov, Diaco Davari, Amit Agrawal, Jeffrey Evans
Miniaturization of Common Mode Filter Based on EBG Patch Resonance
Francesco De Paulis, Bruce Archambeault, Muhammet Hilmi Nisanci, Sam Connor, Antonio Orlandi
System-Level EMI Bounding Calculations Using Equivalent Sources and Genetic Algorithms
Michael Cracraft, Bruce Archambeault, Samuel Connor
High-Speed EMC/EMI Correlation Study- 3D EM Model versus Anechoic Chamber Test
Peerouz Amleshi, Shahriar Mokhtarzak, Xin Wu, Martin Schauer
Secret Cryptographic Key Extraction from Mobile Devices using RF EM Emissions
Gary Kenworthy
Method for Troubleshooting Power Integrity Problems in Programmable Logic Device Electronic
Systems by Embedded Measurement of Power Distribution Impedance
Cosmin Iorga
De-Embedding in High Speed Design
Don DeGroot, David Dunham, Kaviyesh Doshi, Peter J. Pupalaikis
High-confidence S-parameter Measurement Methodologies for 15-28 Gbps
N/A
Probability Distributions of Random Errors in Frequency-Domain Measurements
Sedig Agili, Aldo Morales, Mike Resso
Signal Integrity Test Solution for High-speed Interconnects
Hiroshi Goto
Methodologies and Measurement Comparisons of High-Speed Links Using On-Chip and On-Bench
Instrumentations
Wendem T. Beyene, Chris Madden
Improvements In Time-Domain TRL Accuracy For Transmission Measurements
Victor Khilkevich, Brice Achkir, James L. Drewniak
The Effects of a Linear Equalizer on Uncorrelated Jitter and Noise and Implications for Test
Mike Li, Masashi Shimanouchi
Linguistics of Connector Model Quality
Dennis Miller, Michael Brownell, Heather Monigan
Mixed-Mode De-embedding Methodology Using Multiline Calibration Structures
Chung-Chi Huang
A Practical Approach for Using Circuit Board Qualification Test Results to Accurately Simulate High
Speed Serial Link Performance
Alan Blankman, Eric Bogatin, Don DeGroot
Advances in ATE Fixture Performance and Socket Characterization for Multi-Gigabit Applications
Heidi Barnes, Jose Moreira, Mike Resso, Robert Schaefer
Modeling And Optimization Of Electronic Packaging Structures For Signal And Power Integrity
Antonio Ciccomancini Scogna, A. Ege Engin, Ivan Ndip
A Causal Huray Model for Surface Roughness
J. Eric Bracken
Signal Transition Structure Optimization for 16 Gbps SFP Cage and PCB Interface
Antonio Ciccomancini Scogna, Jianmin Zhang, Kelvin Qiu, Rick Brooks, Jane Lim
Practical Methodology For Analyzing The Effect Of Conductor Roughness On Signal Losses And
Dispersion In Interconnects
Yuriy Shlepnev, Chudy Nwachukwu
Connector Models – Are They Any Good?
Jim Nadolny, Leon Wu
Characterizations of Real Asymmetric Fixtures using a Two-gate Approach
Joel Dunsmore, Ning Cheng, Robert Schaefer
The Relationship Between Discrete-Frequency S-parameters and Continuous-Frequency Responses
Peter J. Pupalaikis
Fast and Optimal Algorithms for Enforcing Reciprocity, Passivity and Causality in S-parameters
Kaviyesh Doshi, Anirudh Sureka, Peter J. Pupalaikis
Dynamic Characterization of DC-DC Converters
Istvan Novak, Kendrick Barry Williams, Chris Young, Brandon Howell, Jason R. Miller, Gustavo Blando
Designing for the Future
Ilan Spillnger
Enhanced Equalization and Forward Correction Coding Technologies for 25+Gb/s Serial Link
System
Cathy Ye Liu, Pervez Aziz, Adam Healey
Heterogeneous Systems Architecture
Joe Macri
The Relationship Between Discrete-Frequency S-parameters and Continuous-Frequency
Responses
Peter J. Pupalaikis
HP Labs and Photonics Technologies
Prith Banerjee