STMicroelectronics

STMicroelectronics
Standard Technology offers at CMP in 2015
Deep Sub‐Micron, SOI and SiGe Processes
http://cmp.imag.fr
CMP Annual users meeting, 5 February 2015, PARIS
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CMP Process Portfolio From ST
STMicroelectronics Technology offers at CMP :
160nm BCD8SP
130nm CMOS : HCMOS9GP
130nm SOI : H9SOI‐FEM
130nm SiGe : BICMOS9MW
1994 at CMP
130nm HV‐CMOS : HCMOS9A
65nm CMOS : CMOS065LPGP
28nm FDSOI : 28FDSOI
2015 at CMP
ST 0.25µ
AMS 0.35µ
18k gates/mm2 35k gates/mm2
AMS 0.6µ
3k gates/mm2
AMS 0.8µ
1.2k gates/mm2
ST 0.18µ
80k gates/mm2
ST 130nm
180k gates/mm2
ST 90nm
400k gates/mm2
ST 65nm
800k gates/mm2
ST 40nm
ST 28nm
1600k gates/mm2 3M gates/mm2
1/1000 x gate delay (from ns to ps)
1/1000 x power consumption (from µW/MHz to pW/MHz)
1300 x density integration
CMP Annual users meeting, 5 February 2015, PARIS
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Max Frequency by Technology Node
Frequency (GHz)
30
Ring Oscillator :
 Using minimum transistors size
 With no parasitics.
24
25
20
15
15
9
10
5
7
3,5
0
Tech. Node
0.35um
0.18um 130nm
65nm
CMP Annual users meeting, 5 February 2015, PARIS
28nm
FDSOI
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Deep Sub‐micro 130nm CMOS
CMOS 130nm HCMOS9GP : General Purpose :
 130nm mixed A/D/RF CMOS SLP/6LM (triple Well)
 Gate length (130nm drawn).
 6 Cu metal layers.  Power supply: 1.2 V
 Multiple Vt transistor offering (Low Leakage, High Speed)  Threshold voltages : VTN = 500/380 mV, VTP = 480/390 mV
6 levels Cu Metal (Cross Section View)
Courtesy STMicroelectronics
 Memories SPRAM/ DPRAM / ROM available free of charge on request
4 MPW runs organised in 2015 : 23rd February, 1st June, 1st September, 16th November
Starting Price : 2200€/mm² for 25 samples
Turnaround : 16 weeks
255 Centers received the design rules and design kits.
20 circuits manufactured in 2014 (9 circuits in 2013)
Applications : General purpose Analog/Digital/ RF applications
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SiGe : 130nm CMOS
CMOS 130nm BiCMOS9MW : MilimeterWave process
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BICMOS9MW technology is using 0.13μm HCMOS9GP as base process.
Gate length (130nm drawn).
SiGe‐C bipolar transistor (fT around 230GHz) 6 Cu metal layers. Thin lower metal layers and Thick upper metal layers.
 CMOS devices for 1.2V applications. 2.5V Capable I/O's.
 Damascene Copper for metal 1 to last metal.
 High performance NPN bipolar transistor. Medium voltage NPN bipolar transistor.
 Memories SPRAM available free of charge on request
4 MPW runs organised in 2015 : 23rd February, 1st June, 1st September, 16th November
Starting Price : 2900€/mm² for 25 samples
Turnaround : 16 weeks
60 Centers received the design rules and design kits.
12 circuits manufactured in 2014 (16 circuits in 2013)
Applications : Millimeter‐Wave applications (frequencies up to 77GHz for automotive radars), WLAN, Optical communications systems driving data rates up to 80Gbits/s.5
Deep Sub‐micro 130nm CMOS
CMOS 130nm HCMOS9A : Mixed Digital / Analog / Energy Management :
 130nm mixed A/D/RF CMOS SLP/4LM (triple Well)
 Gate length (130nm drawn).
 4 Cu metal layers. Thick M4
 Low k inter‐level dielectric Cross section view - Bipolar HV transistor
Power Management.
 Operating voltages : 1V2 GO1, 4V8 for GO2, 20V for HV with DGO option.
 Single Gate Oxide option also qualified : No GO1 1V2 CMOS
 Specific Devices : N&P 20V Drift MOS with 85A gate oxide, MIM 5fF capacitor
 Memories SPRAM / ROM available free of charge on request
1 MPW run organised in 2015 : 1st June
Starting Price : 2200€/mm² for 25 samples
Turnaround : 11 weeks
14 Centers received the design rules and design kits.
2 circuits manufactured in 2014 (2 circuits in 2013)
Applications: Implantable devices, Robots/drones, Energy harvesting applications, Sensors wireless, Connected devices/Internet of thing(cell phones), Autonomous systems 6
SOI :Deep Sub‐micro 130nm CMOS
CMOS 130nm H9‐SOI‐FEM : Front‐End Module:
 130nm mixed A/D/RF CMOS SLP/M3TCTA (Double Thick Metal Stack)
 200mm SOI wafers with high resistive (HR) substrate and Trap Rich SOI.
 4 Cu metal layers.  Power supply: 1.2 V
 High Linearity MIM capacitor (2fF/mm2)
 5.0V NLDMOS & PLDMOS
 HCMOS9‐SOI process stopped and replaced by H9SOI‐FEM
• Address a cost‐driven application
• Performances improvement
• Capability to address all FEM applications (Switches, LNA, PA) 2 MPW run organised in 2015 : 11th May and 23rd November
Starting Price : 2200€/mm² for 25 samples
Turnaround : 16 weeks
13 Centers received the design rules and design kits.
2 circuits manufactured in 2014 (6 circuits in 2013)
Applications: Radio receiver/transceiver, Cellular, GPS receivers, Automative keyless systems
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SOI : Deep Sub‐micro 130nm CMOS
CMOS 130nm H9‐SOI‐FEM : Front‐End Module:
 The design kit is provided with fully characterized devices: Switching
Power Application
Low Noise Amplifier
CMP Annual users meeting, 5 February 2015, PARIS
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Deep Sub‐micro 160nm BCD8SP
CMOS 160nm BCD8SP : Bipolar‐CMOS‐DMOS Smart Power:
NEW
 160nm Mixte Analog / Digital Bipolar‐CMOS‐DMOS 4LM  Gate length (160nm drawn).
 4 Cu metal layers. Thick Power M4
 Operating voltages : 1.8V ‐ 5V : Digital & Analog
 10V – 42V : Power MOS
 Analog + Digital + Power & HV on one chip  High Voltage to drive external loads
 Analog block to interface « external world » to the digital systems
 Digital Core for signal processing.
 Memories SPRAM/ DPRAM / ROM available free of charge on request
 Complementary presentation by Mr. Stephane Bach is following.
2 MPW runs organised in 2015 : 15th June and 16th November
Starting Price : 2600€/mm² for 25 samples
Turnaround : 18 weeks
Applications: Hard Disk Drivers, Power Combo, Motor Drivers, DC‐DC converter, Power 9
Management.
Deep Sub‐micro 65nm CMOS
CMOS 65nm CMOS65LPGP : Low Power General Purpose:
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65nm mixed A/D/RF CMOS SLP/6LM (triple Well)
Gate length (65nm drawn).
7 Cu metal layers. Low k inter‐level dielectric (k=2,9)  Power supply: 2.5V, 1.8V, 1.2V, 1V
 Multiple Vt transistor offering A 55 million transistor many-core chip
Courtesey of B.BAAS et al, University of California, Davis
 High Density of integration : 800kgates/mm²
 Memories SPRAM/ DPRAM / ROM available free of charge on request
3 MPW runs organised in 2015 : 16th February, 15th June and 19 October
Starting Price : 6000€/mm² for 25 samples
Turnaround : 16 weeks
310 Centers received the design rules and design kits.
43 circuits manufactured in 2014 (74 circuits in 2013)
Applications: General purpose, Analog/RF capabilities
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FDSOI : Deep Sub‐micro 28nm CMOS
CMOS 28nm FDSOI : Fully depleted Silicon On Insulator:
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28nm mixed A/D/RF CMOS SLP/10LM (triple Well)
Gate length (28nm drawn).
10 Cu metal layers (6 thin + 2 medium + 2 thick). Low leakage (High Density) SRAM using Low Power core oxide
 IO supply voltage : 1,8 V using the IO oxide
 Ultra low k inter‐level dielectric
 Process options :
• MIM : Metal‐Insulator‐Metal capacitance
• OTP (anti‐Fuse) : Capacitance + Drift MOS transistor
4 MPW runs organised in 2015 : 12th January, 4th May, 27th June, 26th October
Starting price : 12000€/mm² for 25 samples
4mm² block price : 36k€ for 25 samples
Turnaround : 16 weeks
140 Centers received the design rules and design kits.
39 circuits manufactured since 2013
Applications: Low power and high performance applications
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FDSOI : Deep Sub‐micro 28nm CMOS
CMOS 28nm FDSOI : Fully depleted Silicon On Insulator:
 Migration from 28nm LP bulk to 28nm FDSOI :
• No disruptive process, no disruptive design
• Seamless migration
• Same layers numbers and names, allow to load a bulk design in a FDSOI design environment
• Common design rules platform
• Bulk devices can be co‐integrated with FDSOI devices
 Standard Cells Libraries :
• CORE cells libraries includes :
o CORE_LL : Low Power LVT (High Density LP / High Speed LP)
o CORE_LR : Low Power RVT (High Density LP / High Speed LP)
o CLOCK (LL and LR) : Buffer cells for clock tree synthesis
o PR : Place and route filler cells
• IO Cells Libraries :
o Digital
o Analog
o Filp‐Chip bumps
o ESD
 Memories SPRAM/ DPRAM / ROM available free of charge on request
CMP Annual users meeting, 5 February 2015, PARIS
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Overview of the submission process for CMP users
Design transfer
Wafers shipment
Foundry
Users
‐ Research Laboratories
‐ Educationnal Universities
‐ Industrial Entities
‐ Data checking (DRC)
‐ Help for corrections (Report)
‐ Data preparation (Sealring/Tiling)
‐ Supports
11 to 16 weeks
Transfer of validated designs
Report for corrections
2 to 3 weeks
Process
0,35 CMOS
130nm CMOS
90nm CMOS
65nm CMOS
40nm CMOS
28nm CMOS
28nm FDSOI
Nbr. Of DRC RuleChecks
400
750
830
1650
3700
4650
5250
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Thank you!
CMP Annual users meeting, 5 February 2015, PARIS
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