1 - Cenidet

Transcription

1 - Cenidet

S.E.P.
S.E.S.
D.G.E.S.T.
CENTRO NACIONAL DE INVESTIGACIÓN
Y DESARROLLO TECNOLÓGICO
cenidet
ANALYSIS AND DESIGN OF THREE PHASE
REFERENCE GENERATORS AND
AC/AC CONVERTERS
TO ENHANCE POWER QUALITY
D I S S E R T A T I O N
submited to obtain the degree of:
Doctor of Science in Electronic Engineering.
P
R
E
S
E
N
T
S
:
JOSE ANTONIO HOYO MONTAÑO
ADVISORS
DR. JORGE HUGO CALLEJA GJUMLICH
DR. JAIME EUGENIO ARAU ROFFIEL
SEPTEMBER 9, 2005
CUERNAVACA, MORELOS, MÉXICO
S.E.P.
S.E.S.
D.G.E.S.T.
CENTRO NACIONAL DE INVESTIGACIÓN
Y DESARROLLO TECNOLÓGICO
cenidet
ANÁLISIS Y DISEÑO DE GENERADORES DE
REFERENCIA TRIFÁSICA Y
CONVERTIDORES CA/CA PARA MEJORAR
LA CALIDAD DE LA ENERGÍA ELÉCTRICA
T
E
S
I
S
PA R A O B T E N E R E L G R A D O D E :
DOCTOR EN CIENCIAS EN INGENIERÍA ELECTRÓNICA
P
R
E
S
E
N
T
A
:
JOSE ANTONIO HOYO MONTAÑO
DIRECTORES DE TESIS
DR. JORGE HUGO CALLEJA GJUMLICH
DR. JAIME EUGENIO ARAU ROFFIEL
9 DE SEPTIEMBRE DE 2005
CUERNAVACA, MORELOS, MÉXICO
cenidet
Centro Nacional de Investigación y
Desarrollo Tecnológico
ACEPTACIÓN DEL TRABAJO DE TESIS DOCTORAL
Cuernavaca, Mor., a 9 de Noviembre de 2005
Dr. Enrique Quintero Mármol Márquez
Jefe del Departamento de Ingeniería Electrónica
P r e s e n t e.
Los abajo firmantes, miembros del Comité Tutorial de la tesis doctoral del alumno José
Antonio Hoyo Montaño, manifiestan que después de haber revisado su trabajo de tesis
titulado “Análisis y Diseño de Generadores de Referencia Trifásica y Convertidotes CA/CA
para Mejorar la Calidad de la Energía Eléctrica”, realizado bajo la dirección del Dr. Jorge
Hugo Calleja Gjumlich y el Dr. Jaime Eugenio Arau Roffiel, el trabajo se ACEPTA para
proceder a su impresión.
ATENTAMENTE
_______________________________
DRA. MARÍA COTOROGEA PFEIFER
CENIDET
_____________________________
DR. LUIS GERARDO VELA VALÉS
CENIDET
______________________________
DR. ABRAHAM CLAUDIO SÁNCHEZ
CENIDET
________________________________
DR. VICTOR M. CÁRDENAS GALINDO
UASLP
___________________
DR. PASAD N. ENJETI
TEXAS A&M UNIVERSITY
JABC*JOH*SSS*mev
INTERIOR INTERNADO PALMIRA S/N, COL, PALMIRA , A.P. 5-164, CP. 62490, CUERNAVACA, MOR. - MÉXICO
TELS. (777) 312 23 14, 318 77 41, FAX (777) 312 24 34
EMAIL [email protected]
cenidet
Centro Nacional de Investigación
y Desarrollo Tecnológico
Sistema Nacional de Institutos Tecnológicos
ANEXO No. 12
AUTORIZACIÓN DE IMPRESIÓN DE TESIS
M11
Cuernavaca, Mor., a 8 de noviembre del 2005
C. M.C. José Antonio Hoyo Montaño
Candidato al grado de Doctor en Ciencias
en Ingeniería Electrónica
Presente.
Después de haber sometido a revisión su trabajo final de tesis titulado: “Análisis y Diseño de
Generadores de Referencia Trifásica y Convertidores CA-CA para Mejorar la Calidad
de la Energía Eléctrica”, y habiendo cumplido con todas las indicaciones que el jurado
revisor de tesis le hizo, le comunico que se le concede la autorización para que proceda con la
impresión de la misma, como requisito para la obtención del grado de Doctor en Ciencias en
este Centro.
Reciba un cordial saludo.
Atentamente
_____________________________________
C. Dr. Enrique Quintero-Mármol Márquez
Jefe del Departamento de Ingeniería Electrónica
c.c.p.
Subdirección Académica
Departamento de Servicios Escolares
Expediente
1
Reglamento del Programa Académico de Doctorado
ACKNOWLEDMENTS
I would like to express my sincere appreciation and gratitude to my two advisors, Dr.
Hugo Calleja and Dr. Jaime Arau, for their guidance, encouragement, support and patience
through the course of this work, but most of all, for their friendship.
I would like to thank my committee members, Dr. Maria Cotorogea, Dr. Abraham
Claudio, Dr. Gerardo Vela, Dr. Víctor Cárdenas and Dr. Prasad Enjeti, for their valuable
suggestions and discussions regarding this work.
I would also want to acknowledge my fellow classmates, the Electronics Engineering
Department faculty and the cenidet staff for providing a friendly and enjoyable working
atmosphere. Special thanks are due to M.Sc. Janeth Alcalá for her help in the building and
initial testing of the power converter prototype (and the endless discussions about why it
burned out). Another special mention must be made to all my teammates of the “Real
Sociedad” for allowing me to share four straight championships with them.
It would be unforgivable not to give a special acknowledgement to the European
Friday Confraternity for sharing many relaxing moments of chat and snack at the heat of a
cold glass of wine. Without them, life in cenidet would be unthinkable and hollow.
In particular, I would like to thank my wife, Leticia, my children, José Carlos and
Laura Leticia, for their love, understanding, support and sacrifice during the course of my
Sc. D. study, specially this last year, without them this would not be completed.
Finally, I would like to thank the National System of Technological Education
Council (CoSNET) for its economical support during my staying at cenidet, and the
Hermosillo Technological Institute for giving me the opportunity to pursue a higher
education.
i
AGRADECIMIENTOS
Quisiera expresar mi más sincero aprecio y gratitud a mis dos directores de tesis, los
doctores Hugo Calleja y Jaime Arau, por su guía, estímulo, apoyo y paciencia durante el
desarrollo de este trabajo, pero sobre todo, por su amistad.
Quisiera agradecer a los miembros de mi comité, Dra. María Cotorgea, Dr. Abraham
Claudio, Dr. Gerardo Vela, Dr. Víctor Cárdenas y Dr. Prasad Enjeti, por sus valiosas
sugerencias y discusiones sobre este trabajo.
Quisiera también agradecer a mis compañeros de studio, a los profesores del
Departamento de Ingeniería Electrónica y al personal de apoyo del cenidet por generar un
ambiente de trabajo amistoso y agradable. Un agradecimiento especial para la M.C. Janeth
Alcalá por su ayuda en la construcción y pruebas iniciales del prototipo del convertidor de
potencia (y las interminables discusiones sobre el por qué se quemaba). Otra mención
especial para todos mis compañeros de la “Real Sociedad” que me permitieron compartir
con ellos cuatro campeonatos en fila.
Sería imperdonable el no dar un agradecimiento especial a la Cofradía del Viernes
Europeo por compartir muchos momentos de relajación compartiendo charlas y bocadillos
al calor de un vaso frío de vino. Sin ellos, la vida en cenidet sería impensable y vacía.
De manera particular, quiero agradecer a mi esposa, Leticia, a mis hijos, José Carlos
y Laura Leticia, por su amor, comprensión, apoyo y sacrificio durante el transcurso de mis
estudios de doctorado, especialmente este último año, sin ellos esto no estaría completo.
Finalmente, quisiera agradecer al Consejo del Sistema Nacional de Educación
Tecnológica (CoSNET) por su apoyo económico durante mi estancia en cenidet, y al
Instituto Tecnológico de Hermosillo por darme la oportunidad de proseguir con estudios de
postgrado.
ii
DEDICATORY
To God, Who always has given me what I need instead of what I want, for His love,
caring and blessings.
To my father José Hoyo y Rubio† (R.I.P.) for his dedication to his family, his
endless interest in learning new things, his love to my mother and myself, and specially for
teaching me the pleasure of teaching.
To my mother Laura Montaño vda. de Hoyo for her caring, guidance, love and
discipline; for teaching me the value of the family and work.
To my wife Leticia, for her strength and support during this period of our life, for
her patience, advices and right words at difficult times, but above all, for her love and
completing my life.
To my children José Carlos and Laura Leticia, for being a reason to achieve this
goal and look for new ones, for their smiles and hugs, but most important for their love.
To my mother-in-law Rogelia Díaz Santana for her love, concern and prayers. To
my extended family, Gussy, Jaqueline, Julianita, Kikito, Juanito, Lili, Roger, Jaime,
Madga, Mauricio, and Raúl, for bearing me.
To cenidet and the Hermosillo Technological Institute, for their support and help
in the course of my studies.
To all my workmates at cenidet, with whom I have grown both as a person an as a
professional, for allowing me to express my ideas and arguments (telling me most of the
time that I was wrong, he, he, he).
iii
DEDICATORIA
A Dios, Quien siempre me ha dado lo que necesito en vez de darme lo que quiero,
por su amor, cuidados y bendiciones.
A mi padre José Hoyo y Rubio† (Q.E.P.D.) por su dedicación a su familia, su eterno
interés por aprender cosas nuevas, su amor a mí madre y a mí, y de manera muy especial por
enseñarme el placer de enseñar.
A mi madre Laura Montaño vda. de Hoyo por su cariño, guía, amor y disciplina;
por enseñarme el valor de la familia y el trabajo.
A mi esposa Leticia, por su fuerza y apoyo durante este periodo de nuestra vida, por
su paciencia, consejos y sus palabras en los momentos difíciles, pero sobre todo, por su
amor y por completar mi vida.
A mis hijos José Carlos y Laura Leticia, por ser una razón para alcanzar esta meta
y buscar otras nuevas, por sus sonrisas y abrazos, por mas importante por su amor.
A mi suegra Rogelia Díaz Santana por su amor, preocupación y rezos. A mi familia
expandida, Gussy, Jaqueline, Julianita, Kikito, Juanito, Lili, Roger, Jaime, Madga,
Mauricio, y Raúl, por soportarme.
A cenidet y el Instituto Tecnológico de Hermosillo, por su apoyo y ayuda durante el
transcurso de mis estudios.
A todos mis compañeros de trabajo en cenidet, con quienes he crecido personal y
profesionalmente, por permitirme expresar mis ideas y argumentos (y diciéndome casi
siempre que estaba equivocado, ja, ja, ja).
iv
TABLE OF CONTENTS
ABSTRACT
.................................................................................................................viii
RESUMEN
.................................................................................................................x
LIST OF FIGURES ..........................................................................................................xii
LIST OF TABLES ............................................................................................................xvii
LIST OF SYMBOLS ........................................................................................................ xix
CHAPTER I.
INTRODUCTION ................................................................................1
I.1. MOTIVATION ............................................................................................................1
I.2. STATE OF THE ART REVIEW .................................................................................2
I.2.1. POWER ELECTRONICS SYSTEMS USED IN SAG COMPENSATION .......2
I.2.2. CONTROL STAGE AND REFERENCE SIGNAL GENERATION IN
THREE PHASE POWER ELECTRONICS SYSTEMS .....................................4
I.2.3. SUMMARY ..........................................................................................................9
I.3. PURPOSE AND GOALS .............................................................................................10
I.4. DISSERTATION OUTLINE .......................................................................................12
CHAPTER II. PROPOSED SINUSOIDAL REFERENCE SIGNAL
GENERATOR ......................................................................................13
II.1. INTRODUCTION ......................................................................................................13
II.2. PROPOSED SINUSOIDAL REFERENCE SIGNAL GENERATOR ......................13
II.3. DIGITAL METHODS FOR SINUSOIDAL SIGNAL GENERATION ....................14
II.3.1. METHODS REVIEW .........................................................................................15
II.3.1.1. ωt (π − ωt) function .................................................................................15
II.3.1.2. Modified Taylor Series Cosine function .................................................16
II.3.1.3. Look-Up Table ........................................................................................17
II.3.1.4. Direct logic synthesis of LUTs ................................................................19
II.3.1.5. Selection of the converter ........................................................................21
II.4. SYNCHRONIC SYSTEMS FOR REFERENCE SIGNAL GENERATORS ............22
II.4.1. ANALOG PLL ....................................................................................................22
II.4.1.1. Phase Detector .........................................................................................23
II.4.1.2. Voltage Controlled Oscillator (VCO) ......................................................25
II.4.1.3. Loop Filter ...............................................................................................25
II.4.1.4. Performance parameters ..........................................................................27
II.4.2. DIGITAL PLL ....................................................................................................27
II.4.3. ALL-DIGITAL PLL ...........................................................................................32
II.4.3.1. Phase detector ..........................................................................................32
II.4.3.2. Digital filter .............................................................................................36
v
II.4.3.3. Digitally controlled oscillator (DCO) ..................................................... 38
II.5. PROPOSED SINUSOIDAL REFERENCE SIGNAL GENERATOR DESIGN ...... 39
II.5.1. PHASE TO AMPLITUDE CONVERTER ........................................................ 39
II.5.2. ALL-DIGITAL PLL ........................................................................................... 44
II.5.3. PHASE SHIFT CORRECTOR .......................................................................... 48
II.5.4. DECISION BLOCK ........................................................................................... 50
II.5.5. CLOCK SIGNALS GENERATOR ................................................................... 56
II.5.6. ANALOG INTERFACE .................................................................................... 57
II.6. SUMMARY ............................................................................................................... 58
CHAPTER III. SINGLE-STAGE AC/AC CONVERTERS ....................................... 61
III.1. INTRODUCTION .................................................................................................... 61
III.2. VOLTAGE AND CURRENT BI-DIRECTIONAL SWITCHES ............................ 61
III.3. SINGLE-PHASE PWM AC/AC CONVERTERS IN CONTINUOUS
CONDUCTION MODE ............................................................................................ 63
III.3.1. BUCK-BOOST CONVERTER ........................................................................ 67
III.3.1.1. Simulation of an AC/AC buck-boost Converter .................................... 72
III.3.2. CUK CONVERTER ......................................................................................... 77
III.3.2.1. Simulation of an AC/AC Cúk converter ................................................ 79
III.4. SINGLE-PHASE PWM AC/AC CONVERTERS IN DISCONTINUOUS
CONDUCTION MODE ........................................................................................... 81
III.4.1. FLYBACK CONVERTER ............................................................................... 81
III.4.1.1. Simulation of an AC/AC flyback converter ........................................... 86
III.5. THREE-PHASE PWM AC/AC CONVERTERS IN CONTINUOUS
CONDUCTION MODE ............................................................................................ 90
III.6. SELECTION OF THE CONVERTER FOR EXPERIMENTAL TESTING............ 92
III.7. CONVERTER DESIGN ........................................................................................... 93
III.8. CONTROL STAGE DESIGN .................................................................................. 95
III.8.1. FREQUENCY RESPONSE OF THE CONVERTER ...................................... 95
III.8.2. DESIGN OF THE COMPENSATOR .............................................................. 97
III.8.3. SYNCHRONOUS GENERATION OF PWM SIGNALS ............................... 99
III.8.4. PWM SIGNALS DISTRIBUTION CIRCUIT ................................................. 101
III.9. SUMMARY .............................................................................................................. 103
CHAPTER IV. EXPERIMENTAL PROTOCOLS AND DATA ANALYSIS
PROCEDURE....................................................................................... 105
IV.1. INTRODUCTION ..................................................................................................... 105
IV.2. TESTING PROTOCOLS .......................................................................................... 105
IV.2.1. SINUSOIDAL REFERENCE SIGNAL GENERATOR................................... 106
IV.2.2. POWER ELECTRONICS VALIDATION CIRCUIT....................................... 108
IV.3. DATA ANALYSIS PROCEDURE........................................................................... 109
IV.3.1. STATISTICAL ANALYSIS PROCEDURE..................................................... 109
IV.4. SUMMARY............................................................................................................... 111
vi
CHAPTER V. SINUSOIDAL REFERENCE SIGNAL GENERATOR
TESTING AND PERFORMANCE ANALYSIS................................113
V.1. INTRODUCTION .......................................................................................................113
V.2. EXPERIMENTAL TESTING .....................................................................................113
V.2.1. TEST 1: HOLD RANGE AND CENTRAL FREQUENCY...............................113
V.2.2. TEST 2: PULL-IN RANGE.................................................................................117
V.2.3. TEST 3: FREQUENCY JITTER .........................................................................119
V.2.4. TEST 4: PHASE SHIFT OF ADPLL ..................................................................121
V.2.5. TEST 5: TOTAL HARMONIC DISTORTION OF THE SINUSOIDAL
OUTPUT SIGNAL...............................................................................................124
V.2.6. TEST 6: AMPLITUDE AND OFFSET LEVEL OF THE SINUSOIDAL
OUTPUT SIGNAL ..............................................................................................123
V.2.7. TEST 7: LINE FAULT THRESHOLD ...............................................................129
V.2.8. TEST 8: RULE DECODER.................................................................................131
V.3. SIMULATION OF A REFERENCE SIGNAL GENERATOR FOR
COMPARISON ...........................................................................................................132
V.3.1. Case 1: Input voltages balanced in both amplitude and phase.............................134
V.3.2. Case 2: Input voltages with unbalanced amplitude and balanced phase. ............135
V.3.3. Case 3: Input voltages with unbalanced amplitude and phase.............................137
V.3.4. Case 4: Balanced input voltages in both amplitude and phase and with a
10% third harmonic component shifted 10º in each phase...................................139
V.4.- SUMMARY ...............................................................................................................141
CHAPTER VI. THREE PHASE PWM AC/AC CÚK CONVERTER TESTING
AND PERFORMANCE ANALYSIS .................................................143
VI.1. INTRODUCTION .....................................................................................................143
VI.2. EXPERIMENTAL TESTING ...................................................................................143
VI.2.1. TEST 1: OUTPUT VOLTAGE REGULATION ..............................................144
VI.2.2. TEST 2: OUTPUT VOLTAGE TOTAL HARMONIC DISTORTION ...........146
VI.2.3. TESTS 3-8: RESPONSE TIME TO INPUT STEPS .........................................150
IV.4. SUMMARY ..............................................................................................................150
CHAPTER VII. CONCLUSIONS AND FUTURE WORKS ......................................151
APPENDIX A. SINUSOIDAL REFERENCE SIGNAL GENERATOR
SCHEMATICS AND CODING .........................................................153
APPENDIX B. AC/AC CÚK CONVERTER AND CONTROL SCHEMATICS ....161
APPENDIX C. PRINTED CIRCUIT BOARDS ..........................................................165
REFERENCES .................................................................................................................169
vii
ABSTRACT
This dissertation introduces a new approach for the design and development of a
three-phase sinusoidal reference signal generator synchronized with the utility. The
generator is intended for power electronic systems applied to voltage sag compensation, in
particular for AC/AC converters. In order to be used with either analog or DSP-based
control circuits, the proposed generator was implemented in a CPLD, but can be easily
translated into a FPGA for system-on-a-chip (SoC) applications.
The proposed generator consist of four major blocks: an All-Digital PLL (ADPLL), a
phase shift corrector, a phase-to-amplitude converter, and a decision block. The operation of
these blocks depends upon the state of the utility voltages. The array ADPLL – phase shift
corrector provides an in-phase representation of the utility phase angle. The phase-toamplitude converter translates this phase angle to a digital representation of a sine
waveform, and generates two more waveforms: D120 and D240. These waveforms are
digital signals shifted 120º and 240º from the fundamental component of the sine waveform
generated, and are intended to be used as reference replacements by the ADPLLs when an
utility voltage is outside the allowed minimum value.
Chapter II covers the design of the proposed generator. Four basic methods used to
generate sinusoidal waveforms digitally were evaluated for their implementation in CPLD.
Based on the method selected the phase-to-amplitude was designed, and its equations are
presented. Basic theory of PLL circuits is also covered, from analog to all-digital
implementations. This part is important for the understanding of the synchronicity
mechanism, as well as for the selection and development of the component blocks of the
ADPLL and the phase shift compensator. The decision block glues together the three
ADPLL blocks. It has to determine whenever an utility phase is below a predefined
threshold and substitute it with an adequate signal for the operation of the ADPLL.
The AC/AC converters are reviewed in chapter III, both single and three phase
topologies. The operation of single phase converters with different loads is covered. The
additional modes of operation required to transfer energy from the load side to the utility
(when the load is R-L or non-linear) are explained. The converters studied were confined to
the buck-boost derived topologies. This type of converters do not require low-frequency
transformers to compensate voltage sags or swells. The three phase converters reviewed are
suited for symmetrical voltage sag compensation, but their performance under unbalanced
conditions is not adequate. This drawback has lead to the use of independent single phase
converters for three phase compensation. With this option in mind, the design procedure of
the converter and its control stage is presented.
The test of the proposed generator, operating alone, and with the AC/AC converter,
was performed following the procedures included in two protocols. The first protocol is
designed to obtain the performance parameters of the generator: holding frequency, jitter,
THD levels of the sinusoidal waveform, etc. The second protocol is designed to verify the
performance of the generator in static and dynamic conditions when operates in noisy
environments. The protocols are included in chapter IV.
viii
The tests included in the protocols were performed several times in order to reduce
the effect of instrument misreading and random disturbances. All the data measured and
recorded has been analyzed using statistical tools to verify that the performance parameters
are inside the allowed limits. Several equations were developed to describe the behavior of
some parameters.
A comparison of the proposed generator against a basic generator reported in the
literature was also performed at simulation level. Three distorted conditions were studied:
amplitude unbalance with nominal phase shift, amplitude and phase unbalance, and
amplitude and phase balance with a 10% third harmonic. These cases were compared with
each other and with the ideal amplitude and phase balance condition.
Finally, a summary of the dissertation and its conclusions is presented. The papers
written based on this research, and some future works related to both the sinusoidal
reference signal generator and single-phase AC/AC Converters are also included.
ix
RESUMEN
Esta tesis presenta un nuevo esquema para el diseño y desarrollo de un generador
trifásico de referencias sinusoidales sincronizado con la red eléctrica. El generador está
pensado para su uso en sistemas de electrónica de potencia enfocados a compensación de
bajas de voltaje transitorias, de manera particular para convertidores CA/CA. Para su uso
tanto en circuitos de control analógicos, como en los basados en DSP, el generador
propuesto se implementó en un dispositivo CPLD, sin embargo, puede ser fácilmente
implementado en un dispositivo FPGA para su aplicación en dispositivos tipo SoC (siglas en
inglés de System-on-a-Chip).
El generador propuesto está formado por cuatro bloques principales: un circuito de
amarre de fase totalmente digital (ADPLL, por las siglas en inglés de All-Digital PhaseLocked Loop), un corrector de corrimiento de fase, un convertidor de fase-a-amplitud, y un
bloque de toma de decisiones. La operación de estos bloques depende del estado de los
voltajes de la red eléctrica. El arreglo formado por el ADPLL y el corrector de corrimiento
de fase proporciona una representación en fase de los ángulos de fase de los voltaje de la red
eléctrica. El convertidor de fase-a-amplitud convierte este ángulo de fase a una
representación digital de la amplitud de la onda sinusoidal, y genera dos formas de onda
adicionales: D120 y D240. Estas formas de onda son señales digitales que están desfasadas
120º y 240º con respecto a la componente fundamental de la señal sinusoidal generada, y su
finalidad es la de ser utilizadas como reemplazo de las señales de referencia de los ADPLL
cuando alguno de los voltajes de la red eléctrica sea menor a un valor mínimo permitido.
En el capítulo II se trata el diseño del generador propuesto. Cuatro métodos básicos
usados para la generación de formas de onda sinusoidales por medios digitales fueron
evaluados para su posible implementación en dispositivos CPLD. Basados en el método
seleccionado se diseñó el convertidor de fase-a-amplitud, incluyéndose sus ecuaciones en el
texto. También se presenta la teoría básica de los circuitos de amarre de fase (PLL),
cubriendo desde la implementación analógica hasta la completamente digital. Esta sección
es importante para el entendimiento del mecanismo de sincronía, así como para la selección
y desarrollo de los bloques que conforman el ADPLL y el compensador de corrimiento de
fase. El bloque de toma de decisiones une los tres bloque ADPLL. Este bloque debe
determinar cuando un voltaje de la red eléctrica se encuentra por debajo del nivel mínimo
fijado y substituirlo por una señal adecuada para la operación del ADPLL.
Los convertidores CA/CA, tanto en topologías monofásicas como trifásicas, son
estudiados en el capítulo III. La operación de los convertidores monofásicos con diferentes
cargas es cubierta. Se explican los modos de operación adicionales requeridos para la
transferencia de energía del lado de la carga hacia la red eléctrica (cuando las cargas son RL o no lineales). Los convertidores estudiados se confinaron a las topologías derivadas de la
reductora-elevadora. Este tipo de convertidores no requieren el uso de transformadores de
baja frecuencia para compensación de bajas o altas de voltaje transitorias. Los convertidores
trifásicos revisados son apropiados para compensación de bajas de voltaje simétricas, pero
su desempeño en condicione de desbalance de voltaje no son adecuadas. Esta desventaja ha
impulsado el uso de convertidores monofásicos independientes para compensación trifásica.
x
Con esta visión, se presenta el procedimiento de diseño para el convertidor y su etapa de
control.
La prueba experimental del generador propuesto, operando solo, y con el convertidor
CA/CA se realizó siguiendo los procedimientos incluidos en dos protocolos. El primer
protocolo se diseñó para obtener los parámetros de desempeño del generador: la frecuencia
de amarre, la variación de frecuencia (jitter en inglés), los niveles de distorsión armónica
total de la señal generada, etc. El segundo protocolo se diseñó para verificar el desempeño
del generador en condiciones estáticas y dinámicas cuando se opera en ambientes ruidosos.
Los protocolos se incluyen en el capítulo IV.
Las pruebas incluidas en los protocolos fueron repetidas varias veces para reducir el
efecto de malas mediciones y perturbaciones aleatorias. Todos los datos medidos y
registrados fueron analizados usando herramientas estadísticas para verificar que los
parámetros de desempeño se encuentran dentro de los límites permitidos. Varias ecuaciones
se desarrollaron para describir el comportamiento de algunos parámetros.
También se llevó a cabo una comparación del generador propuesto contra un
generador básico reportado en la literatura. Se estudiaron tres condiciones no ideales o
distorsionadas: desbalance de amplitud con ángulos de fase nominales, desbalance de
amplitud y fase, y amplitud y fase balanceadas con un tercer armónico del 10% . Estos casos
se compararon entre sí y contra la condición de amplitud y fase nominal.
Por último, se presenta un resumen de la tesis y sus conclusiones. Se incluyen
también, los artículos escritos basados en esta investigación, y algunos de los posibles
trabajos futuros relacionados tanto al generador de señales de referencia sinusoidales y los
convertidores CA/CA monofásicos.
xi
LIST OF FIGURES
CHAPTER I.
INTRODUCTION
Fig. I.1. Three-phase AC/AC buck converter..................................................................... 3
Fig. I.2. Three-phase AC/AC boost converter. (MODIFICAR FIGURA) ......................... 3
Fig. I.3. Block diagram of the control system reported in [16]. ......................................... 4
Fig.I. 4. Block diagram of the series inverter control reported in [17]. .............................. 5
Fig. I.5. Block diagram of the active power filter control reported in [31]. ....................... 5
Fig. I.6. Block diagram of the active power filter control reported in [32]. ....................... 6
Fig. I.7. Block diagram of the active power filter control reported in [33, 34]. ................. 6
Fig. I.8. Block diagram of the DVR control reported in [35]. ............................................ 7
Fig. I.9. Block diagram of the DVR control reported in [36]. ............................................ 7
Fig. I.10. Block diagram of the DVR control reported in [37]. ......................................... 8
Fig. I.11. Block diagram of the basic topology of the conventional PLL.......................... 8
Fig. I.12. Block diagram of a three-phase PLL.................................................................. 9
Fig. I.13. Block diagram of the proposed three-phase sine-wave reference signal
generator............................................................................................................. 11
CHAPTER II. PROPOSED SINUSOIDAL REFERENCE SIGNAL GENERATOR
Fig. II.1.
Fig. II.2.
Fig. II.3.
Fig. II.4.
Block diagram of proponed sinusoidal reference signal generator. .................. 13
Block diagram of a direct digital synthesizer.................................................... 14
Simulation results using a 10bits word width to calculate the Taylor Series.... 17
Block diagram of the generator using quarter-wave sinusoidal wave
symmetry. .......................................................................................................... 18
Fig. II.5. Basic block diagram of PLL.............................................................................. 22
Fig. II.6. Multiplier PD input signals. (a) signal u1(t) is a sinusoidal waveform.
Dashed line with q1=0; solid line with q1>0. (b) signal u2(t) is a square
waveform. Dashed line with q2=0; solid line with q2>0 ................................. 24
Fig. II.7. Filter used in PLL applications. ........................................................................ 26
Fig. II.8. Most often used PDs in hybrid PLLs ................................................................ 27
Fig. II.9. Waveforms of the XOR gate PD under (a) zero phase error, and (b) phase
error greater than zero ...................................................................................... 28
Fig. II.10. Phase detector output signal vs. phase error of the XOR gate PD. ................... 29
Fig. II.11. Waveforms of the edge-triggered JK flip-flop PD under (a) zero phase
error, and (b) phase error greater than zero ...................................................... 30
Fig. II.12. Phase detector output signal vs. phase error of the edge-triggered
flip-flop PD ....................................................................................................... 30
Fig. II.14. Phase detector output signal vs. phase error of the PFD. .................................. 32
Fig. II.15. Block diagram of an all-digital PLL. ................................................................ 32
Fig. II.16. Schematic diagram of edge-triggered JK flip-flop modified phase detector. ... 34
Fig. II.17. Modified PFD phase detector ........................................................................... 34
Fig. II.18. Block diagram of the modified PFD ................................................................. 35
Fig. II.19. Modified PFD ................................................................................................... 35
Fig. II.20. Difference detector circuit. (a) hybrid implementation, (b) digital equivalent.. 35
xii
Fig. II.21. PFD waveforms ..................................................................................................36
Fig. II.22. Digital filter using a UP/DOWN counter ..........................................................36
Fig. II.23. K counter digital filter ........................................................................................37
Fig. II.24. Recursive filter block diagram. ..........................................................................37
Fig. II.25. Block diagram of a ÷N counter DCO.................................................................38
Fig. II.27. Block diagram of modified ID counter...............................................................39
Fig. II.28. Block diagram of phase-to-amplitude converter with complementor blocks.....43
Fig. II.29. Experimental waveform obtained with the generator.........................................43
Fig. II.30. Block diagram of an ADPLL with divide-by-N counter in the feedback loop. .44
Fig. II.31. Block diagram of ADPLL. .................................................................................46
Fig. II.32. ADPLL with reduction jitter connection. ...........................................................46
Fig. II.33. Schematic diagram of the K-counter filter. ........................................................47
Fig. II.34. Schematic diagram of ID counter DCO. ............................................................47
Fig. II.35. Block diagram of the first proposed modification..............................................48
Fig. II.36. Block diagram of the second proposed modification. ........................................49
Fig. II.38. Digital window comparator. ...............................................................................51
Fig. II.39. Digital counter of the line-fault detector. ...........................................................52
Fig. II.41. Window comparator with glitch-remover circuit. ..............................................53
Fig. II.42. Line-fault detector. .............................................................................................54
Fig. II.43. Initial clock signals generator.............................................................................56
Fig. II.44. Final block diagram of the clock generator. .......................................................56
Fig. II.45. Block diagram for the prototype.........................................................................57
Fig. II.46. ADC input circuit (per phase). ...........................................................................57
Fig. II.47. DAC output circuit (per phase). .........................................................................58
CHAPTER III. SINGLE-STAGE AC/AC CONVERTERS
Fig. III.1. Basic bi-directional switch topologies. . .............................................................61
Fig. III.2. Basic bi-directional switch implemented with reverse-blocking IGBTs. ...........62
Fig. III.3. Cascode array of SiC JFET and Si MOSFET. ...................................................62
Fig. III.4. Inductor current waveform..................................................................................63
Fig. III.5. Capacitor voltage ripple waveform. ....................................................................64
Fig. III.6. AC/AC buck-boost converter..............................................................................67
Fig. III.7. Operating modes with linear resistive load. ........................................................68
Fig. III.8. Operating modes with linear inductive-resistive load.........................................69
Fig. III.9. Operating modes with non-linear capacitive load...............................................71
Fig. III.10. Control signals and voltage and current waveforms of the converter
operating with resistive load. ............................................................................74
operating with R-L load. ...................................................................................75
Fig. III.12. Non-Linear Load. ..............................................................................................76
operating with non-linear capacitive load. ......................................................77
Fig. III.14. AC/AC buck-boost converter............................................................................78
Fig. III.15. Operating modes with resistive load. ................................................................79
operating with resistive load. ...........................................................................80
xiii
Fig. III.17. AC/AC flyback converter................................................................................. 81
Fig. III.18. Operating modes with linear resistive load. ..................................................... 82
Fig. III.19. Operating modes with linear inductive-resistive load. ..................................... 83
Fig. III.20. Operating modes with non-linear capacitive load. ........................................... 85
operating with resistive load. ........................................................................... 87
operating with R-L load. .................................................................................. 88
operating with non-linear capacitive load. . .................................................... 89
Fig. III.24.- Transformation process of a single phase PWM AC/AC buck converter
into a three phase PWM AC/AC buck converter. ........................................... 90
Fig. III.25. Three-phase PWM AC/AC converters. .......................................................... 92
Fig. III.26.- Block diagram of the three phase PWM AC/AC converter including
its control stage................................................................................................. 93
Fig. III.27. Small signal equivalent circuit. ........................................................................ 95
Fig. III.28. Open loop frequency response of the converter. .............................................. 96
Fig. III.29. Pole-zero distribution for the compensating network ...................................... 97
Fig. III.30. Frequency compensating circuit....................................................................... 97
Fig. III.31. Open loop frequency response of the compensated converter. ........................ 99
Fig. III.32. Master-Slave connection of UC3526. .............................................................. 100
Fig. III.33. PWM signals. CH1 Master, CH2 Slave1, CH3 Slave2.................................... 100
Fig. III.34. Master-Slave connection of UC3526. .............................................................. 101
Fig. III.35. PWM signals. CH1 Master, CH2 Slave1, CH3 Slave2.................................... 102
Fig. III.36. One-shoot circuit to limit the maximum duty cycle......................................... 102
Fig. III.37.- Block diagram of the control circuit. .............................................................. 102
PROCEDURE
Fig. IV.1. Laboratory setup for the first seven tests............................................................ 106
Fig. IV.2. Laboratory setup for the Rule Decoder test........................................................ 106
Fig. IV.3. “Eye pattern” proposed for jitter measurement.................................................. 107
CHAPTER V. SINUSOIDAL REFERENCE SIGNAL GENERATOR TESTING
AND PERFORMANCE ANALYSIS
Fig. V.1. Location of confidence interval measured for the hold range limits. .................. 116
Fig. V.2. Location of confidence interval measured for the pull-in range limits. ............. 118
Fig. V.3. Oscillogram of jitter measurement. ..................................................................... 119
Fig. V.4. Location of confidence interval measured for the jitter period limits. ................ 120
Fig. V.5. Input – Output ADPLL response......................................................................... 121
Fig. V.6. Oscillogram of phase shift correction measurement. .......................................... 122
Fig. V.7. Ideal phase error response of the ADPLL. .......................................................... 123
Fig. V.8. Measured phase error response of the ADPLL.................................................... 123
Fig. V.9. Measured phase error response of the ADPLL with the phase shift
correction circuit. ................................................................................................. 124
xiv
Fig. V.10. Recorded data used to perform the THD analysis in MATLAB........................125
Fig. V.11. Measured THD values of the sinusoidal output signal. .....................................125
Fig. V.12. Effect of DCO frequency variation over the input bus of the
combinational ROM............................................................................................126
Fig. V.13. Amplitude...........................................................................................................128
Fig. V.14.- Location of confidence interval measured for the amplitude of the
generated signal..................................................................................................129
Fig. V.15.- Location of confidence interval measured for the amplitude of setting
flag limit.............................................................................................................130
Fig. V.16.- Location of confidence interval measured for the amplitude of resetting
flag limit.............................................................................................................131
Fig. V.17. Rule decoder.......................................................................................................131
Fig. V.18. Phase-to-phase angle. .........................................................................................132
Fig. V.19. Reference generator presented by Chung [33]. ..................................................133
Fig. V.20. Circuits used to simulate the reference signal generators. .................................134
Fig. V.21. Voltage sources used to simulate a balanced voltage case. ...............................134
Fig. V.22. Simulation with balanced amplitude conditions. ...............................................135
Fig. V.22. Simulation with unbalanced amplitude conditions. ...........................................137
Fig. V.24. Resistor array used to generate a virtual ground for the SRSG. ........................137
Fig. V.25. Simulation with amplitude and phase unbalance conditions..............................138
Fig. V.26. Simulation with 10% third harmonic component. .............................................140
Fig. VI.1. Block diagram of AC/AC converter and its control stage. .................................143
Fig. VI.2. Laboratory setup. ................................................................................................144
Fig. VI.3. Converter output voltage.....................................................................................144
Fig. VI.4. Regulation error vs. input voltage.......................................................................145
Fig. VI.5. THD levels vs. input voltage. .............................................................................146
Fig. VI.6. Harmonic components of output voltages, highest and lowest levels
per phase. ............................................................................................................147
Fig. VI.7. Zero-crossing distortion of Van, Vbn and Vcn...................................................148
Fig. VI.8. Converter output voltage.....................................................................................149
Fig. VI.9. System response to input voltage steps...............................................................150
Fig. VI.10. ITIC curve. .......................................................................................................150
APPENDIX A. SINUSOIDAL REFERENCE SIGNAL GENERATOR
SCHEMATICS AND CODING
Fig. A.1.
Fig. A.2.
Fig. A.3.
Fig. A.4.
Fig. A.5.
Fig. A.6.
Fig. A.7.
Schematic diagram of the SRSG .......................................................................153
ADPLL schematic diagram ...............................................................................154
Phase detector schematic diagram .....................................................................154
Module K schematic diagram ............................................................................155
ID counter schematic diagram ...........................................................................155
Feedback counter program coding ....................................................................156
Shift corrector schematic diagram .....................................................................156
xv
Fig. A.8. Shifted signals generator program coding ........................................................ 157
Fig. A.9. Phase-to-Amplitude converter schematic diagram ........................................... 157
Fig. A.10. Sine-wave program coding ............................................................................... 159
Fig. A.11. Clock generator schematic diagram ................................................................. 160
APPENDIX B. AC/AC CÚK CONVERTER AND CONTROL SCHEMATICS
Fig. B.1. Schematic diagram of a single-phase AC/AC Cúk converter module .............. 161
Fig. B.2. Schematic diagram of a control circuit for AC/AC Cúk converter
(PWM section) .................................................................................................. 162
(Reference output section) ................................................................................ 163
(Feedback section) ............................................................................................. 164
APPENDIX C. PRINTED CIRCUIT BOARDS
Fig. C.1.
Fig. C.2.
Fig. C.3.
Fig. C.4.
Top layer of the PCB layout of the SRSG (not at 1:1 scale) ............................. 165
Bottom layer of the PCB layout of the SRSG (not at 1:1 scale) ....................... 165
Top layer of the PCB layout of the AC/AC Cúk converter (not at 1:1 scale) ... 166
Bottom layer of the PCB layout of the AC/AC Cúk converter
(not at 1:1 scale) ................................................................................................ 166
Fig. C.5. Top layer of the PCB layout of the control stage (not at 1:1 scale) .................. 167
Fig. C.6. Bottom layer of the PCB layout of the control stage (not at 1:1 scale) ............. 167
xvi
LIST OF TABLES
CHAPTER II. PROPOSED SINUSOIDAL REFERENCE SIGNAL GENERATOR
Table II.1.
Table II.2.
Table II.3.
Table II.4.
Table II.5.
Table II.6.
Table II.7.
Table II.8.
Table II.9.
Table II.10.
Table II.11.
Table II.12.
THD of modified Taylor series.......................................................................17
THD as a function of k and m ........................................................................19
Number of macrocells.....................................................................................20
Number of macrocells needed to implement ..................................................21
Summary of converters parameters. ...............................................................21
CPLD needed to implement the......................................................................22
PLL equations for different kinds of filters ....................................................26
Values of data(n) for k=9 and m=8.................................................................40
Expected duty cycle vs. Phase Detector .........................................................45
Code listing for the generation of internal reference signals. .........................50
Decision rules .................................................................................................54
Rule decoder coding. ......................................................................................55
CHAPTER III. SINGLE-STAGE AC/AC CONVERTERS
Table III.1.- Equations for the passive elements of AC/AC buck-boost derived
topologies........................................................................................................65
Table III.2.- Equations of the voltage stress for the elements of AC/AC buck-boost
derived topologies in P.U. referred to output voltage.....................................65
Table III.3.- Equations of the current stress for the elements of AC/AC buck-boost
derived topologies in P.U. referred to output current. ....................................66
Table III.4.- Characteristics of PWM AC/AC converters for AC line conditioning...........92
PROCEDURE
Table IV.1. Specific Tests Guide for SRSG. .....................................................................107
Table IV.2. Rule decoder input/output relationship...........................................................108
Table IV.3. Specific tests guide for the validation circuit. ................................................109
CHAPTER V. SINUSOIDAL REFERENCE SIGNAL GENERATOR TESTING
Table V.1. Measured hold range .........................................................................................114
Table V.2. Adjusted measured hold range limits ................................................................115
Table V.3. Measured pull-in Range ....................................................................................117
Table V.4. Adjusted measured pull-in range limits.............................................................117
Table V.5. Measured frequency variation. ..........................................................................120
Table V.6. Measured phase shift. ........................................................................................121
Table V.7. Measured THD of the output signal. .................................................................124
Table V.8. Measured amplitude and offset level of the output signal.................................128
xvii
Table V.9 Measured threshold line fault limits. ................................................................. 129
Table V.10. Measured phase angle between output signals. .............................................. 132
Table V.11. Simulated nominal output values of the compared generators. ..................... 135
Table V.12. Simulation results of study case 2................................................................... 136
Table VI.1.
Table VI.2.
Table VI.3.
Table VI.4.
xviii
RMS value of the output voltage. .................................................................. 145
THD value of the output voltage.................................................................... 146
Harmonic components exceeding the standard limit. .................................... 148
Response time of the converter under input voltage step. ............................. 149
LIST OF SYMBOLS
A
a
AD(i)
ADC_ck
Aj
B
C
C
c
C0
C1
D
D̂
d̂
D(i)
D’
D120
D240
e
F
f()
F()
fc
fclk
fCP1,2
fCZ3
fDCO
fi
fout
fP1
fP2
fP3
freq
fsw
fxo
fZ1
fZ2
fµ
Ho
maximum peak value.
PWM-switch active terminal.
value of the ith input address bit of the combinational ROM
(i=0,1..k-3).
ADC start of conversion signal.
value of the jth equivalent address bit (j=0,1..8).
minimum peak value.
capacitance.
capacitance of non-linear load.
PWM-switch common terminal.
output capacitor.
input capacitor.
maximum converter duty cycle.
PWM-switch perturbed duty cycle.
PWM-switch perturbed variation of duty cycle.
value of the ith output data bit of the phase-to-amplitude
converter (i=0,1..m-1).
1-D.
120º shifted signal.
240º shifted signal.
error signal.
line frequency.
time function.
Fourier function.
central frequency of the ADPLL.
digital clock frequency.
complex-pair pole frequency of the converter function (Hz).
third converter zero frequency (Hz).
clock signal of the DCO.
ith frequency sample value.
output frequency.
first compensator pole at the origin.
second compensator pole frequency (Hz).
third compensator pole frequency (Hz).
frequency in Hertz.
converter’s switching frequency.
compensator crossover frequency (Hz).
first compensator zero frequency (Hz).
second compensator zero frequency (Hz).
samples mean frequency.
zero frequency transfer function gain.
xix
IP
îa
îc
îo
î p
inductor peak current.
PWM-switch perturbed active terminal current.
PWM-switch perturbed common terminal current.
PWM-switch perturbed output current.
PWM-switch perturbed passive terminal current.
is
î1
î2
k
K
Kd
KI
Ko
KV
L0
L1
LCL
Li
m
M
Mfc
n
N
converter input current.
PWM-switch perturbed supply current.
PWM-switch perturbed input capacitance current.
word-width of the phase angle.
power of 2, maximum count of the digital filter,
gain of the PD.
inductor current ripple factor.
VCO gain factor.
capacitor voltage ripple factor.
output inductor.
input inductor.
lower control limit.
ith recorded value of the lower limit frequency.
word-width of the amplitude.
power of 2, defines the clock frequency of the digital filter.
digital clock frequency of the ADPLL filter.
integer ranging from 0 to 2k-2-1.
power of 2, maximum count of a feedback counter of a PLL
circuit.
digital clock frequency of the ADPLL DCO.
number of samples.
transformer turn ratio.
digital representation of a sine waveform.
PWM-switch passive terminal.
first conjugated pair of poles frequency (rad/seg).
second conjugated pair of poles frequency (rad/seg).
converter output power.
ADPLL quality factor.
resistence.
main resistance of non-linear load.
value of the ith output bit of the combinational ROM.
(i=0,1..7).
load resistance.
series resistance of non-linear load.
sample standard deviation from the expected value.
line period.
critical value of t for a level of significance α/2 and N-1
Nfc
Ns
Nt
OUT()
p
p1,2
p3,4
Po
Q
R
R1
Ri
Rload
Rs
s
T
tα
,df
2
degrees of freedom (df).
xx
u1(t)
U10
u2(t)
U20
UCL
ud
Udud(t)
Ud+
uf(t)
Ui
V*as
V*bs
V*cs
V*de
V*qe
V*α
V*β
V1
V3
V5
Vab
Van
Vap
Vas
Vbc
Vbn
Vbs
Vc
Vca
Vcn
Vcs
Vde
V̂g
PLL reference signal.
peak value of the PLL reference signal.
VCO output signal.
peak value of the VCO output signal.
upper control limit.
digital state of the PD.
digital low state of the PD.
output signal of the PD.
digital high state of the PD.
output signal of the PLL’s loop filter.
ith recorded value of the upper limit frequency.
reference phase voltage A.
reference phase voltage B.
reference phase voltage C.
reference direct voltage in the rotating reference frame.
reference quadrature voltage in the rotating reference frame.
reference direct voltage in the static reference frame.
reference quadrature voltage in the static reference frame.
RMS value of the fundamental.
RMS value of the third harmonic.
RMS value of the fifth harmonic.
line to line voltage AB.
line to neutral voltage A.
active-to-passive terminals voltage.
phase voltage A.
line to line voltage BC.
line to neutral voltage B.
phase voltage B.
capacitor peak voltage.
line to line voltage CA.
line to neutral voltage C.
phase voltage C.
direct voltage in the rotating reference frame.
PWM-switch perturbed supply voltage.
Vo
vo
Vqe
VS
vs
Vsmin
Vα
Vβ
W
x
x1
peak value of the output voltage.
converter output voltage.
quadrature voltage in the rotating reference frame.
peak value of the input voltage.
converter input voltage.
minimum input voltaje.
direct voltage in the static reference frame.
quadrature voltage in the static reference frame.
digital window comparator signal.
mean value of the samples.
gate signal of converter switch M1.
xxi
x2
x3
x4
XL
xlower
xnom
xupper
Y
z1,2
z3
Zload
∆
∆F
∆f
∆I
∆Vc
∆ωt
α
δ
φ(n)
φAB
φBC
φCA
φe
φec
η
ϕ
µ0
µ̂1
µ̂ 2
θ
θe
σ
ω
ω1
ω2
ωc
ωn
ωt
ζ
xxii
inductive reactance.
minimum allowed value of a parameter.
nominal value of a parameter.
maximum allowed value of a parameter.
three-phase four wire connection.
first conjugated pair of zeros frequency (rad/seg).
third real zero frequency (rad/seg).
load impedance.
three-phase three wire connection.
difference between the frequency of the input signal and the
ADPLL central frequency.
holding range of the ADPLL.
inductor current ripple.
capacitor voltage ripple.
phase angle increment.
significance level.
duty cycle of PLL output signal.
integer representation of the phase angle.
angle shift between phases A and B.
angle shift between phases B and C.
angle shift between phases C and A.
phase shift between the ADPLL reference and its output
signals.
corrected phase shift between the ADPLL reference and its
output signals.
efficiency.
power factor angle.
process mean value.
lower limit of the confidence interval,
upper limit of the confidence interval,
phase angle.
phase error.
population standard deviation.
angular frequency.
angular frequency of the reference signal,
angular frequency of the VCO output signal.
central frequency of the VCO.
filter natural frequency.
phase angle.
filter dumping factor.
CHAPTER I.- INTRODUCTION
I.1.- MOTIVATION
In recent years, power quality and energy supply reliability have gained special
importance among industrial, commercial and domestic customers. Poor power quality
might disrupt the operation of computers, motor drives, and industrial controls among
several loads, resulting in data losses, equipment malfunction, production and/or economic
losses, and in extreme cases user injuries.
One of the most costly disturbances affecting power quality is the momentary
voltage drop, commonly referred as voltage sag. This disturbance, when not compensated,
can be responsible for huge economical losses in a wide range of customers like paper
mills, radio and TV broadcast facilities, data centers, etc. These economical losses are
related to the costs of product waste, broadcasting time lost, computer information
disruption, etc.
These costs have driven many different efforts to eliminate, or at least mitigate, the
effect of voltage sags. There are several power electronics solutions for this problem with
applications in distribution, mid-voltage and low-voltage levels. One thing these solutions
have in common is the need of sinusoidal reference signals for their proper operation. In
most cases, these signals also need to be synchronized with the power grid.
Traditionally, for three-phase applications, the reference signals generation has been
performed using Clark and/or Park Transformations, implemented in DSP’s, to translate the
power grid three-phase voltage to a quadrature reference frame. The resulting signals are
used to extract the phase information of the grid voltage. The sinusoidal reference signals
are generated by applying the inverse Clark and/or Park Transformation.
One particular drawback of this approach is the error induced by voltage unbalances
in the power grid, and although several solutions have been developed, in some cases the
cost on computational time can be critical. This is particularly true in DSP-based controls
of distributed power electronics systems, and in systems performing complex control laws
It is desirable to free the DSP from this task, and to have a reliable solution that
behaves satisfactorily under voltage unbalance of the power grid. One way to achieve these
goals is by implementing the reference signal generator in hardware, using programmable
logic devices such as CPLD’s and FPGA’s. The hardware implementation can be interfaced
to simple analog control circuits via a Digital-to-Analog Converter, and to DSP-based
complex control circuits.
1
I.2.- STATE-OF-THE-ART REVIEW
The review of the state of the art can be divided into two parts: the first part includes
the power electronics systems for voltage sag mitigation, with special emphasis in singlestage AC/AC converters. The second part is a review of some of the control schemes and
their methods to generate the sinusoidal reference signals. At the end of the section a
summary of the review is presented.
I.2.1.- POWER ELECTRONICS SYSTEMS USED IN SAG COMPENSATION
Momentary voltage drops (from now on we will refer to them as sags) are defined
as reductions on the RMS nominal voltage value during a short lapse, whose length is
between half line cycle and a few seconds [2], [4], [5], [6].
Sags are caused mainly by short circuits, either in the costumer installations or in
the utility distribution systems [1]. However, there are some other sag generation processes:
high power electric motor starting [1], [4], [6], [7], lighting strikes over the electric grid [2],
[7] and fast recovery of circuit breakers [5].
Regardless of its origin, due to the wide use of sensitive loads, even short sags can
cause process interruptions, whose associated costs can be high [1], [3], [7].
These costs explain the growing interest in developing sag mitigation techniques
[1]. Among many options available, dynamic voltage restorers (DVR) [8-14] are used to
mitigate voltage sag effects on the distribution lines; power active filters [15-17] had raised
interest among the power quality community as power conditioners capable of mitigate
disturbances. Static VAR compensators (SVC or SVAr) have been used to improve the
power factor and to stabilize transmission systems [18], [19].
A traditional approach to produce a high quality AC voltage is based on AC/DC/AC
energy conversion systems, just as the one reported in [20]. This structure corrects the input
power factor and regulates the output voltage. As a drawback the structure has two stages,
this means a low efficiency.
A more efficient approach is to use bi-directional current and voltage switches to
modify the CD/CD converter structures, such as: the buck converter [21], boost converter
[22-25] or full bridge converter [26-28].
The buck converter presented in [21], and shown in Figure I.1, is connected just like
a DVR, this means that the voltage sag level that can be mitigated depends on the injection
transformer and the maximum duty cycle allowed. The voltage sag mitigation capability
reported is 75%.
2
L1
V1
Y1
L2
V2
TX1
C1
X1
X2
C2
Y2
TX2
L3
X3
C3
Y3
V3
TX3
CONTROL
PWM
Fig. I.1.- Three-phase AC/AC buck converter.
Another implementation of a buck converter to compensate voltage sags is
presented in [22]. The converter is connected as a DVR, providing voltage compensation
only when needed. It can compensate voltage sags up to 30% and was tested in a 1.5kVA
single-phase application. This approach is proposed to be integrated into a distribution
transformer.
The boost converters reported in [23-25] are connected as voltage regulators. These
converters can mitigate voltage sags in the 77 to 84% range. In [25], the converter used is a
single-phase type, and offers input power factor correction; to implement a three-phase
solution it is necessary to use three independent circuits. Figure I.2 shows the schematic of
a three-phase boost converter.
Va,o
Va
Vb
S1
Vb,o
CARGA
Vc
S3
Vc,o
S4
S2
S6
S5
C
C
C
Fig. I.2.- Three-phase AC/AC boost converter. (MODIFICAR FIGURA)
In [26-28], an AC/DC/AC structure is reported. It is built with a boost converter
connected in series with a full bridge converter that includes a resonant circuit for zero
voltage switching. The system can mitigate voltage sags up to 78% and performs input
power factor correction. The reported efficiencies for a 1.5kW system are in the 74 to 94%
range.
3
I.2.2.- CONTROL STAGE AND REFERENCE SIGNAL GENERATION IN
THREE-PHASE POWER ELECTRONICS SYSTEMS
The performance of DVRs [12], [13], [16], universal power conditioners [17],
SVARs [19], active power filters [12] among others, rely in a proper power stage and
control loop design, and the system output must follow the reference signal as closely as
possible. With this concept in mind, the review of some closed loop controls used by those
power electronics systems was carried on, paying special attention to the reference signal
generation.
Figure I.3 shows the block diagram of the control system used for the series active
filter in [16]. The filter behaves as a sinusoidal current source in phase with the supply
voltage. The error “e” between the rms values of the load voltage and the reference is
processed in the fuzzy controller. Its output K is multiplied by a sinusoidal template current
synchronized to the corresponding phase voltage of the mains to produce the reference
current Iref.
Fig. I.3.- Block diagram of the control system reported in [16].
The control for the multilevel converter used by Tolbert [17] to regulate the load
voltage is based on the short time window sampling technique proposed by Joos and Moran
[30]. The load reference voltage, which must be synchronized with the source phase
voltages, is generated directly from the sampling of the two line-to-line source voltages
over a short time frame. By using these voltages, a synchronization signal can be obtained,
even if one or two of the phase voltages collapses to zero, as in the case of a single or
double line to ground solid fault [17]. Figure I.4 shows the proposed controller.
The control scheme proposed for an active power filter by Perales et al [31] is
shown in Figure I.5. Once measured, load currents (iLr, iLs, iLt) and voltages (vr, vs, vt),
are converted to α-β co-ordinates using the Clark transformation. These components are
filtered using a Self-Tuned Vector Filter (STVF), calculating the main (50Hz) component
of voltage and current. The current vector is then projected over the voltage, producing a
vector in the same direction of V, and with modulo I·cos(ϕ), being the active component of
current. This vector is subtracted from the measured current to generate the current
necessary to compensate harmonics and reactive power. A component intended to
4
compensate DC-link voltage variations is also added, and after performing a reverse Clarke
transformation the current reference signals are generated.
Fig.I. 4.- Block diagram of the series inverter control reported in [17].
Fig. I.5.- Block diagram of the active power filter control reported in [31].
In [32], a PLL (phase locked loop) is used to extract the magnitude and phase of the
direct fundamental voltage component out of the input voltage. This component will be
subtracted from the total voltage signal to separate the disturbing components. The
difference between the desired voltage and the direct voltage provided by the PLL is added
to the disturbing component through Park inverse transformation to form the reference
voltage as shown in Figure I.6.
5
In photovoltaic systems connected to the grid [33], [34] the control of the power
factor is known as one of the most important techniques required to ensure perfect
transmission of generated power without circulating energy. To achieve this goal it is
necessary to accurately detect the phase of the utility voltage. The block diagram shown in
Figure I.7 describes a three-phase PLL based current reference signal generator used to
control an inverter. The generator bases its operation in the transformation of the threephased utility voltage signals into single-phased signals to operated a PLL structure. The
output of the PLL is then passed to a reverse transformation block to obtain the reference
signals in phase with the utility.
Vdir
desired
VA
VB
VC
S in δ d
+
Vq=Vd -
Mesure of
Vd andδd
with a PLL
Cosδ d
Transformation
2/3
Vd=0
Vr3
Vr1 Vr2
S in δ d
Cosδ d
+
Transformation
2/3, Vq
-
VA
+
+
+
- VB
+
+
- VC
Vref_A
+
+
+
Vref_B
Vref_C
Fig. I.6.- Block diagram of the active power filter control reported in [32].
Fig. I.7.- Block diagram of the active power filter control reported in [33, 34].
In [35], the control scheme presented for a DVR, shown in Figure I.8, is based on
the two step transformation of the source voltages to the synchronous reference frame. The
angle ωot can be generated by a PLL connected to the utility. When the utility is balanced,
e
e
its synchronous reference frame equivalents vsq
and v sd
are filtered and stored as
6
e*
e*
references v sq
and v sd
. These references are updated in a continuous way. When a voltage
sag is detected, the last reference values stored are locked and used to calculate the
compensation command. The command voltages for the inverter are drawn from the
difference between v se* and vse . The inverter command voltages are then translated to the
three-phase system. The disturbance filter (DF) blocks are included to attenuate highfrequency disturbances, such as voltage spikes. The last values of v se* are locked when the
positive-sequence component of vse is below K% of the positive-sequence of v se* .
Utility
vssq
abc
vsabc
s
d q
vsqe _
d s qs
e
d q
s
vssd
vinvqe*
e*
sq
v
vinvde*
+
e
vesd
_
vsde*
+
LPF
DF
PWM
s
d q
s
k (vsqe*)2 +(ve*sd)2
S/H
DF
vsabc
de q e
Vth
Inverter
start
Lock
Critical
Loads
LPF
v-esq
-e
sd
v
vLabc
+
x2
Compare
Vpos
+
x2
sag detector
Fig. I.8.- Block diagram of the DVR control reported in [35].
Newman et al [36] propose a sag compensation control based on the combination of
source voltage feed-forward and a PI d-q load voltage feedback, shown in Figure I.9. The
phase angle required to transform the three-phase voltages to the synchronous reference
frame is generated by a PLL. This angle is also used for the generation of the output
reference signals. To reduce the effect of phase jumps, the phase of the reference signals
are controlled to vary slowly during transients. The feed-forward loop calculates the
modulation required for compensating the load voltage. The feedback loop is used to
compensate the inductor and the transformer drops in the DVR in steady state. The voltage
sag detection strategy is based on the rms of the error vector. It allows the detection of
balanced and unbalanced voltage sags as well as phase jumps.
VLoad(abc)
VSupply(abc)
θPLL
abc
α−β
α−β
d-q
abc
α−β
α−β
d-q
VDVR(d-q)
+
θPLL
-
-
(Feedback)
+
+
VDVR,Ref(d-q)
PI
+
+
θPLL
d-q
α−β
(Feedforward)
Injection
limiting
α−β
abc
VDVR(abc)*
Saturation
Control
IInverter
7
Nielsen et al [37] present a simpler approach for the control of a DVR, shown in
Figure I.10. An open loop feed-forward control is used. This control transforms the threephase supply voltages into the synchronous reference frame, again the angle required for
the transformation is provided by a PLL. A voltage sag is detected by measuring the error
generated by the d-q equivalent of the supply voltages and the reference values vd_ref and
vq_ref. vd_ref is set to the rated voltage and Vq_ref to zero.
Supply
- uDVR +
3
+
usupply
-
RST
6
αβ
θ
ud_ref=325
uq_ref=0
Load
Converter
PLL
αβ
+
uload
-
6
θ
dq
PWM
θ
_
dq
+
_
+
2
αβ
αβ
3
RST
At this point of the literature review, some characteristics of the reference signal
generation systems can be summarized:
-
The actual state of the source signals (voltage and/or current) has to be sensed.
Some of them transform the three-phase source signals into a single-phase reference
frame (Clark and Park transformations).
Some of them use a PLL block to synchronize with the utility.
DSP based.
The most common PLL topologies can be classified as zero-crossing structures in
which the detection of phase and frequency disturbances is based on the zero crossing
instants of the input signal, resulting in a slow structure. Additionally, the voltage
controlled oscillator (VCO) block demands a dc input signal. Hence, a low-pass filter is
required, thus contributing to further constrain the dynamic performance of the PLL [34]
(Figure I.11).
Input
Signal
Phase
Detector
Low-pass
Filter
Voltage
Controlled
Oscillator
Phase
Fig. I.11.- Block diagram of the basic topology of the conventional PLL.
8
A basic configuration of a three-phase PLL system that coped with this issue is
reported in [38, 39, 40] and shown in Figure I.12. The phase voltages Vas, Vbs, Vcs are
obtained from sampled line-to-line voltages. These stationary reference frame voltages are
then transformed to voltages Vde, Vqe using a Clark transformation followed by a Park
transformation. The angle θ* used in these transformations is obtained by integrating a
frequency command ω*. If the frequency command ω* is identical to the utility frequency,
the voltages Vde and Vqe appear as dc values.
Fig. I.12.- Block diagram of a three-phase PLL.
In this method, a PI regulator is used to obtain that value of θ* (or ω*) which drives
the feedback voltage Vde to a commanded value Vde*. The magnitude of the controlled
quantity Vde determines the phase difference between the utility voltages and sin(θ*) or
cos(θ*).
The method results not only in the utility frequency ω*, but also allows one to lock
at an arbitrary phase angle θ* with respect to the utility angle θ.
As was mentioned, before these structures base their implementation on DSP
systems. Its performance will depend upon the speed of the DSP and the skills of the
programmer to design an optimum algorithm and code.
I.2.3.- SUMMARY
In the review performed, the control schemes for three-phase power electronics
systems base their operation in the use of the Clark and Park Transformations to convert the
three-phase reference frame into a single-phase reference frame.
Those circuits sense the line voltage phase angle to synchronize its operation. To
gather this data it is necessary to track the voltage signal fundamental component. The
tracking system must satisfy at least three conditions [42]:
9
1.- high convergence speed,
2.- precision at frequency estimation, and
3.- noise immunity.
Several methods have been proposed to satisfy these conditions. One of them bases
its synchronization on the line voltage zero crossing detection [41], [42]. In spite of the
voltage polarity change, it gives enough information about the cycle beginning. In practice,
this voltage signal is often distorted. This is particularly important when the distortion
occurs in the neighborhood of the zero crossing.
Another method used to generate synchronized signals is based on (three-phase)
PLL [32], [33], [34], [38], [39]. Voltage notches, unbalance, sags, phase losses, and
frequency variations are common operating conditions for equipments connected to the
utility; any PLL working under these conditions must be capable not only to lock the phase
generated as fast as possible, but also to generate a low distortion signal [39]. The
synchronization systems reported in [32], [33], [34], [38], [39] are based on three-phase
PLL circuits that incorporate the Clark and Park transforms.
A software PLL that uses the Clark and Park transforms, exhibits some problems
when sags or voltage unbalance occur at the line voltage. These problems can be solved by
programming the DSP to perform compensations on the equations defining the PLL [33,
34, 39].
In order to generate reference signals synchronized with the input voltages, the
implementation of Clark and Park reverse transforms is required, adding computing time to
the DSP program.
One case not mentioned in the literature is the one regarding voltage sags with
phase jumps. Recapitulating, it is interesting to develop a synchronization and/or reference
signal generation systems having the following characteristics:
1.- independent from Clark and Park transforms,
2.- not implemented in a DSP system,
3.- immune to noise and harmonic components present in the line voltage,
4.- with good dynamic response in the locked phase frequency range,
5.- with stable operation under line voltage unbalance, and
6.- with stable operation under single line to ground fault and line to line fault.
I.3.- PURPOSE AND GOALS
The Doctoral Research work is aimed to develop a three-phase reference signal
generation system that complies with the above-mentioned characteristics. The
development includes simulation and experimental tests.
10
Figure I.13 shows a block diagram of the proposed scheme. It is based on three PLL
circuits commanded by a decision block, and a phase-to-amplitude converter. The decision
block must change its outputs when a fault at the input voltage is detected.
It has also been mentioned the intention of not using a DSP with the goal of
reducing the number of system elements. Therefore, it is necessary to use programmable
logic devices, which provide a flexible platform to implement the all digital PLL and the
other blocks.
The general objective of this doctoral research work is focused on the development
of a highly integrated three-phase sinusoidal reference signal generation system
synchronized with the utility line, that can be incorporated to the control system of power
electronic equipments such as uninterruptible power supplies, DVRs, active power filters or
AC/AC converters.
In particular, the work aims at:
1.- Developing a three-phase digital reference signal generation system based on
PLL that does not use Clark and Park transformations.
2.- Developing a system with a good performance in power grids operating either
with 50 Hz or 60 Hz frequencies.
3.- Developing a system with high noise immunity and high lock speed.
4.- Building a prototype to perform laboratory tests using a power electronics
structure mentioned in the general objective.
5.- Performing comparative simulations and experimental tests of the prototype.
DECISION
BLOCK
ADPLL_A
ADC_A[0:7]
ADC_A
FB_A
All Digital
PLL
N[0:k-1]
PHASE
A[0:k-1]
SHIFT
CORRECTOR
Phase-to-Amplitude
Converter
D[0:m-1]
D
A
PHASE A
D120 D240
DA120
DA240
ADPLL_B
ADC_B[0:7]
All Digital
PLL
N[0:k-1]
ADC_B FB_B
PHASE
A[0:k-1]
SHIFT
CORRECTOR
Phase-to-Amplitude
Converter
D[0:m-1]
D
A
PHASE B
D120 D240
DB120
DB240
ADPLL_C
ADC_C[0:7]
ADC_C FB_C
All Digital
PLL
N[0:k-1]
PHASE
A[0:k-1]
SHIFT
CORRECTOR
Phase-to-Amplitude
Converter
D[0:m-1]
D
A
PHASE C
D120 D240
DC120
DC240
Fig. I.13.- Block diagram of the proposed three-phase sine-wave reference signal generator.
11
I.4.- DISSERTATION OUTLINE
In Chapter II, the proposed sinusoidal reference signal generator is presented, and
its required performance parameters are set. The background for the design of each block is
reviewed. First, the review of some of the methods used to generate digitally a sinusoidal
waveform is performed, giving special attention to the distortion level of the generated
waveform and the number of logic elements needed. Then, the basic concepts of phaselocked loops are reviewed, making special emphasis on the characteristics of the inner
block of the all-digital phase-locked loop. Finally, the design procedure for the proposed
generator is presented.
Chapter III presents a review of the single-stage AC/AC converters in particular the
topologies derived from the buck-boost topology, and both discontinuous and continuous
conduction mode are covered. In order to validate the proper operation of the proposed
sinusoidal reference signal generator, a three-phase four-wire AC/AC converter is
presented along with its design procedure and performance parameters. Finally, the control
stage for the converter and its design are included.
The testing protocols for both sinusoidal reference signal generator and the AC/AC
converter used to validate its operation are presented in Chapter IV. The data analysis
procedure is also presented in this chapter.
Chapter V presents the experimental data and their analysis of the sinusoidal
reference signal generator. The design performance parameters are compared with the
experimental results. Based on these comparisons, many of the parameters are presented
using the average value obtained along with its maximum variation. Also, the performance
of the proposed generator is compared against a generator reported in the literature. The
comparison is made using data gathered from simulation tests under four different input
voltage amplitude and phase conditions. The AC/AC converter experimental data are
presented in Chapter VI. These data are analyzed and compared with the performance
parameter defined in Chapter III.
Finally, Chapter VII presents a summary of the dissertation and its conclusions. The
papers published based on this research and some future works related to both the
sinusoidal reference signal generator and the single-phase AC/AC converter are also
included.
12
CHAPTER II.- PROPOSED SINUSOIDAL REFERENCE
SIGNAL GENERATOR.
II.1.- INTRODUCTION
This chapter presents the basic block diagram of the proposed sinusoidal reference
signal generator and its performance parameters. Before the design procedure is presented, the
basic theory for generating sinusoidal signals using digital methods is reviewed, taking special
care on the minimum THD levels of the generated signal and the amount of hardware needed
for implementation. Also, the basic theory of PLLs used for synchronization purposes is
covered. Finally, the design procedure of each of the component blocks of the proposed
generator is presented.
II.2.- PROPOSED SINUSOIDAL REFERENCE SIGNAL GENERATOR
The proposed sinusoidal reference signal generator (SRSG), shown in Figure II.1, is
based on three single-phase sinusoidal signal generators synchronized with the power grid and
controlled by a decision block. The decision block determines the state of each of the voltage
phases of the power grid and takes the corresponding action to keep the output signals of the
single-phase signal generators shifted 120 degrees from each other. The synchronizing action
is performed with three independent All-Digital PLLs (ADPLL) configured as frequency
multipliers.
CK60
Init of Conv.
st
Van
G
+
Offset
A
D
C
ADC_A[0:7]
G
+
Offset
A
D
C
ADC_B[0:7]
G
Offset
+
eoc
PHASE
A[0:k-1]
SHIFT
CORRECTOR
Phase-to-Amplitude
Converter
D[0:m-1]
D
A
D
A
C
G
+
Vcnref
+
Vcnref
+
Vcnref
Offset
D120 D240
Nfc
All Digital
PLL
ADPLL_B
N[0:k-1]
ADC_B FB_B
PHASE
A[0:k-1]
SHIFT
CORRECTOR
Phase-to-Amplitude
Converter
D[0:m-1]
D
A
D
A
C
Mfc
G
Offset
D120 D240
Nfc
DB120
DB240
st
Vcn
ADC_A FB_A
N[0:k-1]
DA120
DA240
eoc
A
D
C
All Digital
PLL
ADPLL_A
Mfc
eoc
st
Vbn
Mfc
Nfc
Clock
Signals
Generator
ADC_C[0:7]
All Digital
PLL
ADPLL_C
N[0:k-1]
ADC_C FB_C
PHASE
A[0:k-1]
SHIFT
CORRECTOR
Phase-to-Amplitude
Converter
D[0:m-1]
D
A
D
A
C
D120 D240
Mfc
G
Offset
Nfc
DC120
DC240
DECISION
BLOCK
M4A3-512/160
Fig. II.1.- Block diagram of proponed sinusoidal reference signal generator.
13
One PLL’s characteristic that must be eliminated is the phase shift that occurs when
the frequency of its input signal moves away form the central frequency. The SRSG includes a
phase shift corrector to perform this task. Additionally, the SRSG has two analog interfaces,
the first one, implemented by three synchronized analog-to-digital converters, provides phase
and amplitude information of the power grid voltage signals. The second interface is
considered as optional, the digital representation of the sinusoidal reference signal is
converted with a digital-to-analog converter to be used with analog PWM control IC’s. All the
clock signals required for the operation of each of the component blocks of the SRSG are
derived form a single source: a 3.6864MHz crystal oscillator for 60Hz grid frequency, or a
3.072MHz crystal oscillator for 50Hz grid frequency.
The design of the three-phase sinusoidal reference signal generator must meet the
following specifications:
1.- center Frequency of 60Hz,
2.- hold Range of ± 5% of the central frequency,
3.- reduced jitter,
4.- output Signals in-phase with the power grid,
5.- THD level of output signal below 1% at central frequency, and
6.- fault line threshold set at 50% of nominal value.
II.3.- DIGITAL METHODS FOR SINUSOIDAL SIGNAL GENERATION
Sinusoidal signal generators are usually referred as direct digital synthesizers [43], and
its basic structure is shown in Figure II.2. The phase accumulator generates the digital
representation of the phase angle θ of the sinusoidal signal to be generated. Its complexity
depends greatly upon the kind of phase-to-amplitude selected, it can be implemented as an
accumulator or, in some simpler implementations, as a binary counter [44].
Phase Accumulator
∆ωt
k
Phase
Register
Phase
k
Amplitude
m
Output
Filter
fout
k
fclk
Fig. II.2.- Block diagram of a direct digital synthesizer.
There are several ways to implement a phase-to-amplitude converter, some are based
on mathematical functions, while others rely on look-up tables or direct functions. In order to
select the converter that allowed to achieve the THD level of less than 1%, a comparison of
maximum THD level and circuit complexity was performed.
14
The methods studied for the implementation of the converter were:
1.- ωt (π – ωt) function [45],
2.- modified Taylor series cosine function [45],
3.- look-up table [45], and
4.- direct logic synthesis of LUTs.
II.3.1.- METHODS REVIEW
II.3.1.1.- ωt (π - ωt) function
An approximation to a sinusoidal wave can be achieved using
⎧ 4
⎪ π 2 ωt (π − ωt ) 0 ≤ ωt ≤ π
(
)
f ωt = ⎨
4
⎪ 2 ωt (π + ωt ) − π ≤ ωt ≤ 0
⎩π
(II.1)
This yields after a Fourier analysis to
F (ωt ) =
32 ⎛
1
1
⎞
sin(ωt ) + 3 sin(3ωt ) + 3 sin(5ωt ) + L⎟
3 ⎜
π ⎝
3
5
⎠
(II.2)
The third and fifth harmonics are 1/27th and 1/125th of the fundamental component and
could be neglected. However, since one of our design goals is to achieve a THD below 1%, it
is necessary to calculate its value using:
THD =
V32 + V52
V1
(II.3)
where
V3 is the RMS value of the third harmonic,
V5 is the RMS value of the fifth harmonic, and
V1 is the RMS value of the fundamental.
Equation (II.2) yields:
THD(%) =
(
32
π3
⋅ 313 ⋅
) +(
1 2
2
32
π
3
32
π3
⋅
1
2
⋅ 513 ⋅
)
1 2
2
⋅100 = 3.7891%
This THD value is higher than our design goal, and therefore this method of generating
a sinusoidal waveform was discarded.
15
II.3.1.2.- Modified Taylor Series Cosine function
Given the Taylor Series for sin(ωt) and cos(ωt):
sin(ωt ) = ωt −
cos(ωt ) = 1 −
ωt 3 ωt 5 ωt 7
3!
+
5!
−
ωt 2 ωt 4 ωt 6
2!
+
4!
−
+L
(0 ≤ ωt ≤ π/2)
(II.4)
+L
(0 ≤ ωt ≤ π/2)
(II.5)
7!
6!
These series can be truncated to use only the first three terms in order to reduce the
computational effort associated with raise to power operations. The calculation of sin(ωt) is
more complex than the one of cos(ωt) since its first three terms involve ωt, and obtaining ωt5
requires an extra multiplication. To reduce the complexity of the hardware needed to
implement (II.5), the equation can be approximated by
ωt
cos(ωt ) = 1 −
2
2
+
ωt 4
(0 ≤ ωt ≤ π/2)
32
(II.6)
The replacement of 4! with 32 is done to simplify the division, since 32 is a power of 2
and can be implemented with a shifting operation. This is a quarter wave representation of the
cosine waveform. To reduce the error produced by this approximation, the constant term of
(II.6) must be replaced by 1.043448 to generated a near zero output when ωt is π/2.
f (ωt ) = cos(ωt ) = 1.043448 −
ωt 2 ωt 4
2
+
32
(0 ≤ ωt ≤ π/2)
(II.7)
The Fourier series representation of the reduced Taylor series with only the first three
harmonic components is:
F (ωt ) = 1.05 cos(ωt ) − 0.007453 cos(3ωt ) + 0.001067 cos(5ωt )
(II.8)
The sinusoidal wave obtained in this approximation has a theoretical THD of
approximately 0.7170%. The actual value of the THD depends upon the width of the digital
representation of the operands in (II.7). Figure II.3 shows the waveforms obtained in
simulation for a 10 bits word width. Table II.1 shows the simulation results using data widths
form 8 to 16 bits, and the number of CPLD macrocells needed for its implementation using
three different structures for calculating ωt2.
16
(a) MATLAB simulation
(b) Pspice simulation
Fig. II.3.- Simulation results using a 10bits word width to calculate the Taylor Series.
Data width
(bits)
16
12
10
8
Table II.1.- THD of modified Taylor series
Matlab
Pspice
CPLD
CPLD
THD (%)
THD (%)
Macrocells
Macrocells
(array
(Wallace tree
multiplier)
multiplier)
0.7173
0.7319
936
919
0.7221
0.7352
763
761
0.8007
0.7892
706
691
1.6460
18.5721
575
422
CPLD
Macrocells
(optimized
squarer)
750
660
457
272
From Table II.1, the data width that gives a THD level below 1% and uses the
minimum number of macrocells is 10 bits. The calculus of ωt2 and ωt4 uses up to 90% of the
macrocells needed (16 bits case with array multiplier). To reduce the number of macrocells
used to implement the modified Taylor series, the multiplier function used to calculate ωt2 and
ωt4 must be replaced with a smaller, yet fast, implementation.
II.3.1.3.- Look-Up Table
The use of look-up tables (LUT) to implement a phase-to-amplitude converter, is
usually accomplished with a ROM that contains the LUT. LUT-based generators use two
words to represent the phase and amplitude information of the sinusoidal waveform. The
phase information is represented using a k-bit wide word, and can be expressed in terms of the
sample value or the phase increment value ∆ωt. The output frequency is a function of the
clock frequency fclk, the phase register width k and the phase increment ∆ωt, as follows:
f OUT =
∆ωt ⋅ f clk
,
2 k rads
∆ωt < 2 k −1 rads
(II.9)
Equation (II.9) can be simplified if ∆ωt is set to its minimum value. The result is:
f OUT =
f clk
2k
(II.10)
17
and in this case the length of the table is 2k.
The amplitude information is represented using an m-bit word; this width defines the
DAC resolution. The output sequence of the table is given by
φ (n ) ⎞
⎛
OUT (n ) = sin⎜ 2 ⋅π ⋅ k ⎟
2 ⎠
⎝
(II.11)
where φ(n) is an integer representing the nth value of the phase register.
The size of the ROM is m x 2k. When sizing the ROM, there are several trade-offs
involving the phase and the amplitude quantification errors. A small phase quantification error
can only be achieved with a large number of memory locations (a large k), but the larger the
ROM, the higher the energy consumption. In turn, a small amplitude quantification error
requires a wide word for the data stored into the ROM (a large m). A wide word means that
more than one ROM should be connected in parallel, increasing cost, board area and energy
requirements.
To obtain a shorter table, it is always possible to take advantage of the quarter-wave
symmetry in the sinusoidal wave. In this case, the length reduction is obtained at the expense
of two additional complementor (1’s complement) blocks, one at each end of the LUT as
shown in Figure II.4. In this approach, the LUT contains only one-quadrant of the sinusoidal
wave data, usually corresponding to the first one. The two most significant bits (MSB) of the
phase register are used to decode the wave quadrant, and the remaining bits are used to
address the LUT. The MSB determines the polarity of the output wave, and the second MSB
determines the slope of the amplitude.
Fig. II.4.- Block diagram of the generator using quarter-wave sinusoidal wave symmetry.
In this case, several combinations of m and k had to be tested to find the total harmonic
distortion (THD) of the synthesized sinusoidal wave before filtering. A series of Pspice
simulations were performed using the scheme of Figure II.2, with several values for k and m.
The results are listed in Table II.2.
18
k
4
5
6
7
8
9
10
11
THD8
(m = 8)
11.3761
5.6689
2.8684
1.4518
0.7906
0.5013
0.3812
0.3385
Table II.2.- THD as a function of k and m
THD12
THD15
Memory Cells/Memory device
(m = 12)
(m = 16)
(m = 8)
(m = 12)
(m = 16)
11.3720
11.3722
16 / 27C64
16 / 27C516 16 / 27C516
5.6584
5.6582
32 / 27C64
32 / 27C516 32 / 27C516
2.8326
2.8315
64 / 27C64
64 / 27C516 64 / 27C516
1.4180
1.4162
128 / 27C64 128 / 27C516 128 / 27C516
256 / 27C64 256 / 27C516 256 / 27C516
0.7082
0.7081
512 / 27C64 512 / 27C516 512 / 27C516
0.3578
0.3541
1024 / 27C64 1024 / 27C516 1024 / 27C516
0.1792
0.1772
2048 / 27C64 2048 / 27C516 2048 / 27C516
0.0872
0.0831
The values listed in the table were obtained taking into account the first 50 harmonics
(f50=3 kHz). According to the Fourier analysis of the generated waves, the first two harmonic
components to appear are 2k-1 and 2k+1. Therefore, if k is incremented by one, the frequency
of the first harmonic component will be nearly doubled.
Also, for k < 8, the width of the data word used in the LUT does not have a noticeable
effect on the THD, and the filtering requirements to obtain a high-quality sinusoidal wave can
be higher. For k ≥ 8, there is an improvement on the THD values.
On the other hand, it can be seen that, for a fixed value of k (k ≥ 8), there is a
noticeable improvement in the THD when m is increased from 8 to 12. However, when m is
further increased from 12 to 16, the THD improvement is quite low. Therefore, k and m can be
restricted to the following ranges:
a) 11 ≥ k ≥ 8
b) 12 ≥ m ≥ 8
The final values for k and m can be selected taking into account factors such as cost,
board space, energy consumption, etc. This approach can be used with FPGAs that provide the
capability of integrating ROM modules. CPLDs have fewer gates than FPGAs, and cannot be
used to implement LUTs directly.
II.3.1.4.- Direct logic synthesis of LUTs
LUTs can be transformed into a set of m combinational logic functions with k input
signals. It should be noted that, depending on the actual values of k and m, this could result in
a set of awfully large functions. This drawback can be solved, however, through a judicious
selection of k and m.
The combinational logic functions can be obtained using any of the various methods
available for minimizing logic function, like Karnough maps or the Quine-McClusky method.
A further reduction or rearrangement can be obtained when the programming file is generated.
Since the CPLD structure is based on logic macrocells, and a fixed number of cells is
available, it is important to obtain the simplest possible combinational functions.
19
The number of inputs to the logic functions is reduced when the scheme in Figure II.4
is selected for the task, since in this case, these functions will only generate the data for the
first quadrant of the sinusoidal wave. Its inputs are the k-2 least significant bits at the output of
the phase accumulator block, and will generate 2k-2 output data values.
The values of the output data words needed to generate a sinusoidal wave, in terms of
m and k, are given by:
⎛ 2 ⋅π
data (n ) = ( 2 m−1 − 1) ⋅ sin⎜ n ⋅ k
2
⎝
⎞ m−1
⎟+2
⎠
n = 0,1, 2,L, 2 k −2 − 1
(II.12)
where n is the equivalent of φ(n) used in equation (II.11).
Suitable values of m and k must be selected to implement the approach. Our goal is to
obtain a THD level below 1%. Taking into account the ranges previously specified for m and
k, setting m equal to 8 yields the minimum number of logic functions required for the
transformation of the LUT.
In order to select k, it is important to keep in mind that the complexity of the
combinational logic functions is proportional to this factor. Looking at Table II.2, it can be
seen that k values greater than 7 provide the desired THD level.
Once the minimum limit for k is set, a second criterion must be used to obtain suitable
values of k and m. A natural choice for this criterion is the silicon area needed for the
implementation. Table II.3 shows the number of macrocells needed to implement the LUT and
the complementor blocks. On the other hand, table II.3 shows the number of macrocells
needed to implement the LUT plus the phase accumulator and the complementor blocks.
k
4
5
6
7
8
9
10
11
20
Table II.3.- Number of macrocells
needed to implement the LUT
m=8
m = 12
m = 16
macrocells macrocells macrocells
8
8
11
14
20
30
42
49
12
12
16
20
27
47
76
111
16
16
20
28
36
56
86
180
Table II.4.- Number of macrocells needed to implement
the sine-wave generator and its THD level.
m=8
m = 12
m = 16
k
macrocells/THD(%) macrocells/THD(%) macrocells/THD(%)
4
5
6
7
8
9
10
11
28 / 11.3761
32 / 5.6689
35 / 2.8684
38 / 1.4518
45 / 0.7906
61 / 0.5013
70 / 0.3812
83 / 0.3385
33 / 11.3720
36 / 5.6584
39 / 2.8326
45 / 1.4180
53 / 0.7082
77 / 0.3578
100 / 0.1792
149 / 0.0872
37 / 11.3722
41 / 5.6582
43 / 2.8315
50 / 1.4162
64 / 0.7081
97 / 0.3541
137 / 0.1772
214 / 0.0831
To achieve the objective of a THD level below 1%, the values of m and k should both
be at least 8.
II.3.1.5.- Selection of the converter
The converters studied, and their parameters to achieve our THD level are summarized
in Table II.5.
Converter
Table II.5.- Summary of converters parameters.
Parameters
Implementation
Macrocells
ωt (π – ωt)
Taylor series
LUT
THD
< 1%
N
Y
Y
10 bits data words
k≥8
FPGA, CPLD
FPGA, EPROM
457- 706
-
Direct logic
Y
m = 8, k ≥ 8
FPGA, CPLD
45 – 83
Comments
Does not meet goal
Multiplier needs redesign
Not suitable for CPLD
Very compact, suitable for
CPLD implementation
Given the fact, that the devices available for the development of the sinusoidal
reference signal generator are CPLDs, the type of converter that fulfils the THD level and
requires a minimum of resources (macrocells) is the direct logic synthesis of LUTs.
For this converter, the value of m has been set to 8. This value was selected to
minimize the number of logic functions to be implemented. To select the value of k, another
criteria were set. A single-IC sinusoidal generator suitable for working with both analog and
digital PLL circuits providing the lowest THD level in the smallest package had to be
designed. This criterion was set to allow control circuits for single-phase AC power
electronics systems to use a low distortion sinusoidal waveform for its reference signal
requirements in a single IC.
Table II.6 shows the THD levels for each value of k and the related devices of the
Lattice MACH 4A family of CPLDs, and their packages. From this table, it can be seen that
the combination of k and m that matches this criteria is k=9 and m=8, an M4A5-64/32 device.
Therefore, this combination will also be used for the three-phase sinusoidal reference signal
generator.
21
k
4
5
6
7
8
9
10
11
Table II.6.- CPLD needed to implement the
sine-wave generator.
THD
CPLD
(%)
(Package)
11.3761
M4A5-32/32 (PLCC 44)
5.6689
M4A5-32/32 (PLCC 44)
2.8684
M4A5-64/32 (PLCC 44)
1.4518
M4A5-64/32 (PLCC 44)
M4A5-64/32 (PLCC 44)
0.7906
M4A5-64/32 (PLCC 44)
0.5013
MA45-96/48 (TQFP 100)
0.3812
MA45-96/48 (TQFP 100)
0.3385
II.4.- SYNCHRONIC
GENERATORS
SYSTEMS
FOR
REFERENCE
SIGNAL
Synchronization of reference signals for power electronics systems has been widely
studied. The review of the state of the art presented in Chapter I showed that many of those
control systems use phase-locked loops (PLL) as the synchronization method. The following
sections describe the basic operational principles of both analog and digital implementation of
PLLs.
II.4.1.- ANALOG PLL
The operational principles of PLLs had been widely described since its first description
by de Bellescize in “La Reception Synchrone” published in L’Onde Electrique in June of 1932
[46]. Gardner [46], Wolaver [47] and Best [48] present a clear description of both the general
operation and the characteristics of the block components of the PLLs.
The PLL has three basic components (Figure II.5):
1.- phase detector,
2.- loop filter, and
3.- voltage controlled oscillator.
Input
Signal
u 1(t)
u2(t)
Phase detector
Output
Signal
ud(t)
Loop
Filter
VCO
Fig. II.5.- Basic block diagram of PLL.
22
uf(t)
The phase detector (PD) compares between the phase of a periodic input signal and the
phase of the signal generated by the voltage controlled oscillator (VCO). The result of this
comparison is the phase difference between these two waves and it is represented as a voltage
signal. This voltage is then averaged using a filter and applied as control voltage for the VCO.
The control voltage on the VCO performs changes in the output frequency in order to reduce
the phase difference in the PD.
When the PLL reaches the locked state, the control voltage provided by the filter is
such that the output frequency of the VCO is the same of the input signal. In order to maintain
the voltage needed to keep the PLL in locked state, the output voltage of the PD must be nonzero, meaning that the PLL will operate with some phase error. A good loop design can
minimize this error.
Some of the signals of interest in a PLL circuit can be defined as:
1.- angular frequency ω1 of the reference signal u1(t),
2.- angular frequency ω2 of the VCO output signal u2(t),
3.- output signal ud(t) of the PD,
4.- output signal uf(t) of the loop filter, and
5.- phase error θe
II.4.1.1.- Phase Detector
As stated before, the PD compares the phases of the reference signal against the VCO
output signal, and provides a voltage that is proportional to the phase error θe, this is valid
within a limited range.
ud (t ) = K d θ e
(II.13)
where
Kd is the gain of the PD.
In the analog (or linear as referred by Best [48]) PLL the PD is implemented with a
four-quadrant analog multiplier. Most of the times, the input signal u1(t) is a sinusoidal
waveform with an angular frequency ω1; the VCO output signal u2(t) is a 50% duty cycle
square waveform with an angular frequency ω2, as shown in Figure II.6. For this kind of PD,
the input signal is usually defined as:
u 1 (t ) = U 10 sin (ω 1 t + θ 1 )
(II.14)
and the VCO output signal is usually a square waveform that can be written as a Walsh
function:
u2 (t ) = U 20 w(ω 2t + θ 2 )
(II.15)
23
u1
θ1
(a)
u2
1
θ2
-1
(b)
Fig. II.6.- Multiplier PD input signals. (a) signal u1(t) is a sinusoidal waveform. Dashed line with θ1=0;
solid line with θ1>0. (b) signal u2(t) is a square waveform. Dashed line with θ2=0; solid line with θ2>0.
Equation (II.15) can be replaced by its Fourier series:
4
⎡4
⎤
u2 (t ) = U 20 ⎢ cos (ω 2t + θ 2 ) +
cos (3ω 2t + θ 2 ) L⎥
3
π
π
⎣
⎦
(II.16)
The output signal of the PD is obtained by multiplying u1(t) and u2(t):
ud (t ) = u1 (t ) u2 (t ) = U 10 U 20 sin(ω1t + θ1 )
4
⎡4
⎤
× ⎢ cos (ω 2t + θ 2 ) +
cos (3ω 2t + θ 2 ) + L⎥
3π
⎣π
⎦
(II.17)
In locked state, the frequencies of u1(t) and u2(t) are identical and (II.17) becomes
⎡2
⎤
ud (t ) = U 10 U 20 ⎢ sin θ e + L⎥
⎣π
⎦
where θe is the phase error θ1 – θ2.
24
(II.18)
The first element of the series is the “dc” component required for the control input of
the VCO. The loop filter would eliminate the remaining elements of the series. If the phase
error is small, equation (II.18) can be rewritten as:
ud (t ) = Kd θ e
(II.19)
with
Kd =
2U 10 U 20
π
, called detector gain.
(II.20)
Equation (II.19) represents the linear model of this phase detector.
II.4.1.2.- Voltage Controlled Oscillator (VCO)
The frequency of the output signal of the VCO is set by the voltage signal uf(t), applied
to its control input. When uf is zero, the VCO generates an output signal at a frequency called
central frequency. The changes in this output frequency are proportional to the control
voltage:
ω 2 = ω c + Ko u f (t )
where
(II.21)
ω2 is the frequency of the VCO’s output signal,
ωc is the central frequency of the VCO,
Ko is the VCO gain factor.
II.4.1.3.- Loop Filter
There are two kinds of loop filters widely used (Figure II.7): passive and active filters.
Passive filters are simple and their performance is satisfactory in many cases. Active filters,
on the other hand, require the use of a high-gain DC amplifier.
Applying a Laplace transformation to equations (II.19) and (II.21) and using F(s) as
the equation describing the filters of Figure II.7, the transfer function of the PLL can be
written as:
Ko K d F (s )
Θ (s )
H (s ) = 2 =
Θ1 (s ) s + Ko K d F (s )
where
(II.22)
Θ2(s) is the phase angle of the VCO’s output signal,
Θ1(s) is the phase angle of the input signal.
By replacing the filter equations of Figure II.7, the transfer functions, undamped
natural frequency and damping factor of the PLL can be deducted. These equations are shown
in Table II.7. The expressions of the transfer functions show that the PLL is a second-order
system and classic control theory methods can be applied in the design.
25
ud(t)
Uf(s) =
sC1R2 + 1
U (s)
sC1(R1 + R2) + 1 d
uf(t)
Uf(s) =
C1 sC2R2 + 1
U (s)
C2 sC1R1 + 1 d
uf(t)
Uf(s) =
sC1R2 + 1
Ud(s)
sC1R1
uf(t)
(a)
ud(t)
(b)
ud(t)
(c)
Fig. II.7.- Filter used in PLL applications.
Filter
Fig. II.7 (a)
Table II.7.- PLL equations for different kinds of filters
Undamped natural
Damping factor
Transfer function
frequency
F(s)
ξ
ωn
2
⎛
ω n ⎞⎟
2
s⎜ 2 ζ ω n −
+ ωn
Ko K d
1
1 ω ⎛⎜ C R +
⎜
Ko K d ⎟
n⎜ 1 2
⎝
⎠
2
C1 (R1 + R2 )
Ko K d
⎝
2
2
s + 2 ζ ωn s + ωn
⎡⎛
Fig. II.7 (b)
G ⎢ s⎜ 2 ζ ω n −
⎜
⎢⎣ ⎝
⎤
⎞
⎟ +ω2⎥
n
Ko K d ⎟
⎥⎦
⎠
4
ωn
2
2
s + 2ζ ωn s + ωn
Fig. II.7 (c)
26
2
2 ζ ωn s + ωn
2
⎞
⎟⎟
⎠
2
s + 2 ζ ωn s + ωn
Ko K d
C1 R1
Ko K d
C1 R1
1
1 ω ⎛⎜ C R +
2 n ⎜⎝ 2 2 K o K d
1ω C R
2 n 1 2
⎞
⎟⎟
⎠
II.4.1.4.- Performance parameters
PLL circuits have several performance parameters [51], [56-60]. Four of the most
important are the hold range, the pull-in range, pull-out range and the lock-in range.
Hold Range.- It is defined as the frequency range in which the PLL is able to statically
maintain phase tracking. The PLL is conditionally stable only within this range.
Pull-in Range.- It is defined as the frequency range in which the PLL will acquire a
locked state.
Pull-out Range.- It is defined as the limit of dynamic stability for the PLL.
Lock-in Range.- It is defined as the frequency range over which the PLL acquires
phase without slips.
II.4.2.- DIGITAL PLL
The so-called “digital” PLL is basically an analog PLL [49], but with the phase
detector implemented digitally. It should be more properly called a hybrid PLL.
The three most important digital phase detectors used in hybrid PLLs are shown in
Figure II.8:
1.- the XOR gate [49, 50, 51],
2.- the edge triggered JK flip-flop [49, 50, 51], and
3.- the phase-frequency detector (PFD) [49, 50, 51].
UB
u1(t)
Ud(t)
u2(t)
“1”
u1(t)
Q
D
Ck
(a)
UP
P
FF
CLR
Ud(t)
u1(t)
J
Q
FF
u2(t)
_
Q
K
(b)
CLR
Ud(t)
u2(t)
ck
“1”
D
FF
Q
DN
N
(c)
Fig. II.8.- Most often used PDs in hybrid PLLs. (a) XOR gate, (b) edge triggered JK FF, (c) phase-frequency
detector.
27
The output of these PDs is used to control the count direction of the digital low-pass
filter (DLPF), but each one of them does it in a different way.
The XOR gate PD requires that both the input reference signal and the VCO’s output
signal be square waves. When the PLL is in locked state, the input signals of the PD are 90º
out of phase with each other. This condition represents a zero phase error, θe = 0 (Figure II.9
(a)). The output signal generated by the XOR gate PD has twice the frequency of u1 and a duty
cycle of 50%. Under this condition the average value of ud is considered as zero, or more
properly as the normal quiescent point of the detector. The real analog value depends upon the
high and low levels of the signal. When u2 lags u1, the phase error becomes positive and the
duty cycle of ud increases; this increase makes the average value of ud to become positive, as
shown in Figure II.9 (b).
θe = 0
u1
u2
_
ud = 0
ud
(a)
u1
u2
θe > 0
_
ud > 0
ud
(b)
Fig. II.9.- Waveforms of the XOR gate PD under (a) zero phase error, and (b) phase error greater than zero.
The linear range of operation of this PD is bounded to –π/2 < θe < π/2, when θe is
between these limits, ud is proportional to the phase error:
ud = Kd θe
(II.23)
The transfer function (ud/θe) of the XOR gate PD can be represented as a non-linear
function of the phase error as shown in Figure II.10.
state):
The value of Kd depends upon the values of Ud+ (in the high state) and Ud- (in the low
U
−U d −
Kd = d +
π
28
(II.24)
_
ud
Kd _π
2
-π
- π_
2
0
π_
2
π
θe
-Kd _π
2
Fig. II.10.- Phase detector output signal vs. phase error of the XOR gate PD.
One important drawback of the XOR gate PD is its performance when u1 and u2 are
asymmetrical. If this condition occurs, the output signal ud is clipped at some intermediate
level. This reduction of ud yields to a reduction of the loop gain of the PLL, smaller lockrange, etc.
The edge-triggered JK flip-flop (FF) PD operates properly with asymmetrical input
signals. The FF used in this detector differs from a regular JK FF in the way its output is
triggered. This FF is edge-triggered by the J and K signals instead of the normal clock signal.
When a positive-going edge is applied to the J input, the FF triggers its output to a
high state. On the other hand, when a positive-going edge appears in the K input, the FF
output is set to a low state. When the PLL is in locked state, θe = 0, u1 and u2 have opposite
phase, as shown in Figure II.11 (a). Under this condition, the PD output signal is in-phase with
u1, it has a 50% duty cycle and its frequency is the same of u1. If the phase error becomes
positive, the duty cycle of ud increases and the average value of ud becomes positive (Figure
II.11 (b)).
The linear operating range of operation of the Flip-Flop phase detector is bounded to
-π < θe < π. Within these limits, the phase error is defined using equation (II.23). The phase
detector output signal can be represented as a saw-tooth function of the phase error, as shown
in Figure II.12.
The value of Kd is half of the XOR gate PD:
U
−U d −
Kd = d +
2π
(II.25)
29
θe = 0
u1
u2
_
ud = 0
ud
(a)
u1
u2
θe > 0
_
ud > 0
ud
(b)
Fig. II.11.- Waveforms of the edge-triggered JK flip-flop PD under (a) zero phase error, and (b) phase error
greater than zero.
_
ud
Kd π
-π
0
π
θe
-Kd π
Fig. II.12.- Phase detector output signal vs. phase error of the edge-triggered flip-flop PD.
The PFD differentiates itself from the XOR gate and edge-triggered JK FF detectors in
the fact that its output depends on both the phase error, θe, and the frequency error, ωe=ω1–ω2.
The basic structure of the PFD is built around two D-FFs (Figure II.8 (c)), whose non-inverted
outputs are denoted UP and DN, respectively.
When the PFD generates a state where both UP and DN signals are in a high state, a
clear signal is generated to reset the FF outputs. This action limits the allowed states of ud to:
⎧+ 1, DN = 0 , UP = 1
⎪
ud = ⎨ 0 , DN = 0 , UP = 0
⎪− 1, DN = 1, UP = 0
⎩
30
(II.26)
The state change is produced by the positive-going edge of the input reference and the
VCO’s output signals. Figure II.13 shows the signals generated by this detector; when u1 and
u2 have a positive-going edge simultaneously, the output ud is in its 0 state, meaning that u1
and u2 are in-phase (Figure II.13 (a)). When u1 leads u2 (Figure II.13 (b)), the PFD toggles its
output ud from the 0 state to the +1 state. If u1 lags u2 (Figure II.13 (c)), the output ud is
toggled from 0 state to the –1 state.
The phase error range of the detector is from –2π to 2π. Within this range, ud is
defined by equation (II.23). The value of Kd for this detector is:
U
−U d −
Kd = d +
4π
(II.27)
The phase output signal variation of the PFD is shown in Figure II.14.
θe = 0
u1
u2
+1
PFD
0
state
-1
_
ud = 0
(a)
θe > 0
u1
u2
θe
+1
PFD 0
state -1
(b)
θe < 0
u1
u2
θe
+1
PFD 0
state -1
(c)
Fig. II.13.- Waveforms of the PFD under (a) zero phase error, (b) phase error greater than zero, (c) phase error
lesser than zero.
31
_
ud
Kd 2π
-4π
-2π
0
2π
4π
θe
-Kd 2π
Fig. II.14.- Phase detector output signal vs. phase error of the PFD.
II.4.3.- ALL-DIGITAL PLL
There are several differences between the all-digital PLL (ADPLL) and the “digital”
PLL of the previous section. The first one is the way they use the output signal of the phase
detector [51]. The digital-PLL uses the output of the PD to generate an analog voltage in the
continuous time. In the other hand, the ADPLL recognizes the output of the PD as a digital
quantity, either if it is a pulse train or a multi-bit word. Additionally, the ADPLL replaces the
analog loop filter with some kind of digital filter and the VCO with a digitally controlled
oscillator (DCO).
Figure II.15 shows the block diagram of an ADPLL. In the remaining of this section,
various implementations of each of its blocks are presented.
Input
Signal
u 1(t)
u2(t)
Phase detector
Output
Signal
ud(t)
Digital
Loop
Filter
uf(z)
DCO
Fig. II.15.- Block diagram of an all-digital PLL.
II.4.3.1.- Phase detector
In the previous section, three digital phase detectors were presented. Those detectors
can be equally used in ADPLL circuits. The XOR gate and the edge-triggered JK flip-flop can
be used without modification, however, in the case of the PFD, the transistor output circuit
must be replaced by a digital equivalent. Another consideration that must be made, is the
value of Kd (equations (II.24), (II.25) and (II.27)). For all-digital PLLs, the values of Ud+ and
Ud- must be set to +1 and –1 respectively. This assignment yields to:
Kd =
32
2
π
(XOR gate)
(II.28)
Kd =
Kd =
1
π
1
2π
(edge-triggered JK flip-flop)
(II.29)
(PFD)
(II.30)
The duty cycle (δ) of the signal u2(t) generated by an ADPLL might be of interest in
some applications, and for the previously mentioned phase detectors their duty cycle is
defined as:
⎛
⎝
1⎞
⎟
N⎠
(XOR gate)
(II.31)
⎛
⎝
M ⎞
⎟
2 K N ⎟⎠
(edge-triggered JK flip-flop)
(II.32)
⎛
∆F ⎞
(PFD)
(II.33)
δ = 0.5 ⎜ 1 ±
δ = 0.5 ⎜⎜ 1 ±
δ = 0.5 ⎜⎜ 1 +
⎝
⎟
fc ⎟⎠
where
N is a power of 2, and represents the maximum count of a feedback counter connected
between the DCO and the phase detector.
M is a power of 2, and multiplied by the ADPLL’s central frequency defines the clock
frequency of the digital filter,
K is a power of 2, and represents the maximum count of the digital filter,
∆F is the difference between the actual frequency of the input signal and the ADPLL
central frequency,
fc is the central frequency of the ADPLL.
Additionally, there are several implementations of phase detectors reported, some of
them use single-bit input signals [52], [54], [55], while others use multi-bit input signals [52].
For the development of this thesis, the emphasis is focused on single-bit detectors.
One variation of the edge-triggered JK flip-flop is presented in [52]. In this detector, a
n-bit counter is added to obtain a representation of the phase error, shown in Figure II.16. The
phase error is proportional to the output count. The operation of the counter is controlled by
the output Q of the flip-flop and the reference signal u1(t). The rising edge of u1(t) is used to
both reset the counter to zero, and set the output Q to a high state. The counter is stopped
when a rising-edge of u2(t) is applied to the flip-flop.
33
N = content ~ θe
U1
t
U2
U1
S
U2
Flip-Flop
R
Q
t
Enable
Counter
Clock Reset
Q
t
High-frequency Clock
N
Content
t
Fig. II.16.- Schematic diagram of edge-triggered JK flip-flop modified phase detector.
Olsson and Nilsson [54] present a modification of the PFD that reduces the deviation
of the phase error measured from the real one. This detector introduces three new output
signals: DIRECTION indicates if u2(t) is leading or lagging u1(t), EVENT gives an indication
of the phase error, and UPDATE a control signal for the filter loop of the ADPLL. Figure II.17
shows the phase detector and the waveforms produced when u2(t) leads and lags u1(t).
u1(t)
“1”
u1(t)
Q
D
Ck
u2(t)
UP
UP
DIRECTION
FF
DN
DIRECTION
CLR
EVENT
UPDATE
(b)
EVENT
u1(t)
CLR
u2(t)
ck
“1”
D
u2(t)
FF
Q
DN
UPDATE
UP
DN
DIRECTION
(a)
EVENT
UPDATE
(c)
Fig. II.17.- Modified PFD phase detector. (a) schematic diagram. (b) waveforms u2(t) leading u1(t).
(c) waveforms u2(t) lagging u1(t).
Another variation of the basic PFD is presented by Cheng et al [55]. This detector
structure is designed to reduce the jitter problem caused by current mismatch when the PFD is
used with charge pump circuits in hybrid PLLs. Figure II.18 shows the block diagram of the
detector. For the implementation of the phase detector, the basic structure of the PFD (Figure
II.8 (c)) is replaced by an edge detector built with inverter delay chains and nand gates; and
the flip-flops are replaced by transistor arrays. Figure II.18 shows the schematic diagram and
its all-digital version.
The operation of the phase detector can be summarized as follows: when the risingedge of u1(t) arrives, the state of the U and D signals is not affected. When the rising-edge of
u2(t) arrives, the state of U and D changes from low to high. If the falling-edge of u2(t) arrives,
34
the state of U is reset to low, meanwhile, D remains unchanged. If the falling-edge of u1(t)
arrives, the state of D is reset to low, and U remains unchanged.
u1(t)
PHASE
DETECTOR
u2(t)
U
UP
D
DOWN
Fig. II.18.- Block diagram of the modified PFD.
“1”
D
Q
D
Q
U
ck
R
Rd
u1(t)
D
Rd
u1(t)
“1”
u2(t)
D
ck
Sd
R
Sd
u2(t)
U
Su
Su
Fig. II.19.- Modified PFD. (a) schematic diagram, (b) all-digital equivalent.
The difference detector circuit is used to balance the currents processed by a charge
pump circuit (in an hybrid PLL). Figure II.20 shows the hybrid circuit implemented along
with a digital version for ADPLL applications. The circuit provides a pulse width difference
between U and D. The waveforms obtained with this phase detector are shown in Figure II.21
with u2(t) leading, lagging and in-phase with u1(t).
UP
D
U
UP
D
U
DOWN
U
D
DOWN
Fig. II.20.- Difference detector circuit. (a) hybrid implementation, (b) digital equivalent.
u1(t)
u1(t)
u2(t)
u2(t)
Rd
Rd
Sd
Sd
Su
Su
D
D
U
U
UP
UP
DOWN
DOWN
(a)
(b)
35
u1(t)
u2(t)
Rd
Sd
Su
D
U
UP
DOWN
(c)
Fig. II.21.- PFD waveforms, (a) u2(t) leads u1(t), (b) u2(t) lags u1(t), (c) u2(t) is in-phase with u1(t).
II.4.3.2.- Digital filter
When selecting a digital filter for an ADPLL, it is important to match the output
signals of the phase detector with its control signals [51], [52]. For most of the phase detectors
presented in 4.3.1, the digital filter can be implemented with a k-bit counter [51], [52]. If the
DCO has a center frequency equal to the nominal counter value, K = 2k, and the UP pulses
increases the counter value meanwhile DOWN pulses decreases it, the counter output can be
considered as an average of the pulses generated by the phase detector:
kout (z ) = ⎛⎜ 1 + z −1 + z − 2 + z −3 + L⎞⎟ θ e (z )
⎝
⎠
(II.34)
this can be translated to the equation of a digital integrator as:
kout (z )
1
z
=
=
1
−
θ e (z ) 1 − z
z −1
(II.35)
A digital filter is using an ordinary UP/DOWN counter as shown in Figure II.22. This
kind of filter preferably should be operated by an PD providing separated UP and DOWN
signals, but can be adapted to be used by single output PD. A pulse-forming network is used
to convert its input signals into a counting clock and a direction (up/dn) signal. This filter does
not give information about the size of the phase error, it only tells whether the phase u1(t) is
leading or lagging u2(t).
UP
content K ~ uf
DN
UP
from
Phase detector
DN
Clock
Pulse
forming
circuit
__
UP/DN
(a)
UP/DOWN counter
Clock
__
UP/DN
(b)
Fig. II.22.- Digital filter using a UP/DOWN counter. (a) block diagram, (b) waveforms.
36
The K counter [50], [52], Figure II.23, is one of the most important digital filters. This
filter always works with the XOR gate or the JK flip-flop PDs. It consists of two independent
up counters labeled as “UP counter” and “DOWN counter”. K is the modulus of both
counters, i.e. they both can count from 0 up to K-1, and the modulus can be controlled using
the K modulus control input, which is an integer binary number (k) that comply with K = 2k.
The clock signal used by this digital filter (K clock) is by definition M times the center
frequency of the ADPLL, M must be a power of 2 integer.
Both counters reset to 0 when their count exceeds K-1. The most significant bit of both
counters are used as output (Carry for the UP counter and Borrow for the DOWN counter).
The positive-going edges of these signals are used to control the frequency of the next stage
DCO.
1 cycle of u1(t)
K clock
Up counter
K clock
__
DN/UP
Up counter
Carry
Dn counter
Borrow
(a)
Dn counter
K modulus control
8
0
__
DN/UP
16
8
K/2
0
8
K/2
0
Carry
Borrow
(b)
Fig. II.23.- K counter digital filter. (a) block diagram. (b) waveforms.
UPDATE
EVENT
T2d
DIRECTION
UPDATE
REGISTER
+/REGISTER
+
0.5
X
W
Fig. II.24.- Recursive filter block diagram.
A different filter is presented in [54], and it is designed to work with the modified PFD
of Figure II.17. The filter consists of two main functions: the time to digital (T2d) block and
37
the recursive filter block, shown in Figure II.24. The time to digital block consist on a counter
that measures the phase error. The clock signal of this counter is connected to the output of the
DCO. This measurement is filtered by the recursive filter. The output of the filter is used as a
control word for the DCO.
II.4.3.3.- Digitally controlled oscillator (DCO)
Digitally controlled oscillators (DCO) can be implemented in numerous ways. Perhaps
the simplest DCO is built using an n-bit counter [52], shown in Figure II.25. This counter is
used to scale down the signal generated by a high-frequency oscillator. The n-bit parallel
output signal of the digital filter is used to control the scaling factor of the counter.
from
loop filter
N modulus
control
÷ N Counter
≈
OUT
Fixed high-frequency oscilator
Fig. II.25.- Block diagram of a ÷N counter DCO.
The Increment-Decrement (ID) counter DCO [50, 52] is shown in Figure II.26. This
DCO is designed to operate with digital filters that generate CARRY and BORROW signals. It
is sensitive to positive-going edges of the input signals; in the absence of carry and borrow
signals, the ID counter just divides the ID clock frequency by 2. Internally the ID counter has
a flip-flop (TFF), that toggles on every positive-going edge of the ID clock if there are no
carry and borrow signals.
If a carry pulse appears at its INC input, it will be processed only in the period when
the TFF is set to 1. If the carry appears when the TFF is set to 0, the TFF output is set to 1
during the next positive-going edge of the ID clock. It will stay at 0, however, during two ID
clock intervals thereafter. This means that the next IDout pulse is advanced in time by one ID
clock period. If the carry becomes 1 when the TFF is set to 1, the TFF output is set to 0 onto
the next two ID clocks. The output frequency of the ID counter cannot be as high as the
frequency of the ID clock, but at most two-thirds of that value.
A modified version of the ID counter is presented in [50]. This DCO overcomes the
non-homogeneous generation of output pulses. The state of the CARRY and BORROW signals
is sampled at each rising-edge of the ID clock. If a rising-edge of the CARRY signal is
detected, the internal counter (inside the LOADER block) is decremented by one. However, if
a rising-edge of the BORROW signal is detected, the internal counter is increased by one. If
any other condition of the CARRY and BORROW signals is present the counter preserves its
contents. The DIVIDER block is built using a down counter, which simply divides the ID
clock and when it reaches underflow state, the ID output is toggled and the DIVIDER loads
the contents of the LOADER. The CARRY and BORROW signals continuously adjust the
count of the LOADER. Figure II.27 shows the block diagram of the DCO.
38
ID clock
CP
Carry
INC
Borrow
DEC
OUT
IDout
ID clock
ID clock
Toggle - FF
Toggle - FF
Carry
(a)
advanced
Borrow
IDout
IDout
(e)
(c)
ID clock
Toggle - FF
ID clock
IDout
Toggle - FF
(b)
delayed
Carry
advanced
IDout
(d)
Fig. II.26.- ID counter DCO. (a) block diagram. (b) waveforms with absence of CARRY and BORROW signals.
(c), (d) waveforms when a CARRY signal appears. (e) waveforms when a BORROW signal appears.
CARRY
ID clock
BORROW
LOADER
DIVIDER
ID clock
ID clock
ID output
ID clock
Fig. II.27.- Block diagram of modified ID counter.
II.5.- PROPOSED SINUSOIDAL REFERENCE SIGNAL GENERATOR
DESIGN
II.5.1.- PHASE TO AMPLITUDE CONVERTER
As stated in 3.1.5, the phase to amplitude converter structure selected is the direct logic
synthesis of LUTs, and the values set for k and m are 9 and 8, respectively. These values allow
the generation of a low distortion waveform with relatively small equations for each of the
output signals.
The converter is based on the block diagram of Figure II.4. The use of the quarter
wave symmetry of the sinusoidal signal ease the obtension of the logical functions. Table II.8
lists the values of data(n) obtained for k = 9, and m = 8. The eight logic functions correspond
to R0 to R7. The address is obtained with the k-2 least-significant-bits at the output of the
phase accumulator.
39
Table II.8.- Values of data(n) for k=9 and m=8.
data(n)
R4
R3
n
Address
R7
R6
R5
R2
R1
R0
0
0000000
1
0
0
0
0
0
0
0
1
0000001
1
0
0
0
0
0
0
0
2
0000010
1
0
0
0
0
0
0
0
3
0000011
1
0
0
0
0
0
0
1
4
0000100
1
0
0
0
0
0
0
1
5
0000101
1
0
0
0
0
0
0
1
6
0000110
1
0
0
0
0
0
1
0
7
0000111
1
0
0
0
0
0
1
0
8
0001000
1
0
0
0
0
0
1
1
9
0001001
1
0
0
0
0
0
1
1
10
.
.
119
0001010
.
.
1110111
1
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
120
1111000
1
0
1
0
1
1
0
1
121
1111001
1
0
1
0
1
1
1
0
122
1111010
1
0
1
0
1
1
1
0
123
1111011
1
0
1
0
1
1
1
0
124
1111100
1
0
1
0
1
1
1
1
125
1111101
1
0
1
0
1
1
1
1
126
1111110
1
0
1
0
1
1
1
1
127
1111111
1
0
1
1
0
0
0
0
The value of Address is formed by the signals A6, A5, A4, A3, A2, A1, and A0, and it
is used as the input for Ri. The individual expressions for R0 through R6 can be simplified
using standard techniques such as Karnough maps. R7 is equal to 1.
R 6 = AD 6 + AD 5 ⋅ AD 4 + AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 ⋅ AD 2
(II.36)
R 5 = AD 6 ⋅ ( AD 5 + AD 4 )
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 + AD 2 ⋅ AD1)
(
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 + AD 2
(II.37)
)
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 + AD 2 ⋅ AD0 + AD 2 ⋅ AD1)
R 4 = AD6 ⋅ AD 5 + AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3
(
)
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 ⋅ AD 2 + AD 3 ⋅ AD1
+ AD6 ⋅ AD 4 ⋅ AD 4 ⋅ AD 3
(
)
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 + AD 3 ⋅ AD1 ⋅ AD0 )
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 + AD 2
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 + AD 3 ⋅ AD1 ⋅ AD0 )
40
(II.38)
R 3 = AD6 ⋅ AD 5 ⋅ AD 4
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 + AD 2 ⋅ AD1 + AD 2 ⋅ AD0 )AD1
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3
(
)
(II.39)
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 + AD 3 ⋅ AD1 + AD 2 ⋅ AD1 ⋅ AD0 )
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 + AD 3 ⋅ AD 2 ⋅ AD1)
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 + AD 3 ⋅ AD 2 + AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD1 ⋅ AD0 )
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD0 )
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 ⋅ AD 2 + AD 3 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
R 2 = AD6 ⋅ AD 5 ⋅ AD 4
(
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 ⋅ AD 2 + AD 2 ⋅ AD1 + AD 3 ⋅ AD1 ⋅ AD0 )
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 2 ⋅ AD1 + AD 3 ⋅ AD1 ⋅ AD0 + AD 2 ⋅ AD1 ⋅ AD0 )
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 ⋅ AD 2 + AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
)
⎛ AD 3 ⋅ AD 2 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⎞
⎟⎟
⎝ + AD 2 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎟⎟
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎝ + AD 2 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD1 ⋅ AD0
⎠
(II.40)
⎛ AD 3 ⋅ AD 2 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 + AD 3 ⋅ AD1 ⋅ AD0 ⎞
⎟⎟
⎝ + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎟⎟
+
⋅
⋅
+
⋅
⋅
⋅
AD
3
AD
1
AD
0
AD
3
AD
2
AD
1
AD
0
⎝
⎠
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
41
R1 = AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 3 + AD 2 ⋅ AD1)
⎛ AD 2 ⋅ AD1 + AD 2 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⎞
⎟⎟
⎝ + AD 3 ⋅ AD 2 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎛ AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD1 ⎞
⎟⎟
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎛ AD1 ⋅ AD0 + AD 3 ⋅ AD1 + AD 2 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD0 ⎞
⎟⎟
AD
3
AD
2
AD
1
AD
0
+
⋅
⋅
⋅
⎝
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎟⎟
⎝ + AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎛ AD 3 ⋅ AD 2 ⋅ AD1 + AD 3 ⋅ AD 2 ⋅ AD0 + AD 3 ⋅ AD1 ⋅ AD0 ⎞
⎜
⎟
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜ + AD 2 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⎟
⎜ + AD 3 ⋅ AD1 ⋅ AD0 + AD 2 ⋅ AD1 ⋅ AD0
⎟
⎝
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ( AD 2 ⊕ AD1 ⊕ AD0 )
⎛ AD 3 ⋅ AD 2 ⋅ AD1 + AD 2 ⋅ AD1 ⋅ AD0 + AD 2 ⋅ AD1 ⋅ AD0 ⎞
⎟⎟
⎝ + AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
(
(II.41)
)
R0 = AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ AD 3 ⋅ ( AD 2 ⊕ AD1)
⎛ AD 3 ⋅ AD1 + AD1 ⋅ AD0 + AD 2 ⋅ AD1 ⎞
⎟⎟
⎝ + AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD0 ⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎟⎟
⎝ + AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎟⎟
⎝ + AD 3 ⋅ AD 2 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
(II.42)
⎛ AD 2 ⋅ AD1 ⋅ AD0 + AD 2 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD0 ⎞
⎟⎟
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
⎛ AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⎞
⎟⎟
⎝ + AD 3 ⋅ AD 2 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD1 ⋅ AD0
⎠
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ ⎜⎜
+ AD6 ⋅ AD 5 ⋅ AD 4 ⋅ AD1
(
+ AD 6 ⋅ AD 5 ⋅ AD 4 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD1 + AD 3 ⋅ AD1 ⋅ AD0 + AD 3 ⋅ AD 2 ⋅ AD0
)
As stated before, in this approach two additional complementor blocks are needed. The
relationship that applies to the one located at the output of the phase-accumulator is:
AD (i ) = A(i )⋅ A( k − 2) + A(i )⋅ A( k − 2)
42
i = 0,1, 2, ... , k − 3
(II.43)
where A(i) is the ith bit of the phase-accumulator, and A(k-2) is the second MSB of the phaseaccumulator. In turn, the relationship that applies to the complementor block at the output of
the phase-to-amplitude converter is:
D (i ) = R (i )⋅ A(k − 1) + R (i )⋅ A( k − 1)
i = 0,1, 2, ... , m − 1
(II.44)
where R(i) is the ith output bit generated by the combinational logic functions block, and
A(k-1) is the MSB of the phase-accumulator.
These equations can be implemented using XOR functions. The block diagram of the
phase to amplitude converter with the complementor blocks is shown in Figure II.28.
COMPLEMENTOR
A0
I15
A1
I14
I13
I12
I11
R2
AD3
R3
AD4
R4
AD5
R5
AD6
R6
D1
R2
D2
R3
D3
R4
D4
R5
I3
AD6
I9
AD2
D0
R1
I4
AD5
I10
A6
A7
R1
I5
AD4
A5
AD1
R0
I6
AD3
A4
R0
I7
AD2
A3
AD0
I8
AD1
A2
COMPLEMENTOR
COMBINATIONAL
AD0
D5
R6
I2
I18
A8
I17
D6
D7
Fig. II.28.- Block diagram of phase-to-amplitude converter with complementor blocks.
To complete the scheme of Figure II.4, the phase accumulator must be replaced with a
9 bit binary counter. This counter generates the input signals A0 to A8, and will be used in the
feedback path of the ADPLL. Figure II.29 shows the sinusoidal waveform obtained with this
generator controlled by an analog PLL; the generator included a shift correction scheme.
Fig. II.29.- Experimental waveform obtained with the generator.
43
II.5.2.- ALL-DIGITAL PLL
The design of the ADPLL for the sinusoidal reference signal generator is based on the
block diagram of Figure II.30. The ADPLL is configured as a frequency multiplier. The
number of bits (n) of the ÷N counter is defined by the input word of the phase-to-amplitude
converter designed in section 5.1 (n=9) and sets a value of 512 for N.
MFc
ADPLL
u1(t)
u1
u2(t)
u2
Output
NFc
MFc
ud(t)
Input
PHASE_DETECTOR
uf(t)
Output
N
uO(t)
DCO out
Digital Controlled
Oscilator
Digital Low-Pass
Filter
MSB
Nfc
Control Output
ck
FEEDBACK COUNTER
Fig. II.30.- Block diagram of an ADPLL with divide-by-N counter in the feedback loop.
The phase detector must be selected taking the duty cycle of the generated signal as the
primary restriction. This restriction is set by the goal of the sinusoidal reference signal
generator to produce a symmetrical sinusoidal signal. Using equations (II.31), (II.32) and
(II.33), the variation of the duty cycle can be found.
For equation (II.32), the value of
M
can be derived from [52]:
2K N
M ⋅ fc
2⋅ K ⋅ N
(II.45)
M
∆f
=
2 ⋅ K ⋅ N fc
(II.46)
∆f =
yielding
where:
fc is the central frequency of the ADPLL, set at 60Hz,
∆f is the holding range of the ADPLL, set at ± 3Hz.
Substituting the values of ∆f and fc in equation (II.46):
44
M
3 1
= =
2 ⋅ K ⋅ N 60 20
(II.47)
∆F
is equivalent to (II.46), yielding the same result
fc
of equation (II.47). Table II.9 shows the expected duty cycle values for the different phase
detector evaluated. It becomes clear that the phase detector that has the narrowest variation
around 50% is the XOR gate detector, given the design restrictions on holding range.
For equation (II.33), the value of
Table II.9.- Expected duty cycle vs. Phase Detector
Duty Cycle
Phase Detector
Minimum (%) Maximum (%)
XOR gate
49.90
50.09
Edge-Triggered JK FF
47.50
52.50
50
52.50
PFD
(at central
(at both limits of
frequency)
the holding range)
From the Digital Filters reviewed in section 4.3.2, the best suited to be used with an
XOR phase detector is the K-counter filter. To select the values of K and M, equation (II.45) is
used again to obtain their relationship:
M ∆f ⋅ 2 ⋅ N
=
K
fc
(II.48)
Since there are two variables one must be set “arbitrarily”. In this case, the value of K
has been set at 32 (5-bit counter). Using this value in equation (II.48), the resulting value of M
is 1638.4. But, since by definition M must be a power of two (1638.4=210.67), this value must
be rounded up to the next power of two (M=211=2048). If a lower value (M=210=1024) is
used, the holding range is reduced. With these new values of K and M, the holding range of
the ADPLL is:
∆f =
M ⋅ fc 2048 × 60 Hz
= 3.75 Hz
=
2 ⋅ K ⋅ N 2 × 32 × 512
(II.49)
The DCO typically used with a K-counter filter is the ID counter. Its clock frequency
is set using:
NFc = 2 ⋅ N ⋅ fc
(II.50)
In our case:
NFc = 2 ⋅ 512 ⋅ 60 Hz = 61,440 Hz
(II.51)
45
Figure II.31 shows the block diagram of the ADPLL using the selected components.
MFc
ADPLL
u1(t)
u2(t)
u1
NFc
MFc dec
Enable
dec Nfc
Out
Dn/Up
u2
inc
PHASE_DETECTOR
K-COUNTER
ID-COUNTER
Digital Filter
Digital Controlled
Oscilator
N
Qn
DCO out
inc
ck
FEEDBACK COUNTER
Fig. II.31.- Block diagram of ADPLL.
The ADPLL of Figure II.31 can be modified to reduce the jitter effect [52], [53]. This
reduction can be achieved by modifying the basic structure of the K-counter filter introducing
an enable input (EN) to control its operation. This input is connected to the output of the XOR
gate phase detector. The second modification is using the second most-significant-bit of the
÷N counter to control the direction of the count of the filter (Dn/Up). The modified structure is
shown in Figure II.32.
MFc
ADPLL
u1(t)
u2(t)
u1
NFc
MFc dec
Enable
dec Nfc
Out
EN
u2
inc
Dn/Up
PHASE_DETECTOR
DCO out
inc
K-MODULUS
ID-COUNTER
Digital Low-Pass
Filter
Digital Controlled
Oscilator
Qn-1
Qn
N
FEEDBACK COUNTER
Fig. II.32.- ADPLL with reduction jitter connection.
For this structure the holding range is defined [52] as:
∆f =
46
M ⋅ fc
(2 ⋅ K + 1) ⋅ 2 ⋅ N
(II.52)
It becomes clear that, in order to maintain a holding range of ±3 Hz, one of the variables
in equation (II.52) must to be adjusted. From equation (II.52) we have:
M=
∆f ⋅ (2 ⋅ K + 1) ⋅ 2 ⋅ N
(II.53)
fc
Using K=32, N=512, fc=60 Hz and ∆f = 3 Hz, equation (II.53) yields to value of M of
3328. Once again, this value (3328=211.7) needs to be rounded to the next power of two. The
new value of M is set to 212=4096, which sets the holding range to 3.692 Hz. The frequency of
the K-counter clock can now be calculated as:
Mfc = M ⋅ fc
(II.54)
The value of Mfc is set to 245,760 Hz.
Summarizing, the parameters needed for the design of the functional blocks of the
ADPLL are: N = 29 = 512, K = 25 = 32, M = 212 = 4096, Nfc = 61,440 Hz, Mfc = 245,760 Hz.
The schematic diagrams of the actual implementation of the K-counter filter and the IDcounter DCO are shown in Figures II.33 and II.34, respectively.
DnUp
En
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
dec
D
Q
D
Q
D
Q
D
Q
D
Q
inc
MFc
Fig. II.33.- Schematic diagram of the K-counter filter.
nNFc
NFc
x5
x17
x1
x1
inc
x5
x9
x13
x17
x9
x5
x11
x7
x17
nNFc
x3
dec
x13
nNFc
x7
NFc
x15
Nfc
x14
x11
x16
x14
x5
x17
x3
J
Q
x17
IDout
K
Fig. II.34.- Schematic diagram of ID counter DCO.
47
II.5.3.- PHASE SHIFT CORRECTOR
In a PLL, there is a phase shift or phase error φe between the input and output signals.
In the case of the ADPLL, this phase shift depends upon the type of phase detector [52]. For a
XOR gate detector the error is between –π/2 and π/2, and is zero at the central frequency.
This performance parameter is very important for the operation of the phase-toamplitude converter. One of the design objectives is the generation of a sinusoidal waveform
in phase with the utility. At first glance, there are two options: to externally correct the shift
before generating the sinusoidal signal, or to modify the shift within the ADPLL.
The first option requires the measurement of the phase shift error so that it can be
corrected. Measuring phase shift error at the rising edge of the input signal, the correction is
made by subtracting the error from the current value of the ÷N counter. The proposed
implementation is shown in Figure II.35.
M fC
u1(t)
u2(t)
Phase
Detector
Qn-1
EN
K Counter
(FILTER)
N fC
ID Counter
(DCO)
ID output
N
Qn
LATCH
n BITS
n BITS
ADDER
CORRECTED
PHASE
Fig. II.35.- Block diagram of the first proposed modification.
The second approach requires that the ÷N counter be adjusted in order to “move” the
central frequency of the ADPLL. The feedback ÷N counter is replaced by an ÷N/L counter
followed by an ÷L counter. The ÷L counter is used to measure the phase shift between the
input signal and the ADPLL output. The ÷N/L counter is used to adjust the loop central
frequency. The adjustments of this counter must be made when the ADPLL is in the locked
condition, so a Lock Detector is needed. The block diagram of the approach is shown in
Figure II.36.
This solution is more complex than the previous one because the lock condition must
be achieved first, and then the modulus of the N/L counter must be adjusted accordingly with
the phase error sampled in the latch. In order to restrain the circuitry from growing
unnecessary, the option shown in Figure II.35 was chosen.
48
M fC
u1(t)
Phase
Detector
u2(t)
EN
N fC
K Counter
(FILTER)
Qn-1
ID Counter
(DCO)
ID output
N/L
L
Qn
N/L MODULUS
ADJUST
PHASE
DATA
LATCH
LOCK
DETECTION
LOCK
DETECTOR
Fig. II.36.- Block diagram of the second proposed modification.
The scheme shown in Figure II.35 uses an addition operation instead of a subtraction.
To perform the phase adjustment an inverted output in the latch is needed. This approach is
simple and effective, and the schematic diagram is shown in Figure II.37.
U1
N0
N1
N2
N3
N4
N5
N6
N7
N8
D
D
D
D
D
Q
Q
Q
Q
Q
Q
CI
B SUM
CO
A
CI
B SUM
A
CO
CI
B SUM
A
CO
CI
B SUM
A
CO
CI
B SUM
A
CO
A5
A4
A3
A2
A1
B SUM
CO
A
D
A0
A7
A6
CI
B SUM
A
CO
A8
CI
B SUM
CO
A
Q
CI
B SUM
A
CO
Q
D
Q
D
D
Fig. II.37.- Schematic diagram of Phase Shift Corrector.
49
The phase shift corrector has also been assigned the task of generating two additional
signals D120 and D240. These signals are 120 and 240 degrees shifted from the mostsignificant-bit of the corrected phase A8. The decision block uses D120 and D240 as reference
signals for the ADPLL when it detects a faulty line voltage. The listing of the code used to
generate these signals is shown in Table II.10.
Table II.10.- Code listing for the generation of internal reference signals.
MODULE PHASE_BC
INTERFACE (N0, N1, N2, N3, N4, N5, N6, N7, N8 -> D120, D240);
TITLE 'PHASES B and C'
DECLARATIONS
N8..N0 pin;
D120, D240 pin;
EQUATIONS
D120 = (!N8 $ (N7 & (N6 # N5 & (N4 # N3 & (N2 # N1 & N0)))));
D240 = (N8 $ (N7 # N6 & (N5 # N4 & (N3 # N2 & N1))));
END
II.5.4.- DECISION BLOCK
The decision block consists of two sub-blocks: the line-fault detector and the rule
decoder blocks.
The line-fault detector is designed around two functions: a digital window comparator
that indicates when the input signal is in the neighborhood of the zero crossing point; and a
fault detector that measures how long the window is active. A flag must be set when the
maximum time allowed for the near zero window is exceeded, indicating that the input signal
is either absent or just below its minimum amplitude.
In order to implement the logic array, which decides what to do when a voltage sag or
an interruption occurs, we needed a circuit to signal when a line voltage was absent or out of
range. In this case we set the threshold at 50% of the nominal value. With this threshold
defined, the search for alternatives to develop the line fault detection (LFD) circuit was carried
out. The structure should include a window comparator centered at zero and a counter to
measure how long the signal is inside the window. If it remains for a long time, a flag must be
set, meaning that there is a line fault.
The digitalized signal obtained form an 8 bit ADC has the zero level at 07Fh or 080h,
the window width was set at 06h, so the lower limit of the windows is 07Ch and the upper
limit is 083h. This window represents five conversion cycles for a nominal voltage waveform
using an 8-bit ADC with a 32.55 µs sampling rate. For a 50% input signal this window
represents eleven cycles.
50
The digital window comparator is based on two adder structures coupled together with
a NOR gate. The first adder detects when the input signal in entering the window from values
greater than 083h and its structure is based on the following operation:
(digitalized number) + 083h,
if carry = 1, the number is outside the window,
otherwise (carry = 0) the number can be inside the window.
The second adder detects if the input signal is entering the window from values lower
than 07Ch and its structure is based on the following operation:
not(digitalized number) + 083h,
if carry = 1, the number is outside the window,
otherwise (carry = 0) the number can be inside the window.
The output signals of these two structures are combined into an OR gate (to obtain an
active low signal) or a NOR gate (to obtain an active high signal). A reduced logic circuit of
the window comparator is shown in Figure II.38.
A7
A6
A5
A4
A3
A2
A7
A6
A5
A4
A3
A2
1 BUF
1
2
3
4
5
U77
2
U78
1
6
OR5
A7
1 BUF
A6
A5
A4
A3
A2
1
2
3
4
5
U83
2
1
2
U81
AND5
2
U79
AND2
3
1
2
U82
NOR2
U80
NOR2
3 window
3
6
Fig. II.38.- Digital window comparator.
The circuit that determines if the input signal has remained for too long near zero is
built with a four-bit counter that stops counting when it reaches eleven. When the counter
reaches eleven, it sets a flag (active low) meaning that the input signal is out of range or
missing. The flag remains set until the window comparator output signal is set low. The circuit
diagram of the counter is shown in Figure II.39.
Combining the circuits of Figures II.38 and II.39, we can build a single-phase line fault
detector. For a three-phase implementation we need to use three of them.
The first tests of the line-fault detector where aimed at verifying the behavior of the
window comparator. The amplitude of the input signal was lowered and the window area
enlarged at the zero crossing point. However, when the amplitude was low enough to set the
line-fault flag, the flag remained reset. After further review, analysis and simulation, the fault
was traced to a glitch occurring during the 011111xxb to 100000xxb (and vice versa)
transitions at the input (Figure II.40).
51
U70
ck
FALLA
window
U75
1
2
3
1
HI
4
2
3
Q
5
CLK
K
Q
6
4
R
AND3
J
JKFFR
U71
1
2
Q
5
CLK
K
Q
6
4
R
3
J
1
2
3
4
NAN4
U86
5
FALLA
JKFFR
U72
U76
1
1
3
2
2
Q
5
CLK
K
Q
6
R
3
J
4
AND2
JKFFR
U84
1
4
3
J
Q
5
CLK
K
Q
4
AND3
2
6
R
U85
1
2
3
JKFFR
Fig. II.39.- Digital counter of the line-fault detector.
Fig. II.40.- Simulation waveforms. The upper waveform is the window comparator output. The
lower waveform is the T-type FF output.
Several solutions were proposed and tested, both in simulation and experimentally.
The first one was aimed at eliminating the propagation time causing the glitch. To accomplish
this task, the definition of the window comparator was changed from:
W=
( ADC_07 ∗( ADC_06 + ADC_05 + ADC_04 + ADC_03 + ADC_02))
+ ( ADC_07 + ( ADC_06 ∗ ADC_05 ∗ ADC_04 ∗ ADC_03 ∗ ADC_02 ))
(II.55)
W=
ADC_07 ∗ ADC_06 ∗ ADC_05 ∗ ADC_04 ∗ ADC_03 ∗ ADC_02
+ ADC_07 ∗ ADC_06 ∗ ADC_05 ∗ ADC_04 ∗ ADC_03 ∗ ADC_02
(II.56)
to
This modification worked very well in the simulator, however, when it was
programmed into the CPLD, the glitch still appeared. Some other changes were tried, all of
them focused at eliminating the glitch, but none of them worked. This led to pursue a different
solution. Instead of eliminating the glitch, it would be better to eliminate its effect upon the
52
fault detector. This meant a major change in the interface between the window comparator and
the fault detector. Originally, the low state of W was used as a reset for the counter inside the
fault detector, but the glitch forced us to change this scheme.
The first change performed was the addition of a glitch-remover circuit to the window
comparator. The glitch-remover was designed around a two-bit counter whose outputs is 00b,
10b, 11b, and is reset when the digital input is 011110xxb or 100001xxb. After the counter is
reset to 00b, the first rising edge at the window comparator’s output causes the counter to
increase its count to 10b. When the glitch appears, the count is further increased to 11b. The
MSB of the counter is used as a glitch-free version of the window comparator output. Two
additional output signals were added to the structure: cwindow (complementary to window),
and clrw (clear window), to be used in the line-fault detector. The final structure of the
window comparator is shown in Figure II.41.
WINDOW COMPARATOR
A7
A6
A5
A4
A3
A2
GLITCH-REMOVER
cwindow
I54
I75
I58
I80
I53
W1
D
Q
kk
D
Q
window
I56
C
C
I84
I52
I57
I55
I85
clrw
clrw
I98
I104
I103
I102
I91
I101
I97
I92
I100
I96
I95
I94
I90
I93
I99
Fig. II.41.- Window comparator with glitch-remover circuit.
The second change was the inclusion of a hysteresis control for the flag latch. This is a
combinational circuit that generates a trigger signal whenever the state of the flag latch needs
to be changed; i.e., when the analog input falls below the minimum threshold (the flag must be
set) and when the analog input returns to a level above this threshold (the flag must be reset).
The circuit designed is shown in Figure II.42.
The hysteresis feature was added to eliminate the bouncing of the flag state when the
analog input signal is close to the threshold. The threshold for setting the line-fault flag was
set at 4.28 Vp and the reset threshold at 4.34 Vp.
The task of the Rule Decoder Circuit is to define what should be done when one or
more line voltage signals are out of range. Since there are three input voltage signals, the
number of rules to be dealt with is eight, as shown in Table II.11. A line voltage was
considered as out of range when its instantaneous value is less than 50% of nominal for more
than 11 sampling cycles; otherwise, it was considered as in range.
53
Fig. II.42.- Line-fault detector.
Table II.11.- Decision rules
Rule
54
Condition
1
All three line voltages are in range.
2
Only line voltage phase A is out of range.
3
Only line voltage phase B is out of range.
4
Only line voltage phase C is out of range.
5
Only line voltage phase C is in range.
6
Only line voltage phase B is in range.
7
Only line voltage phase A is in range.
8
All three line voltages are out of range.
Action
Use MSB of line voltage digitalization as input for
ADPLL.
Use MSB of ADPLL phase C feedback bus shifted
120° as input for ADPLL phase A.
Use MSB of ADPLL phase A feedback bus shifted
120° as input for ADPLL phase B.
Use MSB of ADPLL phase B feedback bus shifted
120° as input for ADPLL phase C.
Use CK60 as input for ADPLL phase A.
These rules are implemented using the coding shown in Table II.12.
Table II.12.- Rule decoder coding.
MODULE D_BLOCK
INTERFACE (F1, F2, F3, ADC_A_07, ADC_B_07, ADC_C_07, DA120, DA240, DB120, DB240, DC120,
DC240, CK60 -> ADPLL_A, ADPLL_B, ADPLL_C);
TITLE 'DECISION BLOCK'
F1, F2, F3 pin; "Fault Flags
ADC_A_07, ADC_B_07, ADC_C_07 pin;
DA120, DA240 pin;
DB120, DB240 pin;
DC120, DC240 pin;
CK60 pin;
ADPLL_A pin;
ADPLL_B pin;
ADPLL_C pin;
FF = [F3..F1]; "Fault Condition
EQUATIONS
"FAULT DECODER EQUATIONS
Va Vb Vc
when (FF == 7) then {
ADPLL_A = ADC_A_07;
ADPLL_B = ADC_B_07;
ADPLL_C = ADC_C_07;}" 1 1 1
ADPLL_A = ADC_A_07;
ADPLL_B = DA120;
ADPLL_C = DA240; }"
1
ADPLL_A = DB240;
ADPLL_B = ADC_B_07;
ADPLL_C = DB120; }"
0 1 0
ADPLL_A = DC120;
ADPLL_B = DC240;
ADPLL_C = ADC_C_07;}"
0 0 1
ADPLL_A = ADC_A_07;
ADPLL_B = ADC_B_07;
ADPLL_C = DB120; }"
1 1 0
ADPLL_A = ADC_A_07;
ADPLL_B = DA120;
1 0 1
ADPLL_A = DC120;
ADPLL_B = ADC_B_07;
0 1
1
ADPLL_A = CK60;
ADPLL_B = DA120;
ADPLL_C = DA240;}"
0
0
0
0
0
END
55
II.5.5.- CLOCK SIGNALS GENERATOR
The clock generator block provides the timing required by the A/D converters
(ADC_ck), the ADPLL´s digital filter (MFc) and DCO (NFc). The frequencies provided
comply with the following relationships:
MFc = M ⋅ fc = 4096 ⋅ 60Hz = 245,760 kHz = 3'686,000Hz/15
(II.57)
NFc = 2 ⋅ N ⋅ fc = 2 ⋅ 512 ⋅ 60 Hz = MFc/4 = 61,440 Hz
(II.58)
ADC_ck = 512 ⋅ 60 Hz = 30,720 Hz
(II.59)
These frequencies are derived from the main crystal generator using the circuit shown
in Figure II.43. As an aid in circuit debugging, a pulse train with a 0.4666 duty cycle is
generated with I26, I17 and I28.
NFc
I38
ADC_ck
q5
I33
q6
D
I32
Q
I31
D
MFc
Q
D
q5
I37
I36
q1
q2
q3
q4
Q
q6
I35
D
I26
Q
MFc
I29
C
I28
clr
I17
q1
I8
q2
D
Q
I7
q3
D
Fck
Q
q1
I6
q4
D
Q
D
q2
C
C
I12
Q
q3
C
I11
I5
C
I10
I9
I16
clr
Fig. II.43.- Initial clock signals generator.
LINE_FREQ
CKin CK60
I39
xtal
*
I4
*
FREQ_DIV
ADC_ck
*
I3
MFc
*
I2
NFc
*
I5
Fck
I1
ADC_ck
MFc
NFc
Fig. II.44.- Final block diagram of the clock generator.
56
I40
CK60
To provide the 60 Hz signal required by the modification in the rule decoder, the
ADC_ck signal is simply divided by 512 using a nine-bit counter. The final structure of this
block is shown in Figure II.44.
II.5.6.- ANALOG INTERFACE
The sinusoidal reference signal generator (SRSG) must be interfaced with the power
grid to obtain information about frequency, amplitude and phase of the input voltages. In
some cases, it requires an interface with analog processing stages. The block diagram of the
array is shown in Figure II.45, and the schematics for both input and output stages are shown
in Figures II.46 and II.47.
Mfc
Va
ADC
DAC
V’a
Vb
ADC
DAC
V’b
Vc
ADC
DAC
V’c
Fig. II.45.- Block diagram for the prototype.
R17
adj1
3k
4
8
1
10k
10k
R19
2
2
U9
LM10
6
U10
Va1
Va1
2
3
Vin
GND
7
5
adj1
3
ref1
ref1
Ci2
0.1u
+
3
R18
-
1
2
VCC
Vcc
ref1
clk
1
+5v
ADCA_ck
Ci1
0.1u
4
5
6
7
Ci3
10u
1
16
R16
Vref
Vdd
J16
Va
CONVST
CS
RD
BUSY
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
ADCA_7
ADCA_6
ADCA_5
ADCA_4
ADCA_3
ADCA_2
AD7819
Fig. II.46.- ADC input circuit (per phase).
The analog to digital interface is built using a LM10 (op-amp with programmable
voltage reference) and an AD7819 (8-bit ADC with 4.5 µs conversion time). The LM10’s
main amplifier is configured as a difference amplifier. This configuration is required to
introduce an offset level and attenuate the AC voltage derived from the power grid, in order to
provide an unipolar signal at the input pin of the ADC. The offset level is adjusted by varying
the gain of the reference voltage amplifier. The clock signal generator block of the SRSG
provides the start-of-conversion signal; when the conversion is completed, the ADC sends an
end-of-conversion signal back to the SRSG. When this signal is acquired, the SRSG latches
the result of the conversion and proceeds with the process.
57
+5v
+5v
Ca1
Ca2
0.1u
11
7
5
VOUT
VOSENSE
CS
CE
15
14
ro
R4
10k
3
2
+
U2
J13
6
1
2
LM10
HEADER 2
ref
GND
VOSELECT
16
4
8
1
D0
D1
D2
D3
D4
D5
D6
D7
12
10
9
0.1u
ro
ref
13
1
2
3
4
5
6
7
8
VCC
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
GND
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
U1
AD558
Ca3
0.1u
R6
10k
ro
-5V
R5
J12a
10k
1
2
3
GND
-5v
TP1
1
1
2
R7
1k
3
DAC
+5v
HEADER 3
Fig. II.47.- DAC output circuit (per phase).
The digital to analog interface can be described as a mirror structure of the analog to
digital interface explained above. The interface is built using an AD558 (8-bit DAC with a 1.5
µs settling time) and a LM10. The AD558 provides an analog equivalent of the digital output
generated by the SRSG. This signal is unipolar and needs to be adjusted in amplitude and
shifted to form an AC signal. Once again the voltage reference amplifier of the LM10 is used
to provide an offset level, converting an unipolar signal into a bipolar or AC signal. The main
amplifier of the LM10 is configured as an adder amplifier, and its gain is adjusted to provide
an amplitude adequate for the control stage.
II.6.- SUMMARY
In this chapter, the structure of the sinusoidal reference signal generator was presented,
as well as its design specifications. The basic operational principles of the phase-to-amplitude
converters and phase-locked loops were also covered. Among several methods reported for
generating sinusoidal waveforms, four of them were studied as possible ways to implement
the phase-to-amplitude converter. Each method was studied and characterized in terms of
THD of the generated signal, complexity of implementation and silicon real state.
In the study of synchronizing method for reference signal generators, the basic theory
of PLL was covered. Even though the proposed SRSG is a digital system, the analog and
hybrid implementation of PLL were studied to have a clear vision of their behavior. Also, as
in the case of hybrid PLL, the phase detector structures can be used in the all-digital
implementations. For the ADPLL, several implementations reported for building digital loop
filters and oscillator stages were analyzed.
Then the selection and design of each of the component blocks of the SRSG was
performed. The phase-to-amplitude converter was selected using the theoretical THD level of
58
the sinusoidal waveform and the amount of silicon resources needed for its implementation in
a CPLD. The converter designed is based in a direct implementation of look-up tables and its
logic equations were presented.
For the selection of the phase detector, digital loop filter and DCO, an input to output
approach was used. First, the phase detector was selected using the symmetry of the generated
signal as a restriction, resulting in the selection of the XOR gate phase detector. Then, a
review of the available loop filters was performed, using their compatibility with the XOR
gate phase detector as the decision factor. Under this procedure, the K-counter filter was
selected. To complete the ADPLL, the DCO was selected using a similar approach: looking
for compatibility with the loop filter. The DCO selected was the ID counter.
With the basic design of the ADPLL completed, a modification was introduced to
reduce the jitter of the generated signal. This modification changed the clock frequency of the
loop filter to maintain the holding range of the ADPLL.
Once the ADPLL was completely designed, the phase shift corrector was presented. Its
task is to eliminate the phase shift between the input and output signals in locked state. This
shift depends on the type of phase detector used to build the PLL. The solution presented is
simple, easy to implement and should reduce the shift to nearly zero.
The phase-to-amplitude converter, the ADPLL and the phase shift corrector are the
component blocks needed to generate a sinusoidal waveform in-phase with the power grid.
However, the SRSG requires some decision-taking process when the power grid voltages fall
below a certain threshold. This process can be divided into two stages: the evaluation of the
input voltage amplitude using a window comparator to estimate its slope at the zero crossing
neighborhood, and decision-taking using this evaluation as input of a rule decoder. This block
replaces the faulty input signals with new ones for the ADPLLs in order to keep their proper
operation.
The last digital block presented was the clock signals generator. This block has the
task of deriving, from a single crystal oscillator, all the timing signals needed for the proper
operation of the SRSG. It generates the clock signals required for the operation of the analog
input interface, the clock signals for the loop filters and DCOs, and a 60 Hz signal to replace
the power grid signals.
Finally, the structure and operation of the two analog interfaces were presented. The
analog-to-digital interface is described as a key element for the correct behavior of the SRSG,
since it gives a digital expression of the amplitude of the power grid voltage. On the other
hand, the digital-to-analog interface is only necessary when the SRSG is used with an analog
control stage.
59
CHAPTER III.- SINGLE-STAGE PWM AC/AC
CONVERTERS
III.1.- INTRODUCTION
This chapter presents the basic operation principles of single stage PWM AC/AC
converters, derived from DC/DC converter topologies, in both single and three phase
configurations. Bi-directional switch arrays are reviewed first. Next, the operating
principles, in both discontinuous and continuous conduction mode, of some single phase
PWM AC/AC converters are studied. The topologies presented are selected because of their
capability of compensating both voltage sags and swells. Three phase converters are also
studied, and their advantages and disadvantages for voltage sag compensation are
discussed.
The selection and design of the PWM AC/AC converter is presented. Finally, for
the control stage, an analog control circuit based on commercial DC/DC PWM integrated
circuits is designed. Its synchronization process and pulse distribution for three phase
applications is presented.
III.2.- VOLTAGE AND CURRENT BI-DIRECTIONAL SWITCHES
Bi-directional switches are used to build commutation cells for different power
electronic systems. Among the power electronic systems that require this type of switch, we
found solid-state tap-changer transformers [61], matrix converters [62], [63] and PWM
AC/AC converters [64].
Bi-directional switches are built using uni-directional devices, and IGBTs are the
most popular [61], [64], [65], [66], [67], [70], [71]. GTOs [62], [69], reverse-blocking
IGBTs [63], [65], [70] and MOSFETs [68], [72] are also used.
There are four basic topologies for the bi-directional switch [63], [64], [65]: the
embedded switch, anti-series common emitter, anti-series common collector, and antiparallel, as they are shown in Figure III.1.
g1 e1
g1
e
g2
e1
g2
g1
e2
ac
ac
ac
ac
ac
ac
ac
ac
g
e2 g2
e
(a)
(b)
©
(d)
Fig. III.1.- Basic bi-directional switch topologies. (a) embedded switch, (b) anti-series common emitter, (c)
anti-series common collector, and (d) anti-parallel.
61
The embedded switch topology is implemented using fast recovery diodes in the
bridge. This topology has high conduction losses due to the series operation of two diodes
and the transistor. The anti-series and anti-parallel topologies improve their performance by
having only one diode and the transistor generating the losses when the array is turned on.
The anti-series common emitter topology has the advantage of providing only three control
connections (g1, g2 and e), instead of the four points required in the common collector and
the anti-parallel topologies. The fourth topology consists in the connection of two unidirectional transistors in anti-parallel configuration, the diode is required to eliminate the
effect of the body diode of the transistor. This array has been modified in [65] and [70],
where the blocking diode is eliminated and the IGBT is replaced by a reverse-blocking
IGBT. This new array is shown in Figure III.2.
g1 e1
ac
ac
e2 g2
Fig. III.2.- Basic bi-directional switch implemented with reverse-blocking IGBTs.
Another array can be derived from the uni-directional switch structure proposed by
Baliga in 1996, as referred by Mihaila [73]. The cascode connection of a high voltage SiC
JFET and a low voltage Si MOSFET. This array is shown in Figure III.3, both in unidirectional (a), and bi-directional (b) configurations.
g1 s1
g s
-
+
ac
ac
(a)
s2 g2
(b)
Fig. III.3.- Cascode array of SiC JFET and Si MOSFET. (a) uni-directional array, (b) bi-directional array.
The cascode array [68] presents several advantages over the “traditional” diodeIGBT array:
-
62
low on-state resistance,
high switching frequency,
high blocking voltage.
III.3.-
SINGLE-PHASE
PWM
AC/AC
CONTINUOUS CONDUCTION MODE
CONVERTERS
IN
PWM AC/AC single stage structures have been selected to carry on performance
analysis of the signal generator. The PWM AC/AC converters were selected due to the fact
that they are a single stage structures and have the ability of producing voltage levels higher
and/or lower than the input voltage signal without the use of low-frequency transformers
[74], [75]. The PWM AC/AC topologies suited for both sag and swell compensation were
buck-boost, Cúk, SEPIC and zeta.
The analysis and design methods developed for DC/DC converters have been
extended to AC/AC structures as reported in [74], [75], [76]. In [76], Venkataramanan
presents the equations for the design of three phase PWM AC/AC converters. These
equations take into consideration parameters such as percentage of current and voltage
ripple in passive components. With these parameters as guide, some considerations for the
development of the passive elements equations have been used.
Consideration 1
To calculate the value of the inductors, instead of using ∆I as an absolute value, a
proportional value of the input current is assumed. This consideration is based on the
desired inductor current waveform shown in Figure III.4.
I
A sin(ωt)
Ip sin(ωt)
B sin(ωt)
t
Fig. III.4.- Inductor current waveform.
The inductor current ripple is then defined as:
∆I (t ) = ( A − B ) ⋅ sin(ωt ) = K ⋅ I P ⋅ sin(ωt )
I
(III.1)
which yields:
KI =
and
A− B
IP
(III.2)
0 < KI < 1
63
Consideration 2
To calculate the value of the capacitor, instead of using ∆Vc as a absolute value, a
proportional value of the voltage is used. This consideration is based on the desired voltage
waveform shown in Figure III.5.
V
A sin(ωt)
VC sin(ωt)
B sin(ωt)
t
Fig. III.5.- Capacitor voltage ripple waveform.
The inductor current ripple is then defined as:
∆VC (t ) = ( A − B )⋅ sin(ωt ) = K ⋅VC ⋅ sin(ωt )
V
(III.3)
which yields:
KV =
and
A− B
VC
(III.4)
0 < KV < 1
This consideration is only applied to the input stage capacitor of the Cúk, SEPIC
and zeta converters.
Consideration 3
Since the output stage of the converters is a low pass, a cutoff frequency approach
can be used to calculate the value of the output capacitor.
The cutoff frequency is set at one tenth of the switching frequency. This allows the
output capacitor to have a small value, as compared with the ones used in DC/DC
applications.
C0 =
100
2
4π 2 L0 f sw
where
L0
fsw
64
is the output inductor,
is the switching frequency.
(III.5)
Table III.1 shows the equations obtained for the AC/AC buck-boost derived
topologies using these considerations, whilst Tables III.2 and III.3 show the equations
describing the electrical stresses of the converter elements.
Table III.1.- Equations for the passive elements of AC/AC buck-boost derived topologies.
Element/
Parameter
Buck-Boost
D Vs
V0
−
L1
V0 (1− D)
f sw K I I P
(1 − D)
L0
100
2
2
4π L1 f sw
C1
C0
Element
−
Cúk
SEPIC
Zeta
D Vs
D Vs
D Vs
(1 − D)
(1 − D)
(1 − D)
VS D
VS D
VS D
f sw K
I
I in P in
f sw K
f sw K
I
I in P in
I
I in P in
V (1 − D)
0
f sw K
I
I out P out
V (1 − D)
0
f sw K
I
I out P out
V (1 − D)
0
f sw K
I
I out P out
Po (1 − D )
2
f sw KV VS
Po (1 − D )
2
f sw KV VS
Po (1 − D )
2
f sw KV VS
100
2
2
4π L0 f sw
100
2
2
4π L0 f sw
100
2
2
4π L0 f sw
Table III.2.- Equations of the voltage stress for the elements of
AC/AC buck-boost derived topologies in P.U. referred to output voltage.
Peak Voltage
Buck-boost
Cúk
SEPIC
L1
⎛ 1 − Dmin ⎞
⎜
⎟
⎜ D
⎟
⎝ min ⎠
C1
⎛ KV ⎞
⎜⎜ 1 +
⎟
2 ⎟⎠
⎝
L2
CO
Sa
(main
sw.)
⎛ 1 ⎞
⎜
⎟
⎜D
⎟
⎝ min ⎠
S’a
(aux.
sw.)
⎛ 1 ⎞
⎜
⎟
⎜D
⎟
⎝ min ⎠
⎛ 1 − Dmin ⎞
⎜
⎟
⎜ D
⎟
⎝ min ⎠
⎛ KV ⎞ ⎛ 1 − 2 D
⎜
min ⎞⎟
1 ⎟⎜
⎜⎜ 1 + 2 ⎟⎟ ⎜ D
⎟
min ⎠
⎠⎝
⎝
(
)
⎛ 2(1 − Dmin ) + Dmin KV + 1 − 2 Dmin KV
⎜
1
2
⎜
2
D
⎜
min
⎝
⎛ KV ⎞
⎜
2⎟
⎜1 + 2 ⎟
⎜
⎟
⎝
⎠
⎛ KV ⎞ ⎛ 1 − 2 D
⎜
min ⎞⎟ 1 − D
1 ⎟⎜
1
+
⎜⎜
min
2 ⎟⎟ ⎜⎝ Dmin ⎟⎠
⎠
⎝
(
⎛ KV ⎞
⎜
1⎟
⎜⎜ 1 + 2 ⎟⎟ (1 − 2 Dmin )
⎠
⎝
)
⎞
⎟
⎟
⎟
⎠
zeta
⎛ 1 − Dmin ⎞
⎜
⎟
⎜ D
⎟
⎝ min ⎠
⎛ KV ⎞ ⎛ 1 − D
⎜
min ⎞⎟
1 ⎟⎜
⎜⎜ 1 + 2 ⎟⎟ ⎜ D
⎟
⎠ ⎝ min ⎠
⎝
⎛ 1 − Dmin ⎞
⎜
⎟
⎜ D
⎟
⎝ min ⎠
⎛ KV ⎞
⎜
1⎟
⎜1 + 2 ⎟
⎜
⎟
⎝
⎠
⎛ KV ⎞ ⎛ 1 − D
⎜
min ⎞⎟
1 ⎟⎜
⎜⎜ 1 + 2 ⎟⎟ ⎜ D
⎟
min ⎠
⎝
⎠
⎝
⎛ 1 − Dmin ⎞
⎜
⎟
⎜ D
⎟
⎝ min ⎠
⎛ KV ⎞
⎜
2⎟
⎜1 + 2 ⎟
⎜
⎟
⎝
⎠
⎛ KV ⎞
⎜
2⎟
⎜1 + 2 ⎟
⎜
⎟
⎝
⎠
⎛ 1 - Dmin ⎞
⎟
⎜ D
⎟
⎝ min ⎠
⎛ 1 - 2 Dmin ⎞
⎜
⎟
⎜ D
⎟
min ⎠
⎝
⎛ 1 ⎞
⎜
⎟
⎜D
⎟
⎝ min ⎠
⎛ 1 ⎞
⎜
⎟
⎜D
⎟
⎝ min ⎠
2⎜
65
Element
L1
C1
Table III.3.- Equations of the current stress for the elements of
AC/AC buck-boost derived topologies in P.U. referred to output current.
Peak Current
Buck-boost
Cúk
⎛ K I ⎞ ⎛ Dmax ⎞
⎟
⎜1 +
⎟⎜
2 ⎠ ⎜⎝ 1 - Dmax ⎟⎠
⎝
⎛ KI ⎞
⎜
1 ⎟ ⎛ Dmax ⎞⎟
⎟
⎜⎜ 1 + 2 ⎟⎟ ⎜⎜ 1 − D
⎝
max ⎠
⎠
⎝
⎛ Dmax K I
⎜1+
2
⎜
⎜ 1 - Dmax
⎜
⎝
⎛ KI ⎞
⎜
1 ⎟ ⎛⎜ Dmax ⎞⎟
1
+
⎜⎜
2 ⎟⎟ ⎜⎝ 1 − Dmax ⎟⎠
⎠
⎝
⎞
⎟
⎟
⎟
⎟
⎠
L2
CO
Sa
(main
sw.)
⎛ K I ⎞ ⎛ Dmax ⎞
⎟
⎟⎜
⎜1 +
2 ⎠ ⎜⎝ 1 - Dmax ⎟⎠
⎝
S’a
(aux.
sw.)
Element
⎛ K I ⎞ ⎛ Dmax ⎞
⎟
⎟⎜
⎜1 +
2 ⎠ ⎜⎝ 1 - Dmax ⎟⎠
⎝
L1
C1
L2
CO
Sa
(main
sw.)
S’a
(aux.
sw.)
66
⎛ KI ⎞
⎞
1
⎜
2 ⎟⎛
⎟⎟
⎜⎜ 1 + 2 ⎟⎟ ⎜⎜ 1 − 2 D
⎝
max ⎠
⎠
⎝
⎛ 4 Dmax + K I ⎞
⎜
2⎟
⎟
⎜⎜ 1 − 2 D
max ⎟
⎠
⎝
⎞
⎛ K I1 ⎞⎛ Dmax ⎞ ⎛ K I2 ⎞⎛
1
⎟ + ⎜1 +
⎟
⎜1 +
⎟⎜
⎟⎜
2 ⎟⎜ 1 − D
2 ⎟⎜ 1 − 2D
⎜
⎟ ⎜
⎟
⎝
⎠⎝
⎠⎝
max ⎠ ⎝
max ⎠
⎞
⎛ K I1 ⎞⎛ Dmax ⎞ ⎛ K I2 ⎞⎛
1
⎟ + ⎜1 +
⎟
⎜1 +
⎟⎜
⎟⎜
2 ⎟⎜ 1 − D
2 ⎟⎜ 1 − 2D
⎜
⎟ ⎜
⎟
⎝
⎠⎝
⎠⎝
max ⎠ ⎝
max ⎠
SEPIC
⎞
⎟ ⎛ Dmax ⎞
⎟⎟
⎟⎟ ⎜⎜ 1 - D
⎝
max ⎠
⎠
⎝
⎛ KI ⎞
⎜
1 ⎟ ⎛ Dmax ⎞⎟
⎟
⎜⎜ 1 + 2 ⎟⎟ ⎜⎜ 1 - D
⎝
max ⎠
⎠
⎝
⎛ KI ⎞
⎜
2⎟
⎜1 + 2 ⎟
⎟
⎜
⎠
⎝
⎛ K I Dmax + K I (1 − Dmax ) ⎞⎛ D
⎜1 + 1
⎟⎜ max ⎞⎟
2
⎜
⎟⎜⎝ 1 − Dmax ⎟⎠
2Dmax
⎝
⎠
K
⎞ ⎛ KI ⎞
⎛
I ⎞⎛ D
⎜ 1 + 1 ⎟⎜ max ⎟ + ⎜ 1 + 2 ⎟
2 ⎟
2 ⎟⎜ 1 − D
⎜
⎟ ⎜
⎠
⎠⎝
⎝
max ⎠ ⎝
⎛ K I1 ⎞⎛ Dmax ⎞ ⎛ K I2 ⎞
⎟ + ⎜1 +
⎟
⎟⎜
⎜1 +
2 ⎟
2 ⎟⎜ 1 − D
⎜
⎟ ⎜
⎠
⎠⎝
⎝
max ⎠ ⎝
zeta
⎞
⎟ ⎛ Dmax ⎞
⎟⎟
⎟⎟ ⎜⎜ 1 − D
⎝
max ⎠
⎠
⎝
⎛ KI ⎞
⎜
1 ⎟ ⎛ Dmax ⎞⎟
⎟
⎜⎜ 1 + 2 ⎟⎟ ⎜⎜ 1 − D
⎝
max ⎠
⎠
⎝
⎛ KI ⎞
⎜
2⎟
⎜1 + 2 ⎟
⎟
⎜
⎠
⎝
⎛ KI
⎜
1
⎜⎜ 1 + 2
⎛ KI
⎜
1
⎜⎜ 1 + 2
KI
2
2
⎛
⎜1 +
⎜
⎝
⎛
⎜1 +
⎜
⎝
K I ⎞⎛ D
⎞
max ⎟ + ⎛⎜ 1 +
1 ⎟⎜
2 ⎟⎜ 1 − D
⎟ ⎜
⎠⎝
max ⎠ ⎝
K I ⎞⎛ D
⎞
max ⎟ + ⎛⎜ 1 +
1 ⎟⎜
2 ⎟⎜ 1 − D
⎟ ⎜
⎠⎝
max ⎠ ⎝
KI
⎞
⎟
⎟
⎠
KI ⎞
2⎟
2 ⎟
⎠
2
2
where
VS
Vo
L1
L0
C1
C0
fsw
KI
IP
Po
KV
is the peak value of the input voltage,
is the peak value of the output voltage,
is the input filter inductor,
is the output filter inductor,
is the energy transfer capacitor (output capacitor in the buck-boost converter),
is the output filter capacitor,
is the switching frequency,
is the inductor current ripple factor,
is the inductor peak current,
is the output power,
is the capacitor voltage ripple factor.
In the next two sections, the operation of the buck-boost and Cúk converters is
explained. The operation with resistive, R-L and non-linear capacitive loads is covered.
III.3.1.- BUCK-BOOST CONVERTER
The AC/AC buck-boost converter of Figure III.6 has different operating modes
depending on the load it feeds. The load defines if there is a uni-directional or bi-directional
power flow between the input source and the load.
g4 e4
g1 e1
+vs
+vo
e2 g2
e3 g3
L1
C1
L
O
A
D
Fig. III.6.- AC/AC buck-boost converter.
Case 1.- Operation with resistive load
When the converter is feeding a linear resistive load, there is an uni-directional flow
of energy from the AC line to the load. In this case the converter operation is very much
related to the two operating modes of two DC/DC converter connected in anti-parallel.
With this load, the converter has four operating modes as shown in Figure III.7.
67
D1
M1
+vs
-vo
C1
L1
i
+vs
-vo
M3
L
O
A
D
L1
MODE 1
i
+vo
M2
D2
i
C1
L1
MODE 3
C1
L
O
A
D
MODE 2
D4
-vs
D3
M4
-vs
L
O
A
D
+vo
L1
i
C1
L
O
A
D
MODE 4
Fig. III.7.- Operating modes with linear resistive load.
Mode 1: When the input voltage is positive, switch M1 is turned on and the current flows
through L1, D1 and M1. Energy is stored in the inductor. The output capacitor supplies
energy to the load. Switches M2, M3 and M4 are kept off.
Mode 2: This mode is the complementary of Mode 1. Switch M1 is turned off and switch
M3 is turned on. The energy stored in the inductor is transferred to the output capacitor and
the load through D3 and M3, while switches M1, M2 and M4 are kept off.
Mode 3: When the input voltage is negative, switch M2 is turned on and the current flows
through L1, D2 and M2. Energy is stored in the inductor. The output capacitor supplies
energy to the load. Switches M1, M3 and M4 are kept off.
Mode 4: This mode is the complementary of Mode 3. Switch M2 is turned off and M4 is
turned on. The energy stored in the inductor is transferred to the output capacitor and the
load through D4 and M4. Switches M1, M2 and M3 are kept off.
Case 2.- Operation with R-L load
When the converter is feeding a R-L load, there is a bi-directional flow of energy
between the power supply and the load. In this case, during some portions of the mains
cycle, the converter returns the energy stored in the load to the line side. This is done by
operating simultaneously the switches at the output stage in the complementary PWM
cycle. With this load, the converter has eight operating modes as shown in Figure III.8.
68
D1
M1
+vs
-vo
L1
i
C1
+vs
M3
L
O
A
D
L1
MODE 1
D1
-vo
D4
+vo
M2
D2
L1
i
i
C1
+vo
M3
L
O
A
D
L1
D2
i
C1
L
O
A
D
+vo
L1
D4
-vo
M2
D2
i
i
L1
MODE 7
L
O
A
D
C1
MODE 6
M1
+vs
M4
-vs
MODE 5
D1
L
O
A
D
C1
MODE 4
+vo
L1
D3
i
D4
M2
M4
-vs
MODE 3
-vs
L
O
A
D
C1
MODE 2
M1
-vs
D3
C1
M4
+vs
L
O
A
D
-vo
M3
L1
D3
i
C1
L
O
A
D
MODE 8
Fig. III.8.- Operating modes with linear inductive-resistive load.
Mode 1: When the input voltage is positive and the input current is positive, switch M1 is
turned on and the current flows through L1, D1 and M1. Energy is stored in the inductor.
The output capacitor supplies energy to the load. Switches M2, M3 and M4 are kept off.
Mode 2: This mode of operation is the complementary of Mode 1. Switch M1 is turned off
and switch M3 is turned on. The energy stored in the inductor is transferred to the output
capacitor and the load through D3 and M3, while switches M1, M2 and M4 are kept off.
69
Mode 3: When the input voltage is negative and the input current is positive, switch M1
and M2 are turned on, so the current flows through L1, D1 and M1. D2 and M2 reduce the
reverse voltage applied to M1 and D1. Energy stored in the inductor is transfer to the AC
line. The output capacitor supplies energy to the load. Switches M3 and M4 are kept off.
Mode 4: This mode of operation is complementary to Mode 3, switches M1 and M2 are
turned off, switches M3 and M4 are turned on and energy from the load is stored in the
inductor.
Mode 5: When the input voltage is negative and the input current is negative, switch M2 is
turned on and the current flows through L1, D2 and M2. Energy is stored in the inductor.
The output capacitor supplies energy to the load. Switches M1, M3 and M4 are kept off.
and M4 is turned on. The energy stored in the inductor is transferred to the output capacitor
and the load through D4 and M4, while switches M1, M2 and M3 are kept off.
Mode 7: When the input voltage is positive and the input current is negative, switch M1
and M2 are turned on, so the can current flows through L1, D2 and M2. Energy stored in the
inductor is transfer to the AC line. The output capacitor supplies energy to the load.
Switches M3 and M4 are kept off.
Mode 8: This mode of operation is complementary to Mode 7 witches M1 and M2 are
turned off, switches M3 and M4 are turned on and energy from the load is stored in the
inductor.
Case 3.- Operation with non-linear capacitive load
When the converter is feeding a non-linear load comprised by a full-wave rectifier, a
capacitive filter and a resistance, in order to obtain a sinusoidal output voltage waveform
the output capacitor has to be discharged. With this type of load, the converter has eight
operating modes as shown in Figure III.9.
70
D1
M1
+vs
-vo
C1
L1
i
+vs
-vo
M3
L
O
A
D
L1
MODE 1
D4
i
M4
D1
-vo
i
C1
M1
+vs
-vo
M2
L
O
A
D
D2
MODE 4
D4
-vs
+vo
D2
i
C1
L1
+vo
L
O
A
D
L1
-vs
+vo
MODE 7
i
L
O
A
D
C1
MODE 6
D1
L1
M4
-vs
MODE 5
M3
L
O
A
D
C1
L1
i
MODE 3
M2
L
O
A
D
C1
MODE 2
+vs
L1
D3
D3
i
C1
M1
-vs
L
O
A
D
+vo
M2
D2
i
L1
C1
L
O
A
D
MODE 8
Fig. III.9.- Operating modes with non-linear capacitive load.
Mode 1: When the input voltage is positive and the voltage error signal (difference
between the reference and the feedback voltages) is positive, switch M1 is turned on and
the current flows through L1, D1 and M1. Energy is stored in the inductor. The output
capacitor supplies energy to the load. Switches M2, M3 and M4 are kept off.
71
and M3 is turned on. The energy stored in the inductor is transferred to the output capacitor
and the load through D3 and M3, while switches M1, M2 and M4 are kept off.
Mode 3: When the input voltage is positive and the voltage error signal is negative (output
voltage greater than the reference), the output capacitor has to be discharged. Switch M4 is
turned on to transfer energy from the capacitor to the inductor. Switches M1, M2 and M3
are kept off.
Mode 4: This mode of operation is complementary to Mode 3. The energy stored in the
inductor has to be transfer to the AC line. Switch M4 is turned off and switches M1 and M2
are turned on. Current flows from the inductor through M2 and D2 to the AC line.
Mode 5: When the input voltage is negative and the voltage error signal is positive, switch
M2 is turned on and the current flows through L1, D2 and M2. Energy is stored in the
inductor. The output capacitor supplies energy to the load. Switches M1, M3 and M4 are
kept off.
and switch M4 is turned on. The energy stored in the inductor is transferred to the output
capacitor and the load through D4 and M4. Switches M1, M2 and M3 are kept off.
Mode 7: When the input voltage is negative and the voltage error signal is negative, the
output capacitor has to be discharged. Switch M3 is turned on to transfer energy from the
capacitor to the inductor. Switches M1, M2 and M4 are kept off.
Mode 8: This mode of operation is complementary to Mode 7. The energy stored in the
inductor has to be transfer to the AC line. Switch M3 is turned off and switches M1 and M2
are turned on. Current flows from the inductor through M1 and D1 to the AC line.
III.3.1.1.- Simulation of an AC/AC buck-boost Converter
To assess the operational behavior described above, some simulations were
performed. The converter has the following operating parameters:
-
72
Input voltage (Vs):
Output power (Po):
Minimum input voltage (Vsmin):
Switching frequency (fsw):
Maximum duty cycle (D):
Inductor current ripple (KI)
Line frequency (f)
220Vrms
1 kVA
132 Vrms
75 kHz
0.63
0.20
60 Hz
The values of L1 and C1 can be obtained using the equations from Table III.1.
Assuming Pi = Po, the maximum rms value of the inductor current can be calculated from:
is =
Po
vs
(III.6)
is =
1000 VA
= 7.57 A , and therefore I P = 2 is = 2 ⋅ 7.57 A = 10.71 A
132V
(III.7)
and
V (1 − D)
220 V (1 − 0.63)
=
L1 = 0
= 506.7 µH
75000 Hz ⋅ 0.1⋅ 10.71 A
f sw K I
I P
C1 =
100
100
=
= 888 nF
2
2
2
4π L1 f sw 4π ⋅ 506.7 µH ⋅ (75000 Hz)2
(III.8)
(III.9)
In the case of a resistive load, the value of the load resistor is found from:
V 2 (220V )2
Rload = o =
= 48.4 Ω
Po 1000 VA
(III.10)
The simulation results using the values from equations (III.7) through (III.10) are
shown in Figure III.10. The figure represents the control signals in the gate of the switches,
the input voltage and inductor current, and the output voltage and current.
(a)
73
(b)
(c)
Fig. III.10.- Control signals and voltage and current waveforms of the converter operating with resistive load.
(a) Voltage and current waveforms during three line cycles, (b) Switching waveforms in modes 1 and 2, (c)
Switching waveforms in modes 3 and 4.
In the case of the R-L load, the values of the load resistor and inductor depend on
the power factor of the array. For this simulation a power factor of 0.7 is set, therefore:
PF = 0.7 = cos (ϕ )
(III.11)
ϕ = cos −1 (0.7 ) = 45.6 deg
(III.12)
V 2 (220V )2
Z load = o =
= 48.4 Ω
Po 1000 VA
(III.13)
Z load = X L2 + RL2
(III.14)
X L = Z load ⋅ sin(ϕ ) = 2π f Lo
(III.15)
⋅ sin(ϕ )
Z
Lo = load
2π f
(III.16)
Rload = Z load ⋅ cos (ϕ )
(III.17)
From equations (III.16) and (III.17) the values of Lo and Rload are 91.68 mH and
33.88 Ω. The simulation results using these element values are shown in Figure III.11. The
figure represents the control signals at the gate of the switches, the input voltage and
inductor current, and the output voltage and current.
74
(a)
(b)
(d)
(c)
(e)
Fig. III.11.- Control signals and voltage and current waveforms of the converter operating with R-L load.
(a) Voltage and current waveforms during three line cycles, (b) Switching waveforms in modes 1 and 2,
(c) Switching waveforms in modes 3 and 4, (d) Switching waveforms in modes 5 and 6, (e) Switching
waveforms in modes 7 and 8.
75
Case 3.- Operation with non-linear capacitive load
In the case of the non-linear capacitive load, the load circuit is a full-bridge rectifier
with a capacitive filter (Figure III.12), as the one described by the IEC62040-3 standard
[77] for testing UPS systems having a power factor of 0.7.
The values of the resistors and capacitor are defined as:
Rs =
0.04 V 2
S
(III.18)
R1 =
VC2
0.66 S
(III.19)
7.5
f R1
(III.20)
C=
Vc = 1.22 ⋅V
(III.21)
Rs
V
Vc
Fig. III.12.- Non-Linear Load.
(a)
76
C
R1
(b)
(c)
(d)
(e)
Fig. III.13.- Control signals and voltage and current waveforms of the converter operating with non-linear
capacitive load. (a) Voltage and current waveforms during three line cycles, (b) Switching waveforms in
modes 1 and 2, (c) Switching waveforms in modes 3 and 4, (d) Switching waveforms in modes 5 and 6,
(e) Switching waveforms in modes 7 and 8.
In these equations, V is the rms value of the input voltage, VC is the DC bus voltage
with a 5% ripple, and S is the apparent power of the circuit. From equations (III.18) through
(III.21), the values of Rs, R1 and C are 1.936 Ω, 109.15 Ω and 1145.2 µF respectively. The
simulation results using these element values and parameters are shown in Figure III.13.
The figure shows the control signals at the gate of the switches, the input voltage and
inductor current, and the output voltage and current.
III.3.2.- CUK CONVERTER
The AC/AC Cúk converter of Figure III.14 has different operating modes as well,
depending on the kind of load it feeds. The type of load defines if there is a uni-directional
or bi-directional power flow between the input source and the load. In order to simplify this
section, only the linear resistive load case is reviewed.
77
+vs
L1
M2
D2
C1
D1
M1
L0
M4
D4
+vo
D3
M3
C0
L
O
A
D
Fig. III.14.- AC/AC buck-boost converter.
Operation with resistive load
When the converter is feeding a resistive load, there is an uni-directional flow of
energy from the AC line to the load. In this case, the converter operation is very much
related to the two operating modes of two DC/DC converters connected in anti-parallel.
With this kind of load, the converter has four operation modes as shown in Figure III.15.
Mode 1: When the input voltage is positive, switch M1 is turned on and the input current
flows through L1, D1 and M1. Energy is stored in the inductor L1. The coupling capacitor
C1 transfers its stored energy to the output capacitor C0, inductor L0 (storing energy) and the
load. Switches M2, M3 and M4 are kept off.
and switch M3 is turned on. The energy stored in the inductor L1 is transferred to coupling
capacitor C1 through D3 and M3. Output inductor L0 transfers its energy to the output
capacitor C0 and the load. Switches M1, M2 and M4 are kept off.
Mode 3: When the input voltage is negative, switch M2 is turned on and the input current
flows through L1, D2 and M2. Energy is stored in the inductor L1. The coupling capacitor
C1 transfers its stored energy to the output capacitor C0, inductor L0 (storing energy) and
load. Switches M2, M3 and M4 are kept off.
and switch M4 is turned on. The energy stored in the inductor L1 is transferred to coupling
capacitor C1 through D4 and M4. Output inductor L0 transfers its energy to the output
capacitor C0 and the load. Switches M1, M2 and M3 are kept off.
78
L1
+vs
C1
L0
-Vo
+vs
L1
C1
L0
D1
i1
D3
C0
i2
M1
L
O
A
D
i1
MODE 1
L1
-vs
M3
L
O
A
D
C0
i2
MODE 2
C1
L0
+vo
-vs
L1
C1
M2
i1
-vo
L0
+vo
M4
i2
D2
C0
L
O
A
D
i1
MODE 3
D4
C0
i2
L
O
A
D
MODE 4
Fig. III.15.- Operating modes with resistive load.
III.3.2.1.- Simulation of an AC/AC Cúk converter
To assess the operational behavior described above, a simulation was performed.
The converter has the following operating parameters:
-
Input voltage (Vs):
Output power (Po):
Input inductor current ripple (KIi):
Output inductor current ripple (KIo):
Capacitor voltage ripple (KV):
Line frequency (f)
220Vrms
1 kVA
132 Vrms
75 kHz
0.63
0.15
0.25
0.6
60 Hz
The values of L1, L0, C1 and C0 can be obtained using the equations from Table
III.1. The maximum rms value of the input inductor current is also given by equation
(III.7).
L1 =
VS D
132V ⋅ 0.63
=
= 690 µH
75000
Hz ⋅ 0.15 ⋅ 10.71 A
f sw K I I P
(III.22)
C1 =
Po (1 − D )
1000 VA (1 − 0.63)
= 471 nF
=
f sw KV Vs2 75000 Hz ⋅ 0.60 ⋅ ( 132 V )2
(III.23)
For the output inductor, the value of the peak current IP is found from:
IP =
1000 VA
Po
2 = 6.428 A
2=
220 V
Vo
(III.24)
79
and
V (1− D )
220 V (1 − 0.63)
=
= 675 µH
L0 = 0
75000
Hz ⋅ 0.25 ⋅ 6.428 A
f sw K I I P
C0 =
(III.25)
100
100
=
= 667 nF
2 4π 2 ⋅ 675 µH ⋅ ( 75000 Hz )2
4π 2 L0 f sw
(III.26)
The value of the load resistor is already given by equation (III.10). The simulation
results using these element values and parameters are shown in Figure III.16. It represents
the control signals at the gate of the switches, the input voltage and inductor current, and
the output voltage and current.
(a)
(b)
(c)
(a) Voltage and current waveforms during three line cycles, (b) Switching waveforms in modes 1 and 2,
(c) Switching waveforms in modes 3 and 4.
80
III.4.SINGLE-PHASE
PWM
AC/AC
DISCONTINUOUS CONDUCTION MODE
CONVERTERS
IN
Throughout the state of the art review, no paper was found regarding the behavior of
AC/AC converters operating in discontinuous conduction mode. One good reason for this
could be that, if their behavior is similar to the DC/DC converters, the switches will be
subjected to high current and voltage stresses. However, it seems interesting to verify if the
power factor correcting capabilities of the topologies with boost characteristics still apply.
An AC/AC flyback converter (Figure III.17) operating in DCM was studied
working under different types of loads:
a) resistive load,
b) R-L load, and
c) non-linear capacitive load.
D1
M1
+vs
D3
M3
+vo
M2
D2
M4
L1
D4
L2
C0
L
O
A
D
Fig. III.17.- AC/AC flyback converter.
III.4.1.- FLYBACK CONVERTER
When the converter is feeding a resistive load, as stated in previous sections, there is
an uni-directional flow of energy from the AC line to the load. With this kind of load, the
converter has four operation modes as shown in Figure III.18.
Mode 1: When the input voltage is positive and the error signal (difference between the
reference and the feedback voltages) is positive, switch M1 is turned on and the current
flows through L1, D1 and M1. A gating signal is kept at switch M3, and the current flowing
through it is controlled by D3, which is reverse biased during this operation mode. The
energy is stored in the flyback transformer. The output capacitor supplies energy to the
load. Switches M2 and M4 are kept off.
Mode 2: This mode is the complementary of Mode 1. Switch M1 is turned off and D3 is
forward biased by the voltage at L2. The energy stored in the flyback transformer is
transferred to the output capacitor and the load through D3 and M3, while switches M2 and
M4 are kept off.
81
D1
M1
+vs
+vs
M3
D3
M3
+vo
i1
L1
C0
i0
L2
+vo
L
O
A
D
L
O
A
D
C0
L2
L1
MODE 1
i0
MODE 2
-vs
-vs
-vo
M2
i1
D2
M4
L1
L2
MODE 3
C0
i0
-vo
L
O
A
D
M4
L2
L1
D4
i0
C0
L
O
A
D
MODE 4
Fig. III.18.- Operating modes with linear resistive load.
Mode 3: When the input voltage is negative and the error signal is positive, switch M2 is
turned on and the current flows through L1, D2 and M2. A gating signal is kept at switch
M4, and the current flowing through it is controlled by D4, which is reverse biased during
this operation mode. The energy is stored in the flyback transformer. The output capacitor
supplies energy to the load. Switches M1 and M3 are kept off.
forward biased by the voltage present at L2. The energy stored in the flyback transformer is
transferred to the output capacitor and the load through D4 and M4. Switches M1 and M3
are kept off.
Case 2.- Operation with R-L Load
When the converter is feeding a R-L load, there is a bi-directional flow of energy
between the power supply and the load. During some portions of the mains cycle, the
converter returns the energy stored in the load to the line side. With this kind of load, the
converter has eight operation modes as shown in Figure III.19.
Mode 1: When the input voltage is positive and the output current is positive, switch M1 is
turned on and the current flows through L1, D1 and M1. A gate signal is kept at switch M3,
the current flowing through M3 is controlled by D3, which is reverse biased during this
operation mode. The energy is stored in the flyback transformer. The output capacitor
forward biased by the voltage across L2. The energy stored in the flyback transformer is
M4 are kept off. When the energy of the flyback transformer is completely transferred to
the output capacitor, the current through L2 reaches zero.
82
D1
M1
+vs
+vs
M3
D3
M3
+vo
i1
L1
C0
i0
L2
+vo
L
O
A
D
L1
MODE 1
-vs
L2
i0
C0
MODE 2
D3
-vs
M3
D1
M1
-vo
M4
L1
L
O
A
D
D4
i0
L2
C0
-vo
L
O
A
D
i1
L1
MODE 3
L
O
A
D
C0
i0
L2
MODE 4
-vs
-vs
-vo
M2
D2
M4
i1
L1
C0
i0
D4
L2
-vo
L
O
A
D
M4
L1
MODE 5
+vs
L2
M4
MODE 7
C0
+vs
M3
+vo
L2
i0
L
O
A
D
MODE 6
D3
L1
D4
D4
i0
C0
+vo
L
O
A
D
M2
i1
D2
L1
L2
C0
i0
L
O
A
D
MODE 8
Fig. III.19.- Operating modes with linear inductive-resistive load.
Mode 3: When the input voltage is negative and the output current is positive, the switches
M3 and M4 are turned on to transfer energy from the load to the flyback transformer. The
current flows through M3, D3, and L2. Switches M1 and M2 are kept off.
Mode 4: This mode is complementary to Mode 3. The energy stored in the flyback
transformer is returned to the AC source by turning on switch M2. Switch M1 is kept off.
Mode 5: When the input voltage is negative and the output current is negative, switch M2
is turned on and the current flows through L1, D2 and M2. A gating signal is kept at switch
M4, and the current flowing through it is controlled by D4, which is reverse biased during
this operation mode. The energy is stored in the flyback transformer. The output capacitor
83
forward biased by the voltage across L2. The energy stored in the flyback transformer is
are kept off. When the energy of the flyback transformer is completely transferred to the
output capacitor, the current through L2 reaches zero.
Mode 7: When the input voltage is positive and the output current is negative, the switches
M3 and M4 are turned on to transfer energy from the load to the flyback transformer. The
current flows through M4, D4, and L2. Switches M1 and M2 are kept off.
Mode 8: This mode is complementary to Mode 7. The energy stored in the flyback
transformer is returned to the line side power supply by turning on switch M1. Switch M2 is
kept off.
Case 3.- Operation with non-linear load
When the converter is feeding a non-linear load comprised of a full-wave rectifier, a
capacitive filter and a resistance, in order to obtain a sinusoidal output voltage waveform,
the output capacitor has to be discharged. With this kind of load, the converter has eight
operating modes as shown in Figure III.20.
Mode 1: When the input voltage is positive and the voltage error signal (difference
between the reference and the feedback voltages) is positive, switch M1 is turn on and the
current flows through L1, D1 and M1. Switch M3 is kept on, the current flowing through
M3 is controlled by D3, which is reverse biased during this operation mode. The energy is
stored in the flyback transformer. The output capacitor supplies energy to the load.
Switches M2 and M4 are kept off.
M4 are kept off. When the energy of the flyback transformer is completely transferred to
the output capacitor, the current through L2 reaches zero.
Mode 3: When the input voltage is positive and the voltage error signal is negative, the
switches M1, M2 and M4 operate at half the normal switching frequency. Switch M4 is
turned on to transfer its stored energy to the AC line through the flyback transformer. The
current flows through M4, D4, and L2. Switches M1, M2 and M3 are kept off.
Mode 4: This mode is complementary to Mode 3. Switch M4 is turned off and switches M1
and M2 are turned on to transfer the energy stored in the flyback transformer to the AC line.
Switch M3 is kept off.
84
D1
M1
+vs
+vs
M3
D3
M3
+vo
i1
L1
C0
i0
L2
+vo
L
O
A
D
L1
MODE 1
+vs
D1
M1
M2
D2
L2
i0
L
O
A
D
C0
MODE 2
+vs
+vo
M4
L1
D4
i0
L2
C0
+vo
L
O
A
D
i1
L1
MODE 3
L
O
A
D
C0
L2
MODE 4
-vs
-vs
-vo
M2
D2
M4
i1
L1
D4
L2
C0
i0
-vo
L
O
A
D
M4
L1
MODE 5
-vs
D3
D1
M1
M2
D2
L2
L2
-vs
M3
MODE 7
i0
i0
L
O
A
D
C0
MODE 6
-vo
L1
D4
C0
-vo
L
O
A
D
i1
L1
L2
C0
L
O
A
D
MODE 8
Fig. III.20.- Operating modes with non-linear capacitive load.
Mode 5: When the input voltage is negative and the voltage error signal is positive, the
switch M2 is turn on and the current flows through L1, D2 and M2. A gate signal is kept at
switch M4, and the current flowing through it is controlled by D4, which is reverse biased
during this operation mode. The energy is stored in the flyback transformer. The output
capacitor supplies energy to the load. Switches M1 and M3 are kept off.
are kept off. When the energy of the flyback transformer is completely transferred to output
capacitor, as in mode 2, the current through L2 reaches zero.
Mode 7: When the input voltage is positive and the voltage error signal is negative, the
switches M1, M2 and M3 operate at half the normal switching frequency. Switch M3 is
85
turned on to transfer its stored energy to the AC line through the flyback transformer. The
current flows through M3, D3, and L2. Switches M1, M2 and M4 are kept off.
Mode 8: This mode is complementary to Mode 7, switch M3 is turned off and switches M1
and M2 are turned on to transfer the energy stored in the flyback transformer to the AC line.
Switch M4 is kept off.
III.4.1.1.- Simulation of an AC/AC flyback converter
The design equations are derived from the ones used in DC/DC converters. The
output requirements for the AC/AC flyback are:
-
Input voltage (Vs):
Output power (Po):
Efficiency (η)
Line frequency (f)
(
127Vrms
200VA
70 Vrms
60 kHz
0.56
0.80
60 Hz
)
η Vsmin D 2 0.80 (70 Vrms ⋅ 0.56 )2
L1=
=
= 51.2 µH
2 f sw Po
Nt =
D Vsmin
Vo (η − D )
=
2 ⋅ 60 kHz ⋅ 200 VA
0.56 ⋅70 Vrms
= 1.286
127 Vrms ⋅ (0.81 − 0.56 )
L2 = Nt 2 ∗ L1 = 1.286 2 ⋅ 51.2 µH = 84.7 µH
CO =
100
100
=
= 8.3 µF
2 L
2 ⋅ (60 kHz )2 ⋅ 84.7 µH
4 π 2 f sw
4
π
2
(III.27)
(III.28)
(III.29)
(III.30)
In the case of the Resistive Load, the value of the load resistor is found from:
V 2 (127V )2
Rload = o =
= 80.6 Ω
Po 200 VA
86
(III.31)
The simulation results using these element values and parameters are shown in
Figure III.21. The figure shows the control signals at the gate of the switches, the input
voltage and inductor current, and the output voltage and current.
(a)
(b)
(c)
(a) Voltage and current waveforms during three line cycles, (b) Gating signals and transformer current of
mode 1 and 2, (c) Gating signals and transformer current of mode 3 and 4.
In the case of the R-L Load, the values of the load resistor and inductor depend on the
power factor of the array. For this simulation a power factor of 0.7 is selected, so that the
phase angle obtained in equation (III.12) is still valid.
V 2 (127V )2
Z load = o =
= 80.6 Ω
Po 200 VA
(III.32)
87
Using equations (III.16) and (III.17), the values of Lo and RL are 152.7 mH and
56.45 Ω. The simulation results using these element values and parameters are shown in
Figure III.22. It represents the control signals at the gate of the switches, the input voltage
and inductor current, and the output voltage and current.
(a)
(b)
(c)
(d)
(e)
Fig. III.22.- Control signals and voltage and current waveforms of the converter operating with R-L load.
(a) Voltage and current waveforms during three line cycles, (b) Gating signals and transformer current of
mode 1 and 2, (c) Gating signals and transformer current of mode 3 and 4, (d) Gating signals and transformer
current of mode 5 and 6, (e) Gating signals and transformer current of mode 7 and 8.
88
Case 3.- Operation with non-linear load
In the case of the non-linear load, the load circuit is again the one described by the
IEC62040-3 standard [77].
(a)
(b)
(c)
(d)
(e)
Fig. III.23.- Control signals and voltage and current waveforms of the converter operating with non-linear
capacitive load. (a) Voltage and current waveforms during three line cycles, (b) Gating signals and
transformer current of mode 1 and 2, (c) Gating signals and transformer current of mode 3 and 4, (d) Gating
signals and transformer current of mode 5 and 6, (e) Gating signals and transformer current of mode 7 and 8.
89
Using equations (III.18) through (III.21), the values of Rs, R1 and C are
3.2258 Ω, 181.86 Ω and 687.31 µF. The simulation results using these element values and
parameters are shown in Figure III.23. The figure shows the control signals at the gate of
the switches, the input voltage and inductor current, and the output voltage and current.
III.5.THREE-PHASE
PWM
AC/AC
CONTINUOUS CONDUCTION MODE
CONVERTERS
IN
Ventakataramanan [75] presents the transformation process from a single phase
PWM AC/AC buck converter into a three phase converter as shown in Figure III.24. The
original buck converter (Figure III.24a) is transformed by rearranging the position of
switches Sa and Sb in relation with Sa’ and Sb’, to take advantage of the structure of halfbridge semiconductor modules as shown in Figure III.24b. The circuit in Figure III.24c
splits both the input source and the output filter/load into two sections. By using symmetry,
the circuit on Figure III.24c is extended into the three phase topology of Figure III.24d.
L
L
Sb
+vs
+vO
Sa
Sa’
+vs
X
Sa’
X’
R
C
R
C
+vO
Sa
Sb’
Sb’
Sb
(a)
(b)
L
L
R
+vSA
R
Sa
+vOA
Sa’
C
Sa
C
Sa’
L
L
R
+vSB
R
Sb
+vOB
C
Sb’
Sb
Sb’
(c)
C
L
+vSC
R
Sc
+vOC
Sc’
C
(d)
Fig. III.24.- Transformation process of a single phase PWM AC/AC buck converter into a three phase PWM
AC/AC buck converter. (a) original topology, (b) switches rearrangement, (c) input source and output
filter/load split into two sections, (d) final three phase topology.
90
PWM AC/AC converters can be considered as the functional equivalent of
transformers [75], [78]. Some topologies behave just like step-down transformers (buck
converters [75], [76], [78-83], others like step-up transformers (boost converters [84], [87])
and some others as selectable step-up/step-down transformers (buck-boost [86] and Cúk
[87] converters). Figure III.24 shows the schematic diagrams of the four basic three-phase
PWM AC/AC converters.
The switches of the converters in Figure III.25 are operated in two groups. The first
group is formed by S1, S3 and S5, while the second group is formed by S2, S4 and S6. The
operation of the converters can be divided into two operational modes. In the first mode,
switches S1, S3 and S5 are turned on for a lapse DT, and during this lapse switches S2, S4
and S6 are turned off. In the second mode, switches S2, S4 and S6 are turned on for a lapse
(1-D)T, during this lapse switches S1, S3 and S5 are turned off. This operation leaves the
duty cycle (D) as the only variable available for control purposes.
For an AC line conditioner, one important performance characteristic of the AC/AC
converters is their response to unbalanced input voltage. Ideally, the converter should be
able to provide a balanced output voltage. In [80] and [85], a buck and a boost converters
were tested under unbalanced voltage sags. In both cases, the amplitude of output voltages
was compensated, but they could not achieve their nominal values. To overcome this
drawback, it has been suggested to implement an individual control for each phase [80], or
the use of single-phase converters for each phase [81-83].
L
C
S2
L
b
S3
C
S4
L
c
S5
C
S6
(a)
a
S2
L
C
S1
b
S4
L
C
S3
c
S6
L
C
S5
THREE-PHASE LOAD
S1
THREE-PHASE LOAD
a
(b)
91
S2
L
b
S3
C
S4
L
c
C
S6
S5
L
C
a
L1
THREE-PHASE LOAD
S1
THREE-PHASE LOAD
a
L0
C1
S1
S2
C0
b
L1
L0
C1
S3
S4
C0
c
L1
L0
C1
S5
(c)
S6
C0
(d)
Fig. III.25.- Three-phase PWM AC/AC converters. (a) buck. (b) boost. (c) buck-boost, (d) Cúk topologies.
III.6.- SELECTION OF THE CONVERTER FOR EXPERIMENTAL
TESTING
There are two approaches to implement the PWM AC/AC converter needed for the
testing of the sinusoidal reference signal generator: using a converter from Figure III.25, or
using three single-phase converters. Both approaches have pros and cons. The first one uses
a reduced number of switches, but it does not behave well with unbalance input voltages;
the second approach uses twice the number of switches, but is able to provide a balanced
output voltage under unbalanced input voltages. In this case, the correction of unbalanced
input conditions has been given a higher priority, resulting in the selection of three singlephase converters.
To select the single-phase topology, a comparison between the four basic structures
has to be performed. Table III.4 summarizes some of the main characteristics of the
converters required for AC line conditioning.
Table III.4.- Characteristics of PWM AC/AC converters for AC line conditioning.
PHASE
TRANSFER
STEP-UP
STEP-DOWN
INPUT CURRENT
CONVERTER
PRESERVATION
RATIO
VOLTAGE
VOLTAGE
Buck
Boost
Buck-Boost
Cúk
92
D
1
1− D
−D
1− D
−D
1− D
NO
YES
DISCONTINUOUS
YES
YES
NO
CONTINUOUS
YES
YES
YES
DISCONTINUOUS
NO
YES
YES
CONTINUOUS
NO
The buck and boost converters are not suitable for AC line conditioning since they
can only compensate swells and sags respectively, but not both; to eliminate this
shortcoming they require the use of transformers. The buck-boost converter can
compensate both swells and sags, but it has a discontinuous input current, which is
undesirable from the power quality point of view. A discontinuous current represents a high
harmonic distortion that has to be filtered. On the other hand, the Cúk converter has this
filter incorporated into its structure, providing continuous conduction of the input current.
Since the input filter is required for the Buck-Boost converter to reduce the current
harmonic content, and the Cúk converter has already included the input filter into its
structure, there is no difference in the number of elements required to implement an AC
line conditioner. Therefore, the structure chosen is the Cúk converter. The structure for the
three phase PWM AC/AC converter, including the control stage is shown in the block
diagram of Figure III.26.
n
c
c’
δc
n
b’
b
Vac
n
δb
a’
a
n
XFRM
RSG
XFRM
δa
Fig. III.26.- Block diagram of the three phase PWM AC/AC converter including its control stage.
III.7.- CONVERTER DESIGN
The converter has the following operating parameters:
Nominal input voltage (Vin):
Nominal output voltage (Vout):
Output power (Po):
Input inductor current ripple (Ki1):
127 Vrms
127 Vrms
200 VA
75 kHz
0.63
0.30
93
Output inductor current ripple (Ki2):
Input capacitor voltage ripple (Kv):
Line frequency (f):
0.60
0.20
60 Hz
From these specifications, the peak value of the minimum input and output voltages,
as well as, input and output currents must be obtained.
Vs =
1− D
1 − 0.63
2 Vin =
⋅ 2 ⋅ 127V
D
0.63
(III.33)
Vs = 105.48 V
I Pin =
2 ⋅ 200 VA
2 Po
=
⎛ 1 − 0.63 ⎞
⎛1− D ⎞
⎟ ⋅ 127 V
⎜
⎟Vin ⎜
⎝ 0.63 ⎠
⎝ D ⎠
(III.34)
I Pin = 3.792 A
Vo = 2 Vout = 2 ⋅ 127 V
(III.35)
Vo = 179.6 V
I Pout =
2 Po
2 ⋅ 200 VA
=
Vout
127 V
(III.36)
I Pout = 2.227 A
Using the equations in Table III.1, the values of the inductors and capacitors are:
L1 =
Vs D
105.48 V ⋅ 0.63
=
f sw K I1 I Pin 75000 Hz ⋅ 0.30 ⋅ 3.792 A
(III.37)
L1 = 778 µH
Lo =
Vo (1 − D )
179.6 V (1 − 0.63)
=
f sw K I 2 I Pout 75000 Hz ⋅ 0.60 ⋅ 2.227 A
(III.38)
Lo = 663 µH
P (1 − D )
200 VA (1 − 0.63)
C1 = o
=
2
f sw KV Vs 75000 Hz ⋅ 0.20 ⋅ (105.48 V )2
94
(III.39)
C1 = 443 nF
C0 =
100
4π
2
2
f sw
Lo
=
100
(III.40)
4 ⋅ π ⋅ (75000 Hz )2 ⋅ 663 µH
2
C0 = 679 nF
For the lab implementation, the values of the components were adjusted to:
L1 = 880 µH,
Lo = 608 µH,
C1 = 0.470 µF, and
C0 = 0.940 µF
III.8.- CONTROL STAGE DESIGN
The design of the control stage is divided in three steps: design of the compensator,
synchronization of the PWM generators for three-phase application, and design of the
distributor circuit for the PWM signals. In order to design a good compensator circuit, the
model of the converter must be obtained. This topic is covered in the next subsection.
III.8.1.- FREQUENCY RESPONSE OF THE CONVERTER
The frequency response can be obtained by substituting the transistors in the
schematic with its PWM-switch model in continuous conduction mode [88]. The
corresponding circuit is shown in Figure III.27.
î
2
î
a
î
1
Z1
^
Vg
î
D
c
a
Z2
î
p
d^ Ic
+
-
î
o
Z3
p
+
^V
D
ap
+
d^ vap
Z4
D D’ re
c
Fig. III.27.- Small signal equivalent circuit.
The resulting circuit can be analyzed using the electric circuit standard techniques.
The converter transfer function, from the control input to the power output, can be
expressed as
H ( s) = H 0
a 3 s 3 + a 2 s 2 + a1 s + a 0
b4 s 4 + b3 s 3 + b2 s 2 + b1 s + b0
(III.41)
95
The values of the elements used to build the converter and needed to obtain a
numerical representation of equation (III.41) are:
L1 = 880 µH,
Lo = 608 µH,
C1= 470 nF,
Co = 970 nF,
r1=17.2 Ω
r3=1 Ω
r2 = 80 mΩ
r4 = 80 mΩ
Using these values, the following results are obtained:
H0 = 421.7
z1,2 = 1 x 104 (0.211 ± 2.06j) rad/sec
z3 = - 1.0638 x 106 rad/sec
p1,2 = 1 x 104 (- 1.09 ± 1.12 j) rad/sec
p3,4 = 1 x 104 (- 0.534 ± 5.97 j) rad/sec
The Bode diagram is shown in Figure III.28. Since the Cúk converter transfer
function involves an unstable response, it is necessary to design a frequency-compensating
network such that a closed-loop stable response is obtained.
Fig. III.28.- Open loop frequency response of the converter.
96
III.8.2.- DESIGN OF THE COMPENSATOR
A suitable pole-zero pattern for the compensator is shown in Figure III.29 [89].
There is a first pole located at the origin, followed by two zeros, located at fZ1 and fZ2
respectively, and two more poles, at fP2 and fP3. The schematic of an active circuit that can
provide such a response is shown in Figure III.30.
A
-20 dB/dec
20 dB/dec
f
fz1
fz2
fp2
fp3
Fig. III.29.- Pole-zero distribution for the compensating network
C2
C3
Vo
R2
R3
R1
C1
Vcomp
Vref
+
Fig. III.30.- Frequency compensating circuit
The transfer function for the circuit can be obtained through routine analysis. The
result is:
H ( s) =
(sC 2 R 2 + 1)(sC 3( R1 + R 3) + 1)
⎛ C1 C 2 R 2 ⎞
+ 1⎟⎟
sR1(sC 3 R 3 + 1)(C 1 + C 2 ) ⎜⎜ s
⎝ C1 + C 2
⎠
(III.42)
The elements in the circuit are calculated as follows. As a first step, a crossover
frequency fXO is set as:
f xo ≤ 0.2 fs
(III.43)
97
Let fCP1,1 be the location of the first complex-pair pole in the transfer function. The
location of the first zero in the compensator design is set to:
f
f z1 = CP1,2
5
(III.44)
The location of the second zero should be within the range
f CP1,2 < f z 2 < 1.2 f CP1,2
(III.45)
f z 2 = 1.1 f CP1,2
(III.46)
and:
The third zero of the converter gives the location of the second pole
f P 2 = f CZ 3
(III.47)
In turn, the third pole should meet the following criteria:
f P 3 > 1.5 f xo
(III.48)
Next, the necessary gain required to bring the control-to-output transfer function to
0 dB at the crossover frequency fxo is:
⎞
⎛ f
⎛ Vo
⎞
G2 = 20 log ⎜⎜ xo ⎟⎟ − 20 log ⎜⎜ nom ⎟⎟
⎝ Vinmin ⎠
⎝ f CP3 ,4 ⎠
(III.49)
and
⎛ G2 ⎞
⎜
⎟
⎜ 20 ⎟
⎠
A2 = 10 ⎝
(III.50)
Additionally, the gain at the region of the two compensating zeros is obtained from:
⎛ f ⎞
G1 = G2 + 20 log ⎜⎜ xo ⎟⎟
⎝ f P2 ⎠
C1 =
1
2 π f xo A2 R1
R2 = A1 R1
98
(III.51)
(III.52)
(III.53)
C2 =
1
2 π f z1 R 2
R
R3 = 2
A2
C3 =
1
2 π f z 2 R3
(III.54)
(III.55)
(III.56)
For the response of the power stage, the zero-crossing point of the compensator is
set at 1500 Hz, the value of R1 is set at 10 kΩ, and the values of the components in the
compensator are the following: C1 = 220nF, C2 = 820nF, C3 = 6.8nF, R1 = 10kΩ, R2 = 57Ω,
R3 = 1.1kΩ. The open-loop frequency response, including the compensator, is shown in
Figure III.31.
Fig. III.31.- Open loop frequency response of the compensated converter.
III.8.3.- SYNCHRONOUS GENERATION OF PWM SIGNALS
To generate the PWM pulses required for the three-phase structure, the PWM IC
UC3526 was selected. This IC allows synchronic operation by connecting the SYNC and
CT signals of the master device with the slaves [90]. However, in practice this arrangement
99
does not allow synchronization. Two options were tested in the lab. The first one connects
the SYNC and CT signals of the master PWM to the SYNC and CT terminals of the slave
PWMs through a buffer, as shown in Figure III.32. The PWM signals generated using this
scheme are shown in Figure III.33.
SLAVE
VC
VCC
14
17
RST
SHDN
SYNC
5
8
12
3
4
10
11
9
VREF
COMP
CSS
CT
RT
RTMG
UC3526
18
7
6
U2
8
1
2
ISENSE+
ISENSE-
13
16
ERR+ OUTA
ERR- OUTB
VC
VCC
BUFFER
14
17
RST
SHDN
SYNC
5
8
12
VREF
COMP
CSS
CT
RT
RTMG
3
4
10
11
9
ISENSE+
ISENSE-
U1
UC3526
18
7
6
1
2
ERR+ OUTA
ERR- OUTB
13
16
MASTER
+
3
1
0
2
-
R1
1k
V-
RT
10K
1
TL082
RTslave
10k
8 4
2
OUT
U3B
5
+
0
V+
CT
10n
U3A
V+
3
-
V-
OUT
6
7
4
TL082
Fig. III.32.- Master-Slave connection of UC3526.
Fig. III.33.- PWM signals. CH1 Master, CH2 Slave1, CH3 Slave2.
When this configuration was tested, it was implemented in a protoboard. It worked
well, however, when implemented in a PCB, it presented several synchronization problems.
The second option connects the timing elements RT and CT in each of the PWM ICs.
In this configuration, each of the PWM ICs must be tuned to the desired switching
frequency. Synchronicity is achieved by connecting the SYNC signal of the master PWM
to the SYNC terminals of the slave PWMs, as shown in Figure III.34. The timing signals
generated using this scheme are shown in Figure III.35.
100
C16
102
3 R17
50K
2
C17
102
3 R18
50K
2
1
17
GND
VCC
CT
C18
102
15
RST
SHDN
SYNC
S1
5
8
12
CSS
VREF
CT
RT
RTMG
18
U8
UC3526
4
10
11
9
3
ISENSE+ VC
ISENSE7
6
COMP
14
13
16
ERR+ OUTA
ERR- OUTB
1
2
17
VCC
GND
15
S1
5
8
12
RST
SHDN
SYNC
18
VREF
CSS
CT
RT
RTMG
CT2
R16
1k
1
U7
UC3526
4
10
11
9
3
COMP
14
ISENSE+ VC
ISENSE7
6
13
16
ERR+ OUTA
ERR- OUTB
1
2
17
VCC
GND
15
RST
SHDN
SYNC
CT
S1
5
8
12
CSS
VREF
CT
RT
RTMG
18
U6
UC3526
4
10
11
9
3
COMP
14
ISENSE+ VC
ISENSE7
6
1
2
ERR+ OUTA
ERR- OUTB
13
16
This configuration presented no problems when implemented in PCB, and was the
one selected. One important characteristic of the PWM pulses generated is that they are
inverted, i.e. their width is equal to (1-d).
3 R19
50K
2
1
VCC
Fig. III.34.- Master-Slave connection of UC3526.
Fig. III.35.- PWM signals. CH1 Master, CH2 Slave1, CH3 Slave2.
III.8.4.- PWM SIGNALS DISTRIBUITON CIRCUIT
To avoid operation with an extremely large duty cycle, the control circuit includes a
maximum duty cycle limiter, implemented using a one-shoot circuit. Since the three PWM
generators are synchronized, only one limiter pulse is needed, as shown in Figure III.36.
The maximum duty cycle allowed is 70%.
A GAL26CV12 is used to send the PWM pulses to the power switches of the
AC/AC converters accordingly to the input voltage polarity. The block diagram of the
control circuit is shown in Figure III.37.
101
VCC
C7
16
0.1u
14
15
3
R3
504
VCC
C
R/C
CLR
Q
Q
13
4
U5A
74LS123
8
2
3
VCC
C8
221
A
B
GND
1
2
1
VCC
Fig. III.36.- One-shoot circuit to limit the maximum duty cycle.
POLARITY A
POLARITY B
POLARITY C
C1
C2
C3
C4
B1
B2
B3
B4
A1
A2
A3
A4
POWER STAGE
PWM C
UC3526
MASTER
UC3526
SLAVE 1
UC3526
SLAVE 2
REF B
OUT B
REF A
SYNC
OUT A
SYNC
REF C
OUT C
74LS123
ONE SHOOT
PWM B
∆MAX
PWM A
GAL26CV12
FEEDBACK ADQUISITION
STAGE
Fig. III.37.- Block diagram of the control circuit.
The logic equations defined for the distribution of the PWM pulses are functions of
the maximum duty cycle (dmax), the polarity of the reference signal (pol_x) and the PWM
pulse (pwm_x), where ‘x’ is the name of the phase (A, B and C).
102
x1 = not ( pol _ x AND (d max AND not ( pwm _ x )))
(III.57)
x 2 = not (not ( pol _ x ) AND (d max AND not ( pwm _ x )))
(III.58)
x 3 = not ( pol _ x AND not (d max AND not ( pwm _ x )))
(III.59)
x 4 = not (not ( pol _ x ) AND not (d max AND not ( pwm _ x )))
(III.60)
The equations are defined as active low functions, due to the fact that the interface
between the control circuit and the MOSFETs driver circuit is a inverting-TTL gate
optocoupler (HCPL2611).
III.9.- SUMMARY
In this chapter, several topics related to single stage PWM AC to AC conversion
were covered. The first topic, the implementation of bi-directional switches using unidirectional devices, was covered from classical approaches using IGBT switches through
the use of cascode arrays using silicon carbide JFETs and silicon MOSFETs. Then, the
basic operational principles of PWM AC/AC converters were presented. Single-phase
topologies were covered in both continuous and discontinuous conduction modes. Besides
the classical approach of studying their operation with linear resistive load, the converters
were studied operating with linear inductive-resistive and non-linear capacitive loads. The
additional operational modes and gate signals were also derived for these loads.
Simulations were presented to validate these operational modes.
Three-phase PWM AC/AC converters were also reviewed, but in a lighter way. The
response of three-wire PWM AC/AC converters working under un-balanced input
conditions was reviewed. Even when these converters are able to compensate voltage sags
and/or swells, they are not able to provide a balanced output voltage. The approach selected
to compensate three-phase unbalanced voltage was the use of three single-phase AC/AC
converters connected in a three-phase four wires configuration.
Finally, the design of the AC/AC Cúk converter and its control stage was presented.
The design of the compensating circuit was based on the methods available for DC/DC
converters and gave good results. The control stage presented was based in commercial
PWM ICs for DC converter applications. These ICs required a synchronization scheme, and
two variations of the manufacturer’s synchronization method were also presented and
tested. A programmable device responsible of distributing the PWM signals to the proper
converter switch completed the control stage.
103
CHAPTER IV.- EXPERIMENTAL PROTOCOLS AND DATA
ANALYSIS PROCEDURE
IV.1.- INTRODUCTION
This chapter presents the set of tests performed to validate the design and
implementation of the sinusoidal reference signal generator (SRSG) as well as the data
analysis procedure used. The test procedure is based on two protocols. The first one is
aimed at obtaining the performance parameters of the SRSG needed for its characterization.
The second one requires the use of a PWM AC/AC Cúk converter as a validation circuit
working in closed loop, to verify the performance of the SRSG under noisy conditions.
IV.2.- TESTING PROTOCOLS
The testing of the SRSG and the validation circuit was carried out following a
modular approach. The goal was to characterize the relevant performance parameters and to
perform a statistical analysis with the measured data.
Objective
To obtain the performance characteristics of the SRSG and the validation circuit.
The parameters of the SRSG involved were the frequency tracking, frequency hold range,
frequency pull-in range, line detection threshold, reference signal substitution (decision
taking process) and output signal characteristics. For the validation circuit, the parameters
involved were the output characteristics of the power stage such as amplitude level,
distortion and response time to input disturbances.
Methodology
To verify the performance of the SRSG and the validation circuit, a set of eight tests
was specifically designed for each parameter. The measurements were recorded in tables
and in data files, in a format suitable for mathematical analysis in packages such as
MATLAB. The analysis is based on statistical methods for large number of samples (≥30),
and the results were summarized in a special format.
General Procedure
The tests performed required the use of a previously calibrated oscilloscope, a
precision waveform generator and a three-phase AC voltage source. For the SRSG, each
test required specific settings for the input signals, both in amplitude and frequency. The
variation of the input signal parameters was performed manually until the desired operating
condition was achieved. For the validation circuit, in the static input condition tests, the
input value was set at various levels, and the measurements were taken after the circuit had
reached steady state. In the dynamic input condition tests, the input signal was reduced
using a step function and the measurements were taken at the instant of the step.
105
Data were processed in two steps: first, the average value and standard deviation of
the set of measurements were obtained; then, using these values and some statistical tools,
the confidence level and confidence interval of the performance parameters were
calculated.
IV.2.1.- SINUSOIDAL REFERENCE SIGNAL GENERATOR
The SRSG was submitted to eight specific tests. The objective, as mentioned before,
was to measure its performance characteristics. For the first seven tests, the laboratory
setup was as shown in Figure IV.1. To test the rule decoder, the function generator was
replaced by a three-phase AC voltage source, as shown in Figure IV.2.
Fig. IV.1.- Laboratory setup for the first seven tests.
Fig. IV.2.- Laboratory setup for the Rule Decoder test.
The tests performed are summarized in Table IV.1. The procedure followed was
simple: for tests 1, 2 and 7, the signal source was set near the input limit for the parameter
being measured, then the input signal was varied very slowly until the desired output
condition was met. For tests 3, 4, 5, and 6, the input signal was set at several specific
frequencies and the output characteristics under study were measured and recorded. The
eighth test was carried out generating all possible conditions defined for the rule decoder
(Table IV.2). The signal source was connected to the SRSG using a transformer array as an
interface.
106
Table IV.1.- Specific Tests Guide for SRSG.
Test
number
1
2
Main
Block
ADPLL
ADPLL
3
ADPLL
NA
4
SSG
Phase shifting
compensator
Phase error
5
SSG
NA
Output THD
6
SSG
NA
Output amplitude
Fault
decoder
Fault
decoder
Fault
decoder
Line Fault
Detector
Line Fault
Detector
7a
7b
8
Sub-block
Parameter
Remarks
NA
NA
Hold range
Pull-in range
Jitter in locked state
Obtain upper and lower limits
Obtain upper and lower limits
To measure the ADPLL’s jitter
(∆F), the oscilloscope will be
triggered on the positive edge of the
feedback signal at 50 percent of the
signal amplitude, displaying an
“eye pattern” similar to the one
shown in Figure IV.3. The Tmin and
Tmax points of the pattern will
provide the value of ∆F, according
to:
Rule Decoder
To be tested at different frequencies
within the hold range
Set threshold
Reset threshold
Rule Table
To be tested at all possible input
conditions defined in table X
FB_A
Tmin
t
Tmax
Fig. IV.3.- “Eye pattern” proposed for jitter measurement.
107
Rule
1
2
3
4
5
6
7
8
Table IV.2.- Rule decoder input/output relationship.
Action
F1
All three line voltages Use MSB of line voltage
ADC_A_7
are within range.
digitalization as input for ADPLL.
Use MSB of ADPLL phase C
Only line voltage phase
feedback bus shifted 120° as input DC120
A is out of range.
for ADPLL phase C.
Use MSB of ADPLL phase A
feedback bus shifted 120° as input ADC_A_7
B is out of range.
for ADPLL phase C.
Use MSB of ADPLL phase B
feedback bus shifted 120° as input ADC_A_7
C is out of range.
for ADPLL phase C.
feedback bus shifted 120° as input
Only line voltage phase for ADPLL phase A.
DC120
C is within range.
for ADPLL phase B.
Only line voltage phase for ADPLL phase A.
DB240
B is within range.
for ADPLL phase C.
Only line voltage phase for ADPLL phase B.
ADC_A_7
A is within range.
for ADPLL phase C.
Use CK60 signal as input for
ADPLL phase A.
All three line voltages feedback bus shifted 120° as input
CK60
are out of range.
for ADPLL phase B.
for ADPLL phase C.
Condition
Output
F2
F3
ADC_B_7 ADC_C_7
ADC_B_7 ADC_C_7
DA120
ADC_C_7
ADC_B_7
DB120
DC240
ADC_C_7
ADC_B_7
DB120
DA120
DA240
DA120
DA240
IV.2.2.- POWER ELECTRONICS VALIDATION CIRCUIT
It is important to test the reference signal generator operating under "normal noisy"
conditions; that is, operating with a power electronic system. The PWM AC/AC Cúk
converter used for this purpose was implemented with a closed loop control. The tests were
divided in two groups: static and dynamic tests. From the static tests, the effect of the
switching noise on the SRSG can be observed. The dynamic tests were designed to observe
the SRSG’s rule decoder performance. Table IV.3 shows the tests performed to the PMW
AC/AC Cúk converter.
108
Table IV.3.- Specific tests guide for the validation circuit.
Test
Test Group
Parameter
Remarks
number
Obtain
regulation
curve
and
Voltage regulation
1
regulation limits
STATIC
Obtain THD curve at central
THD level
2
frequency
Single phase fault, step applied at 90
3
degrees in phase A.
Two phase fault, step applied at 90
4
degrees in phase B and 150 degrees in
phase C.
Two phase fault, step applied at 90
5
degrees in phase C and 30 degrees in
phase B.
DYNAMIC Response time
Three phase fault, step applied at 90
6
degrees in phase A, 210 degrees in
phase C and 330 degrees in phase B.
7
degrees in phase B, 210 degrees in
phase A and 330 degrees in phase C.
8
degrees in phase C, 210 degrees in
phase B and 330 degrees in phase A.
IV.3.- DATA ANALYSIS PROCEDURE
This section presents the analysis of the data gathered in the experimental and
simulation tests. The measured data are compared against the design value using the
measurements mean value and the tolerance limits imposed. Curve fitting methods and
quality control charts are also used to describe the behavior of several parameters. A brief
introduction to the statistical methods applied is presented. Finally, the analysis of the
performance of the SRSG operating under unbalanced input conditions is presented, as well
as, some possible improvements.
IV.3.1.- STATISTICAL ANALYSIS PROCEDURE
Within the methods available for the statistical analysis, statistical inference
(particularly interval estimation) [91], and quality control charts have been selected for the
analysis of the experimental data. Interval estimation is used to define an interval that
contains the parameter of interest, within some level of confidence. There are two methods
to estimate the confidence interval for the mean of a set of samples: with known population
variance and with unknown population variance. Since the variance of the parameters
measured is unknown, the method selected to define the confidence interval (mean with
unknown variance) uses the samples mean and student’s t-distribution. The upper and
lower limits of the confidence interval are defined as:
µˆ 1 = x − tα / 2 ,df
s
Ns
(IV.1)
109
µˆ 2 = x + tα / 2 ,df
where µ̂1
µ̂ 2
x
s
tα
,df
2
Ns
s
Ns
(IV.2)
is the lower limit of the interval,
is the upper limit of the interval,
is the mean value of the samples,
is the standard deviation of the samples,
is the critical value of t for a level of significance α/2 and N-1 degrees of
freedom (df), and
is the number of samples.
Quality control charts, and specifically an x chart, is a graphical tool that has a
central value, about which the experimental data fluctuate, and two limits: the upper control
limit (UCL) and the lower control limit (LCL). The two limits define the region where the
measured data falls when the process is in control. The control limits are defined as:
UCL = µ0 +
3σ
N
(IV.3)
LCL = µ0 −
3σ
N
(IV.4)
and
where µ0
σ
is the process mean value, and
is the population standard deviation.
The procedure applied is the following:
1.- Each measured parameter has a nominal design value xnom.
2.- A tolerance TOL is defined for the parameter.
3.- The mean and standard deviation of the set of measurements is
calculated.
4.- The upper limit of the design value is calculated using:
xupper = xnom (1 + TOL )
(IV.5)
5.- The lower limit of the design value is calculated using:
xlower = xnom (1 − TOL )
6.- The upper limit of the confidence interval µ̂ 2 is calculated.
7.- The lower limit of the confidence interval µ̂1 is calculated.
110
(V.6)
8.- Verification that the confidence interval is within the parameter
tolerances.
xlower < µˆ 1 < µˆ 2 < xupper
(IV.7)
IV.4.- SUMMARY
This chapter presented the testing protocols for both the sinusoidal reference signal
generator and the PWM AC/AC Cúk converter, as well as the statistical analysis procedure
applied to the experimental data gathered. The general objectives, methodology and
procedures of the testing protocols were described. The testing of the SRSG was divided in
eight tests. Some test measured the performance parameters of the ADPLL+phase-shiftcorrector sub-blocks, such as, holding range, pull-in range, frequency jitter and input-output
phase shift. A second set of tests measured the static characteristics of sinusoidal signals
(THD levels and amplitude). The performance of the rule decoder was also tested.
The tests for the PWM AC/AC Cúk converter were divided in two groups: static
and dynamic tests. Static tests were aimed at measuring the THD and output voltage
regulation of the converter. These tests showed the performance of the SRSG under noisy
steady state conditions. The dynamic tests, on the other hand, were aimed at measuring the
time response of the converter under deep sags, they also provide an insight of the ability
of the rule decoder to maintain a steady set of reference signals.
Finally, a summary of the statistical tools used to analyze the data gathered from the
experimental process was presented.
111
CHAPTER V.- SINUSOIDAL REFERENCE SIGNAL
GENERATOR TESTING AND
PERFORMANCE ANALYSIS
V.1.- INTRODUCTION
This chapter presents the experimental data gathered using the testing protocol
designed for the SRSG, along with their analysis. Also, a comparison between the proposed
SRSG and a reference generator reported in the literature is presented. For the analysis of
the performance parameters of the generator, the maximum tolerance allowed for the hold
range, pull-in range, frequency jitter, output voltage amplitude and input threshold level is
set at ±0.5%. The level of confidence is set at 90% (equivalent to 0.90, and α = 0.1). The
mean value µ0 is defined as the expected design (or adjusted) value. The experimental data
is assumed to have a normal distribution function and the number of samples (N) per
parameter is at least 30.
V.2.- EXPERIMENTAL TESTING
V.2.1.- TEST 1: HOLD RANGE AND CENTRAL FREQUENCY
From Test 1, the values of central frequency and hold range of the ADPLL could be
derived. The mean value, and its deviation from the expected value were calculated using:
n
∑ fi
fu = i =1
Ns
(V.1)
n
∑ ( fi − fc )2
s = i =1
where:
(V.2)
Ns − 1
fµ
Ns
fi
s
fc
is the samples mean frequency,
is the number of frequency samples (30),
is the ith frequency sample value,
is the sample standard deviation from fc,
is the expected central frequency (60 Hz).
Test 1 was designed to record the upper and lower frequency limits were the
ADPLL lost the locked state. The frequency values used to calculate the central frequency
and its deviation from the expected designed value were derived from:
fi =
U i + Li
2
(V.3)
where:
113
Ui
Li
is the ith recorded value of the upper limit frequency,
is the ith recorded value of the lower limit frequency.
Using the data generated in (V.3), the central frequency of the ADPLL (fµ) is
59.771983 Hz. This value has a standard deviation of 0.231915 Hz from the expected value
of 60 Hz.
The difference between the central frequency obtained and its expected value
represents an error of -0.38%. This error is caused by the frequency of the crystal oscillator
used to generate the fm and fn clock signals of the ADPLL.
The hold range was determined using equations (V.1) and (V.2). The upper and
lower limits were determined using a central frequency of 60 Hz. Table V.1 shows the
measured values of the upper and lower holding frequencies, their standard deviation from
the expected value and relative error.
Upper Frequency
Lower Frequency
Table V.1.- Measured hold range
EXPECTED
MEASURED MEAN
STANDARD
VALUE (Hz)
VALUE (Hz)
DEVIATION (Hz)
63.692308
63.536267
0.158710
56.307692
56.007700
0.305121
ERROR
(%)
0.244992
0.532773
For a confidence level of 0.90, the value of significance level (α) is 0.10, and using
the student’s t distribution tables the value of tα / 2 ,df , with df equal to 29 is 1.69127. The
upper limit of the range is verified first.
• Upper frequency limit
From equations (IV.1) and (IV.2) the limits of the confidence interval are:
µˆ 1 = 63.487032 Hz
µˆ 2 = 63.585501 Hz
The limits imposed by the tolerance of ±0.5% (using equations (IV.5) and (IV.6)) to
the upper hold frequency (fnom=63.692308 Hz) are:
f1 = 63.373846 Hz
f 2 = 64.010769 Hz
Substituting these values in (IV.7):
( f1 = 63.373846 Hz )< (µˆ 1 = 63.487032 Hz )< (µˆ 2 = 63.585501 Hz )< ( f 2 = 64.010769 Hz )
The measured upper limit of the holding range is within the design restrictions with
a 90% confidence level.
114
• Lower frequency limit
The lower limit of the range is verified, again using equations (IV.1) and (IV.2):
µˆ 1 = 55.913046 Hz
µˆ 2 = 56.102353 Hz
For fnom = 56.307692 Hz, the limits f1 and f2 are:
f1 = 56.026153 Hz
f 2 = 56.589230 Hz
( f1 = 56.026153 Hz ) > (µˆ 1 = 55.913046 Hz )< (µˆ 2 = 56.102353 Hz )< ( f 2 = 56.589230 Hz )
Since f1 is greater than µ̂1 , the confidence interval for the measured lower limit of
the holding range is not within the design restriction for the parameter. This noncompliance is due to the frequency variation of the crystal oscillator. If this analysis is
performed again with a new value of fc (59.771983 Hz), and a new pair of limits for the
hold range found using:
∆f = ±
M ⋅ fc
( 2 ⋅ K + 1) ⋅ 2 ⋅ N
(V.4)
∆f = ± 3.678 Hz.
With this new hold range, the values of the lower and upper limit were calculated.
Table V.2 shows the standard deviation and percent error.
Upper frequency
Lower frequency
Table V.2.- Adjusted measured hold range limits
EXPECTED
MEASURED MEAN
STANDARD
VALUE (Hz)
VALUE (Hz)
DEVIATION (Hz)
63.450259
63.536267
0.087479
56.093707
56.007700
0.087479
ERROR
(%)
-0.135551
0.153327
Now, the new upper limit of the range is verified, the limits of the confidence
interval are:
µˆ 1 = 63.509129 Hz
µˆ 2 = 63.563406 Hz
f1 = 63.133007 Hz
115
f 2 = 63.767510 Hz
Substituting these values in (V.7):
( f1 = 63.133007 Hz )< (µˆ 1 = 63.509129 Hz )< (µˆ 2 = 63.563406 Hz )< ( f 2 = 63.767510 Hz )
Once again, the measured upper limit of the holding range is within the design
restrictions with a 90% confidence level.
Now, the lower limit of the range is tested again:
µˆ 1 = 55.980562 Hz
µˆ 2 = 56.034837 Hz
f1 = 55.813238 Hz
f 2 = 56.374175 Hz
Substituting these values in (V.7):
( f1 = 55.813238 Hz )< (µˆ 1 = 55.980562 Hz )< (µˆ 2 = 56.034837 Hz )< ( f 2 = 56.374175 Hz )
In this occasion, the confidence interval is inside the new design restrictions.
Figures V.1a and b shows the confidence interval (shaded area) inside the area defined by
the expected parameter and its tolerance.
(a)
(b)
Fig. V.1.- Location of confidence interval measured for the hold range limits.
(a) Lower hold limit, (b) Upper hold limit.
116
V.2.2.- TEST 2: PULL-IN RANGE
From Test 2, the value of pull-in range of the ADPLL can be derived. The mean
value, and its deviation from the expected value were calculated using (V.1) and (V.2).
Test 2 was designed to record the upper and lower frequency limits were the
ADPLL went into locked state. The expected limits for this range, since this is a digital
implementation, are the same as the hold range. Table V.3 shows the measured values of
the upper and lower holding frequencies, their standard deviation from the expected value
and relative error.
Upper Frequency
Lower Frequency
Table V.3.- Measured pull-in Range
EXPECTED
MEASURED MEAN
STANDARD
VALUE (Hz)
VALUE (Hz)
DEVIATION (Hz)
63.692308
63.5360
0.15905379
56.307692
56.0076
0.30518864
ERROR
(%)
0.245523
0.532891
These values are also affected by the change of the central frequency of the ADPLL,
therefore, their analysis is performed using the value of 59.771983 Hz for fc, and the new
limits for the pull-in range is found using equation (V.4):
∆f = ± 3.678 Hz.
With this new pull-in range, the values of the lower and upper limit were calculated.
Table V.4 shows the standard deviation.
Upper frequency
Lower frequency
Table V.4.- Adjusted measured pull-in range limits
EXPECTED
MEASURED MEAN
STANDARD
VALUE (Hz)
VALUE (Hz)
DEVIATION (Hz)
63.450259
63.5360
0.087205
56.093707
56.0076
0.087546
ERROR
(%)
-0.135131
+0.153446
• Upper frequency limit
The new upper limit of the range is verified, using equations (IV.1) and (IV.2), the
limits of the confidence interval are:
µˆ 1 = 63.508947 Hz
µˆ 2 = 63.563052 Hz
f1 = 63.133007 Hz
f 2 = 63.767510 Hz
117
( f1 = 63.133007 Hz )< (µˆ 1 = 63.508947 Hz )< (µˆ 2 = 63.563052 Hz )< ( f 2 = 63.767510 Hz )
The measured upper limit of the holding range is within the design restrictions with
a 90% confidence level.
• Lower frequency limit
Now, the lower limit of the range is verified:
µˆ 1 = 55.980441 Hz
µˆ 2 = 56.034758 Hz
f1 = 55.813238 Hz
f 2 = 56.374175 Hz
( f1 = 55.813238 Hz )< (µˆ 1 = 55.980441 Hz )< (µˆ 2 = 56.034758 Hz )< ( f 2 = 56.374175 Hz )
The confidence interval is inside the new design restrictions. Figures V.2a and b
shows the confidence interval (shaded area) inside the area defined by the expected
parameter and its tolerance.
(a)
(b)
Fig. V.2.- Location of confidence interval measured for the pull-in range limits.
(a) Lower pull-in limit, (b) Upper pull-in limit.
118
V.2.3.- TEST 3: FREQUENCY JITTER
The frequency jitter test was made using two approaches, the first one was made
using the scheme shown in Figure IV.3, applying a frequency sweep from 56.3 Hz through
63.0 Hz. Figure V.3 shows one oscillogram of the performed measurement.
Fig. V.3.- Oscillogram of jitter measurement.
The measured period variation of the output signal (∆T) has a mean value of
16.2766 µs (61,436.92 Hz) with a standard deviation of 0.262 µs. The expected value is
16.2760 µs (61,440 Hz) ±0.08138 µs. Using equations (IV.1), (IV.2), (IV.5) and (IV.6), the
confidence interval and the parameter limits are:
µˆ1 = 16.195323 µs
µˆ 2 = 16.357876 µs
T1 = 16.194620 µs
T2 = 16.357380 µs
These values do not comply with the relationship in equation (V.7) since T2 < µ̂ 2 ,
however, µ̂ 2 is +0.503% away form the central value of 16.276 µs. Figure V.4 shows the
confidence interval (shaded area) and the area defined by the expected parameter and its
tolerance.
119
Fig. V.4.- Location of confidence interval measured for the jitter period limits.
The second approach used was to measure the output frequency generated at several
input points. Table IV.5 shows the measured data. The mean value and its deviation from
the expected value were calculated using (V.1) and (V.2).
INPUT
FREQUENCY
(Hz)
57
58
59
60
61
62
63
Table V.5.- Measured frequency variation.
OUTPUT
FREQUENCY
STANDARD
THEORETICAL
MEASURED
DEVIATION
UPPER LIMIT
MEAN VALUE
(mHz)
(Hz)
(Hz)
57.0014
3.871917
56.9471
58.0021
7.988772
57.9452
59.0005
7.290333
58.9433
60.0007
0.783854
59.9414
60.9971
8.323771
60.9394
62.0015
9.133732
61.9374
62.9998
2.592957
62.9354
THEORETICAL
LOWER LIMIT
(Hz)
57.0529
58.0548
59.0567
60.0586
61.0606
62.0626
63.0646
The design of the ADPLL included a ripple reduction scheme. The XOR phase
comparator provides a 50% duty cycle output. The ADPLL, by design, has a frequency
relationship defined as:
fo =
1
1
1
±
fi f DCO
(V.5)
where fDCO is the clock signal of the digital controlled oscillator of the ADPLL.
A rough approximation for (V.5) is:
fo = fi ± 0.000984 ⋅ fi
120
(V.6)
After analyzing the experimental data (Table V.5), the relationship between input and
output frequencies can be defined by:
fo = 0.0001238 fi2 + 0.985 fi + 0.466
(V.7)
Fig. V.5.- Input – Output ADPLL response.
The output frequency showed a maximum deviation from the ideal nominal value of
9.265 mHz when the input frequency was set at 62 Hz, and is within the expected values
defined by (V.7).
V.2.4.- TEST 4: PHASE SHIFT OF ADPLL
The phase shift measurement was taken making an input frequency sweep from 57
to 63 Hz. Figure V.6 shows the shift correction performed on the ADPLL output signal, the
upper signal is the ADPLL input signal, the middle signal is the normal ADPLL output
signal, the lower signal is the corrected output signal. Table V.6 shows the measured data.
The mean value and its deviation from the expected value were calculated using (V.1) and
(V.2).
Table V.6.- Measured phase shift.
INPUT
MEASURED
STANDARD
FREQUENCY (Hz) MEAN VALUE (deg) DEVIATION (deg)
57
-0.8104
0.8250
58
-0.7599
0.7742
59
-0.6589
0.6704
60
-0.5382
0.6107
61
-0.7056
0.7179
62
-0.8054
0.8198
63
-0.7265
0.7392
121
Fig. V.6.- Oscillogram of phase shift correction measurement. Upper: input signal, Middle: normal output
signal, Lower: corrected output.
Recalling that the phase shift of the ADPLL depends upon the type of its phase
detector, for a XOR detector, this error is between –90° and 90°, and it is zero at central
frequency. The phase error, expressed in degrees, can be determined using:
φe =
(
360° ⋅ 2 ⋅ K ⋅ N ⋅ fi − fc
)
kd ⋅ M ⋅ fc
(V.8)
where
kd
fi
is the gain of the phase detector (kd = 2 for an XOR detector)
is the input frequency,
Using K=32, N=512, M*fc=245,760 Hz, kd=2 and fc=60 Hz, the ADPLL phase
error behavior defined as (Figure V.7):
φ
e
= 24 ⋅ fi − 1440
(V.9)
With the data gathered in test 4, an analysis was performed and a new function was
defined:
φ e = 24.018 ⋅ fi − 1442
(V.10)
Figure V.8 shows the measured phase error response of the ADPLL. The measured
data exhibited a maximum deviation of 1.03 degrees from the expected ideal value. This
error response, inherent to the PLLs, is not suitable for the generation of the sinusoidal
122
output waveform. To correct this response, the Phase Shift Correction circuit should be able
to provide a near zero phase error response. The analysis of the measured response of the
Phase Shift Correction circuit shows that the phase shift is bounded between -0.538261º
and –0.810423º, and has a maximum deviation of 0.825071º from the expected value of
zero.
Fig. V.7.- Ideal phase error response of the ADPLL.
Fig. V.8.- Measured phase error response of the ADPLL.
The phase shift presents a sinusoidal behavior as shown in figure V.9, and is defined
as:
⎧0.155 * sin(0.822 * fi − 4.48) − 0.65,
⎩0.155 * sin(1.161* fi − 4.48) − 0.65,
φec = ⎨
fi ≤ fc
fi > fc
(V.11)
123
Fig. V.9.- Measured phase error response of the ADPLL with the phase shift correction circuit.
The frequency and phase shift characteristics of the ADPLL seen by the phase-toamplitude converter module are described by equations (V.7) and (V.11).
V.2.5.- TEST 5: TOTAL HARMONIC DISTORTION OF THE SINUSOIDAL
OUTPUT SIGNAL
The THD measurement was taken applying an input frequency sweep from
57 to 63 Hz. Figure V.10 shows the one of the data sets recorded to perform the THD
analysis in MATLAB. Table V.7 and Figure V.11 show the measured data. The mean value
and its deviation from the expected value were calculated using (V.1) and (V.2). The
expected THD values were obtained by simulation.
INPUT
FREQUENCY (Hz)
57
58
59
60
61
62
63
Table V.7.- Measured THD of the output signal.
EXPECTED THD
MEASURED THD
VALUE (%)
MEAN VALUE (%)
2.5245
2.4609
2.3678
2.4534
1.5805
1.8864
0.5528
0.8603
1.3077
1.3319
1.9310
1.9446
1.9785
2.0463
STANDARD
DEVIATION (%)
0.091980
0.094563
0.312726
0.314364
0.076379
0.061377
0.076249
The THD pattern of the signal generator can be related with the gain behavior of a
band-reject filter. One equation that describes this behavior is:
Gain( freq) =
(2 * π * freq * j )2 + (ωQo − Ho )* (2 * π * freq * j ) + ωo 2
(2 * π * freq * j )2 + (ωQo )* (2 * π * freq * j ) + ωo 2
where
freq
124
is the input frequency in Hertz,
(V.12)
ωo
Q
Ho
j
is the central frequency of the filter in rad/seg,
is the quality factor of the filter,
is the width of the rejection band in rad/seg.
is the imaginary operator.
Fig. V.10.- Recorded data used to perform the THD analysis in MATLAB.
Fig. V.11.- Measured THD values of the sinusoidal output signal.
The process to find a single equation describing this behavior is still under way.
However, a first approach has been drafted using equation (V.12) as a guide:
125
⎧⎪ Ho e Q Gain( freq) + 0.315 freq ≤ fc
THD( freq) = ⎨ 1075 − freq
Q
⎪⎩ Ho
Gain( freq) + 0.366 freq ≥ fc
0.1 e
freq
(V.13)
where
freq
Q
Ho
fc
is the input frequency in Hertz,
is the equivalent band pass quality factor of the ADPLL,
is the value of the module K filter,
is the central frequency of the ADPLL in Hertz.
The fit obtained with this equation still needs further adjustments but clearly relates
the design parameters of the ADPLL with the distortion present in the output sinusoidal
waveform. Using equation (V.13) as a guide, the data measured was fitted, and only the
constant terms of the equation had to be adjusted as shown in equation (V.14) and figure
V.11.
⎧⎪ Ho e Q Gain( freq) + 0.64 freq ≤ fc
THD( freq) = ⎨ 1200 − freq
Q
⎪⎩ 0.Ho
Gain( freq) + 0.72 freq ≥ fc
122 e
freq
(V.14)
This variation in the THD value of the generated sinusoidal signal is due to the
functional characteristic of the digital controlled oscillator (DCO) in the ADPLL. In an
analog or hybrid PLL, the voltage controlled oscillator adjust its output frequency linearly
according to the input control signal; in an all-digital PLL, the output frequency of the DCO
has a fixed input frequency equals to 2*N*fc, and it “simulates” an adjustment in its output
frequency by skipping and passing clock pulses. The effect of this behavior over the phaseto-amplitude converter can be deduced from the variation of its input bus. Figure V.12
shows the equivalent signal generated by this bus when the input frequency is 57 Hz and it
is compared with an “ideal” equivalent signal.
Fig. V.12.- Effect of DCO frequency variation over the input bus of the combinational ROM.
126
This effect can be reduced, but not eliminated, by redesigning the ADPLL, specially
the values of holding range and the equivalent Q-value. By reducing the holding range the
equivalent Q-value is automatically increased. From equation (V.4), the relationship
between the holding range and the ratio N/M can be obtained:
N
fc
=
M 2 ∆f (2 K + 1)
(V.15)
From equation (V.15), a reduction in ∆f represents an increase in the ratio of N/M.
Now lets us examine the equation that defines the equivalent Q-value of the ADPLL:
Q=
2 π fK ⎛ N ⎞
⎜ ⎟
Kd ⎝ M ⎠
(V.16)
An increment in the value of the N/M ratio produce a direct increment in the value
of Q. Substituting (V.15) in (V.16) a new equation relating the holding range with the
equivalent Q-value can be obtained:
Q=
πK
⎛ fc ⎞
⎜ ⎟
Kd (2 K + 1) ⎜⎝ ∆f ⎟⎠
(V.17)
To improve the THD performance of the system by increasing the equivalent Qvalue of the ADPLL some considerations should be taken:
a) the value assigned to K must be a power of 2,
b) the value assigned to N must be a power of 2 (this affects the minimum holding
range value).
With this considerations in mind, the only ADPLL parameter that can be “freely”
changed is the value of M. Changing the value of M to a value different from a power of 2
represents the need of two crystals, or some other method for providing the clock signals to
the ADPLL’s Module-K counter and the DCO.
This approach was tested using simulations and the maximum THD value obtained
at 57Hz was 1.87%, still a high value. Most likely, an improvement in this performance can
be achieved by adding a filtering stage after the phase-to-amplitude converter.
V.2.6.- TEST 6: AMPLITUDE AND OFFSET LEVEL OF THE SINUSOIDAL
OUTPUT SIGNAL
The amplitude and offset level measurements were taken applying an input
frequency sweep from 57 to 63 Hz. Table V.8 shows the measured data. The mean value
and its deviation from the expected value were calculated using (V.1) and (V.2), the
expected amplitude level was set to 2.5 Vpeak with an offset level of 0V.
127
INPUT
FREQUENCY
(Hz)
57
58
59
60
61
62
63
Table V.8.- Measured amplitude and offset level of the output signal.
MEASURED
STANDARD
MEASURED STANDARD
EXPECTED
PEAK-TO-PEAK
DEVIATION
OFFSET
DEVIATION
PEAK-TOMEAN VALUE
(mV)
LEVEL (mV)
(mV)
PEAK (V)
(V)
5.0
4.9746
25.8346
5.8276
5.9279
5.0
4.9736
26.9233
5.0387
5.1278
5.0
4.9732
27.2447
6.0060
6.1106
5.0
4.9778
22.6185
2.9367
2.9928
5.0
4.9795
20.8851
3.9112
4.0016
5.0
4.9802
20.1987
4.1181
4.1913
5.0
4.9792
21.2540
4.3782
4.4542
Fig. V.13.- Amplitude
The amplitude of the reference signal generated depends greatly on the adjustment
procedure of the op-amp used to eliminate the offset level at the DAC output. Due to the
output low frequency, a non-significant drift in amplitude is expected within the holding
range of the DSG.
With the data of Table V.8 and the tolerance assigned, the amplitude of the
generated signal is tested using equations (IV.1), (IV.2), (IV.5), (IV.6) and (IV.7).
The measured amplitude of the output signal has a mean value of 4.976927 Vpp
with a standard deviation of 23.37 mVpp. The confidence interval and the parameter limits
are:
µˆ 1 = 4.974186 Vpp
µˆ 2 = 4.979667 Vpp
V1 = 4.975Vpp
V2 = 5.025Vpp
128
These values do not comply with the relationship in equation (IV.7) since V1 < µ̂1 ,
however, µ̂1 is -0.516% away form the central value of 5 Vpp. Figure V.14 shows the
confidence interval (shaded area) and the area defined by the expected parameter and its
tolerance.
Fig. V.14.- Location of confidence interval measured for the amplitude of the generated signal.
V.2.7.- TEST 7: LINE FAULT THRESHOLD
The design limit for the detection of a fault line was set at 4.28 Vp, and the
detection of the return to a safe level was set at 4.34 Vp. For this test, the analog input
signal had been decreased from the nominal value (6 Vrms or nearly 8.5 Vp) until the line
fault flag was set. In a similar way, once the flag was set, the analog input signal had been
increased until it was reset.
Table V.9 shows the measured values of the upper and lower holding values, their
standard deviation from the expected limit and relative error. The mean value and its
deviation from the expected value were calculated using (V.1) and (V.2).
Setting flag limit
Resetting flag limit
Table V.9- Measured threshold line fault limits.
STANDARD
EXPECTED
MEASURED MEAN
DEVIATION
VALUE (Vp)
VALUE (Vp)
(mVp)
4.28
4.2759
6.6563
4.34
4.3360
6.5132
ERROR (%)
0.096
0.093
With this data and the tolerance assigned, the amplitude of the generated signal is
tested using equations (IV.1), (IV.2), (IV.5), (IV.6) and (IV.7).
The measured amplitude of the setting flag limit has a mean value of 4.2759 Vp
with a standard deviation of 6.6563 mVp. The confidence interval and the parameter limits
are:
µˆ 1 = 4.273835 Vp
129
µˆ 2 = 4.277964 Vp
V1 = 4.2586 Vp
V2 = 4.3014 Vp
These values comply with the relationship in equation (IV.7). Figure V.15 shows
the confidence interval (shaded area) and the area defined by the expected limit and its
tolerance.
Fig. V.15.- Location of confidence interval measured for the amplitude of setting flag limit.
The setting flag point also can be defined as:
Vi( SETTING ) = 4.2759 ± 0.01996 V
The measured amplitude of the resetting flag limit has a mean value of 4.3360 Vp
with a standard deviation of 6.5132 mVp. The confidence interval and the parameter limits
are:
µˆ 1 = 4.333979 Vp
µˆ 2 = 4.338020 Vp
V1 = 4.3183Vp
V2 = 4.3617 Vp
These values also comply with the relationship in equation (IV.7). Figure V.16
shows the confidence interval (shaded area) and the area defined by the expected limit and
its tolerance.
130
Fig. V.16.- Location of confidence interval measured for the amplitude of resetting flag limit.
The resetting flag point also can be defined as:
Vi( RESETTING ) = 4.3360 ± 0.01953 V , with a 90% confidence level.
V.2.8.- TEST 8: RULE DECODER
The test of the rule decoder was carried on by simulating the eight different input
conditions defined in Table IV.2. The measured data were processed using (V.1) and (V.2)
to obtain the mean value, and its deviation, of the phase angle between the output analog
signals. The expected phase angle between the output signals is 120 deg.
Fig. V.17.- Rule decoder
131
Table V.10.- Measured phase angle between output signals.
φBC
φCA
φAB
φAB
φBC
φCA
MEASURED
MEASURED
MEASURED
INPUT
STANDARD
STANDARD
STANDARD
MEAN
MEAN
MEAN
CONDITION
DEVIATION
DEVIATION
DEVIATION
VALUE
VALUE
VALUE
(deg)
(deg)
(deg)
(deg)
(deg)
(deg)
1
120.4239
0.4530
120.0471
0.1651
119.3965
0.6377
2
120.0633
0.2517
120.3068
0.5269
120.4452
0.5610
3
121.2144
1.2471
120.5739
0.5924
120.0452
0.1550
4
121.2591
1.3119
120.6862
0.7886
119.9452
0.1708
5
120.7240
0.7484
120.2556
0.3322
120.3527
0.3918
6
121.3196
1.3539
120.8833
0.9084
119.3129
0.7127
7
120.4288
0.4560
120.7921
0.8113
120.6457
0.6704
8
120.6987
0.7150
120.8757
0.8938
119.8949
0.1348
OVERALL
120.7665
0.8987
120.5528
0.6673
120.0048
0.4806
From the data in Table V.10, the value of the phase-to-phase angle of the output
signal can be defined as both a single value for every input condition and as a function of
the input condition (rule used to maintain the output signal).
Using the data measured, the average values of the phase-to-phase angle, with a
90% (a two standard deviation tolerance) confidence level, are defined as:
φ AB = 120.7665° ± 1.7974° ,
φ BC = 120.5528° ± 1.3346° ,
φCA = 120.0048° ± 0.9612° .
Fig. V.18.- Phase-to-phase angle.
V.3.- SIMULATION OF A REFERENCE SIGNAL GENERATOR FOR
COMPARISON
The proposed SRSG was designed to operate properly with four wire three-phase
voltage sources with no phase-jumps and no harmonic content. The performance of the
SRSG operating with amplitude balanced and unbalanced input voltages should be
132
compared with the performance of one reference generator reported in the literature. Phasejump and low order harmonic content conditions should be also reviewed.
*
Vde
*
Vβ
Vqe
e
LOW
PASS
FILTER
^
ω
VCO
^θ
Vα
V de
*
*
*
V bs
*
V cs
V qe
Vas
*
Vas
Vα
Vβ
REFERENCE
VOLTAGES
V bs
LINE
VOLTAGES V cs
Fig. V.19.- Reference generator presented by Chung [33].
The reference generator selected for comparison is the one presented by Chung [33]
(Figure V.19). This generator provides reference signals synchronized with the power lines,
it uses a single PLL controlled by the direct value extracted from the three-phase
transformation to a rotary reference frame. The PLL provides the value of the angle θ
required to perform the reference frame transformation. It is also used to perform the
inverse transformations required to generate the reference signals of amplitude V*de. The
PLL was designed to have a natural frequency equal to the line frequency and a dumping
factor of 0.7071 using the equations described by Chung.
Four input voltage conditions were simulated: input voltage balanced in both
amplitude and phase, input voltage with amplitude unbalance, input voltage with both
amplitude and phase unbalance, and input voltage balanced in both amplitude and phase
with a third harmonic. The comparison generator was simulated using
MATLAB/SIMULINK (Figure V.20a), meanwhile the SRSG was simulated using Pspice
(Figure V.20b).
(a) MATLAB/SIMULINK circuit.
133
DSTM1
Implementation = XTAL
ADC_ck
S1
U1
IN+ OUT+
IN- OUTEVALUE
V(%IN+, %IN-)/72+2.5
bin
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
bin
cin
eoc_C
cin
0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
ADC_3Phase
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
eoc_C
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
DAC8break
eoc_B
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
U2
DOB7
DOB6
DOB5
DOB4
DOB3
DOB2
DOB1
DOB0
eoc_C
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
SinRefSigGen
13
12
11
10
9
8
7
6
U3
13
12
11
10
9
8
7
6
1k
1k
0
ref_B
R3
r
1k
R4
1k
5
0
DB7
DB6
DB5
3
DB4 OUT
DB3
DB2
4
DB1 REF
DB0
AGND
DAC8break
R1
R2
5
DB7
DB6
DB5
3
DB4 OUT
DB3
DB2
4
DB1 REF
DB0
AGND
DAC8break
DOC7
DOC6
DOC5
DOC4
DOC3
DOC2
DOC1
DOC0
ref_A
r
o
xtal
DOA7
DOA6
DOA5
DOA4
DOA3
DOA2
DOA1
DOA0
o
c
eoc_B
eoc_B
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB7
DB6
DB5
3
DB4 OUT
DB3
DB2
4
DB1 REF
DB0
AGND
ref_C
R5
r
1k
R6
o
IN+ OUT+
IN- OUTEVALUE
V(%IN+, %IN-)/72+2.5
E3
b
ain
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
eoc_A
ADC_ck
ck
V
V
IN+ OUT+
IN- OUTEVALUE
V(%IN+, %IN-)/72+2.5
E2
V
a
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
eoc_A
V
E1
eoc_A
13
12
11
10
9
8
7
6
V
ain
SRSG
V
ADC
1k
5
0
(b) Pspice circuit.
Fig. V.20.- Circuits used to simulate the reference signal generators.
V.3.1.- Case 1: Input voltages balanced in both amplitude and phase.
For this simulation, a balanced voltage of 127 Vrms line-to-neutral was set, Figure
V.21 shows the implementation of the input voltage sources in both MATLAB-SIMULINK
(a) and Pspice (b).
(a)
(b)
Fig. V.21.- Voltage sources used to simulate a balanced voltage case. (a) MATLAB-SIMULINK
implementation. (b) Pspice implementation.
Both generators provided sinusoidal signals of the expected amplitude and shifted
120 degrees from each other. The simulation results are presented in figures V.22a and b.
134
(a) MATLAB/SIMULINK
(b) Pspice
Fig. V.22.- Simulation with balanced amplitude conditions.
The nominal values corresponding to this case are shown in Table V.11. The value
inside the parenthesis is the converted line-to-line voltage.
Table V.11.- Simulated nominal output values
of the compared generators.
Chung’s generator Proposed generator
Amplitude (Vp)
2.5
2.5 (4.33)
Phase (deg)
120
120
THD (%)
0
0.5
As expected, both reference generators performed according to their specifications.
V.3.2.- Case 2: Input voltages with unbalanced amplitude and balanced phase.
For the case of voltage unbalance, the amplitude of phase A was reduced to 70
Vrms (100 Vp), keeping phases B and C in their original values. The angle between phases
was kept at 120 degrees. The characteristics measured from the resulted waveforms were
amplitude, harmonic distortion and angle between phases.
135
The decrease of the amplitude of voltage phase A can be transformed from a four
wire Y to a three wire ∆ connection for its use with the Chung’s generator, resulting in the
following line-to-line voltages:
vab = 244.6 V sin(ωt )
(
)
.3 π )
vca = 244.6 V sin (ωt + 129
180
.3 π
vbc = 311.1V sin ωt − 101
180
The simulation performed in MATLAB-SIMULINK yielded the waveforms shown
in Figure V.23a. The reference signals generated have constant amplitude (2.5 Vp),
however, they are distorted and with non-symmetrical phase angles. The average THD of
these signals is 5.61% and the phase angles are -117.25, -130 and -112.78 degrees.
On the other hand, the simulation performed in Pspice, whose waveforms are
presented in Figure V.23b, presented better distortion and phase angle values. The
amplitude is in this case also constant. The average THD of the signals is 0.4955% and the
phase angles are kept at 120 degrees.
Under these input voltages, the Chung’s generator provides output signals of
constant amplitude, but with high distortion, greater than 5%. In contrast, the proposed
generator provides the nominal amplitude, phase angles and distortion values, clearly
outperforming the Chung’s generator. The values obtained are shown in Table V.12.
Phase
Vab
Vbc
Vca
Table V.12.- Simulation results of study case 2.
Amplitude (Vp)
THD (%)
Angle (degree)
“reference”
proposed
“reference”
proposed
“reference”
proposed
2.5
2.5
5.41
0.51
0
0
2.5
2.5
5.47
0.48
-117.25
-120
2.5
2.5
5.95
0.48
+112.78
+120
(a) MATLAB/SIMULINK
136
(b) Pspice
Fig. V.22.- Simulation with unbalanced amplitude conditions.
V.3.3.- Case 3: Input voltages with unbalanced amplitude and phase.
In this case, the voltage source was changed from four wire to three-wire
configuration. The amplitude of the three phases were set at 173, 220 and 173 Vrms, for
voltages AB, BC and CA. The phase angles were set to -130º, -128.65º and -101.35º. For
the connection of the voltages to the SRSG, a virtual ground was generated using the
resistor array shown in Figure V.24.
a
Ra
1k
b
Rb
1k
c
Rc
0
1k
Fig. V.24.- Resistor array used to generate a virtual ground for the SRSG.
Figure V.25a shows the waveforms obtained from the simulation performed in
MATLAB-SIMULINK. The reference signals generated have constant amplitude, however,
they are distorted and with non-symmetric phase angles. The average THD of these signals
is 6.13% and the phase angles are -130.90º, -116.53º and -112.58º.
Figure V.25b shows the waveforms obtained from the simulation performed in
Pspice. The reference signals generated referred to the virtual ground have constant
amplitude, but when translated to a three-wire system they are unbalanced, this is due to a
phase unbalance. However, the distortion level and phase angles are better than the
obtained in the MATLAB-SIMULINK simulation. The average THD of the signals is
0.6157% and the phase angles are -124.42º, -123.01º and -112.47º.
137
(a) MATLAB/SIMULINK
(b) Pspice
Fig. V.25.- Simulation with amplitude and phase unbalance conditions.
The Chung’s generator, as expected, kept the amplitude constant at the nominal
value, the phase angles of the output signals were degraded. Regarding the distortion of the
output signals, they were greatly degraded to an average of 6.13%. On the other hand, the
proposed generator provided output signals with unbalanced amplitude (the output of the
generator is transformed from a Y to a ∆ system). On the bright side, the phase angles were
improved. The distortion levels of the output signals were kept around 0.5% outperforming
again the Chung’s generator. The values obtained are shown in Table V.13.
Phase
Vab
Vbc
Vca
138
Amplitude (Vp)
THD (%)
Angle (degree)
“reference”
proposed
“reference”
proposed
“reference”
proposed
2.5
3.94
6.01
0.52
0
0
2.5
4.61
5.86
0.46
-130.91
-121.2
2.5
4.23
6.53
0.42
+112.55
+111.1
V.3.4.- Case 4: Balanced input voltages in both amplitude and phase and with a
10% third harmonic component shifted 10º in each phase.
In the last case simulated, a four-wire three-phase configuration was used. The input
voltages were generated with a 10% third harmonic component. For the simulation in
MATLAB-SIMULINK the voltage source was transformed into a three-wire configuration.
The third harmonic component had a 10º shift from each of the phase voltages.
Figure V.26a shows the waveforms obtained from the simulation performed in
MATLAB-SIMULINK. The reference signals generated have constant amplitude, but the
generated signals are distorted and with non-symmetric phase angles. The average THD of
these signals is 3.64% and the phase angles are –112.19º (BC), and +128.37º (CA) from
reference AB. There are also phase shifts between the input fundamental components and
the references generated. These phase shifts are -3.82º, -3.99º and +0.41º for phases AB,
BC and CA, respectively.
Figure V.26b shows the waveforms obtained from the simulation performed in
Pspice. The reference signals generated referred to the virtual ground have constant
amplitude and low THD levels with an average value of 0.66%, but present phase
unbalance of -124.55º (B) and +126.10º (C) from reference A. When translated to a threewire system, the amplitudes are unbalanced (+3.74%, -5.38% and +2.81% of the expected
nominal value), due to the phase unbalance. However, the distortion levels are better than
the one obtained in the MATLAB-SIMULINK simulation. The average THD of the signals
is 0.47%, the phase angles are similar to the ones of the MATLAB-SIMULINK, -118.11º
(BC), and +125.86º (CA) from reference AB. The phase shifts from the fundamental
component are -2.85º, -0.94º and +2.97º for phases AB, BC and CA respectively.
(a) MATLAB/SIMULINK
139
(b) Pspice
.
Fig. V.26.- Simulation with 10% third harmonic component.
The Chung’s generator kept the amplitude constant at the nominal value, the angles
of references Vbc and Vca with respect to Vab were shifted, this represents a phase jump
induced by the harmonic distortion of the input signals. Regarding the distortion of the
output signals, they were degraded to an average of 3.64%. Also, there are phase shift
between the input fundamental component and the output signals. The proposed generator
provided output signals with amplitude unbalance. On the bright side, the distortion levels
of the output signals were kept around 0.5% outperforming again the Chung’s generator.
The phase angles of phases Vbc and Vca were also shifted. There are also phase shifts with
the input fundamental components. These last values are marginally better than the
obtained by the Chung’s generator. The values obtained are shown in Table V.14.
Amplitude (Vp)
THD (%)
Angle (degree)
Shift in-out (degree)
Phase “reference” proposed “reference” proposed “reference” proposed “reference” proposed
Vab
2.5
4.43
3.77
0.49
0
0
-3.82
-2.85
Vbc
2.5
4.04
3.78
0.50
-112.19
-118.11
-3.99
-0.94
Vca
2.5
4.39
3.39
0.42
+128.37
+125.86
+0.41
+2.97
It becomes clear that further improvement in the structure of the proposed generator
has to be performed to compensate unbalanced phase conditions. This can be done by
expanding the function performed by the decision block and modifying the phase shift
corrector block. The functions to be added in the decision block must identify the phase
unbalance and decide which phase should be taken as the “reference” to balance the angles.
For this scenario, the phase shift corrector block should not only compensate the phase
error generated by the ADPLL but also balance the angle between the output signals
accordingly to the control signals generated by the decision block.
140
V.4.- SUMMARY
This chapter presented the experimental data gathered and their analysis of the
sinusoidal reference signal generator. The testing was divided in eight tests. Some test
measured the performance parameters of the ADPLL+phase-shift-corrector sub-blocks,
such as, holding range, pull-in range, frequency jitter and input-output phase shift. A
second set of tests measured the static characteristics of sinusoidal signals (THD levels and
amplitude). The performance of the rule decoder was also tested.
The measured data of the generator were compared with the design parameters
and/or characterized with equations. The tolerance of the design parameters was small
(±0.5%) and served to define the intervals where the measured data must be found. Most of
the measured parameters were found inside these intervals. Only the jitter and the
amplitude of the generated signals were slightly out of limits (0.003% and 0.016%
respectively). The THD and phase angle between the output signals were characterized as
equations. For the THD, a relationship with the design parameters of the ADPLL block and
the behavior of a reject band filter was drawn.
Additionally, a set of test simulations was performed. These simulations were
designed to provide information about the performance of the SRSG when the input
voltages are unbalanced. A reference generator reported in the literature was also simulated
to be used as a reference frame. This testing showed that the proposed generator has an
outstanding performance when voltage sags are presented in a four-wire Y system with no
phase jumps. On the down side, its performance is diminished when phase jumps are
present.
141
CHAPTER VI.- THREE PHASE PWM AC/AC CÚK
CONVERTER TESTING AND
PERFORMANCE ANALYSIS
VI.1.- INTRODUCTION
This chapter presents the experimental results obtained from a three phase PWM
AC/AC Cúk converter. The tests complied with the protocols described in the previous
chapter. For the analysis of the performance parameters of the converter, the maximum
tolerance allowed for voltage regulation is set at ±3%, +5% for THD levels and the
response time must comply with the ITIC curve. The experimental data is assumed to have
a normal distribution function and the number of samples (N) per parameter is at least 30.
VI.2.- EXPERIMENTAL TESTING
The PWM AC/AC Cúk converter was submitted to eight specific tests. The block
diagram of the system and the laboratory setup are shown in Figures VI.1 and VI.2.
n
c
c’
δc
b’
b
Vac
n
δb
a’
a
n
XFRM
RSG
δa
XFRM
n
Fig. VI.1.- Block diagram of AC/AC converter and its control stage.
143
Fig. VI.2.- Laboratory setup.
VI.2.1.-TEST 1: OUTPUT VOLTAGE REGULATION
For this test, nineteen input voltages were selected, ranging from 70 Vrms through
165 Vrms. The output voltage was measured in all three phases. Figure VI.3 shows an
oscillogram of the converter’s output voltages. The data recorded was processed with a
MATLAB program to obtain the RMS values shown in Table VI.1.
Fig. VI.3.- Converter output voltage.
144
Input
Voltage
(Vrms)
70
75
80
85
90
95
100
105
110
115
Phase A
Output
(Vrms)
125.4346
125.3023
125.4969
125.5224
125.5470
125.7557
125.6476
125.7034
125.7306
125.9966
Table VI.1.- RMS value of the output voltage.
Phase B
Phase C
Input
Phase A
Output
Output
Voltage
Output
(Vrms)
(Vrms)
(Vrms)
(Vrms)
125.6970
126.8737
125.9522
120
125.7795
126.9079
126.3292
127
125.7828
126.9259
126.3085
130
125.7978
126.8757
126.7756
135
125.8969
126.9387
127.1300
140
125.8493
126.8726
127.1312
145
125.8227
126.8608
127.3348
150
125.9316
126.9388
127.0411
155
126.0734
127.0411
126.8400
160
126.2081
127.1381
125.6178
165
Phase B
Output
(Vrms)
126.3140
126.8034
126.5932
127.1427
127.5059
128.0576
128.1557
129.0531
129.8056
130.5090
Phase C
Output
(Vrms)
127.3631
127.5249
127.5142
127.5804
127.7734
127.9391
128.0661
128.6144
128.5880
128.9275
Using the data in Table VI.1, the mean value of the phase-to-neutral output voltage
over the input voltage range and the regulation error can be drawn. The mean value of the
output voltage, and its percent drift are found to be:
Van = 126.130 Vrms +0.955%, -0.656%,
Vbn = 126.939 Vrms +2.812% -0.978%,
Vcn = 127.463 Vrms +0.955% -0.656%.
The regulation error vs. input voltage can be plotted using the data yield from:
Regulation Error (%) =
Vxn − 127V
⋅ 100
127V
(VI.1)
where
Vxn
is the phase to neutral output voltage.
Fig. VI.4.- Regulation error vs. input voltage.
From figure VI.4, it can be seen that the output voltage is always within a ± 3% of
the nominal level (127 Vrms), complying with the design regulation goal.
145
VI.2.2.-TEST 2: OUTPUT VOLTAGE TOTAL HARMONIC DISTORSION
For this test, as in test 1, nineteen input voltages were selected from 70 Vrms
through 165 Vrms. The output voltage was measured in all three phases. The data recorded
was processed with a MATLAB-SIMULINK program to obtain the THD values shown in
Table VI.2.
Input
Voltage
(Vrms)
70
75
80
85
90
95
100
105
110
115
Phase A
Output
THD (%)
2.505
2.661
2.533
2.527
2.501
2.419
2.149
2.200
2.141
1.988
Table VI.2.- THD value of the output voltage.
Phase B
Phase C
Input
Phase A
Output
Output
Voltage
Output
THD (%)
THD (%)
(Vrms)
THD (%)
3.459
2.627
1.935
120
3.872
2.675
2.010
127
3.837
2.766
1.980
130
3.723
2.855
2.000
135
3.999
2.801
140
2.271
3.762
2.695
145
2.359
3.828
2.788
150
2.653
3.508
2.707
155
2.913
3.467
2.653
160
3.246
3.457
2.451
165
3.914
Phase B
Output
THD (%)
3.331
3.114
3.245
3.112
3.075
3.133
3.126
3.284
3.498
3.673
Phase C
Output
THD (%)
2.229
2.218
2.233
2.191
2.142
1.966
2.126
2.274
2.326
2.431
The design goal regarding the THD was maximum 5%, which is 3 percentage points
below the limit established in section 5.2.1 by the IEC62040-3. Another goal was to
comply with the individual harmonic limits established in that section of the standard.
Figure VI.5 shows the THD levels obtained for each output phase over the input voltage
range.
Fig. VI.5.- THD levels vs. input voltage.
From figure VI.5, it is clear that the first goal was successfully achieved. To
evaluate the second goal, the highest and the lowest THD level of each phase was
processed with a MATLAB program. The results are shown in Figures VI.6a through VI.6f.
146
(a) Phase A highest THD level
(b) Phase A lowest THD level
(c) Phase B highest THD level
(d) Phase B lowest THD level
(e) Phase C highest THD level
(f) Phase C lowest THD level
Fig. VI.6.- Harmonic components of output voltages, highest and lowest levels per phase.
All three phase signals with the highest THD levels exceeded the allowed limits of
harmonic component 15, 21 and 27, and phases A and B also exceeded harmonic 33rd limit.
The magnitude of these harmonic components and the difference with the limit are shown
in Table VI.3.
147
Table VI.3.- Harmonic components exceeding the standard limit.
Harmonic
Measured
Standard
Difference
Component Magnitude (%)
Limit (%)
15
0.6757
0.3000
0.3757
21
0.5435
0.2000
0.3435
PHASE A
27
0.4092
0.2000
0.2092
33
0.2301
0.2000
0.0301
15
0.5109
0.3000
0.2109
21
0.4526
0.2000
0.2526
PHASE B
27
0.3326
0.2000
0.1326
33
0.2029
0.2000
0.0029
15
0.3894
0.3000
0.0894
PHASE C
21
0.3474
0.2000
0.1474
27
0.2504
0.2000
0.0504
These levels of THD and the non-compliance with the standard’s limits are mostly
due to a poor adjustment on the offset level of the analog input signal feeding the ADC.
This offset generates a displacement in the zero-crossing detector of the DSG. This
displacement is transferred to the output signal of the PWM AC/AC converter as a zerocrossing distortion, as shown in Figure VI.7. This distortion can be easily reduced by
properly adjusting the offset level of the analog input signal to the DSG.
Fig. VI.7.- Zero-crossing distortion of Van, Vbn and Vcn.
VI.2.3.- TESTS 3-8: RESPONSE TIME TO INPUT STEPS
For Test 3 through 8, the threshold limit of the ADPLL’s line fault detector was
shifted from 63.5 Vrms (line input) to 75 Vrms in order to activate the rule decoder under
the test conditions.
For tests 3 through 5, a step input voltage from 127 Vrms to 80 Vrms (a sag to 63%)
had been applied. The sag was designed to start at 90° of one of the phases under test. The
thirty digitalized output waveforms per phase were averaged using (V.1) in order to have a
cleaner signal in which the measurement of the response time was easier.
148
The response time was measured using the error generated by the difference of the
original steady state output waveform and the current output waveform, as described in:
error (%) =
VCURRENT −VSTEADY STATE
⋅100
VSTEADY STATE
(VI.2)
Using the waveform generated with equation (VI.2), the instants were the error falls
below the 10 and 5% limit were found. The data was processed with a MATLAB program.
Table VI.4.- Response time of the converter under input voltage step.
RESPONSE
RESPONSE
RESPONSE
PHASE A PHASE B PHASE C
TIME
TIME
TIME
TEST
VOLTAGE VOLTAGE VOLTAGE
PHASE A (mS) PHASE B (mS)
PHASE C (mS)
(Vrms)
(Vrms)
(Vrms)
10%
5%
10%
5%
10%
5%
8.11
17.46
125.3052
125.6528
3
6.04
7.71
6.89
10.76
125.2620
4
6.75
8.25
7.97
9.76
5
5.93
7.43
3.65
4.64
3.98
10.92
6
9.45
12.45
4.65
5.66
4.49
6.70
7
5.12
8.86
2.52
4.32
5.31
7.79
8
Fig. VI.8.- Converter output voltage.
Figure VI.9 was drawn with the mean recovery times of the system. This figure
shows that the steady state is reached in approximately 1.5 input cycles. This time should
be seen within the ITIC curve (figure VI.10a) context. In this context, the maximum
duration of an outage or an under voltage condition of 70% of nominal value is 20 ms
(approximately 1.2 cycles), if the system recovery time is inserted into the ITIC curve
(figure VI.10b). It can be seen that the system response is fast enough to keep the output
voltage within the operational limits imposed by the curve.
149
Fig. VI.9.- System response to input voltage steps.
(a) ITIC curve.
(b) ITIC curve including the system response.
Fig.VI.10.- ITIC curve.
VI.3.- SUMMARY
This chapter presented the experimental data gathered from the PWM AC/AC Cúk
converter. The tests were divided in two groups: static and dynamic tests. Static tests were
aimed at measuring the THD and output voltage regulation of the converter. These tests
showed the performance of the SRSG under noisy steady state conditions. The dynamic
tests, on the other hand, were aimed at measuring the time response of the converter under
deep sags, they also provide an insight of the ability of the rule decoder to maintain a steady
set of reference signals.
The analysis of the behavior of the AC/AC converter showed that a tight regulation
and low THD levels can be obtained using the proposed generator, both design
specifications were easily complied. Only the amplitude of some particular harmonics were
above the allowed levels, however, this can be corrected with better adjustment of the
control stage. The performance of the converter under voltage sags was also very good.
150
CHAPTER VII.- CONCLUSIONS AND FUTURE WORKS
This dissertation presented a new scheme for the implementation of a sinusoidal
reference signal generator applied to AC-output power electronic systems with utility
synchronization.
The development of the proposed three-phase sinusoidal reference signal generator
presented interesting challenges, which ranged from avoiding the use of Clark and Park
transformations, while providing enough noise immunity, to obtain a minimum silicon
implementation. The basic concepts behind the signal generator were presented in chapter
II. These concepts led to the design of each of the component blocks of the proposed
generator. The final implementation is compact and reliable.
The basic operational principles of AC/AC converters were presented in chapter III.
Single-phase topologies were covered operating in both continuous and discontinuous
conduction modes. Besides the classical approach of studying the operation of the
converters with a linear resistive load, modification in the driving of the switches pattern
when feeding linear inductive-resistive and non-linear capacitive loads was also presented.
The design of a three-phase AC/AC converter was presented from the selection of its
components through the control stage implementation.
A prototype to test the proposed generator was built. The generator used a basic
analog-to-digital conversion stage and was controlled by the CPLD containing the digital
structure. For the power electronic converter, additional stages of drivers, feedback
conditioning and control stages were built to assemble a closed loop AC power
conditioning system.
The experimental procedure was divided in two parts. The first part was performed
to the generator operating with ideal input signals. Several tests were carried out to each of
the component blocks of the proposed generator. These tests were compiled in a testing
protocol, and were designed to help characterizing the performance of the generator. The
second part was designed to characterize the AC/AC converter in static and dynamic input
conditions and to see the performance of the generator under noisy input signals.
Additionally, some simulation test were performed for comparison of the proposed
generator against a basic classic generator. These simulations were designed to provide
information about the performance of the proposed generator when the input voltages are
unbalanced.
One particular result from the data analysis that looks very interesting was the
relationship between the ADPLL design parameters, and the THD level of the sinusoidal
reference signal generated. This relationship still needs further study, using various values
of Q as well as different ADPLL structures, to develop a general equation for the THD
levels generated by digital signal generators synchronized with the utility. Another
important characteristic of the SRSG was the small phase error between the analog input
signal and the reference signal generated (<1deg). The distortion problems associated with
151
zero crossing displacement, in applications such as UPS or AC regulation in a single stage,
can be greatly reduced.
The performance of the three-phase sinusoidal reference signal generator fulfilled
the design specifications and expectations providing a stable three-phase sinusoidal
waveform suitable for control applications. To test the immunity of the SRSG to noisy
utility conditions, it was included in the control loop of a high-frequency PWM AC/AC
Cúk converter. To test the stability of the reference signal generated, large sags signals
were applied to the converter. In all the cases studied, both the SRSG and the PWM
AC/AC Cúk converter presented a good response.
Regarding the PWM AC/AC Cúk converter, the fact of having three independent
converters to implement a three-phase solution raised the question of how the converters
would interact. Several issues were taken into account: the PCB layout and the
synchronization of the PWM controllers, among others. The structure proved to be stable
and with no apparent interference between the converters. There are some issues related to
PWM AC/AC converters that still need to be studied beyond the scope of this research: bidirectional switch implementation, the operation with non-linear loads, and the behavior
under different control structures such as the one used with DC/DC converters for power
factor correction in continuous conduction mode.
The test under unbalance conditions showed that the proposed generator has an
outstanding performance when voltage sags are presented in a four wire Y system with no
phase jumps. However, for operation with phase jumps and harmonic components it
became clear that further improvement in the structure of the proposed generator had to be
performed. Expansion of the function performed by the decision block and modification of
the phase shift corrector block should be explored as well as digital filters to eliminate the
low frequency harmonic components.
Finally, partial research results were used to generate publications in recognized
international conferences and journals.
Single Phase Voltage Sag Compensation System Based on a Modified Flyback Converter
J. Hoyo, H. Calleja, J. Arau, IEEE 33rd POWER ELECTRONICS SPECIALISTS CONFERENCE PESC
2002. Cairn, Australia, June 23-27, 2002
Study of an AC-AC Flyback Converter Operating in DCM
J. Hoyo, H. Calleja, J. Arau, IEEE 34th POWER ELECTRONICS SPECIALISTS CONFERENCE PESC
2003. Acapulco Mexico, June 15 – 19, 2003
A High Quality Output AC/AC Cuk Converter
J. Hoyo, J. Alcalá, H. Calleja, IEEE 35th POWER ELECTRONICS SPECIALISTS CONFERENCE PESC
2004. Aachen, Germany, June 20-25, 2004
High-Quality Output PWM AC Voltage Regulator based on Cuk Converter
J. Hoyo, H. Calleja, J. Alcalá, INTERNATIONAL JOURNAL OF ELECTRONICS, APRIL 2005, VOL. 92,
No. 4, pp. 231-242
Reference Generator for A Four-Wire Three-Phase AC/AC Converter
J. Hoyo, H. Calleja, J. Arau, IEEE Transactions on Industrial Electronics (Submited for revision)
152
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
ADC_A_07
ADC_A_06
ADC_A_05
ADC_A_04
ADC_A_03
ADC_A_02
ADC_B_CK
ADC_B_07
ADC_B_06
ADC_B_05
ADC_B_04
ADC_B_03
ADC_B_02
ADC_C_CK
ADC_C_07
ADC_C_06
ADC_C_05
ADC_C_04
ADC_C_03
ADC_C_02
*
*
ADC_soc
I36
I1
I2
I3
I4
I5
I6
I19
I7
I8
I9
I10
I11
I12
I20
I13
I14
I15
I16
I17
I18
I21
CK60
DC120
DC240
ADPLL_C
DB120
DB240
ADPLL_B
DA120
DA240
I35
CK60
Mfc
Nfc
Nfc
Mfc
Nfc
Mfc
Mfc Nfc
N0
N1
N2
Fin
N3
N4
N5
N6
N7
N8
I27
ADPLL1
Mfc Nfc
N0
N1
N2
Fin
N3
N4
N5
N6
N7
N8
I24
ADPLL1
I32
D240
D120
A0
A1
A2
A3
A4
A5
A6
A7
A8
I26
D240
D120
A0
A1
A2
A3
A4
A5
A6
A7
A8
N0
N1
N2
N3
N4
N5
N6
N7
N8
I31
D240
D120
A0
A1
A2
A3
A4
A5
A6
A7
A8
SHIFT_CORRECTOR
Fin
N0
N1
N2
N3
N4
N5
N6
N7
N8
SHIFT_CORRECTOR
Fin
N0
N1
N2
N3
N4
N5
N6
N7
N8
DA04
DA03
DA02
D4
D3
D2
D0
I25
DB05
D0
D1
D2
D3
A0
A1
A2
A3
A4
A5
A6
A7
A8
DC01
DC00
D0
5555 Northeast Moore Ct.
Hillsboro, Oregon 97124
Lattice Semiconductor Corp.
I29
DC02
D1
DC03
DC04
DC05
DC06
DC07
D2
D3
D4
D5
D6
D7
DB00
DB01
DB02
DB03
DB04
DB06
D5
D4
DB07
D6
DA00
D7
ROM128
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROM128
I30
DA05
D5
DA01
DA06
D6
D1
DA07
D7
ROM128
A0
A1
A2
A3
A4
A5
A6
A7
A8
Date:
Name:
Title:
15/07/2005
MAIN
Sheet
1
of
1
SIGNAL
ADC_ck
CLOCK_GEN
Mfc
xtal
Nfc
ADC_C_02
I23
ADC_C_03
ADC_C_04
ADC_C_05
ADC_C_06
ADC_C_07
ADC_C_CK
ADC_B_02
ADC_B_03
ADC_B_04
ADC_B_05
ADC_B_06
ADC_B_07
ADC_B_CK
ADC_A_02
ADC_A_03
ADC_A_04
ADC_A_05
ADC_A_06
ADC_A_07
DECISION_BLOCK
ADC_A_CK ADPLL_A
Mfc Nfc
N0
N1
N2
Fin
N3
N4
N5
N6
N7
N8
I28
ADPLL1
SHIFT_CORRECTOR
Fin
REFERENCE
XTAL
I34
*
ADC_A_CK
Nfc
Mfc
APPENDIX
A.SINUSOIDAL
SCHEMATICS AND CODING
GENERATOR
Fig. A.1.- Schematic diagram of the SRSG.
153
Fig. A.2.- ADPLL schematic diagram.
Fig. A.3.- Phase detector schematic diagram.
154
I12
DnUp
En
D
I31
I11
D
Q
Q
Q
I9
D
Q
I7
D
Q
D
Q
dec
Q
inc
I30
I25
I27
I24
I6
MFc
I10
D
I13
D
D
I28
Q
I23
I5
Q
I22
I4
D
Q
I20
I3
D
Q
I1
D
Q
D
I29
I19
I18
I17
I16
I14
I26
Title:
MODULE_K
Name:
Date:
05/08/2004
Sheet
1
of
1
Fig. A.4.- Module K schematic diagram.
x13
I112
D
inc
Q
x1
D
Q
x2
D
Q
x11
x3
I110
Tff
I109
I107
Q
x13
nNFc
I111
I118
Tff
J
nNFc
I54
I119
x14
NFc
I108
D
x5
dec
D
Q
I106
x4
D
Q
I105
x5
D
Q
I63
Q
IDout
K
I113
x6
I116
x12
I114
I104
D
Q
x14
Tff
I115
I117
Title:
ID_COUNTER
Name:
Date:
09/12/2004
Sheet
1
of
1
Fig. A.5.- ID counter schematic diagram.
155
MODULE feedback
INTERFACE (ck -> U2, U3, N8, N7, N6, N5, N4, N3, N2, N1, N0);
TITLE 'FEEDBACK COUNTER'
DECLARATIONS
ck pin;
N8..N0 pin istype 'reg';
U2, U3 pin;
Count = [N8..N0];
EQUATIONS
Count.clk = ck;
Count := Count + 1;
U2 = N8;
U3 = !N7;
END
Fig. A.6.- Feedback counter program coding.
Fig. A.7.- Shift corrector schematic diagram.
156
MODULE PHASE_BC
INTERFACE (N0, N1, N2, N3, N4, N5, N6, N7, N8 -> D120, D240);
TITLE 'PHASES B and C'
DECLARATIONS
N8..N0 pin;
D120, D240 pin;
EQUATIONS
D120 = (!N8 $ (N7 & (N6 # N5 & (N4 # N3 & (N2 # N1 & N0)))));
D240 = (N8 $ (N7 # N6 & (N5 # N4 & (N3 # N2 & N1))));
END
Fig. A.8.- Shifted signals generator program coding.
Fig. A.9.- Phase-to-Amplitude converter schematic diagram.
157
MODULE COMBINATIONAL
INTERFACE (AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8 -> R0, R1, R2, R3,
R4, R5, R6);
TITLE 'SINUSOIDAL TABLE'
DECLARATIONS
AD8..AD0 pin;
R6..R0 pin;
EQUATIONS
R6 = AD6 # (AD5 & AD4)
# !AD6 & AD5 & !AD4 & (AD3 & AD2);
R5 = AD6 & (AD5 # AD4)
# AD6 & !AD5 & !AD4 & (AD3 # AD2 & AD1)
# !AD6 & AD5 & !AD4 & (!AD3 # !AD2)
# !AD6 & !AD5 & AD4 & (AD3 # AD2 & AD0 # AD2 & AD1);
R4 = AD6 & AD5
# AD6 & !AD5 & AD4 & (AD3)
# AD6 & !AD5 & !AD4 & (!AD3 & !AD2 # !AD3 & !AD1)
# !AD6 & AD5 & AD4 & AD3
# !AD6 & AD5 & !AD4 & (!AD3 # !AD2)
# !AD6 & !AD5 & AD4 & (!AD3 & !AD2 # !AD3 & !AD1 & !AD0)
# !AD6 & !AD5 & !AD4 & (AD3 & AD2 # AD3 & AD1 & AD0);
R3 = AD6 & AD5 & AD4
# AD6 & AD5 & !AD4 & (AD3 # AD2 & AD1 # AD2 & AD0)
# AD6 & !AD5 & AD4 & (!AD3)
# AD6 & !AD5 & !AD4 & (!AD3 & !AD2 # !AD3 & !AD1 # AD3 & AD2 &
AD1 & AD0)
# !AD6 & AD5 & AD4 & (!AD3 & AD2 # !AD3 & AD1 # AD2 & AD1 &
AD0)
# !AD6 & AD5 & !AD4 & (AD3 & !AD2 # !AD3 & AD2 & AD1)
# !AD6 & !AD5 & AD4 & (!AD3 & !AD2 # AD3 & AD2 # !AD3 & !AD1 &
!AD0 # AD3 & AD1 & AD0)
# !AD6 & !AD5 & !AD4 & (!AD3 & AD2 & AD1 # AD3 & !AD2 & !AD1 #
AD3 & !AD2 & !AD0);
R2 = AD6 & AD5 & AD4
# AD6 & AD5 & !AD4 & (!AD3 & !AD2 # !AD3 & !AD1 & !AD0 # AD3 &
AD2 & AD1 & AD0)
158
MODULE COMBINATIONAL (cont.)
# AD6 & !AD5 & AD4 & (!AD3 & AD2 # AD2 & AD1 # !AD3 & AD1 &
AD0)
# AD6 & !AD5 & !AD4 & (AD2 & !AD1 # AD3 & AD1 & !AD0 # !AD2 &
AD1 & AD0)
# !AD6 & AD5 & AD4 & (!AD3 & !AD2 & !AD1 # !AD3 & AD2 & AD0 #
AD3 & AD2 & !AD1 # AD2 & AD1 & !AD0 # AD3 & !AD2 & AD1 & AD0)
# !AD6 & AD5 & !AD4 & (!AD3 & AD2 & !AD1 # AD3 & !AD2 & AD1 #
AD3 & !AD2 & AD0 # !AD2 & AD1 & AD0 # AD3 & AD1 & AD0)
# !AD6 & !AD5 & AD4 & (AD3 & AD2 & AD0 # AD3 & !AD2 & !AD1 #
AD3 & AD1 & !AD0 # !AD3 & AD2 & !AD1 & !AD0 # !AD3 & !AD2 & AD1 &
AD0)
# !AD6 & !AD5 & !AD4 & (!AD3 & AD2 & !AD1 # AD3 & AD2 & AD0 #
AD3 & !AD2 & !AD1 # AD3 & AD1 & !AD0 # !AD3 & !AD2 & AD1 & AD0);
R1 = AD6 & AD5 & AD4 & (AD3 # AD2 & AD1)
# AD6 & AD5 & !AD4 & (!AD2 & AD1 # AD2 & !AD1 & !AD0 # AD3 &
AD2 & !AD1 # AD3 & AD2 & !AD0)
# AD6 & !AD5 & AD4 & (!AD3 & AD1 & !AD0 # !AD3 & AD2 & AD1 #
AD3 & AD2 & !AD1 # !AD3 & !AD2 & !AD1 & AD0 # AD3 & !AD2 & AD1 &
AD0)
# AD6 & !AD5 & !AD4 & (!AD1 & AD0 # AD3 & !AD1 # AD2 & !AD1 #
AD3 & AD2 & !AD0 # !AD3 & !AD2 & AD1 & !AD0)
# !AD6 & AD5 & AD4 & (!AD3 & !AD1 & !AD0 # !AD3 & !AD2 & AD0 #
!AD3 & AD2 & AD1 # AD3 & AD1 & !AD0 # AD3 & AD2 & !AD1 & AD0)
# !AD6 & AD5 & !AD4 & (!AD3 & AD2 & !AD1 # !AD3 & AD2 & AD0 #
!AD3 & !AD1 & AD0 # AD2 & !AD1 & AD0 # AD3 & !AD2 & !AD0 # AD3 &
!AD2 & AD1 # AD3 & AD1 & !AD0 # !AD2 & AD1 & !AD0)
# !AD6 & !AD5 & AD4 & (AD2 $ AD1 $ AD0)
# !AD6 & !AD5 & !AD4 & (!AD3 & AD2 & !AD1 # !AD2 & AD1 & !AD0 # AD2 & !AD1
& !AD0 # AD2 & AD1 & AD0);
R0 = AD6 & AD5 & AD4 & (!AD3 & (AD2 $ AD1))
# AD6 & AD5 & !AD4 & (AD3 & !AD1 # !AD1 & !AD0 # !AD2 & !AD1 # !AD3 & AD1 &
AD0 # AD3 & AD2 & !AD0)
# AD6 & !AD5 & AD4 & (!AD2 & AD1 & !AD0 # !AD3 & !AD2 & !AD0 # !AD3 & AD2 &
AD0 # AD2 & !AD1 & AD0)
# AD6 & !AD5 & !AD4 & (AD3 & !AD2 & AD0 # !AD3 & AD2 & AD0 # !AD3 & !AD2 &
AD1 # !AD3 & !AD2 & !AD0 # AD3 & AD2 & AD1 & !AD0)
# !AD6 & AD5 & AD4 & (AD2 & !AD1 & !AD0 # !AD2 & !AD1 & AD0 # AD3 & AD2 &
!AD0 # !AD3 & AD2 & AD1 & AD0 # !AD3 & !AD2 & AD1 & !AD0)
# !AD6 & AD5 & !AD4 & (AD3 & !AD1 & !AD0 # !AD3 & AD1 & !AD0 # AD3 & AD2 &
AD1 # AD3 & !AD2 & AD0 # !AD3 & AD2 & !AD1 & AD0)
# !AD6 & !AD5 & AD4 & (AD1)
# !AD6 & !AD5 & !AD4 & (AD1 & !AD0 # AD3 & AD1 # !AD3 & !AD1 & AD0 # AD3 &
!AD2 & AD0);
END
Fig. A.10.- Sine-wave program coding.
159
Fig. A.11.- Clock generator schematic diagram.
160
Vee4
of
Document Number
Size
IN
Date:
OUT
GND
GND
4
1
1
2
0.1u
Vcc4
GND4
6
+
1
2
7
5
1
2
G3
R3
TP10
10
GND
SW3
1u
HCPL2611
Vcc3
7
5
t2
+
U29
8
0.1u
C22
Vcc4
Vcc3
6
3.9k
1u
HCPL2611
x3
8
U26
GND4
EC70
TP9
3
5
6
7
IN
IN
Vee3
7
8
9
10
11
12
C19
0.1u
Vee4
1
C16
X3
7
8
9
10
11
12
1
4
C13
0.1u
3.9k
U2
LM7805C
2
GND
C20
R8
1
1
2
3
4
5
6
MIC4421
U31
10u
GND4
TP5
t2
1
2
2
R7
MKT
JUMPER
VS
OUT
OUT
2
GND
U30
VS
OUT
LM7805C
1
C14
2
U6b
J7
8
10u
t2
3
5
GND
MIC4421
GND
6
7
8
VS
IN
1
U27
C23
0.1u
0.1u
U28
C24
C21
Title
C17
0.1u
VS
OUT
OUT
1
1
2
2
2
OUT
C18
0.1u
GND
1
C15
G4
G3
MKT
OUT
TP6
Vcc3
TP11
1
U6
Vcc4
Vee3
2
2
1
1
Salida
Sheet
Custom
U4
AC/AC Cuk converter
1
Friday, July 15, 2005
Rev
APPENDIX B.- AC/AC CÚK CONVERTER AND CONTROL SCHEMATICS
J3
HEADER 2
2
1
t2
M4
HEADER 2
2
M3
HFA25TB60 D4
1IRFP460
3
IRFP460
J6
3
1
3
1
1
GND4
3
2
1
2
3
4
5
6
J4
D3
0
R11
JUMPER
R12
1k
1k
HFA25TB60
R4
1
2
G4
1
2
10
TP4
JP7
1
JP8
PWM_3
X2
Vee2
Vcc2
GND
IN
Vcc2
Vcc2
0.1u
7
5
GND2
6
8
1
2
R2
1u
HCPL2611
Vcc1
7
5
C10
U23
+
+
0.1u
GND1
6
5
4
3
2
1
3.9k
1u
HCPL2611
1
C7
C8
0.1u
U20
6
8
3.9k
1
HFA25TB60
G2
10
1
J2
HEADER 2
HEADER 2
R9
1k
R10
1
2
1k
1
2
1
U3
JP5
1
2
IN
3
GND
2
IN1
3
TP2
2
TP1
1
J1
EC70
2
6
5
4
3
2
1
Vcc1
1
2
GND1
1
GND2
12
11
10
9
8
7
D2
IRFP460
1
3
JUMPER
0
U1
12
11
10
9
8
7
J5
M1
C4
GND2
1
HFA25TB60
IRFP460
X1
Vee1
M2
C2
0.1u
Vee2
1
LM7805C
2
GND
GND2
3
TP3
U25
10u
4
1
2
1
R5
R6
D1
MIC4421
OUT
GND
VS
OUT
OUT
IN
IN
VS
OUT
2
U24
3
5
8
6
7
3
5
GND
C11
0.1u
0.1u
U22
LM7805C
GND
GND
C1
10u
C12
C9
1
2
GND
4
TP8
MIC4421
GND1
VS
OUT
OUT
10
SW1
2
R1
TP7
MKT
1
IN
2
U21
VS
8
0.1u
G1
2
C5
0.1u
G2
G1
1
6
7
1
C3
GND1
U5
Vcc1
Vee1
PWM_4
C6
Entrada
PWM_1
JP6
PWM_2
Fig. B.1.- Schematic diagram of a single-phase AC/AC Cuk converter module.
161
Fig. B.2.- Schematic diagram of a control circuit for AC/AC Cuk converter (PWM section).
162
Fig. B.3.- Schematic diagram of a control circuit for AC/AC Cuk converter (Reference output section).
163
Fig. B.4.- Schematic diagram of a control circuit for AC/AC Cuk converter (Feedback section).
164
APPENDIX C.- PRINTED CIRCUIT BOARDS
Fig. C.1.- Top layer of the PCB layout of the SRSG (not at 1:1 scale).
Fig. C.2.- Bottom layer of the PCB layout of the SRSG (not at 1:1 scale).
165
Fig. C.3.- Top layer of the PCB layout of the AC/AC Cúk converter (not at 1:1 scale).
Fig. C.4.- Bottom layer of the PCB layout of the AC/AC Cúk converter (not at 1:1 scale).
166
Fig. C.5.- Top layer of the PCB layout of the control stage (not at 1:1 scale).
Fig. C.6.- Bottom layer of the PCB layout of the control stage (not at 1:1 scale).
167
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