Développement et réalisation d`un circuit de - Euso

LAL 12-412
UNIVERSITE PARIS-SUD
ÉCOLE DOCTORALE : PARTICULES, NOYAUX, COSMOS – ED 517
LABORATOIRE DE L’ACCELERATEUR LINEAIRE
DISCIPLINE : MICROELECTRONIQUE
THÈSE DE DOCTORAT
soutenue le 29/11/2012
par
Salleh AHMAD
Développement et réalisation d'un circuit de
microélectronique pour le détecteur spatial de
rayons cosmiques JEM-EUSO
Composition du jury :
Directeur de thèse :
Christophe DE LA TAILLE
- Ingénieur de Recherche au CNRS
Co-directrice de thèse :
Sylvie DAGORET-CAMPAGNE
- Chargée de Recherche au CNRS
Rapporteurs :
Marco CASOLINO
- Chercheur au RIKEN (Japon)
Marc WINTER
- Directeur de Recherche au CNRS
Achille STOCCHI
- Professeur de l’Université Paris-Sud
Philippe GORODETZKY
- Directeur de Recherche au CNRS
Examinateur :
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Résumé
Extreme Universe Space Observatory on Japanese Experiment Module (JEM-EUSO) est conçu comme
l’expérience de rayons cosmiques de prochaine génération pour observer les particules hautement
énergétiques au dessus de 1020 eV. Le projet est mené par RIKEN et soutenu par une collaboration
de plus de 200 membres provenant de 13 pays. Cet observatoire, sous la forme d'un télescope
fluorescent, sera arrimé à la Station Spatiale internationale (ISS) pour un lancement prévu en 2017.
En observant les gerbes atmosphériques produites dans la troposphère, à une altitude de 400 km,
cet observatoire de rayons cosmique offrira une grande surface de détection, qui est au moins 100
fois supérieur que le plus grand détecteur de rayons cosmiques jamais construit.
La surface focale de JEM-EUSO sera équipée d'environ 5000 unités de photomultiplicateur
multianode 8x8 pixels (MAPMT). Un circuit intégré (ASIC), connu sous le nom SPACIROC, a été
proposé pour la lecture du MAPMT. Cet ASIC de 64 voies propose des fonctionnalités comme le
comptage de photons, la mesure des charges et le transfert de données à haute vitesse. Par-dessus
tout, cet ASIC doit peu consommé afin de respecter la contrainte de puissance de JEM-EUSO.
Réalisé en utilisant la technologie AMS Silicium-Germanium (SiGe) 0,35 µm, cet ASIC intègre 64
canaux de comptage de photons rapides (Photon Counting). La résolution de temps pour le
comptage de photons est de 30 ns, ce qui permettra d’atteindre la valeur maximale comptage qui est
de l'ordre de 107 photons / s. Le système de mesure de charge est basé sur le Time-Over-Threshold
qui offre 8 canaux de mesure. Chaque canal de mesure est une somme des 8 pixels du MAPMT et il
est prévu que ce système est capable de mesurer jusqu'à 200 pC. La partie numérique fonctionne en
continu et gère la conversion des données de chaque voie des blocs de Photon Counting et TimeOver-Threshold. Les données numériques sont transmises par l'intermédiaire de liaisons parallèles
dédiées et ces opérations sont effectuées pendant une fenêtre de communication ou « Gate Time
Unit » (GTU) de fréquence 400 kHz. Le taux de transfert des données d’ASIC avoisine les 200 Mbps
ou 576 bits / GTU. La dissipation de puissance est strictement inférieure à 1 mW par canal ou 64 mW
pour l'ASIC.
Le premier prototype de SPACIROC a été envoyé pour fabrication en Mars 2010 au Centre Multi
Projet (CMP). Des puces nues et packagés ont été reçues en Octobre 2010, ce qui a débuté la phase
de caractérisation de cet ASIC. Après une phase de test réussie, des puces SPACIROC ont été intégrés
dans l'électronique frontale d'un instrument pour détecter les sursauts gamma - Ultra Fast Flash
Observatoire (UFFO) qui va être lancé en 2013. Vers la fin de l'année 2012, des cartes électroniques
frontales conçues autour des puces SPACIROC ont été fabriqués pour le projet EUSO-Balloon. Ce
projet de vol en ballon stratosphérique à une altitude de 40 km servira comme le démonstrateur
technologique et l'ingénierie d'un instrument miniaturisé JEM-EUSO.
La deuxième génération de cet ASIC a été envoyée à la fonderie en Décembre 2011. Ce second
prototype, SPACIROC2, a été testé à partir de mai 2012. Les principales améliorations sont les
suivantes: la consommation d'énergie a été revue à la baisse, ainsi que l'amélioration de la résolution
temporelle de Photon Counting et l'extension de la gamme dynamique pour le module Time-OverThreshold. Les mesures en cours ont montré que SPACIROC2 présente un bon comportement général
et apporte des améliorations par rapport à son prédécesseur.
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Abstract
Extreme Universe Space Observatory on Japanese Experiment Module (JEM-EUSO) is conceived as
the next generation cosmic rays experiment for observing the highly energetic particles above 5.1019
eV. The project is lead by RIKEN and supported by an active collaboration of more than 200 members
from 13 countries. This observatory, in the shape of a wide field-of-view UV telescope, will be
attached to the International Space Station (ISS) for a planned launch in 2017. Observing the Air
Showers generated in troposphere from an altitude of 400 km, this space based cosmic rays
experiment will offer a very large instantaneous detection surface, which is at least 100 times bigger
than the largest land based cosmic rays observatory.
The detection surface of JEM-EUSO will be equipped with around 5000 units of 8x8 pixels Multianode
Photomultiplier (MAPMT). A radiation hardened mixed signal application-specific integrated circuit
(ASIC), known as SPACIROC, has been proposed for reading out the MAPMT. This ASIC features 64channel analog inputs, fast photon counting capabilities, charge measurements and high-speed data
transfer. Above all, the power dissipation of this ASIC is required to be very low in order to comply
with the strict power budget of JEM-EUSO.
By taking the advantages of high speed AMS 0.35 µm Silicon-Germanium (SiGe) process, this ASIC
integrates 64 fast Photon Counting channels. The photon counting time resolution is 30 ns, which
allows the theoretical counting rate in the order of 107 photons/s. The charge measurement system
is based on Time-Over-Threshold which offers 8 measurement channels. Each measurement channel
is composed of 8 pixels of the MAPMT and it is expected that this system will measure up to 200 pC.
The digital part is then required to operate continuously and handles data conversion of each Photon
Counting and Time-Over-Threshold channel. For the first version of this ASIC, one channel
measurement channel for the dynode is also available. The digital data are transmitted via dedicated
parallel communication links and within the defined Gate Time Unit (GTU) of 400 kHz frequency. The
ASIC data output rate is in the vicinity of 200 Mbps or 576 bits/GTU. The power dissipation is kept
strictly below 1 mW per channel or 64 mW for the ASIC.
The first prototype of SPACIROC was sent for tapeout in March 2010 through Centre Multi Projet
(CMP) prototyping services. The packaged ASICs and bare dies have been received in October 2010
which marked the characterization phase of this chip. After successful testing phase, SPACIROC chips
were integrated into the front-end electronics of an instrument pathfinder for detecting the gamma
ray bursts – Ultra Fast Flash Observatory (UFFO) which is foreseen to be launched in 2013. Towards
the end of 2012, front-end board designed around SPACIROC chips have been fabricated for the
EUSO-Balloon project. This balloon borne project will serve as a technical and engineering
demonstrator of a fully miniaturized JEM-EUSO instrument which will be flown to the stratosphere at
the altitude of 40 km.
The second tapeout of this ASIC was done in December 2011. This second prototype, SPACIROC2,
was tested from May 2012. The main improvements are as follows: lower power consumption due
to better power management, enhancement in Photon Counting time resolution and extension the
Time-Over-Threshold maximum input rate. The ongoing tests have shown that SPACIROC2 exhibits a
good overall behavior and improvement compared to its predecessor.
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5
Contents
Résumé.................................................................................................................................................... 3
Abstract ................................................................................................................................................... 4
Contents .................................................................................................................................................. 6
Introduction ............................................................................................................................................ 9
Chapter 1 High Energy Cosmic Rays ..................................................................................................... 10
1.1 Introduction & History of cosmic rays ......................................................................................... 10
1.2 High Energy Cosmic Ray sources and propagation ..................................................................... 10
1.2.1 Sources categories................................................................................................................ 10
1.2.2 Propagation .......................................................................................................................... 14
1.2.3 Energy spectrum on earth .................................................................................................... 17
1.3 Air Showers.................................................................................................................................. 18
1.4 Air Showers detection and observation ...................................................................................... 22
1.4.1 Ground detection ................................................................................................................. 22
1.4.2 Imaging by fluorescence detection ...................................................................................... 24
1.4.3 Hybrid and stereo detection ................................................................................................ 26
1.4.4 Imaging from space .............................................................................................................. 28
Chapter 2 JEM-EUSO Instrument ......................................................................................................... 31
2.1 Instrument components .............................................................................................................. 35
2.2 Optics ........................................................................................................................................... 36
2.3 Focal Surface ............................................................................................................................... 37
2.3.1 MAPMT ................................................................................................................................. 39
2.3.2 Electronics ............................................................................................................................ 43
2.4 Trigger.......................................................................................................................................... 45
2.5 Planning and deployment ........................................................................................................... 46
2.6 Design considerations for the MAPMT readout ASIC ................................................................. 48
Chapter 3 Front-end ASIC ..................................................................................................................... 50
3.1 Introduction ................................................................................................................................. 50
3.2 General Architecture ................................................................................................................... 52
3.3 Pre-amplifier design .................................................................................................................... 53
3.3.1 Current conveyor, Gain correction and Signal Distribution ................................................. 54
3.4 Photon Counting.......................................................................................................................... 80
3.4.1 Photon Counting – Pre-amplifier Trigger (Trig_PA).............................................................. 81
6
3.4.2 Photon Counting – FSU Trigger (Trig_FSU) ........................................................................... 85
3.4.3 Photon Counting – VFS Trigger (Trig_VFS) ........................................................................... 99
3.4.4 Conclusion .......................................................................................................................... 106
3.5 Time-Over-Threshold ................................................................................................................ 107
3.5.1 General Architecture .......................................................................................................... 107
3.5.2 KI operations ...................................................................................................................... 109
3.5.3 Simulations ......................................................................................................................... 110
3.5.4 Conclusion .......................................................................................................................... 114
3.6 DAC ............................................................................................................................................ 115
3.7 Digital......................................................................................................................................... 116
3.7.1 General Description ............................................................................................................ 116
3.7.2 Timing diagram ................................................................................................................... 118
3.7.3 Simulations ......................................................................................................................... 121
3.7.4 Data Readout and connection to the FPGA ....................................................................... 122
3.8 Radiation tolerance and Single Events mitigations ................................................................... 123
3.8.1 Cumulative Effect to CMOS and Bipolar transistors........................................................... 124
3.8.2 Single Event Effect and mitigations .................................................................................... 129
Chapter 4 ASIC Characterization ........................................................................................................ 135
4.1 Test board.................................................................................................................................. 135
4.2 LabVIEW Software ..................................................................................................................... 137
4.3 ASIC Measurements .................................................................................................................. 143
4.3.1 DC level measurements ...................................................................................................... 145
4.3.2 Noise measurement ........................................................................................................... 147
4.3.3 DAC measurement ............................................................................................................. 156
4.3.4 Double Pulse Resolution..................................................................................................... 157
4.3.5 Trigger S-curves .................................................................................................................. 159
4.3.6 Photon Counting Gain Measurement ................................................................................ 163
4.3.7 Time-Over-Threshold Measurement .................................................................................. 167
4.3.8 MAPMT Measurements ..................................................................................................... 171
4.4 Conclusion ................................................................................................................................. 180
Chapter 5 JEM-EUSO Calibration ........................................................................................................ 181
5.1 MAPMT absolute gain measurements ...................................................................................... 181
5.2 MAPMT efficiency measurements ............................................................................................ 186
5.3 MAPMT sorting.......................................................................................................................... 190
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Chapter 6 Front-end board prototype for JEM-EUSO........................................................................ 191
6.1 Mechanical requirements and preliminary front-end board studies........................................ 192
6.2 UFFO pathfinder ........................................................................................................................ 195
6.2.1 Introduction ........................................................................................................................ 195
6.2.2 UBAT Analog Board ............................................................................................................ 198
6.3 EUSO-Balloon............................................................................................................................. 211
6.3.1 Front-end electronics design .............................................................................................. 212
Chapter 7 SPACIROC2 ......................................................................................................................... 221
7.1 Introduction ............................................................................................................................... 221
7.2 Photon Counting........................................................................................................................ 221
7.2.1 Pre-amplifier Trigger (Trig_PA) simulations ....................................................................... 222
7.2.2 VFS Trigger (Trig_VFS) discriminator design....................................................................... 225
7.3 KI Time-Over-Threshold ............................................................................................................ 227
7.3.1 Reset implementation ........................................................................................................ 228
7.3.2 Input dynamic range extension .......................................................................................... 229
7.4 Power management and data transmission ............................................................................. 230
7.5 Measurement Results ............................................................................................................... 233
7.5.1 Noise ................................................................................................................................... 233
7.5.2 Photon Counting................................................................................................................. 233
7.5.3 Time-Over-Threshold ......................................................................................................... 239
7.6 Conclusion ................................................................................................................................. 241
Conclusion ........................................................................................................................................... 242
Perspectives ........................................................................................................................................ 243
References........................................................................................................................................... 245
Acknowledgements ............................................................................................................................ 250
List of acronyms .................................................................................................................................. 251
8
Introduction
The discovery of cosmic rays has been always filled with great adventures. Since the last century
pioneering scientists have flown in hot air balloon, climbed mountains and even gone to remote
areas in the quest of studying the particles of extraterrestrial origin. Now, in the beginning of the 21 st
century, an active community of scientists and engineers is striving to build a space borne
observatory which will scrutinize the ultra high energy cosmic rays (UHECRs). This highly ambitious
project, known as Extreme Universe Space Observatory on Japanese Experiment Module or JEMEUSO, represents a big leap in cosmic rays research as it could provide unprecedented statistics for
the UHECRs, surpassing the capacity of the biggest ground based observatory ever built. JEM-EUSO
will enlighten us on the origin and the composition of the cosmic rays in the energy region of over
1019 eV. Understanding the highly energetic cosmic rays could even open up new physics which is not
yet accessible by the ground based accelerator.
The first part of this document is dedicated to the UHECRs and the JEM-EUSO instrument. Several
aspects of the UHECRs and the observation techniques are discussed in Chapter 1. JEM-EUSO as a
space based fluorescence telescope is described in Chapter 2. This chapter enumerates the essential
components of JEM-EUSO telescope such as the optical design, the photo detection surface based on
Multi Anode Photomultiplier (MAPMT) and the electronics. Towards the end of this chapter, the
requirements of the MAPMT readout electronics in form of integrated circuit or ASIC are highlighted.
Chapter 3 covers the main work of this thesis which is the design of the readout ASIC, SPACIROC.
Starting from the requirements, this chapter encompasses the general architecture, analytical and
numerical analysis and functional simulations of the design. The extensive tests and characterization
of the first ASIC prototype are shown in detail in the fourth chapter of this work.
Chapter 5 concerns the MAPMT calibration strategy for JEM-EUSO. The purpose of this chapter is to
highlight the usage of SPACIROC for the calibration on the ground and also during the JEM-EUSO
operations in space. In Chapter 6, the different studies and development of the front-end board for
JEM-EUSO detector surface are presented. The design considerations and current status of the frontend board are discussed in this chapter.
The closing chapter (Chapter 7) describes the second ASIC prototype which was designed according
to the feedbacks from the characterization tests and front-end integration. The major modifications
in the design of this ASIC are presented in this chapter. The preliminary measurement results of the
ASIC are also shown towards the end of this chapter.
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Chapter 1 High Energy Cosmic Rays
1.1 Introduction & History of cosmic rays
The term cosmic rays is used to designate the charged particles of extra-terrestrial origin. Initially, the
term referring particles of extra-terrestrial origin was “Cosmic radiation”, which coincides with the
cosmic rays discovery by Victor Hess [1]. Between 1911 and 1913, Hess flew several balloons up to 5
km of altitude and he noted that the level of ionization first decreased up to the altitude of 1 km
before increasing significantly in higher altitude. His discovery led to the assumption that the ionizing
particles at higher altitude are not only coming from the Earth’s radioactive decays but mostly from
outer space. This discovery was later confirmed by Werner Kolhörster who ascended in balloon to an
altitude of 9km. The term “cosmic rays” was really coined by Robert Milikan in 1920’s as he was
trying to prove that the primary cosmic rays source were photons. However, the primary source of
the cosmic rays was later proven to be charged particles by Walther Bothe and Werner Kolhörster.
In 1938, Pierre Auger observed the phenomena known as “Extensive Air Shower (EAS)” from his
correlated detectors in the Alps. He concluded that the particles which were flagged simultaneously
by his two detectors were in fact the secondary particles generated by the collisions of a single
primary source in the atmosphere. From his measurements, the estimated energy of the primary
cosmic ray was in the region of 1015 eV. Eventually this discovery paved the way towards the ultra
high energy cosmic ray (UHECR) observations.
Since the discovery of the EAS by Pierre Auger [2], several more experiments have been carried for
studying the cosmic rays. Even after all these years, the exact nature of the cosmic rays at the highest
energy is still not obvious. Questions such as the exact composition of high energy cosmic rays or its
origin are still left unanswered despite of the technological leap steadily achieved in the particle
detection. It is widely admitted that the biggest hurdle to understand the origin of those high energy
particles is the lack of significant events and statistics. To overcome this experimental barrier and to
answer the questions regarding the UHECRs, JEM-EUSO [3] (Extreme Universe Space Observatory on
Japanese Experiment Module) project is proposed. This highly ambitious project, which would
observe the EAS from the space for the first time, will enhance our comprehension of the UHECRs to
an unprecedented level.
1.2 High Energy Cosmic Ray sources and propagation
1.2.1 Sources categories
The real origin of the UHECRs is still very poorly understood. For the following, the term UHECR
refers to the cosmic rays of energy greater than 1018 eV. To explain the achievement of such energy
level, two models have been developed: bottom-up and top-down scenarios. The first model is based
on the astrophysical sites in the universe which might have the capabilities to accelerate a particle up
to the energy of around 1021 eV. Meanwhile the top-down concept consists of presuming the super
heavy relic particles in the early universe would decay into the UHECRs. This model requires the
physics which are beyond the energy range covered by standard model.
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1.2.1.1 Bottom-up / Top-down
In top-down scenario, the energy range of the UHECRs is obtained naturally without involving the
particle acceleration. In order to decay into the UHECRs, the relic particles must possess a mass (mXc²)
superior than 1020 eV. These particles (also known as X particles) would decay first to quarks and
leptons. The hadronization of the quarks would produce mostly the pions and few baryons or
nucleons. The produced pions will in turn decay to photons, (anti-)neutrinos and electrons (and
positrons). These particles would form the UHECRs we know today and their energy range would be
around mXc² without any acceleration mechanism. However, as these particles are originated from
relic particles, the following conditions have to be respected in order to detect them on the present
day:



The X particles must be massive enough: mXc² >> 1020 eV.
The decay of the X particles should happen recently in the cosmological timeline or at an
equivalent distance of less than 100 Mpc from the Earth.
The flux of the X particles decay must be large enough to be detectable as UHECRs.
Furthermore not many sources of X particles are known to be able to satisfy the above conditions.
For the time being, there are two cases which are often quoted to be the sources of these X particles.
The first one is the cosmological topological defects [4] where the instability of the defects could
generate among others the super heavy X particles. It could be emitted by the superconducting
strings when it reaches the critical value or the intersections of the ordinary strings. Magnetic
monopoles, ordinary strings and superconducting strings are usually cited as topological defects
which are likely to produce the super heavy particles capable of decaying to UHECRs.
The second case of the top-down scenario is the cosmological relic particles [5] from the early
universe which are independent from the topological defects. This supermassive quasi-stable X
particles would decay to UHECRs and must have a lifetime comparable with Hubble time. These
particles could be a part of the superheavy dark matter and are normally accumulated in the galactic
halo. The signatures of these particles are the dominance of the ultra high energy photons and its
anisotropy.
However in recent results from Pierre Auger Observatory on the high energy neutrinos [6] [7]
indicate that the fraction of the photons is decreasing which is in contradiction with the top-down
signature hypothesis. This gives an indication that most probably the contribution of UHECRs from
top-down scenario is not dominant.
For the bottom-up scenario, it is most likely to occur via the shock wave acceleration. This shock
acceleration known as Fermi mechanism [8] will be described in Section 1.2.1.2. In this mechanism,
the accelerated particles are supposed to gradually gain the energy due to repetitive elastic
reflection with moving magnetic field or magnetic mirror. The acceleration due to Fermi mechanism
is supposed to be related with astrophysical objects such as supernovae (SN) remnants and active
galactic nuclei (AGNs). The Fermi mechanism is usually favored as an explanation of the UHECR
sources as it could naturally build up to power laws usually observed for the cosmic rays energy
spectrum. Another type of mechanism contributing to the bottom-up scenario is the direct
acceleration within a strong electromagnetic field. Rotating neutron stars with huge magnetic field
(~1012 G) are most likely the candidate for the direct acceleration mechanism.
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1.2.1.2 Acceleration mechanics
The original Fermi mechanism was first presented in 1949 and it was proposed that charged particles
would either gain or loss energy by the reflections from the magnetic mirrors associated to the
interstellar medium. These mirrors have a random velocity, V, which could lead to an average energy
gain proportional to 〈 〉
( ) with
. This mechanism is known as the second order
Fermi mechanism. However, there are several issues regarding this model. First, the number of the
accelerated particles would be very low as a result of particle scattering in the interstellar medium
(~0.1 pc) and the small velocity of the clouds compared to light velocity ( ). This mechanism also
suffers from the ionization loss and need particles which posses the energy superior the maximum
energy loss rate. Finally, there is no reason from this mechanism which explains the power law of 2
observed on the cosmic rays energy spectrum.
The Fermi acceleration in strong shock waves, which is also known as diffusive shock acceleration,
was proposed in the 1970s as an improvement to the original version. It this case the shock waves,
the collision between the particles and the medium is only head-on type which will only increase the
particles energy. Therefore the average energy gain in this case is much higher and it is to the order
of 〈 〉
with
. Naturally this mechanism is called the first order Fermi mechanism.
The most important outcome from this mechanism is of course the power law natural derivation of
the energy spectrum of
. Although the obtained spectrum is the power of 2 instead of
the observed 3, this mechanism is still plausible as its spectral index is unique and independent of the
surrounding environment. Furthermore there are known astrophysical objects which could produce
the shock waves in a wide energy range from TeV to ZeV such as supernova remnants and active
galactic nuclei.
1.2.1.3 Source containment with magnetic field
For the cosmic rays with energy up to E~1018 eV, it is most likely that the possible acceleration sites
are situated within our galaxy. However, extragalactic candidates should also be verified when
dealing with cosmic rays with energy range of E ~1019 – 1020 eV. For this purpose Hillas [9] in 1984 has
represented different astrophysical sites which are capable to accelerate the particles to the highest
energy. Hillas argued that the Larmor radius of the accelerated particles must not exceed the size of
the accelerator making that the confinement of the particles with energy up to 1020 eV could be from
extragalactic sources. The maximum energy of an accelerated particle is given by the following
equation:
Where Ze is the electrical charge of the particle, B and L are the magnetic field and size of the
accelerator.
Figure 1.1 shows the plot from this relation, which represents the potential acceleration sites
according to their magnetic fields and size. The upper right part of the red dotted line in Figure 1.1
indicates that protons could be accelerated up to 1020 eV. Above the solid red line in the same figure,
protons could be accelerated up to 1021 eV. By investigating the acceleration source candidate for
such magnetic confinement, the following sites are presumed to be capable of producing protons of
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energy above 1020 eV : high magnetic field neutron stars, active galactic nuclei, radio galaxies lobes
and the shocks of galactic medium. For the iron nuclei represented by the solid green line (shifted by
a factor of
in B or L) in Figure 1.1, additional sites are potentially capable of accelerating to
20
the energy of 10 eV. These sites include the galactic halo and white dwarfs.
Figure 1.1 : Hillas [9] plot representing various astrophysical sites capable of producing UHECRs. The
sites below the diagonal lines are not capable of accelerating particles over the indicated energy.
Objects over the solid red line can accelerate protons upto 1021 eV. Over the dashed red line, the
objects are capable to accelerate protons up to 1020 eV. The solid green line delimitates the objects
capable of accelerating iron nuclei to the maximum energy of 1020 eV.
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1.2.2 Propagation
Before the cosmic rays could be detected, it will have to propagate [10] [11] through the interstellar
medium. Along the way, the charged particles could interact with the Cosmic Wave Background
(CMB) [12] and be deflected by the cosmic magnetic fields [13]. The interactions on the CMB would
alter the composition of the particles and induce the energy loss as explained in Sections 1.2.2.1. On
the other hand, the interaction of a particle with the cosmic magnetic field shall deviate its trajectory.
The angular deflection, in degrees, of the charged particle passing by is given by the following
relation:
With S the distance traveled by the particle through the magnetic field and RL the Larmor radius of
the particle.
The Larmor radius of a given particle depends on its energy, E, its charge Ze and of course the
concerned galactic and extra-galactic magnetic field, B :
In general, the angular deflection of the particles will depend largely on their energy. This case is
usually favorable for the UHECRs which exhibit high energy (>1019 eV) and low electrical charge. The
resulting angular deflections are usually small enough for not disturbing the determination of the
particles arrival direction. Typically, a proton with 5.1019 eV of energy would be deflected only a few
degrees provided the magnetic field do not exceed 2 µG1 in the galaxy or nG in extra-galactic medium.
1.2.2.1 Interaction of cosmic rays on CMB
The CMB is universal and isotropic. The density of CMB photons in the space is around 400 photons
cm-3. This makes that it would likely interfere with the propagating cosmic rays. Shortly after the
discovery of the CMB in 1960s, GZK cutoff was predicted simultaneously by Kenneth Greisen, Georgiy
Zatsepin and Vadim Kuzmin [14] [15] . They predicted that the interactions of UHECRs with the CMB
which produces the pions would introduce a cutoff in the spectrum for energies above than 5.1019 eV.
This cutoff indicates that particles from far distances are strongly suppressed and only the nearest
ones can be detected. Moreover the observed energy range will be lower than the emission value.
The cosmic rays energy losses due to the interactions with the CMB are mainly caused by the
following mechanisms: the photo-pion production and the pair production. The expanding universe
redshift would also contribute slightly to the cosmic rays energy losses as the CMB energy density is
shifted to the higher range.
1
19
In an average galactic magnetic field of 2 µG, the Larmor radius of 5.10 eV proton is around 25 kpc. For
instance this radius is slightly bigger than the radius of Milky Way (~20 kpc) thus the particle deflection should
be very small [70]. Otherwise if the average galactic field is too important, the particles could be diffused
(naturally it will depend on the energy of the particles).
14
The interaction between the proton and the photon of the CMB (
) would generate the pions :
The energy threshold for the photo-pion productions is situated around 1020 eV. These interactions
are dominant for very high energy cosmic rays and it would limit the propagation of the particles to
the radius of ~100 Mpc. This characteristic is called the GZK cutoff which is visible on the energy
spectrum of the cosmic rays.
At lower energy, starting from ~1015 eV, the interactions between the proton and the CMB photon
would produce electron-positron pairs:
As the portion of the energy losses here are smaller, the attenuation length is larger for this energy
range interaction. Therefore the universe is more transparent for protons with energy lower than
1020 eV.
For the heavy nuclei (of mass A), the interaction with CMB would result in the photo-disintegration of
the CMB’s photons. The involved process is the following:
Where N is a nucleon (proton or neutron)
The energy threshold to reach the photo-disintegration is around 3.1019 eV and 8.1019 eV for He and
Fe nuclei respectively. The mass of nuclei would be reduced continuously throughout its propagation.
At the energy of 1020 eV, the propagation of the Fe nuclei would last up to 500 Mpc.
Lastly for the photons of energy above 4.1014 eV, the interaction with the CMB would create an
electron-positron pair :
Depending on the galactic magnetic fields strength, the electron and positron could lose energy
through synchrotron radiation or via inverse Compton scattering. In any case, for energy above 2.1019
eV, the interaction with CMB is dominant and it will decrease the attenuation length of the cosmic
ray photons.
The plots shown in Figure 1.2 illustrate the energy degradation of the ultra high energy proton due to
the interactions with the cosmic wave background.
15
Figure 1.2 : Left : Average energy of protons as a function of the propagation distance in the CMB
[16]. Right: Attenuation lengths of cosmic rays in various backgrounds (IR, CMB and radio). Three
lowest curves correspond to photons propagation in IR, CMB and radio backgrounds. Two solid plots
in the upper right corner correspond to protons propagation in the CMB (photo-pion production and
pair production). The dashed plot is for the attenuation of iron nuclei in CMB and IR. Plots adapted
from [17] and [18].
16
1.2.3 Energy spectrum on earth
The energy spectrum [19] of the cosmic rays is shown in Figure 1.3. For the energy below the GeV
region the particles are related to the solar activities. However, over this region, the cosmic rays
energy spectrum follows the power law
. The exponent, , or the spectral index for the cosmic
20
rays is nearly constant at 2.7 up to 10 eV.
Figure 1.3 : Compilation of the cosmic rays energy measurements [19]. The spectral features of the
cosmic rays are compared to E-3 power law (dotted green line).
At higher energies, the spectrum of the cosmic rays exhibits several features:



The cosmic ray knee where the spectral index changed from 2.7 to 3.1 can be observed. The
change occurs around the energy range of 5.1015 eV. This feature is considered as a possible
change of the acceleration mechanism. It is most likely that the spectrum steepens due to
the composition change in nuclei atomic number. It is thought that the particles below this
energy range are accelerated by galactic astrophysical objects such as the supernova
remnants. A second knee can also be observed at around the energy range of 4-8.1017 eV.
The cosmic ray ankle could be spotted around 5.1018 eV. Starting from this point, the cosmic
rays are considered to be emitted from extragalactic sources.
The GZK cutoff starting from 5.1019 eV of energy. This feature is due to the interaction of the
charged particles with the CMB.
17
Figure 1.4 : Compilation of the cosmic rays energy measurements higher than 1018 eV. The results
from Pierre Auger Observatory, HiRes and Telescope Array seem to be confirming the existence of
GZK cutoff around 1019 eV region. From [20].
1.3 Air Showers
In the atmosphere, the arrival cosmic rays interact mainly with the nuclei of the nitrogen (or oxygen)
atoms. These interactions generate secondary particles. Depending on the energy and the cross
section of the interaction, the secondary particles in turn interact with the atoms in the atmosphere.
This process will generate a cascade of particles. The phenomenon is known as the Extensive Air
Shower (EAS). A simple illustration of EAS is shown in Figure 1.5.
18
Figure 1.5 : EAS components resulting from the interaction of a cosmic ray nucleon and air nucleus.
The resulting particles cascade is divided into three parts: nucleonic cascade of the primary source,
pionic cascade and electromagnetic cascade.
The composition of the air shower depends on type of the arriving primary cosmic rays. In case of the
photon as primary, the resulting cascade will be mostly electromagnetic. On the other hand, the
nucleon primaries would generate a hadronic and an electromagnetic components.
The first interaction of the nucleon primaries with the air nuclei will create pions (
), kaons ( )
and secondary nucleons (p, n). It is important to note that a majority of the generated particles are
pions along with on average nearly half of the energy transferred. Naturally the secondary charged
particles may interact again: the secondary nucleons would produce the same particles as the first
interactions (thus a majority of pions) and the secondary charged pions would decay or re-interact to
generate other hadronic cascades.
The majority (nearly 2/3) of the secondary pions is the charged ones which could re-interact or decay
into muons or muon neutrinos (
). The neutral pions decay nearly instantaneously in
to gamma rays (
electron-positron (
). At this point, a photon with an initial energy of E0 will produce
) pairs. Each part of the
pair will inherit roughly half of the E0. Consequently
19
each of the
pair could produce additional photon of energy E0/4 via bremsstrahlung radiation.
Thus the continuous process of generating
pairs and photons gives birth to the electromagnetic
cascade of the EAS. The process will stop when the average energy of the generated particles reaches
the critical energy, Ec, where the radiation losses equal the ionization losses. Typically the value of Ec
is around 80 MeV in the air.
One of the visual characteristics of the EAS, is the very weak fluorescence light emission during its
development in the atmosphere. The UV light of 300 - 450 nm wavelength is radiated by the excited
nitrogen molecules due to its internal energy transition provoked by low energy electrons. The
emission of the UV light is isotropic where its intensity is proportional to the energy of the particles
generated during the shower. This characteristic is also convenient for the UHECRs detections as the
ratio of the emitted UV light to the total deposited energy is less than 1%. Therefore, the deposited
energy has to be large enough (>1017 eV) in order to obtain sufficient amount UV photons for the
detection and shower profile reconstruction purpose.
Additionally Cherenkov emissions [21] occur during an EAS development. The direction of the
Cherenkov light forward emission depends on the arrival angle of the charged particles. This angle is
usually quite small and in the case where the EAS path is pointing directly to the UV detector, the
Cherenkov light will outshine the original fluorescence trail. The Cherenkov light is scattered by
ground, clouds and mixed up with the fluorescence photons. Consequently, the Cherenkov emissions
need to be taken into account in the air shower profile reconstruction procedure.
Typically an EAS development can be described by two parameters: the slant depth of the shower
maximum and the number of electrons. For the electromagnetic cascades, the number of particles
and the depth of the maximum can be calculated using Heitler’s toy model [22] of the cascade
development. In this model, the cascade consists of 2 particles with half of the initial energy after
each interaction length X0 (equals to 37 g.cm-2 in the air). Therefore the maximum number (Nmax) of
the generated particle can be deducted from the initial energy, E0 and critical energy Ec where the
cascade stops:
The maximum depth of the shower development is proportional to the logarithm of the initial and
critical energy ratio ( ).
(
)
The quantitative assessment of hadronic showers also can be done by using the Heitler’s model.
However for the ease of estimation, it is only assumed that only first generation of neutral pions
which produced the electromagnetic components of the hadronic showers. The estimation of the
total electron (Nemax) at maximum shower development is given by the following:
20
In this estimation, Eel represent the fraction of the initial energy, E0, taken by the electromagnetic
cascade. For example at 1020 eV, it is believed that Eel = 0.9E0. For the Xmax, the estimation is the
following:
(
)
Where m is the multiplicity of the first interaction and X1 is the depth of the first hadronic interaction.
For interaction with heavy nuclei, the superposition principle can be used. The shower initiated by a
nucleus of mass A with initial energy of E0 can be assumed as equals to A showers generated by
nucleons of E0/A energy. The number of electron and the maximum depth of shower development
for a nucleus are given by the following relationships:
Where p denotes the index corresponding to proton primaries and A the index for nuclei of atomic
number A.
The number of muons generated by a hadronic shower can also be estimated. The following
expressions are for proton and nucleus primaries:
(
)
Where A and p denotes the variable corresponding respectively to nucleus and proton primaries and
[23].
For the shower reconstruction analysis, the Gaisser-Hillas formula is widely used to develop the
longitudinal profile of a hadronic shower. This formula depends on the first interaction, X1, the
maximum depth, Xmax, and number of electrons, Nmax and the hadronic interaction length, λ as
shown below:
(
)
Another formulation for the shower longitudinal profile can be used. It is known as Greisen-IlinaLinsley (GIL) formula which is used essentially for pure electromagnetic shower. The formula is
shown below:
with
,
and
( ( )
).
Depending on the reconstruction software, certain formulation of the shower longitudinal profile
could be preferred to the other.
21
1.4 Air Showers detection and observation
To detect the Air Showers generated by the high energy cosmic rays, there are at least 3 different
techniques to proceed. The first method is called ground detection. This detection method is
sensitive to the Air Shower components which reach the ground such as muons, electrons, positrons
and photons. The next detection technique is done by observing the fluorescence photons generated
by the EAS. Typically this type of detection is done at night by using photon sensitive device such as
Photo Multiplier Tubes (PMTs). The last detection method is called hybrid detection where it
combines both ground and fluorescent detection techniques. This method is popular with the recent
cosmic rays experiment. Another way to observe the Air Showers is by detecting its radio signals. This
detection method is still in research and development stage.
1.4.1 Ground detection
Ground based detection is usually done by positioning an array of detectors in a certain pattern over
a given area. Typically the area required for spreading the detector grid is in order of hundreds or
thousands km² for detecting the UHECRs. Of course the required area and the detector pitch depend
on the expected flux of the energy range of interest. This detection technique is very common as it is
employed by some of the biggest cosmic rays experiments (AGASA [24], Pierre Auger Observatory
[25], Telescope Array [26],..). These detectors are usually sensitive to the hadronics components of
an Air Shower. Typically, scintillation counters (sensitive to ) or Cherenkov water tanks (sensitive
to , and ) are used for the particle detection. Figure 1.6 illustrates the Cherenkov detector used
in Pierre Auger Observatory.
Figure 1.6 : Pierre Auger Observatory Surface Detector based on water Cherenkov detector.
An EAS event can be triggered if at least three detectors were hit within the same short time interval.
This timing depends on the size of the detector array and the required zenith angle of the shower
22
arrival direction. The reconstruction method starts with the determination of the location of air
shower core. Basically the time delay between the hit detectors would indicate the angle and
direction of the shower by triangulation.
The particle density or signal density with respect to the shower axis exhibits a typical lateral shower
profile which has the following expression given by Nishimura, Kamata and Greisen [27] [28]:
(
Where s the shower age,
)
(
)
is the Molière radius,
is the total number of electrons and
gamma function.
is the
By fitting this lateral density profile, one could determine position of the shower core. An estimator is
then used to determine the energy of the primary. The estimator is basically the profile of the
shower front development at a given distance from the shower core. Usually the estimator is chosen
so that it would be independent (small sensitivity to shower fluctuations) of the lateral density fit
shape and also to have the least uncertainties. Figure 1.7 shows the estimator used for Pierre Auger
Observatory Surface Detector. The estimator is chosen at 1000 m from the shower core.
Figure 1.7 : An example of the lateral shower distribution from Pierre Auger Observatory. The energy
estimator (vertical red line) is set at 1000 m from the shower core where there are the least
uncertainties.
23
1.4.2 Imaging by fluorescence detection
The fluorescence trail generated by the EAS can be recorded by a UV camera or telescope. Typically a
huge mirror is used to collect the generated EAS induced photons before focusing them in a focal
plane made of an array of PMT. An example of the fluorescence detectors used in Telescope Array
experiment is shown in Figure 1.8. The fluorescence detection is particularly effective for high energy
cosmic rays as the intensity of the emitted photons is proportional to the particle energy. However
this kind of detection is required to be performed during the moonless nights, which basically
reduces the duty cycle to an average of 10%. Furthermore the site chosen for constructing the
fluorescence detectors must have good atmospheric quality and low absorption.
The longitudinal profile reconstruction of an Air Shower is done by the determination of its incident
direction. It is done by determining the shower-detector plane which is obtained from the triggered
PMTs. By using at least two fluorescence detectors, the orientation and the position of the shower
axis can be determined from the intersection of the shower-detector planes. Figure 1.9 illustrates the
determination of the EAS axis with stereoscopic detection.
(a)
(b)
(c)
Figure 1.8 : Telescope Array Fluorescence Detector. (a) Schematical view of the primary mirrors and
the PMT boxes. (b) 16x16 pixels PMT array. (c) 3.3 m diameter primary mirrors.
Figure 1.9 : Stereoscopic view of an Extensive Air Shower (EAS) from a pair of fluorescence detector
(FD). The EAS axis is determined from the intersection of two shower-detector planes (SPD).
24
Once the trajectory if the shower is known, the collected photons of each triggered PMT can be
directly converted into number of electrons according to the atmospheric depth. Obviously the
detected photon should also take into account the Cherenkov light which is beamed towards the axis
of the shower and should be removed from the observed profile. To convert the photon count into
shower energy, the rule of thumb is that 4 fluorescence photons are generated by an electron per
meter path length. This would give directly the shower profiles and the maximum depth of the
shower development, Xmax. Since the shower profile is known, the energy for the electromagnetic
part can be estimated by integrating this shower longitudinal profile:
∫
Where
2
is average ionization loss of the EAS (~2.2 MeV/(g/cm²)) and
profile (e.g. Gaisser-Hillas).
is the EAS longitudinal
To find the initial energy of the primary cosmic ray, a correction factor must be added to the
electromagnetic energy due to the fraction transferred to the hadronic shower components. The
correction factor, estimated by Air Shower Monte Carlo simulations, depends of the primary type
and its energy. Typically it is relatively small at high energies (<10% at 1020 eV). Consequently the
fluorescence detection is a particularly effective way to reconstruct the shower profiles and
properties of UHECR. This detection method is considered as the technique that measures the
shower energy in absolute way (absolute calibration). The different properties of an Air Shower are
shown in Figure 1.10.
2
Bethe-Bloch stopping power formula :
where is the thickness of the
traversed matter,
is the velocity of the particle in units of velocity of light, is the Lorentz factor and Z is
the charge of the ionizing particle.
and
are the constants for dry
air.
25
Figure 1.10 : An example of the measured longitudinal profile of an EAS. (a) Nmax,Emax determination
of the shower profile. (b) Total photon flux collection (black plot). The fluorescence is indicated in red
plot. Estimations of direct and scattered Cherenkov light are plotted in blue and green respectively.
(c) The electromagnetic energy ratio to the primary modeled by QGSJetII for Proton and Iron nucleus.
1.4.3 Hybrid and stereo detection
For recent high energy cosmic rays experiments, hybrid detection [29] method is somehow preferred.
The hybrid detection is done by combining the fluorescence imaging with the ground detection. For
example, at Pierre Auger Observatory, the 1660 Surface Detectors, which are scattered in an area of
3000 km², are complemented with 4 Fluorescent Detectors. Combining both detection methods can
bring a lot of advantages. In average the detection duty cycle will be increased as the ground array
can operated at least 90% of the time. Furthermore it will extend the detection range as the
fluorescent stations are better the high energy primaries and the low energy ones are detected by
the Surface Detector. In the case of the shower detected by only one Fluorescence Detector, having
the ground array would help greatly the determination of the EAS axis and trajectory. For hybrid
events which are triggered by both detectors, the shower profile can be reconstructed with a higher
precision as both detectors will reduce the uncertainties on the geometrical properties of the EAS
development. As explained in Section 1.4.2, the shower direction is determined by triggered PMTs or
more precisely the timing of the triggered pixels. The timing and angular information for a given
shower axis within the shower-detector plane (see Figure 1.11) are given by the following relation:
26
(
)
Where is the arrival time at the pixel, and
are the closest time and distance of the shower to
the pixel, is the pointing angle of the pixel to the shower axis and is the angle between the
shower axis and horizontal line.
The information regarding the shower axis can be extracted with a lot of precision in stereoscopic
observation. However in monocular view, there will be more uncertainties regarding the arrival
information (e.g. and
). This is where the ground array will come in handy where it could
provide better precision in the geometrical construction of the detected shower (see Figure 1.12). It
the case of Pierre Auger Observatory, the angular resolution of the hydride mode is ~0.3° compared
to the 1-2° and 3-5° respectively for the Surface Detector and Fluorescent Detector.
Figure 1.11 : Geometrical information of an Air Shower in hybrid detector.
27
Figure 1.12 : An illustration of a hybrid event reconstruction from Pierre Auger Observatory [30].
Top figure illustrates the Air Shower detected by Surface Detectors and Fluorescent Detectors. Two
bottom images show the air shower depth (Left figure) and lateral distribution (Right figure). The
energy of the primary is around 4.76.1018 eV.
1.4.4 Imaging from space
On the particularities of the EAS fluorescence imaging is it can be performed from the space as well.
The advantages of space based detections are the following:
 Bigger exposure area than ground based detectors
 Well confined space towards the shower
 Cloud and aerosol free on the upper part of troposphere.
 Similar cosmic rays flux exposure for both hemispheres.
Currently there are at least two experiments which are in preparation or in development stage. The
first one is TUS which is going to be a pathfinder of fluorescence imaging from space. TUS will be
launched on the Lomonosov [31] satellite circa 2012/2013. The second experiment still in
development is JEM-EUSO which is the main subject of this thesis. JEM-EUSO telescope shall be
attached to the external exposure facilities of the Japanese International Space Station (ISS) module,
KIBO. The artistic drawings of both experiments are shown in Figure 1.13.
28
(a)
(b)
Figure 1.13 : (a) TUS on Lomonosov satellite. (b) JEM-EUSO accommodated to the International Space
Station.
Figure 1.14 : The principle of space based UHECR detection.
Given by the high orbiting altitude of a space-borne fluorescence detector, there is a huge probability
that the whole Air Shower development could be seen within the detector field of view (see Figure
1.14). The trail of the isotropically emitted fluorescence light can be tracked by the detector’s pixels.
Towards the end of the shower development, a Cherenkov light could be seen due to the reflection
from the Earth. The Cherenkov reflection mark is particularly useful for space based detection as it
could be used for geometrical determination of the detected shower. It could provide a reference
time of the ground just like in a hybrid detection. An example of the fluorescence photons emitted
from an EAS seen downward from the space is shown in Figure 1.15.
29
Figure 1.15 : Simulation of the fluorescence photons seen from space versus time (GTU = 2.5 µs).
Total emitted photons are shown in black lines. The Cherenkov mark (reflected and scattered) is
shown in purple and cyan plots.
In the case of JEM-EUSO, the reconstruction method has been implemented in simulation software
called EUSO Simulation & Analysis Framework (ESAF) which is compatible for any space-borne
telescope detecting UHECR from the fluorescence and Cherenkov light. The reconstruction steps are
similar to monocular fluorescence detection. The pattern of the detected Air Shower has to be
determined and distinguished from the background (man-made light, noise, etc…).
Once the shower is extracted from the sky background, one can estimate its energy and maximum
shower development by resolving its direction in the shower-detector plane. The timing information
of triggered pixels is used in order to establish the arrival angle of the EAS. In the case where the
reflected Cherenkov can’t be recognized, the altitude of the maximum shower development has to
be predetermined and the arrival angle shall be calculated iteratively within the shower-detector
plane. If the Cherenkov mark is available (for shower inclination < 70°), it will ease the determination
of the primary arrival angle as the Cherenkov light indicates the end of the EAS. The timing difference
between the detected shower development and the Cherenkov light should be enough to determine
the arrival angle of the primary.
The last part of the reconstruction is to determine the equivalent energy of the primary. As explained
previously, the emitted fluorescence photons are directly proportional to the energy of the source.
Therefore the quantity of the emitted photons by the shower is estimated by taking into account
various factors such as the backscattering Cherenkov light and the efficiency of the instrument itself.
Finally the equivalent energy can be estimated by the longitudinal profile of the Air Shower.
Specifically to ESAF, the longitudinal profile is fitted to GIL formula (Section 1.3) as it seems to be fast
enough and comparable to the Monte-Carlo simulations. Naturally to finalize the energy estimation,
the missing energy shall be added according the species of the primary and also its estimated energy.
30
Chapter 2 JEM-EUSO Instrument
The concept of detecting high energy cosmic rays from the space is not recent, it was already
proposed by John Linsley [32] in 1979 in response to a NASA call for projects in high energy
astrophysics. However until now none of the space based UHECRs observatory has been flown or
passed the development phase. Since the inception of Pierre Auger Observatory, it is widely accepted
that next generation UHECR experiments with very sensitive detection surface have to be conceived.
Otherwise we would miss the opportunity to study the particles beyond the GZK boundary where the
flux of the cosmic rays is less than of one particle per km² per millenium.
JEM-EUSO (Extreme Universe Space Observatory on Japanese Experiment Module) can be seen as
logical step in the exploration of the extremely high energy particles where it could offer an
instantaneous detection surface of around 1.7 – 3.105 km² (with only 20% duty cycle) compared to
3000 km² of the biggest ground based cosmic rays experiment. This huge detection area will
eventually allow the high statistics required for observing the UHECRs. Previously, this project
(formerly known as ESA-EUSO) was already drafted by the European Space Agency as an external
payload of the International Space Station (ISS) European Module. A launch by the American Space
Shuttle was slated for 2009. Unfortunately this project was halted by financial problems and also by
the logistics issue due to the Space Shuttle Columbia accident. In 2003, this projected is resurrected
again by European and Japanese groups, but this time the telescope is to be attached to the
Japanese Experimental Module of the ISS. A sketch of JEM-EUSO and the incoming cosmic ray is
shown in Figure 2.1.
Figure 2.1 : JEM-EUSO and concepts of the mission operation. From
The UHECR detection technique of JEM-EUSO is based on monocular observation of the UV photons
emitted in the atmosphere. By coupling a wide Field-of-View (FOV) optics and the altitude of the ISS
(~400 km), this 2.6 m diameter telescope shall offer a huge detection mass for observing the Air
Shower.
31
By observing downward on the atmosphere, this telescope could be exposed to any phenomena
capable of generating photons in the UV spectrum. Thus JEM-EUSO could have a secondary scientific
objective from the observation of atmospheric events such as meteorites or Transient Luminous
Events (TLEs).
In the following several characteristics of the UHECR detection from space shall be exposed by using
JEM-EUSO telescope as example. The instrument, the planning and the associated projects to JEMEUSO will be described from Section 2.1 to Section 2.5. The requirements on the photodetector
readout electronics, conceived as an integrated circuit or ASIC, stemming from this instrument design
and the observed phenomena will be outlined towards the end of this chapter.
Figure 2.2 : JEM-EUSO in nadir mode orbiting from 400 km.
Optics
The optics characteristics are particularly important in this telescope design. Typically the FOV should
be chosen correctly as the tradeoff between the optical design, the target detection surface and the
required accuracy. For JEM-EUSO optics, the FOV is chosen at α = ±30° with a point spread function
(PSF) of a few mm. Once the FOV of the telescope is specified, the equivalent detection area
observed on Earth can be estimated. For example by taking the nadir3 position of the telescope (see
Figure 2.2) and flat Earth assumption, the observation area, A0 as a function of the telescope orbit H,
and the FOV angle, α, can be calculated as the following:
In the case of JEM-EUSO, the observation area for nadir mode is around 1.7.105 km² by taking into
account the ISS orbit of 400 km and the ±30° of the telescope FOV. In order to increase the
3
JEM-EUSO telescope will have 2 operation modes : nadir and tilted. In nadir mode, JEM-EUSO will be looking
orthogonally downward to the earth surface. In tilted mode, this instrument will be tilted, forming an angle
between the earth surface axis (zenith) and JEM-EUSO’s optical axis.
32
observation area, it is possible to tilt the instrument axis. Tilting the instrument is the most effective
way for this purpose as it will not require a redesign of the instrument in order to achieve the same
results. Figure 2.3 shows the simulations of the JEM-EUSO field of view and the obtained observation
area from tilting the telescope.
(a)
(b)
Figure 2.3 : (a) Shape of JEM-EUSO observation area. (b) Observation area as a function of the tilting
angle.
In JEM-EUSO, the tilt angle is around 30° (subject to change) which results into an observation area
of nearly 3.105 km². The gain of the observation area will surely increase the yearly exposure of the
cosmic rays fluxes and also raise the threshold of the minimum particle energy which can be
detected. The comparison for both JEM-EUSO exposure modes with other cosmic rays observers is
shown in Figure 2.4.
Figure 2.4 : Expected exposure (km² sr yr) of JEM-EUSO. Thick blue curve corresponds to the nadir
exposition and thick red curve corresponds to the tilted observation. For comparison, JEM-EUSO
exposure shall surpass the exposure of Pierre Auger Observatory (pink curve) in less than 2 years of
33
operation. These numbers include the 20% of JEM-EUSO duty cycle compared to 100% duty cycle of
Pierre Auger Observatory.
Pixel size
Typically the UV camera fitted to a fluorescent telescope is highly pixelated in order to have the
smallest granularity and better precision in Air Shower profile reconstruction. Obviously the required
number of pixels would rule the electronic design of the instrument. As a rule of thumb, for an
observation from the space, pixel granularity (Δl) is expected to be lower than 1 km. In the case of
the optic’s point spread function is well matched to the size of a pixel, the number of pixels, N, can
be estimated directly from the observation area of the instrument,A0:
By taking into account the condition for the granularity and the observation area in nadir mode, the
pixel count of JEM-EUSO telescope is well over 1.7.105. In current instrument design, the UV camera
of JEM-EUSO has roughly 3.105 pixels with the granularity of 0.75 km which covers an area of 0.56
km² on Earth. Considering the number of pixels is very huge, the photon sensor array should be as
compact as possible and have good performances in terms of noise and photon sensibility.
Furthermore the dead space of the detection surface should be as small as possible. The baseline
photo detector for JEM-EUSO is Multi Anode Photo Multiplier Tube (MAPMT) whose pixel size shall
be in the order of 3 mm x 3 mm.
Electronics sampling time
Another aspect which concerns the electronics of the instrument is the sampling time at the pixel
level. Typical duration of an Air Shower seen from JEM-EUSO is in the order of 50-150 µs. For obvious
reason, the sampling time should be the lowest as possible in order to achieve a resolution similar on
all axis. This sampling time could set to match the propagation of an Air Shower within the area
observed by a pixel. In the JEM-EUSO, the sampling time known as Gate Time Unit (GTU) which can
be calculated as the following expression:
In the case of JEM-EUSO pixel granularity of 0.75 km, the GTU for the electronics sampling time is set
at 2.5 µs.
Expected signals
The signal, thus the number of photons is proportional to the collection surface given by the first lens
surface. The fluorescence photons are distributed isotropically during the shower development. It is
estimated for a particle of energy 1020 eV, it would generate around 1015 fluorescence photons.
Therefore for a telescope situated at an altitude of H and equipped with a lens of radius R, the
fraction of photon collection is as the following:
In the case of JEM-EUSO, H = 400 km and R = 1.25 m, the fraction of the detected photons is at the
order of 10-12. Thus the collected photons at the detector surface are around 103. By taking into
34
account the atmospheric absorption which is around 50% and the efficiency of the instrument which
is around 10%, the detected photons would be reduced to hundreds of photoelectrons. It is obvious
that the photon collection is quite low which makes this type of observation more suitable for
extreme energy cosmic rays. In JEM-EUSO, the minimum energy threshold for the cosmic ray
detection would be around 5.1019 eV in the nadir observation mode.
JEM-EUSO instrument characteristics
The general characteristics of JEM-EUSO telescope [33] are summarized in Table 2.1.
Specification parameters
Values
Field of View
±30°
Observational area
> 1.7 x 105 km²
Optical bandwidth
330 – 400 nm
Focal Surface area
4.5 m²
Number of pixels
3.16 x 105
Pixel Pitch
2.88 mm
Pixel granularity at ground
~0.75 km
Spatial resolution
0.07°
Data sampling
2.5 µs
Duty cycle
~20%
Total mass
1983 kg
Power consumption
< 1kW
Table 2.1 : Summary of the JEM-EUSO telescope characteristics.
2.1 Instrument components
In addition to the main fluorescence telescope, an atmospheric monitoring system (Infrared camera
and LIDAR unit) and a calibration system are also to be fitted to this instrument. The atmospheric
conditions (transparency, cloud coverage, height of the clouds,..) needs to be monitored
continuously as this information is required for the shower reconstruction work. Naturally a
calibration system is needed in order to measure the efficiencies of the optics and photon sensitive
devices. The instrument calibrations will be performed on the ground (absolute calibration) and also
onboard of the ISS (relative calibration). For the following only the subsystems of the fluorescence
telescope will be reviewed. A schematic view of the telescope is shown in Figure 2.5.
35
Figure 2.5 : JEM-EUSO telescope within its mechanical structure and deployment system. The three
Fresnel lenses constitute the front optic part of this instrument. The photon to digital conversion is
assured by the electronics in the Focal Surface at the rear of the instrument.
This telescope is based on three Fresnel lenses which are used for focusing the light to the detectors
placed at the rear of the instrument. The electronics related to the detectors are also located in part
of the instrument as well which is known as Focal Surface.
2.2 Optics
The optical module of JEM-EUSO is required to have a large aperture and FOV in order to have an
observation area as big as possible. Additionally the optical system should be lightweight enough in
order to fit the mass budget available for JEM-EUSO on the ISS which is around 2 tons. Due to the
limited unpressurized stowing area of the H-II Transfer Vehicle (HTV), the optical module thus the
telescope shape is not circular. In fact the diameter of optical module is 2.65 m with two sides cut
into 1.9 m. As presented in previous section, three lenses are used for focusing the photons: two
curved double-sided lenses for front and rear lens and a diffractive/Fresnel lens in the middle. There
are two designs based on the fabrication material are being considered for JEM-EUSO. The “Baseline”
design has all lenses made from PMMA and the “Advanced” design use CYTOP lens for the front and
PMMA for the other. CYTOP has superior optical properties than PMMA which is the reason it is
considered for the “Advanced” design. Despite its superior optical performances, CYTOP lens is
penalized by its weight and costs. For this reason, it is not viable to have all CYTOP optics in JEMEUSO. The cross section view of the lenses design and their performances are shown in Figure 2.6
and Table 2.2 respectively.
36
Figure 2.6 : Cross section views of optics Baseline design (left) and Advanced design (right).
Requirements
Baseline optics
Advanced optics
f/# (F number)
< 1.25
1.0
1.0
Lens diameter
≥ 2.5 m
2.5 m
2.5 m
Spot Size (RMS)
≤ 5 mm
5.0 mm
5.0 mm (2.5 mm)
Throughput
50%@0°-10°
59%@0°-10°
62%@0°-10°
40%@10°-20°
52%@10°-20°
58%@10°-20°
30%@20°-30°
39%@20°-30°
42%@20°-30°
Filter transmittance
≥ 90%
> 90%
> 90%
Mass
≤ 264 kg
154 kg
202 kg
Table 2.2 : Summary of the optics Baseline design and Advanced design performances.
2.3 Focal Surface
Basically the Focal Surface [34] of JEM-EUSO is required to perform the detection of UV photons, to
filter the UV background noise and to trigger the Air Shower events. As explained at the beginning of
this chapter, the granularity and the number of pixels are some of the important aspects of UV
imaging. Naturally, the Focal Surface should have good detection characteristics for the UV photons
of 330 - 400 nm wavelengths. In order to track the development of the EAS, the time response of the
Focal Surface should be in the order of µs. Of course the whole components should comply with the
constraints for operating in the space and can stay afloat during the whole duration of this mission.
This subsystem incorporates the photon sensitive devices and the associated electronics at the rear
of the telescope as illustrated in Figure 2.7. The totality of the Focal Surface (FS) sits on a mechanical
structure with dimensions of 2.65 m x 1.9 m. The arrangement of FS in done in a modular way where
it is divided into following units: Photo-Detector (PD), Elementary Cell (EC) and Photo-Detection
Module (PDM). The modularity is an important consideration in the Focal Surface design as it could
reduce risk of single point failures. The equivalent units of each module (from FS to the detection
pixels) are listed as following:




FS = 137 PDMs
PDM = 3x3 ECs = 9 ECs = 36 PDs
EC = 2x2 PDs = 4 PDs
PD = 8x8 Pixels = 64 Pixels
37
In total, there are around 3.105 Pixels for the FS which are arranged in Cartesian coordinates as
illustrated in Figure 2.7. Also shown in the same figure, the Photo-Detectors are arranged with a
certain curvature in order to accommodate the optics focusing. This is done at the level of ECs where
each unit is mounted on a spherical surface with radius of 2.5 m. As shown in Figure 2.7, the PhotoDetector for JEM-EUSO is a 64-channel MAPMT which has the pixels arrangement of 8x8. The
characteristics of this MAPMT will be reviewed later in the following Section 2.3.1.
Figure 2.7 : The structure of the Focal Surface of JEM-EUSO.
Another important aspect of the Focal Surface is the mechanical structure which will house the
MAPMTs and also the readout electronics. For each PDM, a mechanical frame is used to hold
MAPMTs. This frame is designed in order to fit two electronic boards bearing the same size of an EC
unit. Additionally, the volume behind this frame is available and can be used to accommodate other
electronics boards which are required for PDM.
(a)
(b)
(c)
Figure 2.8 : Front (a) and rear (b) view of the PDM frame. (c) The emplacement of the MAPMTs and
electronics within a PDM.
38
The implications on the readout electronic board design due to the PDM mechanical constraints will
be discussed later in Chapter 6.
2.3.1 MAPMT
Since the beginning of ESA-EUSO, MAPMT has been chosen as the photon detection device over
other detectors such as SiPM. This choice was made based on noise performance, availability, cost
and the absence of cooling system. As the baseline for JEM-EUSO Photo-Detector, 64-channel
R11265-M64 MAPMT from Hamamatsu Photonics K.K was selected. This MAPMT was developed in
collaboration with RIKEN which is one the leading institution in JEM-EUSO consortium. The pictures
of this MAPMT are shown in Figure 2.9:
Figure 2.9 : JEM-EUSO baseline MAPMT: Hamamatsu R11265–M64.
This MAPMT is chosen to replace the baseline previously established for ESA-EUSO. Compared to the
old baseline, this MAPMT is significantly better especially for the effective sensitive area.
Furthermore, the pixel number is increased from 36 to 64 which gives a better granularity for the
photon detection. The characteristics of HAMAMATSU R11265-M64 are shown in Table 2.3.
Specifications
Photocathode material
Pixel pitch
Sensitive area
Values
Super Bialkali
2.88 mm
23.04 mm x 23.04 mm
26.2 mm x 26.2mm x 20.25
Physical dimensions
mm
Mass
27.3 g
Spectral response range
185 nm to 650 nm
Quantum efficiency
> 35% (maximum 40%)
Number of dynodes
12
Maximum supply voltage
1100 V
Gain
106 @ 900 V
Dark current
0.4 nA
Anode pulse rise-time
≤ 1 ns
Gain uniformity between each anode
1:3
Cross-talk between pixels
~1%
Operating temperature
-10°C to 30°C
0.1 relative gain variation
Magnetic field effects
at 2 Gauss
Table 2.3 : Characteristics of Hamamatsu R11265 – M64.
39
Usually, the high voltage for powering this MAPMT can be supplied either from a set of voltage
divider or externally for the cathode and the dynodes. For embedded application, a resistive voltage
divider is preferred as the required voltage supplies (14 values in total) can be generated from a
single source and the power consumption could be potentially low depending on application.
However in JEM-EUSO scheme, the dynamic range of the MAPMT input could vary at least in the
order of 100 for each pixel. For the resistive voltage divider solution, its average power consumption
has to be increased as well in order to cope with the MAPMT input dynamic range. Thus this solution
is not suitable for JEM-EUSO. A Cockroft-Walton voltage multiplier is proposed for powering the
MAPMTs. The advantage of this voltage multiplier is that the average power consumption is rather
low but it is capable of supplying sufficient power for the required MAPMT input range due to its low
impedance at each stage.
2.3.1.1 MAPMT operating modes in JEM-EUSO and measurement methods
In the case of JEM-EUSO, the measurements of the MAPMT pixel (or anode) signal are done for two
different operating modes: low light (single photoelectron) and strong light (DC level). The
illustrations of the anode output for both operating modes are shown in Figure 2.10.
(a)
(b)
Figure 2.10 : MAPMT operating modes. (a) Single photoelectron measurement mode. (b). DC level
measurement mode.
Single Photoelectron mode
In a typical case of JEM-EUSO air shower observation, the MAPMT will operate most of the times in
single photoelectron mode where the arrival photons rate is rather low. Ideally in this case, the
readout circuit should work in photon counting mode [35] as the discrete anode pulses can be
counted individually. In this type of measurement, the main specifications for the electronics are the
counting linearity over a lapse of time and the dead-time or double pulse resolution. It should be
known that the photon counting circuit will exhibit non linearity as the arrival photon rate increase.
This non linearity occurs due to the dead-time of electronics caused by the pulse pile-up. The true
counting rate of the photon, N, could be expressed as a function of the measured count rate, M and
the double pulse resolution, t :
40
The illustrations of the counting rate error are shown in Figure 2.11.
(a)
(b)
Figure 2.11 : An example of counting rate from a circuit of 18 ns double pulse resolution. (a)
Counting rate as a function of incident photons. The measured signal (solid black curve) is linear up
to the rate of 107 s-1. (b) Counting rate linearity correction. The error of the corrected linearity in
shown in dashed line.
Another interesting aspect of the photon counting method is the relation between the counted pulse
over a certain threshold and the height distribution of the anode pulse itself. This relation is
illustrated in Figure 2.12.
Figure 2.12 : (a) Pulse height distribution of an anode signal. (b) Noise distribution without input
signal. (c) Count data which corresponds to the number of pulse over the threshold.
From Figure 2.12, the count data of anode pulses (Figure 2.12 (c)) is simply the integral of the anode
pulse height distribution or the single photoelectron spectrum. In similar manner the pulse height
distribution is the differential of the count data. As shown Figure 2.12, the counter threshold is set
low enough in order to discard the noise (e.g. pre-amplifier noise). The single photoelectron peak is
located as the inflection point of the counting values (represented in Figure 2.12 (c)). This property
41
comes from the fact that the pulse count is the cumulative distribution function of the anode pulse
distribution.
Pile-up or DC level mode
The second MAPMT operation mode (see Figure 2.10 (b)) is when the anode output can be
considered as a DC level resulting from high arrival photons rate. Specifically in JEM-EUSO, this case
will happen as the incident photons flux could rise either proportionally to the energy of the primary
cosmic ray or to a much higher level due to the atmospheric phenomenon such as meteors, lighting
or TLEs. Therefore, the readout unit should be able to handle the anode signal transition from
multiple overlapped pulses until it becomes nearly a DC level. Typically for this kind of measurements,
a high speed Analog to Digital Converter (ADC) or a charge integrating circuit is required.
42
2.3.2 Electronics
The electronics of the Focal Surface are required to execute several tasks such as reading out the
MAPMTs, triggering the Air Shower events and compressing and recording the data. Additionally the
Focal Surface electronics would also interact with other components which are required to ensure
the operation of the instrument.
First of all, the MAPMTs readout is assured by SPACIROC ASICs which are the main subject of this
work. The ASICs is required to perform the analog to digital conversion within the defined gated time,
GTU. The electronics which interacts directly with the MAPMTs are classified as Front-end Electronics
(FEE).
The digital data from the FEE is then collected by the PDM board which is mainly a Field
Programmable Gate Array (FPGA). The first level trigger (L1) processing is performed at this level.
This is one of the components of the multilevel trigger implementation in JEM-EUSO. Additionally,
the PDM board would be also responsible to configure the readout ASICs and perform other auxiliary
functions.
Going higher in the hierarchy, there will be Cluster Control Boards (CCBs) which are also based on
FPGA. The second level trigger (L2) is implemented at this level. Finally the last piece of the FS
electronics is the Micro Processor Unit (MPU) which serves as the main controller of the instrument.
It shall be the interface with the ISS and also auxiliary components such as housekeeping unit, power
supply, and memory unit.
The outline of the electronics in JEM-EUSO is shown in Figure 2.13.
Figure 2.13 : Focal Surface electronics data flow from the FEE up to MPU. Data compression is done
progressive at each trigger level (L1 and L2).
The main hardware of the PDM is described in brief in the following sections.
43
2.3.2.1 Front-end Electronics
As described earlier in this section, the FEE concerns the MAPMT readout and digital conversion. For
this usage, a compact readout system based on application-specific integrated circuit (ASIC) is
proposed. In terms of functionality, the ASIC must be able to deal with different types of the anode
signals. As cited in Section 2.3.1, the anodic pulses of the MAPMT will be in discrete mode (photon
counting) and also DC mode (integration) due to the wide range of the events which could be
observed by JEM-EUSO. Both photon counting and integration functions are the basis of the analog
part of this ASIC. To complete the readout solution, digital part are also implemented which allows
the analog-to-digital conversion for each GTU. The design of this ASIC is presented in Chapter 3.
The secondary part of the FEE is the front-end boards which are used to house the MAPMTs and also
the ASICs. Several works have been carried out for designing the front-end boards which are exposed
in Chapter 6. It will be seen later that designing front-end boards for JEM-EUSO is not trivial due to
strict constraints from this instrument operating conditions and congestions.
2.3.2.2 Photo-Detection Module Board
The electronics (PDM board) of this part is mainly responsible for the triggering, data readout and
ASIC configuration. In terms of implementation, each PDM board is connected to nine ECs which
correspond to 36 MAPMTs and ASICs. In total there will be 137 PDM boards as stated at the
beginning of the Focal Surface section.
The PDM board is based on FPGA with huge number of input and outputs as the high-speed
communication interface to the ASICs requires a huge number of pins. Additionally auxiliary memory
storage could also be implemented as huge number of raw data (~7 Gb/s for one PDM) has to be
processed at this level. The processed data which are mainly L1 triggers are then sent to CCB. Besides
the communication interface between the ASICs and CCB, PDM board should also interact with other
modules such as the housekeeping and the high voltage generator.
2.3.2.3 Cluster Control Board
This board is mainly responsible for a cluster of PDM and just like PDM board is also based on FPGA.
Basically a CCB could be connected up to 8 PDM boards. As the data transmission is only started once
L1 is triggered, therefore the data rate is greatly reduced between the PDM and CCB. In any case, the
overall data rate at this level has to be reduced down to 300 kb/s if a downlink to the Earth is used or
900 kb/s if a temporary onboard storage is used. For this reason a L2 trigger is implemented on CCB
which will help greatly to filter the data only to the useful scientific data. The final data will be sent to
the MPU which will serve as the interface between FS electronics and the ISS.
44
2.4 Trigger
Although the data rate at the Focal Surface is relatively huge, not all the data are really useful for the
track reconstruction. Therefore a multilevel trigger implementation is deemed to be suitable for
selecting useful data and reducing the data rate. Additionally the available bandwidth for final data
transmission is limited; therefore trimming down the data is required for this mission.
The trigger can be divided into two levels [33] which are listed in Table 2.4. It also gathers the
expected trigger rate at each level.
Level
Trigger rate at PDM level Trigger rate at FS level
Photon Trigger
~9.2.108 Hz
~1.4.1011 Hz
L1
Counting Trigger
~7.2.105 Hz
~1.1.108 Hz
Persistency trigger
~7 Hz
~103 Hz
-4
L2 (CCB/PDM cluster)
~6.7.10 Hz
~0.1 Hz
Expected cosmic ray events
~6.7.10-6 Hz
~10-3 Hz
Table 2.4 : L1 and L2 Triggering rate for PDM and FS. From [33].
The triggering rate shown in Table 2.4 is for detecting the cosmic rays which is the baseline of the
trigger operations for JEM-EUSO. In this case the sampling time, GTU is set to 2.5 µs. For the first
level trigger,L1, it is divided into 3 sublevels:



Photon Trigger : This trigger is in fact implemented in the readout ASIC. Its role is to
discriminate any incoming UV photons from the electronics noise. Every photon triggered
events is sent to the PDM board.
Counting Trigger : This sublevel trigger is implemented in the FPGA of the PDM board. This
trigger is based on digitally set thresholds which will discard the background noise. Due to
the variation of the background level (e.g. Airglows, moon, urban areas,…), an auto-trigger
function can be implemented in order to automatically set the digital threshold. In order to
contain the whole Air Shower profile, the data needed to be buffered at least for 128 GTUs.
Persistency Trigger : This trigger is set to look for any known pattern within the same PDM
for several GTUs. If the persistency is confirmed with respect to a pre-set value, the first level
trigger will flag the second level and the system will be ready to readout the event according
to the required exposure.
The second level trigger, L2, is implemented at CCB level which regroups the 137 PDMs into 18
clusters. At this level each cluster will handle 8 PDMs. L2 trigger uses an algorithm called “Linear
Track Trigger” which consists of tracking movements at the speed of light 400 km below the detector.
Additionally the trigger decision could be made following trigger modes which consists of modifying
the GTU length according to the physics phenomena observed. By doing so, the trigger information
could be really reduced to the useful data which really resemble to the expected events.
There will be at least two triggering modes for the track detection: Baseline UHECR mode and Slow
mode. In the baseline UHECR mode, the GTU is set at 2.5 µs as explained earlier in this section. The
maximum exposure in this mode is set between 30 µs to 300 µs (12 - 120 GTUs), which is more than
enough to contain the typical Air Shower development. Basically other events which don’t fit this
duration shall be discarded. On the other hand, the slow mode can be used if the targeted
phenomena are longer than 300 µs. The exposure shall be raised higher than 300 µs but at the
45
expense of bigger sampling time, GTU > 2.5 µs. The summary of the events [33] which could be
observed by JEM-EUSO is listed in Table 2.5.
Event
Region
Event rate
Event size
Event
duration
Meteors
Atmosphere
5-100/hour
0.5-2 m
0.5-3 s
Lightning
Troposphere
3/min
~ km
0.1 s
Sprites
Mesosphere
Stratosphere
Troposphere
Mesosphere
Unknown
~km
Few ms
Light
spectrum
Violet to
red
Violet to
red
Red
Unknown
Tens of km
~ 0.4 s
Blue
104 W
Unknown
~200 km
< 1ms
Red
-
Mesosphere
Variable
Tens of km
Hours
Solar
-
Mesosphere
Atmosphere
Variable
Hundreds
of km
Minutes to
hours
Jets
Elves
Noctilucent
clouds
Event
energy
Variable
1012 W
107 W
Violet to
1010 W
red
Space
Violet to
Atmosphere
~5/day
0.5-2 m
0.5-3 s
Variable
debris
red
Table 2.5 : Potentially observable phenomenon from JEM-EUSO. Taken from [33].
Auroras
In terms of the background noise (Airglow, moon or man-made lights), the different studies (based
on data from Tatiana satellite and balloon flights) have shown that the average noise is around 500
photons/m²/ns/sr. The estimated instrument duty cycle for this noise level is around 20%. At one
pixel, the estimated noise level shall be around 15 photons/GTU. By taking into account the
efficiency of the instrument (~10%), the background noise seen at each pixel is around 1.5
photoelectron/GTU.
2.5 Planning and deployment
In current situation, the instrument would be launched not earlier than January 2017 depending on
the decisions from the involved space agencies like JAXA, NASA, ESA and Roscosmos. Currently the
design of the instrument is considered past Phase A which corresponds to the conceptual and
laboratory design. Typically all the collaborators and hardware providers are ready to proceed to the
Phase B or the preliminary design of the instrument. Figure 2.14 shows the tentative schedule until
prospective launch date.
Figure 2.14 : JEM-EUSO schedule for a tentative launch date in January 2012. The current
status,Phase A, was completed in 2011.
46
In the case of the JEM-EUSO deployment to the ISS, the H2B rocket shall be used as the launch
platform. The telescope shall be then conveyed to the ISS by Japanese Space Agency (JAXA)’s HTV
before the telescope is unloaded from the payload bay and attached to the external exposure
platform of KIBO module. In order to enter the payload bay of HTV, the overall dimensions of the
telescope shall be compacted with the usage of expendable cylinders. The illustration of the
telescope in stowed state and deployment state is shown in Figure 2.15.
(a)
(b)
Figure 2.15 : (a) Structural view of JEM-EUSO in launch state. (b) Structural view of JEM-EUSO in
observation mode
Additionally, in parallel to the JEM-EUSO planning, there are also two projects which are conceived as
the test beds for the JEM-EUSO instrument. The first one is flying a smaller scale of JEM-EUSO
telescope with a stratospheric balloon (EUSO-Balloon). This project, which is financed half by Centre
National d’Etude Spatiale (CNES) and other half by JEM-EUSO collaboration, should be launched
around 2014. The payload of EUSO-Balloon is nearly identical JEM-EUSO except for the number of
PDM where it is reduced to only one unit. Naturally, other main components are also scaled down in
order to accommodate one PDM. The objectives of this balloon mission are the following:



Technology demonstrator with real condition tests of the key components and subsystems of
JEM-EUSO.
UV sky background imaging and measurement.
Detection of EAS with energy over 1018 eV which could develop within the field of view.
The second project which shall be deployed towards the beginning of 2013, is for testing PDM unit at
Telescope Array (TA) site. This project, known as EUSO-TA, will use basically the same hardware
developed for EUSO-Balloon [36] at least at the PDM level. The engineering tests of the PDM unit will
be done by performing cross calibrating with the Fluorescence Detector of TA. After the calibration,
the PDM unit under test could be used for Air Shower imaging along with Surface and Fluorescence
Detectors of TA.
47
2.6 Design considerations for the MAPMT readout ASIC
As explained in Section 2.3.1, the MAPMTs are used in single photoelectron mode for detecting the
arrival UV photons emitted from the EAS. Figure 2.16 shows the simulations of the detected photons
of a typical EAS induced by particles with energy at 1020 eV.
Figure 2.16 : Simulations of photons emitted by an EAS generated by a primary of 1020 eV. The
duration of the EAS including the Cherenkov mark is around 60 GTUs (150 µs). The impinging photons
on the first lens are in blue histogram and the detected photons are in green.
From Figure 2.16, the maximum detected photon is within 30-40 photoelectron/GTU. This
information will mainly concern the linearity photon counting part of the readout circuit. When
designing the circuit, the double pulse resolution should be kept as low as possible in order to have
the highest linearity. For example, it is estimated that in order to count linearly up to 30
photoelectron/GTU, the double pulse resolution should be around 27 ns. For the MAPMT the anode
signal rise-time is around 1 ns (cf. Table 2.3) and the signal occupancy is around 5 ns or less. Ideally
the double pulse resolution of the photon counting could be set as low as 10 ns.
The second consideration of the readout design concerns the dynamic range extension of the photon
counting. Usually, the count rate non linearity will increase with the intensity of the incident photons
until at one point the data error due to dead time is too important to be corrected. The incident
photon flux increases proportionally to the energy of cosmic rays which induced the EAS. Moreover,
other atmospheric phenomena can emit photon flux which is orders of magnitude more intense than
the one emitted by the EAS. Generally, a MAPMT could be damaged if it is exposed for a prolonged
duration to intense light (a few ms for Hamamatsu R11265-M64). This is where a secondary readout
function would come in handy where it should be able to readout the equivalent charge of the anode
signal. Usually an ADC is the best solution for this kind of application but it is discarded due to the
high power consumption especially for high speed sampling like in JEM-EUSO. Simpler solutions such
as Time-Over-Threshold based charge measurement could be used as long as the power
consumption requirement is respected. Typically, the baseline MAPMT of JEM-EUSO can handle
48
photon flux up to 100 times of the UV sky background (1.5 photoelectron/GTU/pixel at its nominal
gain). Therefore the upper limit of the charge measurement can be set at 150
photoelectron/GTU/pixel.
There are also several aspects which should be considered in designing the readout ASIC. For
example the nominal gain of the MAPMT is set at 106 in order to have high gain for detecting faint
source of photons. To summarize, the requirements for the ASIC are listed as following:









Low noise: ≤ 25 ke- rms
Power consumption: ≤ 1 mW/ch
Radiation hardness. Expected accumulated radiation dose for 5 year operation : ~30 krad
Data sampling: GTU = 2.5 µs (400 kHz).
Photo Counting linearity : ≥ 30 photoelectrons/GTU
Photon Counting Double Pulse Resolution : ≤ 30 ns
Photon Counting triggering efficiency : 100% @ 1/3 photoelectron/GTU
Charge measurement dynamic range: 1.5 – 150 photoelectron/GTU or sensitivity of factor
100.
Individual gain correction for each MAPMT channel. Correction ratio 1:3.
Based on the above requirements, the technology process for the ASIC has to be chosen correctly in
order to match the required analog processing speed and power consumption. Typically in high
speed analog application such for mobile phones or optical communication, BiCMOS technology is
preferred. The main reason is BiCMOS technology include the contemporary Complementary MetalOxide-Semiconductor (CMOS) transistors and also high-speed Bipolar Junction Transistors (BJT). We
will see later in Chapter 3, the design of this ASIC is done by using a BiCMOS technology provided by
Austriamicrosystems (AMS) which offers 0.35 µm transistors process.
49
Chapter 3 Front-end ASIC
3.1 Introduction
In order to accommodate the readout of the huge number of MAPMTs in JEM-EUSO, it is obvious
that an Application Specific Integrated Circuit (ASIC) solution is the only viable solution as opposed to
the traditional discrete components. Furthermore an ASIC will fit perfectly in terms of mass, power
budget and electrical performances required for this telescope.
According to the specification of JEM-EUSO, this readout ASIC is required to perform the analog to
digital conversion of the MAPMT signals for every GTU which equals to 2.5 µs. For measuring the
MAPMT signals, the ASIC incorporates two functionalities: photon counting and charge measurement.
The photon counting (shall be designated as Photon Counting in this ASIC design), is performed for
the 64 anodes of the Hamamatsu R11265-M64 MAPMT. The design of this part is based on MAROC3
chip which was developed by OMEGA group at Laboratoire de l’Accélérateur Linéaire (LAL). It will be
seen later that the design is based on transimpedance structure which involves current to voltage
conversion.
For the charge measurement unit, the design was supplied by our Japanese partners (ISAS/JAXA,
RIKEN and Konan University) based on KI 02/03 [37] chips. Time-Over-Threshold (ToT) technique is
used for this purpose. Due to the name of the original design, the ToT module is referred as KI
(abbreviation of Konan University and ISAS) in this work. Unlike for Photon Counting, the charge
measurement is not done for each channel. Instead, the 64 pixels are divided into 8 groups by
summing every 8 neighbouring channels. The regrouping is done as the charge measurement is done
for intense incident photon flux which can hit multiple pixels simultaneously. Furthermore it will save
a lot of power as only 8 measuring channels are required instead of 64. Additionally, there is one
channel of ToT module which is dedicated to the MAPMT last dynode. The information from the
dynode could be used in the MAPMT protection strategy as it could give a measurement on the
photon flux arriving on the whole device.
To accommodate the MAPMT readout, an ASIC called “Spatial Photomultiplier Array Counting and
Integrating ReadOut Chip” (SPACIROC) [38] has been developed in 2010. For the design, the MAPMT
gain is supposed to be at nominal value which is 106. Therefore one photoelectron (p.e) is equal to
160 fC. The characteristics of the ASIC based on JEM-EUSO requirements are the following:






64-channel pre-amplifier with individual gain correction (8-bit)
Photon Counting :
 64 channels
 Double Pulse Resolution : 30 ns @ 1p.e (160 fC)
Time-Over-Threshold charge measurements:
 9 channels : 8 internal channels (summed signal) + 1 channel for dynode
 Input range: 2pC - 200pC (12.5 p.e - 1250 p.e )
Power consumption : ~1 mW/channel
9 data serial outputs + Transmit On signal
Data transmission every GTU = 2.5 µs
50
The process technology used for this ASIC is AMS4 0.35 µm SiGe BiCMOS which is a proven mixed –
signal process. The SiGe Heterojunction Bipolar Tansistor (HBT) in this process is particularly suitable
when designing a high-speed and low power front-end circuits. Typically this technology is employed
in telecommunication applications such as GSM, GPS and Wireless LAN.
The design of this ASIC involves two separated flows: analog and digital. Once the design of each flow
is finalized, the physical drawings at the silicon level will be merged together. The final physical
drawings or layout will be then streamed out into GDSII format in order to be sent to the foundry for
fabrication. In our case, the ASIC was produced through France based Circuit Multi-Projets (CMP)
which offers services in low volume ASIC prototyping. The flow charts for both analog and digital
design of this ASIC are shown in Figure 3.1.
Figure 3.1 : ASIC design flow chart. From design specifications to the tape out of the circuits for
fabrication.
For both analog and digital design, the software from Cadence Design System, Inc. is used. Virtuoso
software families are used for analog schematic capture, simulations and layout. On the other hand
IUS simulators, RTL compiler and SOC Encounter were used for simulations, synthesis and
floorplanning of the digital design.
For the following, we will see the descriptions of the main analog (Section 3.3 - 3.6) and digital
(Section 3.7) components in the ASIC. For the main analog components, the simulations were done in
schematic and post-layout (to be referred as Extracted Parasitics in this work) in order to validate the
behavior of the design. The digital parts were simulated in behavioral level in order to validate the
logic designs and in back-annotation (post-layout) mode to verify the compatibility of the design to a
given timing constraints. Afterwards the digital layouts were transferred to the analog design tools in
order to complete the physical side of the chip.
4
ams AG (formely known as austriamicrosystems AG) : http://www.ams.com/eng
51
3.2 General Architecture
The design of SPACIROC ASIC is dominated by the Analog part. A digital part is also included in order
to digitize the analog signals and to manage the data transmission. The general architecture of this
ASIC is shown in Figure 3.2.
Figure 3.2 : SPACIROC general architecture. The 64-channel MAPMT anode signals are pre-amplified
and fed to the Photo Counting (light yellow box) and Time-Over-Threshold (green box) which also
receives the dynode input. The digital part (blue box) is used for the digitizing the signal and
managing the data readout. The auxiliary components such as bandgap voltage reference, DACs and
Slow Control cells are not shown in this Figure.
As shown in Figure 3.2, the 64 inputs are coming from MAPMT Anodes which are fed into 64
channels pre-amplifier. There is one additional input for MAPMT Dynodes (D12) which is used by the
charge measurements. The analog part could be divided into 2 main functions: Photon Counting
(Section 3.4) and Time-over-Threshold (Section 3.5). Both cited functions provide to the digital part,
the discriminator (or trigger) outputs which are used for digital conversion. The digital part takes 64
trigger signals from Photon Counting and 9 trigger signals from the ToT.
The layout of SPACIROC is shown in Figure 3.3. This ASIC has 166 pins and it was packaged in
CQFP240 for the laboratory tests. The core voltage of this ASIC is at 3 V except for the digital output
buffer which is powered at 1.5 V. The configurations of SPACIROC ASIC are done via a set of registers
which are referred as Slow Control in this work.
52
Figure 3.3 : The layout of SPACIROC with the positions of the main components. The ASIC size is
around 19 mm² (4.1 mm x 4.6 mm).
In the following, the functionality of each analog block will be described. Simulations were performed
for each analog component in order to report typical electrical characteristics such as gain, power
consumption, bandwidth, impedance, noise and stability. Design considerations and parasitic
components influences are exposed in order to verify their impact on the performances of the analog
design.
3.3 Pre-amplifier design
The analog part of this ASIC is composed of 3 main blocks: pre-amplifier, Photon Counting and TimeOver-Threshold charge measurements. The performances of the pre-amplification stage are
particularly important as they will influence the general characteristics (e.g. noise and speed) of the
whole circuit. In SPACIROC ASIC, the main challenges are to design high-speed and low power preamplifier for reading out the MAPMT anodes. Additionally it should be highly configurable for
correcting the MAPMT anode gain non-uniformity. The pre-amplifier design and electrical
characteristics will be exposed in depth in the following sections.
53
3.3.1 Current conveyor, Gain correction and Signal Distribution
As the ASIC is located nearby the MAPMT, the input signals coming from the Anode are short pulses.
Typically the input signal pulse width is between 3-5 ns (refer to Section 3.3.1.2). The ASIC preamplifier is a current conveyer based on Common Base amplifier. The structure used in this ASIC is
called Super Common Base (SCB) [39]. The advantages of SCB are the following:




Low input impedance (could be much lower than typical Common Base amplifier)
High bandwidth
Low power consumption
Fast Photon Counting capability
These reasons make SCB current conveyor fit perfectly to high counting rate and lower power
applications especially when using the high output impedance detector such as MAPMT.
Figure 3.4 : Block diagram of pre-amplifier signal distribution in SPACIROC.
For correcting the MAPMT gain dispersion, a correction stage consisting of PMOS current mirrors
(PMOS MIRROR – cf. Figure 3.4) is included. This stage offers the correction factor of 0 to 4 for each
channel. Lastly, a set of NMOS current mirrors are used in order to dispatch the input signals to the
Photon Counting or Time-Over-Threshold. For the ease of configuring the ASIC, each output of the
NMOS current mirrors can be selected independently.
3.3.1.1 SCB current conveyor
In this section the electrical simulations of the SCB current conveyor in order to verify its
performances. Additionally its characteristics are compared to the contemporary Common Base
amplifier. The structure of SCB used in SPACIROC is shown below:
54
Figure 3.5 : Super Common Base5 schematic.
In Figure 3.5, Q2 forms the Common Base amplifier. Q1 and Rc, which are in fact a Common Emitter
amplifier (SCB feedback Amplifier), provide a local feedback to Q2 base. The feedback will help to
lower and maintain the input impedance of Q2 during the operations. Additionally, the resistor Ro in
Figure 3.5 could be used to prevent oscillations in certain case but its effect is barely noticeable for
this ASIC. An extra resistance which really has a huge impact in dampening the oscillation could be
placed in series of the input of SCB amplifier. This resistor (known as “protection resistor”) will be
discussed further in this paragraph.
The amplifier formed by Q1 and Rc, has the following gain expression :
|
|
With simulation values, gm1 = 817 µA/V and RC = 70 kΩ:
|
|
|
|
For this amplifier, the dominant pole will be seen at the Rc node. This is due to Rc which has relatively
high values and also to stray capacitance (Cp) which comes from Q1 and Q2. Therefore the frequency
response of the SCB feedback amplifier is the following:
(
) (3.1)
5
The CMOS counterpart of Super Common Base is known as Regulated Cascode [44]. The advantage of using
Bipolar transistors instead of CMOS is the higher intrinsic gain which makes it suitable for low power
application.
55
The dominant pole for this SBC feedback amplifier is:
Figure 3.6 : SCB – Feedback Amplifier open loop frequency response.
From Figure 3.6, the low frequency gain is at 35.12 dB which is close to 35.1 dB calculated previously.
The -3dB cutoff frequency, fc, is around 85 MHz. The stray capacitance can be easily calculated with
the following expressions:
With RC = 70 kΩ and fc = 85 MHz
From the Cp values, it is estimated that around 10 fF is from Q2 ( Base-Emitter capacitance, CπQ2) and
the rest is contributed by Q1 (Base-Collector capacitance, CµQ1) .
After checking the gain of the SCB feedback amplifier, A0, it is interesting to see the influence of this
gain on the SCB input impedance. Typically, for a Common Base amplifier, its input impedance equals
to
.
From the general schematic of the SCB (Figure 3.5), the expression of the low frequency input
impedance (Rin) is the following:
56
From the simulations results , the input impedance can be calculated by using the following values:
With R0 = 100 Ω, gm2 = 200 µA/V, gm1 = 817 µA/V, Rc = 70 kΩ
It is interesting to note that A0 helps reducing the input impedance without a huge penalty on the
power consumption. When comparing to Common Base amplifier, we will need nearly 80 times more
Collector current in order to achieve the input impedance within the same range of the SCB
configuration in this ASIC.
This value of Rin can be verified by simulations:
Figure 3.7: SPACIROC input impedance. The low frequency impedance is around 92.87 Ω.
In addition to Rin, 40 Ω resistor is also used as a protection in this ASIC. So it brings the low frequency
input impedance to 130 Ω.
From Figure 3.7, input impedance exhibits its imaginary part starting from 10 MHz. This is one of the
drawbacks of the SCB amplifier where the input impedance depends on the frequency response of its
feedback amplifier. As opposed to the Common Base amplifier which is typically having higher
frequency response for its input impedance.
When including the gain expression of the SCB feedback amplifier (3.1), the frequency response of
the input Zin can be investigated. For the following calculations the influence of the stray and
detector capacitance is ignored.
57
(3.2)
From the expression of Zin, it is clear that the input impedance is inversely proportional to the SCB
feedback amplifier gain. Therefore, the zero of Zin is provided by of the SCB feedback amplifier.
The following simulations show the influence of SCB feedback amplifier on the input impedance.
Figure 3.8: SPACIROC input impedance vs. SCB feedback amplifier gain.
From the expression of Zin, we can assimilate the previously calculated expression (3.2) to a non-ideal
inductance6 (Leq) with parasitic resistance (Rin). Leq and Rin are the following:
From the simulations values, Rin = 90 Ω and Leq yields the following value:
Since gm2 = 200 µA/V, gm1 = 817 µA/V. Cp = 27 fF
6
The inductance behavior of Super Common Base or Regulated Cascode can be used as a replacement of
passive on die inductor for telecommunication amplifier. This option is attractive as it usually requires less
silicon surface than traditional passif inductor.
58
The simulations in Figure 3.7 have shown that the input impedance behaves like a second order
transfer function. This behaviour could be verified when including the total capacitance (Ct) seen at
the input of the SCB to the expression of Zin. Ct is the sum of the detector capacitance (Cd) and stray
Fcapacitance of the SCB (Cstray) seen at the input.
Figure 3.9 : SCB input impedance equivalent schematic and 40 Ω protection resistor.
The new expression of Zin is the following:
)‖
(
(
)
|
(
|
)
(
)
From the literature we can easily define the quality factor (Q), the resonance frequency (fres) and the
maximum impedance frequency (fm) :
√
√
√
(3.3)
Eventually the value of Zin will peak at different frequencies when Ct varies. The Ct values depend
largely on the detector capacitance (Cd). The MAPMT itself has reasonably low capacitance value
59
which is around ~1.5 pF. However when considering the connectivity and PCB routing, the value of Cd
could variy from 5 pF to 20 pF. Below is the simulation of Zin with respect to different values of Cd.
Figure 3.10 : SPACIROC input impedance Zin vs detector capacitance Cd.
When Ct is at the minimum value i.e. equal to Cstray, we can assume from (3.3) that fm ≈ fres due to the
fact that the quality factor Q tends to be relatively high. Cstray should be the Base-Emitter capacitance
of Q1 which is in order of tenths of fF.
From the simulations values: fm = 1.9 GHz and Leq = 165 nH , Cstray yields the following value:
From simulations, the calculated stray capacitance corresponds to the Base-Emitter capacitance of
Q1. The following table summarizes the maximum value of Zin , fres and Q depending on the values of
Ct :
Ct
Max Zin
fm
1.812.e3
Ω
32fF(≈Cstray)
1.9 GHz
363 Ω
5pF(≈Cd)
150 MHz
231 Ω
10pF(≈Cd)
102 MHz
147 Ω
20pF(≈Cd)
67 MHz
Table 3.1 : Summary of maximum Zin, fm and Q vs Ct.
Q
22
2
1.4
1
As the MAPMT input pulses have relatively fast rise/fall time (a few ns), it is interesting to verify the
signal settling time of SCB. A 100 µA step current is applied and the voltage “ringing” at the input of
SCB can be seen directly on the output current (Iout) (see Figure 3.11).
60
Figure 3.11 : SBC output current (Iout) step response vs detector capacitance Cd. Without 40 Ω
protection resistance (top), with 40 Ω (bottom).
The 40 Ω protection resistance which was cited previously, is particularly useful in order to dampen
the “ringing” of the SBC output current (Iout) within the expected range of Cd. Figure 3.11 is showing
the output current of the SBC to a step input and the influence of the protection resistance. The
quality factor, Q, will be lower than the calculated values (Table 3.1) when Rin is increased by 40 Ω.
As an example, for Cd = 20 pF, the quality factor is reduced to 0.7 which is approaching a critically
damped system (Q = 0.5). However by increasing the Rin, it will reduce input oscillations but at the
expense of the series noise and input current rise time.
As the SCB acts as a current conveyer, it is interesting to calculate its current gain. Like the Common
Base amplifier, the SCB current has a unity gain at lower frequency. The frequency response of the
current gain is the following (first order approximation):
(
)
The low frequency current gain is the following:
From simulations data : gm1 = 817 µA/V, Rc = 70 kΩ
The dominant pole of the SCB current gain will be the following:
61
In the case where Ct depends only on Cstray, ωiscb will be dominated by Cp and gm2. The -3dB cutoff
frequency, fiscb, can be calculated by the following:
(3.4)
With
and
.
Otherwise Ct will be dominated by the detector capacitance, Cd.
The bode diagram of SCB current gain is shown in Figure 3.12.
Figure 3.12 : Super Common Base current gain (unity DC gain). The bandwidth is around 1.784 GHz.
From Figure 3.12, the cutoff frequency found at -3dB, is equal to 1.784 GHz which is slightly higher
than the calculated value in (3.4). This is because the bandwidth extension due to zero (given by
)
is also simulated in the results represented on Figure 3.12.
62
Figure 3.13 : Super Common Base voltage gain . The DC gain is around 40.27 dB and the bandwidth is
around 37.78 MHz.
Additionally, it is also interesting to check the voltage gain of SCB. The voltage gain is slightly bigger
than the one of Common Base amplifier due to the presence of the feedback circuit. The contribution
of the DC gain of the feedback is noted A0 and was calculated in (3.1). By assuming there is a load (RL)
at the output of the SCB, the low frequency voltage gain expression is the following:
In our case, RL is a “diode connected” PMOS transistor which serves as the reference current source
for the following PMOS current mirrors. By including our load and A0 gain, the voltage gain yields the
following equations:
(
)
(3.4)
Simulations data: gm2 = 200 µA/V, gm1=817 µA/V, Rc = 70 kΩ, (gm+gds)Tload = 105 µA/V
Then the DC voltage gain is the following:
The simulated low frequency gain in Figure 3.13 is in good agreement with the calculated value. The
frequency response of SCB gain depends on the capacitance at output (CL) of the SCB (Q2 Emitter
node). In the case of PMOS transistors load, CL could be dominated by the Gate-Source (Cgs) and
63
Gate-Drain (Cds) capacitances if the transistor size is significant enough. The expression of SCB
voltage gain frequency response (first order approximation) is the following:
(
)
(
)
The cutoff frequency at -3dB can be defined as below:
(
)
In Figure 3.13, the voltage gain simulations were done for PMOS mirrors (for MAPMT gain correction)
transistor load. In total there are 14 transistors when including the master source and the mirrors.
The cutoff frequency from simulations (Figure 3.13) is at 37.8 MHz.
The size of the diode connected transistor and the PMOS mirrors are the following:

Total Size:
( )

|| ( )
|| ( )
|| ( )
|| ( )
Simulated cutoff frequency : fvscb = 37.8 MHz
The cutoff frequency is mainly dominated by RL and CL. The equivalent output capacitance of SCB can
be extracted from the following expressions:
(
)
Calculated value of the expression of CL is the following :
(3.5)
With simulations data: RL = 9.5 kΩ, fvscb = 37.8 MHz, Rc = 70 kΩ, Cp = 27 fF
The calculated value of CL should be the sum of Cgs and Cgd for all the transistors of the gain
correction module. All the transistors can be assimilated to 10 transistors of
. For each
device, Cgs + Cgd ≈ 22 fF, this brings the CL least to 220 fF. For the following, CL is assume to be equal
to (3.5) evaluation which is CL = 240 fF.
The transfer function (1st order approximation) of SCB transimpedance can be expressed by the
following:
(
With
)(
)
(
) (3.6)
and
Typically the transfer function frequency response is dominated by
SBC output. The cutoff frequency is given by the following:
which is the pole at the
64
From the values of RL and CL found in (3.4) and (3.5), we have fSCB ≈ 67 MHz.
Figure 3.14 : Super Common Base Transfer function AC sweep. The transimpedance is around 9.6 kΩ.
From the AC sweep in Figure 3.14, the transimpedance value is as expected equal to
(
)
. The pole is found at fc = 58.35 MHz which is slightly lower than the estimated values
of fSCB. The difference comes from the fact that there is also a contribution coming from the stray
capacitance at the input of SCB which was not taken into account.
The following table summarizes the comparison of the characteristics between Common Base and
SCB amplifier :
Common Base
SCB
Current Gain
Voltage Gain
Input Impedance
(
)
Output Impedance
Table 3.2 : Summary of the comparison between Common Base and SCB amplifier.
Conclusion
From different studies shown in this section, the SCB structure is particularly interesting for high
speed and low power consumption current pre-amplifier. This wideband amplifier’s input impedance
is particularly low thus making it suitable for matching with a current source input such as the
MAPMT anodes. We will see later that it has reasonable noise performances which making this
structure is suitable for high-speed and low power consumption chip like SPACIROC.
65
3.3.1.2 Gain Correction
The current unity gain of SCB means that, a gain adjustment module is needed especially for
correcting the MAPMT gain dispersions. The output of the SCB is connected to a PMOS transistor
which becomes the master current source for the gain adjustment block.
The gain adjustment is done by using a network of switches and binary scaled PMOS current mirrors
as shown in Figure 3.15:
Figure 3.15 : PMOS current mirrors gain adjustment schematic.
These current mirrors offer the current multiplication factor from 0 to 3.984. The typical cascode
current mirrors are used in this block and the layout has been carefully done in order to keep a good
uniformity in current copies. The output of the PMOS current mirrors is fed into NMOS current
mirrors in order to dispatch the input pulses to different analog blocks of this ASIC.
For JEM-EUSO experiment, the MAPMT will mostly operate in single photoelectron mode as the light
source from Extensive Air Shower (EAS) is quite low. In single photoelectron mode, the MAPMT
anodes will deliver clearly separated current pulses. Typically the current pulses are short, around 4
ns wide. It can be illustrated by the following figure:
Figure 3.16 : MAPMT Anode pulses. Equivalent charge,
.
The nominal gain for the MAPMT is set at 1.106 which results 1 p.e equals to 160 fC. This will yield the
peak current,
for a 4 ns wide pulse.
The SCB pre-amplifier is simulated according to the input pulse, with a charge (Qin) varying from
0.053 to 1.92 pC (1/3 - 12 p.e). The simulations are shown in Figure 3.17.
66
Figure 3.17 : Simulation of SBC output current. Input charges, Qin = 1/3 - 12 p.e.
The linearity of the SCB pre-amplifier and PMOS mirror gain correction is also checked. The PMOS
mirror ratio (which is also called pre-amplifier gain in this ASIC) is set at 1. It is shown in the following:
Figure 3.18 : SBC (dashed blue plot) output current & PMOS mirror gain correction (solid light blue
plot) linearity. The peak currents of the original input charges, Qin, are represented in pink plot.
The SCB shows quite good linearity since it can maintain the non-linearity less than 4% up to 12 p.e.
On the other hand, the PMOS current mirror performances are less flattering than the SCB as it starts
to saturate from 2 p.e. However these performances are a result of the following trade-offs:
67



Photon counting operates between 1-2 p.e. Thus it doesn’t need a very high linearity.
Limited power consumption.
Flexibility in MAPMT gain compensation as PMOS mirror offers 256 values (8-bit) for each
channel.
3.3.1.3 Pre-amplifier noise contributions
In a typical multi stage amplifier system, the noise factor will be dominated mainly by the first stage.
This is especially true if the first amplification stage exhibits a large voltage gain and the noise
sources are uncorrelated. In our case, the noise studies will mainly concern the SBC pre-amplifier
stage.
Si
N1,A1
So
N2,A2
Figure 3.19 : Cascade amplifier noise.
By checking Figure 3.19, the input SNR, is simply equivalent to
. Thus the output SNR is given by the
following:
( )
(
( )
(
)
)
Therefore in a multi stage amplifier, the main noise contributor is the first input stage. This is given
by the condition that the first stage gain is very large.
As the SBC pre-amplifier is the first amplification element in SPACIROC, it is desirable to have a good
noise performance. For the voltage noise source, it will be later shown that the major contributions
come from the SBC pre-amplifier. On the other hand, the current noise sources extend few stages
further. As the SCB has unity current gain.
3.3.1.3.1 Noise sources
Without considering the external noise sources, there are several types of noise sources [40] which
are generated within the IC itself. Below are the most widely considered noise sources which could
be often found in IC:
I.
Thermal Noise
This noise (also known as Johnson or Johnson-Nyquist Noise) is due to thermal agitations of
the electrons and depends on the temperature (T in kelvin). Thermal noise is a white noise
and follows a Gaussian distribution for its amplitude. It is a widely known physics phenomena
and is present in any resistive material. Thermal Noise is expressed by the following:
68
̅̅̅
Where Δf is the bandwidth, R is the equivalent resistor, k is the Boltzman constant and 4kT
= 1.66.10-20 (at room temperature). Thus the Thermal Noise tends to 0, when T drops to 0.
Therefore, cooling an electronic system will yield better noise performance.
II.
Shot Noise
Shot noise is present in devices built from P-N junction such as diode and bipolar transistor.
When the junction is forward biased, a current flowing in the junction, Io, can be observed. Io
is in fact the average current flowing through the junction as it results from a series of
charged carriers crossing (non-continuously) the potential barrier of the junction. The
random events of the charged carriers crossing the junction barrier contribute to the
phenomenon called “shot noise”. Statistically speaking the fluctuation of the flowing current
inside the junction can be expressed by the following spectral density:
̅
Where Δf is the bandwidth and q is the carrier (electron) charge = 1.6.10-19 C. The shot noise
is also a white noise and its amplitude distribution is Gaussian.
III.
Flicker Noise ( noise)
Also known as Pink Noise, Flicker Noise has empirical origin and is present in all active
devices. Some of the usually cited sources of the Flicker Noise are the crystal defects and
parasitic carrier generation and recombination due to the transistor base current. Typically
this noise is often associated with a constant current, I, as shown in the equation of the
spectral density:
̅
Where Δf is the bandwidth, K1 is a constant of a particular device, a is a constant between 0.5
to 2 and b is constant ~1. As opposed to the 2 previously cited noise, the amplitude
distribution of Flicker Noise is non-Gaussian. In addition this noise is much more present in a
certain region of frequency (mainly low frequency as Flicker Noise ~ ). Therefore, this noise is
an excess noise type.
There are several more types of noise such as Burst Noise, Avalanche Noises etc. However for
simplification reasons and they are also less dominant, these kinds of noise are often discarded from
noise performance calculations.
SPACIROC is developed by using a BiCMOS process, therefore the noise sources from CMOS and
Heterojunction Bipolar Transistors (HBT) have to be considered. For CMOS transistor, the noise
sources are shown in the following figure (Figure 3.20):
69
Figure 3.20 : CMOS noise sources.
By taking into account the previously cited noise source, the noise source of a CMOS transistor are
the following:
1.
̅̅̅̅
With IG = gate leakage current and q is the electron charge.
2.
̅̅̅̅
(
)
-11
With K=1.5.10
(PMOS) or 2.7.10-11 (NMOS), a=1,ID=drain bias current.
The noise sources of HBT transistor are shown in Figure 3.21:
Figure 3.21 : HBT noise sources.
Where :
1. ̅̅̅̅̅
With rb=transistor base resistance.
2.
̅̅̅̅
With K=device constant, a=constant between 0.5 to 2,IB=base bias current. For AMS 0.35 µm
SiGe HBT process, K = 8.7.10-11 and a = 1.682.
70
3. ̅̅̅̅
With IC=collector bias current
From Figure 3.21, rπ and ro are represented without any noise source. Both are virtual resistors, thus
don’t generate noise.
3.3.1.3.2 Amplifier noise analysis
Typically when analyzing noise sources within an amplifier, we would like to observe the noise
behaviour at the output of the amplifier. One of the easiest ways to proceed is by referring all the
noise generators to the amplifier input as the known sources before applying it to the transfer
function of the amplifier itself. The following figure is showing the equivalent noise sources at the
input of amplifier.
Figure 3.22 : Transformation of Noisy amplifier (left) into Noiseless amplifier (right).
In Figure 3.22 the input noise spectral density,
, is composed of a current noise generator
(
) and a voltage noise generator (
). Both noise generators,
and
, are also respectively
known as “parallel” and “series” noise contribution.
is the impedance seen at the input of the
device which is normally dominated by the detector impedance. In the case of MAPMT as a detector,
its impedance is mainly capacitive ( ) and it will be much higher than the stray capacitance found at
the input of the ASIC. The expression of
is the following:
From Figure 3.22, the output noise spectrum is given by the following equations:
|
In SPACIROC,
|
is the transfer function of the SCB pre-amplifier, given by equation (3.6).
Therefore the equivalent output noise spectral density is given by
(
With |
)(
|
|
:
)
|
71
In order to obtain the noise RMS value at the output of the SCB, the output noise spectral density has
to be examined on the whole frequency range by integrating it:
∫
∫
3.3.1.3.3 SCB noise contributions
To determine the equivalent input noise spectral density
, each component in SCB has to be
investigated for the noise contribution. The noise generators of SCB are shown in the following figure:
Figure 3.23 : SCB noise sources.
For the following, the flicker noise is omitted from the calculation and RC is considered noiseless.
Moreover, to simplify the calculation, the HBT transistor noise sources are referred to the Base the
bipolar transistor. It yields the following noise generators:
(
)
Where q is the electron charge, ib = Base bias current, rb = Base spread resistance and gmHBT =
transistor transconductance.
72
For both HBT transistors:
Q1:
⁄
(
With
⁄
)
,
and
Q2:
⁄
(
With
⁄
)
,
and
From Figure 3.23, Q1 noise generators are referred directly to the input and are the principal sources
of the series noise. On the other hand, Q2 contributes directly to a small portion of parallel noise by
its current noise source (
). The voltage noise source (
) will be simply referred to the input
via the SCB feedback amplifier formed by Q1 and Rc.
For the other CMOS transistors of SCB, the principal noise generator is the thermal noise:
MN0:
⁄
With
MP0:
⁄
With
The thermal noise of MN0 is referred directly to the parallel noise at the input. The same scenario is
also valid for the thermal noise of MP0 as the current gain between the Collector and the Emitter
node is approximately 1 (
).
The total parallel noise at the input of SCB is the following:
⁄
⁄√
(3.7)
73
The series noise of SCB is calculated below:
⁄
Where
is the gain for the SCB feedback amplifier (Q1 and RC).
⁄√
(3.8)
From the results it is interesting to note that Q1 is by far the largest series noise contributor.
Therefore careful dimensioning is needed for the transistor in order to minimize the Base resistance
which is the principal source of the series noise. The transistor Q2 noise contributions are practically
negligible but its unity current gain will make that the input parallel noise will start to increase
whenever the SCB output is connected to another device.
We will see in the following sections that the contribution of the second stage of the pre-amplifier is
not negligible for the parallel noise. The values from (3.7) and (3.8) are verified by simulation in the
following figures:
Figure 3.24 : SCB Equivalent Input Noise – Parallel Noise Floor (
).
⁄√
.
74
Figure 3.25 : SCB Equivalent Input Noise – Series Noise Floor (
).
⁄√ ) and series (
The simulation values for the parallel (
are in agreement with the calculated values in (3.7) and (3.8).
⁄√
.
⁄√
) noise
After identifying the noise source of SCB, the equivalent output noise of SCB can be evaluated. It is
particularly interesting to note the output noise density spectral variation with respect to the
detector capacitance (Cd). The following figure shows the simulation of the equivalent output noise
of SCB:
Figure 3.26 : SBC Equivalent Output Noise density spectral vs detector capacitance (Cd).
Typically when the detector capacitance is not included in the simulation, the contribution of the
series noise is negligible. This is due to the fact that the stray capacitance seen at the input of SCB is
very small (~41 fF). However when the detector capacitance goes up to 20 pF, the RMS noise at SCB
output is also starting to increase rapidly as a result of series noise influence.
75
Below is the table of simulated RMS noise of SCB and the SNR of 1 p.e input. 1 p.e input charge gives
177 mV (without loading) at the SCB output:
Detector Capacitance (Cd)
RMS noise
1p.e Max Amp
SNR
Stray Capacitance ~50 fF
0.145 mV
177 mV
1221
5 pF
1.145 mV
188 mV
164
10 pF
1.502 mV
181 mV
121
20 pF
1.856 mV
155 mV
84
Table 3.3 : Summary of SCB pre-amplifier SNR vs Detector Capacitance ( ).
3.3.1.3.4 Second stage noise contributions
As stated previously, the parallel noise could be increased by other stages of pre-amplification.
Therefore it has to be investigated. The noise generators from the following stage of the SCB are
represented below:
Figure 3.27 : SPACIROC pre-amplifier noise sources. The first stage (SCB amplifier) is highlighted in
dashed cyan box.
From Figure 3.27, only current noise sources are considered as any current noise at the output of the
SCB will be seen directly to the input. The voltage noise sources are neglected as the voltage gain of
SCB is theoretically very high (>100) and it would be negligible if referred to the input.
The closest noise generators which are connected to the SCB are coming from the PMOS MIRROR
gain correction. For simplification only one active device is considered and the current copying ratio
is one. The NMOS transistors which are used to distribute the signals also have a unity current
copying ratio:
MP1:
⁄
With
76
MN1:
⁄
With
MN2:
⁄
With
Noise of MP1 is referred to the input of the SBC because of the unity current ratio. For the same
reason, MN1 and MN2 also contribute to the input parallel noise. In Figure 3.27, there is an
additional stage which is used to generate the pre-amplifier voltage signal in order to discriminate it
(cf. Section 3.4.1 – Pre-amplifier Trigger). This output stage also contributes to the input parallel
noise:
Rpa:
⁄
With
MP2:
⁄
With
MN3:
⁄
With
By taking into account the parallel noise which was calculated for SCB (3.7), the total parallel noise is
the following:
⁄
⁄
⁄√
77
By including the other stages connected to the SCB, the total parallel noise nearly doubles the value
calculated for SCB. Below is the simulation for the total input noise:
Figure 3.28 : Pre-amplifier Equivalent Input Noise – Parallel Noise Floor (
).
⁄√
Figure 3.29 : Pre-amplifier Equivalent Output Noise density spectral vs Detector Capacitance (Cd).
Below is the table summarizing the noise performance of the pre-amplifier:
Detector Capacitance (Cd)
RMS noise
1p.e Max Amp
SNR
Stray Capacitance ~50 fF
0.708 mV
622 mV
879
5 pF
1.301 mV
651 mV
500
10 pF
2.044 mV
641 mV
314
20 pF
3.019 mV
557 mV
184
Table 3.4 : Summary of pre-amplifier output SNR vs Detector Capacitance ( ).
78
Summary
In general the noise measurement in physics detector is expressed with the number of electrons
(
) or equivalent noise charge (ENC) [40]. This can be done by determining the
number of electrons needed which could yield the same RMS noise at the device output. By
definition, ENC is given by the following expression:
⁄
Where
is the input charge,
is the output RMS noise and
is the output amplitude.
Essentially the measurement is done after processing the pre-amplifier signal by using a shaper for
example. Below is the summary of the ENC simulations for SPACIROC pre-amplifier by using a CRRC2 shaper. The time constant of the shaper (τ) is set at 10 ns and the total charge injected is 106
(1 p.e for MAPMT gain of 106 ).
Detector Capacitance (Cd)
ENC
Stray Capacitance ~50 fF
2082
5 pF
2482
10 pF
3312
20 pF
5366
Table 3.5 : Summary of pre-amplifier ENC vs Detector Capacitance (
).
From Table 3.5, it is shown that ENC increases proportionally with the Detector Capacitance. It is
understandable as the series noise increases according to
and the CR-CR2 is set to a low time
constant. This basically means that in a fast counting application, the Detector Capacitance has to be
kept as minimum as possible. Therefore it has to be kept in mind when designing the front-end board
using this ASIC.
79
3.4 Photon Counting
The 64-channel Photon Counting analog block receives the input coming from the pre-amplifier. The
purpose of the Photon Counting is to generate discriminator output (also called trigger) which is sent
to the digital block for digitization. The leading edge of the discriminator output clocks the digital
counters that enable the ASIC to count the arrival photons. The discriminator output pulse length
must be kept as short as possible in order to maximize the counting rate and Photon Counting time
resolution. The figure below shows the signal flow in Photon Counting:
Figure 3.30 : Signal flow in Photon Counting.
For this part, all the outputs are typical application of pre-amplifier, shaper and discriminator for
triggering.
In SPACIROC, there are 3 different Trigger outputs available that can be selected via a multiplexer.
These trigger outputs can be seen in Figure 3.31 which shows the block diagram of one Photon
Counting channel.
Figure 3.31 : Photon Counting channel. The block diagrams show the selection of the different trigger
available.
80
The following trigger outputs are available on this ASIC:
1) Pre-amplifier Trigger (Trig_PA) :
The trigger is obtained directly from the pre-amplifier signal. Conversion from current
to voltage is done via a 30 kΩ resistance.
2) FSU Trigger (Trig_FSU) :
Signal amplification and shaping are done by using a transimpedance amplifier with
variable gain and shaping time.
3) VFS Trigger (Trig_VFS):
A transimpedance amplifier is also used for this trigger in order to amplify and to
shape the pre-amplifier signal. This shaper is based on shunt feedback common
emitter amplifier.
In the following sections, the simulations of each proposed trigger are done in schematics and postlayout (Extracted Parasitics) in order to validate the theoretical studies. The pre-amplifier is set at
unity gain except for certain cases. The equivalent Detector Capacitance seen at the ASIC input is
approximated at 10 pF. The input pulse is as specified in Figure 3.16.
3.4.1 Photon Counting – Pre-amplifier Trigger (Trig_PA)
The motivation behind this trigger design was to obtain a fast single photon counting performance
while maintaining low power consumption. Power consumption can be reduced as the triggering
chain is composed only by the following components: a pre-amplifier and a discriminator. As the preamplifier is a current conveyer, a resistance (30 kΩ) is used to convert the current to a voltage pulse.
Additionally, an operational transimpedance amplifier (OTA) is mounted in follower configuration in
order to set the DC level at the input of the discriminator and to offset the DC current coming from
the pre-amplifier. The structure of Pre-amplifier Trigger is shown in the following figure (Figure 3.32):
Figure 3.32 : Pre-amplifier Trigger (Trig_PA).
As this trigger structure doesn’t need any additional amplifier or shaper, the pre-amplifier output
exhibits the lowest RMS noise compared to the other triggering structures available on this ASIC.
However the lack of an additional gain stage could be penalising for the minimum detectable input.
81
The other drawback of this structure, is the time occupancy which depends greatly on the resistance
value used for the current to voltage conversion and the stray capacitances of the layout. For an ASIC
with big silicon area this could be an issue.
The first order approximation transfer function of the pre-amplifier trigger can be expressed by the
following:
Where
is the pre-amplifier load and
is the stray capacitance found at output.
is the equivalent impedance of the OTA output transistor and the 30 kΩ load transistor. It yields
the following value:
||
With
The simulations are shown in the following figures. The gain correction is set to 1 in order to have a
unity current gain. The input signal is assumed to be as a fast MAPMT input and a 4 ns triangular
pulse width, as shown in Figure 3.16 :
Figure 3.33 : Pre-amplifier output. Schematic simulations (Upper plots). Extracted Parasitics
simulations(Lower plots).
82
As shown in Figure 3.33, the risetime is considerably higher for the Extracted Parasitics simulations.
This is partly due to the unbuffered output of the pre-amplifier and the loading effects of the
parasitic capacitances of the layout and signal routing. It is estimated to be around 400 fF due to the
signal routing. Naturally this parasitic capacitance will increase the time occupancy of the preamplifier output and limits the Double Pulse Resolution.
The 2.5 V DC level of the pre-amplifier output is set by a bandgap voltage reference. The threshold
for the discriminator is set at 20 mV (corresponds to roughly 20 fC) below the DC level by a 10-bit
DAC. Figure 3.34 is showing the trigger simulations:
Figure 3.34 : Pre-amplifier output. Schematic simulations (Up). Extracted Parasitics simulations
(bottom).
From the simulation of Figure 3.34, the timewalk between 1/3 p.e and 2 p.e response increased from
3 ns for schematic simulations to 6ns for Extracted Parasitics simulations. This comes from the fact
that the time occupancy is increased when all the parasitic capacitances are taken into account.
The linearity of the pre-amplifier output is shown in the following figure:
83
Figure 3.35 : Pre-amplifier output linearity. Schematic simulations (Purple). Extracted Parasitics
simulations (Blue).
The Pre-amplifier Trigger output starts to saturate around 2 p.e of input charge. This is similar to the
saturation found for the gain correction stage (Section 3.3.1.2).
Here is the summary of the performance of Pre-amplifier Trigger (unity gain and detector
capacitance = 10 pF):
Parameter
Values - Schematic
Values - Extracted
Transimpedance
80 dBΩ
Bandwith
31 MHz
19 MHz
Double Pulse
26 ns
36 ns
Resolution (1 p.e)
Timewalk (1/3 -2 p.e)
3 ns
6 ns
Gain
1.8 mV/fC
1 mV/fC
SNR(1 p.e)
483
443
Power Consumption
0.23 mW
Table 3.6 : Summary of Pre-amplifier Trigger characteristics.
84
3.4.2 Photon Counting – FSU Trigger (Trig_FSU)
This triggering scheme is classical structure where a pre-amplifier, a shaper and a discriminator are
employed to produce photon triggered pulse. The following figure shows the triggering scheme:
Figure 3.36 : FSU Trigger (Trig_FSU).
The shaper used here is called Fast Shaper Unipolar (FSU7) which was used in MAROC [41] chips. It
will be described in the following section.
3.4.2.1 FSU Shaper
For the fast triggering channel, a transimpedance amplifier (known as FSU) is used for shaping the
pre-amplifier signal. In previous ASICs such as OperaRoc [42], a CRRC2 shaper with differential input
has been used for the fast triggering channel. However when it is required to go for a faster counting
rate (e.g. > 10 MHz), we were starting to meet the hurdles such as design limitation and power
consumption. Redesigning the shaper in single ended configuration seems to be a better idea as it
could achieve better signal time occupancy and of course lower power consumption. Below is the
general block diagram of the shaper.
7
FSU stands for Fast Shaper Unipolar. Although FSU structure is more widely known as charge amplifier, it is still
a shaper.
85
Figure 3.37 : FSU Shaper general architecture.
The amplifier used in this structure is a typical common emitter amplifier with active cascode PMOS
load followed by a common source amplifier [43]. The general schematic of the shaper is shown in
Figure 3.38. The DC open loop gain of
, expression is the following:
||
||
With
(
,
||
)
,
,
and
The core amplifier exhibits a dominant pole (
) at a frequency of 395 kHz due to the input
capacitance (
) of the common source follower transistor. The output load capacitance, ,
introduces a secondary pole (
) to the core amplifier. If the value of
enough, it will start to limit the gain-bandwidth product (GBW) of
have an impact on the stability of the amplifier.
is significant
. This effect will indirectly
86
Figure 3.38 : FSU Shaper schematic.
The transfer function of FSU can be expressed as followed:
⁄
Where represents the feedback impedance,
the stray capacitance at the input and
the
st
1 order open loop gain of the core amplifier. The bandwidth of
is around 395 kHz.
can be simplified to become the following expression:
From the simplified expression of
,
can be identified as the feedback factor of the
transimpedance amplifier. It can be expressed as followed:
⁄
According to Nyquist stability criterion8, the Loop Gain (LG) =
, must have sufficient phase
margin when the LG is approaching 1 in order to avoid oscillations. Basically this criterion can be
checked graphically by inspecting the intersection of
and
. Let’s inspect the case where
only. In this case the feedback factor is the following:
8
From Nyquist stability criterion, a phase margin of 45° is considered as stable. Typically for transimpedance
amplifier it is preferable to reach at least a phase margin of 67° in order avoid a noticeable ringing of the
amplifier output response.
87
With
and
.
From Figure 3.39 which represents the Open Loop gain and the feedback factor, the intersection
point when
is at the frequency f = 218.6 MHz which corresponds to the GBW of LG.
The feedback factor is a 1st order transfer function which introduces a pole (
) at 40 MHz. In
addition to the 90° phase shift due to the pole
of the open loop gain, the feedback factor could
add potentially another 90° phase shift for the LG phase. In total, LG could have nearly 0° of phase
margin which means that the transimpedance feedback amplifier could have a self sustaining
oscillation.
Figure 3.39 : Open Loop Gain and Feedback Factor Intersection for
.
In Figure 3.40, the phase margin of the loop gain for the case
is around 8°. Therefore to
increase the stability, we could shift the pole
to a higher frequency by reducing the feedback
resistance, . For estimation, if
, it could yield a phase margin of 45°. However it is not
satisfying enough as the phase margin will surely be reduced by the variation of
. Furthermore
reducing the will also reduce the output dynamic.
There is another technique which could help to sustain the performance of the Loop Gain while
having a reasonable phase margin. By adding a feedback capacitor, , a zero will be introduced in
the Feedback Factor. This zero will compensate the 90° phase shift introduced by the
of the
Feedback Factor. The new transfer function of
is the following, with
||
:
88
Figure 3.40 : FSU Loop Gain and phase margin for
.
In Figure 3.41, the feedback capacitance
will add a zero around the frequency of 60 MHz.
From the same figure, we can observe that the 20 dB/dec slope of
is crossing a flat region of
at the intersection frequency of 426 MHz. This is a graphical indication of the stability of
the Loop Gain. By checking the Loop Gain GBW in Figure 3.42, the phase margin in this configuration
yields a value of 70° which is quite reasonable.
Figure 3.41 : Open Loop Gain and Feedback Factor Intersection for
and
.
89
Figure 3.42 : FSU Loop Gain and phase margin for
and
.
To set the DC level and also cancel the input DC current, an OTA is used and mounted in parallel to
the amplifier feedback impedance. In order not to interfere the core amplifier feedback impedance,
the OTA equivalent impedance should behave like an inductance at high frequencies. This
requirement implies that we just need a very “slow” OTA which will produce a huge equivalent
impedance (
) in high frequencies. Thus the OTA can be operated at a very low power which is
suitable for a power limited application.
The simple OTA schematic is shown in the following figure:
Figure 3.43 : FSU OTA schematic.
By setting the dominant pole at the output transistor (M4), the OTA transconductance can be
expressed as the following:
90
This gives the equivalent impedance of the OTA:
With the low biasing of 15 µA and
, the following values of
and
can be
achieved:
The simulation of the OTA equivalent impedance is shown in the following figure:
Figure 3.44 : FSU OTA equivalent impedance,
, simulation.
At low frequency, the equivalent impedance is around 10 Ω and it rises gradually according to the
frequency. Around 100 kHz,
introduces a zero to the transimpedance of the FSU and
is
quite large (~1 MΩ) to be negligible from equivalent transimpedance. This behavior will also allow a
better selectivity in terms of working frequencies of the shaper therefore minimizing the noise. The
effects of
on the impedance can be seen in Figure 3.45.
For high frequency responses, the transfer function of FSU could be rewritten by including the
feedback capacitor,
:
(
(
)
)
91
From the obtained equation of
expressed as the following:
, the quality factor (
) and the resonance frequency ( ) can be
√
√
With the DC open loop gain,
, the transfer function of FSU can be reduced as the following:
With
Figure 3.45 : FSU transimpedance for
and
. Bandwidth Close Loop =53 MHz.
The feedback capacitance influences the bandwith of the transimpedance amplifier and also the rise
time and fall time of the output signal. The rise/fall time can be defined as the time between 10%
and 90% of the output which is roughly around 2.2
. The simulation below is done by injecting a
step input of 5µA for different values of :
92
Figure 3.46 : FSU output for
vs
(black),
(gold) and
(blue).
From the simulations done in Figure 3.46, FSU output rise time is 6.6 ns, 11.6 ns and 23.6 ns for
,
and
respectively. As suggested from the general schematic of FSU, and
can be varied. The flexibility of choosing the values of and helps to tune the phase margin due
to the variation of the input capacitance ( ) and also the load capacitance ( ).
Below is the table resuming the characteristics of FSU.
Parameter
Values
Rise Time
Phase Margin
Bandwidth Close Loop
Transimpedance
Power Consumption
Table 3.7 : Summary of FSU characteristics.
93
3.4.2.2 FSU trigger Simulations
For the simulations done in Figure 3.47, charges of 1 p.e are injected at the input. Simulated
configurations of FSU cover from the fastest (τ_fast = 25 kΩ × 25 fF) to the slowest time constant
(τ_slow = 100 kΩ × 175 fF).
Figure 3.47 : FSU output for 1 p.e input charges. Schematic simulations (left plots) and Extracted
Parasitics simulations (right plots).
Apart from the time occupancy it can be seem that the parasitic capacitance affects the stability of
the shaper. The simulation results are summarised in Table 3.8.
Configuration
Rf
25 kΩ
50 kΩ
100 kΩ
Cf
25 fF
100 fF
175 fF
25 fF
100 fF
175 fF
25 fF
100 fF
175 fF
Max Amplitude
Time occupancy
Extracted
Difference
Schematic
Parasitics
1.595 V
1.555 V
40 mV
10ns
1.506 V
1.469 V
37 mV
21ns
1.417 V
1.385V
32 mV
28ns
1.809 V
1.763 V
46 mV
14ns
1.66 V
1.615 V
45 mV
34ns
1.516 V
1.481 V
35 mV
49ns
1.999 V
1.958 V
41 mV
25ns
1.812 V
1.755 V
57mV
59ns
1.602 V
1.557 V
45 mV
68ns
Table 3.8 : Summary of FSU 1p.e simulations (*Ringing).
Schematic
Extracted
Parasitics
28ns*
24ns
30ns
33ns*
39ns
59ns
24ns
64ns
>68ns
From the table summarising the simulations shown in Figure 3.45, there is some drop of amplitude
between 32-57 mV. Overall the drop of the peak amplitude is less than 10% of the initial data which
is quite good. For the time occupancy, in general, the parasitic capacitances add additional delay
from 2ns -10 ns. For the configuration where it is useful for fast photon counting (e.g. Cf = 25 fF), it is
94
more penalising as noticeable ringing can be observed. For obvious reason, the return to the baseline
is necessary for Photon Counting. If it is not the case the discriminator could discriminate two
different peaks from the analog signal. From the stability analysis, both capacitances at the input and
the output of the shaper can affect its stability. In the case of FSU, the loading capacitance is quite
dominant as the routing path from the shaper to the discriminator is quite long. As the load
capacitance starts to increase, it becomes dominant to the pole of the core amplifier and squeezes
the phase margin of the loop gain. The same observation applies when verifying the quality
factor, , established for the FSU in Section 3.4.2.1. The quality factor will increase when the load
capacitance and the dominant pole start to increase.
For the following the simulations are done for the selected FSU settings which can yield time
occupancy smaller or equal to 30 ns as required by the initial ASIC requirements.
The output of the FSU is shown in the following figures:
Figure 3.48 : FSU (Rf = 25 kΩ and Cf = 175 fF) output for 1/3-2 p.e input charges. Schematic
simulations (left plots) and Extracted Parasitics simulations (right plots).
95
Figure 3.49 : FSU (Rf = 25 kΩ and Cf = 100 fF) output for 1/3-2 p.e input charges. Schematic
simulations (left plots) and Extracted Parasitics simulations (right plots).
The DC level of FSU is set at 1 V. For simulations represented in Figure 3.48 and Figure 3.49, the
threshold level is set at 1.09 V in order to trigger at 1/3 p.e. For the FSU with Rf = 25 kΩ and Cf = 175
fF configuration, the timewalk of 1/3 p.e and 2 p.e is at 2.4 ns and 3.4 ns for Schematics and
Extracted Parasitics simulations respectively. For Rf = 25 kΩ and Cf = 100 fF configuration, the
timewalk between 1/3 p.e and 2 p.e is found at 1.6 ns and 2.1 ns for Schematics and Extracted
Parasitics simulations respectively. For both simulations, the timewalk difference between Schematic
and Extracted Parasitics is less than 1ns. The output buffer of FSU is particularly useful here as it
helps to maintain a reasonable time occupancy, signal amplitude and timewalk against the parasitic
capacitances.
96
Below is the simulation of the RMS noise for selected configurations of FSU.
Figure 3.50 : FSU RMS noise vs Detector Capacitance.
From the simulation results (represented in Figure 3.50), it is shown that the lowest noise
performance can be obtained from Rf = 25 kΩ and Cf = 175 fF which are the lowest resistance and the
highest capacitance value available. This configuration can achieve the lowest RMS noise for 2
reasons. First of all, as stated previously (Section 3.3.1.3), the equivalent output noise density
depends on the transfer function of the noiseless amplifier which is FSU in current case. As the gain
of FSU is set by Rf, the lowest resistance value gives the lowest RMS noise for a given Cf. Obviously Cf
values have also an impact on the RMS noise. The RMS noise is obtained from the integrated
equivalent output noise over the bandwidth of the device. Although ideally the bandwidth would be
infinite, the real bandwidth is capped by Cf in the case of FSU. Thus the larger value of Cf will lower
the bandwidth and eventually the RMS noise.
97
Figure 3.51 : FSU output vs input charges.
From the simulations results in Figure 3.51, FSU characteristics are nearly identical from the
schematic to Extracted Parasitic simulations. The observed saturation around 2 p.e comes mainly
from the limitation of the pre-amplifier stage.
Here is the summary of the performance of this triggering scheme for unity gain pre-amplifier and
detector capacitances equal to 10 pF:
Parameter
Values – Extracted
Parasitics
88–100 dB Ω
8.1–48.7 MHz
7.6–44.3 MHz
Values - Schematic
Transimpedance
Bandwidth
Double Pulse
10–68 ns
24–68 ns
Resolution (1 p.e)
Gain
2.48 – 3.54 mv/fC
2.28 – 3.28 mv/fC
SNR(1 p.e)
145-286
184-318
Power Consumption
0.32 mW
Table 3.9 : Summary of FSU trigger characteristics.
98
3.4.3 Photon Counting – VFS Trigger (Trig_VFS)
For this triggering scheme, another shaper is used here. The shaper is also a transimpedance
amplifier. The motivation of building this block is to provide an alternative to FSU shaper.
Furthermore we wanted to achieve a faster performance while having a smaller power dissipation.
Hence the name given to this shaper which is Very Fast Shaper (VFS). Below is the representation of
this structure:
Figure 3.52 : VFS Trigger (Trig_VFS).
3.4.3.1 VFS shaper
Unlike FSU, this shaper doesn’t include a buffer for the output and the feedback path. By doing so, it
could resolve the voltage headroom problem [43] which could happen in a structure like FSU.
The general schematic of this shaper is the following:
(a)
(b)
Figure 3.53 : VFS general structure (a) and schematic(b).
As shown in Figure 3.53 (a), the general structure of this shaper also integrates an OTA mounted in
parallel to the feedback network. As seen in Section 3.4.2.1, the equivalent impedance of OTA
represents a zero around 100 kHz which will eventually limit the working frequencies of the shaper
between 100 kHz and the bandwidth.
99
By ignoring the effect of the OTA, the open loop gain for the core amplifier,
as below:
With
, can be expressed
and
The dominant pole ( ) is given by the equivalent capacitance at the output of the core amplifier,
and the load resistance, . From the simulations, the open loop gain bandwidth is at 238 MHz,
which yields
. Also from the simulations, the GBW of the core amplifier is at 18.8 GHz.
The transfer function of VFS is the following:
(3.9)
⁄
||
The feedback factor of VFS is the following with
(
(
:
)
)
Figure 3.54 : VFS loop gain (black) and Phase (Green). The Phase Margin is 79°.
100
The stability of VFS stability can be verified directly by checking the phase margin of the LG as shown
in Figure 3.54. For the given
, the phase margin is around 79° which is relatively high.
As VFS core amplifier is connected directly to the output load, it is interesting to check how the
feedback amplifier behaves according to the load capacitance , on top of the loading capacitance
of the OTA which is estimated around 500 fF. Below is the variation of the Phase Margin of VFS as a
function of
and also the input capacitance
:
Figure 3.55 : VFS Phase Margin vs
.
As expected the Phase Margin drops drastically when the output capacitance increases. The Phase
Margin is as low as 45° when
. By increasing , the dominant pole of the core amplifier
is decreased thus compressing its bandwidth. Therefore the Phase Margin will be reduced as well if
the same feedback configuration is still the same. This behaviour could be a limitation when
connecting the amplifier to the next stage.
The oscillations can be observed on transient’s simulations of a step input. It is shown in next figure.
101
Figure 3.56 : VFS Output vs
(top) and
(bottom).
From Figure 3.56, VFS output response to step input exhibits noticeable ringing when
.
Unlike FSU, VFS shaper architecture doesn’t include a buffer which could minimize the interstage
capacitive loading. For this reason, the discriminator of VFS trigger is placed very close to VFS shaper
during the floorplanning of the chip.
By arranging the equation (3.9), the transfer function of VFS can be given as following:
(
with
The resonance frequency is
,
√
)
,
and
√
and the quality factor
.
Again by verifying the quality factor,
, it can be increased by having lower value of the core
amplifier pole
. Of course by increasing the quality factor, the transimpedance amplifier is not
dampened sufficiently thus bringing the oscillations for a step response. Interestingly,
can be
decreased by having a bigger
which acts as the feedback capacitance. This technique which is
applied for FSU (Section 3.4.2.1), will not be applied here as we want to keep the VFS output risetime
as fast as possible. The rise time is given by
.
With
and
.
102
Figure 3.57 : VFS transimpedance for
. Bandwidth Close Loop = 807 MHz.
The simulations plot in Figure 3.57 gives the transimpedance values of 87 dB Ω. The Close Loop
Bandwidth, is given by the first pole of
.
Following is the summary of the VFS performances:
Parameter
Values
Rise Time
Phase Margin
Bandwidth Close Loop
Transimpedance
Power Consumption
Table 3.10 : Summary of VFS characteristics.
103
3.4.3.2 VFS trigger simulations
For VFS, the simulations is done for the 1/3 p.e – 2 p.e by including the whole triggering chain. The
pre-amplifier gain is 1 and typical fast input pulse is applied. The simulation results are shown in
Figure 3.58.
(a)
(b)
Figure 3.58 : VFS analog and discriminator outputs. Pre-amplifier gain = 1. Schematic simulations (a).
Extracted Parasitics simulations (b).
From the schematic simulations (Figure 3.58 (a)), VFS output is showing a drop of amplitude when 2
p.e input charges are applied. The voltage drop is noticeable when the input charges are peaking.
This happens when the input signal amplitude is larger than the biasing point of VFS core amplifier,
where the core amplifier will be simply cut off. If the input signal persists, then VFS output starts to
be clamped down by the output resistance of the core amplifier as most current will flow into that
resistance.
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(a)
(b)
Figure 3.59 : VFS analog and discriminator outputs. Pre-amplifier gain = 0.5. Schematic simulations (a).
Extracted Parasitics simulations (b).
The same input range was simulated with reduced pre-amplifier gain. The pre-amplifier gain is set at
0.5 instead of the usual values of 1. The effect of the VFS output resistance clamping is less visible in
the schematic simulation. For the post-layout simulations, the additional loading capacitance is clear
affected the stability of the VFS amplifier and ringing is visible in Figure 3.58 (b) and Figure 3.59 (b).
This is despite of having placed the discriminator close enough to VFS during the floorplanning.
The linearity of VFS is checked by varying the input charges. As shown previously, the saturation
occurs around 2 p.e due to the pre-amplifier limitations.
Figure 3.60 : VFS output linearity. Pre-amplifier gain=1.
105
The characteristics of VFS trigger are listed in Table 3.11.
Parameter
Values – Extracted
Parasitics
87.7 dB Ω
44.85 MHz
35 MHz
Values - Schematic
Transimpedance
Bandwidth
Double Pulse
18ns
21ns
Resolution (1 p.e)
Gain
3.08 mV/fC
2.83 mV/fC
SNR(1 p.e)
252
327
Power Consumption
0.31 mW
Table 3.11 : Summary of VFS Trigger characteristics.
3.4.4 Conclusion
We have seen that the 3 implemented triggers in Photon Counting module can be used in photon
counting application. Specifically for JEM-EUSO application where the Double Pulse Resolution
should be as high as possible, Trig_FSU is a suitable candidate as this design has a good trade-off
between speed, flexibility and power consumption. Furthermore it is a proven design as it is already
implemented in other chip thus making Trig_FSU is a safe choice. Next, there is Trig_VFS which
employs a newly designed shaper. At least on the paper this trigger design is capable to deliver
better performance in terms of speed when compared to FSU. However it has to be proven in the
laboratory tests. Lastly for a low power application which doesn’t have high requirements on the
timing, Trig_PA could be a very interesting candidate. Table 3.12 summarizes the various
characteristics of each trigger available for Photon Counting.
Parameters
Trig_PA
Trig_FSU
Trig_VFS
Transimpedance
80 dB Ω
88–100 dB Ω
87.7 dB Ω
Bandwidth
19 MHz
7.6–44.3 MHz
35 MHz
Double Pulse
36 ns
24–68 ns
21 ns
Resolution (1 p.e)
Gain
1 mV/fC
2.28 – 3.28 mv/fC
2.83 mV/fC
SNR(1 p.e)
443
184-318
327
Power Consumption
0.23 mW
0.32 mW
0.31 mW
Table 3.12 : Comparison of Photon Counting’s triggers characteristics. The characteristics are taken
from Extracted Parasitics/Post-Layout simulations.
106
3.5 Time-Over-Threshold
The secondary function of this ASIC is to measure the number of photon per GTU via the Time-OverThreshold module. This module, also referred as KI, was developed by ISAS (JAXA) & Konan University.
The development of this module has been done earlier in KI ASICs (KI01-03) [37] produced by both
institutes.
As a part of the JEM-EUSO collaboration work, it has been decided to merge the functionally of the
Photon Counting and the Time-Over-Threshold in the same ASIC. For single photoelectron mode,
Photon Counting is preferred as it gives precisely the number of photoelectron seen per GTU.
However, for the big charge (caused by very energetic showers, TLEs or meteors,…), it is necessary to
have a charge measurement module as Photon Counting will not work in this case. Let’s say if only
one module could be put into the ASIC, the charge measurement module is preferred as it will be
more useful then Photon Counting block.
The philosophy behind this circuit design is to use an array of capacitors to integrate the incoming
charge and measure the duration of the integrated signal which is over a given threshold. To
facilitate the measurements, these capacitors are discharged with a constant current source. This will
also offer a greater possibility to adjust the integrated signal timing.
The purposes of the KI circuit can be divided into 2 main categories:


KI should act as a secondary measurement besides Photon Counting. Ideally it should overlap
with the dynamic range of the Photon Counting module. The dynamic range of the Photon
Counting part is determined by its time resolution and the pileup of the analog signal.
KI will provide the information for the MAPMT protection in case of intense photon flux.
Additionally the KI should also handle different types of input signal:



Random arrival time of the photons and also variation of MAPMT High Voltage Power Supply.
Fluctuations of the number of photons governed by the Poisson distribution.
Pile up which occurs at the MAPMT anode level.
Of course adding to the previously stated requirement, the Time-Over-Threshold part should deliver
reliable data every Gate Time Unit (GTU = 2.5 µs).
The general architecture and the operation of this block are described in the following sections.
3.5.1 General Architecture
The general architecture of the KI is shown in Figure 3.61. The 8 first inputs of the KI come from the
pre-amplifier outputs. The 64-channel pre-amplifier outputs are reorganised into 8 outputs by
summing every 8 neighbouring channels. An additional 9th channel is also included which can be
connected to a MAPMT dynode.
107
Figure 3.61 : KI Time-Over-Threshold general architecture.
Each component in Figure 3.61 is described below:
3.5.1.1 Coarse Current Absorber
As the input of the Time-Over-Threshold comes from the sum of 8 SCB pre-amplifier outputs, there
will be also DC current which will be carried along. The presence of this DC current is due to the
biasing points of the pre-amplifier itself. Therefore DC current has to be removed or it will be
integrated within the Time-Over-Threshold block. The DC current cancellation is done simply with a
set of adjustable current mirror. An OTA is also available as another option which can be used for the
DC current cancellation.
3.5.1.2 Impedance Conversion
As the name suggests, this circuit has a role of impedance matching from the input to the rest of the
KI block. It is another application of Regulated Cascode [44] with a differential amplification stage in
order to achieve low input impedance. The input impedance is set around 70 Ω.
3.5.1.3 Dynamic Range , Current Sink and DC Feedback
It is the core of this charge measurement circuit. This is where the input signals are integrated into
the capacitors and the integration path and the slope are defined. The Dynamic Range (DR) is just a
set of capacitor which can be set from the value of 16 pF to 46 pF. The DC feedback is a switched
voltage reference which provides the DC level of the circuit. Currently the DC level is set at 1.5 V. The
Width Adjust (WA) current source is used to set the discharge slope of the Dynamic Range capacitors.
With the available values of 2 µA to 32 µA, the discharge slope can be theoretically calculated from
the following capacitance discharge equation,
.This will yield a tuneable discharging slope from
43 mV/µs to 2000 mV/µs.
3.5.1.4 Fine Current Absorber
The last part of the KI is used to cancel the incoming DC current with a smaller step compared to
Coarse Current Absorber. Typically incoming DC current could enter circuit and integrated as well by
the DR capacitors. Thus it will adjust the voltage DC level of this KI circuit. Therefore the Fine Current
Absorber will be used to offset this effect.
108
3.5.2 KI operations
The operating phase of this Time-Over-Threshold block depends greatly on the total input charges. It
will be described according to the strength of input signal: small input signal and large input signal.
3.5.2.1 Small Input signal
In this case, the integrated signal amplitude is too small to reach the threshold. The incoming signal is
integrated anyway on the Dynamic Range capacitor. However no trigger output is produced here and
the DC level is maintained. Below is the block diagram in this operation mode:
Figure 3.62 : KI in the case of low input charge. Integrated signal (before the comparator) is shown in
red. No trigger output is produced and it stays at low level or ‘0’.
3.5.2.2 Large Input signal
For this case, the input signal is strong enough to be distinguished by the comparator. To produce a
time variable signal, the operations of this circuit, which are determined by the comparator output
level, are described as following:
1. The comparator output changes from low to high level:
The DC level is cut off by the comparator output and the Current Sink is activated at the same
time. Thus it is leaving a floating point at the Dynamic Range capacitor which will allow it to
integrate totally the input charge without the disturbance of the DC level.
2. Comparator output is high:
The Width Adjust current source will help the discharge of the capacitor by providing a constant
current. This current source helps to have a tuneable discharge slope of the Time-Over-Threshold
analog signal. Basically this operation will define the analog pulse width. As long as the analog
signal is over a given threshold, the comparator will remain at high level.
3. Comparator output changes from high to low level:
Normally the Dynamic Range capacitors are almost fully discharged. The discriminator output
restores the analog signal baseline by setting the DC level again and turning off the Current Sink.
The Dynamic Range capacitor will finish discharging through the DC level voltage divider until the
end.
The block diagram of this mode is shown in the following:
109
Figure 3.63 : KI in the case of large input charge. Integrated signal is shown in red and measured
signal (over the threshold) in blue. The integrated signal width varies according to the selected Width
Adjust current source (activated by the comparator output high level or ‘1’).
3.5.3 Simulations
The simulation of the charge integration slope is shown in Figure 3.64 for various Width Adjust (WA)
values and the Dynamic Range capacitors of 16 pF.
Figure 3.64 : KI integration slope vs WA. The DR capacitor is set at 16 pC.
The integration slope is summarized in the Table 3.13. This slope varies according to the selected
values of DR capacitor and the Width Adjust current source.
Slope(mV/µs)
DR = 16 pF
DR = 24 pF
DR= 46 pF
2
153
103
54
6
265
187
99
10
492
357
189
18
936
682
362
32
1608
1222
651
Table 3.13 : KI integration slope vs WA current source. The DR capacitor is set at 16, 24 and 46 pF.
WA(µA)
110
Depending on the input signal rate, the combination of DR and WA has to be chosen accordingly. For
JEM-EUSO where the input signal could reach up to 100 MHz, it is preferable to use the fastest
integration time available. From Table 3.13, the fastest integration slope is given by DR = 16 pF and
WA = 32 µA which corresponds to the lowest DR capacitance and the highest WA current source. This
configuration is used for the following simulations.
3.5.3.1 Charge measurement simulations
For the input charge measurement, the input is considered as multiple pulses which are leading to
the input signal pileup. This case is especially true for the KI inputs which come from the ASIC preamplifiers. For the following, the simulations are focused on inputs which come from the ASIC preamplifier.
The pileup simulations can be done by varying the pulse width of the input signals and theses inputs
are injected simultaneously into 8 channels of the ASIC pre-amplifier. When the input signal is at the
smallest pulse width (2 ns), it can be assimilated to a single photoelectron signal of 200 fC. Therefore
the effective input of KI will be 1.6 pC as it is the sum of 8 channels: 8 x 0.2 pC = 1.6 pC. An example
of simulations is shown in Figure 3.65 which represents the KI effective input varying from 1.6 pC up
to 200 pC (input pulse width = 250 ns).
Figure 3.65 : KI analog signal (top). KI Trigger output (bottom). DR capacitance = 16 pF, WA current =
32 µA.
From the simulations in Figure 3.65, the trigger output width varies according to the input charges.
For these simulations, the trigger output width yields the value of 38 ns and 1030 ns for the
minimum input (1.6 pC ) and the maximum input (200 pC) respectively.
111
Figure 3.66 : KI Trigger Width (top). KI Trigger output (bottom). DR capacitance = 16 pF, WA current =
32 µA. In this configuration, the maximum trigger width is around 3.2 µA for the input charge of 2000
pC (over 8 pre-amplifier channels) or 250 pC/pixel.
Figure 3.66 is showing the results of similar pileup simulations. The maximum input signal increased
to whole GTU duration which yields the equivalent charge of 2000 pC (input pulse width = 2.5 µs) at
the KI input. From the top plot of Figure 3.66, the trigger output width varies linearly up to 100 pC.
Then KI analog signal reaches the maximum amplitude (~1.4 V) and saturates. Even though the
saturation occurs from 100 pC, the trigger output still varies as function of the input charges.
Otherwise this type of simulation is showing that the maximum acceptable input of the KI is relatively
high and good enough for the requirements of JEM-EUSO (2-200 pC/KI channel).
The next simulations are more interesting for the JEM-EUSO application as the input is considered as
discrete photoelectron pulses. The input rate of each channel could vary from 400 KHz up to 100
MHz which will yields the input of 1 to 250 p.e per GTU. The random fluctuations of the
photoelectron pulses are not taken account into the electrical simulations. The input for each
channel is illustrated by the following figure.
112
Figure 3.67 : Input signals steady spread without random fluctuation for each channel per GTU.
Maximum input is 250 p.e/GTU.
In this case 1 p.e is set at 200 fC. The simulations were done by keeping the same configuration
selected previously: DR capacitance = 16 pF and WA current = 32 µA. The results of the simulation
are shown in Figure 3.68. For this simulation the input charges are injected into 8 channels
simultaneously.
Figure 3.68 : KI trigger width(top). KI analog signal amplitude (bottom). Simulations for multiple
photoelectron pulses.
For the KI Trigger Width plot of Figure 3.68, some of the values obtained by summing the width of
each trigger generated by the discrete input pulses. This can be observed by looking at KI analog
signal plot from the same figure which is basically constant until the input is reaching 50 p.e per GTU.
From this point, the analog signal will start to experience the pileup before it becomes a single large
analog pulse. This behavior is translated by the analog signal increase shown in the plot Figure 3.68.
Basically this will induce the saturation of the analog signal and also trigger output. The trigger
output starts to saturate for an input of 80 p.e per GTU or 133 pC effective input charges. If required,
113
the saturation level can be raised by increasing the WA current values externally. Of course it will
come with the expense of extra power consumption.
The same type of simulations is done by injecting multi pulses input into smaller number of preamplifier channel. The simulations results are shown in Figure 3.69.
Figure 3.69 : KI trigger width for multiple photoelectron pulses input injected into 1,2,4 and 8 preamplifier channels.
The plot of trigger width shown in Figure 3.69 indicates that the analog signal varies according to the
number of pre-amplifier channels used. However there are several drawbacks coming from the fact
the input is the sum of 8 pre-amplifier channels. First of all, for a given trigger output width, it is
impossible to know how many MAPMT pixels were hit or even what kind of signal arrived. Therefore
the information from the Photon Counting is required in order to determine the exact measurement
of this Time-Over-Threshold system. Secondly, the minimum detectable signal increases gradually as
the number of the pre-amplifier channels receiving input decrease. For example when the input
charges are injected into 1 pre-amplifier channel, the minimum signal required for KI is around 40 p.e
per GTU. This basically makes the system is not suitable for small signal measurement for 1 pixel and
in this case the Photon Counting information is required again. Otherwise, with 1 pre-amplifier
channel input, the saturation level of the KI is much higher than 8-channel pre-amplifier inputs. From
the simulation, the saturation is reached at 800 p.e per GTU when charge injection is done only for 1
channel pre-amplifier.
3.5.4 Conclusion
From the simulations done and depending on the input signal type, it is safe to say the KI Time-OverThreshold could measure from 2-200 pC/GTU/8-pixel as specified by the initial requirements. As the
simulations were done in perfect conditions (without random distribution of photon), the
measurements with MAPMT and calibrated signals are required in order to establish the correct
charge measurements.
114
3.6 DAC
To set the threshold level, there are four identical 10-bit DACs which are used in the ASIC. The DAC
was designed to have low power consumption which is making it suitable for this ASIC. Furthermore,
its large voltage output range is good enough to fit all the requirements of each analog block in this
ASIC. The architecture of this DAC is shown in the following:
Figure 3.70 : 10-DAC transimpedance architecture.
The DAC value is set by an array of NMOS transistor current mirror. The current source, Iref, is set at
6 µA. With ratio of the current mirrors, the maximum current will be around 4 times of the reference
current:
The current to voltage conversion is done via a transimpedance amplifier. The DC gain of the
amplifier is set by the feedback resistor which is equal to 80 kΩ. Meanwhile the reference voltage is
set at 0.84 V. With the calculated maximum current, the maximum voltage of the DAC can be
determined.
By using the same method, the Least Significant Bit (LSB) of the DAC can be calculated as the
following:
With n = 10.
For example, when the DAC is used with the Pre-amplifier Trigger (1 mV/fC gain), the DAC LSB is good
enough to discriminate 2 fC or 1/80 p.e.
115
3.7 Digital
The main purpose of this part is to perform analog to digital conversion for Photon Counting and KI
Time-Over-Threshold block. The digital part occupies approximately 20% of the total silicon surface
of this ASIC. The layout of the digital part is shown in Figure 3.71 and Figure 3.72.
Figure 3.71 : Photon Counting digital part layout. Total surface: 8*(0.3 mm x 0.6 mm).
Figure 3.72 : KI Time-Over-Threshold digital part layout. Total surface: (0.35 mm x 0.6 mm).
3.7.1 General Description
In order to get the digital part running, it requires the 3 following signals:
a. System clock – 40 MHz – The clock is used for the whole digital system.
b. Gate Time Unit (GTU) clock – 400 kHz – GTU is used for data acquisition from analog and also
readout system.
c. Digital Reset – Global reset to initialize the state machines.
116
The digital part is designed to run continuously whenever all the mentioned signals are available to
the digital part.
For Photon Counting, the digital part is used to record the hit on each analog channel. The maximum
rate of the hit is defined at 100 MHz. Therefore in each GTU, the maximum hit number can be
recorded is the following:
Photon Counting max events
The implementation requires an 8-bit Gray counter for each channel and a readout state machine to
serialize the data.
For the Time-Over-Threshold, a similar approach can be used in order to know the maximum counter
values. However as it is a level counter, the System Clock will be used to sample the trigger length
coming from the analog channel. In this case the input is used as a gate for the counters.
Theoretically the trigger length could be as long as the data acquisition gate which is the GTU. For
Time-Over-Threshold counter:
Time-Over-Threshold max trigger length
Therefore a 7-bit counter is adequate for recording the data of KI Time-Over-Threshold module.
Figure 3.73 and Figure 3.74 show the general description of Photon Counting and KI Time-OverThreshold digital respectively.
Figure 3.73 : Photon Counting digital general architecture for one channel. The main components
are : 8-bit gray counter, 8-bit register for buffering the data and a readout state machine.
117
Figure 3.74 : KI Time-Over-Threshold digital general architecture for one channel. The main
components are : 2 D-type flip flops for synchronising and stabilising the input(KI comp), 7-bit gray
counter, 7-bit register for buffering the data and a readout state machine.
By referring to Figure 3.73 and Figure 3.74, the digital part of this ASIC is made around counters (8-bit
for Photon Counting and 7 or 8-bit for KI Time-Over-Threshold) which are used for each channel.
Additionally for the KI Time-Over-Threshold digital block, 2 D-type flip flops are used for
synchronising the input to the system clock. Afterwards, an array of registers are used is in order to
buffer the counters data before sending them to the parallel outputs of this ASIC. The readout is
managed by a state machine. The operations of the digital part shall be described in detail in the
following section.
3.7.2 Timing diagram
The complete timing diagram of the digital part is shown in Figure 3.75. It will be used in the
following to describe the whole operation of the digital part.
Figure 3.75 : SPACIROC digital timing diagram. The signals in orange box (ClkReadout, GTU and Rstb)
are external inputs. The signals in pink box (TransmitOn and DataOut) are the ASIC outputs for the
data transmission. Other signals are generated internally : Trigger PC and KI from analog part and
RstCounterb by digital part.
118
The operations of the digital part could be described by examining the timing diagram. The timing
can be separated into 3 successive phases namely Initialisation, Acquisition and Data Transmission.
The inputs/outputs of the digital part are regrouped on the left of the timing diagram. The inputs
required for the digital part are the following:
 System clock (ClkReadout)
 Gate Time Unit (GTU)
 Reset (Rstb)
As cited previously, the System clock is set at 40 MHz and the Gate Time Unit is set at 400 kHz (2.5
µs).
At the digital block there are also inputs which come from the analog block. They are corresponding
to the Photon Counting and Time-Over-Threshold triggers:
 Photon Counting trigger (Trigger PC)
 Time-Over-Threshold trigger (Trigger KI)
Lastly the list of the outputs is the following:


Data transmission flag (TransmitOn)
Parallel data output line (DataOut)
The operation phase depends on the Gate Time Unit level. It will be exposed in the following.
3.7.2.1 Initialisation
The initialisation phase is required to reset the digital part. There are 2 types of reset available here.
The first one is the asynchronous global reset which corresponds to the low level of Reset signal on
Rstb pin.
The second reset is a synchronous one which is generated from the low level of the GTU. The
synchronous reset is synchronized internally by a state machine. The purpose of the synchronous
reset is to flush the digital data counters before starting the Acquisition and Data Transmission phase.
The state machine, requires the GTU to stay at low level at least for 50 ns which corresponds to 2
cycles of system clock. This condition will define the dead time of the ASIC and also the duty cycle of
the GTU.
3.7.2.2 Acquisition
In this phase the digital part will acquire the data according to the incoming trigger from the analog
circuits. This phase is initiated by the high level of the GTU. As the detection in done by the rising
edge of the System clock, the GTU clock has to be synchronized to the falling edge of the system
clock by the clock provider. We took a conservative approach in terms of the System clock and GTU
phases in order to avoid timing problems. At least with the phase shift of GTU and the System clock,
we are sure there won’t be any violation of setup/hold timing and also to ease the constraint of the
standard cell synthesis. Towards the end of the data acquisition, the recorded data will be
transferred to the readout buffer by checking the falling edge of the GTU. Therefore in order to
transfer the data as much as possible, the GTU has to stay at high level the longest time as possible
119
which is 2450 ns. Given this condition, and the 50 ns reset phase, the duty cycle of the GTU should be
of 98% as shown in the following figure:
Figure 3.76 : Acquisition phase timing diagram. The GTU of 2.5 µs length and 98 % duty cycle is
shown in top plot.
3.7.2.3 Data Transmission
The data transmission starts with the rising edge of the GTU. It is simply done by serializing the
readout buffer data into the parallel output line. Unlike the data acquisition counters, the data of the
readout buffer is not flushed during the synchronous reset of the Initialisation phase. The
serialization will start the data transmission by sending a start bit and the MSB of the lowest channel
number. Each data serializer (corresponding to one digital module) will shift out 8 channels for
Photon Counting and 9 channels for KI Time-Over-Threshold. In total there are 9 parallel output lines
for the digital part of this ASIC (8 bits for Photon Counting and 1 bit for KI Time-Over-Threshold). The
data transmission ends with a parity bit. The data structure of the output data is shown in Figure 3.77.
Figure 3.77 : Data Transmission timing diagram.
From the figure, the output data is 66-bit wide and each bit is synchronized to the rising edge of the
System clock (ClkReadout). Additionally, a signal called TransmitOn which is used to flag the data
transmission is also available. It will be active during the whole data transmission. As the system is
designed, the data transmission during GTU(n) is in fact for the counter values of the previous GTU(n1).
120
3.7.3 Simulations
The simulations have been carried out for both digital part of Photon Counting and Time-OverThreshold. The simulations shown in the following is only at the behavioral level which is enough for
validating the logic design of the digital part.
Figure 3.78: Photon Counting digital simulations. A trigger signal representing 1 hit is injected at
Channel3 in GTU (n-1).
Figure 3.79 : KI Time Over Threshold digital simulations. A trigger signal of 25 ns width is injected at
Channel3 in GTU (n-1).
For both simulations (Figure 3.78 and Figure 3.79), the minimum signal is injected in channel 3 of
each digital module. The corresponding output on the parallel lines can be seen 1 GTU later. Of
course other variations of the input signal have been simulated and the corresponding outputs have
been validated by the test bench of the digital modules.
121
By using the data of digital simulations, a raw estimation of power consumption can be done by the
digital synthesis tools. With the back annotation information, the input rate and the estimation of
switching frequency, the synthesizer could calculate the digital part dynamic and static power
consumption. The dynamic power consumption is the most interesting information and it is given by
the following relation:
With
the total load capacitance,
the power supply and f the switching frequency.
The power consumption estimation is done for the following case: 25-100 MHz input rate for Photon
Counting trigger and 25-2500 ns input width for Time-Over-Threshold. The results are summarized in
the Table 3.14.
Power Dissipation @
Vdd = 3 V (mW)
Power Dissipation/ch
@ Vdd = 3V (mW)
Notes
Input rate: 25MHz –
100MHz
Input width : 25 ns –
Digital KI
1.5769 - 2.0992
0.1752 - 0.2332
2450ns
Table 3.14 : SPACIROC digital power consumption estimations (static and dynamic).
Digital PC
6.7078 - 37.4368
0.1048 - 0.585
3.7.4 Data Readout and connection to the FPGA
After examining the data transmission method of this ASIC, one could imagine the readout system
based on FPGA. Basically there are two ways of reading out the data from SPACIROC ASIC.
(a)
(b)
Figure 3.80 : TransmitOn readout system (a) and Start Bit readout system (b).
The easiest way to do the readout is to use the TransmitOn signal as shown in Figure 3.80 (a). The
output bit is synchronized on the rising edge of the System (Readout) clock, therefore the data could
be acquired at the FPGA side on the falling edge of the Readout clock. It will be done continuously as
long as TransmitOn is active. The second system shown in Figure 3.80 (b) will omit completely the
TransmitOn signal. The readout system is initialized by the Start Bit. The advantage of this system is
that there will be less headroom on the I/O considering that the PDM FPGA in JEM-EUSO could
manage at least 36 ASICs or maybe more. The disadvantage of the system is that the readout logic is
slightly complicated than the first system as the detection of the Start Bit has to be taken into
account.
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3.8 Radiation tolerance and Single Events mitigations
With the advent of the transistor process miniaturization, more and more electronic system
designers are turning to ASIC as a fully integrated solutions as opposed to the discrete components.
This trend is also increasingly to be important in spaceflight electronics. Of course the primary choice
for spaceflight electronics will be the radiation hardened process from provider such as Aeroflex or
Honeywell. However with the emerging of cost efficient commercial process, designers are looking
seriously to build the ASIC by using more accessible technology. Furthermore, the technology process
such as BiCMOS SiGe is starting to become a very good alternative to the radiation hardened process
in terms of costs, performances, radiation tolerance and power consumption.
The radiation effects which can happen to microelectronics devices [45] can be divided into two
categories: cumulative effects and single event effects (SEE). The cumulative effects will gradually
take place during the lifetime of the device. The continuous exposition of the device to the radiation
will result to 2 types of damage which are called total ionizing dose (TID) [46] and displacement
damage [47]. The total ionizing dose effect will create electron and hole pairs where the pair creation
is proportional to the absorbed dose. CMOS transistors can be affected by TID. On the other hand,
the displacement damage will cause defects to the Silicon lattice. Depending on its energy, a particle
or photon of is capable to remove a Silicon atom from its lattice site [48]. Displacement damages will
usually affect the performances of Bipolar transistors.
For the single event effects (SEE) [49], it could occur when a particle hits or passes through the
microelectronics device. The single event effects could be subdivided into non destructive and
destructive effects. The non destructive effects as its name suggest induce only non permanent
damages or soft errors. However, the destructive effects are harmful and will render the concerned
device useless.
Radiation threats to JEM-EUSO electronics
Specifically for JEM-EUSO mission, this ASIC (and also other electronics) will be exposed to ionization,
displacement damages and the single event effects. ISS is orbiting pretty low (around 400 km) in the
Low Earth Orbit (LEO) and with high inclination (51.6°) [33]. Therefore the radiation sources are
numerous [50] [51]: trapped charges in Van Allen belt, galactic cosmic rays, solar flares, South
Atlantic Anomaly and so on. Electrons and protons trapped in Van Allen belts will cause the
ionization and displacement damages in ASIC. Luckily the total ionizing dose will be not very high
(could be as little as 1 krad/year) if the instrument is properly shielded. Therefore a lot of commercial
process could fit the requirement for the TID in LEO orbit. On the other hand, the single event effects
can be caused by the highly energetic particles coming from cosmic rays (heavy ions,..) or South
Atlantic Anomaly (protons). Some of the single effects can harm the ASIC. Unfortunately shielding is
not very effective against the high energy particles. Therefore the concerned effects have to be
evaluated and mitigations have to be applied. The mitigations for single event effects in SPACIROC
are discussed in Section 3.8.2.
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3.8.1 Cumulative Effect to CMOS and Bipolar transistors
CMOS and MOSFET family transistors are most likely to be exposed to the ionization by the incoming
particles as the device sits on the surface of the silicon substrate. The most sensitive part of this type
of transistor is the gate oxide (SiO2) where electron-pair can be generated by ionizing particles. The
following figure is showing the position of gate oxide within a N-channel MOSFET transistor.
Figure 3.81 : Positive biased N-channel MOSFET.
The gate oxide is an insulator between the gate and the channel. As opposed to more conductive
part such as the transistor gate, the electron hole pair creation will not be evacuated easily.
Depending on the biasing, there could be an accumulation of hole or electron near the gate oxide
and substrate interface. By continuing the example of positively biased N-channel MOSFET transistor
as in Figure 3.81, the mechanism of hole trapping [52] [46] is shown in Figure 3.82.
Figure 3.82 : Energy Band diagram of transport and trapping of holes in gate oxide.
From Figure 3.82, one can see that the electron and hole pairs are generated within the gate oxide
(1). A fraction of the pair will be recombined and the other will be separated by the potential
difference. As the gate is positively biased, the electrons will be evacuated through the gate. For the
124
holes, they will make their way to the SiO2 – SI interface through a very slow transport mechanism
(2).The holes which reach the interface can be trapped (3). The radiation could also induce the
interface trap on the substrate side (4). This will furthermore increase the accumulation of the
trapped holes at the SiO2 – Si interface, as well as the positive charge. Hence an adjustment of the
gate voltage is required in order to keep the same negative charge in the channel between drain and
source. In other terms, the electrical performance of the transistor will be changed as the threshold
voltage, VT, is lowered.
The release of the trapped holes by recombination with electron could happen by the following
mechanisms: tunnel-effect based annealing and thermal effects annealing. Furthermore the number
of the trapped holes is reduced when the gate oxide decreases. Consequently, submicron process
with ultra thin gate oxide [53] will be fairly resistant to the accumulation of the trapped holes at gate
oxide without any special mitigation. Below 12 nm of oxide thickness, which is the case for the
process used for SPACIROC ASIC, the transistor will show lower VT shift due to the fact that trapped
holes are mostly released by the tunnel-effect based annealing. The following figure is showing the
reduction flatband voltage, VFB, and the density of the interface traps as a function of gate oxide
thickness, tox [46] [54]. VFB is related to VT by following equation:
|
Where
|
√ |
|
is the surface potential and is the substrate threshold parameter
(a)
(b)
Figure 3.83 : Flatband voltage shift (a) and variation of the interface traps (b) after 1 Mrad
accumulated dose according to oxide thickness, tox.
In spite of the reduction of trapped charges due to lower thickness of the gate oxide in submicron
process, other problems could occur within the oxide at the edge of the transistors. To separate the
transistors and interconnection purposes, a thicker field oxide is usually employed. In submicron
process technology, there are 2 types of field oxide isolation which can be used: Local Oxidation of
Silicon (LOCOS) and Shallow Trench Isolation (STI). Unfortunately the accumulation of trapped
charges could also be induced by the radiation and it happens at a bigger magnitude due to the
125
thickness of the field oxide. Typically the charges accumulation occurs at the edge of the active
region of the transistor gate as shown below:
Figure 3.84 : Accumulation of positive charges for N-type MOSFET at the edge of the gate and field
oxide (LOCOS).
From Figure 3.84, the accumulation of the charges is shown in the edge region of the transistor
which is also known as the Bird’s beak. Typically this situation will allow additional channel for drain
and source of the MOSFET device on both sides of the defined gate. Thus it can be seen as parasitic
MOS devices on the edge of the transistor. When the parasitic devices are turned on, a leakage
current will flow directly through it instead of the channel beneath the active gate. This phenomenon
could be penalizing for the electrical performance of a thin oxide MOSFET transistor. The mitigation
of this problem can be done physically by special layout of the device [55]. Following figure shows
several proposals of layout which could be used for leakage current mitigation:
(a)
(b)
(c)
Figure 3.85 : TID mitigation layouts. (a) Increase of leakage path via modified gate. (b) Increase of
leakage path by p+ diffusion. (c) Edgeless layout transistor.
126
In Figure 3.85 (a), the gate layout is modified in order to increase the leakage path. It will help to
reduce the possibilities of the parasitic devices to be turned on. This is a fairly simple solution but it
will not be effective when TID requirement is relatively high (e.g > 200 kRad as defined in [51]).
Figure 3.85 (b) uses similar idea but as the leakage path is increased furthermore by laying p+
diffusion around the diffusion of the drain and the source. Lastly in Figure 3.85 (c), it is probably the
best solution for leakage current mitigation when the TID requirement is high. In this layout, the
parasitic leakage path is totally eliminated. However some drawback of this layout is the W/L ratio is
not straight forward. It also occupies larger area thus increasing parasitic capacitances which could
be penalizing in terms of electrical performances.
In certain technology process, lateral Bipolar transistors are also offered by the foundry. However
lateral Bipolar transistors could be affected by ionization problems as the device is etched on the
surface of the Si substrate. The ionization of the field oxide will occur and it will induce the leakage
current of the transistor base. This will degrade the gain of the transistor. Other type of Bipolar
transistor such as SiGe HBT, which is widely used in this ASIC, is fairly immune to the TID problem.
However, as the device is deeply buried in the Silicon bulk, SiGe or vertical Bipolar transistor is more
sensitive to the lattice damage by incident particle. The displacement damage is proportional to nonionizing energy loss (NIEL) and also the particle type and energy. For example a neutron of 1 MeV will
transfer 60-70 keV to Silicon recoil atom which could displace 1000 additional atoms in an area of 0.1
µm. Below is a comparative table of displacement damage by different types of particle [47] [56] :
Particle
Proton
Neutron
Electron
Electron
Energy
1 GeV
1 MeV
1 MeV
1 GeV
Relative
1
2
0.01
0.1
Damage
Table 3.15 : Relative displacement damage for various particles. From [47] [56].
Following are the effects of displacement damage:



Formation of mid-bandgap states which will facilitate the carriers generation or
recombination. In the reverse-biased PN-junction it will lead to leakage current. In the
forward biased junction it will lead to loss of charge carrier as a result of recombination.
Creation of states close to the bandgap edges which can facilitate the charge trapping.
Changes in the doping characteristics.
In terms of electrical performance, Bipolar transistors are mostly affected from the formation of midbandgap states in forward biased junction. More precisely the affected part is the Base-Emitter
junction. The creation of mid-bandgap states will facilitate the recombination of the free carrier in
Base-Emitter junction. Thus it will decrease the DC current gain of the Bipolar transistor. This
degradation also depends on the concentration of the carrier. For example, a smaller device will
experience less DC current gain degradation when compared to bigger device when both are biased
with the same collector current. Following is the measurement of DC current gain of NPN and PNP
transistors which are exposed to 800 MeV protons [57].
127
Figure 3.86 : DC current gain of NPN and PNP device before and after 800 MeV protons irradiation.
Plots taken from [57].
In order to reduce the probability of the free carrier recombination, reducing the carrier transit time
could be used as a mitigation strategy. This strategy is fairly compatible with the current IC process
as newer BiCMOS technology is always increasing the transistor transition frequency. Another
technique to reduce the carrier transit time is by using the minimal width base. For high speed
application, the minimal base is often employed in order to keep the device bandwidth as large as
possible. This is one of the reasons why SiGe technology is increasingly popular especially for
radiation hardened low-power front-end electronics.
The technology used for this ASIC can withstand up to 420 kRad [58] of cumulated dose. Therefore it
is fairly good technology choice for JEM-EUSO mission as the requirement for the ASIC is around 30
kRad9 (refer to Section 2.6 in Chapter 2 ). Furthermore this ASIC employs mainly Bipolar transistors
for the front-end design. As cited previously, Bipolar transistors have superior performance than
CMOS when exposed to the radiation. This is due to the fact that the Bipolar transistors are less
affected by the threshold shift and offer higher bandwidth and device matching for a given power.
9
Total dose rate for a spacelight ICs depends on the mission’s orbit, inclination and shielding. For ISS in Low
Earth Orbit with 51° inclination, the total dose would be 1-10 krad/year (Data from NASA –Johnson Space
Center [51])
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3.8.2 Single Event Effect and mitigations
The Single Event Effects (SEE) are the anomalies which happen to electronic devices when a highly
energetic particle passes through it. The deposited energy could generate electron-hole pairs, which
can simply recombine in Silicon bulk or give a rise of current spike around the P-N junction. Naturally
the sudden rise of current spike will contribute to various transient effects. Single Event Effects can
be classified into non destructive effects and destructive effects. The different types [59] of SEE
which commonly occur are listed below:
Name
Single Event Upset
(SEU)
Single Event Transient
(SET)
Single Event Disturb
(SED)
Single Event Latchup
(SEL)
Single Event Burnout
(SEB)
Single Event Gate
Rupture (SEGR)
Single Event Dielectric
Failure (SEDF)
Sensitive Device
Description
Destructive
Digital ASIC
Bit flip in memory cells

Temporary delay of transient
signal
Temporary disturbance of digital
Digital ASIC
part
Triggering of parasitic thryristor
CMOS, BJT
which induces high current
between the power supply
Parasitic bipolar structure is
activated by heavy ion induced
Power transistors
current. Catastrophic failure due
to high collector current flow.
Power transistors,
Rupture of gate oxide by heavy
EEPROM
ions
Rupture of dielectrics by heavy
FPGA
ionizing particles in a high-field
dielectric region
Table 3.16 : Various Single Event Effects.
Analog ASIC, clocks






Typically for mixed signal ASIC like SPACIROC, Single Event Latchup (SEL) and Single Event Upset (SEU)
are the main concern and have to be taken into account during the design.
3.8.2.1 Single Event Upset
Single Event Upset (SEU) occurs usually in a memorising block of a chip [60]. Typically the error
induced by this type of SEE is bit flip of the memorised data. A bit flip could happen in a single
memorising block or multiple blocks. It is a non destructive effect which means a simple reset or reinitialisation is enough to put the affected device back in order.
SEU could occur when a particle penetrates into the Silicon bulk. Towards the penetration path, the
particle will generate the electron-hole pair formation. This phenomenon will create an amount of
charge. When the charges are collected by a sensitive device, it could change the equipotential of the
concerned device which will induce a state flipping. The following figure illustrates the sectional view
of Silicon bulk when the SEU occurs:
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Figure 3.87 : Sectional view of a MOSFET transistor during SEU.
As shown in Figure 3.87, there are three regions where the electron-hole pair creation could occur,
namely depletion, funnel and bulk region. The charges created due to the drift of the depletion
region could be collected quickly to the surface. This charge collection could occur in sub ns time
scale. Furthermore, the charges created in the funnel region could also rise to the surface, but witht
a slower time scale. The extension of the charge collection from this region is also called the
funnelling effects. The electron-hole pairs created deeply in the bulk could also be collected on the
surface, but normally the charge collection from this region is slow and doesn’t contribute to the SEU
events.
Another parameter which defines the SEU is the density of the pair creation. It could be determined
by the stopping power (dE/dx) or the Linear Energy Transfer (LET) of a particle. The relation of dE/dx
is given by the following equation:
Where denotes the material density. [
]
.
The minimum energy required to create an electron-pair in a Silicon bulk is around 3.6 eV. Therefore
by knowing the minimum charge to trigger the SEU, the minimal deposited energy could be deducted
from the following equation:
The minimum LET is given by the following:
With
the density of Silicon and
the sensitive depth of the device.
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The sensitivity of the SEU is characterized by the cross section of SEU. The cross section of the SEU
can be calculated by the following equation:
(
Where
( [
] )
)
is the SEU saturation cross section,
is the minimal energy, W and S are the fit
parameters.
Plotting the cross section against LET will give the LET threshold which is needed to produce an upset.
Different type of particles will not have the same effect on the Silicon. Heavy ions will have
tendencies to create a lot of electron-hole pairs in the Silicon bulk, therefore they are very good
candidate to trigger the SEU. Meanwhile, the photon (X or γ) creates very few electron-hole pairs. So
it is unlikely to generate the SEU upset. As for the hadrons, it also has lower density of electron-pair
creation and wouldn’t trigger the SEU directly. However, hadrons can generate nuclear interactions
which will create in turn a large number of electron-hole pair and trigger the SEU.
In terms of mitigations, it is mostly done by hardware design. The mitigation could also be done by
software correction as especially when dealing with a large number of critical data. The software
correction is also known Error Detection and Correction (EDAC). EDAC in its simplest form could only
be the parity bit generation up to much more complex system such as Hamming or Reed-Solomon
codes.
For SPACIROC ASIC, most of the mitigation strategy is done by hardware design. The areas of the
ASIC which are vulnerable to the SEU are the analog parameter registers (Slow Control) and the
digital part. For the hardware design, one of the most popular strategy is to use the redundancy
method. This method is relatively easy to implement and quite effective. The only drawback of this
method is probably the large area headroom. One of the most well known redundancy method is
called Triple Modular Redundancy (TMR) [61]. The block diagram of TMR is illustrated below:
(a)
(b)
Figure 3.88 : Triple Modular Redundancy (a). Majority Voter (b).
The basic idea of TMR is replicating identical module three times and a majority voter is attached to
each module output. The voter will select the most represented values or data from the replicated
modules. The majority voter equation is the following:
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TMR technique can be applied basically to any logic level. For example this technique is applied to
the slow control parameter cell of this ASIC.
Figure 3.89 : SPACIROC slow control cell.
The Slow Control parameters are sent to the ASIC via a shift register composed of the elementary
cells as shown in Figure 3.89. The data storage is done via a set of three data latches and a majority
voter is added according to the TMR technique. Error detection logic is also included in order to flag
the SEU event. The data shifting is done via a scan type flip flop in order to have non destructive Slow
Control parameter readout. This readout feature could give the possibilities comparing the output to
the correct parameters before taking decision to reinitialize the ASIC or not.
For the digital part of the ASIC, a similar redundancy method is also used. However, it could not be
used for the whole level of this block because it will increase significantly the silicon area of this part.
Only critical components such as reset generations are replicated for the digital part. Finally the
parity bit generation is included for each parallel output of the digital block. It will allow flagging a bit
flip in the case of SEU but without any correction capabilities.
3.8.2.2 Single Event Latchup
Single Event Latchup is a destructive effect [55] and could destroy the ASIC completely. When the
effect is taking place, there will be a direct path from the power supply to the ground. If the power
supply could drain enough current, it could destroy the device with external power dissipation. In a
CMOS technology, the latchup could occur due to the presence of parasitic transistors which is also
known as thyristor. Basically it is a combination of 2 Bipolar transistors when a PNPN structure is
present. The illustration of the CMOS transistor with the parasitic thyristor is given by Figure 3.90.
As shown in Figure 3.90 (b), Q1 and Q2 provide a positive feedback to each other. This basically
means that if any of the parasitic transistors is activated, it could activate the second one and they
will continuously amplifying the collector current of each device.
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(a)
(b)
Figure 3.90 : (a) Cross section view of CMOS and parasitic transistors. (b) Representation of thyristor.
The mitigation could be done in several ways. First of all the feedback gain (βQ1.βQ2) should be
reduced. It can be done by increasing physically the distance of the parasitic transistor by moving
apart the NMOS and PMOS transistors. A second approach which can be done is reducing the
resistivity of the Rn and Rp resistors shown in Figure 3.90 (b). By having lower resistivity, there will be
less probability of current flowing into the base of each parasitic bipolar transistor. It will help to
prevent the biasing of parasitic transistors. By adding more power supply contact of each substrate
will help to reduce the value of Rn and Rp. Lastly there is also a possibility to choose technology
process which could eliminate completely the parasitic Bipolar transistors. Devices fabricated from
process incorporating Silicon On Insulator (SOI) are completely free from SEL because of the physical
separation of NMOS and PMOS transistors. Although SOI is the best solution for latchup protection,
the process is slightly expensive and not used for designing this ASIC.
The cited mitigation techniques have been applied to the layout of the SPACIROC analog core.
133
Figure 3.91 : An example of CMOS transistors layout. Increased distance of NMOs and PMOS and
multiplication of substrate contact.
As the layout shown in Figure 3.91 was done for full custom analog design, the mitigation strategy is
not employed on the digital part which is based on standard cells. If the same strategy is to be
applied to the digital part, the physical layout modifications of the standard cells have to be carried
out. The heaviest works will be then to set up the environment for designing the digital part in order
to accept custom cells.
Therefore the latchup mitigation of the digital part has to be done externally. Usually the power
supply unit could detect the sudden current spike and cut off the power in order to protect the
circuits from the latchup. The same methodology can be applied locally to the ASIC for example by
clamping down the power supply with a Zener diode or a resistor. For the digital part of the ASIC, a
50 Ω resistor is added in series to the digital part power supply. This can be done if the concerned
block has very low power consumption and the power supply of the block is independent from the
other.
134
Chapter 4 ASIC Characterization
A dedicated measurement test bench has been setup for the laboratory tests of SPACIROC ASIC. The
test bench is made around a test board where a packaged SPACIROC ASIC can be mounted. In order
to control the test board and the ASIC, a control system is made by using National Instrument’s
LabVIEW platform. The picture of the test bench is shown in the following figure:
Figure 4.1 : SPACIROC test bench at LAL.
All the different parts of the test bench are described in the following sections. The descriptions
concerning the hardware and software for the ASIC measurements are given in Sections 4.1 and 4.2.
Section 4.3 is dedicated for the ASIC laboratory tests. The tests which specifically concern the Photon
Counting and Time-Over-Threshold are described from Section 4.3.4 to 4.3.7. The ASIC measurement
results with UV light and Hamamatsu R11265-M64 MAPMT as discussed in Section 4.3.8.
4.1 Test board
A dedicated test board was made for testing and characterizing the ASIC. The first version of test
board is shown in Figure 4.2. As seen in Figure 4.2, the test board is equipped with a socket for
facilitating the test of different packaged SPACIROC ASICs. The ASICs are packaged in CQFP240
specifically to be used with this test board.
135
Figure 4.2 : SPACIROC test board. The socket for the ASICs packaged CQFP240 is highlighted in red
box labelled “SPACIROC”.
The following features are available for the tests:


Various type of inputs for the ASICs :
o ASIC internal charge injection via 2 pF capacitance (Ctest)
o Onboard charge injection via 10 pF capacitance (Vin)
o Footprint for 64-pin Hamamatsu R11265-M64 MAPMT
 High Voltage Power Supply is supplied the Hamamatsu MAPMT base
o External trigger for Digital part
Various points for signals (analog, digital, control, etc ...) monitoring:
o Analog Signals
o Discriminator outputs
o Discriminator OR outputs
o Clocks & Digital signals
o Probe & Slow control signals
On this board there is an Altera Cyclone II field-programmable gate array (FPGA) which is used as an
interface for controlling the ASIC and retrieving the data. The communication between the ASIC and
the FPGA is done following the communication protocols shown in Chapter 3 (Section 3.7.2.3). The
acquired information of the ASIC (data and Slow Control bits) are sent to a personal computer (PC)
through a USB interface which is handled by a USB-to-serial converter chip of FTDI (FT245xx family).
This serial port can be accessed directly from LabVIEW software thanks to the LALUsb library and
driver maintained by Electronics Service (Instrumentation & System Group) of LAL.
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4.2 LabVIEW Software
The development of the software for testing the ASIC was started by using LabVIEW 7.1 before it was
upgraded progressively to LabVIEW 2010/2011 in order to keep the compatibility with different users
of this software. The main purposes of this software are to send the ASIC slow control parameters
and to retrieve data from the ASIC. Several automated tests can also be done with this software. The
screen shots of the software are shown in following figures.
Figure 4.3 : ASIC configuration tab.
The screenshot in Figure 4.3 is the most important part of this software. All the configurations and
parameters of the ASIC are sent from this page. There are 897 bits (Slow Control bits) available for
controlling the ASIC parameters. The list (non-exhaustive) of the parameters which can be controlled
from the LabVIEW is the following:







Biasing stage switches for most of the ASIC analog components
Pre-amplifier gain settings for each ASIC pre-amplifier channel
Internal charge injection selection
DACs step
Photon Counting trigger selection and FSU shaper settings
KI Time-Over-Threshold (ToT) parameters settings: Dynamic Range capacitor, Width
Adjustment current source, Coarse/Fine DC current absorber
Individual channel trigger masking for Photon Counting and KI
137
The second screenshot shown in Figure 4.4 is for reading out the slow control parameters which are
stored inside the ASIC. This is a particularity of this ASIC where the slow control cells implementation
allows unlimited non-destructive readout of its stored value. This feature is particularly useful for
checking the bit flip in case of SEU or for simple verification before scrubbing the ASIC parameters.
Figure 4.4 : Slow control readout tab.
For communications from the PC (LabVIEW) to the FPGA, the parameters between both devices are
defined within a set of “words”. In total there are 5 “words” available and each “word” contains 8
bits data for setting the FPGA. One of the LabVIEW tab (Figure 4.5) is dedicated for writing and
reading these bits. Some of the bits in these “words” are directly affecting the ASIC input such as the
digital part reset, clocks and slow control pins. Therefore, this tab is very convenient for debugging
purpose since certain ASIC pins can be accessed directly. For the other bits, most of them are used
for internal FPGA purpose such as slow control bit sending request and data acquisition.
138
Figure 4.5 : FPGA word write/read tab.
Figure 4.6 shows the page where the parameters of the signal monitoring (also known as probe) can
be selected. The probe parameters contains 265 bits and it is a subset of parameter registers for this
ASIC. The registers can be accessed via the same pins used for sending the slow control bits. There
are two types of probe available: Analog and Digital probes. Analog probe is used for monitoring
analog signals for each analog block of this ASIC (Pre-amplifier, FSU, VFS and KI). Each channel can be
monitored individually. On the other hand, the Digital probe is for monitoring discriminator output of
each Photon Counting trigger channel. However this probe is not implemented for the KI trigger.
Figure 4.6 : Probe and signal monitoring tab.
The screenshots in Figure 4.7 and Figure 4.8 show the automated test for the DAC measurements
and the DC level verifications of each analog output. In order to enable the automated tests, an
external multimeter with GPIB communication port is required. Figure 4.7 shows the tab measuring
139
the linearity of the 10-bit DACs of this ASIC. The linearity and the fit residual will be plotted
automatically after the tests.
Figure 4.7 : DAC measurement tab.
The DC level of analog outputs can also be measured thanks to the GPIB enabled multimeter. In the
tab shown in Figure 4.8, the LabVIEW software are capable of selecting each channel for each analog
output available for this ASIC. Of course, the statistics of each analog output DC level can be given by
this LabVIEW.
Figure 4.8 : DC level measurement tab.
The snapshot shown in Figure 4.9 is one of the important aspects of the ASIC tests as it is used to
readout the data coming from chip via the interface done by the FPGA. In this tab, there are several
140
parameters which can be set for the readout. The number of GTUs can be set to a maximum of 100
frames due to the limited FPGA FIFO capacity and huge number of data. The number of data
acquisitions can be increased via the software with the multiple of 100 GTU frames. Furthermore, the
GTU width can be also controlled from this tab which is useful to control the input rate when the
input is synchronised with this clock. The data of the Photon Counting and the KI are shown in
histogram for each channel in the graph panels visible in the screenshot.
Figure 4.9 : Photon Counting and KI data readout tab.
The S-curves [62] tests (Section 4.3.5) tab is shown in Figure 4.10. The S-curves can be done for both
Photon Counting and KI part. The trigger hit is taken directly from the digital data. By doing so, the
influence of the digital part on the analog performance can be extracted as well. There is another
variant (not shown here) of S-curves test which can be done only by using the analog part. The
parameters concerning the data acquisition in Figure 4.10 is the same as the data readout parameter
tab (Figure 4.9).
Figure 4.10 : S-curves tab.
141
Figure 4.11 shows a variant of S-curves tests which includes the variation of the input charges. The
input charge can be varied by controlling the output of a GPIB enabled waveform generator. This test
is mainly used for checking the Photon Counting linearity and also to verify the charge measurement
of the KI Time-Over-Threshold part.
Figure 4.11 : S-curves vs input charges tab.
The screenshot shown in Figure 4.12, is mostly used during the MAPMT test. This tab is used to
equalise the gain of the 64-channel pre-amplifier due to MAPMT gain dispersion. This function is a
part of MAPMT and ASIC calibration strategy and the methodology which are explained in details in
the Chapter 5.
Figure 4.12 : Pre-amplifier gain adjustment tab.
142
4.3 ASIC Measurements
This section concerns the different tests and measurements which have been carried out in the
laboratory. In the following, general electrical characteristics of this ASIC are reported. Photon
Counting characteristics such as amplitude, gain and trigger efficiency (S-curves) are reported from
Section 4.3.4 to 4.3.6. Meanwhile for Time-Over-Threshold, only functional verifications of this
module are reported in Section 4.3.7. The performances of ASIC with respect the JEM-EUSO running
conditions are reported in Section 4.3.8 which concerns the tests with MAPMT. Additionally the
MAPMT tests are the most convenient way to verify the Time-Over-Threshold performances.
Charge/current Injection
The charge injection method for testing this ASIC can be done either by applying a step input to a
capacitor or applying a voltage pulse to a resistor.
The voltage pulse is normally better since the timing and the amplitude of the pulse can be
controlled. Furthermore this kind of charge injection is suitable when a high input rate is required.
The schematic of this test injection is shown below.
Figure 4.13 : Voltage pulse charge injection.
The input is AC-coupled to the ASIC by using a 50 nF capacitor (Cc). The equivalent input charge can
be calculated as the following:
Where v represents the amplitude of the input, R the chosen resistance values for charge injection
and t represents the half width of the input pulse.
Figure 4.14 : Pulse input waveform from Tabor Electronics waveform generator.
143
Figure 4.14 shows an example of pulse used for charge injection. The pulse amplitude, v, is equal to
80 mV and the half width, t, is equal to 2 ns. Typically for the resistance R, values between 500 Ω and
1000 Ω are used for the current injection. For example when R = 1000 Ω and using the values from
Figure 4.14, the equivalent input charge can be calculated as the following:
(160 fC corresponds to 1 p.e for MAPMT gain of 106)
This kind of charge injection is probably one of the best ways to imitate the MAPMT input pulse as
the condition of the fast input pulse is respected. For the Photon Counting part of the ASIC, the
characterization is done almost exclusively with this kind of input pulse. As there is no dedicated
resistance onboard, the charge injection is done directly on the MAPMT footprint of the test board.
The second type of charge injection used for characterizing the ASIC is obtained with a capacitor. For
a step input into a capacitor, the schematics are the following:
Figure 4.15 : Step input charge injection.
Figure 4.16 : Step input waveform from Tektronix waveform generator.
The equivalent input charge is simply Q = CV. This method is available on the test board (10 pF
capacitance) and also inside the ASIC (2 pF capacitance). To create a negative voltage pulse at the
ASIC input, the falling edge of a step input is used. For example, when the step input shown in Figure
4.16 is applied to 10 pF capacitor on the test board, it will yield an input charge of 160 fC (16 mV x 10
pF). This type of injection charge is not widely used for the ASIC characterization, for the following
reasons:
1.
There is no way to control the input pulse width if a particular width is required.
2. The rising edge of the step input can disturb the measurements as it can’t be suppressed
completely.
144
For our tests, this charge injection is still used when timing precision is not required and several
channels need to be tested at the same time. For example, it is suitable to test the KI Time-OverThreshold part where 8 channels can receive charge inputs simultaneously. As a reminder, 1 channel
of the KI Time-Over-Threshold will take up to 8 channels of pre-amplifier signal as input. Additionally,
this kind of input is also a great debugging tool as the input charge capacitors is available within the
ASIC. It is particularly useful for example during the ASIC screening automated tests or for the selfdiagnostic when the ASICs are mounted on the instruments.
Before starting the measurement, the DC level of each ASIC pin is verified just in case there is any
problem with the ASIC biasing stage. As expected, no particular problem was found when checking
the biasing stage and the DC level of each pin.
4.3.1 DC level measurements
The first measurement to be done is to check the DC level of each analog components of this ASIC.
The measurement is done directly via the LabVIEW software for testing this ASIC. The measurements
accuracy is given by the multimeter which is in the order of 0.01%.
Figure 4.17 : DC level of the pre-amplifier output. The dispersion between each channel is relatively
small at 1 mV rms.
145
Figure 4.18 : DC level of the FSU shaper output. The dispersion is about 1 mV which is small enough.
Figure 4.19 : DC level of the VFS shaper output. The dispersion of VFS DC level is also reasonably
small : 1 mV rms.
146
Figure 4.20 : DC level of the KI Time-Over-Threshold output. The DC level dispersion for this module
which is at 1.5 mV rms is on par with other analog components of this ASIC.
The following table summarizes the measured DC level and the simulation values:
Component
Pre-amplifier
FSU
VFS
KI
Mean (V)
RMS (mV)
Simulation (V)
2.522
1
2.5
1.038
1
1.019
1.037
1
1.03
1.5098
1.5
1.449
Table 4.1 : Measurements of Analog part DC levels
From the DC level measurements, the dispersion between each channel is less than 1.5 mV RMS for
all the analog part available for this ASIC. The small dispersion obtained for this ASIC is partly due to
the careful layout and also the good matching of SiGe process. When compared to the simulation
values, the DC levels are roughly the same. Therefore, it is a good indication that the biasing stage
and the voltage reference values are in a good shape.
4.3.2 Noise measurement
One of the important aspects of this ASIC is noise performances. The noise is inspected for each
channel of the ASIC analog part.
4.3.2.1 Analog Noise
The first measurement is to the check the RMS level of the analog output. The output of the Analog
part is connected to the output buffer on the test board before it reaches the oscilloscope.
In order to check the intrinsic analog noise, the digital part of this ASIC was disabled by resetting it
and the clocks were turned off. Furthermore, the signal flow is only turned on for the measured part
as we wanted to avoid any influence of the other analog block. This is mainly done via the preamplifier’s NMOS block which is used for distributing the pre-amplifier signal (cf. Chapter 3, Section
3.3.1). For the following measurements, the gain of the pre-amplifier is set at the unity value.
147
Pre-amplifier Noise
Figure 4.21 : RMS Noise of pre-amplifier output. The average noise is 218 µV with a standard
deviation of 2.7 µV.
In Figure 4.21 the average RMS noise for all channel yields the value of 218.5 µV with a standard
deviation of 2.7 µv. The noise level of the pre-amplifier output is particularly low and nothing
particular can be noted about the pre-amplifier noise.
FSU Noise
Figure 4.22 : RMS Noise of FSU output. Oscillations (highlighted in dashed red box) are observed on
channels 0-10 for feedback capacitance, Cf = 25 fF.
The noise measurements of the Fast Unipolar Shaper (FSU) shaper are shown in Figure 4.22. As
stated in Chapter 3 (Section 3.4.2), FSU shaper has variable feedback capacitance (Cf) and resistance
148
(Rf). The RMS noise measurements were done for the combination of the Cf values (25 fF, 100 fF and
175 fF) and Rf values (25 kΩ, 50 kΩ and 100 kΩ). The noise measurements in Figure 4.22 are
organized according to the Cf values: 175 fF for top plots, 100 fF for middle plots and 25 fF for
bottom plots. However there is also unexpected behaviour from FSU when Cf is set at 25 fF. The
measurements for Cf = 25 fF are reproduced in Figure 4.23.
Figure 4.23 : RMS Noise of FSU output for Cf = 25 fF vs Rf= 25, 50 and 100 kΩ. High RMS noises due to
oscillations are observed from channel 0 to channel 10.
As can be seen in Figure 4.23, the noise level of each measured configuration is relatively high
between channel 0 and channel 10. It is most likely caused by oscillations at FSU output. From
simulations done in Chapter 3, it is known that for Cf = 25 fF, the response of FSU presents noticeable
ringing. The observed ringing is a good indication that the phase margin of this configuration is
reduced. However, this condition is not enough in order to have sustained oscillations. Unfortunately
the exact reason of why oscillations occur only for channel 0-10 is not known. This condition basically
excludes the configurations of FSU with Cf = 25 fF from being used.
The average values for each FSU configuration is summarize in the table below.
Feedback capacitance, Cf
25 fF
100 fF
25 kΩ ± 17%
4.75
2.19
50 kΩ ± 17%
10.7
3.22
100 kΩ ± 17%
7.63
3.82
Table 4.2 : Measurements of FSU RMS Noise
FSU average RMS Noise (mV)
Feedback
Resistance,Rf
175 fF
1.47
2.18
2.81
From Table 4.2, we can retrieve several information about FSU behaviour according to Cf and Rf
values. For a particular Cf value the RMS noise will increase when the feedback resistance (Rf) is
increased as well. Furthermore the RMS noise will decrease for bigger feedback capacitance Cf values.
Both behaviours are expected as Rf will set the gain and Cf will limit the bandwidth of FSU. Therefore
the configuration of Rf = 25 kΩ and Cf =175 fF is particularly interesting as it can yield the lowest
149
average RMS noise which is at 1.47 mV with the standard deviation of 0.14 mV. Due to its good
noise performance, this configuration is used for other FSU measurements.
VFS Noise
Figure 4.24 : RMS Noise of VFS output. The average noise is 1.3 mV with a standard deviation of 0.12
mV.
The RMS noise measurements were also done for Very Fast Shaper (VFS) output. Just like the preamplifier output, there is nothing peculiar about the measured RMS noise. From Figure 4.24, the
average noise of VFS is 1.3 mV with a standard deviation of 0.12 mV. The noise of VFS and its
dispersion of 9.3% are reasonable for a multichannel ASIC like SPACIROC.
KI Time-Over-Threshold Noise
Figure 4.25 : RMS Noise of KI Time-Over-Threshold. The average noise is 468 µV with a standard
deviation of 0.8 µV.
150
The RMS noise of the KI Time-Over-Threshold is shown in Figure 4.25. The average RMS noise is
around 468 µV with a standard deviation of 0.86 µV. Just like other analog components in this ASIC,
the noise for this module is rather low and nearly uniform for all channels.
4.3.2.2 Digital Noise
For a mixed signal ASIC like SPACIROC, it is particularly important to check the influence of the digital
noise. For SPACIROC, the digital part could contribute greatly to the analog noise performances as
there are 9 digital modules which operate in parallel in this ASIC. These digital modules are running
continuously as long as the GTU and system clocks are provided to the ASIC. Furthermore, there are
10 parallel output lines where high-speed digital output buffers are used.
For the following, the RMS noise measurement was done on the FSU shaper. By measuring the FSU
output, the digital noise influences can be verified on the pre-amplifier and the shaper itself.
Figure 4.26 : RMS Noise of FSU for Cf = 175 fF and Rf = 25 kΩ. The average RMS noise with digital part
is 1.88 mV ±16% (blue plot). The same measurement without digital part running is 1.47 mV ±9.5%
(orange plot).
The measurement done in Figure 4.26 is done for FSU configuration which has the lowest RMS noise:
for Cf = 175 fF and Rf = 25 kΩ. From the lower plot of Figure 4.26, the average RMS noise is measured
at 1.47 mV, when the digital part is turned off. The upper plot of the same figure is showing the
measurement for the same FSU configuration with the digital part of the ASIC running. The average
RMS noise is increased to 1.88 mV. It is also interesting to note that some channels exhibit noise
values much higher than average. This behaviour mainly concerns the channel 0-4 and channel 57-63.
The RMS noise spread between channels is at 16% which is quite high.
In order to determine how the digital noise spreads into the analog part, several verifications have
been carried out. Firstly, the pre-amplifier was disabled in order to see the digital noise influence on
151
FSU shaper. Figure 4.27 shows the waveforms of three selected channels of FSU. Channel 1 and 61
are selected from the channels where the RMS noise is higher than average. For comparison, the
waveform of channel 28 is also taken. From the figure, the glitches from the digital part are clearly
visible. The spikes seen in the waveform are corresponding to readout state machine transitions of
the digital part, on top of the waveform generated by the system clock. The RMS measurement for
the three channels gave identical values which are around 0.98 mV. This is an indication that the
digital noise spreads to the whole ASIC through its substrate.
Figure 4.27 : Digital noise substrate coupling on FSU output. The pre-amplifier is turned off. The
maximum RMS noise is at 0.98 mV.
Figure 4.28 : Digital noise substrate coupling on FSU output. The pre-amplifier is turned on. The
maximum RMS noise is at 3.3 mV.
152
The same measurements were done by turning on the pre-amplifier with unity gain (Figure 4.28). The
digital spikes are amplified especially on the channel 1 and 61. This behaviour is most likely due to
noise pickup through the substrate. The pre-amplifier ground was also polluted by the glitches
created by the ASIC digital part. As the input path of each channel is not located equally from the
digital part, the pre-amplifier channels 0-4 and 57-63 are most likely to exhibit higher noise due to
the channel positioning. From Figure 4.28, the RMS values for FSU outputs are 2.97 mV and 3.3 mV
for channel 1 and 61 respectively. Whereas the RMS noise for FSU channel 28 is at 1.92 mV which is
close to the average RMS noise shown in Figure 4.26.
Figure 4.29 shows the relative positioning of the ASIC input to the digital part.
Figure 4.29 : SPACIROC input positioning. The channels which exhibit higher than average RMS noise
have input located either on top or bottom pins row.
4.3.2.3 Pre-amplifier Equivalent Noise Charge
As shown in Chapter 3 (Section 3.3.1.3), the noise sources of the ASIC are mainly dominated by the
pre-amplifier stage which consists of a Super Common Base (SCB) amplifier and a PMOS mirror Gain
correction. Typically the pre-amplifier noise can be expressed in terms of Equivalent Noise Charge
(ENC) in electrons. ENC can be expressed as following:
⁄
With
is the input charge,
is the output RMS noise and
is the output amplitude.
The output, , is obtained after filtering or shaping the pre-amplifier signal. Therefore, the ENC
measurements could be represented as a function of the timing parameters of the output signal as
shown in the following figure.
153
Figure 4.30 : Hypothetical ENC plot representing the slopes of voltage noise (series noise) and current
noise (parallel noise) contributions.
From the plot in Figure 4.30, the components of ENC can be expressed as following:
With
is series noise,
is the parallel noise and
is the 1/f or flicker noise.
In the case of this ASIC, only parallel and series noise contributions are taken into account. When
taking into account the characteristics of the filter or shaper used to obtain the output signal, ENC
can be expressed as the following:
√(
Where
√
: shaper peaking time (ns),
capacitance (pF),
)
(
√
√ )
: voltage noise (
√
and
),
: current noise (
√
),
input
are the shaper coefficients.
The shaper coefficients are given below.
CR-RC
CR-(RC)²
CR-(RC)3
190
174
148
190
142
98
Table 4.3 : Coefficient for calculating ENC for different type of shapers
Shaper
For the ENC measurement of the SPACIROC pre-amplifier, an external CR-(RC)² shaper is used. The
measurement is shown in Figure 4.31. Additional capacitor (Cd = 15, 22, 39 and 69 pF) is used to
simulate the detector capacitance and verify the variation of the ENC with Cd.
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Figure 4.31 : Pre-amplifier ENC vs CR-(RC)² shaping time. Pre-amplifier gain = 1. The operating region
for this ASIC which is between 10 ns to 20 ns is highlighted in dashed green box.
From the plot in Figure 4.31, the parallel noise is dominant for slow shaping time (e.g. 1 µs) and fairly
constant for any capacitance values. This is a typical characteristic of a current amplifier especially
one with unity gain. On the other hand, the series noise contribution increased as a function of the
input capacitance especially for the small shaping time. For fast counting application like JEM-EUSO
which requires small shaping time (10~20 ns), the series noise could be non negligible. For example,
the ENC for 10 ns shaping time with only onboard parasitic capacitance (estimated around 50 pF) is
around 9 ke- rms. From measurement, the extracted noise values are
and
√
√
for series and parallel noise respectively. Both extracted values are somewhat higher than simulated
values which are
√ and
√ . The additional parallel noise most likely comes from
the biasing stage which was not taken into account into simulations and also other stages which are
connected to the pre-amplifier. Any current noise source at the pre-amplifier signal path will be
referred to the input directly as the consequence of unity current gain. However, it is much more
difficult to explain the difference of the series noise. One reason could come for the measurement
itself where the series noise fit depends on the equivalent input capacitance and it could give
unreliable result. On the other hand the fit of parallel noise doesn’t depend on input capacitance
value and it is quite reliable. Other possibility of additional series noise is the stray resistance int the
input. But it is unlikely to generate
of 400 Ω.
√
extra noise which requires an equivalent resistance
After the extensive noise measurement, we can conclude the noise performance of this ASIC is
satisfying enough with the ENC noise of 9 ke- rms. Even though the noise value is not uniform on all
channel due to digital part, the noisiest channel should be good enough for triggering at 50 fC (1/3
p.e of 106 MAPMT gain) input charge. It will be confirmed in the following sections which are
dedicated for Photon Counting triggers.
155
4.3.3 DAC measurement
The measurement has been done on all 10-bit DACs available on this ASIC in order to check the least
significant bit (LSB), linearity and voltage range. The first 2 DACs are used for the Photon Counting
part (DAC FS and DAC PA). The remaining 2 DACs (DAC KI SUM and DAC KI Dynode) are used for the
KI Time-Over-Threshold.
Figure 4.32 : DACs measurements without bias modification.
For the measurements done in Figure 4.32, the characteristics of the DAC are obtained from the
default biasing values and without external modification. The linearity of the DAC is quite good as the
residuals from the linearity fit are around 0.2%. For DAC FS and DAC PA, the saturation occurs around
DAC 840 (2.654 V) and DAC 811 (2.599 V) respectively. On the other hand, the saturation for KI DACs
occurs at higher values: DAC 945 (2.908 V) and DAC 960 (2.909 V) for DAC KI Dynode and DAC KI SUM
respectively. The summary of the DACs characteristics are listed in Table 4.4.
DAC
FS
PA
KI Dynode
KI SUM
Slope/LSB (mV)
Min (V)
Max (V)
2.18
0.8446 (DAC 0)
2.6542 (DAC 840)
2.19
0.8468 (DAC 0)
2.5991 (DAC 811)
2.17
0.8443 (DAC 0)
2.9084 (DAC 945)
2.2
0.8428 (DAC 0)
2.9091 (DAC 960)
Table 4.4 : DACs characteristics. Default biasing.
From Table 4.4 the least significant bit (LSB) of the DACs are roughly around 2.2 mV. This value is
slightly higher than the expected LSB of 1.88 mV (Chapter 3 - Section 3.6). In order to decrease or
increase the LSB voltage, the DAC reference voltage can be modified externally by using an additional
resistance. The measurements shown in Figure 4.33 were done with an external resistance of 280 kΩ .
156
Figure 4.33 : DACs measurements with DAC reference modifications. External resistance = 280 kΩ.
From the plots in Figure 4.33, the DAC LSB (~1.75 mV) has been reduced and the excursion of DAC FS
and PA has been improved as well. The characteristics of the DAC with the new reference are
summarized in the following table:
DAC
FS
PA
KI Dynode
KI SUM
Slope/LSB (mV)
Min (V)
Max (V)
1.75
0.9024 (DAC 0)
2.6683 (DAC 1021)
1.76
0.9064 (DAC 0)
2.6081 (DAC 981)
1.76
0.9033 (DAC 0)
2.6868 (DAC 1023)
1.74
0.9065 (DAC 0)
2.6061 (DAC 992)
Table 4.5 : DACs characteristics with bias modification.
4.3.4 Double Pulse Resolution
The Double Pulse Resolution has been measured for the Photon Counting part. It is done by injecting
2 inputs of 1 p.e each, which is separated by a certain delay. The threshold is set around 1/3 p.e in
order to trigger both inputs. The delay between both inputs was slowly decreased until there is no
clear trigger generated separately for both inputs. An example of the input pulses is shown in Figure
4.34(a) and the waveforms of the analog output (FSU in this case) are plotted in Figure 4.34(b).
157
(a)
(b)
Figure 4.34 : (a) Inputs separated by 30 ns. (b) FSU waveforms for input charge separated by 30 ns.
The trigger separation is confirmed statistically by the digital data. Figure 4.35 (a) shows an example
of digital output for counting value of 2. Figure 4.35 (b) is more interesting plot, as it shows the
counting error ratio of nearly 50% when the input pulse is separated less than 30 ns for FSU trigger.
(a)
(b)
Figure 4.35 : (a) Example of counter data for the value of 2 hits. (b) Statistical errors when the inputs
are separated lower than 30 ns (for FSU).
Photon Counting Trigger
Double Pulse Resolution
Pre-amplifier - Trig_PA
36 ns
FSU(Cf = 175 fF, Rf = 25 kΩ) – Trig_FSU
30 ns
VFS – Trig_VFS
20 ns
Table 4.6: Photon Counting Double Pulse Resolution.
For the following, FSU is considered as the baseline for the Photon Counting especially for the
feedback configuration of Cf = 175 fF and Rf = 25 kΩ. This is mostly because of the noise performance
and also the reasonable pulse separation of 30 ns. The Pre-amplifier Trigger is also a good candidate
for the baseline, but the Double Pulse Resolution is slightly bigger than the FSU trigger. On the other
hand, the VFS trigger is not considered although the Double Pulse Resolution is at 20 ns. This is
mostly due to the discriminator design which induces a lot of trigger performance discrepancies
between 64 channels. This problem will be seen later in the trigger S-curves measurement section.
158
4.3.5 Trigger S-curves
One of the most important aspects of Photon Counting is the triggering efficiency. Typically it is done
by sweeping the threshold (DAC) for a given injected charges. The resulting plot is known as S-curves
which is in fact the cumulative distribution function of the probability to generate a trigger. For the
Photon Counting, the minimum charge required by JEM-EUSO in order to achieve 100% triggering
efficiency is 50 fC (1/3 p.e for MAPMT gain of 106).
Figure 4.36 : Pre-amplifier Trigger (Trig_PA) S-curves for 50 fC input charges.
Figure 4.37 : Distribution of Trig_PA 50% triggering efficiency for 50 fC input charges.
159
Figure 4.38 : FSU trigger(Trig_FSU) S-curves for 50 fC input charges.
Figure 4.39 : Distribution of Trig_FSU 50% triggering efficiency for 50 fC input charges.
160
Figure 4.40 : VFS trigger(Trig_VFS) S-curves for 132 fC input charges.
Figure 4.41 : Distribution of Trig_VFS 50% triggering efficiency for 132 fC input charges.
161
For Trig_PA and Trig_FSU, all 64 channels are able to trigger at 50 fC. However for Trig_VFS triggering
chain, a minimum input of 132 fC is required in order to achieve 100% triggering efficiency for all
channels. It seems that the discriminator design for Trig_VFS exhibits a very huge dispersion between
each channel. The S-curves results are summarized in Table 4.7.
50% Triggering Efficiency
Photon Counting AveragePedestal
Min Threshold
Trigger
(DAC)
(DAC)
Mean (DAC)
RMS (DAC LSB)
Trig_PA
952
948
941.64
1.18
Trig_FSU
76.7
84
93.7
2.5
Trig_VFS*
NA
80
170.93
17.69
*Due to problems with Trig_VFS discriminator, the pedestal and the minimum DAC can’t be determined via S-curves.
Table 4.7 : Characteristic of Photon Counting Trigger.
From Table 4.7, the RMS for 50% triggering efficiency of Trig_PA and Trig_FSU are quite reasonable.
The RMS values are 0.713 DAC LSB and 2.5 DAC LSB for Trig_Pa and Trig_FSU respectively. However,
for Trig_VFS the dispersion for 64 channels is at 17.69 DAC which is quite high.
The dispersion of Trig_VFS is partly caused by its discriminator design. Unlike the discriminators for
Trig_PA and Trig_FSU, the one for Trig_VFS is designed differently in order to improve the response
time. The basic idea behind the design is to unbalance the discriminator’s differential stage and to set
this differential stage output very close to the Vt (threshold voltage) of PMOS transistor. In theory
the discriminator is very responsive but in practical the response time varies from channel to channel.
This is due to the dependence of the Vt on transistor process variations. This behaviour has been
confirmed by corner simulations which take into account process dispersion as well.
162
4.3.6 Photon Counting Gain Measurement
Data from S-curves can also be used for verifying the gain and to determine the minimum detectable
signal of Photon Counting. By establishing the 50% triggering efficiency as a function of the injected
input charge, the gain can be deduced from the slope of the curve. Furthermore it could also give a
good indication of the triggering chain linearity as a function of the input charge. From each trigger
output of Photon Counting, the measurements are done for 3 selected channels based on the
measurement the RMS noise done in previous section (Section 4.3.2.2). 2 channels are selected in
the zone where the RMS noise is higher than average (channel 0-4 and 57-63). The remaining
channel is chosen from the zone of channel 5-56 where the RMS noise measurement is within the
average value. The charge injection is done by using the 1 kΩ resistor in order to inject a short input
pulse with 2 ns of maximum half width, as explained at the beginning of the Section 4.3.
Pre-amplifier Trigger (Trig_PA)
For the Pre-amplifier Trigger, the measurement is done for channel 1, 28 and 61. The pre-amplifier
gain is set the unity value. For the injected charge, it is done for input from 10 fC to 520 fC which
correspond to 1/16 p.e to 3.25 p.e for 106 MAPMT gain. Figure 4.42 shows the measurement results
for channel 28.
Figure 4.42 : Trig_PA Channel 28 - 50% Triggering Efficiency vs Input Charges.
Channel
Gain
(mV/fC)
Best
Worst
0.4
0.43
Min
50%
Analog
Pedestal
Amplitude
Charge
[email protected]
SNR
(DAC)
@1p.e (mV)
(fC)
(DAC)
@1p.e
20
918.28
885.64
57.44
33
30
917.22
877.2
70.4
44
Table 4.8 : Characteristics of Pre-amplifier Trigger.
Non
linearity
@2p.e
17%
16%
The characteristics of Trig_PA are particularly important as it reflects the characteristic of the Super
Common Base amplifier and PMOS Gain Correction of the input stage of this ASIC. The minimum
163
detectable signal is set at 30 fC by channel 1 which is one of the noisiest channels in this ASIC. The
amplitude for the pre-amplifier signal can also be extracted from the 50% triggering efficiency plot.
For example, the amplitude for 160 fC (1 p.e) input of channel 28 can be calculated as following:
50% Triggering Threshold – Pedestal = (885.64 – 918.28)* DAC LSB = -32.64*1.76 mV = -57.44 mV
With Trig_PA DAC LSB = 1.76 mV.
The amplitude of the pre-amplifier output for each channel is summarized in Table 4.8. Even though
the obtained amplitude is much bigger than the measurement on oscilloscope (~15 mV), it is still
lower than the simulated values (~70% smaller).
FSU Trigger (Trig_FSU)
The same measurements done for Trig_PA were repeated for Trig_FSU. The configuration chosen for
FSU is Cf = 175fF and Rf = 25 kΩ. This configuration is chosen as it can give the lowest noise
performance on the analog output. The measurement results for channel 28 are shown Figure 4.43.
Figure 4.43 : Trig_FSU Channel 28 - 50% Triggering Efficiency vs Input Charges.
Channel
Gain
(mV/fC)
Best
Worst
1.11
1.1
Min
50%
Pedestal
Amplitude
Charge
[email protected]
(DAC)
@1p.e (mV)
(fC)
(DAC)
20
78.13
171.86
164
30
75.39
161.74
151.1
Table 4.9 : Characteristic of FSU Trigger.
Analog
SNR
@1p.e
93
54
Non
linearity
@2p.e
1.4%
2.3%
For FSU, the extracted amplitude from the measurement and the measured amplitude on
oscilloscope of 1 p.e (160 fC) input show a difference of nearly 40 mV. For the injected charges of 20 160 fC, the extracted amplitude from the triggering efficiency plots is 20% less than the values
measured on oscilloscope. One of the plausible explanations is most likely that the counter in the
164
ASIC missed the trigger edges towards the end of the threshold sweep. In any case, the extracted
amplitude is still much lower than the simulated one which is at 325 mV for 1p.e input. Otherwise
the Trig_FSU shows a good linearity up to 2 p.e, which is a better performance than Trig_PA seen
previously. On the other hand, the minimum input is identical to Trig_PA which is at 30 fC.
VFS Trigger (Trig_VFS)
For Trig_VFS, channel 1, 32 and 63 are selected for the measurement. The results of the
measurements are plotted in the following figure:
Figure 4.44 : Trig_VFS Channel 32 - 50% Triggering Efficiency vs Input Charges.
Channel
Gain
(mV/fC)
Best
Worst
1.29
1.41
Min
50%
Pedestal
Amplitude
Charge
[email protected]
(DAC)
@1p.e (mV)
(fC)
(DAC)
23
NA
178.7
175.1
62
NA
187.9
188.9
Table 4.10 : Characteristic of VFS Trigger.
Analog
SNR
@1p.e
156
73
Non
linearity
@2p.e
2%
3.3%
As shown previously, due to the design problem of Trig_VFS discriminator, there is a huge dispersion
between channels for the trigger response. Furthermore the discriminator problem makes that it is
impossible to extract the pedestal information by using the the S-curves information. In order to
estimate the 1 p.e amplitude of VFS, the pedestal has to be taken from the multimeter measurement
in Section 4.3.1. The amplitude for 1 p.e is found between 175.1 mV and 200.7 mV for the measured
channel. The amplitude range is higher than oscilloscope measurement (99 mV) but still smaller than
simulated values (504 mV). Also from Table 4.10 the minimum detectable signal is found at 63 fC
which is higher than the value found for Trig_PA and Trig_FSU which is at 30 fC. The difference
mainly comes from the noise of the analog signal and also the sensitivity of the discriminator.
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Pre-amplifier linearity for different gain settings
As explained earlier, the pre-amplifier linearity can also be measured by checking the S-curves as a
function of the input charge. The measurements in Figure 4.45 were done for different gain of preamplifier which is mainly set by the ratio of current copied of the PMOS current mirror.
Figure 4.45 : Trig_PA Channel 28 - 50% Triggering Efficiency vs Input Charges for PMOS mirror gain =
0.5,1,2 and 4.
PMOS
Mirror
Gain
0.5
1
2
4
Min
50%
Analog
Non
Pedestal
Amplitude
Charge
[email protected]
SNR
linearity
(DAC)
@1p.e (mV)
(fC)
(DAC)
@1p.e.
@2p.e
0.17
40
918.24
901.95
28.7
32
10%
0.4
20
918.28
885.64
57.44
33
17%
0.85
20
918.15
843.04
132.2
94
19%
2.06
20
918.08
749.39
298.8
168
6%
Table 4.11 : Characteristic of pre-amplifier for PMOS mirror gain = 0.5,1,2 and 4.
Gain
(mV/fC)
From Table 4.11 we can see that for 1 p.e input response, the pre-amplifier varies linearly according
to the gain value. As PMOS mirror stage is used to correct the dispersion of the MAPMT gain
(nominal value 106), the linearity for 1 p.e response is obviously a very important aspect.
Summary of Photon Counting performances
Based on the various measurements which have been carried out, we can conclude that at least
Trig_PA and Trig_FSU can be used for general photon counting applications. On the other hand,
Trig_VFS can operate to certain extent but we are quite sceptical about the stability of the VFS
shaper. Both Trig_PA and Trig_FSU triggering schemes have very good performances in terms of
noise, stability and timing. Trig_PA would be very suitable for applications which are not requiring
very high speed counting. For fast counting applications which require the Double Pulse Resolution of
a few tenths of ns, we have little doubt that Trig_FSU would not fit the requirements.
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4.3.7 Time-Over-Threshold Measurement
The functionality of the KI Time-Over-Threshold has been verified under laboratory conditions. There
are two important parameters in this part which are Dynamic Range (DR) capacitors and Width
Adjustment (WA) current source. The first parameter will have an influence on the input dynamic
range. In other words, the DR capacitance values will determine the minimum input capable of
generating a trigger and also the amplitude of the charge integration. On the other hand, the current
source adjustment, WA, will set the discharge slope of the analog signal and eventually the trigger
width. The discharge slope is closely linked with the values of DR capacitance as given by this
relation :
.
Unlike the Photon Counting part, the charge injection is done via 10 pF capacitors on the test board.
The charges are injected simultaneously into 8 channels.
The first measurement done is to check the output amplitude as a function of input charge and the
DR capacitance. Figure 4.46 shows the plots of measurements done on the oscilloscope. The
measurement is done in the condition where the trigger is not generated from this Time-OverThreshold block. Therefore the amplitude here doesn’t reflect the integrated signal. As a reminder,
the KI block will start to integrate the input signal if a trigger is generated.
(a)
(b)
Figure 4.46 : KI Analog for DR capacitance values of 16 pF,24 pF and 26 pF. (a) Qin = 1.28 pC, (b) Qin
= 6.4 pC. These plots shows the adjustment capabilities of this ToT module.
From Figure 4.46 (a) and (b), the amplitude of the KI analog signal is affected by the DR capacitance.
The smallest capacitance values at 16 pF yields the highest amplitude and could give the lowest
detectable signal as the threshold has to be set according to the KI analog signal amplitude.
Theoretically the amplitude of the analog signal is given by the equation :
where V is the
analog amplitude, Q is the input charge and C is the capacitance values. For example by taking the
value of 16 pF, for an input charge of 1.28 pC (8 p.e for 106 MAPMT gain), the analog amplitude
should be equal to: V = 80 mV. From Figure 4.46, the output amplitude for the same DR capacitance
value and input charge is around 17 mV which is 5 times smaller than theoretical 80 mV value. This
discrepancy comes from several reasons. The charge transfer from the ASIC input until the DR
capacitance is not perfect as the input charges are transferred through several stages. Secondly the
integrated charge of the capacitor could be discharged immediately through the voltage reference of
167
this Time-Over-Threshold block. Therefore this effect could attenuate the observed amplitude. Lastly
the loading effect will also attenuate the analog signal as the observation is done on an oscilloscope.
The next measurement was done by setting the DR capacitance at 16 pF, WA current source at 4 µA
and the threshold 20 mV below the baseline (~1.5 V). The WA current source is set at one of the
lowest value available so the amplitude of the integrated pulse can be maximised and not disturbed
by this current source.
Figure 4.47 : KI Analog for DR capacitance values of 16 pF and WA value of 4 µA. Injected charge Qin
= 6.4, 12.8 and 25.6 pC. The width of the analog signal increases according to the amplitude of the
injected charges.
The expected amplitudes of 6.4, 12.8 and 25.6 pC injected charges for 16pF capacitance are 400 mV,
800 mV and 1.6 V respectively. However the measurements (Figure 4.47) only yield the value of 160
mV, 320 mV and 520 mV for 6.4 pC, 12.8 pC and 25.6 pC of input charge respectively. The measured
signal is nearly 3 times lower than the expected signal. Most of the amplitude loss can be attributed
to input signal transfer.
The discharge slope of the integrated signal is also checked as it is one of the important aspects of
this Time-Over-Threshold block. Figure 4.48 are shows the various discharge slopes as observed on
oscilloscope.
Figure 4.48 : KI discharge slope for DR capacitance values of 16 pF and WA current source varies
from 6 µA to 32 µA. The mechanism for tuning the slope works as expected.
168
The measurements of the KI discharging slope according to various combinations of DR and WA
setting are summarized in Table 4.12. As indicated in Table 4.12, the measured slopes are agreement
with the simulation values.
Slope(mV/µs)
DR=16 pF
DR=24 pF
DR=46 pF
Sim
Measure
Sim
Measure
Sim
Measure
6µA
265
214
187
150
99
84
10µA
492
363
357
275
189
136
18µA
936
700
682
550
362
300
32µA
1608
1273
1222
880
651
600
Table 4.12 : KI integration slope vs WA. The DR capacitor is set at 16, 24 and 46 pF.
WA
The following figure shows the dynamic range of KI by using charge injection. In this measurement,
the charge injection is synchronised to the GTU where one pulse is injected every GTU. The input
charge is injected into 64 channels simultaneously in order to check the functionality of the 8channel KI.
Figure 4.49 : KI 8-Pixel-Sum count linearity versus input charge. The DR capacitor is set at 28 pF and
WA current source is equal to 22 µA. Instable charge measurements (< 4 pC) area is highlighted in
dashed green circle.
From the measurement done in Figure 4.49, each KI channel can handle input charge ranging from 4
pC up to 240 pF for a single pulse charge injection and the saturation starts to appear around 20 pC.
For a charge below 4 pC, there are slight variations of the value as the analog signal of KI was unable
to settle for charge integration or not. This behaviour is due to the fact the input signal is weak and it
could not produce a stable trigger output for the KI. For this Time-Over-Threshold design, a stable
trigger output from the discriminator is crucial as the trigger signal is used to control the discharging
path of the integrated signal as explained in Chapter 3. Otherwise, it could produce some sort of
“oscillations” as the discharging path of the DR capacitance could keep switching between the
constant current source (WA) and the DC voltage reference of KI. This behaviour can be seen when
169
the input signal is not strong enough, the small values of WA (<2 µA) and the threshold for KI is set
too close to the analog signal baseline. This behaviour doesn’t disturb the global operations of this
chip as low charge measurements (i.e < 5 pC) is handled by the Photon Counting part.
For the KI Dynode input, several measurements have also been carried out in order to check its
functionality. The following figure shows the measurement of this part.
Figure 4.50 : KI Dynode count linearity versus input charge. The DR capacitor is set at 16 pF and 24 pF
and WA current source is equal to 18 µA. This circuit also couldn’t offer stable measurements below
4 pC (highlighted in dashed green circle).
For the measurement of the dynode part, the charge injection was also done with a capacitance and
the input rate is synchronised to the GTU. From Figure 4.50, the measurement can only be done up
to 32 pC. Although the exact reason is not known, it seems that the ASIC can’t take input beyond 32
pC which can yield a current peak of 6.4 mA.
The measured charge injection doesn’t reflect the reality of the JEM-EUSO experiment, as the charge
injection could not simulate the arrival of photons during an Extensive Air Shower (EAS) development.
Moreover the arrival photon rate varies greatly within a GTU and it can hit only several pixels instead
of full 8 pixels which correspond to 1 KI channel. Otherwise, the laboratory measurements give a
good indication on how the circuit can handle the input charges. Much more accurate measurements
for the EAS will be done during MAPMT tests in the following section.
170
4.3.8 MAPMT Measurements
A series of tests using MAPMT has been carried in France and also in Japan. The huge advantage of
testing by using the MAPMT is to have a setup which is nearly identical to JEM-EUSO running
conditions. In other words, this setup could reproduce realistic physics conditions where the photon
would arrive randomly and uniformly. Therefore it is a perfect measurement method for Time-OverThreshold in order to establish the charge measurement of photons generated from Extensive Air
Shower. Meanwhile, the influence of photoelectron distribution will influence the pile up on the
Photon Counting part and it could be verified as well.
(a)
(b)
(c)
Figure 4.51 : (a) Black box for the MAPMT test. (b) Internal view of the black box. (c) SPACIROC
testboard with mounted MAPMT.
The purpose of the measurements with the MAPMT is the following:


To characterise the ASIC and the readout system exposed to the photons similar to JEMEUSO running conditions
To establish a practical procedure for MAPMT sorting and pixel calibration.
To carry out the test, the MAPMT has to be first measured in order to know the gain and eventually
its efficiency. SPACIROC has been designed to readout a MAPMT with the gain of 106 in order to have
a Single Photo Electron signal of 160 fC. Therefore it is necessary to know accurately the gain of the
MAPMT which is used during the test. Another reason for calibrating the MAPMT, is this ASIC doesn’t
171
include an ADC for providing the spectrum of photoelectron distribution. Unfortunately the
sensitivity of the Time-Over-Threshold block is not low enough in order to read single photoelectron
signal. By using the Photon Counting, the spectrum of photoelectron can be obtained, but it is not
precise enough to be used as an absolute MAPMT gain measurement.
The MAPMT test has been carried out with the 64-pixel HAMAMATSU R11265-M64 as shown in the
following figure.
(a)
(b)
Figure 4.52 : MAPMT mounted on SPACIROC test board. (a) MAPMT mounted with Hamamatsu high
voltage power supply base. (b) MAPMT mounted directly on the test board.
In order to measure the MAPMT gain, a CAMAC charge-ADC has been used. The test setup for
measuring MAPMT gain by using CAMAC charge-ADC is shown below.
Figure 4.53 : MAPMT Test setup for gain measurement. The UV LED (λ = 378 nm) is pulsed at 100 kHz.
An integrating sphere is used to split the light in are repetitive way to MAPMT and NIST photodiode
(light measurement). The CAMAC charge-ADC is also pulsed at 100 kHz and receives amplified
MAPMT anode signal. The data acquisition is done via LabVIEW.
172
A LED of 378 nm wavelength is used to generate the fluorescence light and it is pulsed at 100 kHz.
The intensity of the light is set until the ratio of the single photoelectron peak is around 1% of the
pedestal (cf. Chapter 5 – Section 5.1). The light intensity is measured with a NIST photodiode as
shown in Figure 4.53. The output of the MAPMT anode is amplified before it is sent to the chargeADC. The gate for the charge-ADC is set at 10 ns. Below is an example of the R11265-M64
photoelectron spectrum obtained from CAMAC charge-ADC.
Figure 4.54 : HAMAMATSU R11265-M64 photo electron spectrum with a measured gain of 0.16 pC. 1
ADC channel corresponds to 10 fC.
The spectrum shown in Figure 4.54 corresponds to the measurement done for pixel 36 of the
HAMAMATSU R11265-M64 MAPMT. The pixel 36 is centrally located (Figure 4.55) within the MAPMT
and typically exhibits better gain than other pixels. Therefore the pixels around this region are often
used as the reference when calibrating other pixels. Important information that can be obtained
from the gain measurement is the high voltage power supply on the MAPMT cathode (K). For
example the cathode voltage required for 106 gain in measurement of Figure 4.54 is 1000 V. Typically
for this type of MAPMT, the cathode voltage could vary from 900 V to 1000 V in order to obtain a
gain of 106.
Figure 4.55 : HAMAMATSU R11265-M64 to ASIC channel mapping. The positioning of MAPMT pixel
36 is highlighted by the red box.
173
Once the gain of the MAPMT has been measured, the setup has been changed in order to use the
ASIC for the MAPMT readout. As cited earlier, the MAPMT is mounted directly on the test board as
shown in Figure 4.52. The MAPMT test setup using the ASIC test board is shown in the following
Figure 4.56. This setup is also used for relative gain measurements and calibrations which discussed
in Section 5.1 of Chapter 5.
Figure 4.56 : MAPMT Test setup for S-curves measurement with SPACIROC test board. The test board
will trigger (frequency = 400 kHz) a pulse generator which will drive a UV LED (λ=370 nm). An
integrating sphere splits the light uniformly between the MAPMT and the NIST photodiode (light
measurement). The MAPMT anodes signals are fed directly to the ASIC and the data acquisition is
done through LabVIEW.
For the test setup using the ASIC test board, the LED pulse frequency is synchronized to the GTU
frequency which is at 400 kHz. In order to check the gain by using this ASIC, the S-curves can be used.
As the S-curves is the accumulative function of the Gaussian distribution, the distribution can be
obtained directly from the derivation of the S-curves. Just like the gain measurement with the
CAMAC charge-ADC, the light intensity has to be adjusted in order to have 1% of the single
photoelectron distribution over the pedestal. Figure 4.57 shows an example of the photoelectron
distribution from this ASIC with 1 photoelectron/GTU.
174
Figure 4.57 : HAMAMATSU R11265-M64 pixel 36 photoelectron spectrum obtained from the ASIC Scurves derivation with 1 photoelectron/GTU.
For the measurement done in Figure 4.57, the FSU trigger (Trig_FSU) is used and the settings of the
feedback capacitance, Cf, and resistance, Rf, are set at 175 fF and 25 kΩ respectively. The peak of
single photo electron from our measurement is estimated around 160 DAC value. With the pedestal
value of 90 DAC, the average FSU amplitude for 1 p.e can be calculated as following:
With
,
and
When comparing to the measurement results from Section 4.3.6, the obtained FSU amplitude for
single photoelectron is in agreement with the laboratory test result which is between 151.1 mV and
164 mV.
4.3.8.1 MAPMT tests for Photon Counting and Time-Over-Threshold
The purpose of the tests is to investigate the pileup effects over Photo Counting part and to
determine the acceptable dynamic range KI Time-Over-Threshold. For the following measurement,
the MAPMT gain is set at 106.The setup of this test is nearly like the S-curves measurements (Figure
4.56) except for the LED which is powered by a DC power supply. As the LED is not synchronized to
any reference, the photon would arrive randomly as the running condition of JEM-EUSO experiment.
Furthermore the arrival photon intensity can be adjusted by the DC power supply in order to
simulate the Extensive Air Shower photon intensity or arrival rate. Therefore this test system is
perfect for measuring the KI Time-Over-Threshold input dynamic range. The test setup is shown in
Figure 4.58.
175
Figure 4.58 : MAPMT Test setup for ASIC measurements with SPACIROC test board. The setup is
similar to the one in Figure 4.56 except for the UV LED which is driven by a DC power supply instead
of a pulse generator.
For the Photon Counting part, the FSU trigger is used and the settings of the feedback capacitance, C f,
and resistance, Rf, are set at 175 fF and 25 kΩ. The threshold is set at 1/3 of p.e which corresponds to
DAC 103 (1.062 V). At the beginning, the light intensity is set in order to obtain an average value of
1.510 photoelectron per GTU for the Photon Counting data. The light intensity for this value
corresponds to 250 nW when it is measured with a NIST integrating sphere. For the following, this
value (250 nW) will be the reference for the light intensity measurement. By scaling to this reference
value, the light intensity will be gradually increased in order to see the pileup in Photon Counting
part.
10
1.5 photoelectron per GTU is corresponding to the average background value for JEM-EUSO which is usually
attributed to the photons generated by the atmospheric Airglow and also refection of stars.
176
Photon Counting measurements
Figure 4.59 : Photo Counting pile up measurement. Each run is done for 1000 GTU frames for a total
of 8 runs.
From Figure 4.59, the Photon Counting part data are linear up to 25 p.e/GTU/pixel and follow the
same curve of photoelectron versus NIST integrating sphere measurement (Figure 4.67 - Yellow plot).
After this point, the Photon Counting part slowly reaches the maximum count of 33 hits/GTU/pixel.
Even though the data is around 33 hits, the measured light intensity is around 12.5 µW which
corresponds in reality to 75 p.e/GTU/pixel. With the increasing intensity of the photon flux, the
Photon Counting data gradually collapses as analog signal pile up occured. At the same time the DC
level of FSU starts to collapse which also contributes to the reduction of the Photon Counting data.
For this Photo Counting settings (FSU with Cf = 175 fF and Rf = 25 kΩ), the announced double pulse
resolution is at 30 ns and it was measured with two perfectly separated pulses. In theory, the Photon
Counting part could have a total of 83 hits in a GTU of 2.5 µs wide. However, from the measurement
in Figure 4.59, in average the pile up starts to manifest from 25 hits which is 3.3 times lower than the
theoretical value. The difference is partly due to the random arrival of the photons during the
measurement.
177
Time-Over-Threshold measurements
For the KI Time-Over-Threshold measurements, the method is fairly the same as the Photon Counting
part where the light intensity is raised gradually in order to increase the number of photoelectrons
within a GTU. For the measurements with MAPMT, the settings of the Dynamic Range (DR)
capacitance and the Width Adjust (WA) current source are set at 16 pF and 32 µA respectively. As the
input for the KI is mainly single photoelectron signals (thus small input charge), it is preferable to use
small DR values which can have the best input sensitivity. For the setting of WA, it is mainly chosen in
order to have the fastest integration time due to the number of photoelectrons which could arrive
within 1 GTU (>100 p.e/GTU/pixel).The measurements of the KI Time-Over-Threshold are shown in
Figure 4.60.
Figure 4.60 : KI dynamic range measurements according to the input pixel and light intensity. For
each number of pixel, the run is for 1000 GTUs.
At the beginning of the KI measurements, we were surprised that the KI data already showed
maximum value for light intensity which corresponds to 15 p.e/GTU/pixel. After investigations, this
behaviour is caused by 2 reasons:


The KI Time-Over-Threshold design doesn’t include any operation gate on the analog side.
Therefore, the charge integration is initiated by the input signal itself. It will not be a
problem for low input rate application (e.g. < 100 kHz), but it is not the case for JEM-EUSO
where the input rate is relatively high (> 400 kHz). After receiving inputs of 15 p.e, the analog
signal will be at its maximum for several GTUs which will induce errors for the following
charge measurement. What is more, the analog signal could only recover if there is no input,
which means some kind of reset or gate has to be implemented.
Other issues is the maximum discharge slope (DR = 16 pF and WA = 32 µA settings) is not fast
enough for JEM-EUSO application. Therefore to reach the desirable input rate of 150-200
p.e/GTU/pixel, the value of WA current source has to be raised. For the measurements, the
maximum WA current source is doubled to bring the value to 64 µA.
178
The measurements in Figure 4.60 were done with the adjustment on the WA current source. In these
measurements, the impact of each pixel is also investigated. From the plots, the data of the KI will
rise gradually (although not so linear), as a function of the quantity of pixels which are summed at
the KI input. Of course, the highest value is obtained when 8 pixels are used for the KI input.
The maximum value reached for the KI with 8 pixels summed input, is at 97 counts which is for the
light intensity of 30 µW (180 p.e (28.8 pC)/GTU/pixel or 230 pC/GTU/8-pixel). Subsequently, the
dynamic range for KI with 8-pixel-input is 5-150 p.e/GTU/pixel or 6.4-230 pC/GTU/8-pixel. The
resolution for this charge measurement is roughly 2.3 pC/Count. However, from the plots in Figure
4.60, it is impossible to distinguish the number of input pixel for a given KI data. Therefore the data
for the Photon Counting are required in order to determine how many pixels were hit.
Summary
The measurement of KI for 8 pixels sum is reproduced again with the Photon Counting data in Figure
4.61.
Figure 4.61 : Photo Counting and KI data for input range of 1-180 p.e/GTU/pixel.
The plots in Figure 4.61, represent the dynamic range of this ASIC in the JEM-EUSO running condition.
For this running condition, the Photon Counting part can cover the input range from 1 p.e to 25 p.e
per GTU for each pixel. Meanwhile for the KI with 8 pixels input, the charge measurement starts from
5 p.e/GTU/pixel, which is below the pile up of the Photon Counting part. The fact that the KI
measurement starts below the pile up level of the Photon Counting making that both components
will have an overlap between 5-25 p.e/GTU/pixel. Afterwards, the input dynamic range extension will
be handled by the KI part up to 180 p.e/GTU/pixel. Moreover, dynamic range extension is valid for
any number of pixels for the KI input as shown in Figure 4.60 albeit the limited resolution for low
number of input pixels.
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4.4 Conclusion
The measurements in laboratory conditions and with the MAPMT have been carried out in order to
characterize the ASIC. The laboratory tests have been very useful especially for characterizing the
general aspect of the ASIC such as the DC level, noise, power consumption, output amplitude and
data readout. The tests were also useful especially for checking the pre-amplifier stage and the
Photon Counting part where important characteristics like the linearity, the minimum detectable
input and the gain can be verified. Furthermore the functionality verifications and basic charge
measurements could be done for the KI Time-Over-Threshold under the laboratory charge injection
setup. The real conditions just like the JEM-EUSO experiment were able to be reproduced by testing
the ASIC with a 64-channel MAPMT and an UV-LED. Again, the tests were very fruitful where, the pile
up of Photon Counting could be verified and the real dynamic range for the KI could be established.
Additionally, the MAPMT tests were a good medium to see the limit of the KI design. By combining
both dynamic ranges, the ASIC could measure from 1-180 p.e/GTU/pixel which is suitable for
observing 1020 eV Air Shower. This is based on the instrument simulation results (refer to Figure 2.16
in Section 2.6) where the peak of a 1020 eV Air Shower would be around 40 p.e/GTU/pixel.
Table 4.13 summarizes the characteristics of SPACIROC ASIC.
Item
Power Consumption
Pre-amplifier gain
Pre-amplifier noise ENC
Gain
Photon
Min Input
Counting
Double Pulse Resolution
(FSU)
Dynamic Range (linearity)
Value
Specifications
1.1 mW/channel
< 1 mW/channel
0-4
1-3
9 ke- rms
< 25 ke- rms
1.1 mV/fC
N/A
30 fC
≤ 50 fC
30 ns
≤ 30 ns
1-25 p.e/GTU/pixel
1-30 p.e/GTU/pixel
5-180 p.e/GTU/pixel or
KI 8-pixel-sum Dynamic Range
1.9 – 192 pC/GTU/8-pixel
6.4-230 pC/GTU/8-pixel
Table 4.13 : SPACIROC ASIC characteristics
It can be concluded that this ASIC fits to the requirements for observing the Air Shower. However
there is room for improvements such as power consumption, Double Pulse Resolution and handling
high photon flux originated from other atmospheric phenomenon. These would be the motivations
to design a second version of SPACIROC ASIC. Details on the motivations of the second generation
ASIC design will be established later in Chapter 7 which concerns SPACIROC2 ASIC.
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Chapter 5 JEM-EUSO Calibration
In JEM-EUSO, the instrument calibration is one of the important steps towards the assembly and
commissioning the telescope. The calibration procedure mainly concerns the photo-sensitive device
which is the MAPMT. It is important to note that due to the installation of JEM-EUSO telescope on
the ISS, different calibration approaches have to be elaborated : on the ground during the assembly
phase and onboard of the space station. Furthermore, during the flight, calibrated lights (Xe flashers,
lasers) will be sent to JEM-EUSO from the top of some mountains and from NASA planes. It will be
seen later that for the reasons of practical issues and also resources limitations, the calibrations
methods would involve the readout ASIC and also the high voltage power supply.
In general, the MAPMT calibration for JEM-EUSO is done by two kinds of measurement. The first one
is the MAPMT absolute gain measurements. It is a very important aspect of the instrument
calibration and it shall be repeated numerously through the whole JEM-EUSO experiment lifetime.
Consequently, the possibility to integrate this measurement onboard of JEM-EUSO telescope has to
be verified. The second measurement is the efficiency measurement where it will be done in an
absolute way during the assembly phase for selecting the MAPMTs and in a relative way during the
flight. Therefore the setup of this absolute measurement will be done only on the ground prior the
assembly phase of JEM-EUSO.
For the following, the measurements approaches for the MAPMT calibration will be initially
described. Finally the selection criteria and methodology for the sorting of the MAPMT will be
explained as well.
5.1 MAPMT absolute gain measurements
It has been previously established in Chapter 2, that the Hamamatsu R11265-M64 is considered as
the baseline for the photon detection in JEM-EUSO. This 64-channel MAPMT will be working in single
photoelectron mode and its nominal gain is set at 106. The high gain is required as the single
photoelectron working mode means that the arrival photon intensity will be quite low : the individual
detected single photoelectrons will be well separated in time. In this condition, the detected photons
will be transformed into discrete photoelectron pulses. This property is particularly useful for the
MAPMT gain measurement as the discrete events of the pulse will tell us its amplitude hence its gain.
Therefore, the gain measurements need to be done in a condition where we could have the single
photoelectron signals most of the time.
The probability of MAPMT photon detection is given by the Poisson relation:
Where is the average number of the detected photons per pulse.
photoelectron conversion.
is the probability of the
From the Poisson equation, the probability to obtain the pedestal, single photoelectron and two
photoelectrons is given by the following relations:
181
Pedestal (zero photoelectron) :
Single photoelectron:
Two photoelectrons:
By using these relations, we could set our measurements setup based on the average detected
photon,µ. Typically we would like to distinguish the pedestal and the single photoelectron peak with
a great precision. The ratio of the pedestal and the single photoelectron peak is given by
. For
example, by setting the intensity of a pulsed light source in order to have µ=0.02, would give the
ratio of
. With the same source settings, the ratio between two photoelectrons and the single
peaks is the following:
. Usually µ is set between 0.01 and 0.10 in order to have a good
pedestal/single photoelectron ratio and also to make the disturbances from two photoelectron peak
negligible. Figure 5.1 shows the spectrum of single photoelectron.
Figure 5.1 : Single photoelectron spectrum of a photomultiplier taken by an ADC. The average
detected photons in 0.025
From Figure 5.1, the equivalent charge of the single photoelectron peak could be established by
subtracting the pedestal channel from the single photoelectron channel. This operation will give
directly the MAPMT gain, expressed in number of electrons or in pC.
The MAPMT spectrum shown Figure 5.1 is usually obtained from measurements using a commercial
charge-ADC. Unfortunately this feature is not available on the SPACIROC ASIC which is used for the
MAPMT readout. In order to establish the gain measurement using this ASIC, the information for the
Photon Counting part shall be used. As shown Chapter 4 (Section 4.3.8), the triggering efficiency or
S-curves measurements can be used as an alternative tool to establish the gain. The distribution of
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the single photoelectron peak can be obtained from the derivation of the S-curves plots which are
the corresponding cumulative distribution function. It can be shown that the position of the single
photoelectron peak corresponds to the inflection point in the S-curve.
Typically for this ASIC, the S-curves can be obtained directly from the digital readout. To facilitate the
measurements, the GTU (400 kHz) can be used as the sync for the input signal. The setup used here
is identical to the one used in Chapter 4 and it is reproduced in Figure 5.2 for convenience. A 378 nm
LED is used to illuminate the MAPMT.
Figure 5.2 : MAPMT measurement test setup. The GTU clock is provided by the FPGA of SPACIROC
ASIC test board.
In the case of single photoelectron measurements, we would like to set the light source until we
could achieve a small probability of the averaged detected photons, µ. By using the GTU as the
source sync, the average detected photons are translated directly by the triggering efficiency. The
triggering efficiency in Figure 5.3 (upper plot) is done over 103 GTUs. By examining the data count
after the minimum DAC value (over 5σ of electronic noise), the triggering efficiency is around 8%.
This translates to 0.08 of average detected photons which is good enough to measure the single
photoelectron peak.
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Figure 5.3 : An example of gain measurement from SPACIROC FSU Trigger (Trig_FSU) for Channel 35
(Pixel 36). In this measurement, 1 DAC ~ 2.13 fC. The light intensity has been set in order to have 8%
of triggering efficiency. Upper plot (green): S-curve. Lower plot (blue): S-curve differentiation.
By differentiating the S-curve of Figure 5.3, the equivalent charge or the amplitude can be obtained
directly from the single photoelectron peak. From Figure 5.3 (lower plot), the single photoelectron
peak is 75 DAC steps away from the pedestal. In this measurement setup 1 DAC channel corresponds
to 2.13 fC of equivalent charge or 2.18 mV of amplitude. Therefore the single photoelectron peak of
75 DAC channel corresponds to an equivalent charge of 159.8 fC or amplitude of 163.5 mV. From the
obtained equivalent charge, the gain can be deducted directly and it is around 106 which is the
nominal gain for JEM-EUSO.
When comparing the photoelectron distributions in Figure 5.1 and Figure 5.3, one can observe the
measurement in Figure 5.1 is much better in order to differentiate the single photoelectron peak.
However for practical reasons and to limit power consumption, the measurement setup using the
ASIC is still the best solution especially once the telescope is installed on the ISS. Furthermore, the Scurves information hence the ASIC are required for equalizing the gain of the MAPMT.
One of the important characteristics of a MAPMT is the gain uniformity between the anodes. For
Hamamatsu R11265-M64, the typical ratio of the gain uniformity is 1:3 as announced by the
constructor. In any case this ratio should be compensated by the ASIC pre-amplifier stage. The input
stage of this ASIC is able to correct the MAPMT gain non-uniformity up to the factor of 4. Ideally, the
gain compensation should be corrected by analyzing the photoelectron distribution (Figure 5.3).
However the precision of the gain measurement is not satisfying enough to be used for the MAPMT
gain correction. This is due to the low light condition and also the data analysis which could also adds
to the complexity of the process. To simplify the task, the gain correction for the 64 channels, can be
done directly from the S-curves, but under the following conditions:

LED intensity has to be increased in order to have 100% photon detection for every GTU.
Then the peak from the derivative is at a place given by the product of the gain by the
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
efficiency. In one MAPMT, we have established that the 64 pixels exhibit a variation of
efficiencies contained within 20%. In a first step, we can consider that as constant.
MAPMT gain reduction via the high voltage power supply is required for not saturating the
analog signal response of the ASIC.
Figure 5.4 and Figure 5.5 show the S-curves of FSU Trigger for different high voltage values and also
light intensity. For example, at 700 V (Figure 5.4), the measured light intensity of 12.3 nW in the
controlled NIST photodiode is sufficient to have obtained 100% photons detection. For this intensity,
the triggering efficiency is confined between 100 and 260 of DAC. We have seen previously in
Chapter 3 that FSU Trigger is linear up to 320 fC or 240 DAC in this ASIC setup. For instance, the 50%
triggering efficiency of this light intensity is 162 DAC and it is convenient to use this point as a
reference for correcting the gain of other channel.
Figure 5.4 : S-curves of ASIC Channel 35 for various light intensity. The high voltage value for the
MAPMT cathode is set at 700 V.
In Figure 5.5 the high voltage power supply is set at 900 V. The 100% photon detection is obtained
starting from the light intensity of 15.2 nW. However, the 50% triggering efficiency (~DAC 450) for
this light intensity is already in the saturation region of the FSU Trigger. Consequently, this high
voltage value is unsuitable for the gain correction procedure.
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Figure 5.5 : S-curves of ASIC Channel 35 for various light intensity. The high voltage value for the
MAPMT cathode is set at 900V.Here we had a gain of2.106 and the black curve (NIST=15.2nW) shows
that the single photoelectron peak( after derivation) is at the right place (around 300 DAC).
To sum up, the gain correction procedure will be the following steps:
1.
2.
3.
4.
5.
The nominal pre-amplifier gain is set at unity value.
Do the green curve of Figure 5.4 (yellow plot) for each pixel
Extraction of thresholds corresponding to 50% triggering efficiency for the reference channel.
Recalculation of the gain correction to be applied for the other pre-amplifier channels.
If necessary, repeat step 1, 2 and 3 with lower nominal pre-amplifier gain.
As for the hardware integration for the gain measurements and calibration, a UV-led, LED driver and
NIST photodiode are needed to be installed on board of the JEM-EUSO telescope. For the gain
correction purpose, the Cockroft Walton high voltage generator should be more than adequate to
provide various high voltage values to the MAPMT. In terms of software and data processing, the
gain determination and the equalization method can be implemented at any hardware level after the
readout ASICs. To minimize the resource usage and avoid redundancy, it is preferable to have the
procedure written towards the end of the data acquisition chain.
5.2 MAPMT efficiency measurements
The MAPMT efficiency is the product of the cathode quantum efficiency by the first stage collection
efficiency (which depends slightly on the high voltage). To determine it, one has to measure the
number of photons falling on a pixel, and at the same time the number of photoelectrons given by
that pixel. The efficiency will be a selection criterion for the MAPMTs which are going to equip the
Focal Surface of JEM-EUSO. Unlike the gain non-uniformity, the efficiency defect can’t be
compensated by the ASIC and it is nearly independent from the applied high voltage power supply.
Consequently, the selected MAPMTs for the telescope should at least nearly the same efficiency per
block of MAPMTs (EC units of PDM modules).
The efficiency measurement is done in two steps:
1. Photoelectron measurements: The same method in Section 5.1 is applied here and the setup
is identical to the one shown in Figure 5.2. The readout could be replaced with a charge-QDC
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instead of SPACIROC ASIC. The surface of the single photoelectron peak is proportional to the
efficiency.
2. Measurement of this proportionality factor by photon measurements: The arrival photons at
the surface of the MAPMT shall be measured with a NIST calibrated photodiode replacing the
MAPMT at exactly the same position in order to have the identical geometry configuration.
For the source transmission, we need a light splitter so that the light given by a LED can go to the
MAPMT and also to a NIST calibrated photodiode. The best and most stable splitter is an integrating
sphere. An integrating sphere is then used to split the light source. For example, the integrating
sphere used in the gain measurement (Section 5.1) has 3 ports: 1 input port for the UV LED of 370nm
wavelength and 2 exit ports for the MAPMT or NIST photodiode.
Internally, an integrating sphere is coated with a reflective diffusive layer. For instance, the
integrated spheres produced by Labsphere are coated with the proprietary Spectralon material (a
very purified Teflon) which has a reflectance between 0.98 and 0.99 for the UV light. Due to the
spherical form of the integrating sphere, the internal light diffusion is uniform and constant.
Consequently, the light flux at any exit port is proportional to the incident flux and to the port
surface. The flux for a given exit port, , can be expressed from the ratio of the exit port surface
and the effective diffusion area of the sphere [63]:
Where
is the diffused light flux of the sphere, is the exit port surface and
sphere effective surface (total sphere area minus ports area).
is the
Furthermore, the flux ratio between two exit ports is proportionate to the ratio of the exit surface
and it can be expressed as the following relation:
Where
and
are the radius of the exit ports opening.
This relationship is useful when the flux of a given exit port needs to be reduced such as for the single
photoelectron measurement of a MAPMT pixel. For instance, a collimator with small apertures could
reduce the effective area of the MAPMT exit port to compensate for the MAPMT gain. By measuring
the flux on any unoccupied exit port, the equivalent flux on the MAPMT exit port can be deducted
through the ratio of the two exit ports surface. Figure 5.6 illustrates the integrating sphere as a
source splitter and the devices connected to each input and exit port.
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(a)
(b)
Figure 5.6 : An example of the integrated sphere usage. (a) High gain MAPMT for single photo
electron measurement setup. (b) Strong light photon transmission measurement setup.
The 3-port integrated sphere setup for the single photoelectron measurement is shown in Figure 5.6
(a). The input port is used to set the UV LED and the two exit ports are fitted with the MAPMT and a
photodiode. The photodiode is a NIST calibrated UV detector and it is used for measuring the photon
flux. The surface of the NIST photodiode exit port is kept as big as possible in order to maximize the
photon collection. On the other hand, a collimator of 1 mm holes separated by 20 mm is added for
the MAPMT exit port. The role of the collimator is to limit the illumination onto a single pixel of the
MAPMT (the beam is nearly parallel) and also to reduce the light flux. It is specifically done for the
single photoelectron measurement where a low light condition is required. This condition could also
be achieved by reducing the light source intensity. However, the light intensity can’t be reduced
indefinitely as the noise of the photodiode could dominate in the low light measurement.
In order to establish the flux ratio between two exit ports, it is more convenient to measure the
output flux directly. For this purpose, the MAPMT shown in Figure 5.6 (a) is replaced with a second
NIST calibrated photodiode (Figure 5.6 (b)). Naturally, the geometrical characteristics of both exits
are the same in order to have to have the correct ratio of the photon flux. The UV light source shall
be increased so that the SNR of both NIST photodiode is big enough for having a correct
measurement. Figure 5.7 shows an example of the conversion factor for a NIST calibrated
photodiode.
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Figure 5.7 : NIST calibrated photodiode conversion factor for UV LED wavelength from 350nm to
450nm. The precision of the values is around 1.5%.
Once the flux ratio is obtained for both exit ports, the number of photon [64] can be established by
referencing to the measurements of the main photodiode (NIST Photdiode#1 – cf. Figure 5.6):
Where is the frequency of the pulsed LED ,
is the measured current from the NIST
Photodiode#1,
is the NIST Photodiode#1 conversion factor and is the measured flux ratio.
The statistical error [64] for the photon measurements are mostly related to the second photodiode
(NIST Photodiode#2 – cf. Figure 5.6(b)) which is used for the establishing the ratio. The error is given
by the following:
Where
is the measured current from the NIST Photodiode#2 and
Photodiode#2 conversion factor.
is the NIST
The absolute efficiency is simply given by the following relation:
Where
is measured photoelectron and
is the measured photons.
The statistical error linked to the photoelectrons measurement is usually negligible. It will be mostly
dominated by the photon flux measurements. The error on the ratio is given by the following
equation:
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Due to the complexity of the setup, it is hard to imagine an installation for this measurement
purpose onboard of JEM-EUSO. In fact it is difficult to replace part of the focal surface by a NIST
photodiode.
5.3 MAPMT sorting
As explained earlier, the MAPMT selection criteria are based on the efficiency and the gain. Typically
the efficiency of Hamamatsu R11265 is around 20-25% when the MAPMT is powered with 1000 V.
The MAPMTs which don’t respect the typical efficiency value shall be discarded as it can’t be
compensated. To facilitate the gain correction by the ASIC later, the MAPMTs with identical
characteristics shall be regrouped within the same EC unit and PDM module.
To build the Focal Surface of JEM-EUSO, roughly 5000 MAPMTs are required. If the spare units are
included, there will be nearly 10,000 MAPMTs which have to be characterized and sorted. To
accelerate the measurements, the integrating sphere with a big number of ports shall be used. For
example, the integrated sphere shown in Figure 5.8 has 12 ports, 10 of which are used to illuminate
the MAPMTs. In order to illuminate the full MAPMT surface, hence all its pixels uniformly, one could
use the cos4θ law which gives the non uniformity along a certain length at a distance from a
lambertian emitter. Here we use 3 mm ports on the sphere, and the MAPMTs which are 25 mm wide
are at 30 cm. The non uniformity is then 1%.
Figure 5.8 : An example of multiport integrating sphere which will be used for JEM-EUSO calibration.
The MAPMT on ground characterizations and calibrations shall be done by using the front-end
boards test system. At the time of writing, the front-end test system (which includes a test board, a
high capacity FPGA and a LabVIEW software) is still the most user friendly system available.
Additionally, it could speed up the characterization process as at least 512 pixels or 8 MAPMTs could
be readout simultaneously. The efficiency measurement, the gain tests and equalization procedure
can be integrated seamlessly under the Labview environment.
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Chapter 6 Front-end board prototype
for JEM-EUSO
The Elementary Cell (EC) is one of the most important parts in the core JEM-EUSO electronic chain, as
this is where the photon detection and measurement are performed. The Elementary Cell, as defined
in Chapter 2, consists of the following components:



MAPMTs
Front-end board(s)
Readout ASICs
This chapter is mostly dedicated to the design of the electronics front-end board(s) which is an
important element of the EC. The scope of the electronics front-end is limited to one or several
boards employed for the MAPMT readout purpose.
For the MAPMT, 64-channel Hamamatsu R11265-M64 will be used as the baseline for the photon
detection (Chapter 2). To power this MAPMT, 14 different high voltage values are required: 12 for
the dynode stages, 1 for the cathode and 1 for the guard ring. Obviously, these 14 high voltage lines
need to be taken into account during the design of the front-end boards. Concerning the ASICs, the
constraint on the front-end board design mainly comes from the ASIC input and output signals (I/Os).
It will be seen later that the design difficulties will mostly come from the connectivity to the FPGA
board (PDM board for JEM-EUSO) which consists of the digital I/Os (command, data and clocks) and
the low voltage power supply. Additionally the board dimensions could also be influenced by the
choice of the ASIC packaging. For the obvious reasons of availability, practical issues, reliability and
safety, the choice of the ASIC packaging and the connector is very limited. Thus it will have a direct
impact of the board design in terms of quantity, size and accommodation in the instrument.
The proposed dimensions of the front-end board(s) and the number of MAPMT per EC unit are fixed
by mechanical structure holding the whole JEM-EUSO instrument. Given by condition, we have to
find innovative solutions which will fit the mechanical constraints and also satisfy the requirements
for space-flight electronics. In the following, the principal constraints of the front-end electronics of
JEM-EUSO will be exposed. Later on, the realisations which have been done for UFFO and the
upcoming JEM-EUSO pathfinder on a stratospheric balloon will be shown. The design evolution from
UFFO to EUSO-Balloon will be exposed in the following.
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6.1 Mechanical requirements and preliminary front-end board studies
The mechanical frame [65] supporting the Focal Surface is shown in Figure 6.1 (a) and the subset of
the Focal Surface which is called Photo Detection Module (PDM) is shown in Figure 6.1 (b).
(a)
(b)
Figure 6.1 : (a) JEM-EUSO Focal Surface. (b) PDM unit of the Focal Surface.
The construction of the PDM consists of a mechanical frame housing the EC units and a number of
panel where the PDM board (first level trigger board) could be mounted. The overall dimensions of
the mechanical frame are 167 mm x 167 mm x 28.7 mm. As there are 9 EC units per PDM, each EC
unit will occupy a surface of 55.67 mm x 55.67 mm. This area is enough to fit 4 units of Hamamatsu
R11265-M64 MAPMT. The size of the Hamamatsu R11265-M64 MAPMT is about 26.2 mm x 26.2 mm.
Of course in the ideal case, the 4 readout ASICs should be housed and fitted in the same EC unit.
(a)
(b)
(c)
Figure 6.2 : Cut off view of PDM(a).Front view of PDM frame (b). Back view of PDM frame (c).
From Figure 6.2 (b) and (c), we can distinguish 9 different slots which will house the EC units. The
front-end board(s) could be placed within theses slots. Another important aspect to consider is the
support mechanism (a rod or a screw) is added in the middle of each slots. Such crossing structure is
supposed to strengthen the mechanical frame. The maximum number of boards which can enter into
each slot is two and it is shown in the following figures.
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(a)
(b)
Figure 6.3 : Proposed front-end PCBs for the MAPMTs (a) and ASICs (b).
The size of each proposed board is 52.5 mm x 52.5 mm, which corresponds to the size of the EC slot
minus the edges of the holding structure. This board could perfectly hold all the pins of the 4
MAPMTs. Obviously we would like to squeeze the 4 readout ASICs within the same surface either on
the same board or on the second one.
After the initial assessment of the mechanical frame requirements, it was decided to merge both
front-end boards into a single thick PCB11. This PCB would hold the MAPMTs on one side and house
the packaged ASICs on the other side. The illustration of the concept is shown in Figure 6.4.
(a)
(b)
Figure 6.4 : (a) Cut off view of the proposed front-end PCB. (b) Top view of the proposed front-end
PCB.
11
PCB stands for Printed Circuit Board which the most usual form of producing electronic devices.
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In this proposal, a thick PCB that would be used, receives the Holtites (socket for mounting the
MAPMT) and it will be inserted internally deep into the PCB. Unlike the through board solution, this
kind of PCB is very compact and allows an integration of ASICs and MAPMT on the same board. For
the connectivity from and to the outside area, there are roughly 80 signals including the power
supply for the 4 ASICs. Additionally, there are also 14 lines for the high voltage power supply which
could be shared with the four MAPMTs of an EC unit. When designing the front-end for JEM-EUSO,
the signals which arrive to the electronics boards play a major role on determining the board size.
This is especially true on a limited area such as the EC unit and also when the choice of the connector
is restricted.
In the following section we will focus on how the front-end board could be done for JEM-EUSO
regarding the past experience which has been using SPACIROC ASICs as readout element. The first
iteration of the front-end boards has been developed for UFFO pathfinder project. The similarities in
terms of dimensions of the front-end and first level FPGA boards, were seen as a good platform to
test the idea shown in Figure 6.4. The development related to this front-end board design will be
exposed in the dedicated section for UFFO pathfinder (Section 6.2).
By taking into account the experiences gained from UFFO, a second design of the front-end has been
carried out. This work is specifically done for EUSO-Balloon project which is a technological
demonstrator for JEM-EUSO.
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6.2 UFFO pathfinder
6.2.1 Introduction
UFFO which stands for Ultra Fast Flash Observatory [66], is designed to observe the gamma-ray
bursts (GRB) in the space. It is a collaboration led by EWHA Womans University and University of
California, Berkeley. From the results reported by spacecrafts such as SWIFT, the recorded data are
mostly done after minutes of the detected burst itself. The lack of sub-minute scale data (Figure 6.5)
making the determination of UV-light characteristics for short and hard type GRB is basically
impossible.
Figure 6.5 : SWIFT response time.
This issue should be addressed with the development of UFFO which is using a new approach to track
the triggered GRB. In the previous GRB observation spacecrafts, the whole instrument has to be
rotated in order to track the GRB. The illustration of this system is shown in Figure 6.6.
Figure 6.6 : SWIFT spacecraft rotation for locating GRB.
Moving the spacecraft is the limitation of the current GRB experiments time response. This process
involves of accelerating and decelerating the whole mass of the instrument. A certain settling time is
needed to stabilise the instrument. Moreover, the vibrations produced could cause smearing of the
telescope’s point spread function thus reducing its sensibility.
195
Instead of moving the spacecraft to get into the optical path, it will be much faster to rotate small
mirrors in order to point into the optical path of the located GRB. The response time by using this
method will be much faster than the conventional way of rotating the spacecraft. Figure 6.7
illustrates the idea.
Figure 6.7 : Mirror slewing for moving the optical path.
The mirror slewing technique can obtain a very fast settling time which could be as low as 1s.
However, in order to obtain the sub-second response time, another approach is needed. UFFO
proposal is to embed an array of miniature MEMS mirrors as the reflector of the rotational mirror.
The MEMS mirrors have a settling time less than 1ms thus it allows faster response time albeit with a
lower resolution.
Figure 6.8 : Illustration of MEMS mirror array on a rotating plate.
The MEMS mirror array (MMA), developed by Research Center of MEMS Space Telescope at Ewha
Womans University, is the technological core of UFFO experiment. MMA is a proven design as its
prototypes have been already flown in the space to the ISS in 2008 and on a microsatellite called
Tatiana-2 in 2009. A pathfinder for UFFO has been in construction and it will piggyback on the
LOMONOSOV spacecraft expected to be launched in 2013. The 20 kg pathfinder will be a precursor of
the actual UFFO instrument called UFFO-100 which could be launched by 2015. Figure 6.9 shows the
conceptual drawing of the UFFO pathfinder.
The pathfinder is composed of three main instruments: UFFO Burst Alert & Trigger Telescope (UBAT)
[67], Slewing Mirror Telescope (SMT) and UFFO DAQ (UDAQ). The MMA MEMS mirror is used in the
SMT instrument which consists of a Ritchey-Chrétien telescope of 10 cm aperture. In order for UBAT
to trigger a GRB, a mask coded camera is used in a similar fashion to SWIFT BAT X-gamma trigger
camera. The total surface of the coded mask is 191 cm², which results in a sensitivity of 310 mCrab (5
σ) for 10 s exposure. The detector plane of UBAT consists of LYSO crystals and 64-channel MAPMTs,
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where the detection sensitivity will be within the range of 5 keV to 200 keV. The pathfinder and the
onboard instruments are shown in Figure 6.9.
Figure 6.9 : UFFO pathfinder.
The initial baseline for the UBAT X-gamma ray detection module (Figure 6.10) was to use CdnZnTe
detector and ASIC for the readout. However for various reasons, the baseline was changed to LYSO
crystal and MAPMT detector. Finally it was decided to design a detection module based of the JEMEUSO PDM in order to trigger the gamma ray bursts. The specifications of the UBAT detector are
summarized in Table 6.1.
Telescope
Coded mask aperture camera
Field of view
90.2° x 90.2°
Source position accuracy
≤ 10 arcmin for > 7σ
Energy range
5 – 200 keV
Processing time
1 ~ few seconds
Table 6.1 : UBAT detector characteristics.
(a)
(b)
Figure 6.10 : UBAT instrument (a) . Detailed view of the UBAT detector module (b).
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From the detailed view of the UBAT detector, the components of the detector module are the
following:




36 units of MAPMTs and an array of LYSO crystals
9 units of Analog Board (front-end board housing the SPACIROC ASICs)
1 unit of Digital Board (FPGA) and Low Voltage Power Supply
1 unit of High Voltage Power Supply (HVPS)
The cut off view of the proposed UBAT detector module (without the coded mask) is shown in Figure
6.11.
Figure 6.11 : UBAT detector module cut off view. The positioning of the Analog Board (EC Board) is
highlighted in dashed red box. Dimensions: 167 mm x 167 mm x 79 mm.
As shown in Figure 6.11, the proposed detector module is slightly different from the PDM unit shown
previously in Figure 6.2 (a). Due to the height limitation of the UBAT detector module, the board
housing the FPGA has to be placed horizontally instead of the vertical position as shown in Figure 6.2
(a). Otherwise the position of the Analog Boards within the mechanical frame is identical to the JEMEUSO PDM module (Figure 6.2 (b) and (c)). The design of the Analog Board front-end will be
described in the following sections.
6.2.2 UBAT Analog Board
36 ASICs are required for reading out the MAPMTs, thus with 9 Analog Boards, each board is housing
4 SPACIROC ASICs. The requirement to use 9 Analog Boards is originated from the PDM frame of
JEM-EUSO. When designing this front-end board and the mounting support, the PDM frame physical
dimensions are used as input.
To design the Analog Board, there are several factors which have to be considered:




ASIC packaging
Connector and I/Os
High voltage distribution
PCB fabrication process for non-through holes
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The most important constraints on the design were the ASIC packaging and the connector size. For
the ASIC packaging, we had to settle for the Chip-on-Board (COB12) solution as none of the widely
available packages such as CQFP would fit the board. Due to the project time scale, grid array
package (BGA or CGA) was not even considered as there is a huge risk of the availability
(procurement difficulties) for this type of packaging. Furthermore COB is the lowest profile solution
available for the ASIC and could minimize the area usage of the board. Another big issue for this
front-end design is the connector as there are nearly 80 I/Os for each board. To reduce the area
occupancy, we decided to use only one connector. A low profile 80-pin connector (AXN 5/6 from
Panasonic) with 6.8 mm x 22.4 mm footprint has been chosen to equip the board. The sketch of the
UBAT Analog Board is shown in the following figure:
Figure 6.12 : UBAT Analog design sketch.
Figure 6.12, shows the positioning of each component on the Analog board. As shown in Figure 6.12,
most of the passive components are made of the resistive voltage divider for the MAPMT power
supply. To facilitate the high voltage power supply routing, 2 sets of voltage divider are used on this
board. Another important aspect of the Analog Board design is the connector positioning : where it
needs to be located in the middle of the board. This location was dictated by the constraints on the
input and output signals routing. There was a possibility to split the signals into several connectors
but this kind of solution would have made the routing and the connector placement impossible on
the board. By placing the connector in the center of the board, it means that the hole of 6.1 mm
diameter for the support structure (Figure 6.3) have to be moved to somewhere else. The PDM
frame of JEM-EUSO needs to be altered in order to have an opening for the cable to reach the
connector and also to relocate the holding structure. The comparison between the JEM-EUSO PDM
frame and UBAT detector module mechanical frame is shown in Figure 6.13.
12
Chip-on-Board refers to the technology where the ASIC die is mounted directly on a circuit board. This
solution, which is popular for a small and compact front-end design, is not yet fully adopted in the space
industries due to the rigorous rules of the reliability by the space agencies.
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(a)
(b)
Figure 6.13 : The illustrations of JEM-EUSO PDM frame (a) and UBAT mechanical frame (b). The
connectors (red box) and the holes for support structure (blue round) are placed in respect with the
proposed solution.
As shown in Figure 6.13 the proposed location of the 80-pin connector is not compatible with the
PDM frame. Therefore, the mechanical frame for UFFO has been built based on the drawing in Figure
6.13 (b).
Analog Board design
The first version of the Analog Board is shown in Figure 6.14. The final dimension of the Analog Board
after the components placement and signal routing is 54 mm x 54 mm. It is slightly larger the
proposed 52.5 mm x 52.5 mm (Figure 6.3).
Figure 6.14 : Analog Board top view including the holding structure for the PCB fabrication. The
dimensions of the Analog Board : 54 mm x 54 mm.
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Figure 6.15 : Analog Board cut off view. Board thickness : 4.1 mm.
In total there are 10 layers which are required for routing this PCB as shown in Figure 6.15. The
bottom layer corresponds to 75% of the PCB total thickness which is 4.1 mm. The list of the layers is
reproduced in Table 6.2.
As explained at the beginning of this chapter, the Holtites13 which are used for holding the MAPMT
pins are inserted into the front-end board. For this purpose, holes of 3 mm depth and 1.04 mm
diameter are drilled within the PCB (Bottom layer – cf. Table 6.2). The insertion process is done by
exerting sufficient amount of force until the Holtites fully enters the holes on the bottom side of the
PCB. In order to ensure a proper placement of the Holtites, the drilling and the metallization of the
holes are required to be precisely14 done. Otherwise, the Holtites could not be fully inserted or the
insertion process could break the PCB as a result of excessive forces applied to the Holtites.
Unfortunately, the metallization precision for a non through-hole can’t be well controlled and it
could worsen with the depth of the drilling. For this reasons, several PCB fabrication methods have
been considered. Figure 6.16 shows two different approaches which have been tested for making the
non through-hole.
(a)
(b)
Figure 6.16 : Non through-hole fabrication process. (a) Single 3mm layer. (b) 3x 1mm layers.
13
Holtite is a socket solution from TE Connectivity (formerly of TYCO Electronics). The model used for the
Analog Board is 5P (Part Ref: 6-1437514-7).
14
The required precisions are : ±0.01mm on the hole drill and ±0.05mm on the metallization.
201
As this PCB is a non-standard fabrication process, both approaches shown in Figure 6.16 could
achieve very different results. The process in Figure 6.16 (a), uses only single layer for the bottom
part. For this process, the PCB fabrication has to be started from the bottom layer in order to control
the metallization of the hole. Afterwards, the fabrication sequence will go through the layer 9 until it
reaches the top layer. This process seems to have a very good precision control but it could induce
other unexpected problem. By stacking up several layers, the planarity defects can be very important
and it will cause the PCB to warp. This will render the PCB useless as a flat surface is required for
mounting the SMD15 components and bonding the ASICs.
The second approach shown in Figure 6.16 (b) is nearly the opposite of the first process explained
previously. For this fabrication process, the bottom layer of 3 mm thick is equally divided into three
different layers with 1 mm thickness. By doing so, the fabrication of the PCB could start from the top
to the bottom layer which follows the usual fabrication method. The only issue which could come
from this process is the holes drilling precision and the rigidity of the holes metallization. By stacking
3 layers, there will be spaces between each layer. This could be a problem for the thermal cycling and
the vacuum outgassing around the frontier of the stacked layers.
Both methods were tried on this PCB manufacturing and the process shown in Figure 6.16 (b) was
more successful to produce the Analog Board. All the Analog Boards were produced using this
method by a Korean PCB manufacturer.
Layer Name
Top
C2 Signal
C3 GND
C4 Signal
C5 Power Supply
C6 High voltage
C7 High voltage
C8 Signal
C9 Signal
Bottom
Material
Thickness(mm)
Air/Copper
0.035
FR-4/Copper
0.105
FR-4/Copper
0.084
FR-4/Copper
0.089
FR-4/Copper
0.084
FR-4/Copper
0.089
FR-4/Copper
0.105
FR-4/Copper
0.155
FR-4/Copper
0.32
Air/Copper
3.045
Total
4.111
Table 6.2 : Analog Board design cross section. Total thickness : 4.111 mm.
Table 6.2 shows the distribution of different layers of this PCB according to the type of signal or
power supply. Additionally, there are also 14 high voltage lines which have to be routed. The voltage
values which ranges from 1000 V to 30 V are routed in layer 6 and 7. Special precaution has been
taken for routing these power lines in order to prevent the arching and the corona effects. Internally,
the design rules have been set at 1 kV/mm separation between the high voltage lines and other
traces such as input signals and ASIC power supply. The FR-4 material which is used as the dielectric
in this PCB has an effective (aging factors included) voltage rating of 11.8 V/µm. Therefore the
minimum thickness of FR-4 used for isolating the layer 6 and 7 is set at 70 µm which could sustain up
to 830 V. Additionally, between these 2 layers, none of the high voltage lines are allowed to cross
each other in order to increase safety distance. Higher clearances are required as for the space or
15
SMD stands for Surface Mount Device which refers to the passive component used on this board. The
component packages which are used are 0603 (1.6 mm x 0.8 mm) and 0805 (2 mm x 1.25 mm).
202
high-altitude application, the high voltage could spark over at four times of the sea-level voltage
rating. On the surface of the PCB, conformal coating is sprayed in order to increase the voltage rating
of this PCB (up to 2000 V).
The top and bottom view of the Analog Board are shown in Figure 6.17.
(a)
(b)
Figure 6.17 : Analog Board top (a) and bottom (b) view.
The reproduced top view (Figure 6.17 (a)) includes all the routing of the electrical interconnections,
passive components and power supplies. On this layer there are 59 digital I/Os and 256 analog inputs
which have to be routed. On the bottom part, the density is on the other term as a huge number of
holes have to be drilled for the Holtites insertion and mounting of the MAPMT. When including the
high voltage power supply, there are 86 holes for each MAPMT. This brings a total of 344 drilled
holes on the back side of the ASIC.
The dimensions of the board are set by the placement of the 4 MAPMTs and also the distance
needed for the holes of the mechanical structure support. The distance between components are
kept as minimum as possible due of the lack of usable area. For example the distance between each
MAPMT is only 1 mm and between the outer MAPMT pins to the edge of the board is also 1 mm.
Cable design
In order to bring out the data and transport the power supply to the ASIC, a flex cable (flexible
electronics circuit) was designed. The choice of this type of cable over the other type is mainly based
on the flexibility and the thickness of the cable. Of course other type of cable such as twisted pair or
coaxial could offer better protection against the electromagnetic interference, however this kind of
solution is not practical for the connection from the Analog Board to the Digital Board.
The design of the cable is a typical one where rigid parts (FR-4) are used to hold the connectors and
the flexible (Kapton/polyimide) part is used for transporting the data. Figure 6.18 illustrates the
design of this rigid-flex cable.
203
Figure 6.18 : Design of rigid-flex cable. 6 layers and 4 layers are used for rigid and flexible part
respectively.
As shown in Figure 6.18, the 4 flexible layers are separated into 2 different cables. For each cable, the
top layers (C2 and C4 – cf. Table 6.3) are reserved for the data and control signals routing. The
bottom layers (C3 and C5 – cf. Table 6.3) are reserved for the ground plane and also transport the
power supply to the ASICs. In order to reduce the crosstalk between each signal, the signal traces
have been done by having certain spacing between each other. The minimum spacing is taken about
3 times of the trace width which is 450 µm. Although the best strategy against the crosstalk is
shielding with the ground tracks, the lack of space made this approach impossible to be implemented.
The layers which are reserved for the ground plane have a secondary purpose here, where they can
reduce the electromagnetic radiation which could comes from the signal layers.
Layer Name
Top
C2 Signal
C3 GND
C4 Signal
C5 GND
Bottom
Material
Thickness (mm)
Air/Copper
0.030
FR-4/Copper
0.234
Polyimide Film/Copper
0.107
Air
Polyimide Film/Copper
0.107
FR-4/Copper
0.234
Air/Copper
0.030
Total
0.742
Table 6.3 : Flex cable design cross section. Total thickness: 0.742 mm.
The first version of the cable is 24 cm long and the width is 2.4 cm. The cable was shortened further
in the newer version in order to reduce the capacitive load and to improve the data transmission.
Figure 6.19 : Flex cable top view.
204
Productions, tests and Analog Boards integration
For the production of the Analog Board, there were at least 4 production runs. Due to various
problems, only 3 runs were successful to produce usable bare PCBs.
Analog Board Design
notes
April-May 2011
45%
Initial design
Correction over
SeptemberMAPMT footprint,
20/30
67%
October 2011
ASIC orientation
changes
Routing revisions
and adding
April-May 2012
15/47
31%
decoupling
capacitors.
Table 6.4 : Analog Board production history.
Run
Period
N°1
N°2
N°3
(a)
Working
boards/bonded
10/22
(b)
Yield
(c)
Figure 6.20 : The produced Analog Board: (a) Run N°1. (b) Run N°2. (c) Run N°3.
Figure 6.21 : Bottom view of the Analog Board from production run N°2.
205
Figure 6.22: Analog Board and the test board.
In Figure 6.22, the Analog Board is connected to a test board via the dedicated flex cable. The test
board is an evolution of the one used for the SPACIROC tests and characterisation (Chapter 4). The
FPGA firmware and the Labview software had to be adapted in order to send the parameters for 4
ASICs and to retrieve data from 36 parallel outputs. In total there are 3592 bits for the ASICs
parameters and 2304 bits of data output for every GTU. For UBAT and UFFO application, the
frequency of SPACIROC system clock had to be reduced due to the high capacitive load (~30 pF) of
the flex cable. Instead of the 40 Mhz baseline frequency, the digital part system clock and the
readout frequency runs at 20 MHz. Due to the readout data frame (66 bits), the GTU had to be
adapted as well which brought the GTU width to 5 µs instead of 2.5 µs.
At the time of the writing, the integration and the calibration of the UBAT detector module is
underway. Figure 6.23, Figure 6.24, Figure 6.25 and Figure 6.26 show different views of the Analog
Board and the UBAT detector module assembly.
Figure 6.23 : Analog Board fitted into the mechanical frame.
206
Figure 6.24 : Side view of 9 Analog Boards and the Digital board.
Figure 6.25 : Side view of the UBAT detector module complete with the MAPMTs and LYSO crystals.
207
Figure 6.26 : Top view of the UBAT detector module.
Figure 6.27 : Readout of the Photon Counting (2304 pixels) data from an Americium (Am241)
radioactive source. X and Y axes represent the matrix of the Photon Counting pixels. The hit pixel is
indicated by the red spot.
208
(a)
(b)
Figure 6.28 : Readout of the Photon Counting and KI data from an Americium (Am241) radioactive
source. (a) 20keV signal. (b) 60keV signal. For each signal, the corresponding charge measurement (KI)
and the hit pixels (PC map) are shown. The pixels are for 1 MAPMT (8x8).
Figure 6.27 and Figure 6.28 show the measurements done from the UBAT detector module. The tests
were done with an Americium (Am241) radioactive source which decays the gamma ray of 20 keV
and 60 keV.
Summary
By designing the front-end board for UFFO pathfinder, there is a lot of valuable information that we
learned about the front-end design and also the mechanical aspects of the JEM-EUSO PDM frame.
For the front-end design, it seems that a compact integration of the MAPMT, high voltage and mixed
signal ASICs is probably too ambitious. The difficulties and the drawbacks that we found can be
summarized in three key points:



The production yield of the Analog Board is particularly low (e.g. 31% for Run N°3 – cf. Table
6.4). This is partly due to the unconventional PCB fabrication process and the Chip-On-Board
assembly for the ASICs. These two factors caused most of the rejected boards.
High and low voltage power supplies co-habitation in a small compact board could be a
nightmare for routing the power lines. The high voltage traces design rules can’t be
compromised due to safety reasons. Thus the low voltage traces have to accommodate the
higher voltage. This could cause problems such as lack of grounding and breaking power
planes of the low voltages. We were reaching at one point where the compromise taken on
the low voltages starts to show the effects on the ASIC performances.
Unexpected constraint from the bonding company making that the ASICs orientation had to
be changed. The original orientation was to have all digital outputs concentrated in the
middle of the board. However, this orientation is making the ASIC bonding process becoming
slightly difficult. In order to facilitate the bonding, all the ASICs must have the same
orientation. With the board’s small size, two of the ASICs have inputs which are facing
directly the digital signals. As expected the two concerned ASICs exhibit higher noise and
stability problems compared to the others.
209
The issues for the PDM mechanical frame of JEM-EUSO are the following:


The area reserved for front-end electronics is too small and underestimated. It is most likely
that the studies done for the front-end electronics board area took into account unrealistic
lead count of the ASIC packaging. In any case, with a 52.5 mm x 52.5 mm area, it is very
difficult to build an electronic board which is compliant to space agencies criteria.
The mechanical structure is not adapted to the connectivity where the crossing mechanical
support (Figure 6.13) literally blocks the cabling for bringing out the signals. Again here,
perhaps the studies on the mechanical frame didn’t take into account a realistic approach on
the cable harnessing.
The integration of the front-end electronics also shows the limit of the ASIC itself where a lot of
practical issues have been pointed out. It mainly concerns the control interface, KI Time-OverThreshold settings, data transmission and large number of data output lines. Despite all the
difficulties, the work done for the UBAT detector helped to build a solid foundation on the front-end
design of the upcoming EUSO-Balloon project.
210
6.3 EUSO-Balloon
In this section, the description on the EUSO-Balloon [36] front-end boards will be given. EUSOBalloon is a project which should be regarded as a pathfinder or the technological demonstrator for
the JEM-EUSO telescope. The idea behind this project is to fly via a high altitude balloon, a small scale
of the whole JEM-EUSO instrument; from the optical system up to the final data processing stage.
The difference between both instruments is summarized in Table 6.5.
JEM-EUSO
EUSO-Balloon
Height (km)
420
40
Diameter (m)
2.5
1
Field of view/pix (deg)
0.08
0.25
Pixel@ground (km)
0.0580
0.175
Field of view/PDM (deg)
3.8
12
PDM@ground (km)
28.2
8.4
Signal Ratio
1
17.6
BG Ratio
1
0.9-1.8
S/√N
1
20-10
Ethr(eV)
3x1019
1.5-3x1018
Number of PDM
143
1
Table 6.5 : JEM-EUSO and EUSO-Balloon instrument comparison.
For this project, all the subsystems of the instrument are rebuilt in order to fit the mechanical
structure of the balloon payload. However, the PDM module is constructed according the mechanical
constraints of JEM-EUSO as discussed at the beginning of this chapter. It concerns especially the
front-end electronics as the integration of the MAPMTs and the ASICs on the PDM frame has proven
to be extremely tricky.
(a)
(b)
Figure 6.29 : (a) Overview of EUSO-Balloon payload. (b) Electronics booth is completely independent
from the optics side for facilitating the integration.
The illustration shown in Figure 6.29 represents the box-shaped payload of the balloon. The payload
is watertight and its dimension is 1.2 m x 2.1 m x 1.2 m. In order to fit payload, the Fresnel lenses are
manufactured into rectangular shape. The outer Fresnel lens has a dual purpose. The first one is of
course to focus the photon and the second one is to watertight the instrument. As shown in Figure
6.29 the PDM module is fitted at the focal point of the lenses. For the focusing optimization purpose,
211
the PDM module positioning can be adjusted. The rest of the electronics, which is mostly composed
of the data processing unit (DP) and the power pack, are fitted towards the end of the payload
structure. For the telemetry and command (TM/TC) system, it is not included within the gondola
payload. The TM/TC system is completely independent from the payload and it is built from the
newly developed CNES NOSYCA platform. The onboard TM/TC interface, known as SIREN, will be
connected wirelessly to the payload data processing unit.
Figure 6.30 : EUSO-Balloon subsystems block diagram. The PDM subsystem is highlighted in green
dashed box.
6.3.1 Front-end electronics design
The approach taken for designing the front-end electronics is completely different from the studies
did for UBAT Analog Board (Section 6.2.2). For EUSO-Balloon front-end electronics, the design should
fulfil the following objectives:



To be compliant to the PDM frame mechanical structure (cf. Figure 6.2)
Complete separation of high and low voltages for safety and signal integrity reasons.
To use space qualified components as much as possible in order to finalise the front-end
design for JEM-EUSO.
The mechanical constraint makes that the MAPMTs and its readout ASICs could not be placed
together on the PDM frame. Therefore the MAPMTs and ASICs are placed into different boards. The
front part of the PDM frame will be exclusively reserved for the MAPMTs. The SPACIROC ASICs, will
be situated inside the PDM module on dedicated boards. This situation is illustrated in Figure 6.31.
212
Figure 6.31 : The illustrations of the MAPMTs and ASICs placement in the PDM module.
Figure 6.32 shows the conceptual drawings of the front-end boards for one Elementary Cell (EC). As a
reminder, an EC unit corresponds to 4 MAPMTs. Consequently, the front-end boards and the ASICs
are always expressed with the corresponding units of EC.
Figure 6.32 : Conceptual drawings of the EUSO-Balloon front-end boards.
213
By referring to Figure 6.32 the front-end boards are organised as the following:


EC-Front boards (Front side of PDM frame):
o EC-Dynode
o EC-Anode
o EC-HV
EC-Back boards (Back side of PDM frame):
o EC-ASIC
The classifications of the front-end boards reflect very much the approach of the design: complete
separation of high voltages, each board has a specific role and positioning of the readout electronics
with respect to the PDM frame.
For the front part of the PDM module, called EC-Front, there are three different boards for powering
the MAPMTs and sending out the anodes signal. The first board, which is called EC-Dynode, is used
for distributing the high voltage lines to all the MAPMT dynodes and cathodes for one EC unit. The 14
high voltage lines for powering the MAPMTS come from an intermediate board called EC-HV. This
board is rather small as it is required only to have 14 traces of the high voltage power supply. The
connection between the EC-Dynode and the EC-HV is done via the pin extension of the dynodes and
cathode of the MAPMT. Several high voltage pins of the MAPMT were rerouted EC-Dynode in order
to facilitate the transport of the anode signals through flex cables (cf. Figure 6.33).
The reason to have the intermediate EC-HV board is caused by the existence of the boards dedicated
to the anode signals, EC-Anode. EC-Anode boards are placed directly beneath the EC-Dynode board
where 4 EC-Anode boards are required for one EC unit. EC-Anode boards are rigid-flex-rigid type
board where the flexible part (flex cable) is used to transport the anode signals to the readout ASICs.
Naturally the rigid parts of the EC-Anode are used for collecting the anode signals and to house the
connector for the ASICs boards (EC-ASIC). The illustrations of the ASIC-Front assembly are shown in
the following figure.
(a)
(b)
Figure 6.33 : EC-Front assembly illustrations. (a) The assembly of 3 different boards for the EC-Front
with the associated cabling to the High Voltage power supply unit and the EC-Back. (b) The
illustration of the flex-cable (from EC-Anode) passing through the PDM frame mechanical support
structure.
214
EC-Dynode
Unlike the UBAT Analog Board design, the pins of MAPMTs are directly soldered to the boards
forming the EC-Front. The high voltage pins (dynodes and cathode) of the MAPMTs are soldered to
the EC-Dynode board (Figure 6.34). The high voltage pin extenders will envelope the original pins.
The soldering of the extender is done on the EC-HV side. For the 256 anode pins, the soldering is
done on the EC-Anode boards. To cover the whole EC-Front and to protect it from high voltage
breakdown especially at low pressure16, the compound such as Arathane or RTV can be used for the
potting. For example the distance of the MAPMT cathode which is at 1000 V to the mechanical
(grounded) is only around 100 µm. This small distance requires extra protection against the high
voltage breakdown. Basically the potting will cover the three PCBs of the EC-Front and the MAPMT.
The MAPMT filters and the cables are not included in the potted area.
Figure 6.34 : EC-Dynode top view
EC-Anode
As shown in Figure 6.33 (b), there are 2 flex cables which come out from each side of the EC unit. Due
to the orientation of the MAPMTs, which are rotated 90° from each other, two types of the EC-Anode
board are required. The first board, which is called “straight”, is aligned horizontally on x-axis (from
top view) without any deviation. For the assembly purpose, the flexible part is folded 90° in the z-axis
in order to bring out the connector rigid part. The top view of EC-Anode “straight” is shown in Figure
6.35.
16
By using Paschen’s law, one could determine the breakdown voltage between two electrodes separated by a
distance is the required atmospheric pressure. For example, in stratosphere of 3 mbar pressure and electrodes
separated by 1 mm, the voltage required to arc over the gap is only around 450 V.
215
Figure 6.35 : EC-Anode “straight” top view.
The second type of EC-Anode board is shown in Figure 6.36. Compared to its “straight” counterpart,
the flexible part of this EC-Anode board is “curved” where it is deviated 90 from the horizontal axis
(top view). For the assembly, the flexible part will be bended 90° vertically around the curved area.
The assembly of both EC-Anode boards are illustrated in Figure 6.33 (a). Both flexible parts will come
out in parallel on the connecter side. The connector which is chosen for both EC-Anode is a 68-pin
straight connector from Hirose (FX2CA-68P-1.27DSA).
Figure 6.36 : EC-Anode “curved” top view.
EC-HV
The last piece of the EC-Front boards is the EC-HV which has the purpose as the arrival points of the
high voltages for powering the MAPMT. It is a rather simple and small board. The footprint of this
board is roughly the same size of the Hamamatsu R11265-M64 MAPMT. For EUSO-Balloon and JEMEUSO, the dynodes and the cathode high voltage values are generated independently. For this reason
14 different high voltage cables from the high voltage generator are soldered to the EC-HV board.
The mounting pad for the cables is situated in the middle of the board as illustrated in Figure 6.37.
216
Figure 6.37 : EC-HV top view.
EC-ASIC
As explained earlier, the back side of the PDM frame which is called EC-Back will house the boards
(EC-ASIC) dedicated to the readout ASICs. In total there are 6 units of these readout EC-ASIC boards.
Each EC-ASIC will hold 6 SPACIROC chips as shown in Figure 6.38 (a). The first 3 ASICs are placed on
the top side of the board and the others are situated at the bottom side of the board. The ASICs are
packaged in a 160-pin Quad Flat Package (QFP) type packaging which can be procured easily from the
local provider. Unlike the ASICs, the connectors can be placed only on top of the board as all the
chosen connector are through-hole type. To match the 68-pin connector from EC-Anode, a 68-pin
Hirose (FX2CA-68S-1.27DSA) receptacle connectors is used. For connecting to the PDM board, a 120pin connector also from Hirose (FX2-120P-1.27DS) is used. The 120 pins are adequate connecting the
digital I/Os and the power supply for the 6 ASICs.
(a)
(b)
Figure 6.38 : Conceptual drawings of the EC-ASIC. (a) Top view of the EC-ASIC board. (b) Side view of
the EC-ASIC board with respect to the PDM frame. For each pair of the EC-ASIC boards, the bottom
sides are facing each other.
The EC-ASIC boards are arranged into pairs as shown in Figure 6.38 (b). For each pair, the bottom
side of the board will be facing each other and the top side which holds the connectors are facing
towards the outside. With this organization, 3 EC units of 12 MAPMTs are readout by a pair of ECASIC boards.
217
Figure 6.39 : Anode signals distribution from the EC unit to the EC-ASIC boards. Each dash arrows
(black and red) corresponds to the flexible cable of the EC-Anode.
The sketch shown in Figure 6.39 illustrates the readout by using these EC-ASIC boards. As stated
earlier, for each EC unit, two of EC-Anode flex cables come out on the same side. By referring to the
first EC unit (EC unit #1) in Figure 6.39, MAPMT 1 and 3 will have the anode signals going to the same
EC-ASIC. These anode signals are sent to EC-ASIC board #1 which is drawn in yellow colour. The same
system applies for EC unit #2 and #3 where MAPMT 1 and 3 of each EC unit are connected to EC-ASIC
#1. This architecture is mainly dictated by the assembly constraints. This makes that each EC-ASIC
board readout half of 3 EC units. Naturally the other half of the EC units is readout by the second ECASIC board (EC-ASIC #2 in Figure 6.39).
Figure 6.40 : Top view of EC-Board routing. The ASICs are positioned in the middle of the board,
whereas the connectors for the PDM board and EC-Anode boards are placed on upper and lower part
of the board.
218
Figure 6.40 shows the top view of the ongoing routing work of the EC-ASIC board. The ASICs are
arranged in a way so that the digital signals and the analog inputs will not be crossing each other.
This is done to ensure the integrity of the anode signals. For this reason, the routing of the analog
inputs is done at the lower part of the board and the digital signals routing is mostly done on the top
of the boards. The board grounding is assured by 6 pads which are connected to the mechanical
structure. This could ensure a stable grounding for the boards and also to help the thermal
dissipations of the ASICs. The heat of the ASICs will be passively evacuated through its substrate and
eventually to the EC-ASIC board ground. Subsequently it is a good solution to have the mechanical
structure connected to the board.
Summary
The Table 6.6 summarizes the characteristics of each board which is used as the front-end for EUSOBalloon.
EC-Dynode
Rigid-Anode
ECFlex
Anode
Rigid-Connector
EC-HV
Dimensions
(mm)
54.5x54.5x1.2
24x23.7x1.2
17x60x0.2
17x55x1.2
24x24x1.2
Quantity
per EC
1
Quantity per
PDM
9
4
36
1
9
Notes
Rigid-flex board
1 EC-ASIC readout half
EC-ASIC
115x159x2
1
6
of 3 ECs
Table 6.6 : EUSO-Balloon front-end electronic boards summary.
At the time of writing, there are several works which are still ongoing for the PCBs. This mainly
concerns the work on the electromagnetic compatibility (EMC) for the EC-ASIC board. As seen on the
PCB works of UFFO project, the EMC of several mixed signal ASICs on the same board could be quite
challenging. The signal integrity is one of the main reasons that the boards are completely separated
according to the functionally from the MAPMT dynodes up to the readout ASICs. This approach
makes the assembly process quite difficult but it will ease the constraint on the PCB routing. Basically
for all the described PCBs, the routing is quite simple except for the 10 layers EC-ASIC board. In any
case, the EC-ASIC board is by far much simpler to route than the design of the UBAT Analog board
which was described in Section 6.2.2.
Concerning the PDM mechanical frame, it is shown again that the structure still needs to be refined
in order to fit all front-end electronics. Due to the density of the analog and digital signals, it is very
difficult to fit the front-end boards into current mechanical structure. By using the so called “space
qualified” components such QFP packaging and the through-hole connector, the PCBs for the ASICs
had to be deported far from MAPMT as a result of lack of area. As the volume taken by the EC-ASICs
was reserved for the PDM board, several adjustments have to be done in order to accommodate the
PDM board and also the high voltage generator.
In order to check the feasibility and the assembly procedures, the mock up version of the EC-Front
boards have been produced. The assembly tests have been carried out with the MAPMTs and PDM
frame as shown in Figure 6.41, Figure 6.42 and Figure 6.43.
219
(a)
(b)
Figure 6.41 : (a) EC-Dynode assembly with 4 MAPMTs. (b) EC-Dynode placed on the PDM frame.
Figure 6.42 : The assembly of the EC-Anode boards (“straight” and “curved”) and the EC-Anode board.
(a)
(b)
Figure 6.43 : (a) Back side view of the PDM frame with the flexible part of the EC-Anode. (b) Close up
view of the PDM frame and the flexible cable coming out through the mechanical support structure.
220
Chapter 7 SPACIROC2
7.1 Introduction
A new version of the SPACIROC chip has been developed in order to improve the performances of
the first prototype (to be referred as SPACIROC1 in this chapter). Based on the ASIC characterisation
results and the feedbacks from the UFFO pathfinder project, the design improvements are mostly
applied to the analog part of the ASIC. The digital design was untouched for this ASIC version. In
terms of performances enhancement, the targets for SPACIROC2 are the following:



Reduction on the power consumption by 30%
Improvement on the Double Pulse Resolution for the Photon Counting (< 30 ns)
Improvement on the KI Time-Over-Threshold: Dynamic range extension and Reset
implementation
Along with the development of the electronics for JEM-EUSO project, the power consumption budget
is becoming a critical issue. Therefore, the power consumption reduction is an important aspect of
SPACIROC2 design. SPACIROC2 ASIC was submitted for production in November 2011. The packaged
chips were then received in March 2012. The general architecture for SPACIROC2 is shown in Figure
7.1.
Figure 7.1 : SPACIROC2 general architecture. The Photon Counting part is highlighted in light yellow
and the KI Time-Over-Threshold part is highlighted in light green. For this ASIC version the inputs are
only from the MAPMT anodes.
7.2 Photon Counting
The main target of the Photon Counting part is to improve the time resolution while having lower
power consumption. As stated the FSU trigger design is considered as the baseline for the Photon
221
Counting part, thus its design is untouched. Only minor modifications related to the power
consumption have been carried out for FSU trigger. The main modifications of this part were done
for the Pre-amplifier trigger which exhibits the lowest power consumption compared to the other
trigger design. The architecture of the Photon Counting part is illustrated in Figure 7.2.
Figure 7.2 : Photon Counting general architecture. The biggest changes are for the Pre-amplifier
trigger (Trig_PA).
The general architecture shown in Figure 7.2 is nearly identical to the one shown previously in
Chapter 3. The modification on the architecture is visible only for the Pre-amplifier trigger (Trig_PA)
where a variable resistance and a buffer have been introduced.
7.2.1 Pre-amplifier Trigger (Trig_PA) simulations
As shown in the Extracted Parasitics (post-layout) simulations (cf. Chapter 3 – Section 3.4.1), the Preamplifier trigger analog response is dominated with the parasitic capacitance. In order to decrease
the interstage parasitic capacitance, a buffer was added between the pre-amplifier output and the
discriminator. Furthermore, the resistance value which is used for the current to voltage conversion
is reduced. This is done in order to minimize the time occupancy of the pre-amplifier output. The
new resistances values are 5 and 10 kΩ compared to 30 kΩ used previously. The frequency
responses of Trig_PA are simulated in Figure 7.3.
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Figure 7.3 : The simulations of frequency responses for 5 and 10 kΩ pre-amplifier load. Solid black
plot (top) is for 5 kΩ load where the gain is 76 dBΩ and the bandwidth is 23 MHz. Solid blue plot
(bottom) is for 10 kΩ load where the gain is 81 dBΩ and the bandwidth is 28 MHz.
The transient simulations for the Trig_PA were done for both pre-amplifier loads. The simulations are
done for the post-layout (Extracted Parasitics) in order to verify the effectiveness of the buffer for
handling the input charge between 1 – 2 p.e (160-320 fC). The DC level at Trig_PA discriminator input
is shifted down by 0.8 V as the buffer is a simple voltage follower. Instead of 2.5 V, the DC level of the
pre-amplifier is now around 1.7 V. The transient simulations are shown in Figure 7.4 and Figure 7.5.
For each pre-amplifier load, the simulations were done for input charges of 1/3, 1, and 2 p.e (50, 160
and 320 fC). The threshold for the discriminator is set 15 mV below the DC level at the input of
Trig_PA discriminator.
223
Figure 7.4 : The transient simulations (post-layout) for 5 kΩ pre-amplifier load. The input charges are
1/3, 1, and 2 p.e (50, 160 and 320 fC). Top plots are the pre-amplifier output. Middle plots are the
buffer outputs. Bottom plots are for the discriminator (trigger) outputs.
Figure 7.5 : The transient simulations (post-layout) for 10 kΩ pre-amplifier load. The input charges
are 1/3, 1, and 2 p.e (50, 160 and 320 fC). Top plots are the pre-amplifier output. Middle plots are
the buffer outputs. Bottom plots are for the discriminator (trigger) outputs.
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The simulations shown in Figure 7.4 and Figure 7.5 indicate that for both pre-amplifier loads, Trig_PA
could trigger down to 1/3 p.e (50 fC). The main purpose of adding the buffer is of course to reduce
the loading effects due to the parasitic capacitances of the ASIC layout. This would improve the
Double Pulse Resolution where the target is to achieve a value lower than 30 ns. As summarized in
Table 7.1, the Double Pulse Resolutions obtained from post-layout or Extracted Parasitics simulations
are 21 and 23 ns for 5 and 10 kΩ of pre-amplifier loads respectively.
Parameter
Rpa = 5 kΩ
Extracted
Schematic
Parasitics
76 dBΩ
23 MHz
20 Mhz
Rpa = 10 kΩ
Extracted
Schematic
Parasitics
81 dBΩ
28 MHz
23 Mhz
Transimpedance
Bandwith
Double Pulse
17 ns
21 ns
20 ns
23 ns
Resolution (1 p.e)
Gain
1.4 mV/fC
0.8 mV/fC
2.4 mV/fC
1.4 mV/fC
Timewalk (1/3 - 2p.e)
2.3 ns
4.3 ns
1.7 ns
2 ns
SNR (1 p.e)
380
370
402
381
Power Consumption
0.32 mW
Table 7.1 : The characteristics of Trig_PA for 5 and 10 kΩ pre-amplifier loads.
7.2.2 VFS Trigger (Trig_VFS) discriminator design
For the VFS trigger (Trig_VFS), the shaper design itself was preserved as in SPACIROC1. From the
laboratory measurements (cf. Chapter 4 – Section 4.3.5), the dispersion of the trigger performances
among the 64 channels are quite important (17 DAC units RMS) which leads to the conclusion of the
discriminator design problem. For SPACIROC2, the discriminator design of Trig_VFS has been
replaced with a new one. The new discriminator design [68] is a typical two stage comparator.
However it employs almost exclusively NPN BJT transistors which offer better voltage matching,
lower power consumptions and higher speed than its CMOS counterpart. The target of this new
discriminator design is to achieve superior performances compared to the other discriminators
available in this ASIC within the same power budget.
In Figure 7.6, the performances of the discriminator of Trig_VFS are compared to the discriminator
used for Trig_FSU. The simulations are done in post-layout and a capacitor of 200 fF is used for the
output loading. The input used is a square signal of 50 mV which is a simple representation of a
shaper output corresponding to input charge of 50 fC and the gain is assumed to be 1 mV/fC.
Additionally a square input is used to verify the slew rate of the discriminator itself.
225
Figure 7.6 : Post-layout simulations for Trig_VFS and Trig_FSU. Top section corresponds to the
discriminator input (orange plot) where the threshold is set at 10 mV above the DC level. Bottom
section corresponds to the discriminator outputs: Trig_FSU discriminator (purple) and Trig_VFS
discriminator (cyan).
From the simulations results in Figure 7.6, Trig_VFS discriminator is more reactive than the
discriminator for Trig_FSU. The input to output delay for Trig_VFS discriminator equals to 3.2 ns
compared to 4 ns for Trig_FSU discriminator. Additionally, the slew rate achieved by the Trig_VFS
discriminator is around 1.3 V/ns which is considerably faster than 0.3 V/ns recorded by the Trig_FSU
discriminator.
The different characteristics of the Trig_VFS discriminator design are summarized in Table 7.2. In this
table the performances between schematics and Extracted Parasitics (post-layout) simulations are
compared. From the simulation results, the performances of Trig_VFS discriminator for both
simulations are nearly similar.
Parameter
Schematic
Extracted parasitic
Minimum input
15 mV
20 mV
Minimum input pulse width
4 ns
4 ns
Slew rate (Load = 200 fF)
1.3 V/ns
1.3 V/ns
Input/Output Delay
3.2 ns
4.3 ns
Power consumption
0.1 mW
Table 7.2 : The characteristics of Trig_VFS discriminator design for schematics and Extracted
Parasitics simulations.
The full simulations of Trig_VFS are shown in Figure 7.7. The simulations were done for input charge
of 1/3, 1 and 2 p.e (50, 160 and 320 fC). The threshold is set at 40 mV above the VFS shaper DC level.
From the simulation results shown in Figure 7.7, the newly designed discriminator is good enough to
be used within the Trig_VFS triggering chain.
226
Figure 7.7 : Extracted Parasitics (post-layout) simulations for Trig_VFS. Top section corresponds to
the VFS shaper outputs for different input charges: 50 fC (red plot), 160 fC (blue plot) and 320 fC
(orange plot). Bottom section corresponds to the discriminator output: 50 fC (red plot), 160 fC (blue
plot) and 320 fC (orange plot).
7.3 KI Time-Over-Threshold
For SPACIROC2, the inputs of the KI Time-Over-Threshold (ToT) are only from the MPAMT anodes.
The dynode input for this part is removed. The decision to remove the dynode input is due to the fact
that this input is AC coupled to the KI Time-Over-Threshold. Initially the dynode signal shall be used
for detecting intense arrival photon flux as it could damage the MAPMT. Typically in this kind of
event, the dynode signal would be most likely a DC level and it could not be detected by the KI TimeOver-Threshold as the dynode input is AC coupled. Additionally the intense photon flux detections
can be performed directly in an FPGA by using the data of this Time-Over-Threshold for the MAPMT
anodes.
The modifications of this ToT are mainly done for implementing the reset or a gate for the analog
side of this part. Eventually a minor modification was also done for extending dynamic range of the KI
Time-Over-Threshold. The operations principle of this Time-Over-Threshold block is still the same (cf.
Chapter 3 – Section 3.5). The general architecture of this module for SPACIROC2 is shown in Figure
7.8.
227
Figure 7.8 : KI Time-Over-Threshold general architecture. The reset/gating implementation is done by
adding a switch at the input, just before the Impedance Conversion block. The reset signal will also
force the discharging path of the Dynamic Range capacitors from the Current Sink to the DC feedback
reference and change the trigger output to low level.
7.3.1 Reset implementation
The basic idea of the reset implementation is to temporary disable the input signal while the reset
signal is applied. At the same time, the comparator output is forced to low level following the reset
signal. By doing so, the integrated signal path will be switched immediately to the DC feedback block
in order to be discharged. A dedicated LVDS input is used to reset the circuit and also mask the
output trigger. Figure 7.9 shows the switch implementation of the KI Time-Over-Threshold input.
Figure 7.9 : KI input (8-pixel-sum current source) switching implementation. The input is highlighted
in red box, “8-pixel-sum”. When the Reset signal is at high level, MN0 transistor is activated and the
input signal is routed into the KI Time-Over-Threshold circuit. On the other hand when Reset signal is
low, MN1 transistor is activated and the input current source is sunk directly into the power supply.
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Figure 7.10 : Simulations of KI analog signal reset. Top section plots represent the trigger outputs and
bottom section represents the analog signals of the KI. The applied reset is highlighted dashed red
circle. The black and blue dashed plots show the behaviour of the circuit after the reset compared to
the normal operations shown in solid blue and black plots.
By examining the analog signal (solid and dashed blue plots) shown in Figure 7.10, there is a dead
time which has to be taken into account after the reset is applied. This is due to the time taken by
the Dynamic Range capacitor to discharge and restore its initial DC level (cf. dashed blue plots in
Figure 7.10). The dead time depends on the selected value of the Dynamic Range capacitors and also
the resistivity of the DC Feedback path. The maximum discharge time according to different values of
Dynamic Range capacitors are shown in Table 7.3. The maximum discharge time is defined as the
time taken in order to reach 99% of this Time-Over-Threshold DC level (1.5 V).
Dynamic Range Capacitors
16 pF
24 pF
46 pF
Discharge time %99 (5*tau)(ns)
74
107
231
Table 7.3 : Maximum discharge for different Dynamic Range capacitors values. The values chosen are:
16 pF (min), 24 pF and 46 pF (max).
In Table 7.3, the dead time varies from 74 ns to 231 ns depending on the Dynamic Range capacitor
values. This dead time has to be taken into account especially for high speed sampling application
like JEM-EUSO. Specifically for JEM-EUSO application, resetting or gating the KI Time-Over-Threshold
operations is only required when the photon flux is very important. Otherwise in normal operation
(e.g. measuring Air Shower of 1020 eV energy range), this Time-Over-Threshold can operate without a
reset or a gate.
7.3.2 Input dynamic range extension
In order to increase the measurement ceiling of this Time-Over-Threshold module, the discharging
slopes for the Dynamic Range capacitors have to be increased as well. This is done by doubling the
maximum current in the Width Adjust (WA) module. It was done previously off-chip during the
229
measurements and characterisations of SPACIROC1 ASIC (cf. Chapter 4 – Section 4.3.8.1). The
maximum current for WA is now 64 µA compared to 32 µA in previous ASIC which will allow this
Time-Over-Threshold module to measure up to 180 p.e/GTU/pixel without requiring any gate or
reset usage. Table 7.4 summarizes the various discharge slopes available with for this ToT module.
The combination of WA current of 64 µA and Dynamic Range capacitor equals to 16 pF gives the
fastest discharging time where the discharge rate equals to 3672 mV/µs.
Slope(mV/µs)
DR = 16 pF
DR = 24 pF
DR= 46 pF
2
153
103
54
6
265
187
99
10
492
357
189
18
936
682
362
32
1608
1222
651
64
3672
2483
1322
Table 7.4 : KI integration slope vs WA current source. The Dynamic Range capacitor is set at 16, 24
and 46 pF.
WA(µA)
7.4 Power management and data transmission
The other design modifications for this ASIC concern mostly the power management and also the
data transmission. Modifications concerning the power management are the following:





Modifications in Photon Counting discriminators biasing stage
Corrections for FSU & VFS shaper OTA output stage
Adding power off switch for VFS shaper
LVDS receivers power off
ASIC pins rearrangement for facilitating off-chip power supply cut
With these modifications, each component of SPACIROC2 can be activated or deactivated completely
via the Slow Control registers. This will allow a great flexibility in the power management of this chip.
The power management in SPACIROC2 is more efficient than the previous ASIC as the design bugs
from previous version were corrected and several enhancements have been added as well.
Figure 7.11 illustrates the potential problems with the OTAs used for setting the DC level of the
Photon Counting’s FSU and VFS shapers (cf. Chapter 3 – Sections 3.4.2.1 & 3.4.3.1 for the OTA usage
in the shapers design). In SPACIROC1, the shapers can’t be disabled due to the fact that the shapers
will draw very huge current when they are turned off through the Slow Control registers. When
switched off, the output stage the OTA will sink a huge current into the shaper. This problem occurs
as the shapers are based on BJT transistors whereas the same design with the CMOS devices will not
have the same problem.
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Figure 7.11 : PMOS transistor (M1) used in the OTA could sink a huge current into the base (B) of BJT
transistor (Q1) of a shaper or amplifier. It could occur when M1 is left floating. The problem can be
resolved by cutting the path from M1 to Q1 (highlighted in red) with a switch.
Other modification to be mentioned concerns the digital data transmission. The data transmission for
this chip is done through a digital buffer which allows a level shift from the 3 V of the digital core to
1.5 V for the FPGA. Naturally the digital buffer should be designed correctly in order to have
sufficient driving strength. From the UFFO project (cf. Chapter 6 – Section 6.2), it seems that
SPACIROC1 digital buffer is not capable of driving 24 cm long cable to the FPGA at 40 MHz. In UFFO
project, the data transmission frequency was reduced to 20 MHz following this problem. However in
JEM-EUSO, 40 MHz data transmission has to be maintained as the GTU is required to be at 2.5 µs.
Otherwise digital data could not be transferred to the FPGA in time. Counter overflow could also
happen as event rate in JEM-EUSO is higher than in UFFO.
The simulations of the newly designed digital buffer are shown in Figure 7.12. The input for the
simulations is a square signal of 25 ns which represents 1 bit transmission at 40 MHz. The buffer is
loaded with a 40 pF capacitor.
231
Figure 7.12 : Simulations digital output buffer for a load of 40 pF. Gold plot represents the new
buffer output compared to black plot which represent the old buffer. With a square 25 ns input, new
buffer output width is around 22 ns which is adequate for transmitting data at 40 MHz. The old
buffer is not capable of reaching the required 1.5 V amplitude or has sufficient width for 40MHz data
transmission.
The characteristics of the digital buffer are summarized in Table 7.5. The simulations were done for
selected capacitive load values of 1 pF (typical ASIC pad value), 15 pF (typical test board value) and 40
pF (maximum loading).
Load (pF)
1
15
40
Rise time (ns)
0.7
5.6
13.7
Fall time (ns)
0.4
2.7
6.2
Table 7.5 : Digital buffer characteristics for capacitive loading of 1, 15 and 40 pF.
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7.5 Measurement Results
Typical measurements such as noise, S-curves and charge injection have been carried out in order to
check the performances of this ASIC. The measurements have been started in May 2012, with a
newly designed test board and a batch of 5 SPACIROC2 ASICs packaged in CQFP208. Towards August
2012, another batch of 5 ASICs packaged in PQFP208 and 2nd version of SPACIROC2 test boards have
been received from our Japanese partner.
7.5.1 Noise
The noise measurements have been carried out for all channels of each analog component of
SPACIROC2. The results are compared to the noise measurements of SPACIROC1 as shown in Table
7.6.
RMS Noise (mV)
SPACIROC2
SPACIROC1
Rpa = 5 kΩ
0.178 ±4%
PA
0.218 ±1.2%
Rpa = 10 kΩ
0.269 ±7%
FSU (Rf = 25 kΩ, Cf = 175fF)
0.998 ±7.8%
1.47 ±9.5%
VFS
0.875 ±8.6%
1.3 ±9.3%
Table 7.6 : Average RMS Noise comparison between SPACIROC2 and SPACIROC1.
Components
From the measurement results in Table 7.6, the noise performances of SPACIROC2 are more than
satisfying. In general, the measured RMS noise of this chip is slightly lower when compared to
SPACIROC1 chip.
7.5.2 Photon Counting
Several tests have been done in order to check the performances of Photon Counting module. The
first measurement is the trigger efficiency tests or S-curves which were done by injecting charges of
1/3 p.e (50 fC) and sweeping the discriminator threshold. Next, several measurements were done for
checking each triggering scheme gain. The gain measurements are based on the S-curves method but
with various input charges. Finally the tests for checking the Double Pulse Resolution have also been
carried out for each Photon Counting trigger.
233
7.5.2.1 Trigger S-curves
Pre-amplifier Trigger (Trig_PA)
The measurement results for Trig_PA are shown in Figure 7.13 and Figure 7.14. In these plots, the
Pre-amplifier load is set at 10 kΩ.
Figure 7.13 : Trig_PA S-curves for 50 fC input charges. The pedestals are shown in green plots and the
triggering efficiency for 50 fC input charges are shown in red plots.
Figure 7.14 : Distribution of Trig_PA 50% triggering efficiency for 50 fC input charges. The average
threshold is at 954.6 DAC with the RMS of 1 DAC unit.
From the results presented in Figure 7.13 and Figure 7.14, we could conclude that all 64 channels of
Trig_PA could trigger the input charges of 50 fC. With RMS of 1 DAC unit for the 50% triggering
234
efficiency, the uniformity between the channels of this trigger design can be considered as quite
good.
FSU Trigger (Trig_FSU)
The configuration of FSU shaper used in here is Cf = 175 fF and Rf = 25 kΩ which is considered as the
baseline configuration for Photon Counting.
Figure 7.15 : Trig_FSU S-curves for 50 fC input charges. The pedestals are shown in green plots and
the triggering efficiency for 50 fC input charges are shown in red plots.
Figure 7.16 : Distribution of Trig_FSU 50% triggering efficiency for 50 fC input charges. The average
threshold is at 92.3 DAC with the RMS of 2.3 DAC unit.
235
This trigger design is identical to the one in SPACIROC1. Therefore this design is expected to trigger
down to 50 fC without any difficulties. The threshold uniformity for all channels is still good which is
shown by its RMS value of 2.3 DAC units.
VFS Trigger (Trig_VFS)
For Trig_VFS design, its discriminator was replaced with a new design in SPACIROC2. This
discriminator is supposed to have superior performances compared to other discriminators available
in this ASIC.
Figure 7.17 : Trig_VFS S-curves for 50 fC input charges. The pedestals are shown in green plots and
the triggering efficiency for 50 fC input charges are shown in red plots.
Figure 7.18 : Distribution of Trig_VFS 50% triggering efficiency for 50 fC input charges. The average
threshold is at 112.25 DAC with the RMS of 3.48 DAC unit.
236
As shown in Figure 7.17 and Figure 7.18, the Trig_VFS design could trigger down to 50 fC for all
channels, which was not the case in SPACIROC1. Additionally the threshold uniformity for all
channels is good where the dispersion is around 3.48 DAC units.
7.5.2.2 Gain measurements
For the measurements in this section, the triggering efficiency of each trigger design is verified
according to the input charges. From this type of measurements, the characteristics such as gain,
minimum input and saturation can be extracted.
Pre-amplifier Trigger (Trig_PA)
The measurements shown in Figure 7.19 were done for channel 32 which represents one of the best
channels for Trig_PA. In this measurement, the pre-amplifier load is set at 10 kΩ.
Figure 7.19 : Trig_PA Channel 32 - 50% Triggering Efficiency vs Input Charges. The measured gain is
0.563 mV/fC and the minimum detectable input is 30 fC.
From Figure 7.19, the measured gain for Trig_PA is around 0.563 mV/fC. The minimum charge can be
detected by this trigger is around 30 fC.
FSU Trigger (Trig_VFS)
Similar to Trig_PA, the measurements for Trig_FSU were also done for channel 32. The values of the
feedback capacitor and resistor of FSU are set to the baseline configuration which is Cf = 175 fF and Rf
= 25 kΩ. The measurement results are shown in Figure 7.20.
237
Figure 7.20 : Trig_FSU Channel 32 - 50% Triggering Efficiency vs Input Charges. The measured gain is
1.23 mV/fC and the minimum detectable input is 20 fC.
The gain obtained for Trig_FSU is 1.23 mV/fC. This value is in agreement with the gain measured in
SPACIROC1 which is 1.11 mV/fC for the same FSU configuration. The minimum detectable input is
equal to 20 fC which is similar to the previous ASIC.
VFS Trigger (Trig_VFS)
The gain measurements for Trig_VFS were also done for channel 32 and the results are shown in
Figure 7.21.
Figure 7.21 : Trig_VFS Channel 32 - 50% Triggering Efficiency vs Input Charges. The measured gain is
1.18 mV/fC and the minimum detectable input is 20 fC.
238
With the measured gain of 1.18 mV/fC and minimum detectable input charges of 20 fC, the
characteristics of Trig_VFS is rougly the same as SPACIROC1.
7.5.2.3 Double Pulse Resolution
In this measurement, 2 inputs of 1 p.e (160 fC) were injected consecutively. The delay between the 2
pulses was then reduced gradually until the Photon Counting part can’t distinguish the double pulse.
The threshold was set 1/3 p.e for this measurement. For Trig_PA, the load was equal to 10 kΩ and
the feedback capacitor and resistor configuration for FSU is Cf = 175 fF and Rf = 25 kΩ. The results are
shown in Table 7.7.
Double Pulse Resolution
Photon Counting
Trigger
SPACIROC2
SPACIROC1
Trig_PA
28.5
36
Trig_FSU
30
30
Trig_VFS
22
20
Table 7.7 : SPACIROC2 Double Pulse Resolution. The Double Pulse Resolution for Trig_PA is improved
in SPACIROC2. Meanwhile the time resolution for Trig_VFS is increased with the new discriminator.
The improvement can be seen for Trig_PA where the Double Pulse Resolution is much lower when
compared to the performances of the same trigger in SPACIROC1. The improvement of the Double
Pulse Resolution for Trig_PA is expected as a buffer for the analog signal is included in this trigger
design.
7.5.2.4 Summary of Photon Counting performances
The performances of the Photon Counting triggers are summarized in Table 7.8. The same
measurements from SPACIROC1 are also included for comparison.
Double Pulse Resolution
Photon
Gain (mV/fC)
Minimum Charges (fC)
(ns)
Counting
Trigger SPACIROC2 SPACIROC1 SPACIROC2 SPACIROC1 SPACIROC2 SPACIROC1
Trig_PA
0.563
0.4
30
20
28.5
36
Trig_FSU
1.23
1.11
20
20
30
30
Trig_VFS
1.18
1.29
20
23
22
20
Table 7.8 : The comparison of Photon Counting triggers performances between SPACIROC1 and
SPACIROC2. Trig_FSU and Trig_VFS can be compared directly as the configurations for both design
are identical in SPACIROC1 and SPACIROC2. For Trig_PA, the loading resistor used for SPACIROC2
measurement is 10 kΩ instead of 30 kΩ in SPACIROC1.
From the data in Table 7.8, we can conclude that SPACIROC2 has at least identical performances for
Trig_FSU and Trig_VFS when compared to SPACIROC1. On the other hand, the gain of Trig_PA of
SPACIROC2 seems to be superior when compared to the same trigger design in SPACIROC1. The
performances of Trig_PA are as expected thanks to the buffer added to this trigger design.
7.5.3 Time-Over-Threshold
For the KI Time-Over-Threshold, several measurements have been carried out in order to verify the
functionality of this module. The measurements shown in Table 7.9 correspond to the discharge
rates or slopes for the Dynamic Range (DR) capacitor array which is used for integrating the input
signals. As the discharge is done through the Width Adjust (WA) current source, tuning the WA
239
values would result a longer or shorter discharging duration. In SPACIROC2, the DR values are
identical to SPACIROC1. However the WA maximum value has been increased to 64 µA instead of 32
µA in SPACIROC1. This is done in order to accommodate higher rate of arrival photons when
observing the Air Shower.
Slope(mV/µs)
DR=16 pF
DR=24 pF
DR=46 pF
Sim
Measure
Sim
Measure
Sim
Measure
6µA
270
210
190
150
100
80
10µA
490
370
360
260
190
130
18µA
940
730
680
530
360
300
32µA
1610
1300
1220
790
650
490
64µA
3670
2140
2480
1570
1320
840
Table 7.9 : KI integration slope vs WA. The DR capacitor is set at 16, 24 and 46 pF.
WA
Specifically for high signal rate application like JEM-EUSO, the configuration of WA=64 µA and DR =
16 pF is particularly useful as the discharge slope is the fastest (2140 mV/µs – cf. Table 7.9). Based
on the previous measurements done with SPACIROC1 ASIC (Chapter 4 – Section 4.3.8.1), this
configuration could integrate the signal with the maximum rate of 180 p.e/GTU/pixel. However these
performances are yet to be confirmed with SPACIROC2.
Charge linearity
The charge linearity measurements for this Time-Over-Threshold module were done by varying the
input from 6 pC up to 220 pC. The charges are injected simultaneously into 8 pre-amplifier channels
which correspond to 1 KI measurement channel. The measurement results are shown in Figure 7.22.
Figure 7.22 : KI 8-Pixel-Sum count linearity versus input charge. The DR capacitor is set at 16 pF and
WA current source is equal to 2 µA. The measurement was done from 6 pC to 220 pC.
The measurements in Figure 7.22 indicate that this Time-Over-Threshold module is capable of
integrating input charges up to 220 pC. Even though the shown measurements don’t represent the KI
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measurements for an Air Shower in JEM-EUSO experiment, the results still can give a good
representation on how this module could handle huge input charges.
7.6 Conclusion
From the preliminary measurements of SPACIROC2, we can conclude that there are improvements
compared to the previous version. The main improvements can be classified as the following:




Lower power consumption thanks to better power management (~0.8 mW/channel).
Better Double Pulse Resolution for Trig_PA.
Trig_VFS non-uniformity problem was corrected.
Faster discharge duration for KI Time-Over-Threshold.
With the presented measurement results, SPACIROC2 fulfils at least the main requirements of this
chip design: 100% triggering for 1/3 p.e (50 fC), 30 ns minimum Double Pulse Resolution, low-power
consumption. Further tests will be carried out in order to produce the full specifications of this chip
and to verify its performances with the MAPMT under the JEM-EUSO running conditions.
241
Conclusion
During the 3 years of working for JEM-EUSO experiment within OMEGA microelectronics group at
Laboratoire de l’Accélérateur Linéaire, I have been involved with every technical aspects of an ASIC
design: from the simulations to the layout of the analog and digital parts and the ASIC
characterization and the full detector instrument tests (from the physics to the computing).
A high-speed, low-power and multi-channel ASIC has been proposed for reading out the 64-channel
Hamamatsu R11265-M64 MAPMT which will be used to equip the focal surface of the JEM-EUSO
florescence telescope. The SPACIROC ASIC was then conceived by combining the expertise of OMEGA
in fast photon counting and ISAS/JAXA knowledge in Time-Over-Threshold design. The ASIC is
required to trigger at least 1/3 p.e (50 fC), to have power dissipation less than 1 mW/channel and to
measure up to 200 pC for 8 summed channels.
My work in this thesis can be divided in to 3 different themes:
A. ASIC design
I took the responsibility to design (coding, simulations and layout) the digital part of
SPACIROC by taking into account the required gate time for the data transmission. The digital
design was done carefully in order to minimize digital noise on the ASIC substrate.
Additionally the digital part was also designed so that a simple yet robust data readout
system can be implemented on the FPGA side. To complete the design of SPACIROC, I was in
charge of transferring the KI Time-Over-Threshold design from our Japanese partners to the
chip. For this part I did overall simulations of this module and finalizing its layout for the
tapeout.
For SPACIROC2 I was fully in charge of the analog core of the ASIC. The biggest works done
for the analog part are the simulations, bug corrections, components re-design and
improving the design of the Pre-amplifier trigger (Trig_PA). The works on SPACIROC2 were
mainly based on the feedbacks from SPACIROC tests and front-end board integration. Thanks
to the characterization results, the power consumption was reduced by 30% (0.8
mW/channel), the Double Pulse Resolution of Trig_PA is lower than 30 ns and better
uniformity for VFS trigger (Trig_VFS) is achieved. Improvement also have been done to the KI
design in order to cope with higher arrival photon rate (180 p.e/GTU/pixel).
B. ASIC characterizations and tests
The tests of SPACIROC were started in October 2010. During this phase, my main works were
to characterize the Photon Counting and KI Time-Over-Threshold part. During the ASIC
characterizations I singled out the problem with the ASIC power management and Trig_VFS
discriminator design. The SPACIROC ASIC was also then tested with MAPMT where I pointed
out the limitation of the KI Time-Over-Threshold module in handling the high arrival photon
rate.
C. Front-end board design and ASIC integration.
I was involved deeply in the design of electronics front-end especially for UFFO project. This
project is proven to be very challenging as we were trying to accommodate the high voltage
242
power supplies and low voltage components in a very small area. My works concerned the
signal integrity of the ASIC, electromagnetic compatibility of the boards, high voltage
integration in the PCB and the communications between the ASIC and the FPGA.
Due to my involvement with JEM-EUSO, I was given the opportunity to work on the design of a very
innovative ASIC. Designing mixed signal ASIC with strict requirements like JEM-EUSO is particularly
challenging endeavor. Fortunately, I had a lot of guidance from senior designers at OMEGA which
really enhance my knowledge in analog and digital design. With my involvement in different aspects
of this project, I could have a larger view of the instrument’s main components such as the photodetector, the readout ASIC and the main controller. Naturally it is easy for me to see the advantages
of integrating the readout ASIC in proximity of the detector.
Perspectives
Concerning the chip design, there are still rooms for optimizing the analog performances. Thanks to
the SiGe process, the analog part of SPACIROC exhibits very good performances in terms of speed,
Signal-to-Noise ratio and power consumption. However when combining the digital part, noise
performances degrade very quickly due to the substrate coupling effect. Based on the measurements,
the digital part of SPACIROC contributes around 0.8 mV RMS in addition to the analog part noise.
Therefore several precautions should have been taken in designing the digital part. For example,
signaling the data transfer (Start Bit) simultaneously on each data output would not be necessary as
it will only induce more coupling into the chip substrate. Of course this effect could be worst if high
slewing digital drivers are used for transferring the data. Another consideration which could reduce
the impact of the digital part on the analog performance is to lower the bit count for the internal
data transfer. The data transferred internally could matter especially several identical modules
operate simultaneously like the digital part of SPACIROC ASIC. The digital noise increases also the
non-uniformity between the analog channels as the channels with input pads closer to the digital
part will exhibit higher noise compared to the others. One of the easy ways to reduce this effect is to
introduce additional ground pads close to the concerned input. Naturally this solution is very
effective but it will increase the ASIC lead counts. Otherwise the distance between the analog core
and the digital part can be increased in order to reduce the pickup noise in the analog channel. But
this solution is less effective than the grounding. For the next iteration of SPACIROC chips, the digital
part should be revised in order to reduce its noise contributions.
For the analog design, the design has been really pushed to the limit especially on the power budget
in order to offer the highest counting rate, flexibility in the configurations, huge charge integration
and very low power consumption. For finalizing the flight model design, it is most likely that one or
two trigger design in Photon Counting module will be removed. If required, most of the analog part
consumption could be scaled down slightly (for example to reach 0.5 mW/channel). However this
operation could penalize the timing and speed in the Photon Counting module. On the other hand,
several optimizations can be incorporated to the KI Time-Over-Threshold module. This module has
been proven to be capable of measuring the Air Shower in the 1020 eV energy range. However it is
very desirable that this module could handle perfectly other type of signal especially for the MAPMT
protection purpose. Further tests with the MAPMT for simulating other atmospheric phenomena
243
shall confirm the effectiveness of this Time-Over-Threshold module for the photodetector protection
strategy. Otherwise, the dynode channel could be restored in the ASIC and a simple circuit only for
the MAPMT protection usage can be implemented.
As highlighted in Chapter 6, the front-end electronic boards for JEM-EUSO could represent a huge
challenge for completing the instrument in the flight model version. Currently we have studied and
fabricated two different types of front-end (UFFO and EUSO-Balloon). Neither of those two front-end
boards would really fit the space flight JEM-EUSO electronics requirements such as safety issues and
mass budget. One of the plausible solutions is to combine the best features of both front-end studies
which are separating the low voltage components from the high voltage part and using a compact
solution based on Chip-on-Board or any other bare ASIC bonding technology. There are some
arguments concerning the Chip-on-Board or similar technology especially on the component
qualifications. At one point, combining very huge number of pixels within a small area using the
standard components (e.g. standard ASIC packaging) will not able to fit the mass budget, let alone
the real estate problem. Somehow fulfilling the requirements will eventually outweigh the hassle of
qualifying a component. Additionally the Chip-on-Board solution is not unknown to the space
industries. For example the near-IR instrument of James Webb Space Telescope is equipped with the
readout ASICs [69] which are wired bonded directly on the front-end boards.
244
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Acknowledgements
I would like to express my gratitude to numerous people who have helped me in completing this
thesis. If I have to name everyone, the list would be very long.
First of all, I would like thank all the jury members: Prof. Achille Stocchi, Dr. Christophe de La Taille,
Dr. Sylvie Dagoret-Campagne, Dr. Marc Winter, Dr. Marco Casolino and Dr. Philippe Gorodetzky.
Thank you very much for evaluating my work.
My gratitude also goes to the director of Laboratoire de l’Accélérateur Linéaire, Prof. Achille Stocchi,
and the administrative staff. I’m very grateful to be given a chance to complete my phd in this lab.
I’m also very indebted to my research supervisors: Dr. Christophe de La Taille and Dr. Sylvie DagoretCampagne. Thank you for the support, numerous advice and valuable insights in microelectronics
(Christophe) and physics (Sylvie).
Special big thanks to OMEGA team:
To Gisèle, thank you very much for taking care of me during my stay here. Thanks to Nathalie for all
the long discussions on the analog design. Frédéric, thank you for your help from the beginning and
also recruiting me! To Pierre and Sylvie, without your countless help on the chip design, tests and
many more, I don’t think this thesis could be done. To Stephane, thanks for always being around
during the uncountable late nights in the office (and also for the $100 shushi ). Thanks to my
officemates, Damien and Jeanne, who have been very nice to me (and not too noisy in the office ).
To Ludovic and Selma, thank you for sharing all the jokes and also the advices. To my mate Aftab,
thank you for correcting my French. Benoit and Taibi, thanks a lot for the good time. I appreciate all
the support, help and expertise from OMEGA in designing the ASIC for JEM-EUSO.
Many thanks also for the Service Electronique (SERDI) people. Especially the guys from CAD
(Dominique C and the others), cabling and firmware group. Without them it will be difficult to
conceive all the boards that I’ve been working with. Special thanks also to JPM for his expertise in
Cadence troubleshooting (yes I crashed the software so many times).
Thank you also for the people from JEM-EUSO collaboration. My special thought goes to the French
part of the collaboration at APC (Philippe and Carl) especially for their help during the MAPMT tests.
The same goes for the Korean group where I couldn’t forget the extended working hours in Seoul. Of
course many thanks to the friends from around the world that I met while working for the
collaboration : Aera, Gowoon, Hiroko, Angelica, Hector and Jorg.
Last but not least, very special thanks to my beloved parents and family who always supported me.
250
List of acronyms
AC : Alternating Current
ADC : Analog-to-Digital Converter
AGASA : Akeno Giant Air Shower Array
AGN : Active Galactic Nuclei
AMS: Austriamicrosystem
ASIC : Application Specific Integrated Circuit
BiCMOS : Bipolar-CMOS
CAMAC : Computer Automated Measurement and Control
CCB : Cluster Control Board
CMB : Cosmic Microwave Background
CMOS : Complementary Metal–Oxide–Semiconductor
CMP : Circuit Multi-Projets
CNES : Centre National d’Etude Spatiale
COB : Chip-on-Board
DAC : Digital-to-Analog Converter
DC : Direct Current
DPU : Data Processing Unit
DR : Dynamic Range capacitors – cf. KI Time-Over-Threshold design
EAS : Extensive Air Shower
EC : Elementary Cell
EDAC : Error Detection and Correction
ENC : Equivalent Noise Charge
ESA : European Space Agency
ESAF: EUSO Simulation & Analysis Framework
FD : Fluorescence Detector
FEE : Front-end Electronics
251
FIFO : First In, First Out
FOV : Field-of-View
FPGA : Field Programmable Gate Array
FS : Focal Surface
FSU : Fast Shaper Unipolar
GBW : Gain-Bandwidth
GND : Ground
GPIB : General Purpose Interface Bus
GRB : Gamma-ray Burst
GTU : Gate Time Unit
GZK : Greisen–Zatsepin–Kuzmin
HBT : Heterojunction Bipolar Transistor
HTV : H-II Transfer Vehicle
IC : Integrated Circuit
IR : Infrared
ISS : International Space Station
JAXA : Japan Aerospace Exploration Agency
JEM-EUSO : Extreme Universe Space Observatory on Japanese Experiment Module
KI : Konan University/ISAS
LAL : Laboratoire de l’Accélérateur Linéaire
LED : Light-Emitting Diode
LET : Linear Energy Transfer
LG : Loop Gain
LIDAR : Light Detection And Ranging
LOCOS : Local Oxidation of Silicon
LSB : Least Significant Bit
MAPMT : Multianode Photomultiplier
252
MEMS : Microelectromechanical Systems
MOS(FET) : Metal–Oxide–Semiconductor Field-Effect Transistor
MPU : Micro Processor Unit
NASA : National Aeronautics and Space Administration
NIEL : Non-Ionizing Energy Loss
NIST : National Institute of Standards and Technology
NMOS : n-channel MOSFET
NOSYCA : Nouveau Système de Contrôle d'Aérostats
NPN : One of the two types of Bipolar transistors. P-doped "base" between two N-doped layers.
OTA : Operational Transconductance Amplifier
p.e : photoelectron
PA : Pre-amplifier
PCB : Printed Circuit Board
PD : Photo-Detector
PDM : Photo-Detection Module
PMOS : p-channel MOSFET
PMT : Photo Multiplier Tube
PNP : One of the two types of Bipolar transistors. N-doped "base" between two P-doped layers.
PSF : Point Spread Function
RIKEN : Rikagaku Kenkyūjo (The Institute of Physical and Chemical Research)
RMS : Root Mean Square
Roscosmos : Russian Federal Space Agency
SCB : Super Common Base
SEE : Single Event Effect
SEL : Single Event Latchup
SEU : Single Event Upset
SiGe : Silicon-Germanium
253
SiPM : Silicon photomultiplier
SMD : Surface Mount Device
SN : Supernovae
SNR : Signal-to-Noise Ratio
SOI : Silicon On Insulator
SPD : Shower-detector Planes
STI : Shallow Trench Isolation
SWIFT : Swift Gamma-Ray Burst Mission
TID : Total Ionizing Dose
TLE : Transient Luminous Event
TM/TC : Telemetry/Telecommand
TMR : Triple Modular Redundancy
ToT : Time-Over-Threshold
Trig_FSU : FSU Trigger
Trig_PA : Pre-amplifier Trigger
Trig_VFS : VFS Trigger
TUS : Russian abbreviation for “Tracking Instrument”
UBAT : UFFO Burst Alert & Trigger Telescope
UFFO : Ultra Fast Flash Observatory
UHECR : Ultra High Energy Cosmic Ray
UV : Ultraviolet
VFS : Very Fast Shaper
WA : Width Adjust – cf. KI Time-Over-Threshold design
254