9. Spare Part List

Transcription

9. Spare Part List

PRESTIGIO NOBILE 150
TECHNICAL SERVICE MANUAL
Contents
1. Hardware Engineering Specification ………………………………………………………………………. 4
1.1 Introduction ………………………………………………………………………………………………………………… 4
1.2 Other Functions …………………………………………………………………………………………………………… 38
1.3 Peripheral Components …………………………………………………………………………………………………... 42
1.4 Power Management ……………………………………………………………………………………………………….. 46
1.5 Appendix 1 : Intel 82801DBM ICH4-M GPIO Definitions ……………………………………………………………... 49
1.6 Appendix 2 : Prestigio Nobile 150 Product Specification ………………………………………………………………. 50
2. System View and Disassembly ……………………………………………………………………………...
51
2.1 System View ……………………………………………………………………………………………………………….. 51
2.2 System Disassembly ……………………………………………………………………………………………………….. 54
3. Definition & Location of Connectors / Switches …………………………………………………………..
78
3.1 Mother Board-A ……………………………………………………………………………………………………………. 78
3.2 Mother Board-B ……………………………………………………………………………………………………………. 79
4. Definition & Location of Major Components ……………………………………………………………..
80
4.1 Mother Board-A …………………………………………………………………………………………………………… 80
4.1 Mother Board-B …………………………………………………………………………………………………………… 81
5. Pin Description of Major Component …….………………………………………………………………..
82
5.1 Intel Pentium M Processor ……………………………………………………………………………………………….. 82
Contents
5.2 Intel Montara-GME Memory Controller Hub (GMCH) ………………………………………………………………. 86
5.3 Intel 82801DBM I/O Controller Hub Mobile (ICH4-M) ……………………………………………………………….. 95
6. System Block Diagram ………………………………………………………………………………………
103
7. Maintenance Diagnostics ……………………………………………………………………………………
104
7.1 Introduction ……………………………………………………………………………………………………………….. 104
7.2 Maintenance Diagnostics………………………………………………………………………………………………….. 105
7.3 Error Codes ……………………………………………………………………………………………………………….. 106
8. Trouble Shooting …………………………………………………………………………………………….
108
8.1 No Power …………………………………………………………………………………………………………………… 109
8.2 No Display …………………………………………………………………………………………………………………. 115
8.3 VGA Controller Failure LCD No Display ……………………………………………………………………………….. 118
8.4 External Monitor No Display …………………………………………………………………………………………….. 120
8.5 Memory Test Error ……………………………………………………………………………………………………….. 122
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………………… 124
8.7 Hard Driver Test Error …………………………………………………………………………………………………… 126
8.8 CD-ROM Driver Test Error ……………………………………………………………………………………………… 128
8.9 USB Port Test Error ………………………………………………………………………………………………………. 130
8.10 Audio Failure …………………………………………………………………………………………………………….. 132
8.11 LAN Test Error ………………………………………………………………………………………………………….. 135
8.12 PC Card Socket Failure …………………………………………………………………………………………………. 137
Contents
8.13 TV Test Error….…………………………………………………………………………………………………………. 139
9. Spare Parts List ……………………………………………………………………………………………...
141
10. System Exploded Views ……………………………………………………………………………………
153
11. Circuit Diagram ……………………………………………………………………………………………. 155
12. Reference Material ………………………………………………………………………………………… 184
Prestigio Nobile 150
1. Hardware Engineering Specification
1.1 Introduction
1.1.1 General Description
This document describes the brief introduction for Prestigio Nobile 150 portable notebook computer system.
1.1.2 System Overview
The Nobile 150 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It
can support Banias 1.3GHz ~ 1.7GHz. ,Dothan 1.7GHz ~ 1.9GHz, and Banias Celeron 1.2GHz ~ 1.4GHz.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface
(ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can
be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC Power indicator, Battery Power indicator, Battery status indicator, CD-ROM, HDD, NUM LOCK,
CAP LOCK, and SCROLL LOCK. It also equipped with LAN, 56K Fax MODEM, 4 USB port, 3D stereo audio
functions, S-Video and audio line out, and internal microphone.
The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC2100/PC2700 DDR-SDRAM
4
The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port
(DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M.
The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller , the IDE Master/Slave controllers,
and Intel Hub interface technology.
The VIA VT6105LOM “Rhine III” Ethernet controller is a cutting edge, feature-rich, and cost-competitive single
ASIC chip solution for PC “LAN On Motherboard” applications or Low Cost NIC applications. The 6105LOM
eases server processor utilization by optimizing throughput between NIC and PCI bus allowing data transfers of up
to at 200Mbps in full duplex mode, without using the system CPU. The VT6105LOM contains advanced power
management feature for low power consumption including Wake On LAN (WOL) and is implemented using a low
power 0.22 micron design.
The TIE PCI1410A device is a high-performance PCI-to-PC Card controller that supports a single PC Card socket
compliant with the PC Card Standard. The PCI1410A device provides features that make it the best choice for
bridging between PCI and PC Cards in both notebook and desktop computers. The PC Card Standard retains the 16bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, as
being capable of full 32-bit data transfers at 33 MHz. The PCI1410A device supports both 16-bit and CardBus PC
Cards, powered at 5 V or 3.3 V, as required.
5
The ALC101 is an 18-bit, full duplex AC'97 2.2 compatible stereo audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC101 AC'97 CODEC supports multiple
CODEC extensions with independent variable sampling rates and built-in 3D effects. The ALC101 CODEC
provides a pair of stereo outputs with independent volume controls and multiple stereo and mono inputs, along with
flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital
interface circuitry of the ALC101 CODEC operates from a 5V/3.3V power supply with EAPD (External Amplifier
Power Down) control for use in notebook and PC applications. The ALC101 integrates a 50mW/20ohm headset
audio amplifier into the CODEC, saving BOM costs.
The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and transmits
data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable
voltage data port which supports five different data format including RGB and YcrCb. The TV-Out processor will
perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the
NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text
display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan
capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video
quality. Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the
input data.
The Winbond mobile keyboard and embedded controller W83L950D architecture consists of a Turbo-51 core logic
controller and surrounded by various components, 2K+256 bytes of RAM, 40K on-chip MTP-ROM, ISA or
LPChost interface, 9 general purpose I/O port with 13 external interrupt source, 4 timers, 2 serial port, 2 SMBus
interface for master and slave, 3 PS2 port, two 8-bits and two 16-bits PWM channels, 2 D-A and 8 A-D converters.
6
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows XP to
take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced Power
Management (APM) with application restart, software-controlled power shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
System Parts
CPU : Intel Banias processor in Micro-FCPGA package
Synthesizer : PLL207-151
North Bridge : Montara-GME GMCH
South Bridge : ICH4-M
TV-Out : CH7011A
Keyboard System: Winbond W83L950D Universal Controller
Fax/Modem : Billonton MDC56S-I56Kbps Fax Modem
LAN Single Chip : VT6105LOM
PCMCIA Controller : TIPC1410A
7
AC’97 Codec : ALC101
Thermal Sensor : ADT7460
System Flash Memory (BIOS)
1.1.2.1 CPU Module : Banias
Intel Banias Processors with 478 pins Micro-FCPGA package.
The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyperpipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced
dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming
SIMD Extensions 2 (SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia
applications including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data
four times per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the
voltageand frequency between two performance modes.
8
1.1.2.2 Synthesizer : PLL207-151
System frequency synthesizer: PLL207-151
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions.
Programmable watchdog safe frequency.
Support I2C Index read/write and block read/write operations.
Use external 14.318MHz crystal.
1.1.2.3 Montara-GME GMCH IGUI 3D Graphic DDR/SDR Chipset
Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel
Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP
4X interface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M.
Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with
integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep InOrder-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D
Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Banias series based PC systems. It also integrates a high performance DDR333 Memory controller to
9
sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the
multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP slot with
AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub
architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-Mtogether. Intel®’
I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB
bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded
I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer
dataw/533MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multithreaded I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/533MB/s from/to Multithreaded I/O Link layer to/from INTEL 82801DBM ICH4-M.
An Unified Memory Controller supporting DDR333 DRAM is incorporated, delivering a high performance data
transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining
the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH
adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
Features :
Processor/Host Bus Support
• Intel® Banias processor
• 2X Address, 4X Data
10
• Support host bus Dynamic Bus Inversion (DBI)
• Supports system bus at 400MT/s (100 MHz)
• Supports 64-bit host bus addressing
• 8-deep In-Order-Queue
• AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation
(1.05V)
• Supports Enhanced Intel® SpeedStepTM Technology (EIST) and Geyserville III
• Support for DPWR# signal to Banias processor for PSB power management
Memory System
• Directly supports one DDR channel, 64-bits wide (72-b with ECC)
• Supports up 2 Double-Sided SO-DIMMs(4 rows populated) with unbuffered PC1600/PC2100/PC2700
DDR (with or without ECC)
• Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x
16 devices
• All supported devices have 4 banks
• Supports up to 16 simultaneous open pages
• Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row
11
• Support for memory self refresh in C3
• UMA support only
System Interrupt
• Supports 8259 and Processor System Bus interrupt delivery mechanism
• Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface
• MSI sent to the CPU through the system Bus
• From IOxAPIC in ICH4-M
• Provides redirection for upstream interrupts to the System Bus
• Video Stream Decoder
• Improved HW Motion Compensation for MPEG2
• All format decoder (18 ATSC formats) supported
• Dynamic Bob and Weave support for Video Streams
• Software DVD at 60 fields/second and 30 frames/second full screen
• Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization
• Video Overlay
• Single high quality scalable overlay and second Sprite to support second overlay
12
• Multiple overlay functionality provided viaArithmetic Stretch Blt
• Direct YUV from Overlay to TV-out
• Independent Gamma Correction
• Independent Brightness / Contrast / Saturation
• Independent Tint / Hue support
• Destination Color keying
• Source Chromakeying
• Maximum source resolution of 1920x1080 pixels
• Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or
1280x1024@ 85 Hz
Display
• Analog Display Support
• 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor up to
1800x1350 @ 85 Hz
• Accompanying I2C and DDC channels provided through multiplexed interface Hotplug and display
support
• Dual independent pipe with single display support Simultaneous: Same images and native display timings
13
on each display device
• Dedicated LFP (local flat panel) interface
Single l LVDS panel support up to SXGA+ panel resolution with frequency range from 25MHz to
112MHz per channel
Supports data format of 24 bpp
LCD panel power sequencing compliant with SPWG timing specification
Compliant with ANSI/TIA/EIA –644-1995 spec
Integrated PWM interface for LCD backlight inverter control
Bi-linear Panel fitting
• Tri-view support through LFP interface, TV ports and CRT
• Internal Graphics Features
• Core Frequency
Display Core frequency of 133MHz,200MHz,250MHz
Render Core frequency of 100 MHz, 133 MHz, 166 MHz, 200 MHz, 250 MHz
Intel® Dual-Frequency Graphics Technology
• 2D Graphics Engine
• Optimized 128 bit BLT engine
• Ten programmable and predefined monochrome patterns
14
• Alpha Stretch Blt (via 3D pipeline)
• Anti-aliased lines
• Hardware-based BLT Clipping & Scissoring
• 32-bit Alpha Blended cursor
• Programmable 64*64 3-color Transparent cursor
• Color Space Conversion
• 3 Operand Raster BLTs
• 8-bit, 16-bit, and 32-bit color
• ROP support
• DIB translation and Linear/Title addressing
• 3D Graphics Engine
• 3D Setup and Render Engine
• Viewpoint Transform and Perspective Divide
• Triangle Lists, Strips and Fans support
• Indexed Vertex and Flexible Vertex formats
• Pixel accurate Fast Scissoring and Clipping operation
• Backface Culling support
15
• DirectXTM and OGL Pixelization rules
• Enhanced Hardware Binning Instruction Set supported
• Bi-Cubic Filtering supported
• Linear Gamma Blending for Video Mixer Rendering (VMR)
• Video Mixer Rendering (VMR) supported
• Anti-Aliased Lines support
• Sprite Points support
• Zone Rendering
• Provides the highest sustained fill rate performance in 32-bit color and 24-bit W mode
• High quality performance Texture Engine
• 266 Mega Texel/speak performance
• Per Pixel Perspective corrected Texture Mapping
• Single Pass Texture Compositing (Multi-Texture) at rate
• Enhanced Texture Blending functions
• Twelve Level of Detail MIP Map Sizes from 1x1 to 2Kx2K
• Numerous Texture formats including 32-bit RGBA
• Alpha and Luminance Maps
16
• Texture Chromakeying
• Bilinear, Trilinear, Anisotropic MIP-Mapped Filtering
• Cubic Environment Reflection Mapping
• Embossed Bump-mapping
• DXTn Texture Decompression
• 3D Graphics Rasterrization enhancements
• One Pixel per Clock
• Flat and Gouraud Shading
• Color Alpha Blending for Transparency
• Vertex and Programmable Pixel Fog and Atmospheric effects
• Color Specular Lighting
• Vertex and Programmable Pixel Fog and Atmospheric effects
• Z Bais support
• Dithering
• Line and Full-Scence Anti-Aliasing
• 16 and 24-bit Z Buffering
• 16 and 24-bit W Buffering
17
• 8-bit Stencil Buffering
• Double and Triple Render Buffer support
• 16 and 32 –bit color
• Destination Alpha
• Vertex Cahec
• Maximum 3D resolution of 1600x1200 x32 bpp at 85 Hz
• Optimal 3D resolution supported
• Fast Clear support
• ROP support
HUB Interface for ICH4
• 533 MB/s point to point hub interface to ICH4-M
• 66-M Hz base clock
• Supports the following traffic types to the ICH4-M
• Hub interface-to DRAM
• CPU-to-Hub interface
• Messaging
18
• MSI interrupt messages
• Power Management state change
• SMI, SCI, and SERR error indication
• Power Management
SMRAM space remapping to A0000h (128-KB)
Supports extended SMRAM space above 256- MB ,additional 1 MB TSEG from top of Memory,
cacheable (cacheability controlled by CPU)
APM rev 1.2 compliant power management
Supports Suspend to System Memory(S3),Suspend to Disk(S4) and Hard Off/Total Reboot(S5)
ACPI 1.0b,2.0 Support
1.1.2.4 I/O Controller Hub : Intel 82801DBM
The Intel 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller
with AC 97 Interface, the IDE Master/Slave controllers, and Intel® I/O Hub architecture. The PCI to LPC
Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management
functionalities are integrated as well.
The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host
controllers with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB
devices as well as over current detection are also implemented.
19
The Integrated AC ’ 97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and
HSP v.90 modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable
of supporting multiple audio codecs with one separate modem codec.
The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode
transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE
channels that sustain the high data transfer rate in the multitasking environment.
Intel 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates
the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three
8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse
interface(not use in Prestigio Nobile 150 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59
compatible Interrupt controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB
interrupt delivery modes is supported.
The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the Intel 82801DBM ICH4-M supports Deeper Sleep power state for Intel
Mobile processor.
A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel
82801DBM ICH4-M Hub interface together. Intel® I/O Hub architecture is developed.
20
Features :
PCI Bus Interface
Supports PCI Revision 2.2 Specification at 33 MHz
133 MB/sec maximum throughput
Supports up to six master devices on PCI
One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller)
Support for 44-bit addressing on PCI using DAC protocol Integrated LAN Controller
WFM 2.0 and IEEE 802.3 compliant
LAN Connect Interface (LCI)
10/100 Mbit/sec Ethernet support Integrated IDE Controller
Supports “Native Mode” register and interrupts
Independent timing of up to 4 drives, with separate primary and secondary IDE cable connections
Ultra ATA/100/66/33, BMIDE and PIO modes
Tri-state modes to enable swap bay
USB
Includes three UHCI host controllers that support six external ports
New: Includes one EHCI high-speed USB 2.0 Host Controller that supports all six ports
21
New: Supports a USB 2.0 high-speed debug port
Supports wake-up from sleeping states S1–S5
Supports legacy keyboard/mouse software AC-Link for Audio and Telephony CODECs
Supports AC ’97 2.3
New: Third AC_SDATA_IN line for three codec support
New: Independent bus master logic for seven channels (PCM In/Out, Mic 1 input, Mic 2 input, modem
in/out, S/PDIF out)
Separate independent PCI functions for audio and modem
Support for up to six channels of PCM audio output (full AC3 decode)
Supports wake-up events Interrupt Controller
Support up to eight PCI interrupt pins
Supports PCI 2.2 message signaled interrupts
Two cascaded 82C59 with 15 interrupts
Integrated I/O APIC capability with 24 interrupts
Supports serial interrupt protocol
Supports processor system bus interrupt delivery New: 1.5 V operation with 3.3 V I/O
5 V tolerant buffers on IDE, PCI, USB over current and legacy signals Timers Based on 82C54
22
System timer, refresh request, speaker tone output Power Management Logic
ACPI 2.0 compliant
ACPI-defined power states (C1–C2, S3–S5 )
Supports Desktop S1 state (like C2 state, only STPCLK# active)
ACPI power management timer
PCI PME# support
SMI# generation
All registers readable/restorable for proper resume from 0V suspend states External Glue Integration
Integrated pull-up, pull-down and series termination resistors on IDE, processor interface
Integrated Pull-down and Series resistors on USB Enhanced Hub Interface Buffers Improve Routing
flexibility (Not available with all Memory Controller Hubs)
1.1.2.5 TV Encoder : CH7011A
The CH7011 is a Display controller device which accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide
variable voltage data port which supports five different data formats including RGB and YCrCb.The TV-Out
processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data
into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to
23
enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and
horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create
outstanding video quality. Support is provided for Macrovision™ and RGB bypass mode which enables driving
a VGA CRT with the input data.
Features :
Macrovision™ 7.X copy protection support
TV output supporting up to 1024x768 graphics resolutions
Programmable digital interface supports RGB and YCrCb
True scale rendering engine supports underscan in all TV output resolutions
Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering
Support for all NTSC and PAL formats
Provides CVBS, S-Video and SCART (RGB) outputs
TV connection detect
Programmable power management
10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
24
Low voltage interface support to graphics device
1.1.2.6 KBC Controller_Winbond W83L950D
The Turbo-51 core logic of Winbond Keyboard controller is based on the industry standard 8032 device. It is
built around an 8-bit ALU that uses internal registers for temporary storage and control of the peripheral
devices. It can execute the standard 8032 instruction set.
The Winbond Keyboard controller separates the memory into two sections, the Program Memory and the Data
Memory. The Program Memory, MTP-ROM, is used to store the instruction op-codes, and the Data Memory,
RAM, is used to store data and now is consists of a 256 bytes scratch pad RAM and a 2K bytes external SRAM.
The external SRAM can be accessed by either MOVX instruction in generally or to be a scratched ultra ROM
for special purpose.
The brief descriptions of the internal blocks are shown as follows.
Features :
Pin Out
• Pin–to-Pin compatible with Mitsubishi M3886 family (ISA mode)
25
Core Logic
• Turbo 8052 microprocessor based
• 256 bytes internal RAM
• 40K bytes embedded programmable flash memory
• 2K bytes external SRAM
• Host interface
• Software optional with ISA or LPC interface
• Primary programmable I/O address communication port in LPC mode
• Support either Parallel IRQ in ISA or SERIRQ in LPC interface
• Hardware Fast Gate A20 and KBRST support
• Port 92h support
SMBus
• Support 2 SMBus interface for master and slave
Timers
• Support 4 Timer signal with 3 pre-scalars
26
• Timer 1 and 2 shard the same pre-scalar and are free-running only
• Timer X and Y have individual pre-scalar and support up to 4 control modes, free running, pulse output,
event counter and pulse width measurement
PWM
• Support 4 PWM channels
ADC
• Support 2 DA output and 8 AD input
• DA 0, 1 are 8bits resolution
• AD 0-7 are firmware programmable optional with 10 or 8 bits resolution
PS2
• Support 3 hardware PS2 channels
• Optional PS2 clock inhibit by hardware or firmware
27
GPIO
• Support 72 GPIO pins totally, and all are bit–addressable to facility firmware coding
FLASH
• Support External On-Board Flash via Matrix interface (GP0, 1, 3)
ACPI
• Support ACPI appliance
• Secondary programmable I/O address communication port in LPC mode
1.1.2.7 Fast Ethernet Controller VT6105LOM
The VIA Rhine III VT6105LOM is a 10/100Mbps Fast Ethernet controller designed to provide system designers
an easy to integrate single chip solution, with advanced management and power conservation features. Featuring
a 3-in-1 design the VIA VT6105LOM integrates the physical, media, and management layers into a single chip.
Features :
Single chip full/half duplex 10/100Mbps Fast Ethernet Management Controller
28
IEEE 802.3/802.3u 10BASE-T and 100BASE-T Compatible
32bit PCI Bus-Master Interface
VIA Rhine based CSR definition provides efficiency PCI bus-mastering
Low power 100base-TX transceiver embedded Support 10Mbps and 100Mbps N-way Auto-negotiation
operation Support Auto-MDIX function
Enhancement MAC functions for 802.3 networking 802.1 Priority Transmit Maximum eight priority queues
by drivers programmable 802.1q Multiple VLAN support VLAN long frames support (1518+4bytes) VLAN
tag auto inserting and extracting on TX and RX side (VT6105LOM) NIC auto filtering on VLAN ID optional
(VT6105LOM)
IP header Checksum Offload supporting for Ipv4 frames. Support both of TCP and UDP protocol
(VT6105LOM)
Support Physical, Broadcast, and Multicast addresses filtering using both hashing table look-up and perfectmatchmechanisms (VT6105LOM)
12 sets hardware 16 bit MIB counters (VT6105LOM)
Fiber Optic network support (VT6105LOM)
WFM 2.0 (VT6105LOM)
DMI 2.0 (H/W)
IO 3.3v with PCI bus 5V tolerant / Core 2.5v power, using low power 0.22um TSMC CMOS process, 128pin
PQFP package.
29
1.1.2.8 FAX/MODEM Module_MDC56S-1
Made by Billionton Computer corporation
Integrated PCI v2.2 Interface
Host-based ITU V.70 DSVD.
Operation support: Windows 95/NT/ME/2000
K56flex for internet connection rates approaching 56kbits/s.
Data Modes capabilities
• Support 2 DA output and 8 AD input
• DA 0, 1 are 8bits resolution
• AD 0-7 are firmware programmable optional with 10 or 8 bits resolution.
FAX mode capabilities:
• ITU-T V.17, V.29, V.27ter, and V.21 CH 2
• TIA/EIA 578 Class 1 FAX
V.80 Host Controlled Communication Protocol Standards
• H.324 Interface Support
On Chip PnP Logic
ACPI support “On Now”
30
Support “Call ID”
PC 97 Compliant – Unimodem/V Compliant
Low Power Consumption
Operation Voltage 3.3V
1.1.2.9 PCMCIA Controller_ TI PCI1410A + TI TPS2211A
PCI1410A
The TIE PCI1410A device is a high-performance PCI-to-PC Card controller that supports a single PC Card
socket compliant with the PC Card Standard. The PCI1410A device provides features that make it the best
choice for bridging between PCI and PC Cards in both notebook and desktop computers. The PC Card
Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new
32-bit PC Card, CardBus, as being capable of full 32-bit data transfers at 33 MHz. The PCI1410A device
supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.
The PCI1410A device is compliant with the PCI Local Bus Specification, and its PCI interface can act as
either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card
DMA transfers or CardBus PC Card bridging transactions. The PCI1410A device also is compliant with the
latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface
Specification for PCI to CardBus Bridges.
31
All card signals are buffered internally to allow hot insertion and removal without external buffering. The
PCI1410A device is register-compatible with the IntelE 82365SL-DF and 82365SL ExCA controllers. The
PCI1410A internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI
cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed
performance level with sustained bursting. The PCI1410A device also can be programmed to accept fastposted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA,
and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to
implement sideband functions. Many other features designed into the PCI1410A device, such as socketactivity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power
consumption, while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host
power management system to further reduce power consumption.
Features :
Ability to wake from D3hot and D3cold
Full compatibility with the Intel 430TX (Mobile Triton II) chipset
A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGAE ball grid array (GGU) package, or
209-terminal MicroStar BGAE (GHK) package
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
32
Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
Single PC Card or CardBus slot with hot insertion and removal
Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI
interrupts, and serial ISA IRQ and PCI interrupts
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
Pipelined architecture allows greater than 130 Mbit/s sustained throughput from CardBus to PCI and from
PCI to CardBus
Interface to parallel single-slot PC Card power-switch interfaces like the TIE TPS2211 device
Up to five general-purpose I/Os
Programmable output select for CLKRUN
Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
Two I/O windows and two memory windows available to the CardBus socket
Exchangeable card architecture (ExCA) compatible registers are mapped in memory and I/O space
Compatibility with Intel 82365SL-DF and 82365SL registers
Distributed DMA (DDMA) and PC/PCI DMA
16-bit DMA on the PC Card socket
Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN
33
Socket-activity LED pins
PCI bus lock (LOCK)
Advanced submicron, low-power CMOS technology
Internal ring oscillator
1.1.2.10 TPS2211A(Power Switch)
The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a
single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection
for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOS
process. The circuit allows the distribution of 3.3-V, and/or 5-V card power, and is compatible with many
PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component
count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card.
The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V.
Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such
as sleep mode and pager mode where only 3.3 V is available.
End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants
(PDAs), digital cameras, and bar-code scanners.
34
Features :
Fully Integrated VCC and Vpp Switching for Single-Slot PC Card. Interface
Low rDS(on) (90-mΩ 5-V VCC Switch and 3.3-V VCC Switch)
Compatible With Controllers From Cirrus, Ricoh, O2Micro, Intel, and Texas Instruments
3.3-V Low-Voltage Mode
Meets PC Card Standards
Short-Circuit and Thermal Protection
Space-Saving 16-Pin SSOP (DB)
Compatible with 3.3-V, and 5-V PC Cards
Break-Before-Make Switching
1.1.2.11 AC'97 Codec _ Realtek ALC101
The ALC101 is an 18-bit, full duplex AC'97 2.2 compatible stereo audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC101 AC'97 CODEC supports
multiple CODEC extensions with independent variable sampling rates and built-in 3D effects. The ALC101
CODEC provides a pair of stereo outputs with independent volume controls and multiple stereo and mono
inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for
PCs. The digital interface circuitry of the ALC101 CODEC operates from a 5V/3.3V power supply with EAPD
35
(External Amplifier Power Down) control for use in notebook and PC applications. The ALC101 integrates a
50mW/20ohm headset audio amplifier into the CODEC, saving BOM costs. The ALC101 CODEC supports
host/soft audio from Intel 810/815/820/845 chipsets as well as audio controller based VIA/SIS/ALI chipsets.
Bundled Windows series drivers (Win95/98/ME/2000/XP/NT) and sound effect utilities (supporting Karaoke,
26-kind of environment sound emulation, 5-band equalizer) provide an excellent entertainment package for PC
users. Finally, internal PLL circuits generate required timing signals, eliminating the need for external clocking
devices.
Features :
Single chip audio CODEC with high S/N ratio
Compliant with AC’97 2.2 specification
16-bit stereo full-duplex CODEC with fixed 48KHz sampling rate
3 analog line-level stereo inputs with 5-bit volume control: LINE-IN, CD-IN, AUX-IN
1 analog line-level mono input: PHONE-IN
1 MIC input
Power management
3D Stereo Enhancement
LINE output with 50mW/20Ω headphone driver
External amplifier power down capability
36
Power supply: Digital: 3.3V Analog: 5V/3.3V
Clocking by external 14.318MHz or 24.576MHz source to save crystal
Standard 48-pin LQFP Package
1.1.2.12 Thermal Sensor_ ADM1021A
The ADT7460 dBCOOLTM controller is a systems monitor and multiple PWM fan controller for noisesensitive applications requiring active system cooling. It can monitor the temperature of up to 2 remote sensor
diodes, plus its own internal temperature. It can measure and control the speed of up to 4 fans so that they
operate at the lowest possible speed for minimum acoustic noise. The Automatic Fan Speed Control Loop
optimizes fan speed for a given temperature. A unique Dynamic TMIN Control Mode enables the system
thermals/acoustics to be intelligently managed. The effectiveness of the System's Thermal Solution can be
monitored using the THERM input. The ADT7460 also provides critical Thermal Protection to the system
using the bidirectional THERM pin as an output to prevent system or component overheating.
1.1.2.13 System Flash Memory (BIOS)
4M bit Flash memory
Flashed by 5V only
User can upgrade the system BIOS in the future just running flash program
See Software BIOS Specification
37
1.2 Other Functions
1.2.1 Hot Key Function
Keys
Combination
Feature
Meaning
Fn + F1
Reserve
Fn + F2
Reserve
Fn + F3
Volume Down
Fn + F4
Volume Up
Fn + F5
LCD/External CRT
Switching
Rotate display mode in LCD only, CRT only and simultaneously
display.
Fn + F6
Brightness Down
Decreases the LCD brightness
Fn + F7
Brightness Up
Increases the LCD brightness
Fn + F8
Reserve
Fn + F9
Reserve
Fn + F10
Battery beep enable/disable
Battery low beep sound enable/disable
Fn + F11
Panel Off/On
Toggle panel Off/On
Fn + F12
Suspend to DRAM/HDD
Force the computer into either Suspend to HDD or Suspend to
RAM mode.
38
1.2.2 Power On/Off/Suspend/Resume Button
1.2.2.1 APM Mode
At APM mode, power button is on/off system power.
1.2.2.2 ACPI Mode
At ACPI mode, power button behavior was set by windows power management control panel.
You could set “standby” , “power off” or “hibernate”(must enable hibernate function in power management) to
power button function. Continue pushing power button over 4 seconds will force system off at ACPI mode.
1.2.3 Cover Switch
System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong
the usage time when user closes the notebook cover.
At ACPI mode there are four functions to be chosen at windows power management control panel.
1. None
2. Standby
3. Off
39
4. Hibernate (must enable hibernate function in power management)
1.2.4 LED Indicators
System has eight status LED indicators to display system activity, which include three at front side and five above
keyboard.
Three LED indicators on LCD panel:
From left to right that indicate: RF, POWER and BATTERY STATUS.
1.2.5 Fan Power On/Off Management
FAN is controlled by W83L950D embedded controller using ADT7460 to sense CPU temperature and PWM
control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster fan speed.
1.2.6 CMOS Battery
CR2032 3V 220mAh lithium battery.
When AC in or system main battery inside, CMOS battery will consume no power. AC or main battery not exist,
CMOS battery life at less (220mAh/5.8uA) 4 years. Battery was put in battery holder, can be replaced.
40
1.2.7 I/O Port
One Power Supply Jack
One External CRT Connector For CRT Display
One S-Video TV Output Connector
Supports four USB2.0 port for all USB devices
One MODEM RJ-11 phone jack for PSTN line
One RJ-45 for LAN
Microphone Input Jack
One CardBus Sockets for one type II PC card extension
41
1.3 Peripheral Components
1.3.1 LCD Panel
1st Source: Hydis 15” TFT: HT15X34-100
2nd Source: AU 15” TFT : B150XG02
Please reference the spec for detail.
1.3.2 Ext. Floppy Disk Drive
External USB 3.5” 1.44MB /1.2 MB/720KB FDD (Option)
1st Source :Mitsumi D353FUE
1.3.3 HDD
Fujitsu 30GB: MHT2030AT / 40GB: MHT2040AT/ 60GB : MHT2060AT
HGST 30GB: IC25N030ATMR04-0 /40GB: IC25N040ATMR04-0 /60GB: IC25N060ATMR04-0
/80GB: IC25N080ATMR04-0
42
1.3.4 CD ROM Drive
1st source : TEAC CD-224E-C93 (24X)
1.3.5 DVD ROM Drive
1st source : MKE :SR-8177-B ( 8X DVD-ROM/24X CD-ROM)
1.3.6 COMBO Drive
1st source : Liteon: LSC-24082K ( 24 X 24 X 8 X 24 ) (Read:8X DVD-ROM/24X CD-ROM ; Write :24X
CD-R/24X CD-RW)
2nd source : QSI: SBW-242 (24X10X8X24) (Read:8X DVD-ROM/24X CD-ROM ; Write :24X CD-R/10X
CD-RW)
3rd source : KME: UJDA750MT ( 24 X 24 X 8 X 24 ) (Read:8X DVD-ROM/24X CD-ROM ; Write :24X
CD-R/24X CD-RW)
1.3.7 Super COMBO Drive
1st source : MKE UJ810B ( Read : 8X DVD-ROM/24X CD-ROM ; Write 16X CD-R / 4X CD-RW / 8X
High Speed CD-RW / 2X DVD-R /1X DVD-RW / 2X DVD-RAM)
43
2nd source : QSI SDW-041 (DVD+RW)
3rd source: Liteon: SDW-421S
4th source: HLDS GWA-4040N (8X DVD-ROM / 24X CD-ROM)
1.3.8 Keyboard
TJME 19mm pitch/3.0mm stroke
1.3.9 Track Pad : Synaptics TM41PUM311-2
Accurate positioning
Low fatigue pointing action
Low profile
No moving part, high reliability
Low power consumption
Environmentally sealed
Compact size
Software configurable
44
Low weight
Operating temperature: 0 to 60 degree C
Operating humidity : 5%-95% relative humidity, non condensing
Storage temperature: -40 to +65 degree C
ESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01
Power supply voltage : 5.0Voltage ± 10%
Power supply current : 4.0mA max operating
1.3.10 Fan
HY45J05-001
45
1.4 Power Management
The Prestigio Nobile 150 system has built in several power saving modes to prolong the battery usage for mobile purpose.
User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by
pressing F2 key). Following are the descriptions of the power management modes supported.
1.4.1 System Management Mode
1.4.1.1 Full On Mode
In this mode, each devices is running with the maximal speed. CPU clock is up to its maximum.
1.4.1.2 Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This
can save battery power without loosing much computing capability.
The CPU power consumption and temperature is lower in this mode.
46
1.4.1.3 Standby Mode
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device:
• CPU: Stop grant
• LCD: Backlight off
• HDD: Spin down
1.4.1.4 Suspend to DRAM and HDD
The most chipset of the system is entering power down mode for more power saving. In this mode, the following is
the status of each device:
Suspend to DRAM
• CPU: off
• NB: Partial off
• VGA: Suspend
• PCMCIA: Suspend
• Audio: off
• SDRAM: Self Refresh
47
Suspend to HDD
• All devices are stopped clock and power-down
• System status is saved in HDD
• All system status will be restored when powered on again
1.4.2 Other Power Management Functions
HDD & Video Access
System has the ability to monitor video and hard disk activity. User can enable monitoring video and/or hard
disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending
on the application. When the VGA activity monitoring is enabled, the performance of the system will have some
impact.
48
1.5 Appendix 1: Intel 82801DBM ICH4-M GPIO Definitions
Pin Name
MUX Function
GPIO Function
Power Plane
Pin Name
GPIO0
CRT_IN#
GPI
MAIN
GPIO23
GPIO1
X
GPI
MAIN
GPIO2
INT_PIRQE#
GPI
GPIO3
INT_PIRQF#
GPIO4
MUX Function
GPIO Function
Power Plane
X
O
MAIN
GPIO24
PCLKRUN#
GPIO
RESUME
MAIN
GPIO25
X
GPIO
RESUME
GPI
MAIN
GPIO27
X
GPIO
RESUME
INT_PIRQG#
GPI
MAIN
GPIO28
X
GPIO
RESUME
GPIO5
X
GPI
MAIN
GPIO32
WIRELESS_PD#
GPIO
MAIN
GPIO6
AGP_BUSY#
GPI
MAIN
GPIO33
LCDID0
GPIO
MAIN
GPIO7
KB_US/JP#
GPI
MAIN
GPIO34
LCDID1
GPIO
MAIN
GPIO8
EXTSMI#
GPI
RESUME
GPIO35
LCDID2
GPIO
MAIN
GPIO11
SMBALERT#
GPI
RESUME
GPIO36
SIDE_IN#
GPIO
MAIN
GPIO12
SCI#
GPI
RESUME
GPIO37
ICH_SIDE_IN#
GPIO
MAIN
GPIO13
WAKE_UP#
GPI
RESUME
GPIO38
IDERST#
GPIO
MAIN
GPIO16
SIDE_OFF#
GPO
MAIN
GPIO39
MINIPCI_ACT#
GPIO
MAIN
GPIO17
PIDE_OFF#
GPO
MAIN
GPIO40
DEBIG_EN
GPIO
MAIN
GPIO18
STOP_PCI
GPO
MAIN
GPIO41
SIDEDET
GPIO
MAIN
GPIO19
SUSA#
GPO
MAIN
GPIO42
SPK_OFF
GPIO
MAIN
GPIO20
STOP_CPU
GPO
MAIN
GPIO43
SIDERST#
GPIO
MAIN
GPIO21
X
GPO
MAIN
GPIO22
CPUPERF#
OD
MAIN
49
1.6 Appendix 2: Prestigio Nobile 150 Product Specification
Model
System A
System B
Core logic
Intel 855GME + ICH4M
Intel 855GME + ICH4M
CPU
Intel Pentium M 1.3G
Intel Pentium M 1.6G
14” XGA
Hydis :HT14X19-100
HGST 40GB
IC25N040ATMR04-0
15” XGA
Samsung: LTN150XB-L03
RAM Module
DDR 333 MHz 256MB DDR
memory Module
Apacer 77.10634.110 (Infineon
32x8)
DDR 333 MHz 512MB DDR memory
Module
Twinmos
M2S5J08D1AMC5F1611A-T,TWINMOS
Modem
Billionton :MDC56S-I
Billionton :MDC56S-I
Display
HDD
Fujitsu 40GB
Video Controller Intel 855 GME Int.
MHT2040AT
Intel 855 GME Int.
Audio
Audio Power Amplifier: TI
/TPA0212
AC 97 CODEC: Realtek ALC101
Audio Power Amplifier: TI /TPA0212
AC 97 CODEC: Realtek ALC101
Wireless lan
Intel Pro/Wireless 2100
Intel Pro/Wireless 2100
PCMCIA
TI PCI1410A / Power Switch : TI TI PCI1410A / Power Switch : TI
TPS2211A
TPS2211A
Keyboard
Controller
Winbond W83L950D
Winbond W83L950D
LAN Controller VIA VT6105LOM
VIA VT6105LOM
AC Adapter
60W(Delta)
60W(Delta)
Battery
6 cell 2000mAH (Panasonic)
9 cell 2000mAH (Panasonic)
50
2. System Assembly & Disassembly
2.1 System View
2.1.1 Front View
External Microphone Input
External Audio output
Top Cover Latch
2.1.2 Left-Side View
VGA Port
Ventilation Openings
USB Ports *4
Phone Line Input
LAN Connector
PC Card Slot
51
2.1.3 Right-Side View
CD-ROM/DVD-ROM Drive
2.1.4 Rear View
Lock hole
Battery Pack
Power Connector
S-Video Port
52
2.1.5 Bottom View
Hard Disk Drive Cover
DDR-SDRAM Cover
CPU Cover
Battery Pack
Mini PCI Cover
2.1.6 Top-Open View
Power Button
Keyboard
Internal Microphone
Device LED Indicators
Touch Pad
Battery Power Indicator
Battery Charge Indicator
AC Power Indicator
LCD Screen
Stereo Speaker
53
2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations. Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.2.1 Battery Pack
2.2.2 Keyboard
2.2.3 CPU
Modular Components
2.2.4 HDD Module
2.2.5 CD/DVD-ROM Drive
2.2.6 DDR-SDRAM
2.2.7 Wireless Card
NOTEBOOK
2.2.8 LCD Assembly
LCD Assembly Components
2.2.9 LCD Panel
2.2.10 Inverter Board
2.2.11 System Board
Base Unit Components
2.2.12 Touchpad
54
2.2.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.
2. Pull the battery pack out of the compartment () while sliding and holding the release lever outwards to the
“unlock” ( ) position (). (Figure 2-1)
Figure 2-1 Remove the battery pack
Reassembly
1. Push the battery pack into the compartment. The battery pack should be correctly connected when you hear a
click-ing sound.
2. Slide the release lever to the “lock” ( ) position.
55
2.2.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 disassembly)
2. You can push the keyboard cover to loose the locks from the battery compartment. (Figure 2-2)
Figure 2-2 Push the keyboard cover
Figure 2-3 Remove the keyboard cover
3. Lift the keyboard cover up. (Figure 2-3)
56
4. Slightly lift up the keyboard. (Figure 2-4)
Figure 2-4 lift up the keyboard
Figure 2-5 Disconnect the cable
5. Then disconnect the cable from system board to detach the keyboard. (Figure 2-5)
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Fit the keyboard cover.
3. Replace the battery pack. (Refer to section 2.2.1 reassembly)
57
2.2.3 CPU
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (Refer to section 2.2.1 disassembly)
2. Remove three screws fastening the CPU compartment cover. (Figure 2-6)
Figure 2-6 Remove the CPU compartment
cover
Figure 2-7 Remove the heatsink
3. Remove four spring screws that secure the heatsink and disconnect the fan’s power cord to detach the heatsink
from the CPU compartment. (Figure 2-7)
58
4. Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-8)
Figure 2-8 Remove the CPU socket
Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into
the holes. Tighten the screw by a flat screwdriver to locking the CPU.
2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with four
spring screws.
3. Replace the heatsink compartment cover and secure with three screws.
59
2.2.4 HDD Module
Disassembly
2. Remove two screws fastening the HDD compartment cover, and lift the cover up. (Figure 2-9)
Figure 2-9 Remove the HDD cover
Figure 2-10 Remove the HDD drive
3. Slide the hard disk drive leftwards to unplug the drive. (Figure 2-10)
60
4. Loosen the four screws to separate the hard disk drive from the bracket. (Figure 2-11)
Figure 2-11 Free the HDD drive
Reassembly
1. To install the hard disk drive, place it in the bracket and secure with four screws.
2. Put the hard disk drive in the compartment and slide it inwards to plug and secure with one screw.
3. Replace the HDD compartment cover and secure with two screws.
61
2.2.5 CD/DVD-ROM Drive
Disassembly
2. Loosen the one screw that secure the CD/DVD-ROM drive. (Figure 2-12)
Figure 2-12 Remove the CD/DVD-ROM
3. Put the notebook back to the upright position. Then insert a small rod, such as a straightened paper clip, into the
drive’s manual eject hole and push firmly to release the tray (). Pull the tray out until fully extended (), then
carefully pull harder to remove the CD/DVD-ROM drive. (Figure 2-12)
Reassembly
1. To replace the CD/DVD-ROM drive, slide and push it all the way into the compartment to plug.
2. Secure the CD/DVD-ROM drive with one screw.
62
2.2.6 DDR-SDRAM
Disassembly
2. Loosen one screw that secure the DDR compartment cover. (Figure 2-13)
Figure 2-13 Remove the cover
Figure 2-14 Remove the DDR-SDRAM
3. Pull the retaining clips outwards () and remove the DDR-SDRAM (). (Figure 2-14)
Reassembly
1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the DDR into
the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position.
2. Tighten one screws to secure the DDR compartment cover to housing.
63
2.2.7 Wireless Card
Disassembly
2. Loosen the two screws that secure the wireless card cover to the housing. (Figure 2-15)
Figure 2-15 Remove the Wireless card
compartment cover
Figure 2-16 Remove the wireless card
3. Disconnect the wireless card’s antennae first (). Then pull the retaining clips outwards () and remove the
wireless card (). (Figure 2-16)
Reassembly
1. To install the wireless card, match the wireless card 's notched part with the socket's projected part and firmly
insert it into the socket. Then push down until the retaining clips lock the wireless card into position. Then sure
that the antennae fully populated.
2. Tighten the screws to secure the wireless card compartment cover to the housing.
3. Replace the battery pack. (See section 2.2.1 reassembly)
64
2.2.8 LCD Assembly
Disassembly
2. Remove the keyboard cover. (Refer to steps 1—3 of section 2.2.2 disassembly)
3. Remove the heatsink. (Refer to steps 1—3 of section 2.2.3 disassembly)
4. Disconnect the wireless card’s antennae. (Refer to section 2.2.7 disassembly)
5. Open the top cover to level plane. Then remove the two hinge covers. And disconnect the two LCD cables from the
system board. (Figure 2-17)
Figure 2-17 Remove two hinge covers and
Figure 2-18 Loosen the screws and
disconnect two cables
disconnect the cable
6. Remove the four screws of the hinges. Then disconnect the speaker’s cord and touch pad cable. (Figure 2-18)
65
7. Put the notebook upside down. Remove twenty- two screws that secure the housing. Then lift the housing from the
rack. (Figure 2-19)
Figure 2-19 Remove the housing
Figure 2-20 Remove the screws
8. Remove two screws in the rear of the notebook. (Figure 2-20)
66
9. To remove the modem card, loosen the screws and disconnect the cable. (Figure 2-21)
Figure 2-22 Remove the system board
10. Remove the three screws and two hex nuts that secure the system board. And disconnect one cord. (Figure 2-22)
67
11. Free the wireless card’s antennae wires. Separate the LCD ASSY away. (Figure 2-23)
Figure 2-23 Separate the LCD ASSY
Reassembly
1. Fit the LCD assembly and sure the wireless card’s antennae wires no overlaid by top cover
2. Attach the system board and tighten the screws and hex nuts to secure the system board in the top cover. Then
reconnect the cord
3. Fit the modem card and secure it with two screws. Then Reconnect the cable.
4. Replace the housing. Tighten all of screws to secure the housing.
5. Secure the LCD assembly with four screws of the hinges.
6. Reconnect the LCD cables、speaker cord and touch pad cable.
7. Replace two hinge covers.
8. Replace the heatsink 、keyboard cover and battery pack. (Refer to sections 2.2.1、 2.2.2 and 2.2.3 reassembly)
68
2.2.9 LCD Panel
Disassembly
5. Remove the LCD assembly. (See section 2.2.8 Disassembly.)
6. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-24)
Figure 2-24 Remove LCD frame
Figure 2-25 Remove LCD panel
7. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until the
cover is completely separated from the housing.
8. Remove the six screws on two sides of LCD panel, and disconnect the cable from the inverter board. (Figure 2-25)
69
9. Remove the four screws to remove the LCD bracket on side of the LCD panel. (Figure 2-26)
Figure 2-26 Remove the LCD bracket
Figure 2-27 Remove the LCD wire
10. Disconnect the wire from bottom of the LCD panel. (Figure 2-27)
Reassembly
1. Reconnect the wire to the LCD panel.
2. Attach the LCD bracket on the LCD panel and secure with four screws.
3. Fit the LCD panel back into place and secure with six screws, and reconnect the cable to the inverter board.
4. Fit the LCD cover back into the LCD housing. Tighten two screws to secure the LCD cover attach the rubber pads.
5. Replace the LCD assembly and battery pack. (See section 2.2.1and 2.2.7 reassembly.)
70
2.2.10 Inverter Board
Disassembly
5. Remove the LCD assembly. (See section 2.2.8 Disassembly.)
6. Remove the LCD cover. (Refer to steps 6-7 of section 2.2.9 disassembly. )
7. Remove two screws and disconnect the cables from the inverter board. (Figure 2-28)
Figure 2-28 Remove the Inverter Board
71
Reassembly
1. Replace the inverter board and secure it with two screws.
2. Reconnect the inverter board cables.
3. Fit the LCD cover back into the LCD housing. Tighten two screws to secure the LCD cover attach the rubber pads.
4. Replace the LCD assembly and battery pack. (See section 2.2.1and 2.2.7 reassembly.)
72
2.2.11 System Board
Disassembly
5. Open the top cover to level plane. Then remove the two hinge covers. And disconnect the two LCD cables from the
system board. (Figure 2-29)
Figure 2-29 Remove two hinge covers and
disconnect two cables
Figure 2-30 Loosen the screws and
disconnect the cable
6. Remove the four screws of the hinges. Then disconnect the speaker’s cord and touch pad cable. (Figure 2-30)
73
7. Put the notebook upside down. Remove twenty- two screws that secure the housing. Then lift the housing from
the rack. (Figure 2-31)
Figure 2-31 Remove the housing
8. Remove two screws in the rear of the notebook. (Figure 2-32)
74
9. To remove the modem card, loosen the two screws and disconnect the cable. (Figure 2-33)
Figure 2-33 Remove the screws and hex nuts
Figure 2-34 Remove the system board
10. Remove the three screws and two hex nuts that secure the system board. And disconnect one cord. Now you can
lift up the system board. (Figure 2-34)
75
Reassembly
1. Fit the system board and secure with three screws and two hex nuts.
2. Fit the modem and secure with two screws and reconnect the wire.
3. Replace the housing and secure with twenty-two screws.
4. Upturn the notebook. Take ulterior step to fasten the housing by two screws on the rear of the notebook.
5. Reconnect the touch pad’s cable and speaker’s cord.
6. Replace the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly. (See the
reassembly parts in previous sections.)
76
2.2.12 Touch pad
Disassembly
1. Remove the system board. (See section 2.2.10disassembly)
2. Remove the two screws to lift up the touchpad button. (Figure 2-35)
Figure 2-35 Remove the touch pad button
Figure 2-36 Remove the touchpad shield
3. To tack the touchpad out, remove the thirteen screws that secure the touchpad shielding. (Figure 2-36)
Reassembly
1. Replace the touchpad and fit the touchpad shielding upon it and secure with thirteen screws.
2. Replace the touch pad button and secure with two screws.
3. Assemble the notebook. (See the reassembly parts in previous sections.)
77
3. Definition & Location of Connectors / Switches
3.1 Mother Board-A
J501 : S-TV Output Connector
J514
J502 : VGA Connector
J510
J503 : Internal Right Speaker Connector
J503
J504
J504 : Mini PCI Slot
J505 : CPU Fan Connector
PJ502
J509
J512
J515
J506,J507 : USB Connector
J508 : Modem Connector
J516
J509,J512 : SO DIMM Slot
J505
J510 : CD-ROM Connector
J511 : RJ11/RJ45 Connector
PJ501
J514 : HDD Connector
J515 : MDC Connector
J501
J511 J508
J507
J506
J516 : CMOS Battery Connector
PJ501 : AC Adapter Jack
J502
78
PJ502 : Battery Connector
3. Definition & Location of Connectors / Switches
3.2 Mother Board-B
J1 : LCD Connector
J511
J2 : Left Audio Channel Connector
J515
SW7
J3 : LCD Inverter Board Connector
J4 : Internal Keyboard Connector
J4
J5 : Touch Pad Connector
J5
J6 : PC Card Slot
J8 : Microphone Jack
SW6
J9
J9 : Audio Output Jack
SW2 : H8 Power Button
J1
SW6 : SW_LEFT
J2
SW2
J8
J6
J3
79
SW7 : SW_RIGHT
4. Definition & Location of Major Components
4.1 Mother Board-A
U504 : Intel Monrata-GME
U506 : Intel Banias CPU
U519
U508 : Clock Generator PLL207-1510C
U510 : CB710 Card Bud Control&Reader
U504
U511 : LAN VT6105-L
U512 : BIOS SST49LF004A
U519 : Audio Codec ALC202
U508
U506
U510
U511
U512
80
4. Definition & Location of Major Components
4.2 Mother Board-B
U5 : TV Encoder CH7011A
U7 : Winbond W83L950D
U12 : Intel ICH4-M
U7
U12
U5
81
5. Pin Descriptions of Major Components
5.1 Intel Pentium M Processor
CPU Pin Description
`Signal Name
CPU Pin Description Continue
Type
Description
A[31:3]#
I/O
A20M#
I
A[31:3]# (Address) define a 2 32 -byte physical memory address space.
In sub-phase 1 of the address phase, these pins transmit the address of a
transaction. In sub-phase 2, these pins transmit transaction type
information. These signals must connect the appropriate pins of both
agents on the Intel Pentium M processor system bus. A[31:3]# are source
synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#. Address signals are used as straps which are sampled
before RESET# is deasserted.
If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents
observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising
and falling edges. Strobes are associated with signals as shown below.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[31:17]#
ADSTB[1]#
The differential pair BCLK (Bus Clock) determines the system bus
frequency. All processor system bus agents must receive these signals to
drive their outputs and latch their inputs.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent
that is unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor that indicate the
status of breakpoints and programmable counters used for monitoring
processor performance. BPM[3:0]# should connect the appropriate pins
of all Intel Pentium M processor system bus agents. This includes debug
or performance monitoring tools.
ADS#
I/O
ADSTB[1:0]#
I/O
BCLK[1:0]
I
BNR#
I/O
BPM[2:0]#
BPM[3]
O
I/O
Signal Name
BPRI#
BR0#
COMPP3:0]
D[63:0]#
DBR#
82
Type
I
Description
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of both
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes the other agent to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting BPRI#.
I/O BR0# is used by the processor to request the bus. The arbitration is done
between the Intel Pentium M processor (Symmetric Agent) and the
MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM
chipset.
Analog COMP[3:0] must be terminated on the system board using precision
(1% tolerance) resistors. Refer to the platform design guides for more
implementation details.
I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
path between the processor system bus agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in
a common clock period. D[63:0]# are latched off the falling edge of
both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals
correspond to a pair of one DSTBP# and one DSTBN#. The following
table shows the grouping of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups
Data Group
DSTBN#/DSTBP#
DINV#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3
Furthermore, the DINV# pins determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DINV# signal. When
the DINV# signal is active, the corresponding data group is inverted and
therefore sampled active high.
O
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system reset. If
a debug port is implemented in the system, DBR# is a no connect.
DBR# is not a processor signal.
Signal Name
DBSY#
DEFER#
DINV[3:0]#
DPSLP#
DRDY#
Type
Description
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use.
The data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both processor system bus agents.
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or Input/Output agent. This
signal must connect the appropriate pins of both processor system bus
agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate
the polarity of the D[63:0]# signals. The DINV[3:0]# signals are
activated when the data on the data bus is inverted. The bus agent will
invert the data bus signals if more than half the bits, within the covered
group, would change level in the next cycle.
DINV[3:0]# Assignment To Data Bus
Bus Signal
Data Bus Signals
DINV[3]#
D[63:48]#
DINV[2]#
D[47:32]#
DINV[1]#
D[31:16]#
DINV[0]#
D[15:0]#
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep state to the Deep Sleep state. In order to return
to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the
ICH4-M component and also connects to the MCH-M component of the
Intel 855PM or Intel 855GM chipset.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common clock
data transfer, DRDY# may be deasserted to insert idle clocks. This
signal must connect the appropriate pins of both processor system bus
agents.
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBN[0]#
D[31:16]#, DINV[1]#
DSTBN[1]#
D[47:32]#, DINV[2]#
DSTBN[2]#
D[63:48]#, DINV[3]#
DSTBN[3]#
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBP[0]#
D[31:16]#, DINV[1]#
DSTBP[1]#
D[47:32]#, DINV[2]#
DSTBP[2]#
D[63:48]#, DINV[3]#
DSTBP[3]#
I
I/O
I
I/O
DSTBN[3:0]#
I/O
DSTBP[3:0]#
I/O
Type
Description
DPWR#
Signal Name
I
FERR#/PBE#
O
GTLREF
I
DPWR# is a control signal from the Intel 855PM and Intel 855GM
chipsets used to reduce power on the Intel Pentium M data bus input
buffers.
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point when
the processor detects an unmasked floating-point error. FERR# is
similar to the ERROR# signal on the Intel 80387 coprocessor, and is
included for compatibility with systems using MS-DOS* type
floating-point error reporting. When STPCLK# is asserted, an assertion
of FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until
STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active
will also cause an FERR# break event.
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Either system bus agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor system bus. This transaction
may optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error. IGNNE# has no effect when
the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
REQ[4:0]# (Request Command) must connect the appropriate pins of
both processor system bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
HIT#
HITM#
I/O
I/O
IERR#
O
IGNNE#
I
REQ[4:0]#
83
I/O
Signal Name
Type
Description
INIT#
I
LINT[1:0]
I
INIT# (Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-point registers.
The processor then begins execution at the power on Reset vector
configured during power on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal. However, to ensure recognition of this signal following an
Input/Output Write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both processor system bus
agents. If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST)
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of
all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor.
Both signals are asynchronous.
Both of these signals must be software configured using BIOS
programming of the APIC register space and used either as NMI/INTR
or LINT[1:0]. Because the APIC is enabled by default after Reset,
operation of these pins as LINT[1:0] is the default configuration.
LOCK# indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of both processor system
bus agents. For a locked sequence of transactions, LOCK# is asserted
from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor system bus, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of the processor
system bus throughout the bus locked operation and ensure the
atomicity of lock.
Probe Ready signal used by debug tools to determine processor debug
readiness.
Probe Request signal used by debug tools to request debug operation of
the processor.
PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit has been activated, if enabled.
This signal may require voltage translation on the motherboard.
Processor Power Status Indicator signal. This signal is asserted when the
processor is in a lower state (Deep Sleep and Deeper Sleep).
LOCK#
I/O
PRDY#
O
PREQ#
I
PROCHOT#
O
PSI#
O
Signal Name
84
Type
Description
PWRGOOD
I
ITP_CLK[1:0]
I
RESET#
I
RS[2:0]#
I
RSVD
-
SLP#
I
PWRGOOD (Power Good) is a processor input. The processor requires
this signal as a clean indication that the clocks and power supplies are
stable and within their specifications. ‘Clean’ implies that the signal will
remain low (capable of sinking leakage current), without glitches, from
the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high
state. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should be
driven high throughout the boundary scan operation.
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects. These are not processor signals.
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents.
For a power-on Reset, RESET# must stay active for at least two
milliseconds after VCC and BCLK have reached their proper
specifications. On observing active RESET#, both system bus agents
will deassert their outputs within two clocks. All processor straps must
be valid within the specified setup time before RESET# is deasserted.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect
the appropriate pins of both processor system bus agents.
These pins are RESERVED and must be left unconnected on the board.
However, it is recommended that routing channels to these pins on the
board be kept open for possible future use. Please refer to the platform
design guides for more details.
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to
enter the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Locked Loop
(PLL) still operating. Processors in this state will not recognize snoops
or interrupts. The processor will recognize only assertion of the
RESET# signal, deassertion of SLP#, and removal of the BCLK input
while in Sleep state. If SLP# is deasserted, the processor exits Sleep
state and returns to Stop-Grant state, restarting its internal clock signals
to the bus and processor core units. If DPSLP# is asserted while in the
Sleep state, the processor will exit the Sleep state and transition to the
Deep Sleep state.
Signal Name
SMI#
STPCLK#
TCK
TDI
TDO
TEST1,
TEST2,
TEST3
THERMDA
THERMDC
THERMTRIP#
TMS
TRDY#
TRST#
Type
Signal Name
Description
I
SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management Mode
(SMM). An SMI Acknowledge transaction is issued, and the processor
begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will
tristate its outputs.
I
STPCLK# (Stop Clock), when asserted, causes the processor to enter a
low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals to
all processor core units except the system bus and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the processor
restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
I
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
I
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
I
TEST1, TEST2, and TEST3 must be left unconnected but should have a
stuffing option connection to V SS separately using 1-k, pull-down
resisitors.
Other Thermal Diode Anode.
Other Thermal Diode Cathode.
O
The processor protects itself from catastrophic overheating by use of an
internal thermal sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature exceeds
approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
I
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
I
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both system bus agents.
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
85
Type
Description
VCC
VCCA[3:0]
VCCP
VCCQ[1:0]
I
I
I
I
VCCSENSE
O
VID[5:0]
O
VSSSENSE
O
Processor core power supply.
VCCA provides isolated power for the internal processor core PLL’s.
Processor I/O Power Supply.
Quiet power supply for on die COMP circuitry. These pins should be
connected to VCCP on the motherboard. However, these connections
should enable addition of decoupling on the VCCQ lines if necessary.
VCCSENSE is an isolated low impedance connection to processor core
power (VCC ). It can be used to sense or measure power near the silicon
with little noise.
VID[5:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (Vcc). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Intel Pentium
M processor. The voltage supply for these pins must be valid before the
VR can supply Vcc to the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID pins becomes valid. The
VID pins are needed to support the processor voltage specification
variations.
VSSSENSE is an isolated low impedance connection to processor core
VSS. It can be used to sense or measure ground near the silicon with
little noise.
5.2 Intel 82855GME Graphics and Memory Controller Hub (GMCH)
Host Interface Signal Descriptions
Signal Name
Host Interface Signals Continue
Type
Description
ADS#
I/O
AGTL+
BNR#
I/O
AGTL+
BPRI#
O
AGTL+
Address Strobe: The system bus owner asserts ADS# to indicate the
first of two cycles of a request phase. The GMCH can assert this
signal for snoop cycles and
interrupt messages.
Block Next Request: Used to block the current request bus owner
from issuing a new request. This signal is used to dynamically control
the CPU bus pipeline depth.
Bus Priority Request: The GMCH is the only Priority Agent on the
system bus. It asserts this signal to obtain the ownership of the
address bus. This signal has priority over symmetric bus requests and
will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was
asserted.
Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal
low during CPURST#. The signal is sampled by the processor on the
active-to-inactive transition of CPURST#. The minimum setup time
for this signal is 4 BCLKs. The minimum hold time is 2 clocks and
the maximum hold time is 20 BCLKs. BREQ0# should be tristated
after the hold time requirement has been satisfied.
During regular operation, the GMCH will use BREQ0# as an early
indication for FSB Address and Ctl input buffer and sense amp
activation.
CPU Reset: The CPURST# pin is an output from the GMCH. The
GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M)
is asserted and for approximately 1 ms after RESET# is deasserted.
The CPURST# allows the processor to begin execution in a known
state.
Note that the ICH4-M must provide CPU strap set-up and hold-times
around CPURST#.
This requires strict synchronization between GMCH, CPURST#
deassertion and ICH4-M driving the straps.
Data Bus Busy: Used by the data bus owner to hold the data bus for
transfers requiring more than one cycle.
Defer: GMCH will generate a deferred response as defined by the
rules of the GMCH’s Dynamic Defer policy. The GMCH will also
use the DEFER# signal to indicate a CPU retry response.
BREQ0#
CPURST#
DBSY#
DEFER#
I/O
AGTL+
O
AGTL+
I/O
AGTL+
O
AGTL+
Type
Description
DINV[3:0]#
Signal Name
I/O
AGTL+
DPSLP#
I
CMOS
DRDY#
I/O
AGTL+
I/O
AGTL+
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.
Indicates if the associated signals are inverted or not. DINV[3:0]# are
asserted such that the number of data bits driven electrically low (low
voltage) within the corresponding 16-bit group never exceeds 8.
DINV# Data Bits
DINV[3]# HD[63:48]#
DINV[2]# HD[47:32]#
DINV[1]# HD[31:16]#
DINV[0]# HD[16:0]#
Deep Sleep #: This signal comes from the ICH4-M device, providing
an indication of C3 and C4 state control to the CPU. Deassertion of
this signal is used as an early indication for C3 and C4 wake up (to
active HPLL). Note that this is a low-voltage
CMOS buffer operating on the FSB VTT power plane.
Data Ready: Asserted for each cycle that data is transferred.
HA[31:3]#
86
HADSTB[1:0]#
I/O
AGTL+
HD[63:0]#
I/O
AGTL+
Host Address Bus: HA[31:3]# connects to the CPU address bus.
During processor cycles the HA[31:3]# are inputs. The GMCH drives
HA[31:3]# during snoop cycles on behalf of Hub interface.
HA[31:3]# are transferred at 2x rate. Note that the
address is inverted on the CPU bus.
Host Address Strobe: HA[31:3]# connects to the CPU address bus.
During CPU cycles, the source synchronous strobes are used to
transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
Strobe Address Bits
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
Host Data: These signals are connected to the CPU data bus.
HD[63:0]# are transferred at 4x rate. Note that the data signals are
inverted on the CPU bus.
DDR SDRAM Interface Descriptions
Host Interface Signal Descriptions (Continued)
Signal Name
HDSTBP[3:0]#
HDSTBN[3:0]#
Type
Description
I/O
AGTL+
Differential Host Data Strobes: The differential source synchronous
strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x
transfer rate.
Strobe Data Bits
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#
Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, driven in conjunction with HITM# by the target
to extend the snoop window.
Hit Modified: Indicates that a caching agent holds a modified version
of the requested line and that this agent assumes responsibility for
providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
Host Lock: All CPU bus cycles sampled with the assertion of
HLOCK# and ADS#, until the negation of HLOCK# must be atomic,
i.e. no Hub interface snoopable access to system memory is allowed
when HLOCK# is asserted by the CPU.
Host Request Command: Defines the attributes of the request.
HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting
agent during both halves of the Request Phase. In the first half the
signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second half the
signals carry additional information to define the complete transaction
type.
The transactions supported by the GMCH Host Bridge are defined in
the Host Interface section of this document.
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data transfer phase.
Response Status: Indicates the type of response according to the
following the table:
RS[2:0]# Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit Write back
111 Normal data response
HIT#
I/O
AGTL+
HITM#
I/O
AGTL+
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
I/O
AGTL+
I/O
AGTL+
O
AGTL+
O
AGTL+
Type
Description
SCS[3:0]#
Signal Name
O
SSTL_2
SMA[12:0]
O
SSTL_2
O
SSTL_2
Chip Select: These pins select the particular DDR SDRAM
components during the active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM
device row.
These signals can be toggled on every rising System Memory Clock
edge (SCMDCLK).
Multiplexed Memory Address: These signals are used to provide
the multiplexed row and column address to the DDR SDRAM.
Bank Select (Memory Bank Address): These signals define which
banks are selected within each DDR SDRAM row. The SMA and
SBA signals combine to address every possible location within a
DDR SDRAM device.
DDR Row Address Strobe: SRAS# may be heavily loaded and
requires tw0 DDR SDRAM clock cycles for setup time to the DDR
SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define
the system memory commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and
requires two clock cycles for setup time to the DDR SDRAMs. Used
with SRAS# and SWE# (along with SCS#) to define the system
memory commands.
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
define the DDR SDRAM commands. SWE# is asserted during writes
to DDR SDRAM.
SWE# may be heavily loaded and requires two clock cycles for setup
time to the DDR SDRAMs.
Data Lines: These signals are used to interface to the DDR SDRAM
data bus.
NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
SBA[1:0]
87
SRAS#
O
SSTL_2
SCAS#
O
SSTL_2
SWE#
O
SSTL_2
SDQ[71:0]
I/O
SSTL_2
DDR SDRAM Interface Descriptions (Continued)
Signal Name
Type
Description
SDQS[8:0]
I/O
SSTL_2
SCKE[3:0]
O
SSTL_2
SMAB[5,4,2,1]
O
SSTL_2
SDM[8:0]
O
SSTL_2
RCVENOUT#
O
SSTL_2
O
SSTL_2
Data Strobes: Data strobes are used for capturing data. During
writes, SDQS is centered on data. During reads, SDQS is edge
aligned with data. The following list matches the data strobe with the
data bytes.
There is an associated data strobe (DQS) for each data signal (DQ)
and check bit
(CB) group.
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
SDQS[5] -> SDQ[47:40]
SDQS[4] -> SDQ[39:32]
SDQS[3] -> SDQ[31:24]
SDQS[2] -> SDQ[23:16]
SDQS[1] -> SDQ[15:8]
SDQS[0] -> SDQ[7:0]
NOTE: ECC error detection is supported by the SDQS[8] signal.
Clock Enable: These pins are used to signal a self-refresh or power
down command to the DDR SDRAM array when entering system
suspend. SCKE is also used to dynamically power down inactive
DDR SDRAM rows. There is one
SCKE per DDR SDRAM row. These signals can be toggled on every
rising SCK edge.
Memory Address Copies: These signals are identical to
SMA[5,4,2,1] and are used to reduce loading for selective
CPC(clock-per-command). These copies are not inverted.
Data Mask: When activated during writes, the corresponding data
groups in the DDR SDRAM are masked. There is one SDM for every
eight data lines. SDM can be sampled on both edges of the data
strobes.
NOTE: ECC error detection is supported by the SDM[8] signal.
Clock Output: Reserved, NC.
RCVENIN#
AGP Addressing Signal Descriptions
Signal Name
Type
Clock Input: Reserved, NC.
88
I
AGP
Description
Pipelined Read: This signal is asserted by the AGP master to
indicate a full width address is to be enqueued on by the target using
the AD bus. One address is placed
in the AGP request queue on each rising clock edge while PIPE# is
asserted. When PIPE# is deasserted no new requests are queued
across the AD bus.
During SBA Operation: This signal is not used if SBA (Side Band
Addressing) is selected.
During FRAME# Operation: This signal is not used during AGP
FRAME# operation.
PIPE# is a sustained tri-state signal from masters (graphics
controller), and is an input to the GMCH.
I
Side-band Address: These signals are used by the AGP master
GSBA[7:0]
AGP
(graphics controller) to pass address and command to the GMCH. The
SBA bus and AD bus operate independently. That is, transactions can
proceed on the SBA bus and the
AD bus simultaneously.
During PIPE# Operation: These signals are not used during PIPE#
operation.
During FRAME# Operation: These signals are not used during
AGP FRAME# operation.
NOTE: When sideband addressing is disabled, these signals are
isolated (no external/internal pull-ups are required).
5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use
one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is
used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example,
during configuration time, if the master indicates that it can use either mechanism, the configuration
software will indicate which mechanism the master will use. Once this choice has been made, the
master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use
the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when
the device is first being configured after reset
GPIPE#
AGP Status Signal Descriptions
Signal Name
GST[2:0]
AGP Flow Control Signals
Type
O
AGP
Description
Status: Provides
information from
the arbiter to an
AGP Master on
what it may do.
ST[2:0] only
have meaning
to the master
when its GNT# is
asserted. When
GNT# is
deasserted
these signals have
no meaning and
must be gnored.
ST[2:0
Meaning
000
Previously requested low priority
read data is being returned to the
master arbiter to an AGP
001
100
Previously requested high priority
read data is being returned to the
master
The master is to provide low priority
write data for a previously queued
write command
The master is to provide high
priority write data for a previously
queued write command.
Reserved
101
Reserved
110
Reserved
111
The master has been given
permission to start a bus transaction.
The master may queue AGP requests
by asserting PIPE# or start a PCI
transaction by asserting FRAME#
010
011
Signal Name
89
Type
Description
GRBF#
I
AGP
GWBF#
I
AGP
Read Buffer Full: Read buffer full indicates if the master is ready to
accept previously requested low priority read data. When RBF# is
asserted the GMCH is not allowed to initiate the return low priority
read data. That is, the GMCH can finish
returning the data for the request currently being serviced. RBF# is
only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is
not required to implement this signal.
FRAME# operation.
Write-Buffer Full: indicates if the master is ready to accept Fast
Write data from the GMCH. When WBF# is asserted the GMCH is
not allowed to drive Fast Write data to the AGP master. WBF# is
only sampled at the beginning of a cycle.
If the AGP master is always ready to accept fast write data then it is
not required to implement this signal.
FRAME# operation.
AGP Strobe Descriptions
AGP/PCI Signals-Semantics Descriptions
Signal Name
GFRAME#
GIRDY#
Type
Description
I/O
AGP
G_FRAME: Frame.
During PIPE# and SBA Operation: Not used by AGP SBA and
PIPE# operations.
During Fast Write Operation: Used to frame transactions as an
output during Fast Writes.
During FRAME# Operation: G_FRAME# is an output when the
GMCH acts as an initiator on the AGP Interface. G_FRAME# is
asserted by the GMCH to indicate the
beginning and duration of an access. G_FRAME# is an input when
the GMCH acts as a FRAME#-based AGP target. As a
FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and
the AD[31:0] signals on the first clock edge on which
GMCH samples FRAME# active.
G_IRDY#: Initiator Ready.
During PIPE# and SBA Operation: Not used while enqueueing
requests via AGP SBA and PIPE#, but used during the data phase of
PIPE# and SBA transactions.
During FRAME# Operation: G_IRDY# is an output when GMCH
acts as a FRAME#-based AGP initiator and an input when the GMCH
acts as a FRAME#-based AGP target. The assertion of G_IRDY#
indicates the current FRAME#-based AGP bus initiator's ability to
complete the current data phase of the transaction.
During Fast Write Operation: In Fast Write mode, G_IRDY#
indicates that the AGP-compliant master is ready to provide all write
data for the current transaction. Once G_IRDY# is asserted for a write
operation, the master is not allowed to insert wait states. The master is
never allowed to insert a wait state during the initial data transfer (32
bytes) of a write transaction. However, it may insert wait states after
each 32-byte block is transferred.
I/O
AGP
Signal Name
90
Type
Description
GADSTB[0]
I/O
AGP
GADSTB#[0]
I/O
AGP
GADSTB[1]
I/O
AGP
GADSTB#[1]
I/O
AGP
GSBSTB
I
AGP
GSBSTB#
I
AGP
Address/Data Bus Strobe-0: provides timing for 2x and 4x data on
AD[15:0] and C/BE[1:0]# signals. The agent that is providing the
data will drive this signal.
Address/Data Bus Strobe-0 Complement: With AD STB0, forms a
differential strobe pair that provides timing information for the
Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on
Address/Data Bus Strobe-1 Complement: With AD STB1, forms a
differential strobe pair that provides timing information for the
AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is
providing the data will drive this signal.
Sideband Strobe: Provides timing for 2x and 4x data on the
SBA[7:0] bus. It is driven by the AGP master after the system has
been configured for 2x or 4x sideband address mode.
Sideband Strobe Complement: The differential complement to the
SB_STB signal. It is used to provide timing 4x mode.
AGP/PCI Signals-Semantics Descriptions (Continued)
Type
Description
GTRDY#
Signal Name
I/O
AGP
GSTOP#
I/O
AGP
GDEVSEL#
I/O
AGP
GREQ#
I
AGP
G_TRDY#: Target Ready.
During PIPE# and SBA Operation: Not used while enqueueing
requests via AGP SBA and PIPE#, but used during the data phase of
PIPE# and SBA transactions.
During FRAME# Operation: G_TRDY# is an input when the
GMCH acts as an AGP initiator and is an output when the GMCH
acts as a FRAME#-based AGP target. The assertion of G_TRDY#
indicates the target’s ability to complete the current data phase of the
transaction.
During Fast Write Operation: In Fast Write mode, G_TRDY#
indicates the AGP-compliant target is ready to receive write data for
the entire transaction (when the transfer size is less than or equal to 32
bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater
than 32 bytes. The target is allowed to insert wait states after each
block (32 bytes) is transferred on write transactions.
G_STOP#: Stop.
During PIPE# and SBA Operation: This signal is not used during
PIPE# or SBA operation.
During FRAME# Operation: G_STOP# is an input when the
GMCH acts as a FRAME#-based AGP initiator and is an output when
the GMCH acts as a FRAME#-based AGP target. G_STOP# is used
for disconnect, retry, and abort sequences on the AGP interface.
G_ DEVSEL#: Device Select.
During PIPE# and SBA Operation: This signal is not used during
PIPE# or SBA operation.
During FRAME# Operation: G_DEVSEL#, when asserted,
indicates that a FRAME#-based AGP target device has decoded its
address as the target of the current access. The GMCH asserts
G_DEVSEL# based on the DDR SDRAM
address range being accessed by a PCI initiator. As an input,
G_DEVSEL# indicates whether the AGP master has recognized a
PCI cycle to it.
G_REQ#: Request.
During SBA Operation: This signal is not used during SBA
operation.
During PIPE# and FRAME# Operation: G_REQ#, when asserted,
indicates that the AGP master is requesting use of the AGP interface
to run a FRAME#- or PIPE#-based operation.
Signal Name
GGNT#
Type
O
AGP
Description
G_GNT#: Grant.
During SBA, PIPE# and FRAME# Operation: G_GNT#, along
with the information on the ST[2:0] signals (status bus), indicates
how the AGP interface will be used next. Refer to the AGP Interface
Specification, Revision 2.0 for further explanation
of the ST[2:0] values and their meanings.
I/O
GAD[31:0]
G_AD[31:0]: Address/Data Bus.
AGP
During PIPE# and FRAME# Operation: The G_AD[31:0] signals
are used to transfer both address and data information on the AGP
interface.
During SBA Operation: The G_AD[31:0] signals are used to
transfer data on the AGP interface.
I/O
GCBE#[3:0]
Command/Byte Enable.
AGP
During FRAME# Operation: During the address phase of a
transaction, the G_CBE[3:0]# signals define the bus command.
During the data phase, the G_CBE[3:0]# signals are used as byte
enables. The byte enables determine which byte lanes carry
meaningful data. The commands issued on the G_CBE# signals
during FRAME#-based AGP transactions are the same G_CBE#
command described in the PCI 2.2 specification.
During PIPE# Operation: When an address is enqueued using
PIPE#, the C/BE# signals carry command information. The command
encoding used during PIPE#-based AGP is different than the
command encoding used during FRAME#-based AGP cycles (or
standard PCI cycles on a PCI bus).
During SBA Operation: These signals are not used during SBA
operation.
I/O
GPAR
Parity.
AGP
During FRAME# Operation: G_PAR is driven by the GMCH when
it acts as a FRAME#-based AGP initiator during address and data
phases for a write cycle, and during the address phase for a read
cycle. G_PAR is driven by the GMCH when it acts as a
FRAME#-based AGP target during each data phase of a
FRAME#-based AGP memory read cycle. Even parity is generated
across G_AD[31:0] and G_CBE[3:0]#.
During SBA and PIPE# Operation: This signal is not used during
SBA and PIPE# operation.
PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface
logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as
an input to reset its internal logic.
91
Hub Interface Signals
Signal Name
HL[10:0]
HLSTB
HLSTB#
Digital Video Output B (DVOB) Port Signal Descriptions
Type
I/O
Hub
I/O
Hub
I/O
Hub
Description
Name
Packet Data: Data signals used for HI read and write operations.
DVOBD[11:0]
Type
O
DVO
Packet Strobe: One of two differential strobe signals used to transmit
or receive packet data over HI.
Packet Strobe Complement: One of two differential strobe signals
used to transmit or receive packet data over HI.
DVOBHSYNC
O
DVO
DVOBVSYNC
O
DVO
DVOBBLANK# O
DVO
Dedicated LVDS LCD Flat Panel Interface Signal Descriptions
Name
Type
ICLKAP
O
LVDS
O
LVDS
O
LVDS
O
LVDS
O
LVDS
O
LVDS
O
LVDS
O
LVDS
ICLKAM
IYAP[3:0]
IYAM[3:0]
ICLKBP
ICLKBM
IYBP[3:0]
IYBM[3:0]
Voltage
Description
1.25 V± 225 mV Channel A differential clock pair output (true):
245-800 MHz
1.25 V±225 mV Channel A differential clock pair output
(compliment): 245-800 MHz.
1.25 V±225 mV Channel A differential data pair 3:0 output (true):
245-800MHz.
1.25 V±225 mV Channel A differential data pair 3:0 output
1.25 V±225 mV Channel B differential clock pair output (true):
245-800 MHz.
1.25 V±225 mV Channel B differential clock pair output
1.25 V±225 mV Channel B differential data pair 3:0 output (true):
245-800MHz.
1.25 V± 225 mV Channel B differential data pair 3:0 output
DVOBFLDSTL I
DVO
92
Description
DVOB Data: This data bus is used to drive 12-bit RGB data on each
edge of the differential clock signals, DVOBCLK and DVOBCLK#.
This provides 24-bits of data per clock period. In dual channel mode,
this provides the lower 12-bits of pixel data.
DVOBD[11:0] should be left as left as NC (“Not Connected”) if not
used.
Horizontal Sync: HSYNC signal for the DVOB interface.
DVOBHSYNC should be left as left as NC (“Not Connected”) if not
used.
Vertical Sync: VSYNC signal for the DVOB interface.
DVOBVSYNC should be left as left as NC (“Not Connected”) if the
signal is NOT used when using internal graphics device.
Flicker Blank or Border Period Indication: DVOBBLANK# is a
programmable output pin driven by the GMCH.
When programmed as a blank period indication, this pin indicates
active pixels excluding the border. When programmed as a border
period indication, this pin indicates active pixel including the border
pixels.
DVOBBLANK# should be left as left as NC (“Not Connected”) if not
used.
TV Field and Flat Panel Stall Signal. This input can be
programmed to be either a TV Field input from the TV encoder or
Stall input from the flat panel.
DVOB TV Field Signal: When used as a Field input, it synchronizes
the overlay field with the TV encoder field when the overlay is
displaying an interleaved source.
DVOB Flat Panel Stall Signal: When used as the Stall input, it
indicates that the pixel pipeline should stall one horizontal line. The
signal changes during horizontal blanking. The panel fitting logic,
when expanding the image vertically, uses this.
DVOBFLDSTL needs to be pulled down if not used.
Digital Video Output C (DVOC) Port Signal Descriptions
DVOB and DVOC Port Common Signal Descriptions
Name
DVOBCINTR#
ADDID[7:0]
DVODETECT
Type
Description
I
DVO
I
DVO
DVOBC Interrupt: This pin is used to signal an interrupt, typically
used to indicate a hot plug or unplug of a digital display.
ADDID[7:0]: These pins are used to communicate to the Video BIOS
when an external device is interfaced to the DVO port.
Note: Bit[7] needs to be strapped low when an on-board DVO device
is present.
The other pins should be left as NC.
DVODETECT: This strapping signal indicates to the GMCH
whether a DVO device is present or not. When a DVO device is
connected, then DVODETECT = 0.
I
DVO
Type
Description
DVOCD[11:0]
Name
O
DVO
DVOCHSYNC
O
DVO
DVOCVSYNC
O
DVO
DVOCBLANK#
O
DVO
DVOCFLDSTL
I
DVO
DVOC Data: This data bus is used to drive 12-bit RGB data on each
edge of the differential clock signals, DVOCCLK and DVOCCLK#.
This provides 24-bits of data per clock period. In dual channel mode,
this provides the upper 12-bits of pixel data.
DVOCD[11:0] should be left as left as NC (“Not Connected”) if not
used.
Horizontal Sync: HSYNC signal for the DVOC interface.
DVOCHSYNC should be left as left as NC (“Not Connected”) if not
used.
Vertical Sync: VSYNC signal for the DVOC interface.
DVOCVSYNC should be left as left as NC (“Not Connected”) if the
signal is NOT used when using internal graphics device.
Flicker Blank or Border Period Indication: DVOCBLANK# is a
programmable output pin driven by the GMCH.
When programmed as a blank period indication, this pin indicates
active pixels excluding the border. When programmed as a border
period indication, this pin indicates active pixel including the border
pixels.
DVOCBLANK# should be left as left as NC (“Not Connected”) if not
used.
TV Field and Flat Panel Stall Signal. This input can be
programmed to be either a TV Field input from the TV encoder or
Stall input from the flat panel.
DVOC TV Field Signal: When used as a Field input, it synchronizes
the overlay field with the TV encoder field when the overlay is
displaying an interleaved source.
DVOC Flat Panel Stall Signal: When used as the Stall input, it
indicates that the pixel pipeline should stall one horizontal line. The
signal changes during horizontal blanking. The panel fitting logic,
when expanding the image vertically, uses this.
DVOCFLDSTL needs to be pulled down if not used.
Analog CRT Display Signal Descriptions
Pin Name
VSYNC
HSYNC
RED
RED#
GREEN
GREEN#
BLUE
BLUE#
Type
Description
O
CMOS
O
CMOS
O
Analog
CRT Vertical Synchronization: This signal is used as the vertical
sync signal.
CRT Horizontal Synchronization: This signal is used as the
horizontal sync signal.
Red (Analog Video Output): This signal is a CRT Analog video
output from the internal color palette DAC. The DAC is designed for
a 37.5-§Ù equivalent load on each pin (e.g., 75-§Ù resistor on the
board, in parallel with the 75-§Ù CRT load).
Red# (Analog Output): Tied to ground.
O
Analog
O
Analog
O
Analog
O
Analog
O
Analog
Green (Analog Video Output): This signal is a CRT analog video
a 37.5-§Ù equivalent load on each pin (e.g.,75-§Ù resistor on the
board, in parallel with the 75- §Ù CRT load).
Green# (Analog Output): Tied to ground.
Blue (Analog Video Output) : This signal is a CRT Analog video
a 37.5-§Ù equivalent load on each pin (e.g., 75ohm resistor on the board, in parallel with the 75-§Ù CRT load).
Blue# (Analog Output): Tied to ground.
93
GPIO Signal Descriptions
GPIO I/F Total
RSTIN#
PWROK
AGPBUSY#
EXTTS_0
LCLKCTLA
LCLKCTLB
PANELVDDEN
PANELBKLTE
N
PANELBKLTC
TL
DDCACLK
DDCADATA
DDCPCLK
DDCPDATA
Type
I
CMOS
I
CMOS
O
CMOS
I
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
I/O
CMOS
I/O
CMOS
I/O
CMOS
I/O
CMOS
GPIO I/F Total
Comments
Reset: Primary Reset, Connected to PCIRST# of ICH4-M.
Type
MI2CCLK
I/O
DVO
MI2CDATA
I/O
DVO
MDVICLK
I/O
DVO
MDVIDATA
I/O
DVO
MDDCDATA
I/O
DVO
MDDCCLK
I/O
DVO
Power OK: Indicates that power to GMCH is stable.
AGPBUSY: Output of the GMCH IGD to the ICH4-M, which
indicates that certain graphics activity is taking place. It will indicate
to the ACPI software not to enter the C3 state. It will
also cause a C3/C4 exit if C3/C4 was being entered, or was already
entered when
AGPBUSY# went active. Not active when the IGD is in any ACPI
state other than D0.
External Thermal Sensor Input: This signal is an active low input
to the GMCH and is used to monitor the thermal condition around the
system memory and is used for triggering a read throttle. The GMCH
can be optionally programmed to send a SERR, SCI, or SMI message
to the ICH4-M upon the triggering
of this signal.
SSC Chip Clock Control: Can be used to control an external clock
chip with SSC control.
SSC Chip Data Control: Can be used to control an external clock
chip for SSC control.
LVDS LCD Flat Panel Power Control: This signal is used enable
power to the panel interface.
LVDS LCD Flat Panel Backlight Enable: This signal is used to
enable the backlight inverter (BLI)
LVDS LCD Flat Panel Backlight Brightness Control: This signal
is used as the Pulse
Width Modulated (PWM) control signal to control the backlight
inverter.
CRT DDC Clock: This signal is used as the DDC clock signal
between the CRT monitor and the GMCH.
CRT DDC Data: This signal is used as the DDC data signal between
the CRT monitor and the GMCH.
Panel DDC Clock: This signal is used as the DDC clock signal
between the LFP and the GMCH.
Panel DDC Data: This signal is used as the DDC data signal
between the LFP and the GMCH.
94
Comments
DVO I2C Clock: This signal is used as the I2C_CLK for a digital
display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
tri-stated during a hard reset.
DVO I2C Data: This signal is used as the I2C_DATA for a digital
display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
DVI DDC Clock: This signal is used as the DDC clock for a digital
display connector (i.e. primary digital monitor). This signal is
DVI DDC Data: The signal is used as the DDC data for a digital
display connector (i.e. primary digital monitor). This signal is
DVI DDC Clock: The signal is used as the DDC data for a digital
display connector (i.e. secondary digital monitor). This signal is
DVI DDC Data: The signal is used as the DDC clock for a digital
display connector (i.e. secondary digital monitor). This signal is
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
Signal Name
Firmware Hub Interface Signals
Type
Description
HI[11:0]
I/O
HI_STB/HI_STBS
I/O
HI_STB#/
HI_STBF
I/O
Hub Interface Strobe/ Hub Interface Strobe Second: One of two
differential strobe signals used to transmit and receive data through
the hub interface.
Hub Interface 1.5 mode this signal is not differential and is the
second of the two strobe signals.
Hub Interface Strobe Complement / Hub Interface Strobe First:
One of two differential strobe signals used to transmit and receive
data through the hub interface.
Hub Interface 1.5 mode this signal is not differential and is the first
of the two strobe signals.
Hub Interface Compensation: Used for hub interface buffer
compensation.
Hub Interface Voltage Swing: Analog input used to control the
voltage swing and impedance strength of hub interface pins.
HICOMP
HI_VSWING
I/O
I
Signal Name
FWH[3:0]/
LAD[3:0]
FWH[4]/
LFRAME#
Type
Firmware Hub Signals. Muxed with LPC address signals.
I/O
LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME#
signal.
PCI Interface Signals
Type
Description
AD[31:0]
Signal Name
I/O
C/BE[3:0]#
I/O
DEVSEL#
I/O
PCI Address/Data: AD[31:0] is a multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a
physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The ICH4 drives all 0s on AD[31:0] during the address
phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3:0]# define the bus command. During
the data phase, C/BE[3:0]# define the Byte Enables.
C/BE[3:0]#
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0110
Memory Read
0111
Memory Write
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1110
Memory Read Line
1111
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH4 does not
decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.
Device Select: The ICH4 asserts DEVSEL# to claim a PCI
transaction. As an output, the ICH4 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH4 address or
an address destined for the hub interface (main memory or AGP).
As an input, DEVSEL# indicates the response to an ICH4-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until
driven by a Target device.
LAN Connect Interface Signals
Type
Description
LAN_CLK
Signal Name
I
LAN_RXD[2:0]
I
LAN_TXD[2:0]
O
LAN_RSTSYNC
O
LAN I/F Clock: Driven by the LAN Connect component.
Frequency range is 5 MHz to 50 MHz.
Received Data: The LAN Connect component uses these signals to
transfer data and control information to the integrated LAN
Controller. These signals have integrated weak pull-up resistors.
Transmit Data: The integrated LAN Controller uses these signals
to transfer data and control information to the LAN Connect
component.
LAN Reset/Sync: The LAN Connect component’s Reset and Sync
signals are multiplexed onto this pin.
EEPROM Interface Signals
Signal Name
Type
Description
EE_SHCLK
O
EEPROM Shift Clock: Serial shift clock output to the EEPROM.
EE_DIN
I
EE_DOUT
O
EE_CS
O
EEPROM Data In: Transfers data from the EEPROM to the ICH3.
This signal has an integrated pull-up resistor.
EEPROM Data Out: Transfers data from the ICH3 to the
EEPROM.
EEPROM Chip Select: Chip select signal to the EEPROM.
Description
I/O
95
PCI Interface Signals (Continue)
Signal Name
FRAME#
IRDY#
TRDY#
PAR
Type
Description
I/O
Cycle Frame: The current Initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the Initiator
asserts FRAME#, data transfers continue. When the Initiator
negates FRAME#, the transaction is in the final data phase.
FRAME# is an input to the ICH4 when the ICH4 is the Target, and
FRAME# is an output from the ICH4 when the ICH4 is the Initiator.
FRAME# remains tri- stated by the ICH4 until driven by an
Initiator.
Initiator Ready: IRDY# indicates the ICH4's ability, as an
Initiator, to complete the current data phase of the transaction. It is
used in conjunction with TRDY#. A data phase is completed on any
clock that both IRDY# and TRDY# are sampled asserted. During a
write, IRDY# indicates the ICH4 has valid data present on
AD[31:0]. During a read, it indicates the ICH4 is prepared to latch
data. IRDY# is an input to the ICH4 when the ICH4 is the Target
and an output from the ICH4 when the ICH4 is an Initiator. IRDY#
remains tri-stated by the ICH4 until driven by an Initiator.
Target Ready: TRDY# indicates the ICH4's ability, as a Target, to
complete the current data phase of the transaction. TRDY# is used
in conjunction with IRDY#. A data phase is completed when both
TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH4, as a Target, has
placed valid data on AD[31:0]. During a write, TRDY# indicates
that the ICH4, as a Target, is prepared to latch data. TRDY# is an
input to the ICH4 when the ICH4 is the Initiator and an output from
the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the
leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4
until driven by a target.
Calculated/Checked Parity: PAR uses “even” parity calculated on
36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the
ICH4 counts the number of 1s within the 36 bits plus PAR and the
sum is always even. The ICH4 always calculates PAR on 36 bits
regardless of the valid byte enables. The ICH4 generates PAR for
address and data phases and only guarantees PAR to be valid one
PCI clock after the corresponding address or data phase. The ICH4
drives and tri-states PAR identically to the AD[31:0] lines except
that the ICH4 delays PAR by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all ICH4
initiated transactions. PAR is an output during the data phase
(delayed one clock) when the ICH4 is the Initiator of a PCI write
transaction, and when it is the Target of a read transaction. ICH4
checks parity when it is the Target of a PCI write transaction. If a
parity error is detected, the ICH4 will set the appropriate internal
status bits, and has the option to generate an NMI# or SMI#.
I/O
I/O
I/O
Type
Description
STOP#
Signal Name
I/O
PERR#
I/O
Stop: STOP# indicates that the ICH4, as a Target, is requesting the
Initiator to stop the current transaction. STOP# causes the ICH4, as
an Initiator, to stop the current transaction. STOP# is an output
when the ICH4 is a Target and an input when the ICH4 is an
Initiator. STOP# is tri-stated from the leading edge of PCIRST#.
STOP# remains tri-stated until driven by the ICH4.
Parity Error: An external PCI device drives PERR# when it
receives data that has a parity error. The ICH4 drives PERR# when
it detects a parity error. The ICH4 can either generate an NMI# or
SMI# upon detecting a parity error (either detected internally or
reported via the PERR# signal).
PCI Requests: The ICH4 supports up to 6 masters on the PCI bus.
REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the
other, but not both). If not used for PCI or PC/PCI,
REQ[5]#/REQ[B]# can instead be used as GPIO[1].
NOTE: REQ[0]# is programmable to have improved arbitration
latency for for supporting PCI-based 1394 controllers.
PCI Grants: The ICH4 supports up to 6 masters on the PCI bus.
GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the
other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can
instead be used as a GPIO.
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for
all transactions on the PCI Bus.
NOTE: This clock does not stop based on STP_PCI# signal.
PCICLK only stops based on SLP_S1# or SLP_S3#.
PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on
the PCI bus. The ICH4 asserts PCIRST# during power-up and when
S/W initiates a hard reset sequence through the RC (CF9h) register.
The ICH4 drives PCIRST# inactive a minimum of 1 ms after
PWROK is driven active. The ICH4 drives PCIRST# active
a minimum of 1 ms when initiated through the RC register.
PCI Lock: This signal indicates an exclusive bus operation and
may require multiple transactions to complete. ICH4 asserts
PLOCK# when it performs non- exclusive transactions on the PCI
bus. Devices on the PCI bus (other than the ICH4) are not permitted
to assert the PLOCK# signal.
System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
ICH4 has the ability to generate an NMI, SMI#, or interrupt.
REQ[4:0]#
REQ[5]#/
REQ[B]#/
GPIO[1]
I
GNT[4:0]#
GNT[5]#/
GNT[B]#/
GPIO[17]
O
PCICLK
I
PCIRST#
O
PLOCK#
I/O
SERR#
96
I/OD
Signal Name
PME#
IDE Interface Signals (Continue)
Type
Description
I/OD
PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1-M–S5. PME# assertion
can also be enabled to generate an SCI from the S0 state. In some
cases the ICH4 may drive PME# active due to an internal wake
event. The ICH4 will not drive PME# high, but it will be pulled up
to VccSus3_3 by an internal pull-up resistor.
PCI Clock Run: Used to support PCI Clock Run protocol.
Connects to PCI devices that need to request clock re-start, or
prevention of clock stopping.
NOTE: An external pull-up to the core power plane is required.
PC/PCI DMA Request [A:B]: This request serializes ISA-like
DMA Requests for the purpose of running ISA-compatible DMA
cycles over the PCI bus. This is used by devices such as PCI based
Super I/O or audio codecs which need to perform legacy 8237 DMA
but have no ISA bus.
When not used for PC/PCI requests, these signals can be used as
General Purpose Inputs. REQ[B]# can instead be used as the 6th
PCI bus request.
PC/PCI DMA Acknowledges [A: B]: This grant serializes an
ISA-like DACK# for the purpose of running DMA/ISA Master
cycles over the PCI bus. This is used by devices such as PCI based
Super/IO or audio codecs which need to perform legacy 8237 DMA
but have no ISA bus.
When not used for PC/PCI, these signals can be used as General
Purpose Outputs. GNTB# can also be used as the 6th PCI bus
master grant output. These signal have internal pull-up resistors.
CLKRUN#
I/O
REQ[A]#/
GPIO[0]
REQ[B]#/
REQ[5]#/
GPIO[1]
I
GNT[A]#/
GPIO[16]
GNT[B]#/
GNT[5]#/
GPIO[17]
O
Type
Description
PDD[15:0],
SDD[15:0]
Signal Name
I/O
PDDREQ,
SDDREQ
I
PDDACK#,
SDDACK#
O
PDIOR#/
(PDWSTB/PRDMA
RDY#)
O
Primary and Secondary IDE Device Data: These signals directly
drive the corresponding signals on the primary or secondary IDE
connector. There is a weak internal pull-down resistor on PDD[7]
and SDD[7].
Primary and Secondary IDE Device DMA Request: These input
signals are directly driven from the DRQ signals on the primary or
secondary IDE connector. It is asserted by the IDE device to request
a data transfer, and used in conjunction with the PCI bus master IDE
function and are not associated with any AT compatible DMA
channel. There is a weak internal pull-down resistor on these
signals.
Primary and Secondary IDE Device DMA Acknowledge: These
signals directly drive the DAK# signals on the primary and
secondary IDE connectors. Each is asserted by the ICH4 to indicate
to IDE DMA slave devices that a given data transfer cycle (assertion
of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is
used in conjunction with the PCI bus master IDE function and are
not associated with any AT-compatible DMA channel.
Primary and Secondary Disk I/O Read (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may drive
data onto the PDD or SDD lines. Data is latched by the ICH4 on the
deassertion edge of PDIOR# or SDIOR#. The IDE device is
selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing
to disk, ICH4 drives valid data on rising and falling edges of
PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready
(Ultra DMA Reads from Disk): This is the DMA ready for reads
from disk. When reading from disk, ICH4 deasserts
PRDMARDY# or SRDMARDY# to pause burst data transfers.
Primary and Secondary Disk I/O Write (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may latch
data from the PDD or SDD lines. Data is latched by the IDE device
on the deassertion edge of PDIOW# or SDIOW#. The IDE device is
selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this
signal to terminate a burst.
SDIOR#/
(SDWSTB/SRDMA
RDY#)
IDE Interface Signals
Signal Name
Type
Description
PDCS1#, SDCS1#
O
Primary and Secondary IDE Device Chip Selects for 100 Range:
For ATA command register block. This output signal is connected
to the corresponding signal on the primary or secondary IDE
connector.
Primary and Secondary IDE Device Chip Select for 300 Range:
For ATA control register block. This output signal is connected to
the corresponding signal on the primary or secondary IDE
connector.
Primary and Secondary IDE Device Address: These output
signals are connected to the corresponding signals on the primary or
secondary IDE connectors. They are used to indicate which byte in
either the ATA command block or control block is being addressed.
PDCS3#, SDCS3#
PDA[2:0],
SDA[2:0]
O
O
PDIOW#/
(PDSTOP)
SDIOW#/
(SDSTOP)
97
O
IDE Interface Signals (Continue)
LPC Interface Signals
Signal Name
Type
Description
PIORDY#/
(PDRSTB/PWDMA
RDY#)
I
Primary and Secondary I/O Channel Ready (PIO): This signal
will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW#
or SDIOW# on writes) longer than the minimum width. It adds wait
states to PIO transfers.
Primary and Secondary Disk Read Strobe (Ultra DMA Reads from
Disk): When reading from disk, the ICH4 latches data on rising and
falling edges of this signal from the disk.
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to
Disk): When writing to disk, this is de-asserted by the disk to pause
burst data transfers.
SIORDY#/
(SDRSTB/SWDMA
RDY#)
Signal Name
LAD[3:0]/
FWH[3:0]
LFRAME#/
FWH[4]
LDRQ[1:0]#
Type
I/O
O
I
Description
LPC Multiplexed Command, Address, Data: For the LAD[3:0]
signals, internal pull-ups are provided.
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an
abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used
to request DMA or bus master access. These signals are typically
connected to an external Super I/O device. An internal pull-up
resistor is provided on these signals.
USB Interface Signals
Signal Name
Interrupt Signals
Signal Name
SERIRQ
PIRQ[D:A]#
PIRQ[H:E]#/
GPIO[5:2]
Type
Description
I/O
Serial Interrupt Request: This pin implements the serial interrupt
protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fashion: PIRQ[A]# is connected to IRQ16,
PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19.
This frees the legacy interrupts.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fashion: PIRQ[E]# is connected to IRQ20,
PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23.
This frees the legacy interrupts. If not needed for interrupts, these
signals can be used as GPIO.
Interrupt Request 14:15: These interrupt inputs are connected to
the IDE drives. IRQ14 is used by the drives connected to the
Primary controller and IRQ15 is used by the drives connected to the
Secondary controller.
APIC Clock: This clock operates up to 33.33 MHz.
I/OD
I/OD
IRQ[14:15]
I
APICCLK
I
APICD[1:0]
I/OD
APIC Data: These bi-directional open drain signals are used to
send and receive data over the APIC bus. As inputs the data is valid
on the rising edge of APICCLK. As outputs, new data is driven
from the rising edge of the APICCLK.
98
Type
Description
USBP0P,
USBP0N,
USBP1P,
USBP1N
I/O
USBP2P,
USBP2N,
USBP3P,
USBP3N
I/O
USBP4P,
USBP4N,
USBP5P,
USBP4N
I/O
OC[5:0]#
I/O
USBRBIAS
O
USBRBIAS#
I
Universal Serial Bus Port 1:0 Differential: These differential
pairs are used to transmit data/address/command signals for ports 0
and 1. These ports can be routed to USB UHCI Controller #1 or the
USB EHCI Controller.
NOTE: No external resistors are required on these signals. The
ICH4 integrates 15 k . pull-downs and provides an output driver
impedance of 45 . which requires no external series resistor
USB EHCI Controller.
impedance of 45 . which requires no external series resistor.
USB EHCI Controller
impedance of 45 . which requires no external series resistor
Overcurrent Indicators: These signals set corresponding bits in
the USB controllers to indicate that an overcurrent condition has
occurred.
USB Resistor Bias: Analog connection point for an external
resistor to ground. USBRBIAS should be connected to
USBRBIAS# as close to the resistor as possible.
USB Resistor Bias Complement: Analog connection point for an
external resistor to ground. USBRBIAS# should be connected to
USBRBIAS as close to the resistor as possible.
Power Management Interface Signals Continue
Power Management Interface Signals
Signal Name
Type
Description
THRM#
I
THRMTRIP#
I
Thermal Alarm: This is an active low signal generated by external
hardware to start the hardware clock throttling mode. The signal can
also generate an SMI# or an SCI.
Thermal Trip: When low, THRMTRIP# indicates that a thermal
trip from the processor occurred; the ICH4 will immediately
transition to a S5 state. The ICH4 will not wait for the processor
stop grant cycle since the processor has overheated.
S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power
plane control. Optional use is to shut off power to non-critical
systems when in the S1- M (Powered On Suspend), S3 (Suspend To
RAM), S4 (Suspend to Disk) or S5 (Soft Off) states.
S3 Sleep Control: SLP_S3# is for power plane control. It shuts off
power to all non-critical systems when in S3 (Suspend To RAM),
S4 (Suspend to Disk), or S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. It shuts
power to all non-critical systems when in the S4 (Suspend to Disk)
or S5 (Soft Off) state.
S5 Sleep Control: SLP_S5# is for power plane control. The signal
is used to shut power off to all non-critical systems when in the S5
(Soft Off) states.
Power OK: When asserted, PWROK is an indication to the ICH4
that core power and PCICLK have been stable for at least 1 ms.
PWROK can be driven asynchronously. When PWROK is negated,
the ICH4 asserts PCIRST#.
NOTE: PWROK must deassert for a minimum of 3 RTC clock
periods for the ICH4 to fully reset the power and properly generate
the PCIRST# output
Power Button: The Power Button causes SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal causes a wake event. If PWRBTN# is pressed
for more than 4 seconds, this causes an unconditional transition
(power button override) to the S5 state with only the PWRBTN#
available as a wake event. Override occurs even if the system is in
the S1-M–S4 states. This signal has an internal pull-up resistor.
Ring Indicate: This signal is an input from the modem interface. It
can be enabled as a wake event, and this is preserved across power
failures.
System Reset: This pin forces an internal reset after being
debounced. The ICH4 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle
before forcing a reset on the system.
Resume Well Reset: This signal is used for resetting the resume
power plane logic.
SLP_S1#
O
SLP_S3#
O
SLP_S4#
O
SLP_S5#
O
PWROK
PWRBTN#
I
I
RI#
I
SYS_RESET#
I
RSMRST#
I
Signal Name
99
Type
Description
LAN_RST#
I
SUS_STAT#/
LPCPD#
O
C3_STAT#
O
SUSCLK
O
AGPBUSY#
I
STP_PCI#
O
STP_CPU#
O
BATLOW#
I
CPUPERF#
OD
SSMUXSEL
O
VGATE/
VRMPWRGD
I
LAN Reset: This signal must be asserted at least 10 ms after the
resume well power (VccLAN3_3 and VccLAN1_5 is valid. When
deasserted, this signal is an indication that the resume well power is
stable.
Suspend Status: This signal is asserted by the ICH4 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs
that may be going to powered-off planes. This signal is called
LPCPD# on the LPC I/F.
C3_STAT#: This signal will typically be configured as C3_STAT#.
It is used for indicating to an AGP device that a C3 state transition
is beginning or ending. If C3_STAT# functionality is not required,
this signal may be used as a GPO.
NOTE: This signal will be asserted in S1-M on the ICH4-M.
Suspend Clock: Output of the RTC generator circuit to use by other
chips for refresh clock.
AGP Bus Busy: To support the C3 state. This signal is an
indication that the AGP device is busy. When this signal is asserted,
the BM_STS bit will be set. If this functionality is not needed, this
signal may be configured as a GPI.
Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock. Used to support PCI
CLKRUN# protocol. If this functionality is not needed, This signal
can be configured as a GPO.
Stop CPU Clock: Output to the external clock generator for it to
turn off the processor clock. Used to support the C3 state. If this
functionality is not needed, this signal can be configured as a GPO.
Battery Low: This signal is an input from the battery to indicate
that there is insufficient power to boot the system. Assertion will
prevent wake from S1-M–S5 state. Can also be enabled to cause an
SMI# when asserted.
CPU Performance: CPUPERF# is used for Intel SpeedStep
technology support. The signal selects which power state to put the
processor in.
SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep
technology support. The signal selects the voltage level for the
processor.
VGATE/VRM Power Good: VGATE/VRMPWRGD is used for
Intel SpeedStep technology support. This is an output from the
processor’s voltage regulator to indicate that the voltage is stable.
This signal may go inactive during an Intel SpeedStep transition.
Power Management Interface Signals (Continue)
Signal Name
DPRSLPVR
Type
Description
O
Deeper Sleep - Voltage Regulator: This signal is used to lower the
voltage of VRM during C4 and S1-M states. When the signal is
high, the voltage regulator outputs the lower “Deeper Sleep”
voltage. When the signal is low (default), the voltage regulator
outputs the higher “Normal” voltage. During PCIRST#, the output
driver is disabled and an internal pull-down is enabled. This is
needed for implementing a strap on the pin. When PCIRST#
deasserts, the output driver is enabled. To guarantee no glitches on
the DPRSLPVR pin, the pull-down is disabled after the output
driver is fully enabled.
NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a
functional strap.
Processor Interface Signals (Continue)
Signal Name
Processor Interface Signals
Signal Name
Type
Description
A20M#
O
CPUSLP#
O
FERR#
I
Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE
input being active.
Speed Strap: During the reset sequence, ICH4 drives A20M# high
if the corresponding bit is set in the FREQ_STRP register.
CPU Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during
that time, no snoops occur. The ICH4 can optionally assert the
CPUSLP# signal when going to the S1-M state.
Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the ICH4
coprocessor error reporting function is enabled in the General
Control Register (Device 31:Function 0, Offset D0, bit 13). If
FERR# is asserted, the ICH4 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the processor unless FERR#
is active. FERR# requires an external weak pull-up to ensure a high
level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the General Control Register bit setting.
CPU Interrupt: INTR is asserted by the ICH4 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Speed Strap: During the reset sequence, ICH4 drives INTR high if
the corresponding bit is set in the FREQ_STRP register.
INTR
O
100
Type
Description
IGNNE#
O
INIT#
O
NMI
O
SMI#
O
STPCLK#
O
RCIN#
I
A20GATE
I
Ignore Numeric Error: This signal is connected to the ignore error
pin on the processor. IGNNE# is only used if the ICH4 coprocessor
error reporting function is enabled in the General Control Register
(Device 31:Function 0, Offset D0, bit 13). If FERR# is active,
indicating a coprocessor error, a write to the Coprocessor Error
Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains
asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not
asserted.
Speed Strap: During the reset sequence, ICH4 drives IGNNE# high
if the corresponding bit is set in the FREQ_STRP register.
Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to
reset the processor. ICH4 can be configured to support CPU BIST.
In that case, INIT# will be active when PCIRST# is active.
Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The ICH4 can generate an NMI when
either SERR# or IOCHK# is asserted. The processor detects an NMI
when it detects a rising edge on NMI.
NMI is reset by setting the corresponding NMI source
enable/disable bit in the NMI Status and Control Register.
Speed Strap: During the reset sequence, ICH4 drives NMI high if
the corresponding bit is set in the FREQ_STRP register.
System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH4 in response to
one of many enabled hardware or software events.
Stop Clock Request: STPCLK# is an active low output
synchronous to PCICLK. It is asserted by the ICH4 in response to
one of many hardware or software events. When the processor
samples STPCLK# asserted, it responds by stopping its internal
clock.
Keyboard Controller Reset CPU: The keyboard controller can
generate INIT# to the processor. This saves the external OR gate
with the ICH4’s other sources of INIT#. When the ICH4 detects the
assertion of this signal, INIT# is generated for 16 PCI clocks.
NOTE: The ICH4 ignores RCIN# assertion during transitions to the
S1-M, S3, S4 and S5 states.
A20 Gate: A20GATE is from the keyboard controller. The signal
acts as an alternative method to force the A20M# signal active. It
saves the external OR gate needed with various other PCIsets.
Processor Interface Signals (Continued)
Signal Name
CPUPWRGD
DPSLP#
Real Time Clock Interface Signals
Type
Description
OD
CPU Power Good: This signal should be connected to the
processor’s PWRGOOD input. To allow for Intel ® SpeedStep™
technology support, this signal is kept high during an Intel
SpeedStep technology state transition to prevent loss of processor
context. This is an open-drain output signal (external pull-up
resistor required) that represents a logical AND of the ICH4’s
PWROK and VGATE / VRMPWRGD signals.
Deeper Sleep: This signal is asserted by the ICH4 to the processor.
When the signal is low, the processor enters the Deeper Sleep state
by gating off the processor Core clock inside the processor. When
the signal is high (default), the processor is not in the Deeper Sleep
state. This signal behaves identically to the STP_CPU# signal, but
at the processor voltage level.
O
Signal Name
Type
I/OD
SMBus Data: External pull-up is required.
SMBCLK
I/OD
SMBus Clock: External pull-up is required.
SMBALERT#/
GPIO[11]
I
RTCX2
Special
Crystal Input 2: This signal is connected to the 32.768 kHz crystal.
Type
Description
CLK14
I
CLK48
I
CLK66
I
Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz.
This clock is permitted to stop during S1-M (or lower) states.
48 MHz Clock: This clock is used to run the USB controller. It runs
at 48 MHz. This clock is permitted to stop during S1-M (or lower)
states.
66 MHz Clock: This is used to run the hub interface. It runs at 66
MHz. This clock is permitted to stop during S1-M (or lower) states.
Miscellaneous Signals
Signal Name
Type
Description
SPKR
O
RTCRST#
I
Speaker: The SPKR signal is the output of counter 2 and is
internally “ANDed” with Port 61h bit 1 to provide Speaker Data
Enable. This signal drives an external speaker driver device, which
in turn drives the system speaker. Upon PCIRST#, its output state is
0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap.
RTC Reset: When asserted, this signal resets register bits in the
RTC well and sets the RTC_PWR_STS bit (bit 2 in
GEN_PMCON3 register).
NOTES:
1. Clearing CMOS in an ICH4-based platform can be done by using
a jumper on RTCRST# or GPI, or using SAFEMODE strap.
Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
2. Unless entering the XOR Chain Test Mode, the RTCRST# input
must always be high when all other RTC power planes are on.
SMBus Alert: This signal is used to wake the system or generate
SMI#. If not used for SMBALERT#, it can be used as a GPI.
System Management Interface Signals
Signal Name
Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
Signal Name
Description
SMBDATA
Description
Special
Other Clock Signals
SMBus Interface Signals
Signal Name
Type
RTCX1
Type
Description
INTRUDER#
I
SMLINK[1:0]
I/OD
Intruder Detect: Can be set to disable system if box detected open.
This signal’s status is readable, so it can be used like a GPI if the
Intruder Detection is not needed.
System Management Link: SMBus link to optional external
system management ASIC or LAN controller. External pull-ups are
required.
Note that SMLINK[0] corresponds to an SMBus Clock signal, and
SMLINK[1] corresponds to an SMBus Data signal.
101
Power and Ground Signals
AC’97 Link Signals
Signal Name
Type
Signal Name
Description
AC ’97 Reset: This signal is a master hardware reset to external
Codec(s).
O
AC ’97 Sync: This signal is a 48 kHz fixed rate sample sync to the
AC_SYNC
Codec(s).
I
AC97 Bit Clock: This signal is a 12.288 MHz serial data clock
AC_BIT_CLK
generated by the external Codec(s). This signal has an integrated
pull-down resistor.
O
AC97 Serial Data Out: Serial TDM data output to the Codec(s).
AC_SDOUT
NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a
functional strap.
I
AC97 Serial Data In 2:0: These signals are Serial TDM data inputs
AC_SDIN[1:0]
from the three Codecs.
NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK
Shutoff bit in the AC’97 Global Control Register is set to 1, or Both Function 5 and Function 6 of
Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled.
AC_RST#
O
VCC3_3
VCC1_5
VCCHI
V5REF
HIREF
VCCSUS3_3
VCCSUS1_5
General Purpose I/O Signals
Signal Name
GPIO[43:32]
GPIO[31:29]
GPIO[28:27]
GPIO[26]
GPIO[25]
GPIO[24:18]
Type
I/O
O
I/O
I/O
I/O
I/O
Description
Fixed as Output only. Main power well. Can be used instead as
PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for
PCI GNT[5]#. Integrated pull-up resistor.
I
Not implemented.
GPIO[15:14]
I
Fixed as Input only. Resume power well. Unmuxed.
GPIO[13:12]
I
Fixed as Input only. Resume power well. Can be used instead as
GPIO[11]
SMBALERT#.
I
Not implemented.
GPIO[10:9]
I
Fixed as Input only. Resume power well. Unmuxed.
GPIO[8]
I
Fixed as Input only. Main power well. Unmuxed.
GPIO[7]
I
Not Implemented in Mobile (Assign to Native Functionality)
GPIO[6]
I
Fixed as Input only. Main power well. Can be used instead as
GPIO[5:2]
PIRQ[E:H]#.
I
Fixed as Input only. Main power well. Can be used instead as
GPIO[1:0]
PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI
REQ[5]#.
NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO
are not 5V tolerant.
GPIO[17:16]
V5REF_SUS
Can be input or output. Main power well.
Not implemented.
Can be input or output. Resume power well. Unmuxed.
Not implemented.
Can be input or output. Resume power well. Unmuxed.
Not Implemented in Mobile (Assign to native Functionality).
VCCLAN3_3
O
VCCLAN1_5
VCCRTC
VCCPLL
VBIAS
V_CPU_IO
VSS
102
Description
3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5
or G3 states.
1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3
states.
1.5 V supply for Hub Interface 1.5 logic.
1.8 V supply for Hub Interface 1.0 logic.
This power may be shut off in S3, S4, S5 or G3 states.
Reference for 5 V tolerance on core well inputs. This power may be shut off in
S3, S4, S5 or G3 states.
Analog Input. Expected voltages are:
• 0.9 V for HI 1.0 (Normal Hub Interface) Series Termination
• 350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination
This power is shut off in S3, S4, S5, and G3 states.
3.3 V supply for resume well I/O buffers. This power is not expected to be shut
off unless the main battery is removed or completely drained and AC power is
not available.
1.5 V supply for resume well logic. This power is not expected to be shut off
unless the main battery is removed or completely drained and AC power is not
available.
Reference for 5 V tolerance on resume well inputs. This power is not expected
to be shut off unless the main battery is removed or completely drained and AC
power is not available.
3.3 V supply for LAN Connect interface buffers. This is a separate power plane
that may or may not be powered in S3–S5 states depending upon the presence or
absence of AC power and network connectivity. This plane must be on in S0 and
S1-M.
1.5 V supply for LAN Controller logic. This is a separate power plane that may
or may not be powered in S3–S5 states depending upon the presence or absence
of AC power and network connectivity. This plane must be on in S0 and S1-M.
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power
is not expected to be shut off unless the RTC battery is removed or completely
drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper
to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done
by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
1.5 V supply for core well logic. This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states.
RTC well bias voltage. The DC reference voltage applied to this pin sets a
current that is mirrored throughout the oscillator and buffer circuitry.
Powered by the same supply as the processor I/O voltage. This supply is used to
drive the processor interface outputs.
Grounds.
6. System Block Diagram
U506
LVDS
TFT Flat Panel
J504
MINI PCI
TV S-Video
Micro-FCPGA
RGB
CRT Connector
U502
Thermal Sensor
ADT7460
Intel Banais Processor
U508
Clock Generator
PLL207-151
U5
CH7011A
DVOC
U504
Memory Controller
Hub
Montara - GME
PCI Bus
200/266/333MHz
200 pin DDR SO-DIMM Socket * 2
Hub Link
External Microphone
Internal Microphone
USB * 4
U510
HDD
CardBus
PCI1410A
U513
Power Switch
TPS2211A
DVD-ROM
U511
Ethernet Controller
VT6105-L
U12
P-IDE
S-IDE
AC Link
U519
AC'97 Codec
I/O Controller Hub
ALC101
U520
Amplifier
TPA0212A
Internal Speaker
SPDIF Jack
ICH4 - M
J515
M.D.C
LPC
FWH
System BIOS
RJ-11 Jack
FAN
U7
Power Button
Embedded Controller
RJ-45 Jack
Winbond W83L950D
PCMCIA
Slot
Touch Pad
Keyboard
103
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This poweron self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can
alert you to the problems of your computer.
If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs
before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are
used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI
PCI slot.
104
7.2 Maintenance Diagnostics
7.2.1 Diagnostic Tool for Mini PCI Slot :
P/N:411906900001
Description: PWA; PWA-MPDOG/MINI PCI DOGKILLER CARD
Note: Order it from MIC/TSSC
105
7.3 Error Codes
Following is a list of error codes in sequent display on the PIO debug board.
Code
POST Routine Description
Code
10h
Some type of lone reset
20h
Test keyboard
11h
Turn off FAST A20 for POST
21h
Test keyboard controller
12h
Signal power on reset
22h
Check if CMOS RAM valid
13h
Initialize the chipset
23h
Test battery fail & CMOS X-SUM
14h
Search for ISA Bus VGA adapter
24h
Test the DMA controller
15h
Reset counter / Timer 1
25h
Initialize 8237A controller
16h
User register config through CMOS
26h
Initialize int vectors
17h
Size memory
27h
RAM quick sizing
18h
Dispatch to RAM test
28h
Protected mode entered safely
19h
Check sum the ROM
29h
RAM test completed
1Ah
Reset PIC’s
2Ah
Protected mode exit successful
1Bh
Initialize video adapter(s)
2Bh
Setup shadow
1Ch
Initialize video (6845Regs)
2Ch
Going to initialize video
1Dh
Initialize color adapter
2Dh
Search for monochrome adapter
1Eh
Initialize monochrome adapter
2Eh
Search for color adapter
1Fh
Test 8237A page registers
2Fh
Sign on messages displayed
106
7.3 Error Codes
Following is a list of error codes in sequent display on the PIO debug board.
Code
Code
30h
Special init of keyboard ctlr
40h
Configure the COMM and LPT ports
31h
Test if keyboard Present
41h
Initialize the floppies
32h
Test keyboard Interrupt
42h
Initialize the hard disk
33h
Test keyboard command byte
43h
Initialize option ROMs
34h
Test, blank and count all RAM
44h
OEM’s init of power management
35h
Protected mode entered safely(2)
45h
Update NUMLOCK status
36h
RAM test complete
46h
Test for coprocessor installed
37h
Protected mode exit successful
47h
OEM functions before boot
38h
Update output port
48h
Dispatch to operate system boot
39h
Setup cache controller
49h
Jump into bootstrap code
3Ah
Test if 18.2Hz periodic working
50h
ACPI init
3Bh
Test for RTC ticking
51h
PM init & Geyserville
3Ch
Initialize the hardware vectors
52h
USB HC init
3Dh
Search and init the mouse
3Eh
Update NUMLOCK status
3Fh
Special init of COMM and LPT ports
107
8. Trouble Shooting
8.1 No Power
8.2 No Display
8.3 VGA Controller Failure LCD No Display
8.4 External Monitor No Display
8.5 Memory Test Error
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error
8.7 Hard Driver Test Error
8.8 CD-ROM Driver Test Error
8.9 USB Port Test Error
8.10 Audio Failure
8.11 LAN Test Error
8.12 PC Card Socket Failure
8.13 TV Test Error
108
8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
No Power
Is the
notebook connected
to power (either AC adaptor
or battery)?
Check following parts and signals:
No
Connect AC adaptor
or battery.
Parts:
Yes
Try another known good
battery or AC adapter.
Power
OK?
Yes
Board-level
Troubleshooting
Replace the faulty AC
adaptor or battery.
Where from
power source problem
(first use AC to
power it)?
AC
Power
PJ501
PF2
PL2
PL3
PR24
PQ5
PD4
PD5
PD7
Signals:
ADINP
DVMAIN
PWR_VDDIN
No
Is the
M/B and charger
BD connected
properly?
Yes
Check following parts and signals:
Connect AC adaptor
or battery.
Parts:
No
Try another known
good charger BD.
Power
OK?
No
Battery
Replace
Motherboard
Yes
Replace the faulty
Charger BD.
109
PD503
PL501
PQ504
PU1
PL1
PL8
PF1
PQ502
PQ501
Signals:
BATT
BAT_TEMP
BAT_VOLT
BAT_CLK
BAT_DATA
8.1 No Power
Main Voltage Map
P29
DD_CPU
PD509,PL508,PU5
PQ6,PL506,PU505
PF1,PL2,PL3
P24
BATT
Charge
PL505,PL507
PF1,PL2
PL3,PQ5,PQ4
PU4,PU507,PU506
PU510,PU509
PL509,PR520
P29
+VCC_CORE
PF501,PL501
PL502,PR502
P23
PQ501
POWER IN
P26
PL4,PU3
DVMAIN
P22
+1.8V
PL1,PU2
PU502,PL503
PR508
PD503
+3V_P
+3V
F2,U10
U1,JO11,JO12
AVDDAD
PU503,PU504
PL504,PR509
P22
JO74
JO75
P28
+5V_PP
H8_AVREF
P22
VDD3
P22
F3,U3
U513
P21
+VCC_USB_2,+VCC_USB_4
P25
PU7
+1.35V_P
P20
DVMAIN_INV
P22
+5V_P
Q11
P22
VDD5
U4
P22
SVDD3
R209,D511
+KBC_VDD
PU11,PU12
PL511,PR522
P18
R851
+KBC_VDDA
L534
JO521
JO517
P27
+2.5V_DDR_P
P22
+2.5V_DDR
L536
NOTE :
PU10
P24 : Page 24 on M/B Board circuit diagram.
PL6,PU13
PU9
PL510,PR81
110
P27
+1.05V_P
JO53
JO52
P22
+VCCP
L21
P3
+VCCQ
JO17
JO18
JO16
P22
+1.35V
P22
+1.5V
P15
+LAN_D2.5V
P15
+LAN_A2.5V
R134 R135
C233 C192
PF2 : Through by part PF2.
+1.5V_P
+VCC_RTC
P18
R850
P25
PU6
PL5
P9
P17
+CARD_VCC
+VCC_USB_1,+VCC_USB_3
PU14
VDD1.5
P22
+5V
P17
+VPPOUT
P21
R585,U521
R574,U522
+5V_P
P22
U16
+3VCLKPCI
U513
P12
P4
+3VCLKANA
P4
L27
P22
Q524
R800,JS507
Q16
+3VCLKCPU
+VCCA
+LAN_D3V
U501
JO506,JO505
P28
PWR_VDDIN
Q14
P4
L26
P3
L18
L532
PD501
Discharge
P4
+3VCLK66
P15
R694
P23
JO15
+1.8V_P
P23
PJ501
P14
+3V_LCDVCC
+VCC_CORE_KBC
L25
PD504
ADINP
+3V_KBC
F1,PU1,
L2
P18
R844
Discharge
P23
P18
R76
P7
+DDR_REF
P26
+1.25V_DDR_P
JO54
P22
+1.25V_DDR
8.1 No Power
PL501
120Z/100M
PJ501 P23
PF501
7A/24VDC
PR502
.02
PC505
1µ
PC506
0.1µ
PD502
RLZ24D
PR503
470K
3
PR501
10
I_LIMIT
76
4
6
P18
23
U7
P23
VCC
RS+
RSPJO501
OPEN-SMT4
OUT MAX4173FEUT
PC503
0.1µ
DVMAIN
PL1
120Z/100M
PR507
1M
23
VDD5
Controller
SUSC#
P9
PQ2
2N7002
13
From ICH4
DVMAIN
8
INPUT
P22
OUTPUT
H8_AVREF
1
D
PC72
10µ
VDD5
S
Q11
SI2301DS
S
C96
4.7µ
28
D
SUSB#
SW_VDD5
PWR_VDDIN H8_AVREF VDD5
5V_P
VDD5
23
VDD5
PR87
100K
R63
100K
PL6
120Z/100M
+5V_P
G
D3
RLZ5.6B
Q14
SI2301DS
G
U10
AMS3107
Q12
DTC144WK
+5V_P
P9
13
PQ504
2N7002
PR85
100K
SUSC#
PR525
1M
P9
P27
RUN/SS1
PQ15
2N7002
+1.05V_P
RUN/SS2
LTC3728L
+2.5V_DDR_P
PQ16
2N7002
From ICH4
PR86
1M
111
VIN
PU13
VDD5
PQ505
2N7002
From ICH4
RUN/SS2
DVMAIN +3V_P ,+5V_P
PR5
1M
F2
FUSE_1206
PU2
PQ3
2N7002
SW_VDD5
PWR_VDDIN
+3V_P
LTCC3728L
W83l950D
26
P28
PQ1
2N7002
PQ11
DTC144WK
ADEN#
VIN
28 RUN/SS1
PR2
100K
14
PC4
1000P
PU501
LEARNING
Embedded
PC3
0.1µ
PR55
226K
PQ502
2N7002
PC501
1µ
PWR_VDDIN
DVMAIN
PR505
4.7K
PR506
4.7K
PR504
100K
5
PC502
0.1µ
3
1
PD504
SBM1040
1,2
3
8
7
6
5
3
2
1
G
JO501,JO502
SPARKGAP_6
PD501
BAV70LT1
ADINP
PQ501
AO4407
S
3,4
2
JO1
OPEN-SMT4
PL502
120Z/100M
1
POWER IN
2
Mother Board
D
Main Voltage
DVMAIN +1.05V_P ,+2.5V_DDR_P
8.1 No Power
PR25
0
VCC_CORE
PR26
0
REF_CORE
PR24
0
PC21
0.22µ
PR11
PR28
0
SUSB#
10
GND_A
GND
PC43
0.1µ
D
PD511
EC31QS04
-TE12L
G
VID[0:5]
PR65
PR66
PR67
PR70
PR68
PR71
0
0
0
0
0
0
PR60
0
S
PD510
EC31QS04
-TE12L
3
2
1
From CPU
VID5
VID4
VID3
VID2
VID1
VID0
PC78, PC73
PC537, PC536
PC71,PC68
220µ
PC48
4700P
8
7
6
5
S
PC50
10µ
PR61
200
PU509
FDS7788
G
+5V_P
PR520
.001
PR57
200
D
3
2
1
PR31
56.2K
+VCC_CORE
PL509
0.68µH
8
7
6
5
GND_A
PR39
1M
PU506
AO4406
S
PU510
FDS7788
GND
GND
D
G
PD4
EC10QS04
21
22
23
24
25
26
27
28
29
30
MAX1907
S
PC42
0.1µ
3
2
1
PU4
PR32
0
PC52
0.1µ
JS1
SHORT-SMT1
PR36
PR41
PR46
PR49
0
0
0
0
CSP+
CSN-
GND_A
PR54
510
GND_A
PR59
0
OAIN+
OAIN-
+3V
112
PR16
1.96K
RUNPWROK
PQ8
2N7002
PQ7
2N7002
8
7
6
5
P29
11
12
13
+VCC_CORE
14
15
OAIN- 16
OAIN+ 17
CSP+ 18
PC41
CSN- 19
100P
20
43
42
41
40
39
38
37
36
35
34
33
32
31
P9
From ICH4
G
PR20
10K
PR18
100K
PR17
100K
PC526
0.1µ
D
3
2
1
PR40
100K
PC524
10µ
PU507
AO4406
GND
GND_A
PC39
47P
PC529
1000P
49.9K
PC17
1µ
PR45
2.74K
VDD5
8
7
6
5
PR13
10
RUN_PWROK
PR22
301K REF_CORE
DD_CPU
PL505
120Z/100M
9
8
7
5
4
3
2
1
+5V_PP
PL507
120Z/100M
+5V_PP DVMAIN
PR27
0
CORE_CLKEN#
VRMPWRGD
VCCP_PWRGD
DPRSLPVR
STOP_CPU#
To U508 Clock Generator
To U15
From PU13
From U12 ICH4-M
From U12 ICH4-M
PR52
1K
PC67
PC66
0.1µ
8.1 No Power
Charge
PQ6
AO4407
PL508
120Z/100M
3
2
1
S
ADINP
P24
PU505A
AO4807
8
7
6
5
D
PD509
EC31QS04
PR51
4.7K
PR53
4.7K
G
PC532
10µ
4
PC531
0.01µ
PC527
0.01µ
PQ9
MMBT2222A
PF2
FUSE_1206
PR38
100K
PL506
47µH
8
7
PC550
10µ
1
PR4
20K
PD508
EC31QS04
-TE12L
2
PR10
13.7K
From H8 U7
S
13
5
6
PC49
1000P
PR58
15K
14
VCC
P18
PR73
124K
C1,C2
P24
2IN+
OUTPUTCTRL
CT
RT
REF
PU5
1IN-
16
FEEDBACK
DTC
2IN-
PC46
0.1µ
PU8A
LMV393M
PR64
1M
PC54
150P
PR518
6.19K
3
4
VDD5
PC533
0.1µ
PC535
0.01µ
PC62
1µ
PC59
0.1µ
PQ503
2N7002
LI_OVP
1
_
PR62
13.7K
PR75
2.49K
PC65
0.1µ
REF
+
2IN+
15
PR74
10K
3
2
PWM
TL594C
1.25V
2
8,11
12
8
PR69
0
4
PQ12
2N7002
PC55
0.1µ
From H8 U7
PR79
100K
PR76
3.3K
1.25V
DVMAIN
PC63
0.1µ
PR78
100K
PR77
590K
5
PJS501
6
PQ14
SCK431LCSK-5
113
VDD5
8
P18
PD2
BZV55C20
PR513
33K
P18
PR63
4.7K
PC64
0.1µ
PR80
100K
BATT_DEAD
+
7
_
4
From H8 U7
BATT
4
PR8
976K
PR9
487K
VDD5
I_CTRL
G
PR514
100K
PD3
RLS4148
PQ13
DTA144WK
CHARGING
5
6
3
2IN+
PR56
130K
CHARGING
D
PU505B
AO4807
PU8B
LMV393M
P18
To H8 U7
8.1 No Power
Discharge
PQ4
AO4407
C275
2.2µ
PQ5
AO4407
PC14
1000P
PC22
0.01µ
8
7
6
5
VMAIN
4
3
2
1
2
PR42
100K
14
4
SVDD3
PR55
226K
R97
0
PR47
33K
ADINP
H8_PWRON_RSM5V
H8_ADEN#
PJ502
PQ11
DTC144WK
ADEN#
PQ10
2N7002
PL2
120Z/100M
D7
RLS4148
3
PC19
0.1µ
SVDD3
U7
78
BAT_VOLT
C536
0.1µ
Controller
3
BAT_V
PC12
0.1µ
R559
2.2K
C531
0.1µ
PR7
4.99K
BAT_T
PC32
0.1µ
PR34
100K
PR6
20K
VDD5
2
1
R857
4.7K
R855
4.7K
2
BAT_CLK
3
BAT_DATA
R842
33
PR510
0
BAT_C
1
PD507
BAV99
PD506
BAV99
3
W83L950D
VDD5
VDD5
2
BAT_TEMP
PR19
499K
PC15
0.1µ
3
2
1
77
R560
2.2K
P23
6,7
5
BAT_D
4
PR511
0
R841
33
114
JPO507
SPARKGAP-6
JPO501
SPARKGAP-6
Battery Connector
D506
BAV70LT1
Embedded
PF1
6.5A/32VDC
PL3
120Z/100M
SVDD3
P18
PWR_VDDIN
PD503
BAV70LT1
G
5
R91
47K
R1
Q15
DTC144TKA
3
1
S
D
D2
BAS32L
3
2
1
D
D
G
R92
100K
BATT
S
S
8
7
6
5
VDD3
Q16
SI2301DS
G
SVDD3
8.2 No Display
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor
or LCD module
OK?
No
Replace monitor
or LCD.
Board-level
Troubleshooting
Yes
Make sure that CPU module,
DIMM memory are installed
Properly.
Display
OK?
Yes
No
1.Try another known good CPU module,
DIMM module and BIOS.
2.Remove all of I/O device ( HDD,
CD-ROM…….) from motherboard
except LCD or monitor.
Display
OK?
No
Yes
System
BIOS writes
error code to port
378H?
Correct it.
Replace
Motherboard
Yes
No
Check system clock,
reset circuit and
reference power
1. Replace faulty part.
2. Connect the I/O device to the M/B
one at a time to find out which part
is causing the problem.
To be continued
Clock,reset and power checking
115
Refer to port 378H
error code description
section to find out
which part is causing
the problem.
8.2 No Display
****** System Clock Check ******
+3V
P3 U506
HSTPCLK#
+3V
P29 CORE_CLKEN#
From PU4
R137
10k
R136
0
VTT_PWRGD#
28
R143
8.2K
L26
120Z/100M
+3VCLKCPU
46,50
L27
120Z/100M
+3VCLKPCI
8,14
L532
120Z/100M
+3VCLKANA
L25
120Z/100M
+3VCLK66
45
R619
27.4
44
R616
27.4
HCLK_CPU
R595
R615
60.4
43
1,26,37
19,32
R626
27.4
HCLK_MCH
P5
48
R623
27.4
HCLK_MCH#
P6
21
R612
33
66M_MCH
39
R613
33
48M_DREFCLK
R622
60.4
R625
60.4
3V66[5:0]
PCI
166.66
66.66
33.33
001 x
x
0
1
100.00
66.66
33.33
1
0
200.00
66.66
33.33
R148
4.7K
FS0
54
x
1
1
133.33
66.66
33.33
FS1
55
Mid
0
0
Tristate
Tristate
Tristate
Mid
0
1
TCLK/2
TCLK/2
TCLK/2
FS2
40
Mid
1
0
Reserved
Reserved
Reserved
Mid
1
1
Reserved
Reserved
Reserved
0 : 0V
1 : 3.3V
R155
4.7K
SUSCLK
Q508
2N7002
R744
10K
29
R759
10K
R510
33
S
SMBDATA
70
P18
U7
Embedded
Controller
P17
P16
PCICLK_MINIPCI
MINIPCI
Connector
R620
33
S
SMBCLK
C600
10P
C603
10P
PLL207-151
3
X501
14.318MHz
R743
2.2K
SMB_DATA
D
P9 P10
U12
SMB_CLK
D
Q521
2N7002
SUSCLK
39
R611
33
USBCLK_ICH
22
R609
33
66M_ICH
7
R632
33
PCICLK_ICH
56
R642
33
14M_ICH
12
1
U510
PCMCIA
Controller
J504
2
21
30
R748
2.2K
Q522
2N7002
G
13
16
VDD3
G
Generator
LPCCLK_KBC
SMBDATA
+3V
Clock
R617
33
SMBCLK
U508
R140
4.7K
UNIT : MHz
PCICLK_CARD
CLK_DDR[0:5]#
D
CPU
0
CLK_DDR[0:5]
855GME
R520
1K
G
FS0
0
P7 J512, J509
DDR SO-DIMM
S
FS1
x
Pentium-M
HTCLK
U504
Memory
Controller
+1.5V
+3V
FS2
27.4
R618
60.4
49
P4
CPU
HCLK_CPU#
MULTSEL0
I/O
Controller
Hub
ICH4-M
HSTPCLK#
11
R621
33
PCICLK_BIOS
31
10
R627
33
PCICLK_LAN
115
2
116
P20 U512
System BIOS
P15 U511
Ethernet
Controller
8.2 No Display
****** Power Good & Reset Circuit Check ******
+VCCP
U503
MAX809
H8_RESET#
2
SW2
POWERBTN#
13
R68
0
R110
300
SVDD3
JL5
JL4
MCH_PCIRST#
LCD_PCIRST#
Refer Chapter 8.3
+3V
PCIRST#
4,5
P9
VDD3
JL6
6
R73
4.7K
R837
0
RSMRST#
7
H8_PWRON_SB#
R843
0
ICH_PWRBTN#
VDD3
R220
4.7K
R209
SVDD3
0
1
3
0
R839
0
1
SLP_S5#
I/O
1,2
3
Hub
U15A
74AHC08_V
VCC_RTC
180K
C706
1µ
ICH4-M
RTCRST#
C696
0.1µ
ICH_VGATE
R221
22
1
C256
18P
X3
32.768KHz
LPCKBC_RST#
JL3
CB_PCIRST#
JL2
PCIRST0#
2
20
P8
U5
TV Controller
P16
J504
MINIPCI
P20 U512
System BIOS
P17 U510
PC CARDBUS
P11
R206
10M
ICH_LAN_RST#
RTC_X2
117
12
13
VRMPWRGD
From PU4, P29
Refer VCC_CORE
PWROK
7
ACRST#
RTC_X1
11
2
1.25MM/ST/MA-2
ACES
85205-0200
JL1
To D5,D4
11
U15D
74AHC08_V
R718
10M
C255
18P
LPCBIOS_RST#
P15 U511
Ethernet
Controller
+3V
RTC_VBIAS
J516
JL7
14
R765
C697
0.047µ
26
U15C
74AHC08_V
+3V
Controller
D511
BAV70LT1
2
R767
1K
SLP_S4#
WAKE_UP#
3
MINIPCI_PCIRST#
SUSB#
D6
BAW56
2
WAKE_UP#
JL8
8
7
H8_WAKE_UP#
38
R219
10K
9,10
U12
7
Q9
DTC144TKA
VDD3
13
14
H8_RSMRST#
H8_SUSB
TV_PCIRST#
+3V
8
W83L950D
114
U15B
74AHC08_V
JL9
R835
4.7K
LAN_PCIRST#
14
R840
10K
R838
U506
CPU
Pentium-M
HPWRGD
855GME
PWROK
VDD3
SUSC#
P3
HCPURST#
LPCKBC_RST#
4
HTRST#
ICH_SYS_RESET#
R505
0
64
22
R594
680
14
U7
U504
Memory
Controller
PWROK
R226
10K
POWRSW#
R856
1K
Embedded
Controller
P5
VDD3
R853
10K
1
VCC
R861
100K
SVDD3
P18
P18
RESET#
3
R122
51
7
25
+VCCP
SVDD3
R745
10K
P12 U519
Audio Codec
ALC101
There is no display or picture abnormal on LCD although power-on-self-test is passed.
VGA Controller Failure
LCD No Display
1. Confirm LCD panel or monitor is good
and check the cable are connected
properly.
2. Try another known good monitor or
LCD module.
Display
OK?
Yes
Check if
J1, J3 are cold
solder?
Board-level
Troubleshooting
No
Display
OK?
No
Parts:
Yes
Re-soldering.
One of the following parts on the mother-board may be
defective, use an oscilloscope to check the following signal or
replace the parts one at a time and test after each replacement.
Replace faulty
LCD or monitor.
Replace
Motherboard
Remove all the I/O device & cable from
motherboard except LCD panel or
extended monitor.
Yes
Connect the I/O device & cable to
the M/B one at a time to find out
which part is causing the problem.
No
118
D1
R11
Q1
F1
PU1
L2
R10
R6
J1
J3
Signals:
L8
L37
L6
L7
U3
F3
Q23
U504
U12
U7
+3V
LCDVCC
FPVDD
LCD_ID[0..2]
TXOUT[0..2]+
TXOUT[0..2]TXCLKOUT0+
TXCLKOUT0ENBL
LCD_PCIRST#
ENABLE_BKLT
+VMAIN_INV
There is no display or picture abnormal on LCD although power-on-self-test is passed.
+3V
PU1
SI4800DY
F1
MICROSMDC110
8
7
6
5
P5
L2
120Z/100M
3
2
1
D
C5
0.1µ
J1
S
+3V
G
+3V_LCDVCC
C8
0.1µ
C7
10µ
C6
0.1µ
C4
1000P
C2
1000P
1,2
C1
0.1µ
P14
DVMAIN
R11
10K
D1
BAW56
U504
2
3
1
+3V
Q1
DTC144TKA
R6
10K
LCD_ID0
17
R5
10K
LCD_ID1
19
R2
10K
LCD_ID2
20
LCD Connector
FPVCC
R10
470K
LCD_PCIRST#
Refer Chapter 8.2
Memory
Controller
Hub
TXOUT[0..2]+
7,13,14
TXOUT[0..2]-
5,11,12
TXCLKOUT0+
LCD
8
TXCLKOUT0-
6
U3
SI4835DY
SUSB#
G
S
G
R195
100K
D
Q23
2N7002
LCD_PCIRST#
Refer Chapter 8.2
U12
J3
P20
L8
ENABLE_BKLT
120Z/100M
3
C13
0.1µ
Q2
DTC144TKA
L37
120Z/100M
1,2
L6
120Z/100M
9
L7
120Z/100M
4
SUSB#
I/O Controller
SW1
LCD_ID0
LID#
LCD_ID1
ICH4-M
LCD_ID2
P22
R1
470
16
VDD3
P18
11
U7
W83L950D
119
BLADJ
C15
0.1µ
C12
0.1µ
5,11
Inverter
P9 P10
D
+VMAIN_INV
R193
470K
C249
0.1µ
+3V
8
7
6
5
3
2
1
DVMAIN
S
855GME
F3
FUSE-2.5
R200
0
ENBL
Inverter
Board
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.
External Monitor No Display
1. Confirm monitor is good and check
the cable are connected properly.
2. Try another known good monitor.
Board-level
Troubleshooting
Check if
J502
are cold solder?
Yes
Re-soldering.
No
Display
OK?
Yes
One of the following parts on the mother-board may be
defective, use an oscilloscope to check the following signal or
replace the parts one at a time and test after each replacement.
Replace faulty monitor.
No
Display
OK?
Yes
Connect the I/O device & cable to
the M/B one at a time to find out
which part is causing the problem.
No
Replace
Motherboard
120
Parts:
Signals:
U504
U12
J502
F501
D503
L510
Q504~Q507
L503~L509
R511
R515
CP503
+5V
+3V
CRT_DDA
CRT_HSYNC
CRT_VSYNC
CRT_DDCK
CRT_R
CRT_G
CRG_B
CRT_IN#
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.
+5V
+1.5V
F501
MICROSMDC110
1
GND
D613
BAV99
R515
2.2K
P14
VGA_DDC2B
9
3
R511
2.2K
G
S
1
2
39
R513
39
120Z/100M
VGA_DDDA
12
L507
120Z/100M
VGA_HSYNC
13
L508
120Z/100M
VGA_ VSYNC
14
L509
120Z/100M
VGA_ DDCK
15
5
1
2
U524
AHCT1G08DBV
4
3
CRT_ VSYNC
Memory
R512
L506
G
CRT_ DDCK
S
D
Q507
2N7002
Hub
1
CRT_ G
L504
120Z/100M
VGA_ GREEN
2
CRT_B
L505
120Z/100M
VGA_BLUE
3
C778
3.3P
C779
3.3P
C777
3.3P
P9
C781
3.3P
C780
3.3P
CP503
22P*4
16,17
JL501
1
C776
3.3P
R43
75
2
R9
75
4
R41
75
7
VGA_ RED
8
120Z/100M
6
L503
5
CRT_ R
JL502
+3V
GND
U12
I/O Controller
ICH4-M
GND_CRT15
GND
R729
8.2K
GND_CRT15
GND_CRT15
R514
1K
CRT_IN#
GND
5
C504
100P
6,7,8,10
GND_CRT15
GND
121
External VGA Connector
U525
AHCT1G08DBV
4
3
CRT_HSYNC
D
Q504
2N7002
5
U504
855GME
L501
120Z/100M
10K
CRT_DDDA
Controller
D503
D1FS4
+5V
3
R522
2
2
D612
BAV99
3
D611
BAV99
+3V
10K
3
P5
1
2
+3V
R521
1
J502
+3V
Extend DDRAM is failure or system hangs up.
Memory Test Error
1.If your system installed with expansion
SO-DIMM module then check them for
proper installation.
2.Make sure that your SO-DIMM sockets
are OK.
3.Then try another known good SO-DIMM
modules.
Test
OK?
Yes
Board-level
Troubleshooting
Replace the faulty
DDRAM module.
No
If your system host bus clock running at
266MHZ then make sure that SO-DIMM
module meet require of PC 266.
Test
OK?
Yes
Replace
Motherboard
Replace the faulty
DDRAM module.
No
122
One of the following components or signals on the motherboard
may be defective ,Use an oscilloscope to check the signals or
replace the parts one at A time and test after each replacement.
Parts:
Signals:
RP1~RP13
RP13~RP29
R78
R130
Q521
Q522
J512
J509
U504
U12
U508
R743
R748
+1.25V_DDR
+2.5V_DDR
CKE [0..3],
CS# [0..3]
SMA [1,2,4,5]
SMAB [1,2,4,5]
NB_MA [0,3,6..12]
NB_MD [0..63]
NB_DQS [0..8],
NB_BA [0,1]
NB_CB [0..7],
NB_DM [0..8]
NB_RAS#
NB_CAS#
NB_WE#
SMB_DATA
SMB_CLK
HCLK_MCH
HCLK_MCH#
66M_MCH
CLK_DDR [0..5]
CLK_DDR [0..5]#
Extend DDRAM is failure or system hangs up.
+1.25V_DDR
RP16~RP29
RP14,RP15
56*8
56*4
J512
CKE [0..3], CS# [0..3], SMA [1,2,4,5], SMAB [1,2,4,5]
NB_MA [0,3,6..12]
MA [0,3,6..12]
NB_MD [0..63]
MD [0..63]
NB_DQS [0..8], NB_BA [0,1]
DQS [0..8], BA [0,1]
NB_CB [0..7], NB_DM [0..8]
MCB [0..7], DM [0..8]
NB_RAS#, NB_CAS#, NB_WE#
RAS#, CAS#, WE#
RP1~RP13
R130,R78
+1.25V_DDR
P7
10*8
10
DDR SODIMM
P6
CKE [0,1], CS# [0,1], SMA[1,2,4,5]
CLK_DDR [0..2] , CLK_DDR [0..2]#
SMVREF_0
U504
C126
0.1µ
VDD3
+3V
+2.5V_DDR
GND
R743
2.2K
P9
SMB_DATA
Memory
U12
Controller
I/O Controller
Hub
ICH4-M
R744
10K
G
D
S
Q522
2N7002
SMB_CLK
R759
10K
R135
75
C233
0.01µ
C192
0.1µ
+DDR_VREF
+3V
SMBDATA
G
D
S
R134
75
SMBCLK
C182
0.01µ
C168
0.1µ
C142
0.1µ
C139
0.1µ
Q521
2N7002
HCLK_MCH
R626
27.4
HCLK_MCH#
R623
27.4
66M_MCH
R612
33
49
P7
P4 U508
29
48
21
Clock
Generator
J509
DDR SODIMM
855GME
R748
2.2K
30
PLL207-151
CKE [2,3], CS[2,3]#, SMAB [1,2,4,5]
CLK_DDR [3..5] , CLK_DDR [3..5]#
CLK_DDR [0..5] , CLK_DDR [0..5]#
123
Error message of keyboard or touch-pad failure is shown or any key does not work.
Keyboard or Touch-Pad
Test Error
Is K/B or T/P
cable connected to notebook
properly?
No
Board-level
Troubleshooting
Re-soldering.
No
Replace
Motherboard
Try another known good Keyboard
or Touch-pad.
Yes
Yes
Correct it.
Yes
Test
Ok?
Check
J4, J5
for cold solder?
Replace the faulty
Keyboard or Touch-Pad.
No
124
One of the following parts or signals on the motherboard
may be defective, use an oscilloscope to check the signals
or replace the parts one at a time and test after each
replacement.
Parts
Signals
U512
U7
J4,J5
SW6,SW7
U12
F502
L525
R48
C49
CP504
X2
+KBC_VDDA
KI[0..7]
KO[0..15]
T_CLK
T_DATA
Error message of keyboard or touch-pad failure is shown or any key does not work.
VCC
74
+VCC_CORE_KBC
75
+3V_KBC
+3V
R64
10K
P9
U12
HRCIN#
I/O Controller
SERIRQ
R65
0
J4
55~62
KI[0..7]
17~24
39~54
KO[0..15]
1~16
72
P18
Internal
Keyboard Connector
+KBC_VDDA
P18
+5V
F502
0.5A/POLYSW
U7
65~68
LAD[0:3]
L525
120Z/100MHZ
J5
12
+5V
70
LPCCLK_KBC
From U508
P4
LAD[0:3]
23~26
+KBC_VDD
69
ICH4-M
P20
VREF
21
H8_RCIN#
71
Keyboard
Controller
R62
4.7K
P20
C585
0.1µ
R60
4.7K
6
T_CLK
L527
120Z/100MHZ
1,2
9
T_DATA
L526
120Z/100MHZ
3,4
SW6
TC010-PSS11CET
W83L950D
R592
0
5,6
SW_LEFT
U512
25,271,32
7
FWH
8
R868
4.7K
+3V
C802
4.7µ
JO67
R869
4.7K
R48
1M
28
23
LFRAME#
63
2
LPCKBC_RESET#
64
CP504
47P*4
SW_RIGHT
29
SST49LF004A
R591
0
SW7
TC010-PSS11CET
C46
22P
X2
8MHZ
125
JO63
C49
22P
7,8
Touch-Pad
8.7 Hard Drive Test Error
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Driver Test Error
1. Check if BIOS setup is OK?.
2. Try another working drive and cable.
Re-boot
OK?
Yes
Board-level
Troubleshooting
Replace the faulty parts.
No
Replace
Motherboard
Check the system driver for proper
installation.
Re - Test
OK?
Yes
End
No
126
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Parts:
Signals:
U12
J514
Q19
D5
R187
L49
R196
+5V
HDD_LED#
PD_D[0..15]
IDERST#
PDCS1#
PDA[0..2]
PDDACK#
PIORDY
PDIOR#
PDIOW#
PDREQ
PDCS3#
IRQ14
8.7 Hard Drive Test Error
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
R256
330
HDD_LED#
+5V
+5V
P10
IDERST#
U12
I/O
Controller
R172
R165
0
0
1
2
+3V
R162
10K
R697
4.7K
3
+3V
P11
C245
10µ
C243
0.1µ
C244
0.1µ
C_PD_D[0..15]
27~42
C_RSTDRV1#
43
+5V
Q19
DTC144TKA
R185
10K
R187
22
PDCS1#
C_PDCS1#
PDA2
C_PDA2
10
PDDACK#
C_PDDACK#
15
PIORDY
C_PIORDY
17
PDIOR#
C_PDIOR#
19
PDIOW#
C_PDIOW#
21
PDDREQ
C_PDDREQ
Hub
7
23
R196
470
+3V
18
R693
8.2K
ICH4-M
PDCS3#
C_PDCS3#
PDA0
C_PDA0
9
PDA1
C_PDA1
11
IRQ14
C_PINTRQ
13
127
8
Primary EIDE Connector for Hard-Disk
P9 From U12 PCIRST0#
Refer Chapter 8.2
+3V
5
3,4
L49
120Z/100MHZ
PD_D[0..15]
D5
BAW56
J514
D16
CL-190G
8.8 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.
CD-ROM Driver
Test Error
Board-level
Troubleshooting
1. Try another known good compact disk.
2. Check install for correctly.
Test
OK?
Yes
Replace the faulty parts.
No
Replace
Motherboard
Check the CD-ROM drive for
proper installation.
Re - Test
OK?
Yes
End
No
128
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Parts:
Signals:
U12
J510
Q18
D4
R183
R655
R673
R164
L50
C141
+5V
CD_LED#
SD_D[0..15]
SIDERST#
SDA[0..2]
IRQ15
SDDACK#
SIORDY
SDIOW#
SDDREQ
SDIOR#
SDCS1#
SDCS3#
8.8 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.
J510
D15
CL-190G
R255
330
37
CD_LED#
+5V
38~42
+5V
L50
120Z/100MHZ
C141
0.1µ
SD_D[0..15]
C140
0.1µ
C143
10µ
C_SD_D[0..15]
P10
SIDERST#
U12
I/O
Controller
R171
R161
0
0
1
2
+3V
R160
10K
R655
8.2K
3
+3V
R673
4.7K
+3V
6~21
+5V
Q18
DTC144TKA
R164
10K
R183
22
C_RSTDRV2#
5
SDA1
C_ SDA1
31
IRQ15
C_ SINTRQ
29
SDDACK#
C_ SDDACK#
28
SIORDY
C_ SIORDY
27
SDIOW#
C_ SDIOW#
25
SDDREQ
C_ SDDREQ
22
SDIOR#
C_ SDIOR#
24
SDA0
C_ SDA0
33
SDCS1#
C_ SDCS1#
35
SDCS3#
C_ SDCS3#
36
SDA2
C_ SDA2
34
Hub
ICH4-M
P12
1
CDROM_RIGHT
2
CDROM_COMM
3
To U519
To U519
129
CDROM_LEFT
To U519
Secondary EIDE Connector for CD-ROM
P9 From U12 PCIRST0#
Refer Chapter 8.2
+3V
D4
BAW56
P11
8.9 USB Test Error
An error occurs when a USB I/O device is installed.
USB Test Error
Check if the USB device is installed
properly. (Including charge board.)
Board-level
Troubleshooting
Test
OK?
Yes
Correct it.
No
Replace another known good charge
board or good USB device.
Replace
Motherboard
Re-test
OK?
Yes
Correct it.
No
130
Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time
and test after each replacement.
Parts:
Signals:
U12
J507
J506
U521
U522
L44
L47
L38
L41
R585
R574
C763
+5V_P
USBOC1#
USBOC3#
USBP[0..3]+
USBP[0..3]-
8.9 USB Test Error
An error occurs when a USB I/O device is installed.
JO23
SHORT-SMT4
JO51
SHORT-SMT4
U521 P21
RT9701-CBL
R585
0
3,4
+5V_P
GND
VOUT0,1
R805
390
USBP0_P
USBP0-
USBP0_N
USBP1-
C765
1000P
L44
90Z/100M
J507
R804
560
GND_USB
3
1
4
2
+VCC_USB_3
L47
90Z/100M
USBP1_P
1
P21
3
2
USBP1_N
USBP1+
A1
A2
1
4
2
3
A3
U12
JO70
USBOC5#
JO529
USB Port
USBP0+
超出
I/O
C766
150µ
USBOC1#
P10
USBOC4#
+VCC_USB_1
1,5
C764
1µ
GND_USB
USBOC1#
VIN0,1
JO71
JO73
JO72
JO530
R184
10K
VDD3
U522 P21
RT9701-CBL
R688
10K
R574
0
Controller
3,4
+5V_P
Hub
VIN0,1
VOUT0,1
GND_USB
+VCC_USB_2
1,5
C686
1µ
USBOC3#
USBP3-
USBP3+
JO528
C763
1000P
L38
90Z/100M
USBP2_P
USBP2_N
J506
R570
560
GND_USB
3
1
4
2
+VCC_USB_4
L41
90Z/100M
USBP3_P
A1
A2
1
4
2
3
A3
JO20
JO21
JO50
GND_USB
131
P21
3
2
USBP3_N
1
JO49
JO527
USB Port
USBP2-
C528
150µ
USBOC3#
ICH4-M
USBP2+
R567
390
8.10 Audio Failure
No sound from speaker after audio driver is installed.
Audio Failure
1. Check if speaker cables are
connected properly.
2. Make sure all the drivers are
installed properly.
Yes
Test
OK?
Board-level
Troubleshooting
1.If no sound cause
of line out, check
the following
parts & signals:
Correct it.
No
1.Try another known good
speaker, CD-ROM.
2. Exchange another known
good charger board.
Re-test
OK?
No
Yes
Replace
Motherboard
Correct it.
Check the following parts for cold solder or one of the following parts on the
motherboard may be defective,use an oscilloscope to check the following signal
or replace parts one at a time and test after each replacement.
2. If no sound cause
of MIC, check
the following
parts & signals:
3. If no sound cause
of CD-ROM, check
the following
parts & signals:
Parts:
Signals:
Parts:
Signals:
Parts:
Signals:
U12
U510
U519
U18
J9
J2
J503
R785
C735
R779
C723
R243
L34
AOUT_R
AOUT_L
ACRST#
ACSDOUT
ACSDIN0
ACSDYNC
ACBITCLK
+3V
AVDDAD
SPK_OFF
U12
U510
J8
L33
L546
R506
R238
H8_AVREF
MIC
U519
J510
R242
R240
C745
C743
CDROM_LEFT
CDROM_RIGHT
CDROM_COMM
132
8.10 Audio Failure – Audio IN
Q524
SI2301DS
S
+5V_PP
D
AVDDAD
R800
4.7
JS507
SHORT-SMT4
G
From U7
25,38
C759
22µ
H8_SUSB
P18
C691
10µ
AGND
AGND
C692
0.1µ
AVDD[1,2]
R236
0
C730
0.1µ
AGND
MIC1
H8_AVREF
1
R237
4.7K
C266
4.7µ
AGND
C755
47P
R238
4.7K
2
R144
0
L546
600Z/100M
C267
2.2µ
5
AGND
AGND
P17 U510
CARDBUS
62 CARDSPK#
2
R762
47K
Controller
21
+5V
C689
0.1µ
C701
0.1µ
P12
3
U518
GND
1
MIC
PC_BEEP
NC7S32
P10
U12
GND
SPK_OFF
Audio Codec
To next page
ACRST#
R881
0
ACRST_CODEC#
5
ACSDIN0
R776
22
R7
22
ICH4-M
GND
ALC101
8
J510
C745
0.33µ
R242
0
CDROM_RIGHT
2
18
C743
0.33µ
R240
0
CDROM_LEFT
1
19
C744
0.33µ
R241
0
CDROM_COMM
3
35
AOUT_L
36
AOUT_R
To next page
For EMP202
R150
0
R151
0
R186
0
R189
0
6
ACBITCLK_CODEC
C808
22P
C810
22P
Current Selection
2
C809
22P
R230
1M
3
GND
GND
GND
C709
22P
X503
24.576MHZ
C704
22P
AGND
GND
133
P11
CD-ROM
Connector
10
ACSYNC
ACBITCLK
CAGND
20
11
ACSDOUT
I/O
Controller
Hub
CAGND
12
SBSPKR
P9
External
MIC
JO64
U519
C720
0.1µ
R769
1K
R506
0
AGND
PC_BEEP
4
4
3
6
2
C265
100P
GND
R768
100K
J8 P12
1
C746
1µ
P12
P12
5
L33
600Z/100M
AGND
MIC1
Internal
MIC
P12
JO524
GND
FREQ
ID1#
ID0#
14.318MHZ
OPEN
OPEN
27MHZ
OPEN
1K
48MHZ
1K
OPEN
24.576MHZ
1K
1K
8.10 Audio Failure – Audio OUT
+5V
J503
L541
120Z/100M
7,18
R191
0
C269
100µ
GND
C718
0.1µ
PVDD0/PVDD1
C59
0.47µ
From previous page
ROUT+
1
16
ROUT-
2
4
LOUT+
9
LOUT-
C521
0.1µ
L3
600Z/100M
P13
AGND
AOUT_R
21
RHP_IN
20
RLINE_IN
23
2
L4
600Z/100M
RHPIN
JO13
JO14
JO9
JO10
C715
100µ
GND
J9 LINE OUT
1
Audio
R228
100K
R785
1K
Amplifier
C735
100P
R779
1K
R244
22
L35
600Z/100M
2
R243
22
L34
600Z/100M
6
3
4
5
C723
100P
22
MUTE#
R37
10K
JO65
SPK_OFF
R1
Q20
DTC144TKA
C507
1µ
TPA0212A
15,17
LHP_IN
6
LLINE_IN
5
R245
100K
LINE_IN#
C268
0.1µ
LHPIN
LLINEIN
3
GAIN1
2
GAIN0
R56
10K
+5V
R57
10K
134
JO66
+5V
AGND
From previous page
C246
0.47µ
Internal Speaker
Connector
RLINEIN
+5V
From previous page
L
U18
+3V
C89
0.47µ
Internal Speaker
Connector
J2
1
C714
100µ
C86
0.47µ
AOUT_L
R
R239
100K
R507
0
CAGND
CAGND
GND
8.11 LAN Test Error
An error occurs when a LAN device is installed.
LAN Test Error
1.Check if the driver is installed properly.
2.Check if the notebook connect with the
LAN properly.
Board-level
Troubleshooting
Test
OK?
Yes
Correct it.
No
Check if BIOS setup is ok.
Replace
Motherboard
Re-test
OK?
Yes
Correct it.
No
135
to check the following signal or replace the parts one at a time and
test after each replacement.
Parts:
Signals:
U511
U12
U515
U509
J511
X504
L534
L536
Q520
Q519
L531
L533
L535
R645
JS3
+LAN_A2.5V
+LAN_D2.5V
CARD_RI#
PCICLK_LAN
PCIRST#
IN_PIRQE#
PCI_REQ1
PCI_FRAME#
PCI_DEVSEL#
PCI_TRDY#
PCI_IRDY#
PCI_PME#
PCI_STOP#
PCI_GNT1#
PCI_PAR
AD[0..31]
CBE#[0..3]
RXIN+
RXINTXD+
TXDEECS
EESK
EEDI
EEDO
8.11 LAN Test Error
An error occurs when a LAN device is installed.
+3V_P
+LAN_D3V
91,103,97,106,96
+LAN_A2.5V
3,16,28,40,56,67,82,120
115
L694
120Z/100M
P4
PCICLK_LAN
+LAN_D2.5V
49,111
P17
+3V_P
U510
CARDBUS
Controller
Q519
DTC144WK
43
C598
0.1µ
PCI1410
VCCRAM
C658
0.1µ
CARD_RI#
U515
NM93C46
VCC25_[0,1]
R707
2.2
50
EECS
1
58
EESK
2
57
EEDI
3
54
EEDO
4
P15
LAN_GND
+2.5V_DDR +LAN_D2.5V
+2.5V_DDR +LAN_A2.5V
From U508 Clock Generator
CS
+3V_P
VCC
SK
DO
GND
LAN_WAKE
0
4,5
WOL
104
JL6
LAN_PCIRST#
114
LAN
ICH4-M
R649
49.9
R648
49.9
R647
49.9
RXIN+
2
105
J511
L531
PLP3216S
3
RXIN-
6
P15
1
4
+3V
108
L533
PLP3216S
TXD+
2
RP43,RP510 8.2K*4
R208 8.2K
VT6105-L
109
1
U509
1
3
TXD-
4
PH163112
PCI_FRAME#, PCI_DEVSEL#
15,19
PCI_TRDY#, PCI_IRDY#
18,17
PCI_PME#, PCI_STOP#
119,21
94
LANX1
95
LANX2
R637
0
2
117,23
PCI_GNT1#, PCI_PAR
AD18
R662
0
4
2,7
+LAN_A2.5V
C617
22P
C619
22P
AD[0..31], CBE#[0..3]
GND
136
R624
0
3
PJRX-
R628
0
6
16
PJTX+
R634
0
1
14
PJTX-
R641
0
2
10
R146
75
R643
75
R153
75
R633
75
15
GND
GND
PJ7 7,8
PJ4 4,5
C190
1000P
C604
0.1µ
P19
GND_45
GND
1
X504
25MHZ
PJRX+
9
3
113,118
INT_PIRQE#, PCI_REQ1#
11
8
Controller
GND
I/O
Controller
Hub
R650
49.9
GND
6
LAN_GND
GND
L535
120
RJ45 LAN Connector
U15B
74AHC08_V
+LAN_A2.5V
U511
Q520
DTC144WK
7
PCIRST#
U12
112
14
P9
C621,C657,C614 0.1µ
C616,C608
2.2µ
GND
R645
10K
+3V
+LAN_A2.5V
L536
120Z/100M
C659,C613
0.1µ
5
+3V_P
ICH_RI# R640
+2.5V_DDR
L534
120Z/100M
C663
1µ
P15
DI
+LAN_D2.5V
8
JS503
SHORT-SMT4
JS3,JS504
SHORT-SMT4
JS502
SHORT-SMT4
JS505,JS506
SHORT-SMT4
GND_45
GND
LAN_GND
An error occurs when a PC card device is installed.
PC Card & Card
Reader Socket Failure
1. Check if the PC Card device is installed
properly.
2. Confirm PC Card driver is installed ok.
Test
OK?
Yes
Board-level
Troubleshooting
Correct it
No
Try another known good PC
Card or device.
Replace
Motherboard
Parts:
Signals
U12
U510
J6
U513
R819
R816
RP41
U15
PCICLK_CARD
PCIRST#
INT_PIRQB#
PCI_REQ0#
PCI_SERR#
PCI_PERR#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
Re-test
OK?
Yes
PCI_TRDY#
Change the faulty
part then end.
PCI_STOP#
PCLKRUN#
PCI_PME#
No
PCI_GNT0#
137
PIC_PAR
SERIRQ
SUSB#
AD[0..31]
CC/BE#[0..3]
VCC5_EN#
VCC3_EN#
VPPD0
VPPD1
An error occurs when a PC card device is installed.
+5V
R812
+3V
0
AUX_VCC
5,6
C782
0.1µ
P17
PCICLK_CARD
P4
16
SKT_VCC0/1
+CARD_VCC
VCC5_EN#
1
VCC3_EN#
2
VPPD0
15
VPPD1
14
From U508 Clock Generator
5VA,B
SHDN
P17
3.3VA,B
VCCD0
VCCD1
U513
AVCCC,B,A
VDDP0
VDDP1
OC
TPS2211
AVPP
R684
10K
+3V
3,4
+CARD_VCC
10
P17
14
1,2
R813
0
R822
10K
CORE_VCC1
RP41,RP510
RP43 8.2K*4
R215 8.2K
I/O
INT_PIRQB#
Hub
PCI_REQ0#
R819
CARDBUS
CCLK,CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#
CPERR#, CSERR#, CPAR, CREQ#, CGNT#, CINT#, CBCOLK#
Controller
R2_D2, R2_D14, R2_A18, CCD[1,2]#, CVS[1,2], CBLOCK#, CAUDIO, CSTSCHG
PCI_SERR#, PCI_PERR#, PCI_DEVSEL#
PCI1410
PCI_FRAME#, PCI_IRDY#
ICH4-M
0
CCLKRUN#
CRST#
+3V
Controller
C783
0.1µ
C675
1µ
CB_PCIRST#
U510
U12
C649
2.2µ
C786
0.1µ
C787
0.1µ
+CARD_VCC
JL3
7
U15A
74AHC08_V
3
J6
R816
0
CAD9
R815
0
CAD12
CAD[0..10,12..31], CC/BE[0..3]#
PCI_TRDY#, PCI_STOP#
PCLKRUN#, PCI_PME#, PCI_GNT0#
CARDSPK#
PCI_PAR, SERIRQ, SUSB#
To U518
P12
To Q519
P15
AD[0..31], CBE#[0..3]
CARD_RI#
AD19
R59
0
IDSEL
138
R820
10K
Card Bus Socket
P9
PCIRST#
+VPPOUT
11-13
C629
0.1µ
C628
0.1µ
+3V
8
8.13 TV Test Error
An error occurs when a TV device is Connected.
TV Fail
1. Check if the TV device is installed
properly.
2. Confirm TV driver is installed ok.
Board-level
Troubleshooting
Test
OK?
Yes
Correct it.
Parts:
Signals
U504
U5
R29
Q7
Q8
R33
R16
L501
L502
J501
C502
L509
DVOCD[0:11]
No
Check if BIOS setup is ok.
Replace
Motherboard
Re-test
OK?
Yes
Correct it.
No
DVOCHSYNC
DVOCVSYNC
DVOCCLK
DVOCCLK#
POUT/DET#
DVOCFLDSTL
TV_DDCK
TV_DDDA
TV_LUMA
TV_CRMA
139
+1.5VS
+3VS
8.13 TV Test Error
An error occurs when a TV device is connected.
+3V
+1.5V
45
R35
0
+1.5V
L12
120Z/100M
18,44
R16
10K
R18
1K
R17
10K
R20
1K
C16
0.1µ
C30
0.1µ
+3V
C34
10µ
G
S
M12CLK
G
P5
S
M12CDATA
D
D
Q7
2N7002
TV_DDCK
15
TV_DDDA
14
Q8
2N7002
DVOCCLK, DVOCCLK#
U504
DVOCHSYNC, DVOCVSYNC
Memory
Controller
Hub
855GME
57,56
4,5
DVOCFLDSTL
47
POUT/DET#
46
R33
1K
C35
0.1µ
C19
0.1µ
C17
10µ
C50
0.1µ
C48
10µ
GND
TV
GND
ENCODER
13
TV_PCIRST#
R61
100K
P9
From U12 ICH-4
Refer Section 8.2
J501
CH7011A
GND
DVOVREF
1
3
2
L501
120Z/100M
C31
0.1µ
37
TV_LUMA
38
TV_CRMA
3
4
L502
120Z/100M
GND
42
43
2
C24
20P
X1
14.318MHZ
GND1
X1N
XOUT
R25
75
R22
75
C21
100P
C23
100P
C501
270P
C502
270P
GND2
JO503
JO504
1
C27
20P
R501
0
GND
140
TV_GND
P8
TV OUT CONN
R36
1K
C22
0.1µ
33
U5
DVOCD[0..11]
+1.5V
GND
1,12,49
P8
9. Spare Part List
Spare Part List 1
Part Number Description
Price(US)
Price(US)
221672350007 REINFORCE BRKT;50 x 50 x 830MM
242600000433 LABEL;BLANK,11*5MM,COMMON
221673550007 REINFORCE BRKT;L985*50*50*T5
242600000439 LABEL;25*6,HI-TEMP,COMMON
221674550004 REINFORCE BRKT;L800*50*50*T5
242600000439 LABEL;25*6,HI-TEMP,COMMON
221677040001 BOX,AK,LYNX
242600000452 LABEL;BLANK,7MM*7MM,PRC
221677050003 CARD BOARD;TOP/BTM,PALLET,LYNX
242600000452 LABEL;BLANK,7MM*7MM,PRC
221677750002 PARTITION;MANUAL,GHARIAL-N
242664800013 LABEL;CAUTION,INVERT BD,PITCHING
221682820001 CARTON;N-B,8089
242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE
221682850002 CARD BOARD;FRAME,PALLET,8089P
242669600005 LABEL;LOT NUMBER,RACE
222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS
242670800113 BFM-WORLD MARK;WINXP,7521N
222670820003 PE BAG;L560*W345,7521N
242677000027 LABEL,AK BOX,LYNX
222672730001 PE BUBBLE BAG;200*240mm,AMM-9019
242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8
224672330001 PALLET;1200x1050x135MM,MANGUSTA
242682800001 LABEL;AGENCY-GLOBAL,ID2,8089P
225600000054 TAPE;INSULATING,POLYESTER FILM,1
242682800015 LABEL;BATT,11.1V/4.0AH,LI,PANASO
225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U
270140000003 VARISTOR;280V,5.6X3.8MM,TVB280-0
S1
226600030332 SPONGE;320*290*10,CAIMAN,PWR
271002000301 RES;0 ,1/10W,5% ,0805,SMT
L18,R236,R35,R501,R574,R585,R8
227677000001 END CAP;L/R,LYNX
271002472301 RES;4.7K ,1/10W,5% ,0805,SMT
PR505,PR506
227677000002 PAD;LCD/KB,LYNX
271013478301 RES;4.7 ,1/4W,5% ,1206,SMT
R800
242600000001 LABEL;PAL,20*5MM,COMMON
271045057101 RES;.005 ,1W,1% ,2512,SMT
PR522
242600000145 LABEL;10*10,BLANK,COMMON
271045107101 RES;.01 ,1W ,1% ,2512,SMT
PR508,PR81
242600000157 LABEL;BAR CODE,125*65,COMMON
271046017301 RES;.001,2W,5%,2512,CYNTEC,SMT
PR520
242600000195 LABEL;SOFTWARE,INSYDE BIOS-M
271046087301 RES;.008 ,2W,5% ,2512,SMT
PR509
242600000232 LABEL;6*6MM,GAL,BLANK,COMMON
271046407101 RES;.040 ,2W ,1% ,2512,SMT,PRC
R18A,R18B,R18C
242600000378 LABEL;27*7MM,HI-TEMP 260'C
271061000002 RES;0 ,1/16W,0402,SMT
R391,R392,R393,R394,R395,R396
242600000380 LABEL;10*8MM,BIOS,HI-TEMP 260
271061103501 RES;10K ,1/16W,5% ,0402,SMT
R684,R818,R820,R822
242600000385 LABEL;27*10,LAN ID BAR CODE
271061104501 RES;100K ,1/16W,5% ,0402,SMT
R54
141
9. Spare Part List
Spare Part List 2
Price(US)
Price(US)
271071000002 RES;0 ,1/16W,5% ,0603,SMT
L28,L29,L30,L31,PR1,PR24,PR25
271071137271 RES;13.7K,1/16W,.1%,0603,SMT
PR10,PR62
271071100302 RES;10 ,1/16W,5% ,0603,SMT
PR13,PR501,R130,R188,R78
271071141102 RES;140 ,1/16W,1% ,0603,SMT
R19
271071101101 RES;100 ,1/16W,1% ,0603,SMT
R52,R578,R581,R586,R67,R88
271071151101 RES;150 ,1/16W,1% ,0603,SMT
R103,R105,R125,R158,R167,R525
271071101301 RES;100 ,1/16W,5% ,0603,SMT
R37
271071152101 RES;1.5K ,1/16W,1% ,0603,SMT
R523
271071102102 RES;1K ,1/16W,1% ,0603,SMT
PR50,PR52,R116,R126,R520,R569
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT
R17
271071102302 RES;1K ,1/16W,5% ,0603,SMT
R111,R18,R20,R33,R36,R514,R542
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT
R19
271071102302 RES;1K ,1/16W,5% ,0603,SMT
R11
271071153101 RES;15K ,1/16W,1% ,0603,SMT
PR48,PR533,PR58
271071102302 RES;1K ,1/16W,5% ,0603,SMT
R35,R39,R43
271071184301 RES;180K ,1/16W,5% ,0603,SMT
R14,R765
271071103101 RES;10K ,1/16W,1% ,0603,SMT
PR33,PR74
271071196111 RES;1.96K,1/16W,1% ,0603,SMT
PR16
271071103302 RES;10K ,1/16W,5% ,0603,SMT
PR20,PR21,PR88,PR95,R107,R11,
271071201101 RES;200 ,1/16W,1% ,0603,SMT
R234
271071103302 RES;10K ,1/16W,5% ,0603,SMT
R3,R4
271071201301 RES;200 ,1/16W,5% ,0603,SMT
PR57,PR61,R656
271071104101 RES;100K ,1/16W,1% ,0603,SMT
PR2,PR34,PR40,PR80
271071201301 RES;200 ,1/16W,5% ,0603,SMT
R14,R17
271071104101 RES;100K ,1/16W,1% ,0603,SMT
R7
271071202102 RES;2K ,1/16W,1% ,0603,SMT
PR89,PR90,R566
271071104302 RES;100K ,1/16W,5% ,0603,SMT
PR17,PR18,PR38,PR42,PR504,PR
271071202301 RES;2K ,1/16W,5% ,0603,SMT
R12
271071104302 RES;100K ,1/16W,5% ,0603,SMT
R7
271071203101 RES;20K ,1/16W,1% ,0603,SMT
271071104302 RES;100K ,1/16W,5% ,0603,SMT
R11,R15,R2,R38,R44,R48
271071220101 RES;22 ,1/16W,1% ,0603,SMT
R170
271071105301 RES;1M ,1/16W,5% ,0603,SMT
271071221302 RES;22 ,1/16W,5% ,0603,SMT
R183,R187,R221,R243,R244,R7,R7
271071105301 RES;1M ,1/16W,5% ,0603,SMT
R40
271071222302 RES;2.2K ,1/16W,5% ,0603,SMT
R511,R515,R559,R560,R743,R748
271071106301 RES;10M ,1/16W,5% ,0603,SMT
R206,R718
271071225301 RES;2.2M,1/16W,5% ,0603,SMT
R34,R36
271071107311 RES;107K ,1/16W,1% ,0603,SMT
PR15
271071226311 RES;226K ,1/16W,1% ,0603,SMT
PR55
271071124311 RES;124K ,1/16W,1% ,0603,SMT
PR73
271071228301 RES;2.2 ,1/16W,5% ,0603,SMT
R707
271071127011 RES;127 ,1/16W,1% ,0603,SMT
R44
271071244301 RES;240K ,1/16W,5% ,0603,SMT
R41
271071131101 RES;130 ,1/16W,1% ,0603,SMT
R163
271071249111 RES;2.49K,1/16W,1% ,0603,SMT
PR75
271071134701 RES;130K ,1/16W,0.1% ,0603,SMT
PR56
271071274111 RES;2.74K,1/16W,1% ,0603,SMT
PR45
271071137011 RES;137 ,1/16W,1% ,0603,SMT
R14A
271071274301 RES;270K ,1/16W,5% ,0603,SMT
R42
142
9. Spare Part List
Spare Part List 3
Price(US)
Price(US)
271071274811 RES;27.4 ,1/16W,1% ,0603,SMT
R100,R527,R553,R595,R87
271071473301 RES;47K ,1/16W,5% ,0603,SMT
PR63,R211,R227,R762,R91
271071274911 RES;27.4 ,1/16W,1% ,0603,SMT
R616,R619,R623,R626
271071474301 RES;470K ,1/16W,5% ,0603,SMT
PR503,R10,R193,R573
271071301011 RES;301 ,1/16W,1% ,0603,SMT
R526,R563
271071475011 RES;475 ,1/16W,1% ,0603,SMT
R142
271071301301 RES;300 ,1/16W,5% ,0603,SMT
R110,R875
271071487011 RES;487 ,1/16W,1% ,0603,SMT,MUS
R168
271071301311 RES;301K ,1/16W,1% ,0603,SMT
PR22
271071487311 RES;487K ,1/16W,1% ,0603,SMT
PR9
271071301311 RES;301K ,1/16W,1% ,0603,SMT
R13,R3
271071487811 RES;48.7 ,1/16W,1% ,0603,SMT
R177
271071330302 RES;33 ,1/16W,5% ,0603,SMT
R510,R572,R583,R604,R609,R611
271071499111 RES;4.99K,1/16W,1% ,0603,SMT
PR37,PR7
271071331301 RES;330 ,1/16W,5% ,0603,SMT
R145,R255,R256,R257,R258,R259
271071499211 RES;49.9K,1/16W,1% ,0603,SMT
PR11
271071331301 RES;330 ,1/16W,5% ,0603,SMT
R16,R20,R22
271071499311 RES;499K ,1/16W,1% ,0603,SMT
PR19
271071331301 RES;330 ,1/16W,5% ,0603,SMT
R18,R21,R23
271071499811 RES;49.9 ,1/16W,1% ,0603,SMT
R147,R152,R580,R647,R648,R649
271071332302 RES;3.3K ,1/16W,5% ,0603,SMT
PR76
271071510301 RES;51 ,1/16W,5% ,0603,SMT
R112,R122,R596,R597,R598,R601
271071332311 RES;332K ,1/16W,1% ,0603,SMT
PR35,PR532
271071511101 RES;510 ,1/16W,1% ,0603,SMT
PR54
271071333301 RES;33K ,1/16W,5% ,0603,SMT
PR47,PR513
271071549811 RES;54.9 ,1/16W,1% ,0603,SMT
R101,R79,R80,R89
271071343101 RES;34K ,1/16W,1% ,0603,SMT
PR92
271071560301 RES;56 ,1/16W,5% ,0603,SMT
R127,R129,R169,R176,R182,R657
271071374812 RES;37.4 ,1/16W,1% ,0603,SMT
R576
271071561101 RES;560 ,1/16W,1% ,0603,SMT
R570,R804
271071390302 RES;39 ,1/16W,5% ,0603,SMT
R123,R512,R513
271071562201 RES;56.2K,1/16W,1% ,0603,SMT
PR31
271071391302 RES;390 ,1/16W,5% ,0603,SMT
R567,R805
271071562301 RES;5.6K ,1/16W,5% ,0603,SMT
R45
271071402811 RES;40.2 ,1/16W,1% ,0603,SMT
R235,R50
271071563101 RES;56K ,1/16W,1% ,0603,SMT
R6
271071432111 RES;4.32K,1/16W,1% ,0603,SMT
R10
271071604111 RES;6.04K,1/16W,1% ,0603,SMT
R651
271071432211 RES;43.2K,1/16W,1% ,0603,SMT
PR526
271071604112 RES;604,1/16W,1% ,0603,SMT
R104,R106
271071432211 RES;43.2K,1/16W,1% ,0603,SMT
R1
271071604811 RES;60.4 ,1/16W,1% ,0603,SMT
R615,R618,R622,R625,R96,R98
271071471302 RES;470 ,1/16W,5% ,0603,SMT
PR14,R1,R196,R874
271071619111 RES;6.19K,1/16W,1% ,0603,SMT
PR518
271071471302 RES;470 ,1/16W,5% ,0603,SMT
R1
271071634111 RES;6.34K,1/16W,1% ,0603,SMT
PR530
271071472101 RES;4.7K ,1/16W,1% ,0603,SMT
R799
271071634211 RES;63.4K,1/16W,1% ,0603,SMT
PR12
271071472302 RES;4.7K ,1/16W,5% ,0603,SMT
PR51,PR53,R140,R148,R155,R220
271071681111 RES;6.81K,1/16W,1% ,0603,SMT
R21
143
9. Spare Part List
Spare Part List 4
Price(US)
Price(US)
271071681301 RES;680 ,1/16W,5% ,0603,SMT
R594
272005104402 CAP;.1U ,50V,+/-10%,0805,X7R,SMT
C8,PC42,PC43,PC7,PC8,PC86,PC9
271071681813 RES;68.1,1/16W,1%,0603,SMT
R577
272005104502 CAP;.1U ,CR,50V,20%,0805,Z5U,SM
PC24,PC35,PC40
271071698311 RES;698K ,1/16W,1% ,0603,SMT
R5
272010680301 CAP;68P,2KV,5%,1206,NPO,SMT,only
C18
271071750101 RES;75 ,1/16W,1% ,0603,SMT
R134,R135,R146,R153,R22,R25,R4
272010680401 CAP;68P ,CR,2KV,10%,1206,NPO,SM
271071750311 RES;750K,1/16W,1% ,0603,SMT
PR77
272011106409 CAP;10U,10V,+-10%,1203,X5R,SMT,T
PC34,PC511,PC541,PC74
271071753301 RES;75K ,1/16W,5% ,0603,SMT
R8
272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S
C11,C111,C112,C113,C114,C115,C
271071822102 RES;8.2K ,1/16W,1% ,0603,SMT
R14B
272011226701 CAP;22U ,CR,10V,1206,Y5V,+80~20%
C28,C32,C40,C556,C565,C759,C85
271071822301 RES;8.2K ,1/16W,5% ,0603,SMT
R138,R143,R149,R166,R173,R192
272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S
C14A,C14B
271071909101 RES;9.09K,1/16W,1% ,0603,SMT
R24
272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y
C539,C58,C608,C616,C649
271071976311 RES;976K ,1/16W,1% ,0603,SMT
PR8
272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y
C802,C96
271072287011 RES;287 ,1/10W,1% ,0603,SMT
R584
272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S
PC89,PC90
271072474101 RES;470K ,1/10W,1% ,0603,SMT
R4
272023106002 CAP;10U,25V,M,1210,T2.8MM,X5R,SM
PC507,PC508,PC519,PC520,PC52
271072474101 RES;470K ,1/10W,1% ,0603,SMT
R5
272023475401 CAP;4.7U ,25V ,10%,1210,X5R,SMT
C1
271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM
RP1,RP10,RP11,RP12,RP13,RP2,R
272030050302 CAP;5P,3KV,5%,1808,NPO,SMT,only
C19
271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT
RP16,RP17,RP18,RP19,RP20,RP2
272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT
C157,C158,C190
271586026101 RES;.02 ,2W,1%,2512,SMT
PR502,PR512
272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT
C10,C4
271611560301 RP;56*4 ,8P ,1/16W,5% ,0612,SMT
RP14,RP15
272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5
C10,C163,C173,C175,C238,C239,C
271611822301 RP;8.2K*4,8P ,1/16W,5% ,0612,SMT
RP38,RP41,RP43,RP510
272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT
C2
271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT
RP512
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM
PC533
272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT
PC17,PC501,PC62
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM
C17,C6
272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y
C14,C266,C582
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM
C12
272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y
C170,C185,C191,C20,C260,C267,C
272072104702 CAP;.1U ,16V,+80-20%,0603,Y5V,S
C139,C142,C159,C160,C161,C162
272002474401 CAP;.47U ,CR,16V ,10%,0805,X7R,S
C13,C14
272072224402 CAP;.22U ,16V ,10%,0603,X7R,SMT
PC21
272002475702 CAP;4.7U ,CR,16V ,+80-20%,Y5V,08
C2
272072334701 CAP;.33U ,CR,16V ,+80-20%,0603,Y
C743,C744,C745
272003105701 CAP;1U ,CR,25V ,+80%-20%,0805,
PC505
272072473401 CAP;.047U,16V ,10%,0603,X7R,SMT
C697
144
9. Spare Part List
Spare Part List 5
Price(US)
Price(US)
272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S
C1,C23,C28
272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT
C15A
272072683404 CAP;.068U ,16V ,10%,0603,X7R,SMT
C16
272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT
C501,C502
272073104401 CAP;.1U ,CR,25V,10%,0603,X7R,PR
C22,C7
272075339901 CAP;3.3P ,CR,50V ,+-.25PF,0603,N
C776,C777,C778,C779,C780,C781
272073104501 CAP;.1U ,25V,+80-20%,0603,Y5V,S
PC52
272075470401 CAP;47P ,50V ,10%,0603,COG,SMT
C755,PC39
272073151301 CAP;150P ,CR,25V,5% ,0603,NPO,SM
PC54
272075472701 CAP;4700P,50V ,+ -20%,0603,X7R,S
PC48,PC95
272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S
C255,C256
272101474702 CAP; .47U ,CR,10V,+80-20% ,0402,
C246,C59,C86,C89
272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S
C9
272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y
C44
272073472301 CAP;4700P,CR,50V ,5% ,0603,X7R,S
C5
272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S
C807
272075100302 CAP;10P ,CR,50V ,5%,0603,NPO,SM
C600,C603
272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343
C528,C766,PC517,PC518
272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM
C606
272431157512 CAP;150U,6.3V,+/-20%,H2.8,PT,NCC
272075101401 CAP;100P ,50V ,10%,0603,COG,SMT
C21,C23,C265,C504,C723,C735,PC
272431227402 CAP;220U,2V,-35/+10%,H1.9,S,SP-C
PC536,PC537,PC68,PC71,PC73,P
272075101401 CAP;100P ,50V ,10%,0603,COG,SMT
C20,C21
272431227510 CAP;220U ,TPC,4V,20%,H1.9,7343,S
PC514,PC53,PC542,PC543,PC58
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM
C2,C4,C711,C719,C763,C765,PC1
272601107506 EC;100U ,6.3V,M,9.3*3.6,-55~105'
C714,C715
272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S
C269
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S
PC22,PC527,PC531,PC535
272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S
CP503
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S
C11
272625470401 CP;47P*4 ,8P,50V ,10%,1206,NPO,S
CP504
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S
C13,C3,C8
273000111002 CHOKE COIL;120OHM/100MHZ,20%,321
L531,L533
272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT
C20,C21,C22
273000130038 FERRITE CHIP;600OHM/100MHZ,1608,
L3,L33,L34,L35,L4,L546
272075103702 CAP;.01U ,50V,+80-20%,0603,Y5V,S
C182,C193,C194,C195,C196,C197
L10,L11,L12,L13,L14,L16,L19,L2
272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S
C1,C100,C101,C102,C103,C105,C
L1
272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S
C24,C26,C3,C4,C5,C6
273000150002 FERRIET CHIP;120OHM/100MHZ,2012,
L21,L23,L24,L25,L26,L27,L525,L
272075200302 CAP;20P ,CR,50V ,5% ,0603,NPO,S
C24,C27
272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT
C617,C619,C808,C809,C810
273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012
L38,L41,L44,L47
272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S
C46,C49
273000150332 FERRIET CHIP;120OHM/100MHZ,2012,
L2,L37,L49,L50,L510,L541,L6,PL
272075221401 CAP;220P ,CR,50V ,10%,0603,X7R,S
C535,PC101,PC102,PC26,PC37
273000500084 CHOKE COIL;400UH(REF),D.2*1,10.5
L529
145
9. Spare Part List
Spare Part List 6
Price(US)
Price(US)
273000610019 FERRITE ARRAY;130OHM/100MHZ,3216
FA1
284506105001 IC;VT6105LOM, PCI LAN CONTROLLER
U511
273000990018 INDUCTOR;10uH,CDRH125,SUMIDA,SMT
PL503,PL504
284507011001 IC;CH7011A,TV ENCODER,LQFP,64P
U5
273000990024 INDUCTOR;47uH,CDRH127,SUMIDA,SMT
PL506
284507460002 IC;ADT7460,TEMPERATURE MTR,QSOP,
U523
273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI
PL509
284508807001 IC;AME8807AEHA,600mA,CMOS LDO,AM
PU3
273000990129 INDUCTOR;4.7UH,20%,D124C,H4.5,TO
PL510,PL511
284520715001 IC;PLL207-151,CLOCK GEN,TSSOP,56
U508
273001050028 XSFORMER;10/100 BASE,LF-H41S,SMT
U509
284582801044 IC;FW82801DBM,ICH4-M,BGA,421P
U12
273001050126 XFMR;CI8.5,25T/2150T,292mH,Varni
T1
284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8
274010800405 XTAL;8Mhz,30PPM,16PF,8*4.5,2P,SM
X2
286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT
U3
274011431409 XTAL;14.318MHZ,16PF,50PPM,8*4.5,
X1
286100212001 IC;TPA0212,AMPLIFIER,TSSOP,24P,S
U18
274011431414 XTAL;14.318MHZ,32PF,50PPM,8*4.5,
X501
286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P
PU8
274012500415 XTAL;25MHZ,20PF,30PPM,8.0*4.5,SM
X504
286104073001 IC;MAX4073F,I-SENSE AMP,SOT23,6P
PU501
274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20
X3
286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P
281101015001 IC;MP1015EM-Z,CCFL CTRL,TSSOP20,
U1
286300317010 IC;AMS3107C, VOLTAGE REGULATOR,
U10
282574008005 IC;74AHC08,QUAD 2-I/P AND,TSSOP,
U15
286300338001 IC;SC338,FET CTRL,SC,MSOP-10
PU14
282574014004 IC;74AHC14,HEX INVERTER,TSSOP,14
U2
286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2
PQ14
282574108002 IC;74AHC1G08,SINGLE AND GATE,SOT
U524,U525
286300594001 IC;TL594C,PWM CONTROL,SO,16P
PU5
282574132001 IC;74AHCT1G32,SINGLE OR GAT,SOT2
U518
286300690001 IC;GMT690B,RESET CIRCUIT,2.93V,S
U503
283467490001 IC;FLASH,512K*8,FWH,SST49LF004A,
286300809009 IC;MAX809STR,RESET CIRCUIT,2.93V
283467490002 IC;FLASH,512K*8,FWH,W39V040FAP,P
286300812002 IC;S-812C,DECECTOR,SOT-89,PRC
U1
283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM
U2
286301117021 IC;AMS1117,VOL REGULATOR,1A,SOT-
U16,U4
283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT
U515
286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR
U5
284500101006 IC;ALC101,AC97 CODEC,LQFP,48P,SM
U519
286301907001 IC;MAX1907A,PWM CONTROLLER,40-QF
PU4
284500522001 IC;855GME GMCH,NORTH BRIDGE,BGA,
U504
286302211004 IC;TPS2211A,POWER INTERFACE SW,S
U513
284501410007 IC;PCI1410A,PCI/CARDBUS,PQFP,144
U510
286302996001 IC;G2996,DDR,GMT,SOP8FD,SMT
PU10
286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF
PU13,PU2
284502996001 IC;LP2996,DDR,NS,PSOP8,SMT
146
9. Spare Part List
Spare Part List 7
286309701001 IC;RT9701,POWER DISTRI SW,SOT23-
Price(US)
U521,U522
288100014007 DIODE;SS14,40V,1A,SMA
Price(US)
288202222001 TRANS;MMBT2222AL,NPN,TO236AB
PQ9
288202237002 TRANS;MUN2237T1,NPN,SOT-23,SMT,O
PQ11,Q12,Q510,Q519,Q520
288100018003 DIODE;UDZS18B,ZENER,18V,SOD-323,
ZD3,ZD4
288202240001 TRANS;MUN2240T1,NPN,SOT-23,ON
Q1,Q15,Q18,Q19,Q2,Q20,Q5,Q525
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80
D2
288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23
Q11,Q13,Q14,Q16,Q512,Q524
288100034004 DIODE;SSA34,40V,3A,SMA
PD508,PD509,PD510,PD511
288203904010 TRANS;MMBT3904L,NPN,Tr35NS,TO236
288100054001 DIODE;BAT54,30V,200mA,SOT-23
D509,D510,D8
288203904022 TRANS;MMBT3904L,NPN,Tr35NS,TO236
Q518
288100056001 DIODE;RLZ5.6B,ZENER,5.6V,5%,LL34
D3,D507
288204406001 TRANS;AO4406,N-MOS,.0165OHM,SO8
PU506,PU507
288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM
PQ4,PQ5,PQ501,PQ6
288100056003 DIODE;BAW56,70V,215mA,SOT-23
288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM
ZD1,ZD2,ZD5
288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL,
Q2A,Q3C
288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23,
D1,D4,D5,D6,PD1,PD5
288204788001 TRANS;SI4788CY,P-MOS,5A1.8~5.5V,
U1,U501
288100070006 DIODE;BAV70LT1,70V,225MW,SOT-23,
D506,D511,PD501,PD503
288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO
PU1,PU11,PU503,PU6,PU7
288100099001 DIODE;BAV99,70V,450MA,SOT-23
288100099012 DIODE;BAV99LT1,70V,450MA,SOT-23,
288204800004 TRANS;SI4800,7A,30V,33mOHM,SO8
D611,D612,D613,PD506,PD507
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23
288204807001 TRANS;AO4807,DUAL PMOS,5A,SO8
PU505
288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM,
PU12,PU504
U3
288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP,
D503,PD4,PD512
288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035,
288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER
PD504
288204900001 TRANS;AO4900,DUAL N-MOSFET WITH
PU502,PU9
288207788001 TRANS;FDS7788,18A,30V,5mOHM,SO8
PU509,PU510
288103104001 DIODE;EC31QS04-TE12L,40V,3A,SMT
288104148001 DIODE;RLS4148,200MA,500MW,MELF,S
D7,PD3
288208107001 TRANS;TPC8107,13A/30V,P-MOSFET,S
288105520001 DIODE;BZV55-C20,ZENER,5%,SOD-80,
PD2
288221371002 TRANS;MUN2137T1,PNP,SMT,ON
PQ13
288105524003 DIODE;BZV55-C24,ZENER,5%,SOD-80,
PD502
288227002001 TRANS;2N7002LT1,N-CHANNEL FET,SO
Q527,Q528
288114148004 DIODE;1N4148WS,75V,200mW,SOD-323
D1
288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES
PQ1,PQ10,PQ12,PQ15,PQ16,PQ2
288200112002 TRANS;BSH112,N CHANNEL FET,ESD
291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
J2
288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT
291000001206 CON;MINI PCI SOCKET,P124,QTC,C10
J504
288200144002 TRANS;DTA144WK,PNP,SMT
291000011101 CON;HDR,MA,11P*1,1.25,ST,SMT
J3
288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23
291000012022 CON;HDR,MA,10P*2,1MM,H4.25,ST,SM
J1
147
9. Spare Part List
Spare Part List 8
Price(US)
291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A
J2,J503,J508,J516
291000020221 CON;HDR,MA,11P*1,1.25MM,R/A,ACES
Price(US)
295000010105 FUSE;1A,NORMAL,1206,SMT
F2,PF2
295000010110 FUSE;NORMAL,2.5A/63VDC,3216,SMT
F3
295000010120 FUSE;FAST,1.5A,63V,1206,SMT,PRC
F1
291000021104 CON;HDR,MA,11P*1,1.25,R/A,3811Y-
CN1
295000010149 FUSE;FAST,1.5A,63VDC,1206,SMT,04
291000023008 CON;HDR,FM,15P*2,0.8MM.H5,R/A,SM
J515
297004010001 SW;PUSH BUTTOM,5P,SPST,12VDC,50m
SW2,SW6,SW7
291000024421 CON;HDR,MA,22P*2,R/A,SUYIN,20038
J514
297140200002 SW;COVER SWITCH,SPST,.1A,30V,4P,
SW1
291000025028 CON;HDR,FM,25P*2,R/A,SUYIN,80094
J510
310111103011 THERMISTOR;10K,1%,RA,DISK,103AT-
T1
291000141204 CON;FPC/FFC,12P,0.5MM,H=2,ACES,S
J5
312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY
PC504,PC525,PC528
291000152603 CON;FPC/FFC,26P,1MM,R/A,KBD,SMT
J4
316677000002 PCB;PWA-LYNX/BATTERY BD,PWR
291000256827 CON;IC CARD,68P,0.635MM,62596-00
J6
316682200001 PCB;PWA-INVERTER BD (DA-1A08-B);
R0C
291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB
J505
316682800001 PCB;PWA-8089P/MOTHER BD
R01
291000616803 IC SOCKET;BANIAS m-FCBGA478P, MO
U506
322677000003 CABLE;FFC,T/P,LYNX
291000622007 CON;DIMM,R/A,200P,.6,H9.2,REVERS
J509
323767720004 DDR SODIMM MODULE;256MB,77.10634
291000810607 CON;PHONE JACK,6P,SG-2SJ-S820
J8,J9
324180786386 IC,CPU,BANIAS,1.3GHZ,MICRO-FCPGA
291000811008 CON;PHONE JACK,2 IN 1,7.0MM,ALLT
J511
331000007005 CON;BATTERY,7P,2.5MM,H9,R/A,DIP,
294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT
D15,D16,D17,D18,D19
331000007019 CON;BATTERY,7P,2.5MM,25032A-07G1
294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR
LED1
331000008068 CON;USB,FM,4P*2,R/A,MOLEX,67298-
J506,J507
294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR
LED2
331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0
J512
294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190
LED3,LED5
331720015006 CON;D,FM,15P,2.29,R/A,3ROW
J502
294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190
LED4,LED6
331870004021 CON;MINI DIN,4P,R/A,SUYIN,35144A
J501
295000010014 FUSE;1.1A/6V,POLY SWITCH,PTC,SMD
F1,F501
331910002006 CON;POWER JACK,2P,20VDC,5A,DIP
PJ501
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT
PF1
332110020042 WIRE;#20,UL1007,70MM,RED,PRC
295000010020 FUSE;NORMAL,7A/24VDC,1206,SMT
PF501
332110020067 WIRE;#20,UL1007,40MM,BLACK,PRC
295000010028 FUSE;0.14A/60V,POLY SWITCH,PTC,S
F503
332110020089 WIRE;#20,UL1007,L105mm,RED,PRC
295000010048 FUSE;0.5A/15V,POLY SWITCH,SMD
F502
332110020096 WIRE;#20,UL1007,40MM,BLACK,YIYI;
148
PJ502
9. Spare Part List
Spare Part List 9
Price(US)
332110020104 WIRE;#20,UL1007,105MM,RED,YIYI;P
340682810001 COVER ASSY;8089P
332110020108 WIRE;#20,UL1007,70MM,RED,YIYI;PW
340682810004 COVER ASSY;KB,8089P
332110026007 WIRE;#26,UL1007,80MM,YELLOW
340682810005 COVER ASSY;LCD,14",8089P
332110026124 WIRE;#26,UL1007,80MM,YELLOW,YIYI
340682810007 HOUSING ASSY;LCD,14",8089P
332110026134 WIRE;#26,UL1007,135MM,BLACK,PRC,
341677000002 SPRING;SCREW,HEATSINK,LYNX
332110026135 WIRE;#26,UL1007,40MM,ORANGE,PRC,
342503200003 CONTACT PLATE;W4L18T0.15,7521/GR
332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC
342503400004 CONTACT PLATE;W5L45T0.13,7170LI,
333050000107 SHRINK TUBE;UL,600V,105'C,ID2.5*
342503400006 CONTACT PLATE;W5L45T0.13,7170LI,
333050000120 SHRINK TUBE;600V,105'C,D0.8*9MM,
342503400007 CONTACT PLATE;W5L45T0.13 ,1/3T,7
335152000044 CFM-BAT;FUSE THERMAL 98'C
342665500010 CFM-SUYIN,S-STANDOFF,#4-40H4.8,N
335152000062 FUSE;LR4-730,POLY SWITCH,PRC
342672200010 BRACKET;CD-ROM,8500
335612000004 THERMAL CUTOFFS;378,8A/50VDC,139
342673100025 CONTACT PLATE;W5L46T0.13 ,2T,806
338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA
342677000005 BRACKET;LCD 14"QDI,L,LYNX
339115000046 MICROPHONE;-60dB+-2dB,D6.0*H2.7,
MIC1
342677000006 BRACKET;LCD 14"QDI,R,LYNX
340677000001 SPEAKER ASSY;L,LYNX
342677000014 SMT NUT;A40M20-50,EMI STOP,LYNX
340677000008 COVER ASSY;CPU,LYNX
342677000016 HINGE;LCD14 L,LYNX
340677000009 SHIELDING ASSY;HDD,LYNX
342677000017 HINGE;LCD14 R,LYNX
340677000011 COVER ASSY;HDD,LYNX
342677000019 CONTACT PLATE;W5L76T0.13 ,1/3T,L
340677000013 SPEAKER ASSY;R,LYNX
342677000022 HINGE;LCD14L,LYNX,(SZS CHINA)
340677000037 HOLDER;PCMCIA FCI-62599,BLACK,LY
Price(US)
J6
342677000023 HINGE;LCD14R,LYNX,(SZS CHINA)
340677000040 HEATSINK ASSY;BANIAS,LYNX
342677000026 HINGE;LCD14 L,LYNX-AMD(BANIAS),1
340677000044 HEATSINK ASSY;BANIAS,MPT,LYNX
342677000027 HINGE;LCD14 R,LYNX-AMD(BANIAS),1
340677000081 BEZEL ASSY;COMBO,LITEON,LSC-2408
343677100001 HEATSINK;NORTHBRIDGE,BANIAS,LYNX
340682600010 HOUSING;ASSY,8689
344503100304 DUMMY;D18L65,BATT ASSY,7521C
340682800001 SHIELDING ASSY;COVER,8089P
344677000006 COVER;DDR,LYNX
149
MTG501,MTG502
9. Spare Part List
Spare Part List 10
Price(US)
344677000007 COVER;MINIPCI,LYNX
346677000029 INSULATOR;SINGLE-FA,FOR PCB-B,LY
344677000012 COVER;HINGE,LYNX
346677000030 INSULATOR;BATT ASSY,POLY,W30L64,
344677000022 COVER;BATTERY,LYNX
346677000031 INSULATOR;FOR 3 CELLS,SINGLE-FA,
344677000023 HOUSING;BATTERY,LYNX
346677000032 INSULATOR;BATT ASSY,THERMAL FUSE
344682810004 BUTTON;T/P,8089P
346677000033 INSULATOR;M/B,HEATSINK,BAINAS,LY
345677000006 GASKET;AUDIO,LYNX
346677000034 INSULATOR;M/B,BAINAS,LYNX
345677000007 GASKET;DC_JACK,LYNX
346677000037 INSULATOR;SPEAKER,LYNX
345677000008 GASKET;TV_OUT,LYNX
346677000042 AL FOIL;LCD,BANIAS,LYNX
345677000009 GASKET;USB,LYNX
346677000043 SHIELDING;NB,BANIAS,LYNX
345677000010 GASKET;RJ_COMBO,LYNX
346677000044 INSULATOR;W8L45T0.8, DOUBLE-FA,L
345677000024 CONDUCTIVE TAPE;INSULATOR MB,LYN
346682600005 INSULATOR;T/P-BUTTON,8689
345677000029 SPONGE;HEATSINK NB,BANIAS,LYNX
346867700001 FILM;PROTECT FOR APOLLON BATTERY
346503100005 INSULATOR;5,BATTERY ASSY,7521Li
347105045025 GASKET;1,05,045,025
346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL
347108020015 GASKET;1,08,020,015
346503400503 INSULATOR;BATT ASSY,W7L13,8175
361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P
346669900004 INSULATOR;INVERTER,7170
361200003047 SOLDER PASTE;NO CLEAN,RMA,CK3000
346670500014 INSULATOR;MDC,TETRA
361400003003 JET-MELT ADHESIVES;3478-Q,5/8in*
346677000009 INSULATOR;FOR 3CELL DOUBLE-FA,LY
361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W)
346677000010 INSULATOR;W8L45, DOUBLE-FA,LYNX,
361400003021 SOLDER CREAM;NOCLEAN,P4020870980
346677000012 MYLAR;COVER,LCD,LYNX
361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA
346677000016 SPONGE;RTC,LYNX
365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14
346677000020 THERMAL PAD;DDR,LYNX
370102010204 SPC-SCREW;M2L2,NIW/NLK,K-HD
346677000026 INSULATOR;DDR,LYNX
370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK
346677000027 INSULATOR;PCMCIA,LYNX
370102010502 SPC-SCREW;M2 L5,NIB,K-HD,t0.8,NL
346677000028 INSULATOR;SINGLE-FA,FOR PCB-A,LY
370102010502 SPC-SCREW;M2 L5,NIB,K-HD,t0.8,NL
150
Price(US)
9. Spare Part List
Spare Part List 11
Price(US)
Price(US)
370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
413000020416 LCD;HT14X19-100,TFT,14.1",LVDS,X
416268282001 LT PF;14",ID2,HYDIS,HT14X19-100,
422677000005 WIRE ASSY;INVERTER,LYNX
370102610303 SPC-SCREW;M2.6L3,KHD,D4.4,t0.45,
422677000006 WIRE ASSY;MDC.LYNX
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N
422677000008 WIRE ASSY;BATT TO MB,FOR LYNX,MO
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,
422677000011 WIRE ASSY;MDC.LYNX,KAI CHI
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,
422677000012 WIRE ASSY;LCD 14",HYUNDAI,LYNX
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
422681400031 WIRE ASSY;ANTENNA,MPT,CALYPSO
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
422681400032 WIRE ASSY;ANTENNA,HANNSTAR,CALYP
370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3
431682820001 CASE KIT;8089P,ID2
371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK
441682800075 BATT ASSY;8089/10.8V,4AH,PANASON
371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK
441682820001 LCD ASSY;14",ID2,HYDIS,HT14X19-1
373101722501 T-SCREW;B,M1.7,L2.5,KHD(+),T0.5,
442672600031 AC ADPT ASSY;19V,3.16A,DELTA,706
411682200001 PWA;PWA-INVERTER BD,DA-1A08-B,PW
442677000031 TOUCH PAD MODULE;TM41PUF1311-2
411682200002 PWA;PWA-INVERTER BD,SMT,DA-1A08-
442682800001 BATT ASSY;10.8V/4.0AH,LI,PANASON
411682200003 PWA;PWA-INVERTER BD,SMT TOP,DA-1
451677000091 HDD ME KIT;LYNX-AMD
411682200004 PWA;PWA-INVERTER BD,SMT BOT,DA-1
451682800051 LABEK KIT;ID2,N-B,8089P
411682800012 PWA;PWA-8089/BATT PANASONIC,6CEL
451682800071 ROM ME KIT;8089
411682800013 PWA;PWA-8089/BATT PANASONIC,6CEL
451682820001 LCD ME KIT;14",ID2,HYDIS,HT14X19
411682810001 PWA;PWA-8089P,MB
451682820031 HOUSING KIT;8089P,ID2
411682810002 PWA;PWA-8089P,T/U
461682800012 PACKING KIT;8089/10.8V,4AH,PANAS
411682810003 PWA;PWA-8089P,MB,SMT
461682810001 PACKING KIT;N-B,8089P
412672300001 PCB ASSY;FAX MODEM 56K,MDC56S-I,
481682810001 F/W ASSY;SYS/VGA BIOS,8089P
U512
412673400008 PCB ASSY;MINI-PCI,TYPE IIIB,INTE
481682810002 F/W ASSY;KBD CTRL,8089P
U7
412682200001 PCB ASSY;INVERTER BD,DA-1A08-B,P
523405320072 HDD DRIVE,40GB,2.5",IC25N040ATMR
151
9. Spare Part List
Spare Part List 12
Price(US)
523430061007 DVD COMBO DRIVE;24x24x8X24,LSC24
523468280032 HDD ASSY;40G,IC25N040ATMR04-0,HG
523468300001 DVD COMBO ASSY;24X,LITEON,LSC-24
526268282001 LTXNX;8089P/4HAI/40M/1US0/O5D3B/
531020237826 KBD;88,US,K011718M4,8089P
541668281031 AK;8089P,UTILITY ONLY
541668281033 AK;BOX,8089P,UTILITY ONLY
565168281001 S/W;CD ROM,SYSTEM DRIVE,8089P
600100010005 SOLDER WIRE;63/37,0.8,NA,N/C,PRC
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
622200000008 TAPE;CARTON,2.5"W,30M/RL,PRC
627207522141 CAP;220P ,50V ,10%,0603,X7R,SMT
C25
628820014401 TRANS;DTA144EKA,PNP,100MA,50V,SO
Q6,Q7
P/N: 526268282001
152
9. Spare Part List
Spare Part List 12
523430061007 DVD COMBO DRIVE;24x24x8X24,LSC24
523468280032 HDD ASSY;40G,IC25N040ATMR04-0,HG
523468300001 DVD COMBO ASSY;24X,LITEON,LSC-24
526268282001 LTXNX;8089P/4HAI/40M/1US0/O5D3B/
531020237826 KBD;88,US,K011718M4,8089P
541668281031 AK;8089P,UTILITY ONLY
541668281033 AK;BOX,8089P,UTILITY ONLY
565168281001 S/W;CD ROM,SYSTEM DRIVE,8089P
600100010005 SOLDER WIRE;63/37,0.8,NA,N/C,PRC
622200000008 TAPE;CARTON,2.5"W,30M/RL,PRC
C25
Price(US)
627207522141 CAP;220P ,50V ,10%,0603,X7R,SMT
Q6,Q7
628820014401 TRANS;DTA144EKA,PNP,100MA,50V,SO
P/N: 526268282001
154
5
4
3
2
1
REV
8089P Stack Up
VT6105L
IDSEL: AD18
PCI REQ1#
PCI GNT1#
PCI INTE#
4 mil
6 mil
7 mil
6 mil
Mini PCI
IDSEL: AD17
PCI REQ2#
PCI GNT2#
PCI INTD# INTF#
7 mil
6 mil
4 mil
0.5 oz Cu
GND
0.5 oz Cu
In1
0.5 oz Cu
In2
0.5 oz Cu
PWR
0.5 oz Cu
In3
0.5 oz Cu
GND
0.5 oz Cu
Solder
0.5 oz Cu
Initail release (base on Lynx Banias)
R0A
1. Remove power VDD5S and add SVDD3 for software standby power.
2. Fix 5 KBC signals pull hi voltage from VDD3 to SVDD3.
3. Fix signal "LPCCLK_KBC" from 48MHz to 33MHz.
4. Reserve signal "SUPERIO_48M" for software debug.
5. Fix signal "HINIT#" pull hi voltage from Vcore to +VCCP.
6. Fix Inverter LED power from VDD5S to VDD3.
7. Add Celeron_Banias CPU power saving circuit.
8. Fix Vcore circuit short issue.
9. Signal BAT_T and BAT_V pull hi voltage to SVDD3 in page 18
and page 23.
10.Inverter power add a PMOS to turn on power.
11.Signal "Wireless_LED#" control changed from KBC to BIOS.
12.+1.5V_P and +1.35_P power turn on control changed form SUSB#
to PWRON_1.35V_1.5V.
13.KBC add 2 NA pins.
14.USB circuit change resistor from 33K & 47K to 390 & 560 to
speedy discharge time.
15.Remove D506 to disable ENABLE_BKLT controled by LID#.
16.Remove U17 for cost down.
17.Use 24.576MHz oscillator instead of codec clock which come
from clock gen. to fix audio EMI issue.
18.Use 0 ohm to instead of bead between GND & AGND in audio for
EMI recommendation.
PCI1410A
IDSEL: AD19
PCI REQ0#
PCI GNT0#
PCI INTB#
GND
16
15
14
13
12
GND
C
ETP9
TOUCHPAD_METAL5
ETP10
TOUCHPAD_METAL5
ETP1
TOUCHPAD_METAL5
GND
1
GND
ETP8
TOUCHPAD_METAL5
1
GND
GND_USB
GND
GND
AGND
1
9
10
11
4
5
6
7
8
GND
G115930372
ETP4
ETP5
TOUCHPAD_METAL5TOUCHPAD_METAL5
1
16
15
14
13
12
9
10
11
4
5
6
7
8
3
2
1
16
15
14
13
12
GND
MTG13
ID3.0/OD9.0
2004/2/5
9
10
11
4
5
6
7
8
3
2
1
3
2
1
16
15
14
13
12
9
10
11
4
5
6
7
8
MTG14
ID3.0/OD9.0
D
1
MTG3
ID3.0/OD11
MTG118-RD433-N-30X16
3
2
1
MTG1
ID3.0/OD11
MTG118-RD433-N-30X16
1. Change SUSB# pull hi from VDD3 to SVDD3 for support RTC wake
up.
2. Correct NUM#,CAP#,SCROLL# pull hi from +5V to +3V.
3. Change R234,R235 resistance for stable VDD1.5 voltage.
4.Use internal clock from clock gen. to instead X'tal.
5.Add C507 to fix audio noise.
6. Change PC95 to let 1.05V later.
7.Add U524,U525 to improve VESA quality.
8.Change X501 to fix clock timing.
ECR No.
1
MTG4
ID3.0/OD11
MTG118-RD433-N-30X16
1
MTG2
ID3.0/OD11
MTG118-RD433-N-30X16
C
R01
ETP3
TOUCHPAD_METAL5
1
1
1
ETP6
ETP7
TOUCHPAD_METAL5 TOUCHPAD_METAL5
DATE
R00
1
D
Comp
Change detail
16
15
14
13
12
4
5
6
7
8
GND
3
2
1
3
2
1
4
5
6
7
8
16
15
14
13
12
16
15
14
13
12
ETP505
TOUCHPAD_METAL5
GND
ETP502
TOUCHPAD_METAL5
MTG17
1
1
9
10
11
9
10
11
9
10
11
4
5
6
7
8
GND
1
1
GND
1
1
GND
Used for MDC
16
15
14
13
12
MTG/ID5.2/OD7.0
MTG16
MTG/ID5.2/OD7.0
FD504
FIDUCIAL-MARK
CAGND
8
6
GND
5
7
3
4
2
6
5
7
3
4
2
GND
GND
1
FD502
FIDUCIAL-MARK
1
FD503
FIDUCIAL-MARK
1
FD501
FIDUCIAL-MARK
1
FD3
FIDUCIAL-MARK
1
FD2
FIDUCIAL-MARK
1
1
FD4
FIDUCIAL-MARK
GND
ETP2
TOUCHPAD_METAL5
1
1
GND
ETP507
TOUCHPAD_METAL5
1
1
GND
8
GND
GND
1
GND
ETP15
TOUCHPAD_METAL5
B
GND
MTG10
ID3.0/OD11
MTG118-RD433-N-30X16
MTG12
ID3.0/OD11
MTG118-RD433-N-30X16
3
2
1
3
2
1
4
5
6
7
8
16
15
14
13
12
GND
FD1
FIDUCIAL-MARK
GND
ETP503
TOUCHPAD_METAL5
MTG9
ID3.0/OD11
MTG118-RD433-N-30X16
9
10
11
4
5
6
7
8
ETP13
TOUCHPAD_METAL5
GND_RJ11
GND
MTG11
ID3.0/OD11
MTG118-RD433-N-30X16
GND
ETP12
TOUCHPAD_METAL5
MTG501
MTG502
MTG/ID1.2/OD4.6 MTG/ID1.2/OD4.6
9
10
11
9
10
11
16
15
14
13
12
AGND
AGND
B
GND
ETP501
TOUCHPAD_METAL5
3
2
1
4
5
6
7
8
16
15
14
13
12
9
10
11
9
10
11
4
5
6
7
8
GND_USB
1
MTG15
ID3.0/OD11
MTG118-RD433-N-30X16
3
2
1
3
2
1
16
15
14
13
12
1
GND
MTG7
ID3.0/OD11
MTG118-RD433-N-30X16
MTG8
ID3.0/OD11
MTG118-RD433-N-30X16
3
2
1
3
2
1
16
15
14
13
12
9
10
11
4
5
6
7
8
4
5
6
7
8
1
MTG5
ID3.0/OD11
MTG118-RD433-N-30X16
MTG6
ID3.0/OD11
MTG118-RD433-N-30X16
A
A
8
1
MTG19 MTG/ID5.2/OD7.0
8
1
MTG18 MTG/ID5.2/OD7.0
6
5
7
3
4
2
6
5
7
3
4
2
Title
Mounting Hole
Size
C
GND
GND
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
Thursday, February 05, 2004 Sheet
1
2
of
29
5
4
3
2
1
U506C
VCC : PROCESSOR CORE POWER SUPPLY.
VCCA : ISOLATE POWER FOR INTERNAL PLL.
U506B
3
Q17
1
0/NA
VID[0..4]
VID[0..4]
CPUVID5
2 R133
0603
1
1
2
1
1
1
TEMP_ALERT#
1%
1
0603
1%
1
0603
TEMP_ALERT# 10,20
DTC144TKA/NA
GND
2 R80
54.9
2 R79
54.9
E2
F2
F3
G3
G4
H4
AE7
AF6
4
1
C71
10U
1206
10V
2
1
C72
10U
1206
10V
2
1
C73
10U
1206
10V
2
1
2
1
2
1
C55
10U
1206
10V
1
2
1
C562
10U
1206
10V
2
1
2
C561
10U
1206
10V
C152
10U
1206
10V
B
VCCA0
VCCA1
VCCA2
VCCA3
VID0
VID1
VID2
VID3
VID4
VID5
VCCSENSE
VSSENSE
BANIAS
BGA479_SKT3
GND
3
1
1
C144
0.1U
0603
50V
C145
0.1U
0603
50V
2
1
C120
0.1U
0603
50V
2
1
C130
0.1U
0603
50V
2
1
C108
0.1U
0603
50V
2
C105
0.1U
0603
50V
2
1
GND
1
C82
0.1U
0603
50V
C81
0.1U
0603
50V
2
1
C80
0.1U
0603
50V
2
1
C62
0.1U
0603
50V
2
1
C63
0.1U
0603
50V
2
1
C64
0.1U
0603
50V
2
1
2
C156
10U
1206
10V
2
+VCCP
+VCCP
GND
C131
0.1U
0603
50V
C568
0.1U
0603
50V
1
1
1
1
C119
0.1U
0603
50V
2
C567
0.1U
0603
50V
2
C569
0.1U
0603
50V
2
C575
10U
1206
10V
1
C572
10U
1206
10V
2
C573
10U
1206
10V
1
C574
10U
1206
10V
1
C571
10U
1206
10V
C122
0.1U
0603
50V
2
GND
C146
0.1U
0603
50V
+VCC_CORE
1
C155
10U
1206
10V
C147
0.1U
0603
50V
2
1
1
C115
10U
1206
10V
2
C154
10U
1206
10V
2
1
1
2
2
1
C153
10U
1206
10V
C114
10U
1206
10V
2
C558
10U
1206
10V
C113
10U
1206
10V
2
C559
10U
1206
10V
C112
10U
1206
10V
1
C111
10U
1206
10V
2
C560
10U
1206
10V
+VCC_CORE
1
+VCC_CORE
1
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
2
VCCQ0
VCCQ1
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
C121
0.1U
0603
50V
GND
A
GND
+1.8V
+1.5V
+VCCA
L17 1
2 0/NA 0805
L18 1
2 0 0805
C58
2.2U
1206
16V
C129
0.1U
0603
50V
GND
C138
0.1U
0603
50V
Title
Size
C
GND
Date:
5
2
2
2
1
1
1
2
29
VID0
VID1
VID2
VID3
VID4
C148
10U
1206
10V
2
F26
B1
N1
AC26
C74
10U
1206
10V
1
+VCCA
C75
10U
1206
10V
GND
VCCP_0
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_8
VCCP_9
VCCP_10
VCCP_11
VCCP_12
VCCP_13
VCCP_14
VCCP_15
VCCP_16
VCCP_17
VCCP_18
VCCP_19
VCCP_20
VCCP_21
VCCP_22
VCCP_23
VCCP_24
2
P23
W4
2
2
1
C149
10U
1206
10V
C76
10U
1206
10V
1
+VCCQ
1.8V, Option to 1.5V
for future support.
R132
10K/NA
0603
R1
HPROCHOT#
C150
10U
1206
10V
2
Celeron Banias CPU
1
2
R127
56
0603
C77
10U
1206
10V
1
Banias CPU
GND
+3V
1
+VCCP
C151
10U
1206
10V
1
0
power on default = 1
+VCCP
C53
10U
1206
10V
2
B/CB#
GPIO16
A
C54
10U
1206
10V
2
C123
0.1U
0603
50V
G
S
1
GND
C78
10U
1206
10V
1
1
C110
0.1U
0603
50V
G
BAT54
C79
10U
1206
10V
2
2
C116
10U
1206
10V
2
120Z/100M
2012
D
1
2
2
2
GND
D
S
D 2
D8
+VCCQ
L21
1
1
1
+VCCP
S
C56
10U
1206
10V
2
G
R107
10K
0603
SI2301DS
D Q21
S
2N7002
G
4,5,9,29 STOP_CPU#
29
1
VID5
Q13
3
C57
10U
1206
10V
1
2N7002
D
B/CB#
1
GND
U506D
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21
C
Core power decoupling
+VCC_CORE
PLACEMENT MAX. 3" FROM CPU.
0603
D
BANIAS
BGA479_SKT3
+VCC_CORE
Don't overlay by CHOKE or vibrating signals.
+VCCP
2 0/NA
D
S
8,9
R111
1K
0603
C136
10U
1206
10V
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
GND
CPU_THRMTRIP_OUT# 10
Q10
+1.5V
C132
10U
1206
10V
1
CPU_THERMDA 20
CPU_THERMDC 20
C124
10U
1206
10V
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
1
HINIT#
C125
10U
1206
10V
2
CPU_THERMDA
CPU_THERMDC
5
5
+VCCP
C135
10U
1206
10V
2
HDPSLP#
HSLP#
HDBSY#
HDRDY#
C134
10U
1206
10V
1
HSTPCLK#
C133
10U
1206
10V
1
HNMI
HSMI#
(1.05V)
R102 1
S
1
200/NA
1
200/NA
1
200/NA
1
200/NA
1
200/NA
1
200/NA
1
200/NA
1
200/NA
1
200/NA
HINTR
BANIAS
BGA479_SKT3
CPUVID5
200
HIGNNE#
HDSTBP#[0..3] 5
2 R656
0603
2 R119
0603
2 R128
0603
2 R117
0603
2 R114
0603
2 R120
0603
2 R113
0603
2 R115
0603
2 R131
0603
2 R121
0603
1
CPUPERF#
2
1
2
1
1
9
HDSTBN#[0..3] 5
HDSTBP#[0..3]
BANIAS
BGA479_SKT3
+VCCP
2
HA20M#
C17
THERMTRIP#
2
1
+3V
R602
HDBR#
1
10K/NA
0603
1
B18
A18
THERMDA
THERMDC
ITP_CLK0
ITP_CLK1
Close to CPU as possible.
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
2
A16
A15
4 CLK_ITP_CPU
4 CLK_ITP_CPU#
B
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18
2 CPU_TEST3
GND
M2
H2
DBSY#
DRDY#
INIT#
RESET#
C22
L24
W24
AE25
+VCC_CORE
2 CPU_TEST2
1
B5
B11
LINT0
LINT1
0603
2 CPU_TEST1
R603
1
1K 1%
R116
1
1K 1%
R126
1
1K 1%
2
HINIT#
HINIT#
HCPURST#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
0603
2
D1
D4
STPCLK#
DPSLP#
0603
1
HINTR
HNMI
PROCHOT#
DINV0#
DINV1#
DINV2#
DINV3#
2
C6
B7
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
D25
J26
T24
AD20
GND
HDSTBN#[0..3]
C23
K24
W25
AE24
HDINV#0
HDINV#1
HDINV#2
HDINV#3
1
HINTR
HNMI
B17
HSTPCLK#
HDPSLP#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
HDINV#[0..3]
HCOMP3
2
9
9
HPROCHOT#
IGNNE#
SMI#
PWRGOOD
5
HCOMP2
TEST1
TEST2
TEST3
HDINV#[0..3]
1
HSTPCLK#
HDPSLP#
A3
B4
E4
1
1
HCOMP1
2
9
5,9
HIGNNE#
HSMI#
HPWRGD
54.9
1%
2 R100
0603
2 R101
0603
2 R87
0603
2 R89
0603
RSVD_2
RSVD_3
C5
F23
C16
2
HIGNNE#
HSMI#
HPWRGD
1
1
CPU_TEST1
CPU_TEST2
CPU_TEST3
HCOMP0
1
9
9
9
TP1
HDBR#
HSLP#
HPSI#
A20M#
FERR#
DPWR#
DBR#
SLP#
PSI#
1
RSVD_0
C14
C3
2
HSLP#
C2
D3
C19
A7
A6
E1
27.4
54.9
1%
27.4
HCOMP1 & HCOMP3 should be
route with 5 mil width
1
9
HA20M#
RS0#
RS1#
RS2#
AF7
HCOMP0 & HCOMP2 should be
2
HA20M#
HFERR#
HDPWR#
H1
K1
L2
IERR#
HIT#
HITM#
DEFER#
TRDY#
GND
COMP0
COMP1
COMP2
COMP3
1
HRS#0
HRS#1
HRS#2
HRS#[0..2]
9
10
5
A4
K3
K4
L4
M3
BR0#
BPRI#
BNR#
LOCK#
P25
P26
AB2
AB1
2
HHIT#
HHITM#
HDEFER#
HTRDY#
HRS#[0..2]
9,20
4,5
2 56
0603
ADSTB0#
ADSTB1#
HCOMP0
HCOMP1
HCOMP2
HCOMP3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
1
R129 1
N4
J3
L1
J2
R566
2K
0603
1%
C532
1U
0603
2
5
5
5
5
U3
AE5
HBR0#
C535
220P
0603
10%
1
HBR0#
HBPRI#
HBNR#
HLOCK#
AD26
E26
G1
AC1
Close to CPU as possible.
2
HADSTB#0
HADSTB#1
5
5
5
5
TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#
1
5
5
ADS#
A13
C12
A12
C11
B13
B10
A10
2
HADS#
+VCCP
5
N2
5
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
HTCLK
HTDI
HTDO
HTMS
HTRST#
HPREQ#
HPRDY#
1
C
R2
P3
T2
P1
T1
R569
1K
0603
1%
0603 1
0603 1
HTCLK
HTDI
HTDO
HTMS
HTRST#
HPREQ#
HPRDY#
2
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
4
4
4
4
4
4
4
1
HREQ#[0..4]
+VCCP
2
5
HREQ#[0..4]
0
0
HD#[0..63] 5
BPM0#
BPM1#
BPM2#
BPM3#
1
HPWRGD
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
2
2
R110
300
0603
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
2
1
+VCCP
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
2
D
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
D6
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18
F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
BCLK0
BCLK1
C8
B8
2 R599 A9
2 R600C9
2
HD#[0..63]
U506A
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
B15
B14
HCLK_CPU
HCLK_CPU#
HBPM#0
HBPM#1
HBPM#0
HBPM#1
2
HA#[3..31]
HA#[3..31]
4
4
2
4
4
VCCQ : QUIET POWER SUPPLY FOR ON DIE COMP CKT.
2
VCCP : PROCESSOR I/O POWER SUPPLY.
5
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
+VCC_CORE
2
CPU
Document
Number
Rev
01
411682810001
1
3
of
29
5
4
3
2
1
+3V
0
0
0
0
0
1
1.692
1
0
0
0
0
1
1.180
0
0
0
0
1
0
1.676
1
0
0
0
1
0
1.164
0
0
0
0
1
1
1.660
1
0
0
0
1
1
1.148
0
0
0
1
0
0
1.644
1
0
0
1
0
0
1.132
0
0
0
1
0
1
1.628
1
0
0
1
0
1
1.116
0
0
0
1
1
0
1.612
1
0
0
1
1
0
1.100
0
0
0
1
1
1
1.596
1
0
0
1
1
1
1.084
0
0
1
0
0
0
1.580
1
0
1
0
0
0
1.068
0
0
1
0
0
1
1.564
1
0
1
0
0
1
1.052
0
0
1
0
1
0
1.548
1
0
1
0
1
0
1.036
0
0
1
0
1
1
1.532
1
0
1
0
1
1
1.020
0
0
1
1
0
0
1.516
1
0
1
1
0
0
1.004
0
0
1
1
0
1
1.500
1
0
1
1
0
1
0.988
0
0
1
1
1
0
1.484
1
0
1
1
1
0
0
0
1
1
1
1
1.468
1
0
1
1
1
1
0
1
0
0
0
0
1.452
1
1
0
0
0
0
1
0
0
0
1
1.436
1
1
0
0
0
1
0
0
1
0
1.420
1
1
0
0
1
0
0
1
1
1.404
1
1
0
1
0
1
0
0
1.388
1
1
0
1
0
1
0
1
1.372
1
1
R597
51
0603
R601
51
0603
R598
51
0603
R124
51/NA
0603
1
1
FS0
FS1
FS2
1
2
R140
4.7K
0603
GND
R594
680
0603
FS0
CPU
0
0
166.66
66.66
33.33
0
1
100.00
66.66
33.33
X
1
0
200.00
66.66
33.33
X
1
1
133.33
66.66
33.33
0.972
Mid
0
0
Tristate
Tristate
Tristate
0.956
Mid
0
1
TCLK/2
TCLK/2
TCLK/2
0
0.940
Mid
1
0
Reserved
Reserved
Reserved
0
1
0.924
Mid
1
1
Reserved
Reserved
0
1
0
0.908
0:0V
1:3.3V
0
0
1
1
0.892
0
1
0
0
0.876
0
1
0
1
0.860
001
GND
0
0
1.324
1
1
1
0
0
0
0.812
0
0
1
1.308
1
1
1
0
0
1
0.796
1
0
1
0
1.292
1
1
1
0
1
0
0.780
0
1
1
0
1
1
1.276
1
1
1
0
1
1
0.764
0
1
1
1
0
0
1.260
1
1
1
1
0
0
0.748
0
1
1
1
0
1
1.244
1
1
1
1
0
1
0.732
0
1
1
1
1
0
1.228
1
1
1
1
1
0
0.716
1
C600
10P
0603
5%
1
1
1
1
0.700
7,10
7,10
29
30
SMBDATA
SMBCLK
FS0
FS1
FS2
54
55
40
+3V
R605 1
R138 1
R149 1
1
+3V
R137
10K
0603
1%
2 8.2K
2 8.2K
2 8.2K
+3V
0603D
0603D
0603D
8.2K
2 R143
VTT_PWRGD#
+3VCLKANA
2
0
1
0603
29 CORE_CLKEN#
CLK_PCI_STOP#
CLK_CPU_STOP#
1
+3VCLK66
B
+3VCLKCPU
46
50
+3VCLKPCI
3,5,9,29 STOP_CPU#
9
STOP_PCI#
1
0603
2 R157
0/NA
CLK_CPU_STOP#
1
0603
2 R139
0/NA
CLK_PCI_STOP#
43
28
1
37
26
19
32
VTT_PWRGD#
2
R136
25
34
53
8
14
4
9
15
20
27
31
36
41
47
X1
48MHZ_USB
48MHZ_DOT
X2
2
14M_CODEC 12
14M_ICH 9
3V66_1/VCH_CLK
SDATA
SCLK
REF
FS0
FS1
FS2
CPUCLKT0
CPUCLKT1
CPUCLKT2
*PD#
PCI_STOP#
CPU_STOP#*
MULTSEL0*
VTT_PWRGD#
VDDREF
VDD48
VDDA
VDD3V66_0
VDD3V66_1
VDDCPU0
VDDCPU1
CPUCLKC0
CPUCLKC1
CPUCLKC2
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI0
VDDPCI1
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
66MHZ_OUT0/3V66_2
66MHZ_OUT1/3V66_3
66MHZ_OUT2/3V66_4
3V66_0
66MHZ_IN/3V66_5
IREF
35
56
HCLK_MCH# 5
HCLK_MCH 5
2 R604
1
0603 33
1
0603 33
2 R642
R630
R638
2 0603D
2 0603D
1
1
52
49
45
33/NA 0603 1
0603 27.4 1
0603 27.4 1
2 R639
2 R626
2 R619
0603 49.9 1
1% 0603 60.4 1
1% 0603 60.4 1
1%
51
48
44
33/NA 0603 1
0603 27.4 1
0603 27.4 1
2 R631
2 R623
2 R616
0603 49.9 1
1% 0603 60.4 1
1% 0603 60.4 1
1%
10
11
12
13
16
17
18
0603
0603
0603
0603
0603
5
6
7
21
22
23
1
133
133
133
133
33
2
2
2
2
2
0/NA
0/NA
2 R152
2 R625
2 R618
CLK_ITP_CPU# 3
CLK_ITP_CPU 3
2 R147
2 R622
2 R615
C601
10P/NA
0603
10%
C590
10P/NA
0603
10%
C592
10P/NA
0603
10%
GND
R627
R621
R620
R617
R510
PCICLK_LAN 15
PCICLK_BIOS 20
PCICLK_MINIPCI 16
PCICLK_CARD 17
LPCCLK_KBC 18
1
0603 33
2 R632
1
0603 133
0603 33
2 R612
2 R609
C812
10P/NA
0603
10%
C596
10P/NA
0603
10%
C597
10P/NA
0603
10%
C594
10P/NA
0603
10%
C595
10P/NA
0603
10%
B
Remind BIOS don't turn off.
GND
PCICLK_ICH
9
66M_MCH 5
66M_ICH 10
33
24
42
PLL207-151
TSSOP56
C588
10P/NA
0603
10%
C591
10P/NA
0603
10%
C599
10P/NA
0603
10%
R142
475
0603
1%
GND
2
GND
HCLK_CPU# 3
HCLK_CPU 3
39
38
1
1
3
2
1
2
1
1.212
Layout note: Place crystal within
500 mils of CLK Gen.
2
1
GND
U508
1
1
2 C606
10P
2 R644
33
1
0603
GND
1
0603
10%
1
0
1
1
C
VCH_CLK
2
1
1
0
2
1
1
0
C586
10P/NA
1
0603
10%
2
0
R613 R611 R610
33
33
33/NA
0603 0603 0603
1
0.828
2
1
1
1
2
1
1
0
2
1
1
1
2
1.340
C589
10P/NA
0603
10%
1
1
2
1
1
1
2
0
1
1
Reserved
48M_DREFCLK 5
USBCLK_ICH 10
SUPERIO_48M 16
2
0
PCI*
UNIT: MHz
2
2
0.844
1
0
2
1
1
1
2
0
1
1
1
1
2
1.356
3V66[5:0]
X501
14.31818MHZ
X502
1
3
2
4
14.318MHZ/NA
C603
10P
0603
5%
1
0
GND
Place close to CPU socket within 2".
2
1
2
FS1
1
1
D
X
0
1
R154
4.7K/NA
0603
X
1
1
R155
4.7K
0603
FS2
0
0
1
R141
R159
R148
4.7K/NA 4.7K/NA 4.7K
0603
0603
0603
R122
51
0603
2
2
2
2
HTRST#
HTCLK
R125
150
0603
R123
39
0603
1
3
3
2
HPREQ#
HPRDY#
HBPM#1
HBPM#0
HTDO
HTMS
HTDI
HCPURST#
1
3
3
3
3
3
3
3
3,5
R595
27.4
0603
1
C
R596
51
0603
2
1.196
2
VCC-Core
0
1
0
0
1
1
0
2
2
0
2
3
0
2
4
1
2
5
1.708
2
1
VCC-Core
0
1
0
0
2
1
0
1
2
0
1
3
0
1
4
0
1
5
2
D
VID
1
+VCCP
1
+VCC_CORE
VID
+3V
+3VCLKANA
L532
+3V
+3VCLKCPU
C189
0.1U
0603
50V
C185
2.2U
0805
+80-20%
GND
GND
+3V
+3VCLKPCI
9,18,20,22,25,26,27,29
L27
+3VCLK66
L25
VCH_CLK
1
1
2
R636 0/NA
SMBDATA
SMBCLK
8
6
7
2
CLKIN
**CLKOUT/FS_IN0
*REF_OUT/FS_IN1
*PD#
VDD
SDATA
SCLK
GND
4
5
66M_DEFSSCLK 5
+3V
A
2
3
ICS91718/NA
SO8
1
C186
0.1U
0603
50V
C191
2.2U
0805
+80-20%
R606
10K/NA
0603
2
C188
0.1U
0603
50V
2
1
1
120Z/100M
2012
2
C234
0.1U
0603
50V
2
C170
2.2U
0805
+80-20%
2
1
C183
0.1U
0603
50V
2
1
C172
0.1U
0603
50V
2
1
1
2
120Z/100M
2012
2
1
1
C169
0.1U
0603
50V
1
SUSB#
R607 33/NA
1
2
1
2
R635 10K/NA
U507
1
+3V
2
R608
0
0603
GND
A
1
VCH_CLK
1
1
C187
0.1U
0603
50V
2
2
C171
0.1U
0603
50V
2
GND
2
120Z/100M
2012
1
2
C607
2.2U
0805
+80-20%
2
1
C184
0.1U
0603
50V
2
1
C587
0.1U
0603
50V
2
2
C602
0.1U
0603
50V
2
1
1
2
1
1
C605
0.1U
0603
50V
GND
L26
2
120Z/100M
2012
1
1
Title
GND
GND
GND
GND
GND
Size
C
Date:
5
4
3
2
Clock generator
Document
Number
Rev
01
411682810001
1
4
of
29
5
4
3
2
+VCC_CORE
1
ADD ID : 0x7Fh
HADSTB#0
HADSTB#1
B20
B18
H28
K28
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
K27
D26
E21
E18
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
J28
C27
E22
D18
HDINV#0
HDINV#1
HDINV#2
HDINV#3
J25
E25
B25
G19
HXRCOMP
HXSWING
HYRCOMP
HYSWING
HDSTBP#[0..3]
3 HDSTBP#[0..3]
HDSTBN#[0..3]
3 HDSTBN#[0..3]
HDINV#[0..3]
3 HDINV#[0..3]
3
3
3
3
3
3
3
3
3
3
3
HADS#
HTRDY#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBR0#
HBNR#
HBPRI#
HDBSY#
HRS#[0..2]
B
3
HXRCOMP
HXSWING
HYRCOMP
HYSWING
HRS#[0..2]
3,4 HCPURST#
9,18 PWROK
HDSTBN[0]#
HDSTBN[1]#
HDSTBN[2]#
HDSTBN[3]#
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
L28
M25
N24
M28
N28
N27
P27
M23
N25
P28
M26
N23
P26
M27
F15
J11
HBR0#
HRS#0
HRS#1
HRS#2
1
R68
HDSTBP[0]#
HDSTBP[1]#
HDSTBP[2]#
HDSTBP[3]#
2
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS[0]#
RS[1]#
RS[2]#
CPURST#
PWROK
0
HDVREF[0]
HDVREF[1]
HDVREF[2]
HAVREF
HCCVREF
1
2
F7
AE29
AD29
D5
Y23
AA22
B7
AGPBUSY#
HCLK_MCH
HCLK_MCH#
D
S
14
14
14
G14
E15
C15
C13
F14
E14
C14
B13
H12
E12
C12
G11
G12
E11
C11
G10
TXOUT0TXOUT1TXOUT2-
14
14
14
TXOUT0+
TXOUT1+
TXOUT2+
GND
1
2
R519
0/NA
Place near to GMCH.
DVOVREF
C522
0.1U
0603
50V
14
14
TXCLKOUT0TXCLKOUT0+
4
8
66M_MCH
DVOVREF
D14
E13
E10
F10
DDR_EXTTS#
GND
HUB_HI0
HUB_HI1
HUB_HI2
HUB_HI3
HUB_HI4
HUB_HI5
HUB_HI6
HUB_HI7
HUB_HI8
HUB_HI9
HUB_HI10
+VCCP
10
10
HAVREF
HCCVREF
C60
0.1U
0603
50V
C67
0.1U
0603
50V
C65
1U
0603
HUB_MCH_VREF
HUB_RCOMP
9 MCH_PCIRST#
R67
100
0603
1%
14
14
REFSET
CRT_DDDA
CRT_DDCK
1
2
1R521 10K 2
R522 10K
+3V
GND
855GM/GME
BGA707_25
14
CRT_R
14
CRT_G
14
CRT_B
W1
T2
AD28
E8
G9
B6
B4
C5
A7
A8
C8
D8
C9
D9
GND
H10
J9
14 CRT_HSYNC
14 CRT_VSYNC
Non SSC
W/ SSC
U7
U4
U3
V3
W2
W6
V6
W7
T3
V5
V4
W3
V2
HUB_STB
HUB_STB#
Maximum length less than
0.5" from pin to voltage
divider.
R74
49.9
0603
1%
D6
Y3
F1
1
DVOBCLK
DVOBCLK#
DVOBD[0]
DVOBD[1]
DVOBD[2]
DVOBD[3]
DVOBD[4]
DVOBD[5]
DVOBD[6]
DVOBD[7]
DVOBD[8]
DVOBD[9]
DVOBD[10]
DVOBD[11]
AGPBUSY#
BCLK
BCLK#
DPMS
DPSLP#
DPWR#
DREFCLK
IYAM[0]
IYAM[1]
IYAM[2]
IYAM[3]
IYAP[0]
IYAP[1]
IYAP[2]
IYAP[3]
IYBM[0]
IYBM[1]
IYBM[2]
IYBM[3]
IYBP[0]
IYBP[1]
IYBP[2]
IYBP[3]
DVOBCCLKINT
DVOBCINTR#
DVOBFLDSTL
DVOBBLANK#
DVOBHSYNC
DVOBVSYNC
1
4 66M_DEFSSCLK
2
R524 0
B17
R46
10K
R3
R5
R6
R4
P6
P5
N5
P2
N2
N3
M1
M5
R260
DDR_EXTTS#
1
2
STOP_CPU# 3,4,9,29
0
0603
100K 0402
1
2 5%
R54
M3
G2
M2
L2
1
2
R571
100K
0603
T6
T5
GND
POUT/DET# 8
DVOBCINTR# 8
GND
LVDS
DVOCCLK
DVOCCLK#
DVOCD[0]
DVOCD[1]
DVOCD[2]
DVOCD[3]
DVOCD[4]
DVOCD[5]
DVOCD[6]
DVOCD[7]
DVOCD[8]
DVOCD[9]
DVOCD[10]
DVOCD[11]
DVO
ICLKAM
ICLKAP
ICLKBM
ICLKBP
EXTTS_0
GCLKIN
GVREF
HL[0]
HL[1]
HL[2]
HL[3]
HL[4]
HL[5]
HL[6]
HL[7]
HL[8]
HL[9]
HL[10]
P3
P4
2
ADDID[0]
ADDID[1]
ADDID[2]
ADDID[3]
ADDID[4]
ADDID[5]
ADDID[6]
ADDID[7]
DVODETECT
DVORCOMP
DVOCFLDSTL
DVOCBLANK#
HUB_HI[0..10]
10 HUB_HI[0..10]
K21
J21
J17
Y22
Y28
G
SUSCLK
1
3
3
HREQ[0]#
HREQ[1]#
HREQ[2]#
HREQ[3]#
HREQ[4]#
HADSTB[0]#
HADSTB[1]#
D
E5
F5
E3
E2
G5
F4
G6
F6
3,9 HDPSLP#
3
HDPWR#
4 48M_DREFCLK
D Q508
S
2N7002
2
C
R28
P25
R23
R25
T23
T26
AA26
9
+3V
2
330/NA2
330/NA2
330/NA2
330/NA2
330/NA2
330/NA2
330/NA2
1K 0603
9
4
4
GND
1
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
R520
1K
0603
1%
2
HREQ#[0..4]
CPU
1
1
1
1
1
1
1
1
1
3
HREQ#[0..4]
+1.5V
1
GND
R531
R549
R534
R539
R557
R555
R562
R542
2
2
2
2
2
2
2
2
U504A
HD#[0..63] 3
2
HYRCOMP
HD[0]#
HD[1]#
HD[2]#
HD[3]#
HD[4]#
HD[5]#
HD[6]#
HD[7]#
HD[8]#
HD[9]#
HD[10]#
HD[11]#
HD[12]#
HD[13]#
HD[14]#
HD[15]#
HD[16]#
HD[17]#
HD[18]#
HD[19]#
HD[20]#
HD[21]#
HD[22]#
HD[23]#
HD24]#
HD[25]#
HD[26]#
HD[27]#
HD[28]#
HD[29]#
HD[30]#
HD[31]#
HD[32]#
HD[33]#
HD[34]#
HD[35]#
HD[36]#
HD[37]#
HD[38]#
HD[39]#
HD[40]#
HD[41]#
HD[42]#
HD[43]#
HD[44]#
HD[45]#
HD[46]#
HD[47]#
HD[48]#
HD[49]#
HD[50]#
HD[51]#
HD[52]#
HD[53]#
HD[54]#
HD[55]#
HD[56]#
HD[57]#
HD[58]#
HD[59]#
HD[60]#
HD[61]#
HD[62]#
HD[63]#
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
8.2K/NA
8.2K/NA
8.2K/NA
8.2K/NA
8.2K/NA
8.2K/NA
8.2K/NA
8.2K/NA
2
1
2
R553 27.4
HXRCOMP
HA[3]#
HA[4]#
HA[5]#
HA[6]#
HA[7]#
HA[8]#
HA[9]#
HA[10]#
HA[11]#
HA[12]#
HA[13]#
HA[14]#
HA[15]#
HA[16]#
HA[17]#
HA[18]#
HA[19]#
HA[20]#
HA[21]#
HA[22]#
HA[23]#
HA[24]#
HA[25]#
HA[26]#
HA[27]#
HA[28]#
HA[29]#
HA[30]#
HA[31]#
K22
H27
K25
L24
J27
G28
L27
L23
L25
J24
H25
K23
G27
K26
J23
H26
F25
F26
B27
H23
E27
G25
F28
D27
G24
C28
B26
G22
C26
E26
G23
B28
B21
G21
C24
C23
D22
C25
E24
D24
G20
E23
B22
B23
F23
F21
C20
C21
G18
E19
E20
G17
D20
F19
C19
C17
F17
B19
G16
E16
C16
E17
D16
C18
1
Less than 0.5"
P23
T25
T28
R27
U23
U24
R24
U28
V28
U27
T27
V27
U25
V26
Y24
V25
V23
W25
Y25
AA27
W24
W23
W27
Y27
AA28
W28
AB27
Y26
AB28
1
HXRCOMP & HYRCOMP should be
1
2
R527 27.4
HD#[0..63]
U504B
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
2
HA#[3..31]
HA#[3..31]
2
3
1
1
1
1
1
1
1
1
DVOCHSYNC
DVOCVSYNC
LCLKCTLA
LCLKCTLB
HUB
LIBG
MDDCCLK
MDDCDATA
MDVICLK
MDVIDATA
MI2CCLK
MI2CDATA
HLSTB
HLSTB#
HLVREF
HLRCOMP
PANELBKLTCTL
PANELBKLTEN
PANELVDDEN
RSTIN#
REFSET
PSWING
RCVENIN#
RCVENOUT#
DDCADATA
DDCACLK
DDCPCLK
DDCPDATA
RED
RED#
GEEN
GREEN#
BLUE
BLUE#
J3
J2
DVOCCLK 8
DVOCCLK# 8
K5
K1
K3
K2
J6
J5
H2
H1
H3
H4
H6
G3
DVOCD0
DVOCD1
DVOCD2
DVOCD3
DVOCD4
DVOCD5
DVOCD6
DVOCD7
DVOCD8
DVOCD9
DVOCD10
DVOCD11
L7
D1
H5
L3
1 33/NA 2
1R70
2
R50 40.2
1
2
R5680/NA
DVOCD[0..11]
DVOCD[0..11]
C
DVORCOMP
10/20 : WIDTH/SPACE
DVORCOMP
GND
DVOCFLDSTL 8
K6
L5
DVOCHSYNC 8
DVOCVSYNC 8
R45 10K/NA
1
2
1
2
R47 10K/NA
R523 1
2
1.5K
H9
C6
A10
P7
T7
N7
M6
K7
N6
1
1R83
1R85
1R81
R75
G8
F8
A5
U2
AC16
AC15
8
1
2
HBR0#
D
R541
R561
R554
R556
R538
R533
R548
R530
2
10K 2
10K 2
10K 2
10K
R61
100K
0603
+3V
2
1
+1.5V
R112
51
0603
GND
GND
+1.5V
+1.5V
MI2CCLK 8
MI2CDATA 8
1
2
R53 0/NA
BLADJ
ENBL
FPVCC
MCH_PSWING
RCVENIN#
1
RCVENOUT#
R95
18,20
20
14
2
0/NA
B
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
CRT
HSYNC
VSYNC
DREFSSCLK
AJ29
AH29
B29
A29
AJ28
A28
AA9
AJ4
AJ2
A2
AH1
B1
855GM/GME
BGA707_25
+1.35V
1
1
2
1
2
1
2
C545
1U
0603
R578
100
0603
1%
GND
2
C546
0.1U
0603
50V
127
0603
1%
GND
A
GND
2
2
R558
150
0603
C530
0.1U
0603
50V
1
1
C550
0.01U
0603
2
C551
0.1U
0603
50V
1
R525
150
0603
C518
0.1U
0603
50V
2
2
R581
100
0603
1%
1
1
1
1
1
C549
1U
0603
2
C552
0.1U
0603
50V
2
2
R88
100
0603
1%
2
C97
1U
0603
1
1
1
C102
0.1U
0603
50V
2
1
2
A
R44
REFSET
R586
100
0603
1%
MCH_PSWING
2
R563
301
0603
HYSWING
2
HXSWING
2
1
R526
301
0603
2
R580
49.9
0603
1%
HCCVREF
2
HAVREF
1
1
1
R86
49.9
0603
1%
R577
68.1
0603
HUB_MCH_VREF
2
+VCCP
1
+VCCP
2
+VCCP
R584
287
0603
1%
1/10W
1
Less than 0.5"
2
+VCCP (1.05V)
+1.35V
1
Maximum length less than 0.5" from pin to
voltage divider.
+1.35V
GND
GND
GND
R576
GND
1
2
HUB_RCOMP
37.4
0603
1%
Title
Montara_GME CPU_LVDS_DVO_HUB_CRT(1)
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
5
of
29
5
R529
1K/NA
0603
RSVD_8
RSVD_9
B2
B3
RSVD_10
RSVD_11
SDM[0]
SDM[1]
SDM[2]
SDM[3]
SDM[4]
SDM[5]
SDM[6]
SDM[7]
SDM[8]
Clock config bit GST[1,0]
PSB/Sys Mem Core/GFX Core(CL/CH)
NB_DQS[0..8] 7
Y2
D29
VCCALVDS
A11
VCCAGPLL
VCCAHPLL
C515
0.1U
0603
50V
C514
0.01U
0603
B11
VCCALVDS
B8
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
VCCTXLVDS
V29
M29
H29
A24
A22
VTTHF_0
VTTHF_1
VTTHF_2
VTTHF_3
VTTHF_4
AB29
Y29
K29
F29
A26
V22
T22
P22
M22
H22
U21
R21
N21
L21
H20
A20
J19
H18
A18
H16
G15
+VCCP
C36
0.1U
0603
50V
VSSADAC
855GM/GME
BGA707_25
VSSADAC
GND
VSSALVDS
A12
D10
B10
F9
C61
0.1U
0603
50V
1
VCCAGPLL
VCCAHPLL
VCCQSM_0
VCCQSM_1
VCCADPLLA
VCCADPLLB
C554
10U
1206
10V
GND
1
A6
B16
2
2
2
L9
120Z/100M
VCCADPLLA
VCCADPLLB
VCCGPIO_0
VCCGPIO_1
C566
0.1U
0603
50V
1
1
1
2
1
1
2
1
2
1
2
AJ8
AJ6
C583
10U
1206
10V
C92
22U
1206
10V
2
AG2 NB_DQS0
AH5 NB_DQS1
AH8 NB_DQS2
AE12 NB_DQS3
AH17 NB_DQS4
AE21 NB_DQS5
AH24 NB_DQS6
AH27 NB_DQS7
AD15 NB_DQS8
NB_DQS[0..8]
1
VCCQSM
VCCASM_0
VCCASM_1
C580
0.1U
0603
50V
2
SDQS[0]
SDQS[1]
SDQS[2]
SDQS[3]
SDQS[4]
SDQS[5]
SDQS[6]
SDQS[7]
SDQS[8]
RSVD_6
RSVD_7
D3
D2
GST0
GST1
B
GST[0]
GST[1]
GST[2]
F2
F3
+1.5V
A4
A3
VTTLF_0
VTTLF_1
VTTLF_2
VTTLF_3
VTTLF_4
VTTLF_5
VTTLF_6
VTTLF_7
VTTLF_8
VTTLF_9
VTTLF_10
VTTLF_11
VTTLF_12
VTTLF_13
VTTLF_14
VTTLF_15
VTTLF_16
VTTLF_17
VTTLF_18
VTTLF_19
VTTLF_20
C577
0.1U
0603
50V
2
1
C4
C3
C2
2
2
R528
1K/NA
0603
GST0
GST1
NB_CB[0..7] 7
AF1
AD1
VCCGPIO
VCCADAC_0
VCCADAC_1
C555
10U
1206
10V
C85
22U
1206
10V
GND
NB_DM[0..8]
MAX : 0.09A
NB_DM[0..8] 7
AE5 NB_DM0
AE6 NB_DM1
AE9 NB_DM2
AH12 NB_DM3
AD19 NB_DM4
AD21 NB_DM5
AD24 NB_DM6
AH28 NB_DM7
AH15 NB_DM8
+1.5V
1
VCCADAC
2
L10
120Z/100M
1
+1.35V
C513
0.1U
0603
50V
VCCASM
2
L518
120Z/100M
C512
0.01U
0603
VSSADAC
C565
22U
1206
10V
C556
22U
1206
10V
1
+1.5V
RSVD_5
NB_CB[0..7]
VCCASM
VTTHF_0
VTTHF_1
VTTHF_2
VTTHF_3
VTTHF_4
C581
0.1U
0603
50V
C553
10U
1206
10V
C557
0.01U
0603
2
+1.5V
1
L4
RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
GND
B9
A9
VCCDLVDS_0
VCCDLVDS_1
VCCDLVDS_2
VCCDLVDS_3
C563
0.1U
0603
50V
1
F12
D12
B12
AA5
D7
C517
0.1U
0603
50V
VCCADAC
AA29
W29
U29
N29
L29
J29
G29
E29
C29
AE28
AC28
E28
D28
AJ27
AG27
AC27
F27
A27
AJ26
AB26
W26
R26
N26
L26
J26
G26
AE25
AA25
D25
A25
AG24
AA24
V24
T24
P24
M24
K24
H24
F24
B24
AJ23
AC23
AA23
D23
A23
AE22
W22
U22
R22
N22
L22
J22
F22
C22
AG21
AB21
AA21
Y21
V21
T21
P21
M21
H21
D21
A21
AJ20
AC20
AA20
J20
F20
AE19
AB19
H19
D19
A19
AJ18
AG18
AA18
J18
F18
AC17
AB17
U17
R17
N17
H17
D17
A17
AE16
AA16
T16
C99
10U
1206
10V
GND
2
GND
C516
0.1U
0603
50V
C579
0.1U
0603
50V
1
SMRCOMP
C33
10U
1206
10V
C101
0.1U
0603
50V
GND
2
AB1
B15
B14
J13
G13
+1.5V
VCCTXLVDS_0
VCCTXLVDS_1
VCCTXLVDS_2
VCCTXLVDS_3
C100
0.1U
0603
50V
GND
1
MCH_SMRCOMP
GND
1
2
C126
0.1U
0603
50V
C91
0.1U
0603
50V
AG29
AF29
AC29
AF27
AJ25
AF24
AB22
AJ21
AF21
AB20
AF18
AB18
AJ17
AB16
AF15
AB14
AJ13
AA13
AF12
AB12
AA11
AB10
AJ9
AF9
Y9
AB8
AA8
Y7
AF6
AB6
AA6
AJ5
Y4
AF3
AB3
AG1
AC1
2
SMVREF_0
1
AJ24
SMVSWINGH
SMVSWINGL
C529
0.1U
0603
50V
POWER
VCCDVO_0
VCCDVO_1
VCCDVO_2
VCCDVO_3
VCCDVO_4
VCCDVO_5
VCCDVO_6
VCCDVO_7
VCCDVO_8
VCCDVO_9
VCCDVO_10
VCCDVO_11
VCCDVO_12
VCCDVO_13
VCCDVO_14
VCCDVO_15
VCCSM_0
VCCSM_1
VCCSM_2
VCCSM_3
VCCSM_4
VCCSM_5
VCCSM_6
VCCSM_7
VCCSM_8
VCCSM_9
VCCSM_10
VCCSM_11
VCCSM_12
VCCSM_13
VCCSM_14
VCCSM_15
VCCSM_16
VCCSM_17
VCCSM_18
VCCSM_19
VCCSM_20
VCCSM_21
VCCSM_22
VCCSM_23
VCCSM_24
VCCSM_25
VCCSM_26
VCCSM_27
VCCSM_28
VCCSM_29
VCCSM_30
VCCSM_31
VCCSM_32
VCCSM_33
VCCSM_34
VCCSM_35
VCCSM_36
2
+1.25V_DDR
MCH_SMVSWINGHAJ19
MCH_SMVSWINGL AJ22
SCK[0]
SCK[0]#
SCK[1]
SCK[1]#
SCK[2]
SCK[2]#
SCK[3]
SCK[3]#
SCK[4]
SCK[4]#
SCK[5]
SCK[5]#
C70
10U
1206
10V
VCCHL_0
VCCHL_1
VCCHL_2
VCCHL_3
VCCHL_4
VCCHL_5
VCCHL_6
VCCHL_7
1
AB2
AA2
AC26
AB25
AC3
AD4
AC2
AD2
AB23
AB24
AA3
AB4
P9
M9
K9
R8
N8
M8
L8
J8
H7
E6
M4
J4
E4
N1
J1
E1
2
CLK_DDR0
CLK_DDR0#
CLK_DDR1
CLK_DDR1#
CLK_DDR2
CLK_DDR2#
CLK_DDR3
CLK_DDR3#
CLK_DDR4
CLK_DDR4#
CLK_DDR5
CLK_DDR5#
1
7
7
7
7
7
7
7
7
7
7
7
7
SCKE[0]
SCKE[1]
SCKE[2]
SCKE[3]
2
AC7
AB7
AC9
AC10
GND
+1.5V
1
CKE0
CKE1
CKE2
CKE3
SCS[0]#
SCS[1]#
SCS[2]#
SCS[3]#
C87
0.1U
0603
50V
2
7
7
7
7
DDR
SBA[0]
SBA[1]
V9
W8
U8
V7
U6
W5
Y1
V1
1
AD23
AD26
AC22
AC25
C93
0.1U
0603
50V
2
CS#0
CS#1
CS#2
CS#3
C68
10U
1206
10V
U504E
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
1
NB_BA0
NB_BA1
7
7
7
7
MAX : 0.09A
+1.35V
2
7
7
AD22
AD20
SWE#
SCAS#
SRAS#
C95
0.1U
0603
50V
1
AD25
AC24
AC21
C83
0.1U
0603
50V
2
NB_WE#
NB_CAS#
NB_RAS#
7
7
7
W21
AA19
AA17
T17
P17
U16
R16
N16
AA15
T15
P15
J15
U14
R14
N14
H14
T13
P13
GND
1
SMAB[1]
SMAB[2]
SMAB[4]
SMAB[5]
2
AD16
AC12
AF11
AD10
1
SMAB1
SMAB2
SMAB4
SMAB5
SMAB[4..5]
2
SMAB[4..5]
C94
0.1U
0603
50V
1
SMAB[1..2]
7
C90
0.1U
0603
50V
2
7
SMAB[1..2]
C88
0.1U
0603
50V
C69
0.1U
0603
50V
1
NB_MA[6..12]
NB_MA[6..12]
C98
10U
1206
10V
2
D
AF2 NB_MD0
AE3 NB_MD1
AF4 NB_MD2
AH2 NB_MD3
AD3 NB_MD4
AE2 NB_MD5
AG4 NB_MD6
AH3 NB_MD7
AD6 NB_MD8
AG5 NB_MD9
AG7 NB_MD10
AE8 NB_MD11
AF5 NB_MD12
AH4 NB_MD13
AF7 NB_MD14
AH6 NB_MD15
AF8 NB_MD16
AG8 NB_MD17
AH9 NB_MD18
AG10NB_MD19
AH7 NB_MD20
AD9 NB_MD21
AF10 NB_MD22
AE11 NB_MD23
AH10 NB_MD24
AH11 NB_MD25
AG13 NB_MD26
AF14 NB_MD27
AG11 NB_MD28
AD12 NB_MD29
AF13 NB_MD30
AH13 NB_MD31
AH16 NB_MD32
AG17 NB_MD33
AF19 NB_MD34
AE20 NB_MD35
AD18 NB_MD36
AE18 NB_MD37
AH18 NB_MD38
AG19 NB_MD39
AH20 NB_MD40
AG20 NB_MD41
AF22 NB_MD42
AH22 NB_MD43
AF20 NB_MD44
AH19 NB_MD45
AH21 NB_MD46
AG22 NB_MD47
AE23 NB_MD48
AH23 NB_MD49
AE24 NB_MD50
AH25 NB_MD51
AG23 NB_MD52
AF23 NB_MD53
AF25 NB_MD54
AG25 NB_MD55
AH26 NB_MD56
AE26 NB_MD57
AG28 NB_MD58
AF28 NB_MD59
AG26 NB_MD60
AF26 NB_MD61
AE27 NB_MD62
AD27 NB_MD63
AG14 NB_CB0
AE14 NB_CB1
AE17 NB_CB2
AG16 NB_CB3
AH14 NB_CB4
AE15 NB_CB5
AF16 NB_CB6
AF17 NB_CB7
2
SMA[4..5]
SDQ[0]
SDQ[1]
SDQ[2]
SDQ[3]
SDQ[4]
SDQ[5]
SDQ[6]
SDQ[7]
SDQ[8]
SDQ[9]
SDQ[10]
SDQ[11]
SDQ[12]
SDQ[13]
SDQ[14]
SDQ[15]
SDQ[16]
SDQ[17]
SDQ[18]
SDQ[19]
SDQ[20]
SDQ[21]
SDQ[22]
SDQ[23]
SDQ[24]
SDQ[25]
SDQ[26]
SDQ[27]
SDQ[28]
SDQ[29]
SDQ[30]
SDQ[31]
SDQ[32]
SDQ[33]
SDQ[34]
SDQ[35]
SDQ[36]
SDQ[37]
SDQ[38]
SDQ[39]
SDQ[40]
SDQ[41]
SDQ[42]
SDQ[43]
SDQ[44]
SDQ[45]
SDQ[46]
SDQ[47]
SDQ[48]
SDQ[49]
SDQ[50]
SDQ[51]
SDQ[52]
SDQ[53]
SDQ[54]
SDQ[55]
SDQ[56]
SDQ[57]
SDQ[58]
SDQ[59]
SDQ[60]
SDQ[61]
SDQ[62]
SDQ[63]
SDQ[64]
SDQ[65]
SDQ[66]
SDQ[67]
SDQ[68]
SDQ[69]
SDQ[70]
SDQ[71]
SMA[0]
SMA[1]
SMA[2]
SMA[3]
SMA[4]
SMA[5]
SMA[6]
SMA[7]
SMA[8]
SMA[9]
SMA[10]
SMA[11]
SMA[12]
1
SMA[4..5]
AC18
AD14
AD13
AD17
AD11
AC13
AD8
AD7
AC6
AC5
AC19
AD5
AB5
2
7
NB_MA0
SMA1
SMA2
NB_MA3
SMA4
SMA5
NB_MA6
NB_MA7
NB_MA8
NB_MA9
NB_MA10
NB_MA11
NB_MA12
SMA[1..2]
1
SMA[1..2]
+2.5V_DDR
U504D
MAX : 2.24A
NB_MD[0..63] 7
2
7
C
1
+1.35V
NB_MD[0..63]
U504C
7
2
NB_MA3
1
NB_MA3
3
2
7
4
NB_MA0
1
NB_MA0
2
7
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
GND
P16
J16
F16
AG15
AB15
U15
R15
N15
H15
D15
AC14
AA14
T14
P14
J14
AE13
AB13
U13
R13
N13
H13
F13
D13
A13
AJ12
AG12
AA12
J12
AJ11
AC11
AB11
H11
F11
D11
AJ10
AE10
AA10
C10
AG9
AB9
W9
U9
T9
R9
N9
L9
E9
AC8
Y8
V8
T8
P8
K8
H8
AJ7
AE7
AA7
R7
M7
J7
G7
E7
C7
AG6
Y6
L6
Y5
U5
B5
AE4
AC4
AA4
W4
T4
N4
K4
G4
D4
AJ3
AG3
R2
AJ1
AE1
AA1
U1
L1
G1
C1
J10
U26
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_126
VSS_125
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
D
C
B
855GM/GME
BGA707_25
GND
GND
GND
855GM/GME
BGA707_25
GND
00(def): 400/266/200(133/200)
+3V
1
VCCGPIO
1
2
L13
120Z/100M
C103
0.1U
0603
50V
C42
10U
1206
10V
GND
C47
0.01U
0603
2
C51
0.1U
0603
50V
GND
Place within 0.5" with 15-mil wide.
VCCAGPLL
2
L19
120Z/100M
1
+1.35V
1
VCCAHPLL
2
L16
120Z/100M
2
1
1
+1.35V
2
: 400/200/133(100/133)
1
: 400/200/200(100/200)
10
2
01
GND
+2.5V_DDR
1
2 0.1U
C5341
2 0.1U
VTTHF_2
C5231
2 0.1U
VTTHF_3
C37 1
2 0.1U
VTTHF_4
C38 1
2 0.1U
1
C32
22U
1206
10V
C39
0.01U
0603
GND
2
1
1
1
L14
120Z/100M
GND
1
VCCQSM
C52
0.01U
0603
C582
4.7U
0805
+80-20%
2
C41
10U
1206
10V
2
C40
22U
1206
10V
+2.5V_DDR
1
2
L22
120Z/100M
1
VCCTXLVDS
1
+2.5V_DDR
1
2
L20
120Z/100M
2
2
1
A
1
GND
VCCADPLLB
2
C106
0.1U
0603
50V
2
GND
+1.35V
C511
0.01U
0603
1
2
C109
0.1U
0603
50V
MCH_SMRCOMP
C28
22U
1206
10V
2
1
2
L11
120Z/100M
2
GND
VCCADPLLA
2
GND
R98
60.4
0603
1%
C128
0.1U
0603
50V
2
2
1
1
R106
604
0603
1%
C127
0.1U
0603
50V
1
1
MCH_SMVSWINGH
2
2
2
R103
150
0603
1
1
2
MCH_SMVSWINGL
R96
60.4
0603
1%
2
R105
150
0603
2
R104
604
0603
1%
1
1
1
+1.35V
A
C5441
VTTHF_1
+2.5V_DDR
2
+2.5V_DDR
VTTHF_0
C578
0.01U
0603
Title
Montara-GME DDR_POWER_GND(2)
GND
GND
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
6
of
29
5
4
3
2
1
+1.25V_DDR
6
NB_MD[0..63]
6
NB_CB[0..7]
6
NB_DM[0..8]
SMAB[4..5]
6
SMA[1..2]
6
SMA[4..5]
CKE1
C165
0.1U
0603
50V
C179
0.1U
0603
50V
MA7
SMA5
MA3
SMA1
MA10
BA0
WE#
CS#0
1
2
1
MA12
MA9
C180
0.1U
0603
50V
1
C166
0.1U
0603
50V
C164
0.1U
0603
50V
C178
0.1U
0603
50V
2
2
1
C181
0.1U
0603
50V
2
C167
0.1U
0603
50V
2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
MD32
MD33
DQS4
MD34
GND
+2.5V_DDR
2
C160
0.1U
0603D
1
C161
0.1U
0603D
MD41
DQS5
C174
0.1U
0603D
1
MD42
MD43
C159
0.1U
0603D
C173
1U
0603D
2
1
1
2
C175
1U
0603D
C176
0.1U
0603D
2
C162
0.1U
0603D
2
C177
0.1U
0603D
2
C163
1U
0603D
1
1
MD35
MD40
MD48
MD49
GND
DQS6
MD50
MD51
MD56
MD57
DQS7
MD58
MD59
4,10
4,10
SMBDATA
SMBCLK
SMBDATA
SMBCLK
+3V
J509
MD4
MD5
MD0
MD1
DM0
MD6
DQS0
MD2
MD7
MD12
MD3
MD8
MD13
DM1
MD9
DQS1
MD14
MD15
MD10
MD11
CLK_DDR3
CLK_DDR3#
MD20
MD21
MD16
MD17
DM2
MD22
DQS2
MD18
MD23
MD28
MD19
MD24
MD29
DM3
MD25
DQS3
MD30
MD31
MD26
MD27
MCB4
MCB5
MCB0
MCB1
DM8
MCB6
DQS8
MCB2
MCB7
MCB3
CLK_DDR5
CLK_DDR5#
CKE0
CKE3
MA11
MA8
NB_MA12
NB_MA9
MA6
SMA4
SMA2
MA0
NB_MA7
SMAB5
NB_MA3
SMAB1
BA1
RAS#
CAS#
CS#1
NB_MA10
NB_BA0
NB_WE#
CS#2
MD36
MD37
MD32
MD33
DM4
MD38
DQS4
MD34
MD39
MD44
MD35
MD40
MD45
DM5
MD41
DQS5
MD46
MD47
MD42
MD43
CLK_DDR1#
CLK_DDR1
MD52
MD53
MD48
MD49
DM6
MD54
DQS6
MD50
MD55
MD60
MD51
MD56
MD61
DM7
MD57
DQS7
MD62
MD63
MD58
MD59
SMBDATA
SMBCLK
+3V
0.6MM/200P/H5.2
QUASAR
CA0115-200N01
MCB4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DM0
MD6
D
MD7
MD12
MD13
DM1
MD14
MD15
MD20
MD21
DM2
MD22
MD23
MD28
MD29
DM3
MD30
MD31
MCB4
MCB5
DM8
MCB6
MCB7
C
CKE2
NB_MA11
NB_MA8
NB_MA6
SMAB4
SMAB2
NB_MA0
NB_BA1
NB_RAS#
NB_CAS#
CS#3
MD36
MD37
DM4
MD38
MD39
MD44
MD45
DM5
MD46
MD47
CLK_DDR4#
CLK_DDR4
B
MD52
MD53
DM6
MD54
MD55
MD60
MD61
DM7
MD62
MD63
0.6MM/200P/H9.2
QUASAR
CA0145-200N01
1
2
1
2
1
2
1
2
2
GND
1
C142
0.1U
0603
16V
2
1
2
1
1
2
C168
0.1U
0603
16V
C139
0.1U
0603
16V
2
2
C182
0.01U
0603D
Title
Size
C
GND
3
C230
0.1U
0603
50V
1
1
2
+DDR_VREF
Date:
4
C229
0.1U
0603
50V
A
C192
0.1U
0603
16V
SO-DIMM
GND
GND
C228
0.1U
0603
50V
2
2
C233
0.01U
0603D
2
C227
0.01U
0603
C232
10U
1206
10V
1
2
R134
75
0603
0.5%
1
2
C216
0.01U
0603
C231
10U
1206
10V
1
R135
75
0603
0.5%
2
1
2
1
2
1
2
1
C204
0.01U
0603
C215
0.01U
0603
C226
0.01U
0603
2
1
1
1
1
2
2
C203
0.01U
0603
C214
0.01U
0603
C225
0.01U
0603
2
C224
0.01U
0603
2
C223
0.01U
0603
C202
0.01U
0603
C213
0.01U
0603
1
2
C212
0.01U
0603
1
2
1
C222
0.01U
0603
C201
0.01U
0603
1
2
1
1
2
C200
0.01U
0603
C211
0.01U
0603
2
C221
0.01U
0603
1
1
1
2
2
1
1
C220
0.01U
0603
+2.5V_DDR
C199
0.01U
0603
C210
0.01U
0603
2
C219
0.01U
0603
C209
0.01U
0603
2
C208
0.01U
0603
C198
0.01U
0603
1
2
C197
0.01U
0603
1
1
C207
0.01U
0603
C218
0.01U
0603
1
1
C196
0.01U
0603
2
2
1
2
C206
0.01U
0603
C217
0.01U
0603
2
C195
0.01U
0603
2
C194
0.01U
0603
2
C193
0.01U
0603
1
1
2
3
4
5
6
7
8
+1.25V_DDR
1
+1.25V_DDR
+1.25V_DDR
C205
0.01U
0603
5
MD4
MD5
GND
2
16
15 RP22
14 56*8
13 RPX8
12
11
10
9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
1
8
7
6
5
2
RP14
56*4
1206
1
1
2
3
4
2
CS#0
CS#1
CS#2
CS#3
1
RP15
56*4
1206
8
7
6
5
2
1
2
3
4
1
CKE0
CKE1
CKE2
CKE3
SMA2
MA3
SMA4
SMA5
MA6
MA7
MA8
MA9
A
MCB3
NB_MA3
2
DQS8
RP24
56*8
RPX8
DQS8
MCB2
NB_MA0
1
2
10
0603
10*8 MCB7
RPX8 MCB3
MCB2
MCB6
MCB1
DM8
MCB0
MCB5
RP16
56*8
RPX8
SMA[4..5]
1
1
10*8
RPX8
RP17
56*8
RPX8
MCB0
MCB1
+2.5V_DDR
1
NB_DQS8
10*8
RPX8
RP18
56*8
RPX8
SMAB[4..5]
NB_MA3
2
R78
10*8
RPX8
RP19
56*8
RPX8
MD26
MD27
SMA[1..2]
NB_MA0
1
R130 10 0603
1
2
10*8
RPX8
RP20
56*8
RPX8
SMAB[1..2]
CLK_DDR2
CLK_DDR2#
2
NB_CB4
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
MD25
DQS3
NB_DM[0..8]
6
6
MD19
MD24
NB_CB[0..7]
SMAB[1..2]
6
DQS2
MD18
NB_DQS[0..8]
6
1
B
8
7
6
5
4
3
2
1
8
7
6 10*8
5 RPX8
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
CLK_DDR0
CLK_DDR0#
NB_MD[0..63]
6 NB_DQS[0..8]
RP5
NB_MD34
NB_MD38
NB_DQS4
NB_DM4
NB_MD33
NB_MD37
NB_MD32
NB_MD36
NB_DQS5RP4
NB_DM5
NB_MD41
NB_MD45
NB_MD40
NB_MD44
NB_MD35
NB_MD39
NB_MD49RP3
NB_MD53
NB_MD48
NB_MD52
NB_MD43
NB_MD47
NB_MD42
NB_MD46
NB_MD56RP2
NB_MD60
NB_MD51
NB_MD55
NB_MD50
NB_MD54
NB_DQS6
NB_DM6
NB_MD59RP1
NB_MD63
NB_MD58
NB_MD62
NB_DQS7
NB_DM7
NB_MD57
NB_MD61
NB_CB7 RP8
NB_CB3
NB_CB2
NB_CB6
NB_CB1
NB_DM8
NB_CB0
NB_CB5
MD10
MD11
MD16
MD17
NB_MA[6..12]
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
MD9
DQS1
NB_MA[6..12]
6
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
MD3
MD8
1
RP21
56*8
RPX8
CLK_DDR0
CLK_DDR0#
CLK_DDR1
CLK_DDR1#
CLK_DDR2
CLK_DDR2#
CLK_DDR3
CLK_DDR3#
CLK_DDR4
CLK_DDR4#
CLK_DDR5
CLK_DDR5#
CLK_DDR0
CLK_DDR0#
CLK_DDR1
CLK_DDR1#
CLK_DDR2
CLK_DDR2#
CLK_DDR3
CLK_DDR3#
CLK_DDR4
CLK_DDR4#
CLK_DDR5
CLK_DDR5#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DQS0
MD2
2
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
RP23
56*8
RPX8
CS#0
CS#1
CS#2
CS#3
6
6
6
6
6
6
6
6
6
6
6
6
J512
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MD0
MD1
CS#0
CS#1
CS#2
CS#3
1
MD34
MD38
DQS4
DM4
MD33
MD37
MD32
MD36
DQS5
DM5
MD41
MD45
MD40
MD44
MD35
MD39
MD49
MD53
MD48
MD52
MD43
MD47
MD42
MD46
MD56
MD60
MD51
MD55
MD50
MD54
DQS6
DM6
MD59
MD63
MD58
MD62
DQS7
DM7
MD57
MD61
MCB2
MCB6
DQS8
DM8
MCB1
MCB5
MCB0
MCB4
RP25
56*8
RPX8
6
6
6
6
+2.5V_DDR
+DDR_VREF
CKE0
CKE1
CKE2
CKE3
2
10*8 WE#
RPX8 CAS#
BA0
RAS#
BA1
MA10
MA0
RP26
56*8
RPX8
CKE0
CKE1
CKE2
CKE3
1
10*8 MA3
RPX8MA6
MA7
MA8
MA9
MA11
MA12
RP27
56*8
RPX8
6
6
6
6
+2.5V_DDR
+DDR_VREF
2
10*8
RPX8
RP28
56*8
RPX8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
10*8
RPX8
RP29
56*8
RPX8
2
10*8
RPX8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
10*8
RPX8
MD2
MD6
DQS0
DM0
MD1
MD5
MD0
MD4
DQS1
DM1
MD9
MD13
MD8
MD12
MD3
MD7
MD17
MD21
MD16
MD20
MD11
MD15
MD10
MD14
MD24
MD28
MD19
MD23
MD18
MD22
DQS2
DM2
MD27
MD31
MD26
MD30
DQS3
DM3
MD25
MD29
MA11
MA12
SMAB1
SMAB5
SMAB2
SMAB4
MCB3
MCB7
WE#
CAS#
BA0
RAS#
BA1
MA10
SMA1
MA0
2
10*8
RPX8
NB_BA0
NB_BA1
NB_RAS#
NB_WE#
NB_CAS#
1
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
2
8
7
6
5
4
3
2
1
RP12
8
7
6
5
4
3
2
1
RP11
8
7
6
5
4
3
2
1
RP10
8
7
6
5
4
3
2
1
RP9
8
7
6
5
4
3
2
1
NB_MA3 8
NB_MA67
NB_MA7 6
NB_MA8 5
NB_MA9 4
NB_MA113
NB_MA122
1
RP6 NB_WE# 8
NB_CAS# 7
NB_BA0 6
NB_RAS# 5
NB_BA1 4
NB_MA10 3
NB_MA0 2
1
2
C
RP13
NB_BA0
NB_BA1
NB_RAS#
NB_WE#
NB_CAS#
1
D
NB_MD2
NB_MD6
NB_DQS0
NB_DM0
NB_MD1
NB_MD5
NB_MD0
NB_MD4
NB_DQS1
NB_DM1
NB_MD9
NB_MD13
NB_MD8
NB_MD12
NB_MD3
NB_MD7
NB_MD17
NB_MD21
NB_MD16
NB_MD20
NB_MD11
NB_MD15
NB_MD10
NB_MD14
NB_MD24
NB_MD28
NB_MD19
NB_MD23
NB_MD18
NB_MD22
NB_DQS2
NB_DM2
NB_MD27
NB_MD31
NB_MD26
NB_MD30
NB_DQS3
NB_DM3
NB_MD25
NB_MD29
RP7
6
6
6
6
6
2
Document
Number
Rev
01
411682810001
1
7
of
29
5
4
3
2
1
L12
2
C35
0.1U
0603
50V
1
C50
0.1U
0603
50V
C48
10U
1206
10V
2
1
1
C22
0.1U
0603
50V
2
C16
0.1U
0603
50V
2
1
1
1
C30
0.1U
0603
50V
2
2
R33
1K
0603
DVOVREF
2
RDDP recommend
1K ohm resistor
+3V
C34
10U
1206
10V
2
1
120Z/100M
1608
2
8080 PLACE 10K
1
1
+3V
+1.5V
GND
+1.5V
1
R35
0
0805
2
2
C19
0.1U
0603
50V
1
1
D
C17
10U
1206
10V
2
2
+3V
Place near
to 7011.
C31
0.1U
0603
50V
2
1
1
GND
R36
1K
0603
D
GND
1
1
C27
20P
0603
5%
TV_DDCK
TV_DDDA
15
14
XIN
42
+3V
XOUT
43
45
XO
5
DVOCFLDSTL
1
R19
1
R49
1
C
2
140 2
0/NA
10
35
47
AS
ISET
BCO
+1.5V
1
R31
2
9
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
1
2
R29
8.2K
0603
2
0/NA
DVOBCINTR# 5
R27
330
0603
C29
0.1U
0603
50V
GND
C25
0.1U
0603
50V
GND
R32
330/NA
0603
Default NTSC
GND
C
GND
CH7011A
PQFP64_0.5MM
1
GND
GND
S
MI2CCLK
R18
1K
0603
G
R16
10K
0603
Q7
2N7002
2
2
R28
8.2K/NA
0603
TV_DDCK
D
D
S
5
GND
+3V
1
+3V
34
40
2
R26
330
0603
RESET*
C/HSYNC
DGND_0
DGND_1
DGND_2
TV_PCIRST#
P-OUT
6
11
64
9
13
48
AGND_0
AGND_1
AGND_2
46
GND_0
GND_1
POUT/DET#
5
1
1
12
49
18
44
XI/FIN
16
17
41
R23
8.2K/NA
0603
GND
2
GND
8
7
GPIO[0]
GPIO[1]
SPC
SPD
1
2
2
2
14.31818MHZ
CVBS/B
CVBS
1
1
C24
20P
0603
5%
C/R
Y/G
2
39
36
2
38
37
1
TV_CRMA
TV_LUMA
2
XOUT
2
X1
5
+3V
1
R30
1M/NA
DVOCD[0..11]
+3V
2
1
H
V
DVOCD[0..11]
DVOCD0
DVOCD1
DVOCD2
DVOCD3
DVOCD4
DVOCD5
DVOCD6
DVOCD7
DVOCD8
DVOCD9
DVOCD10
DVOCD11
63
62
61
60
59
58
55
54
53
52
51
50
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
1
4
5
DVDDV
5 DVOCHSYNC
5 DVOCVSYNC
XCLK
XCLK*
2
XIN
VREF
DVDD_0
DVDD_1
DVDD_2
DVOCCLK
DVOCCLK#
5
5
VDD
U5
3
57
56
AVDD_0
AVDD_1
33
GND
DVOVREF
5
+1.5V
MI2CDATA
S
D
2
2
Q8
2N7002
TV_DDDA
D
S
5
R20
1K
0603
G
R17
10K
0603
1
+3V
1
+3V
B
B
+3V
3
TV
TV CONNECTOR
CHIP
D502
BAV70LT1/NA
10
10
ICH_GPIO37
ICH_GPIO41
9
ICH_GPIO17
3,9
B/CB#
R207
1
R667
1
R173
1
R203
1
R714
1
R742
1
R175
1
A
9
ICH_GPIO21
9
ICH_GPIO23
2 8.2K
0603
2 8.2K
0603
2 8.2K/NA
0603
2 8.2K
0603
ICH_GPIO27
9
ICH_GPIO28
1
R218
1
R223
1
2
1
C21
100P
0603
10%
1
1
2
R503
75/NA
0603
2
R502
75/NA
0603
C502
270P
0603
10%
1
1
1
1
C501
270P
0603
10%
2
1
2
1
JO504
R22
75
0603
0.5%
C23
100P
0603
10%
R25
75
0603
0.5%
2
ICH_GPIO25
9
JO503
2
9
2 8.2K/NA
0603
2 8.2K/NA
0603
2
D501
BAW56/NA
DIN/4P/RA
SUYIN
35144A-04T1
R222
2
2 8.2K
0603
2 8.2K
0603
TV_CRMA
2
ICH_GPIO5
1
TV_LUMA
1608
2
9
R202
1608
2
2
120Z/100M
3
ICH_GPIO1
120Z/100M
1
1
L502
1
9
GND1
GND2
VDD3
L501
GND1
GND2
1
+3V
1
2
3
4
2
1
2
3
4
1
J501
R501
2 8.2K/NA
0603
GND
1
2
0
0805
TV_GND
GND
GND
GND
A
2 8.2K/NA
0603
2 8.2K/NA
0603
Title
Size
C
Date:
5
4
3
2
TV Encoder
Document
Number
Rev
01
411682810001
1
8
of
29
5
4
3
2
1
PCI_REQ4#
PCI_REQ3#
16
15
17
PCI_REQ2#
PCI_REQ1#
PCI_REQ0#
8
14
ICH_GPIO1
CRT_IN#
16 PCI_GNT2#
15 PCI_GNT1#
17 PCI_GNT0#
8
ICH_GPIO17
3,8 B/CB#
15,16,17
15,16,17
15,16,17
15,16,17
15,16,17
15,16,17
15,16,17
B6
C7
B3
A2
B1
ICH_GPIO1
CRT_IN#
A6
B5
PCI_GNT4#
PCI_GNT3#
D6
B7
A7
E6
C1
C5
E8
ICH_GPIO17
B/CB#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCIRST#
4 PCICLK_ICH
PCI
REQB#/REQ5#/GPIO 1
REQA#/GPIO 0
GNT# 4
GNT# 3
GNT# 2
GNT# 1
GNT# 0
GNTB#/GNT5#/GPIO 17
GNTA#/GPIO 16
F1
L5
F2
M3
F3
G1
L4
M2
K5
W2
U5
P5
PCI_LOCK#
16,17 PCI_SERR#
10,15,16,17 PCI_PME#
REQ# 4
REQ# 3
REQ# 2
REQ# 1
REQ# 0
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PERR#
PLOCK#
SERR#
PME#
PCIRST#
PCICLK
C/BE#3
C/BE#2
C/BE#1
C/BE#0
N4
M4
K4
J2
CBE#3
CBE#2
CBE#1
CBE#0
U12A
A5
B2
H6
J1
K6
M10
P6
U1
P12
V10
V16
V18
AC8
AC17
H18
J18
JL3
74AHC08_V
TSSOP14
1
2
JP_NET10
CB_PCIRST# 17
GND
+3V
JL4
1
2
JP_NET10
MCH_PCIRST# 5
U15B
4
JL5
1
2
JP_NET10
6
PCIRST#
5
LCD_PCIRST# 14,20
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
+LAN_3V
JL6
1
2
JP_NET10
74AHC08_V
TSSOP14
VDD3
LAN_PCIRST# 15
E9
F9
E11
F10
V9
V8
V7
F15
F16
F17
F18
K14
GND
+3V
JL8
1
2
JP_NET10
MINIPCI_PCIRST#
16
U15C
9
JL9
1
2
JP_NET10
JL7
1
2
JP_NET10
8
10
CBE#[0..3]
CBE#[0..3] 15,16,17
74AHC08_V
TSSOP14
+1.5V
TV_PCIRST# 8
+VHI_ICH
GND
1
+1.5V
ICH4
BGA360_25_36
2
R680 0/NA
0805C_DFS
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCCHI0
VCCHI1
VCCHI2
VCCHI3
+LAN_1.5V
VDD1.5
F6
F7
E12
R6
T6
U6
G18
E13
F14
E20
1
R729
1
INT_PIRQG#
GPIO6
R213
1
R798
1
16,18,20 LFRAME#
16
LDRQ0#
SVDD3
R209
2
T2
R4
T4
U2
SUSCLK
INTRUDER#
RTC_RST#
5
SUSCLK
5,18
18
PWROK
RSMRST#
+VCC_RTC
RTC_VBIAS
RTC_X1
RTC_X2
1
R660 0
10,29 DPRSLPVR
3,5
HDPSLP#
+VCC_RTC
2
AA4
W6
W7
AB6
AA6
AB5
Y6
AC7
AC6
V20
U23
1
3
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
SUSCLK
INTRUDER#
RTCRST#
PWROK
RSMRST#
VCCRTC
VBIAS
RTCX1
RTCX2
LPC/FWH
RTC
DPRSLPVR
DPSLP#
SLP_S3#
SLP_S4#
SLP_S5#
RI#
PWRBTN#
SYS_RESET#
LANRST#
BATLOW#/TP[ 0 ]
SUS_STAT#/LPCPD
VGATE/VRMPWRGD
THERMTRIP#
THRM#
SMILINK 0
SMLINK 1
SMBUS SMBDATA
SMBCLK
SMBALERT#/GPIO 11
SPKR
CLK14
AC3
AB1
AB4
AC4
AA5
H23
J23
SLP_S4#
SLP_S5#
2
1
J516
2
1
180K
0603
2
1
R741 10K/NA
+VCC_RTC
CPU_THRMTRIP# 10
SB_THRM# 18
1
2
R217 0/NA
0603D_DFS
1
SMLINK0 10
SMLINK1 10
SMB_DATA 10
SMB_CLK 10
SMBALERT# 10
SBSPKR 10,12
14M_ICH 4
2 R178
0
1
0603
R723 10K
+5V
R220
4.7K
0603
RTC_RST#
D6
SLP_S4#
2
SLP_S5#
1
2 R695
0/NA
0805C_DFS
C696
0.1U
0603
50V
3
+3V
SUSC#
C665
0.1U
0603
50V
VDD5
D510
VDD3
R689
1K
0603
BAT54
C672
1U
0603
18,27,28
B
GND
+3V
R717
1K
0603
C655
10U
1206
10V
C
ICH4
BGA360_25_36
GND
+LAN_3V
1
0805
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
INTRUDER#
2
VDD3
HSTPCLK#
VCCPLL
D
V5REF
C676
0.1U
0603
50V
D509
BAT54
C635
1U
0603
V5REF_SUS
C641
0.1U
0603
50V
GND
BAW56
GND
GND
+3V
1
GND
1
C637
0.1U
0603
50V
2
1
C638
0.1U
0603
50V
2
1
2
1
2
C630
0.1U
0603
50V
C654
0.1U
0603
50V
A
GND
1
R181
A20GATE
2
0/NA
C239
1U
0603
2
C667
10U
1206
10V
C671
0.1U
0603
50V
1
C242
0.1U
0603
50V
2
1
R180
10K
0603
18
+LAN_1.5V
2 R702
0/NA
0805C_DFS
1
1
0805
1
+1.5V
+3V
2
2
0/NA
2
1
R225
C263
1U/NA
0603
1
C262
4.7U/NA
0805
+80-20%
RTC_X2
4
C668
1U
0603
50V
+VHI_ICH
C633
0.1U
0603
50V
Title
ICH4-M PCI_GPIO_AGTL_LPC_POWER(1)
GND
A20_GATE
Size
C
GND
Date:
5
C664
1U
0603
50V
2
1
C640
0.1U
0603
50V
1
1
C634
0.1U
0603
50V
2
1
1
C647
0.1U
0603
50V
GND
GND
4
1
GND
18P
C670
0.1U
0603
50V
5
1
2
NC1
2
2
NC0
AME8800AEEV/NA
SOT25
2
C256
1
1
32.768KHZ
C254
10U
1206
10V
GND
GND0
VIN
VOUT
2
X3
R206
10M
0603
1
2
3
1
1
4
18P
C261
2.2U/NA
0805
RTC_X1
2
1
1
2
U17
VDD5
2
C255
74AHC08_V
TSSOP14
2
R718
10M
0603
A
ICH_VGATE
2
22
0603
2
7
RTC_VBIAS
2
1
13
2
11
PWROK
1
R221
12
VRMPWRGD
2
U15D
29
GND
1
GND
VDD3
2
1.25MM/ST/MA-2
ACES
85205-0200
14
2
2
C697
0.047U
0603
1
1
1
2
1
LDRQ1#
2
V_CPU_IO
V_CPU_IO
V_CPU_IO
D1
C23
C21
C19
C17
C15
C6
B22
B20
B18
B16
B12
B9
A22
A20
A18
A16
A4
A1
C238
1U
0603
2
1
V5REF_SUS
C22
ICH_VGATE
1
1
GND
C632
0.1U
0603
50V
+3V
+3V
1
2
R765
C645
0.1U
0603
50V
4,18,20,22,25,26,27,29
ICH_RI# 15
ICH_PWRBTN# 18
ICH_SYS_RESET# 10
ICH_LAN_RST# 10
ICH_BATLOW# 10
2
R767
1K
0603
C237
10U
1206
10V
GND
LFRAME#/FWH4
LDRQ0#
LDRQ1#
C706
1U
0603
D511
BAV70LT1
1
SUSB#
3,4,5,29
8
3
8
10,16,17
8
8
8
V5REF1
V5REF2
E15
P14
U18
AA23
+1.5V
SERIRQ
ICH4
BGA360_25_36
2
0
0603
Y4
Y2
AA2
Y1
AA1
Y3
Y5
AB2
AB3
V19
W20
V1
4
2
1
LAD0
LAD1
LAD2
LAD3
LAD[0..3]
16,18,20 LAD[0..3]
2 8.2K
0603
2 8.2K
0603
2 8.2K
0603
2 8.2K
0603
2 8.2K
0603
2 8.2K
0603
T5
U3
U4
LDRQ1#
STOP_PCI#
TP503
STOP_CPU#
ICH_GPIO21
CPUPERF#
ICH_GPIO23
PCLKRUN#
ICH_GPIO25
ICH_GPIO27
ICH_GPIO28
E7
V6
V5REF_SUS
1
R216
CRT_IN#
J22
10,16,17,18 SERIRQ
RP510
8.2K*4
1206
Y21
SUSA#
W18
1
W19
ICH_GPIO21
T3
Y20
ICH_GPIO23
J21
AC2
ICH_GPIO25
V2
ICH_GPIO27
W1
ICH_GPIO28
W4
V5REF
+VCCP
3
PCI_LOCK#
POWER
STP_PCI/GPIO 18
SLP_S1#/GPIO 19
STP_CPU#/GPIO 20
C3_STAT#/GPIO 21
CPUPERF#/GPIO 22
SSMUXSEL/GPIO 23
CLKRUN#/GPIO 24
GPIO 25
27
MANAGEMENT GPIO
GPIO 28
SCI#
18
WAKE_UP# 10,18
1
1
RP43
8.2K*4
1206
GPIO
V5
W3
GND
VCCLAN1_5/VCCSUS1_5
VCCLAN1_5/VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
2
R208
A20_GATE
18 HRCIN#
10 CPU_FERR#
3,20 HINIT#
GPIO 12
GPIO 13
1
PCI_REQ1#
R179 2
0
1
STPCLK#
A20M#
CPUSLP#
CPUPWRGD
INTR
NMI
AGTL+
SMI#
IGNNE#
A20GATE
RCIN#
FERR#
INIT#
GND
AGPBUSY# 5
KBD_US/JP# 18
EXTSMI# 18
2
1
V23
AB23
U21
Y23
AB22
V21
W23
W21
Y22
U22
AA21
V22
GPIO6
R2
R3
V4
1
R205
RP38
8.2K*4
1206
HSTPCLK#
HSTPCLK#
HA20M#
HSLP#
HPWRGD
HINTR
HNMI
HSMI#
HIGNNE#
AGPBUSY#/GPIO 6
GPIO 7
GPIO 8
2
INT_PIRQD#
C648
0.1U
0603
50V
1
1
2
3
4
3
3
3
3
3
3
3
3
GND
8
7
6
5
2 8.2K
0603
8
7
6
5
2 100K
0603
8
7
6
5
C646
0.1U
0603
50V
2
ICH_GPIO21
PCI_SERR#
PCI_PERR#
PCI_DEVSEL#
10K
2
1
2
3
4
R201 1
8.2K
8.2K
8.2K
8.2K
8.2K
1
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
ICH_GPIO1
2
2
2
2
2
2
PCI_REQ3#
PCI_REQ0#
1
2
3
4
R215 1
PCI_REQ4#
B
1
1
1
1
1
1
0603
0603
0603
0603
0603
APICCLK
APICD_0
APICD_1
2
J19
H19
K20
2
1
2
R665 1
R192
R722
R728
R753
R732
C623
0.1U
0603
50V
U12D
R666 1
0
INT_PIRQE#
INT_PIRQF#
INT_PIRQA#
ICH_GPIO5
PCI_GNT3#
C644
0.1U
0603
50V
2
2
RP41
8.2K*4
1206
8
7
6
5
2
1
2
3
4
1
INT_PIRQB#
PCI_GNT4#
PCI_REQ2#
INT_PIRQC#
C669
10U
1206
10V
2
+3V
1
1
C
POWER
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
K10
K12
K18
K22
P10
T18
V14
U19
L23
M14
P18
T22
LPCBIOS_RST# 20
D22
AC23
AC18
AC14
AC10
AC5
AC1
AB20
AB7
AA22
AA16
AA12
AA9
AA3
Y19
Y7
W22
W8
W5
V17
V15
V3
U20
T23
T19
T1
R21
R18
R5
P22
P20
P13
P11
P3
N23
N21
N19
N14
N13
N12
N11
N10
N5
M13
M12
M11
M1
M22
L21
L14
L13
L12
L11
L10
K23
M20
K19
K13
K11
K3
J6
H1
G21
G19
G6
G3
F8
E22
E21
E19
E18
E17
E16
E14
E10
D23
D21
D19
D17
D15
D12
D8
D4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
INT_PIRQG#
ICH_GPIO5
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
+3V
3
PCIRST#0 11,22
1
ICH_GPIO5
D
P4
D2
R1
D3
P2
E1
P1
E2
M5
E4
N3
E3
N2
E5
N1
F4
F5
L3
H2
L2
G4
L1
G2
K2
J5
H4
J4
G5
K1
H3
J3
H5
7
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
8
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
14
16
15
16
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI0 2
PIRQF#/GPIO 3
PIRQG#/GPIO 4
PIRQH#/GPIO 5
7
INT_PIRQB# INT_PIRQC#
D5
C2
B4
A3
C8
D7
C3
C4
15,16,17
14
17
1 R727 0 2
1 R210 0 2
1 R204 0 2
AD[0..31]
7
INT_PIRQA#
2
AD[0..31]
2
U12B
1
3
2
LPCKBC_RST# 18
JL2
1
2
JP_NET10
U15A
1
1
JL1
1
2
JP_NET10
2
14
+3V
3
2
Document
Number
Rev
411682810001
01
1
9
of
29
5
4
3
2
1
VDD3
+VCCP
USBRBIAS#
AC97
USBRBIAS
22.6 ohm , 1%
RDDP
recommanded.
1
VDD3
2
1
3 CPU_THRMTRIP_OUT#
R658
2
CPU_THRMTRIP# 9
56 0603
Q518
VDD3
1
ICH_SYS_RESET#
SMLINK0
9
SMBALERT# 9
ICH_BATLOW# 9
ICH_SYS_RESET# 9
SMBDATA 4,7
1
2
R757 0/NA
R688
10K
0603
2
2
D
Q521
2N7002
R188
10
0603
C
SMB_DATA
VDD3
9
ICH4
BGA360_25_36
ICH_BATLOW#
9
2 R668 SPK_OFF
10K/NA
1
0603
R744
10K
0603
2
9
12,19
12,19
12,19
12,19
12
19
R759
10K
0603
Q522
2N7002
S
2
EE_DOUT
R743
2.2K
0603
G
R748
2.2K
0603
GND
ACSYNC
ACSDOUT
ACBITCLK
ACRST#
ACSDIN0
ACSDIN1
SMBALERT#
SMLINK1
TEMP_ALERT# 3,20
2
C9
D9
B8
C13
D13
A13
B13
SMLINK0
+3V
MMBT3904L
TP4
10K
D11
D10
C12
A8
SMLINK1
+3V
1
R593 0603 1K
1
2
B
2 R227
47K
2 R211
47K
2 R731
10K
2 R231
10K
2 R226
10K
1
0603
1
0603
1
0603
1
0603
1
0603
1
+VCCP
D
GND
1
2
4
1
R170
22
0603
1%
ACSYNC
ACSDOUT
ACBITCLK
ACRST#
ACSDIN0
ACSDIN1
ACSDIN2
66M_ICH
2 R219
10K
2 R224
10K
2 R745
10K
1
0603
R657
56
0603
HI_COMP
HI_VSWING
HI_VREF
1
0603
1
0603
WAKE_UP#
G
CLK48
1
A23
EE_DIN
EE_CS
EE_SHCLK
EE_DOUT
HUB_STB# 5
HUB_STB 5
1
R190 1
ICH_LAN_RST#
56
0603
+VCCP
9,18
9,15,16,17 PCI_PME#
D
SMB_CLK
S
SMBCLK
D
S
B23
GPIO
A10
A9
A11
B10
C10
A12
B11
C11
CPU_FERR# 9
2 0603
8.2K
2 0603
8.2K
2 R737
10K/NA
D
S
F19
4 USBCLK_ICH
LANRXD0
LANRXD1
LANRXD2
LANTXD0
LANTXD1
LANTXD2
LANRSTSYNC
LANCLK
HFERR#
2
2
ICH_GPIO41
8 ICH_GPIO41
13
SPK_OFF
11
SIDERST#
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO 40
GPIO 41
GPIO 42
GPIO 43
R182
1
GND
1
R212
1
0603
9 ICH_LAN_RST#
2
N20
P21
R23
R22
M23
T21
R166
9,16,17 PCLKRUN#
2
ICH_GPIO37
8
ICH_GPIO37
11
IDERST#
16 MINIPCI_ACT#
HI_COMP
HIVSWING
HIREF
CLK66
3
1
9,16,17,18 SERIRQ
R169
56
0603
C
J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23
16 WIRELESS_PD#
14
LCD_ID0
14
LCD_ID1
14
LCD_ID2
HI_STB#/HI_STBF
HI_STB/HI_STBS
HUB_HI0
HUB_HI1
HUB_HI2
HUB_HI3
HUB_HI4
HUB_HI5
HUB_HI6
HUB_HI7
HUB_HI8
HUB_HI9
HUB_HI10
R176 1
56
E
USBOC1#
USBOC3#
USBOC4#
USBOC5#
USBOC1#
USBOC3#
OC#0
OC#1
OC#2
OC#3
OC#4
OC#5
HUB
L19
L20
M19
M21
P19
R19
T20
R20
P23
L22
N22
K21
1
21
21
B15
C14
A15
B14
A14
D14
USB
HI 0
HI 1
HI 2
HI 3
HI 4
HI 5
HI 6
HI 7
HI 8
HI 9
HI 10
HI 11
4,7
1
2
R736 0/NA
R184
10K
0603
2
D
USBP_0
USBP_0#
USBP_1
USBP_1#
USBP_2
USBP_2#
USBP_3
USBP_3#
USBP_4
USBP_4#
USBP_5
USBP_5#
+3V
5
1
C20
D20
A21
B21
C18
D18
A19
B19
C16
D16
A17
B17
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3-
HUB_HI[0..10]
2
21
21
21
21
21
21
21
21
HUB_HI[0..10]
1
U12E
C
GND
GND
GPIO CHARACTERISTIC LIST
NAME
USBOC4#
USBOC5#
1
+1.5V
2
+1.5V
R163
130
0603
1%
R168
487
1%
+1.5V
R177
HI_VSWING
1
R167
150
0603
R158
150
0603
C241
0.1U
0603
50V
+3V
ACSDOUT
2
2
C236
0.01U
0603
2
C240
0.1U
0603
50V
2
2
2
C235
0.01U
0603
1
1
1
48.7
CURRENT DEFINE
I
MAIN POWER WELL
CRT_IN#
GPIO[1]
TYPE
I
MAIN POWER WELL
GPIO[2]
I
MAIN POWER WELL
INT_PIRQE#
GPIO[3]
I
MAIN POWER WELL
INT_PIRQF#
GPIO[4]
I
MAIN POWER WELL
INT_PIRQG#
GPIO[5]
I
MAIN POWER WELL
GPIO[6]
I
MAIN POWER WELL
AGP_BUSY#
GPIO[7]
I
MAIN POWER WELL
KB_US/JP#
GPIO[8]
I
RESUME POWER WELL
EXTSMI#
GPIO[11]
I
RESUME POWER WELL
SMBALERT#
GPIO[12]
I
RESUME POWER WELL
SCI#
GPIO[13]
I
RESUME POWER WELL
WAKE_UP#
GPIO[16]
O
MAIN POWER WELL
B/CB#
GPIO[17]
O
MAIN POWER WELL
GPIO[18]
O
MAIN POWER WELL
STOP_PCI#
GPIO[19]
O
MAIN POWER WELL
SUSA#
GPIO[20]
O
MAIN POWER WELL
STOP_CPU#
GPIO[21]
O
MAIN POWER WELL
GPIO[22]
OD
MAIN POWER WELL
GPIO[23]
O
MAIN POWER WELL
GPIO[24]
I/O
RESUME POWER WELL
GPIO[25]
I/O
RESUME POWER WELL
X
GPIO[27]
I/O
RESUME POWER WELL
X
GPIO[28]
I/O
RESUME POWER WELL
GPIO[32]
I/O
MAIN POWER WELL
WIRELESS_PD#
GPIO[33]
I/O
MAIN POWER WELL
LCDID0
GPIO[34]
I/O
MAIN POWER WELL
LCDID1
GPIO[35]
I/O
MAIN POWER WELL
LCDID2
GPIO[36]
I/O
MAIN POWER WELL
X
X
2
HI_VREF
1
2
1
1
1
HI_COMP
STRAPPING
POWER PLANE
GPIO[0]
EE_DOUT
GND
GND
1
4.7K/NA
2
0603
R709
1
4.7K/NA
2
0603
R197
GND
X
+VHI_ICH
B
11
U12C
PD_D[0..15]
PD_D[0..15]
PD_D15
PD_D14
PD_D13
PD_D12
PD_D11
PD_D10
PD_D9
PD_D8
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
Y11
W11
W10
AB10
W9
AC9
Y9
AB9
AA8
Y8
AB8
AA7
AA10
Y10
AC11
AB11
11
11
11
11
11
PDIOW#
PDDACK#
PDDREQ
PDIOR#
PIORDY
W12
Y12
AA11
AC12
AB12
11
11
11
PDA0
PDA1
PDA2
AA13
AB13
W13
11
11
PDCS1#
PDCS3#
Y13
AB14
PDD 15
PDD 14
PDD 13
PDD 12
PDD 11
PDD 10
PDD 9
PDD 8
PDD 7
PDD 6
PDD 5
PDD 4
PDD 3
PDD 2
PDD 1
PDD 0
PDIOW#
PDDACK#
PDDREQ
PDIOR#
PIORDY
PDA0
PDA1
PDA2
PDCS1#
PDCS3#
IDE
SDD 15
SDD 14
SDD 13
SDD 12
SDD 11
SDD 10
SDD 9
SDD 8
SDD 7
SDD 6
SDD 5
SDD 4
SDD 3
SDD 2
SDD 1
SDD 0
SDIOW#
SDDACK#
SDDREQ
SDIOR#
SIORDY
SDA2
SDA1
SDA0
SDCS1#
SDCS3#
IRQ14
IRQ15
A
9,29 DPRSLPVR
SD_D[0..15]
Y17
AA17
Y16
AB16
Y15
AA15
AC15
Y14
AA14
W14
AB15
W15
AC16
W16
AB17
W17
SD_D[0..15] 11
SD_D15
SD_D14
SD_D13
SD_D12
SD_D11
SD_D10
SD_D9
SD_D8
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0
2
0603
2
0603
B
R661
R659
GND
X
CPUPERF#
X
+3V
9,12
AA18
AB19
AB18
Y18
AC19
SDIOW#
SDDACK#
SDDREQ
SDIOR#
SIORDY
11
11
11
11
11
AC21
AC20
AA20
SDA2
SDA1
SDA0
11
11
11
AB21
AC22
SDCS1#
SDCS3#
11
11
AC13
AA19
IRQ14
IRQ15
11
11
ICH4
BGA360_25_36
1
4.7K/NA
1
4.7K
SBSPKR
1
4.7K/NA
2
0603
PCLKRUN#
R174
STRAPPING AT RISING EDGE OF PWROK
X
X
STRAPPING PINS
FUNCTIONS
GPIO[37]
I/O
MAIN POWER WELL
ACSDOUT
SAFE MODE
GPIO[38]
I/O
MAIN POWER WELL
X
IDERST#
EEDOUT
RESERVED
GPIO[39]
I/O
MAIN POWER WELL
MINIPCI_ACT#
GNTA#
OP-BLOCK SWAP OVERRIDE
GPIO[40]
I/O
MAIN POWER WELL
DPRSLPVR
HUB INTERFACE TERMINATION SCHEME
GPIO[41]
I/O
MAIN POWER WELL
HUB_ICH_COMP
HUB INTERFACE SCHEME(1.0 OR 1.5)
GPIO[42]
I/O
MAIN POWER WELL
X
SPK_OFF
SBSPKR
NO REBOOT
GPIO[43]
I/O
MAIN POWER WELL
SIDERST#
X
A
Title
ICH4-M USB_HUB_GPIO_AC97_IDE(2)
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
10
of
29
5
4
2
PD_D[0..15]
Primary EIDE Connector
For Hard-Disk
RP40
0*8/NA
RPX8
RP_16P8R_4016_DFS
R0A reverse the pin definition
D
J514
R233
1
C_RSTDRV1#
C_PD_D7
C_PD_D6
C_PD_D5
C_PD_D4
C_PD_D3
C_PD_D2
C_PD_D1
C_PD_D0
2
10K/NA
0603
GND
Enhance driving force for GPO.
+3V
+5V
C_PDDREQ
C_PDIOW#
C_PDIOR#
C_PIORDY
C_PDDACK#
C_PINTRQ
C_PDA1
C_PDA0
C_PDCS1#
+3V
2
2
3
1
2
2
R185
10K
0603
1
10
10
10
10
10
10
10
Q19
DTC144TKA
BAW56
20
3
1
R165
0
R697
4.7K
0603
2
PCIRST#0
D5
2
IDERST#
9,22
1
R162
10K
0603
R1
10
2
1
1
+3V
PDDACK#
PDIOR#
PDIOW#
PDDREQ
0603 22 1
C_PDCS1#
C_PDA2
C_PDDACK#
C_PIORDY
C_PDIOR#
C_PDIOW#
C_PDDREQ
16
15
14
13
12
11
10
9
2 R187
C_RSTDRV1#
GND
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
C_PD_D8
C_PD_D9
C_PD_D10
C_PD_D11
C_PD_D12
C_PD_D13
C_PD_D14
C_PD_D15
R196
1
2
470
GND
C_PDA2
C_PDCS3#
FM/22PX2/2MM
SUYIN
20038A-44G2-J
L49
1
C244
0.1U
0603
50V
GND
RP37
0*8/NA
RPX8
RP_16P8R_4016_DFS
1
0603D
1
2
3
4
5
6
7
8
PDCS1#
PDCS1#
PDA2
PDDACK#
PIORDY
PDIOR#
PDIOW#
PDDREQ
HDD_LED#
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
GND
C243
0.1U
0603
50V
GND
2
+5V
120Z/100M
2012
1
RP39
0*8/NA
RPX8
RP_16P8R_4016_DFS
2
1
2
3
4
5
6
7
8
C_PD_D9
C_PD_D8
C_PD_D10
C_PD_D11
C_PD_D7
C_PD_D5
C_PD_D6
C_PD_D4
C_PD_D0
C_PD_D1
C_PD_D15
C_PD_D14
C_PD_D3
C_PD_D12
C_PD_D2
C_PD_D13
1
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
2
D
1
2
3
4
5
6
7
8
1
PD_D[0..15]
PD_D9
PD_D8
PD_D10
PD_D11
PD_D7
PD_D5
PD_D6
PD_D4
PD_D0
PD_D1
PD_D15
PD_D14
PD_D3
PD_D12
PD_D2
PD_D13
0603D
R172 0
1
1
2
10
3
C245
10U
1206
10V
GND
R194
5.6K/NA
0603
C
2
C
GND
1
+3V
2
R693
8.2K
0603
10
10
10
10
PDCS3#
PDA0
PDA1
PDCS3#
PDA0
PDA1
IRQ14
8
7
6
5
C_PDCS3#
C_PDA0
C_PDA1
C_PINTRQ
1
2
3
4
RP507
0*4/NA
1206
RPSOA_8C_DFS
SD_D[0..15]
SD_D10
SD_D5
SD_D9
SD_D11
SD_D4
SD_D7
SD_D8
SD_D6
SD_D14
SD_D1
SD_D15
SD_D0
SD_D13
SD_D12
SD_D3
SD_D2
B
2
R161
0
0603D
1
Secondary EIDE Connector
For CD-ROM
RP32
0*8/NA
RPX8
RP_16P8R_4016_DFS
W/S=16/12/12/16 mils
10
10
10
10
10
10
10
C_RSTDRV2#
C_SD_D7
C_SD_D6
C_SD_D5
C_SD_D4
C_SD_D3
C_SD_D2
C_SD_D1
C_SD_D0
C_SDIOW#
C_SIORDY
C_SINTRQ
C_SDA1
C_SDA0
C_SDCS1#
1
GND
2
2
SDA1
IRQ15
SDDACK#
SIORDY
SDIOW#
SDDREQ
SDIOR#
R673
4.7K
0603
1
2
3
4
5
6
7
8
SDA1
SDACK#
SIORDY
SDIOW#
SDREQ
16
15
14
13
12
11
10
9
0603 22 1
C_SDA1
C_SINTRQ
C_SDDACK#
C_SIORDY
C_SDIOW#
C_SDDREQ
C_SDIOR#
2 R183
C_RSTDRV2#
20
RP31
0*8/NA
RPX8
RP_16P8R_4016_DFS
1
Q18
DTC144TKA
W=12 mils
J510
12 CDROM_LEFT
12 CDROM_COM M
R156
10K/NA
0603
R655
8.2K
0603
3
1
BAW56
B
+3V
1
1
R164
10K
0603
2
22
3
1
2
1
R664
5.6K/NA
0603
CD_LED#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
CDROM_RIGHT 12
C_SD_D8
C_SD_D9
C_SD_D10
C_SD_D11
C_SD_D12
C_SD_D13
C_SD_D14
C_SD_D15
C_SDDREQ
C_SDIOR#
GND
C_SDDACK#
C_SDA2
C_SDCS3#
R109
GND1
GND2
R108
0/NA
0603D_DFS
GND
2
470/NA
A
1
A
GND
GND
RA/.8MM/H5
SUYIN
80094A-050G1T
GND
L50
120Z/100M
2012
RP30
0*4/NA
1206
RPSOA_8C_DFS
C141
0.1U
0603
50V
1
C_SDA0
C_SDCS1#
C_SDCS3#
C_SDA2
C140
0.1U
0603
50V
2
8
7
6
5
1
1
2
3
4
1
SDA0
SDCS1#
SDCS3#
SDA2
SDA0
SDCS1#
SDCS3#
SDA2
GND
2
2
10
10
10
10
1
2
+5V
1
SIDERST#
PCIRST#0
2
10
R160
10K
0603
D4
R1
0603D
0
R171
RP33
0*8/NA
RPX8
RP_16P8R_4016_DFS
+5V
+3V
1
C_SD_D10
C_SD_D5
C_SD_D9
C_SD_D11
C_SD_D4
C_SD_D7
C_SD_D8
C_SD_D6
C_SD_D14
C_SD_D1
C_SD_D15
C_SD_D0
C_SD_D13
C_SD_D12
C_SD_D3
C_SD_D2
1
+3V
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
2
+3V
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
SD_D[0..15]
2
10
C143
10U
1206
10V
Title
GND
GND
Size
C
Date:
5
4
3
HDD & CD-ROM
GND
2
Document
Number
Rev
01
411682810001
1
11
of
29
5
4
3
2
1
1
+3V
2
R760
10K/NA
0603
2
AU_XIN
2 R758
0
1
0603
Q524
1
0.01U
0603
R761
10K/NA
0603
AVDDAD
SI2301DS
+3V
JS507
2
R800
1
SHORT-SMT4
C691
10U
1206
10V
D
+5V_PP
2
D
S
4.7 1206
1
2
C759
22U
1206
10V
G G
1
C692
0.1U
0603
50V
2
1
2
C730
0.1U
0603
50V
1
GND
C724
10U
1206
10V
2
C810
22P
0603
5%
C702
0.1U
0603
50V
2
1
C809
22P
0603
5%
2
C808
22P
0603
5%
2
2
1
GND
1
1
1
1
2
ACRST_CODEC#
ACBITCLK_CODEC
ACSYNC
2
D
D
S
C688 1
4 14M_CODEC
H8_SUSB 18
AGND
GND
AGND
AGND
R782
AGND
MODEM_SPK
2
10K
0603
1
CD-GND
XTL/OUT
NC_9
PCBEEP
AUX-L
31
0603
10V
1U/NA
1
2 C705
32
0603
10V
1
2 C699
33
0603
50V 1000P/NA 1
1U/NA
2 C695
34
GND
40
43
44
45
46
47
48
C700
1
0.1U/NA
EMP202
X
Cap pin33:
1U
X
Cap p33/34
X
X
0603
1
0.1U/NA
2
50V
0603
LINE-OUT-L
NC_2
LINE-OUT-R
NC_3
PHONE
NC_4
NC_5
NC_6
NC_7
XELSEL
EAPD
TEST
0.33U 16V
0603
19
C744 1
2
0.33U 16V
0603
16
C741 1
2
1U/NA
17
C742 1
2
1U/NA
14
C739 1
2
1U 10V
0603
15
C740 1
2
1U 10V
0603
R764
0/NA
0603
1
2
2
35
36
NC_11
NC_12
NC_13
AOUT_L
13
AGND
R242 1
AOUT_R
13
C738 1
2
1U 10V
0603
37
C703 1
2 1U/NA 10V
0603
39
C756 1
2 1U/NA 10V
0603
41
C274 1
2 1U/NA 10V
0603
C719 1
2 1000P 50V
0603
C711 1
2 1000P 50V
0603
2 0
CDROM_RIGHT
0603
R240 1
2 0
R796
0/NA
0603
2 0
CDROM_RIGHT 11
CDROM_LEFT
0603
R241 1
0603
CDROM_LEFT 11
CDROM_COM M
R794
0/NA
0603
CDROM_COM M 11
R795
0/NA
0603
C
MIC1
AGND
13
29
AFILT1
30
AFILT2
R229
0
0603
AGND
1
2
AGND
MONO_OUT
VREF
C755
47P
0603
10%
D5.8/H2.0
EM147TK
JO524
R144
0
0603
28
VREFOUT
2
ALC101
PQFP48_0.5MM
C722
0.1U
0603
50V
2
26
42
4
7
+
-
MONO_OUT 19
C694
1000P/NA
0603
20mil
27
1
2
2
Cap pin31: 0.1U
2
50V
C710
NC_1
C743 1
1
1
ALC201
AUX-R
DVSS1
DVSS2
AGND
CHIP
NC_0
18
MIC
0603
1
2 C708
0603
0603
1
1
0.33U 16V
1
2
GND
C709
22P/NA
0603
5%
1U/NA
AVSS1
AVSS2
1
1
2
C704
22P/NA
0603
5%
50V
2
2
CD-L
XTL/IN
NC_10
0603
C745 1
2
CD-R
24.576MHZ/NA
C
20
C732
0.1U
0603
50V
C734
1U
0603
10V
2
12
NC_8
2
PC_BEEP
1U/NA 10V
2
1M/NA
X503
2
+80-20%
1U 10V
2
1
1
3
0805
2
MIC2 C747 1
2
0603
2
2 2.2U
MIC1 C746 1
22
MODEM_SPK 19
2
1 R230
2
C749 1
21
1
AU_XIN
24
2
R7
0603
MIC1
1
R776
0603
ACBITCLK_CODEC
+80-20%
C753
0.1U/NA
0603
50V
1
2
LINE-L
LINE-R
RESET#
SDATA/OUT
SDATA/IN
SYNC
BIT/CLK
0805
R786
1K
0603
1
1
22
2
11
5
8
10
6
2 2.2U
2
ACRST_CODEC#
2 0603
C748 1
23
1
0
U519
AVDD1
AVDD2
DVDD1
DVDD2
ACRST# R881
1
10,19 ACRST#
ACSDOUT
10,19 ACSDOUT
ACSDIN0
10
ACSDIN0
ACSYNC
10,19 ACSYNC
1
10,19 ACBITCLK
22
1
GND
25
38
GND
1
9
GND
AGND AGND
AGND
GND
AGND
H8_AVREF
1
2
R232
0/NA
0603
1
4.7K
1608
L33 600Z/100M
1
R506 1
R238
R237
2
GND
2
0603
1
4.7K
2
0603
For EMP202
0
0603
GND
AGND
R186
1
GND
Current selection
AGND
R189
2
0
0603
2
1
GND
AGND
FREQ.
ID1#
ID0#
14.318MHz
OPEN
OPEN
27MHz
OPEN
1K
48MHz
1K
OPEN
24.576MHz
1K
1K
2
0
0603
Cap. pin39: 1000P
560P
Cap. pin41: 1000P
560P
Cap. pin20: 1U
0.33U
Cap. pin18: 1U
0.33U
Cap. pin19: 1U
0.33U
C266
4.7U
0805
+80-20%
C267
2.2U
0805
+80-20%
0
RA/D6/6P
2SJ-SB2014D3
CONN_JACK_SB2014
2
1
1
EMP202
1
ALC201
C265
100P
0603
10%
JO64
AGND
CAGND
When using an external clock replace C211
with 0 ohm resistor.(updated 10/19/2001)
AGND
2
2
1
1
CHIP
2
2
0
0603
GND
R151
2
1
5 J8
4
3
6
2
1
0603
2
R150
B
L546
600Z/100M
1608
R236
0
0805
1
2
B
AGND
2
R504
0/NA
0603
AGND
GND
1
1
AGND
CAGND
+5V
C701
1
2
9,10 SBSPKR
CARDSPK#1
CARDSPK#
1
2
3
2
A
B
GND
VCC
Y
NC7S32
SOT25
5
4
2
R768
100K
0603D
GND
C720
1
1
2
0.1U
0603
50V
A
PC_BEEP
R769
1K
0603
1%
R762
47K
0603
2
2
0.1U
50V
0603
1
17
1
U518
C689
A
0.1U
50V
0603
GND
Title
GND
Size
C
Date:
5
4
3
2
Audio Codec
Document
Number
Rev
01
411682810001
1
12
of
29
5
4
3
2
1
1
AVDDAD
2
R882
0/NA
0603
L541
+5V
1
D
1
1
+
2
C718
0.1U
0603
50V
2
1
2
C521
0.1U
0603
50V
2
D
120Z/100M
2012
C269
100U
16V
CPWX6.6
J503
1
2
R191
1
2
0
0603
AGND
HDR/MA-2
ACES
85204-0200
GND
U18
RHP_IN
RLINE_IN
20
23
C26
1U 1
2 0603 8
C43
1U 1
2 0603 14
2
3
LINE_IN#
15
ROUT+
ROUT-
RIN
PVDD0
PVDD1
PC-BEEP
VDD
GAIN0
GAIN1
BYPASS
SEBTL
SHUTDOWN
21
16
ROUT+
ROUT-
7
18
19
11
22
MUTE#
1
GAIN0
GAIN1
RHPIN
RLINEIN
ACES
ST/MA-2
85204-0200
291000020206
2
2
2
1
2
AGND
C714
+ 100U
20%
6.3V
JO13
JO14
JO9
JO10
1
RHP_IN
1
AGND
1608
1608
C
C715
+ 100U
20%
6.3V
J9
16V 20%
C86
0.47U 0402
1
2
RLINE_IN
16V 20%
C89
0.47U 0402
1
2
LHP_IN
16V 20%
C246
0.47U 0402
1
2
LLINE_IN
GND
R244 22 2
R243 22 2
GND
1 0603
1 0603
GND
GND
L35 1
L34
1
2 600Z/100M
1608
2 600Z/100M
1608
1
2
6
3
4
5
AGND
C723
100P
0603
10%
2
+5V
2
2
AGND
C735
100P
0603
10%
1
2
2
16V 20%
RA/D6/6P
2SJ-SB2014D3
CONN_JACK_SB2014
1
R785
1K
0603
2
R779
1K
0603
1
AOUT_L
AOUT_L
0.47U 0402
2
2 600Z/100M
2 600Z/100M
1
1
1
1
L3
L4
1
12
AOUT_R
AOUT_R
TPA0212_GND
TSSOP24_TPA0102
J2
LOUT+
LOUT-
25
26
27
28
29
2
AGND
C59
12
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
4
9
1
C
LOUT+
LOUT-
LIN
1
30
31
32
33
34
2
2 0603 10
C44
1U
0402
+80-20%
10V
1
1U 1
LLINEIN
LHPIN
1
12
13
24
2
C45
5
6
GND0
GND1
GND2
GND3
1
LLINE_IN
LHP_IN
HP/LINE
2
17
1
2
MUTE#
B
R57
R58
10K 1
10K/NA
1
2 0603
2 0603
10
2
SPK_OFF
R1
2
Q20
R507
2
1
2
1
2
0
0603
100K
0603
1
R37
10K
0603
1
JO66
JO65
GND
C268
0.1U
0603
50V
CAGND
CAGND
CAGND
B
1
GAIN0
GAIN1
LINE_IN#
3
2 0603
2 0603
R245
R228
100K
0603
2
10K/NA
1
10K 1
R239
100K
0603
AGND
1
+3V
R55
R56
AGND
1
+5V
+5V
C507
1U
0603
AGND
2
1
DTC144TKA
GND
GND
*
GAIN0
GAIN1
0
0
SE/BTL#
0
-2 V/V
AV
0
1
0
-6 V/V
1
0
0
-12 V/V
1
1
0
-24 V/V
X
X
1
-1 V/V
A
A
Title
Size
C
Date:
5
4
3
2
OP AMP
Document
Number
Rev
01
411682810001
1
13
of
29
5
4
3
2
1
1
1
R5
10K
0603
R2
10K
0603
2
LCD_ID0
LCD_ID1
LCD_ID2
D
1
LCD_ID0
LCD_ID1
R3
1K/NA
0603
1%
2
GND1
GND2
1
TXOUT0- 5
TXOUT0+ 5
R8
R4
1K/NA 1K/NA
0603
0603
1%
1%
2
LCD_ID2
10
10
10
TXOUT2- 5
TXOUT2+ 5
2
5 TXOUT15 TXOUT1+
R6
10K
0603
1
5 TXCLKOUT05 TXCLKOUT0+
D
1
3
5
7
9
11
13
15
17
19
2
J1
2
4
6
8
10
12
14
16
18
20
2
+3V_LCDVCC
AU 14" TFT XGA : B141XN04-2(UB141X03)
Hydis 14" TFT XGA : HT14X13-102
Chi-mei 14" TFT XGA : N141X6-L01
Hydis 15" TFT XGA : HT15X34-100
AU 15" TFT XGA : B150XG02
Hannstar 15" TFT XGA : HSD150PX14-A
Samsung 15" TFT XGA : LTN150XB-L03
AU 15" TFT SXGA+ : B150PG01
1
+3V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
LCD CONNECTOR
GND
GND
MA/10PX2/ST
ACES
87216-2000
GND
PU1
4
1
DVMAIN
C5
0.1U
0603
50V
C3
10U/NA
1206
10V
2
R514
1K
0603
C504
100P
0603
10%
1
MICROSMDC110
C8
0.1U
0805
10%
1
+3V
2
GND
C
R10
Q1
R1
GND
GND
J502
470K
0603
16
1
3
GND
1
CRT_IN#
1
2
1
GND
2
GND
2
1
GND
C7
10U
1206
10V
2
1
1
1
2
C6
0.1U
0603
50V
2
GND
C4
1000P
0603
2
2
C2
1000P
0603
C1
0.1U
0603
50V
9
+3V
F1
8
7
6
5
G
1
S
D
3
2
1
2
2 120Z/100M 2012
1
2
L2
1
SI4800DY
SO8
+3V_LCDVCC
R11
10K
0603
2
1
DTC144TKA
VGA_RED
VGA_DDC2B
VGA_GREEN
2
2 FPVCC
3
1
FPVCC
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
VGA_BLUE
5
LCD_PCIRST# 9,20
VGA_DDDA
D1
BAW56
VGA_HSYNC
VGA_VSYNC
VGA_DDCK
C
17
VGA
SUYIN
7535S-15G2T-05
CONN_SYN7535S_15GT
331720015006 JL501
+1.5V
2
GND_CRT15
SHORT-SMT4
GND
D612
GND_CRT15
D613
BAV99
F501
MICROSMDC110
3
BAV99
3
3
BAV99
1
SHORT-SMT4
JL502
1
2
D611
2
1
2
1
2
1
2
+5V
GND
B
B
1
+5V
CRT_G
5
CRT_B
K
1
2 L503120Z
1608
1
2 L504120Z
1608
1
2 L505120Z
1608
L510
VGA_RED
VGA_DDC2B
VGA_GREEN
2 2012
1
120Z/100M
VGA_BLUE
G
CRT_R
5
R515
2.2K
0603
2
2
R511
2.2K
0603
5
D1FS4
D503
1
1
A
+3V
VGA_DDDA
D
D
S
Q504
2N7002
S
D
120Z/100M 1608
120Z/100M 1608
120Z/100M 1608
VGA_HSYNC
1
2 L509
120Z/100M 1608
VGA_DDCK
VGA_VSYNC
2
3.3P 3.3P 3.3P
060306030603
50V 50V 50V
R40
75/NA
1%
R51
75/NA
1%
JO2
JO6
JO4
JO3
JO5
JO7
2
2
2
2
2
2
2
C503
10U/NA
1206
10V
1
1
1
1
1
1
C779C780C781
2
22P*4
1206
1
1
1
2
CP503
3.3P
0603
50V
GND
R9
75
1%
JO8
1
1
1
1
1
AHCT1G08DBV
SOT25
A
1
1
2
2
0603
3.3P
0603
50V
4
3
2
1
CRT_HSYNC
3
5
39
3.3P
0603
50V
2
2
2
4 R512 1
C776 C777 C778
R43
75
1%
2
U525
VCC
2
2
2
R41
75
1%
5
1
1
1
1
1
5
6
7
8
Q507
2N7002
2
+3V
2
CRT_DDCK
2 L506
2 L507
2 L508
D
S
5
1
1
1
2
CRT_DDDA
G
S
5
R42
75/NA
1%
GND
GND_CRT15
GND_CRT15
GND_CRT15
A
GND
5
GND
U524
VCC
1
4 R513 1
CRT_VSYNC
2
39
Place near to the
CRT connector.
2
0603
GND
3
5
R,G,B
NB to Bead : 37.5 ohm impedance
Bead to connector : 75 ohm
impedance
AHCT1G08DBV
SOT25
GND_CRT15
Title
Size
C
GND
Date:
5
4
3
2
LCD & CRT connector
Document
Number
Rev
01
411682810001
1
14
of
29
5
4
3
2
1
RJ45
VT6105L
IDSEL: AD18
PCI REQ1#
PCI GNT1#
PCI INTE#
+LAN_D2.5V
+2.5V_DDR
+LAN_A2.5V
L534
AD[0..31]
9,16,17 AD[0..31]
L536
1
CBE#[0..3]
CBE#[0..3] 9,16,17
2
1
120Z/100M
2012
2
120Z/100M
2012
2
R645
10K
0603
2
1
3
2 R640
0
1
0603
Q519
DTC144WK
0.1U
16V
0603
ICH_RI#
9
LAN_WAKE
VCC
NC1
NC0
GND
8
7
6
5
2
16
15
14
NC
NC
NC
NC
PJRX+
PJRX-
PJTX-
12
13
PJ4
PJ7
1
2
1
1
1
C617
22P
0603
5%
TP2
TP3
35
24
14
2
GND
GND
LAN_GPIO
84
98
GNDA1
GNDA5
GNDRX
GNDRAM
GNDAREXT
GNDTX
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
73
74
75
76
77
78
79
80
83
59
60
61
62
63
101
100
R651
6.04K
0603
1%
C
LAN_GND
JS3
VT6105-L
PQFP128A_0.4MM
1
2
GND
SHORT-SMT4
JS505
1
2
SHORT-SMT4
JS506
2
SHORT-SMT4
C658
0.1U
0603
16V
GND
LAN_GND
PJRX+
19
PJRX-
19
PJTX+
19
PJTX-
19
19
19
STRAPPING
+3V
1
PJ4
PJ7
B
LAN_GPIO
1
0603
2 R682
10K
LAN_TEST
1
0603
2 R700
10K
TEST MODE(0=Internal PHY test mode, 1=Normal mode)
LAN_NWAY
1
0603
2 R678
10K
N-WAY enable(0=disable, 1=enable)
LANTEST0
1
0603
2 R710
10K
LANTEST1
1
0603
2 R701
10K
R643
75
0603
1%
Mount when use WOL function.
+LAN_D3V
2
2
2
C190
1000P
1806
2KV
10%
GND
C612
0.1U
0603
50V
R633
75
0603
1%
2
R153
75
0603
1%
1
2
C604
0.1U
0603
50V
2
120
1608
1
1
R146
75
0603
1%
1
L535
1
1
PH163112
2
2
R647
49.9
0603
1%
1
1
GND
2
11
10
9
1
2
3
1
1
2
R648
49.9
0603
1%
+LAN_A2.5V
2 R707
2.2
1
1
4
1
4
3
PLP3216S
TXD-
LANX2
85
86
LAN_GND
6
7
8
4
5
95
2
C619
22P
0603
5%
1
1
0603
2
2
3
2
L533
LANX1
LAN_GND
+LAN_D2.5V
U509
TXD+
94
25MHZ
SHORT-SMT4
JS504
2
GND
PLP3216S
X504
1
+LAN_A2.5V
C663
1U
0603
R637
0
0603
RXIN-
TXD+
1M/NA
1
1
CS
SK
DI
DO
M93C46
SO8
L531
TXD-
108
LANX2
2
0603
+LAN_D3V
+3V_P
1
2
3
4
+LAN_A2.5V
RXIN+
109
LANX1
R652 1
2
R650
49.9
0603
1%
2
R649
49.9
0603
1%
93
92
102
42
99
107
49
111
3
16
28
40
56
67
81
82
1
EECS
EESK
EEDI
EEDO
1
GND
RXIN+
LAN_NWAY
U515
2
C615
0.1U
0603
50V
1
2
+LAN_D2.5V
R711
100K/NA
0603
1
+LAN_A2.5V
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
+3V_P
GND
20
31
41
9
125
116
110
68
55
48
1
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
120
91
103
43
97
106
96
DTC144WK
VCC
VCCA
VCCRX
VCCRAM
VCCREXT
VCCTX
VCCXTAL
3
WOL
PME#
53
52
51
64
65
66
69
70
71
72
LANTEST0
LANTEST1
B
GPIO
REXT
ECS
EDO
EDI
ECK
112
119
Q520
LAN_WAKE 2
C
TESTM0
TESTM1
PCIRST#
50
54
57
58
9,10,16,17 PCI_PME#
X1
RXIN-
104
1
1
CARD_RI#
EECS
EEDO
EEDI
EESK
X0
VCC25_0
VCC25_1
VCC33_0
VCC33_1
VCC33_2
VCC33_3
VCC33_4
VCC33_5
GND
VCC33_7
17
114
9 LAN_PCIRST#
2
C598
TXP
IRTY#
GNT#
REQ#
TRDY#
STOP#
105
2
+3V_P
1
+3V_P
TXM
PCICLK
INTA#
17
117
118
18
21
PCI_IRDY#
PCI_GNT1#
PCI_REQ1#
PCI_TRDY#
PCI_STOP#
CBE0#
CBE1#
CBE2#
CBE3#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
115
113
4 PCICLK_LAN
9 INT_PIRQE#
9,16,17
9
9
9,16,17
9,16,17
RXP
LAN_TEST
1
9,16,17 PCI_PAR
RXM
90
89
88
87
2
2 R662
0
1
0603
LED0
LED1
LED2
LED3
FRAME#
DEVSEL#
PERR#
IDSEL
PAR
1
AD18
15
19
22
4
23
R670
10K/NA
0603
2
2 R676
0/NA
1
0603
9,16,17 PCI_PERR#
9,16,17 PCI_FRAME#
9,16,17 PCI_DEVSEL#
D
R663
10K/NA
0603
U511
2
R677
4.7K
0603
47
46
45
44
39
38
37
36
34
33
32
30
29
27
26
25
13
12
11
10
8
7
6
5
1
128
127
126
124
123
122
121
1
+3V
2
2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
D
CBE#0
CBE#1
CBE#2
CBE#3
+LAN_D3V
GND_45
Mount to enable Cable Detect.
GND
Place as close to VT6105LOM as possible.
+3V_P
+LAN_D3V
R694
1
1
C626
0.1U
0603
50V
2
C660
0.1U
0603
50V
2
1
1
C656
0.1U
0603
50V
2
2
C642
0.1U
0603
50V
2
1
C618
0.1U
0603
50V
2
SHORT-SMT4
JS502
1
2
A
2
JS503
1
2
120Z/100M
2012
1
1
C639
0.1U
0603
50V
A
GND
C621
0.1U
0603
50V
1
C657
0.1U
0603
50V
2
1
1
C608
2.2U
1206
16V
2
C616
2.2U
1206
16V
2
C613
0.1U
0603
50V
1
1
1
C659
0.1U
0603
50V
2
GND_45
+LAN_A2.5V
2
GND
2
1
+LAN_D2.5V
2
SHORT-SMT4
C614
0.1U
0603
50V
Title
GND
Ethernet controller
LAN_GND
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
15
of
29
5
4
3
2
1
+5V
JS501
SHORT-SMT3
+3V
1
9,15,17 CBE#[0..3]
J504
2
4 PCICLK_MINIPCI
9
PCI_REQ2#
AD31
AD29
AD27
AD25
CBE#3
AD23
AD21
AD19
AD17
CBE#2
9,15,17 PCI_IRDY#
9,10,17 PCLKRUN#
9,17 PCI_SERR#
9,15,17 PCI_PERR#
CBE#1
AD14
AD12
AD10
C
AD8
AD7
AD5
AD3
AD1
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
D
MINI_LPC_AD1
R518 0
1
0603
2
INT_PIRQD# 9
MINI_LPC_AD2
MINIPCI_PCIRST#
9
PCI_GNT2# 9
PCI_PME# 9,10,15,17
MINI_LPC_AD3
AD30
AD28
AD26
AD24
R52
1
100 0603 1%
2
AD17
AD22
AD20
PCI_PAR
AD18
AD16
9,15,17
PCI_FRAME# 9,15,17
PCI_TRDY# 9,15,17
PCI_STOP# 9,15,17
PCI_DEVSEL# 9,15,17
AD15
AD13
AD11
C
AD9
CBE#0
+3V
AD6
AD4
AD2
AD0
R579 1
INTEL_PD#
1
2
R583 33
WIRELESS_PD# 10
VDD3
+3V
MINI_PCI_SERIRQ
R145
330
0603
R799
4.7K
0603
MINIPCI_ACT# 10
WIRELESS_LED# 20
GND1
GND2
D
124P/0.8MM/H9.2
QTC
C102A-092B31-01
+3V
10K
0603
2
1
2
RING
TX+
TXPJ4
PJ5
LED2_YELP
LED2_YELN
RESERVED4
5V[1]
INTA#
RESERVED5
3.3VAUX[0]
RST#
3.3V[4]
GNT#
GROUND9
PME#
RESERVED6
AD[30]
3.3V[5]
AD[28]
AD[26]
AD[24]
IDSEL
GROUND10
AD[22]
AD[20]
PAR
AD[18]
AD[16]
GROUND11
FRAME#
TRDY#
STOP#
3.3V[6]
DEVSEL#
GROUND12
AD[15]
AD[13]
AD[11]
GROUND13
AD[9]
C/BE[0]#
3.3V[7]
AD[6]
AD[4]
AD[2]
AD[0]
RESERVED_WIP4[0]
RESERVED_WIP4[1]
GROUND14
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED7
GROUND15
SYS_AUDIO_IN
SYS_AUDIO_IN_GND
AUDIO_GND2
MPCIACT#
3.3VAUX[1]
2
1
R516
0
1
R517
0
0603
INT_PIRQF#
TIP
RX+
RXPJ7
PJ8
LED1_GRNP
LED1_GRNN
CHSGND
INTB#
3.3V[0]
RESERVED0
GROUND0
CLK
GROUND1
REQ#
3.3V[1]
AD[31]
AD[29]
GROUND2
AD[27]
AD[25]
RESERVED1
C/BE[3]#
AD[23]
GROUND3
AD[21]
AD[19]
GROUND4
AD[17]
C/BE[2]#
IRDY#
3.3V[2]
CLKRUN#
SERR#
GROUND5
PERR#
C/BE[1]#
AD[14]
GROUND6
AD[12]
AD[10]
GROUND7
AD[8]
AD[7]
3.3V[3]
AD[5]
RESERVED2
AD[3]
5V[0]
AD[1]
GROUND8
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND0
SYS_AUDIO_OUT
SYS_AUDIO_OUT_GND
AUDIO_GND1
RESERVED3
VCC5VA
1
INTEL_PD#
9
1
3
5
7
9
11
13
15
17
19
MINI_LPC_LDRQ#
21
23
25
27
29
31
33
35
37
39
41
MINI_LPC_FRAME# 43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
MINI_LPC_AD0
93
95
97
99
101
103
105
107
109
111
113
115
117
119
48M
121
123
2
D
AD[0..31]
9,15,17 AD[0..31]
Mini PCI
IDSEL: AD17
PCI REQ2#
PCI GNT2#
PCI INTD# INTF#
+3V
2
CBE#[0..3]
D Q22
S
2N7002
4 SUPERIO_48M
9,18,20 LFRAME#
9 LDRQ0#
9,10,17,18 SERIRQ
9,18,20 LAD0
9,18,20 LAD1
9,18,20 LAD2
A
9,18,20 LAD3
SUPERIO_48M R390 1
1
C519
0.1U
0603
50V
2
1
C525
0.1U
0603
50V
2
1
C510
0.1U
0603
50V
2
1
C538
0.1U
0603
50V
2
1
C520
0.1U
0603
50V
2
1
C66
0.1U
0603
50V
2
1
C539
2.2U
1206
16V
2
B
2
1
S
G
C509
0.1U
0603
50V
GND
GND
0/NA 2 0402
5%
48M
LFRAME#
R391 1
0
2 0402
5%
MINI_LPC_FRAME#
LDRQ0#
R392 1
0
2 0402
5%
MINI_LPC_LDRQ#
PCI_SERIRQ R393 1
0
2 0402
5%
MINI_PCI_SERIRQ
LAD0
R394 1
0
2 0402
5%
MINI_LPC_AD0
LAD1
R395 1
0
2 0402
5%
MINI_LPC_AD1
LAD2
R396 1
0
2 0402
5%
MINI_LPC_AD2
LAD3
R397 1
0
2 0402
5%
MINI_LPC_AD3
GND
B
A
Title
Size
C
Date:
5
4
3
2
Mini PCI
Document
Number
Rev
01
411682810001
1
16
of
29
5
SIGNAL
4
PC CARD PULL UP
CCD#1
CCD#2
CBLOCK#
CSTOP#
+3V
+3V
CARD_VCC
CARD_VCC
3
SIGNAL
PC CARD PULL UP
SIGNAL
PC CARD PULL UP
CRST#
CSERR#
CDEVSEL#
CTRDY#
CVS1
CVS2
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
+3V
+3V
CPERR#
CINT#
CIRDY#
CREQ#
CSTSCHG#
CAUDIO
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
2
1
CARDBUS CONTROLLER
PCI1410 HAVE INTEGRATED ALL PULL UP RES ABOVE
D
D
CB_PCIRST# R813 0
2 0402
1
2
5%
R812
0
0805
VCC5_EN#
VCC3_EN#
VPPD0
VPPD1
2
R811
0/NA
0805
FOR 1410
PCI1410A
IDSEL : AD19
PCI REQ0#
PCI GNT0#
PCI INTB#
+3V
1
1
+3V_P
+3V
0/NA
R814 1
2 0402
5%
CARD_VCC
1
B
2
R818
10K
0402
5%
5%
CB_PCIRST#
13
21
32
28
29
31
33
36
34
35
1
2
20
CARDSPK#
59
70
62
9,10,15,16 PCI_PME#
12
CARDSPK#
PCLKRUN#
9,10,16 PCLKRUN#
69
68
67
65
64
61
60
15
CARD_RI#
9,10,16,18 SERIRQ
0
INT_PIRQB#
R821 1
2 0402
5%
MF6
MF5
MF4
MF3
MF2
MF1
MF0
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
1
2
1
108
111
110
109
107
105
101
104
133
123
106
132
103
136
119
143
84
100
131
117
75
137
134
135
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
R819 0
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CSTSCHG
125
112
99
88
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
C783
0.1U
0603
50V
2
GND
J6
GND
CAD0
CAD1
CAD3
CAD5
CAD7
CC/BE0#
CAD9
CAD11
CAD12
CAD14
CC/BE1#
CPAR
CPERR#
CGNT#
CINT#
CAD12
CAD9
GND
GND
CCLK
CIRDY#
CC/BE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
R2_D2
CCLKRUN#
1
C786
0.1U
0603
50V
2
1
VPPOUT
C785
10P/NA
0603
2
C784
10P/NA
0603
1
2 0402
1
2 0402
0
2
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
R815
1 0
CAD11
CAD10
R816
1
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
2
73
74
71
72
63
AUX_VCC
14
66
86
102
122
138
CORE_VCC0
CORE_VCC1
CORE_VCC2
CORE_VCC3
CORE_VCC4
CORE_VCC5
RI_OUT#/PME#
SUSPEND#
SPKR_OUT#
6
22
42
58
78
94
114
130
9
IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
REQ#
GNT#
RST#
144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76
GND
C787
0.1U
0603
50V
GND
For 16 bit card
CARD_VCC
2 0402CCLKRUN#
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND1
GND2
GND3
GND4
GND5
GND6
R820
10K
0402
5%
C788
10P/NA
0603
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND7
GND8
GND9
GND10
GND11
GND12
CCD1#
CAD2
CAD4
CAD6
R2_D14
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
R2_A18
CBLOCK#
CSTOP#
CDEVSEL#
C
VPPOUT
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CC/BE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
B
FM/34X2P/H5.5
FCI 62596-00A
1
2 0402
1
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CSTSCHG
90
126
2
0
4 PCICLK_CARD
9,15,16 PCI_DEVSEL#
9,15,16 PCI_FRAME#
9,15,16 PCI_IRDY#
9,15,16 PCI_TRDY#
9,15,16 PCI_STOP#
9,15,16 PCI_PAR
9,15,16 PCI_PERR#
9,16
PCI_SERR#
9
PCI_REQ0#
9
PCI_GNT0#
9
CB_PCIRST#
+3V
C/BE3#
C/BE2#
C/BE1#
C/BE0#
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
1
AD19 R59
12
27
37
48
SKT_VCC0
SKT_VCC1
C782
0.1U
0603
50V
CRST#
2
9,15,16 AD[0..31]
9,15,16 CBE#3
9,15,16 CBE#2
9,15,16 CBE#1
9,15,16 CBE#0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCCD0#/VCC5#/SDAT
VCCD1#/VCC3#/SCLK
VPPD0/VPP_PGM/SLAT
VPPD1/VPP_VCC
C
3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI_VCC0
PCI_VCC1
PCI_VCC2
PCI_VCC3
18
30
44
50
CARD_VCC
U510
GND
GND
GND
PCI1410
PQFP144_0.5MM
GND
GND
GND
GND
8
7
6
5
RP511
10K*4/NA
1206
ONLY FOR OZ6812
GND
1
2
2
1
C793
0.1U
0603
50V
C794
0.1U
0603
50V
A
C792
0.1U
0603
50V
1
1
2
3
4
C791
0.1U
0603
50V
C795
0.1U
0603
50V
2
PCLKRUN#
CARDSPK#
PCI_PME#
2
2
1
GND
CCLKRUN#
C675
1U
0603
C790
0.1U
0603
50V
1
VPPOUT
C649
2.2U
1206
16V
2
SSOP16
2
TPS2211
C789
0.1U
0603
50V
2
R822
10K
0402
5%
1
CARD_VCC
1
C629
0.1U
0603
50V
+3V
2
CARD_VCC
1
+3V
VPPD0
VPPD1
2
16
15
14
13
12
11
10
9
1
SHDN
VDDP0
VDDP1
AVCCA
AVCCB
AVCCC
AVPP
12V
1
C628
0.1U
0603
50V
2
1
2
R684
10K
0402
5%
VCCD0
VCCD1
3.3VA
3.3VB
5VA
5VB
GND
OC
1
A
1
2
3
4
5
6
7
8
2
VCC5_EN#
VCC3_EN#
2
+5V
U513
+3V
1
+5V
1
+3V
C796
0.1U
0603
50V
Title
GND
CardBus (PCI1410A)
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
17
of
29
5
4
3
2
1
+5V
J4
+3V
2
2
1 JO31
SW_VDD5
2 4.7K
1 JO39
R1
BATT_DEAD
2
BATT_DEAD 24
1 JO45
1 JO47
BAT_TEMP
BAT_VOLT
Q525
DTC144TKA
R560
R559
2
C531
0.1U
0603
50V
GND
GND
BAT_T
BAT_V
0603
0603
BAT_T
BAT_V
23
23
VDD3
1
GND_H8
1
DTC144TKA
GND
+5V_P
1
Q512
NDS356P
D
J505
FAN#
2
R572
33
0603
FAN#
GND
20
1
R536
10K
0603
2
KBC_X-
VDD3
1
2
3
4
5
10
9
8
7
6
R855 1
2 4.7K
0603
R857 1
2 4.7K
0603
THRM_CLK
R859 1
2 4.7K
0603
THRM_DATA R860 1
2 4.7K
0603
2
1
2
10K
0603
C247
0.1U
0603
50V
+3V
1
+3V_KBC
R846
10K
0603
+3V
R76
1
C248
0.1U
0603
50V
R848
2
H8_THRM#
1
10K
0603
2
R82
4.7K
0603
+KBC_VDDA
R851
2
1
0
0805
2
R90
H8_SMI#
0
0603
1
2
C799
0.1U
0603
50V
GND
0
EXTSMI#
B
+KBC_VDD
GND_H8
R508
10K/NA
0603
SVDD3
C800
0.1U
0603
50V
C801
10U
1206
10V
L547
1
GND_H8
R853
10K
0603
2
JP_BEAD_DFS GND
0603D_DFS
POWERBTN#
1
FAN_SPEED 20
PWRSW#
2
R856
1K
0603
KBC_XR509
10K
0603
+5V_P
PWRSW# 22
GND
KBC_X+
R48
1
2
0603
GND
X2
1
D603
K
9
0603
1M
A
SB_THRM# 9
0
0603
+KBC_VDD
R850
1
VDD3
BAT_DATA
C
VDD3
1206
BAT_CLK
ICH_PWRBTN# 9
GND
30
73
24
VDD3
KI4
KI5
KI6
KI7
2
0
0603
GND
+KBC_VDD
Q510
DTC144WK
2
H8_PWRON_SB# 1
2
71
+5V_P
FAN_SPEED
R844 1
+KBC_VDDA
72
RP512
KI1
KI0
KI2
KI3
R843
+VCC_CORE
+VCC_CORE_KBC
SVDD3
VSS
AVSS
CNVSS
2
R537
10K
0603
R550
1 0/NA
2
0603D_DFS
29
GND_H8
47K*8
3
RLZ5.6B
GND
KBC_X+
VDD5
+5V
1
K
VCC
28
R840
10K
0603
WAKE_UP# 9,10
H8_RESET#
25
+5V_P
D507
A
VREF
H8_PWRON_RSM5V 22
SUSC#
9,27,28
5,20
24
2
G
XOUT
GP30/PWM0/FCTRL0
GP31/PWM10/FCTRL1
GP32/FCTRL2
GP33/FCTRL3#
GP34/BANK0
GP35/BANK1
GP36/CE#
GP37/OE#
BLADJ
I_CTRL
1
GND
2
2
S
2
R573
470K
0603
C542
0.1U
0603
50V
XIN
VDD3
POWERBTN#
R34 1
0603
2 0
PWRON_1.35V_1.5V 25
R38 1
2
BAT_VOLT
0/NA 0603
BAT_TEMP
I_LIMIT
I_LIMIT
23
+3V_KBC
+VCC_CORE_KBC
1
80
79
78
77
76
75
74
W83L950D
PQFP80_0.5MM
1
1
1
R587
10K/NA
0603
RESET#
BLADJ
I_CTRL
11
10
RSMRST# 9
0603
2
62
61
60
59
58
57
56
55
GP60/AN0/INT5
GP61/AN1/INT6
GP62/AN2/INT7
GP63/AN3/INT8
GP64/AN4/INT9
GP65/AN5/INT10
GP66/AN6/INT11
GP67/AN7/INT12
GP0/P3REF/FA0
GP1/FA1
GP2/FA2
GP3/FA3
GP4/FA4
GP5/FA5
GP6/FA6
GP7/FA7
GP10/FA8
GP11/FA9
GP12/FA10
GP13/FA11
GP14/FA12
GP15/FA13
GP16/FA14
GP17/FA15
20
2
+5V
KI0
KI1
KI2
KI3
KI4
KI5
KI6
KI7
GP56/DA1/PWM01
GP57/DA2/PWM11
GP54/CNTR0
GP55/CNTR1
T_CLK
1
2 SUSC#
0
0603
H8_WAKE_UP# R839 1
0 0603 WAKE_UP#
2
R198 1
2 0/NA
0603
BATT_G#
BATT_G# 20
BATT_R#
BATT_R# 20
KBC_PWRON_LED#
KBC_PWRON_LED# 20
CAP#
CAP#
20
NUM#
NUM# 20
SCROLL#
SCROLL# 20
38
37
36
35
34
33
32
31
2
0
1
Q9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
20
2
R1
13
12
GP40/XOUT/PWM2
GP41/XCIN/PWM3
T_DATA
2
3
H8_SUSB
0603
0603
KO0
KO1
KO2
KO3
KO4
KO5
KO6
KO7
KO8
KO9
KO10
KO11
KO12
KO13
KO14
KO15
GP76/SDA
GP77/SCL
R837
H8_RSMRST# 1
A20GATE 9
1
2
R73
4.7K
0603
SUSB# 2
27
26
0
2
1 0/NA
1
R505 1
R199
2
H8_SMI#
SW_VDD5
GP20/FD0/LPCEN
GP21/FD1
GP22/FD2/SDA1/RXD1
GP23/FD3/SCL1/TXD1
GP24/FD4
GP25/FD5
GP26/FD6
GP27/FD7
T_DATA
H8_RSMRST#
H8_PWRON_SB#
T_CLK
H8_PWRON_RSM5V
H8_SUSC#
R838
2
PWROK
SVDD3
3
2
H8_RCIN#
A20GATE
9
8
7
6
5
4
20,22
1
22 SW_VDD5
BAT_DATA
BAT_CLK
GP50/A0
GP52/INT30#/R
GP53/INT40#/W
GP42/INT0/OBF00
GP43/INT1/OBF01
GP46/SCLK1/OBF1
21
20
LID#
2
0603
0603
GP70/SIN2
P71/SOUT2
GP72/SCLK2
GP73/SRDY2#/INT21
GP74/INT31
GP75/INT41
LID#
H8_THRM#
1
BAT_D
BAT_C
2 33
2 33
1
1
GP44/RXD
GP45/TXD
16
18
1
23
23
R841
R842
17
15
14
23
22
19
GP51/INT20#/S0
GP47/SRDY1#/S1
2
RLS4148
CHARGING
BATT_DEAD#
H8_ADEN#
LEARNING
H8_SUSB
SCI#
GP80/SD0
GP81/SD1
GP82/SD2
GP83/SD3
GP84/SD4
GP85/SD5
GP86/SD6
GP87/SD7
1
23 LEARNING
12 H8_SUSB
9 SCI#
70
69
68
67
66
65
64
63
2
A
LPCCLK_KBC
SERIRQ
LAD3
LAD2
LAD1
LAD0
LPCKBC_RST#
LFRAME#
1
24 CHARGING
K
ADEN#
LPCCLK_KBC
SERIRQ
LAD3
LAD2
LAD1
LAD0
LPCKBC_RST#
LFRAME#
1
2
1
4
9,10,16,17
9,16,20
9,16,20
9,16,20
9,16,20
9
9,16,20
D7
SUSB#
R835
4.7K
0603
U7
GND
MA/3P/ST
HIROSE
DF13B-3P-1.25V
2 2.2K
2 2.2K
1
1
C536
0.1U
0603
50V
+3V
KBD_US/JP# 9
1
2
3
2
D
D506
BAV70LT1
1 JO43
C
9
SVDD3
1 JO41
22,23
HRCIN#
0603
0603
BATT_DEAD#
8.2K
0603
B
2
0
2 4.7K/NA 0603
1
R831
10K
0603
1 JO37
R72
FAN
R824 1
H8_ADEN#
R66
3
1 JO35
R71
0/NA
0603D_DFS
R65
1
SVDD3
VDD3
1 JO33
JO48
4,9,20,22,25,26,27,29
R64
10K
0603
H8_RCIN#
2
GND
0603
VDD5
1
FPC/FFC/1MM/26P
ACES
85202-26-00
291000152603
0603
2 4.7K
2
1
0603
2 4.7K
1
2
2
2 10K
1
R62
1
2
R828 1
R60
T_DATA
2
2
LID#
T_CLK
1
2
0603
1
2
2 4.7K
1 JO29
1
2
R827 1
2
2
1 JO27
SCI#
3
2
1 JO25
1
2
2
D
1 JO24
2
1 JO26
2
1 JO28
2
1 JO30
2
1 JO32
2
1 JO34
2
1 JO36
2
1 JO38
2
1 JO40
2
1 JO42
2
1 JO44
2
1 JO46
2
2
1
VDD3
KO0
KO1
KO2
KO3
KO4
KO5
KO6
KO7
KO8
KO9
KO10
KO11
KO12
KO13
KO14
KO15
KI0
KI1
KI2
KI3
KI4
KI5
KI6
KI7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
G
GND
S
PWROK
PWROK
5,9
U503
MAX809
SOT23N
SVDD3
3
+5V_P
1
RESET#
S
THRM_DATA
GND
GND
A
H8_RESET#
2
R861
100K
0603
809M
2
D
D
S
2
BAT_DATA
1
G
R69
100K/NA
0603
809S
VCC
C49
22P
0603D
1
2
C46
22P
0603D
THRM_CLK 20
GND
RESET#
GND
VCC
1
3
1
THRM_CLK
Q527
2N7002
2
U8
MAX809/NA
SOT23N
2
D
D
S
BAT_CLK
+3V
A
8MHZ
TXC8X4.5
1
RLS4148/NA
THRM_DATA 20
Title
GND
Q528
2N7002
GND
GND
Embedded Controller
GND
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
18
of
29
5
4
3
2
1
MDC
+5V
J515
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
MONO_OUT
+3V
+3V_P
C
2 0/NA
0603
J511
MODEM_SPK 12
15
R730 1
2 4.7K
0603
R716 1
2 22
0603
R713 1
2 0
0603
15
+3V
ACSYNC 10,12
ACSDIN1 10
15
15
15
15
ACBITCLK 10,12
PJRXPJRX+
PJTXPJTX+
R628
R624
R641
R634
0
0
0
0
1
1
1
1
2
2
2
2
8
7
6
5
4
3
2
1
PJ7
PJ7
PJ4
PJ4
0603
0603
0603
0603
MODEMP
MODEMN
A2
A1
GND
GND1
GND2
GND_RJ11
GND_45
2
2
GND
GND
A2 RJ11
A1
1
JO516JO518 JO519 JO520
2
GND
1
1
C661
10P/NA
0603
D
2
2
C681
1U
0603
RJ45
RJ11-2P/RJ45-8P
C10037-102XX
2
FM/0.8MM/H5
1
MTG1
MTG2
C682
1U
0603
2
2
C679
1U
0603
8
7
6
5
4
3
2
1
GND1
GND2
1
1
10,12 ACSDOUT
10,12 ACRST#
D
R752 1
1
D
M
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
12
GND_45
GND
GND
GND_45 GND_45
GND_45
C
C
R118 1
L24
2
1
2
GND
1
2
1
L23
2
130Z/100M
0603
GND
GND_45
GND_RJ11
2
2
3
HDR/MA-2
ACES
85204-0200
F503
L530
2
1
2
100Z/100M/NA
1608
1
2
140mA
POLYSW_MINISMDC110
295000010028
2
120Z/100M
2012
R646 1
MODEMP
MODEMN
S1
Protector
1808A
L529
50UH
CHOKE_WLT04020201
B
GND
C158
1000P
1812
2KV
10%
1
5
1
RJ11
J508
1
130Z/100M
0603
100Z/100M/NA
1608
2
120Z/100M
2012
1
1
2
L528
C157
1000P
1812
2KV
10%
B
GND
Using 1808 x 2
A
A
Title
Size
C
Date:
5
4
3
2
MDC&RJ45&RJ11
Document
Number
Rev
01
411682810001
1
19
of
29
5
4
3
TOUCH_PAD
2
+5V
74AHC14_V
TSSOP14
1
47PX4
1206
7
7
1
14
7
2
2
2
1
1
1
2
GND
GND
GND
GND
+3V_P
HDR/MA-12
ACES
87151-1207
291000141204
GND
2
4
5
PWRON_LED#
R1
Q6
DTC144TKA
2
SUSB#
4,9,18,22,25,26,27,29
D
S
Q3
2N7002
G
+3V_P
U2D
74AHC14_V
TSSOP14
9
8
+3V_P
U2E
74AHC14_V
TSSOP14
11
10
U2F
74AHC14_V R12
TSSOP14
13
1
12
2
S
SW_RIGHT
D
C585
0.1U
0603
50V
1
2
3
4
1
3
JO67
74AHC14_V
TSSOP14
5
14
2
CP504
SW7
U2C
6
14
8
7
6
5
TC010-PSS11CET
297004010001
2
0603
2
0603
C283
0.1U/NA
0603
16V
10%
74AHC14_V
TSSOP14
3
4
14
1
R592 0
1
R591 0
C282
0.1U/NA
0603
16V
10%
D
2
4
5
SW_LEFT
C281
0.1U/NA
0603
16V
10%
3
SW6
1
3
1
2
3
4
5
6
7
8
9
10
11
12
2
T_DATA
C280
0.1U/NA
0603
16V
10%
+3V_P
U2B
1
2
18
1
2
L527 120Z/100M
1608
1
2
L526 120Z/100M
1608
C279
0.1U/NA
0603
16V
10%
2
Add for EMI request. Only for Lynx-Banias.
GND
J5
T_CLK
2
2
L525
120Z/100M
2012
1
1
1
1
C84
0.1U/NA
0603
16V
10%
D
+3V_P
U2A
14
+5V
miniSMDC050
14
2
+3V_P
F502
0.5A/POLYSW
18
1
7
1
7
GND
1M
0603
GND
GND
1
JO63
7
GND
KBC_PWRON_LED#
18 KBC_PWRON_LED#
2
1
TC010-PSS11CET
297004010001
GND
GND
2
GND
C14
4.7U
0805
+80-20%
1
R14
1
2
C
C
180K
0603
LCD_PCIRST# 9,14
+3V
ENBL
1
2
+3V
1
2
R39
BAW56/NA
0/NA
+VMAIN_INV
ENBL
5
LID#
18,22
0603
2
GND
4
3
2
1
32
31
30
GND
1
16 WIRELESS_LED#
C804
0.1U
0603
50V
2
GND
1
2
3
4
5
6
7
8
9
10
11
2 120Z/NA 0805C
2 120Z/100M
2 120Z/100M
1
L8 1
L7 1
4
3
2
1
5
6
7
8
120OHM/100MHZ
GND
GND
2 120Z
1
0805C
C12
0.1U
0603
50V
R866
2
4.7K
0603
GND
B
GND
+VCCP
INIT#
+VCCP
LFRAME# 9,16,18
DQ1/LAD1
DQ2/LAD2
GND
DQ3/LAD3
DQ4/RSV
DQ5/RSV
DQ6/RSV
2
1
3,9 HINIT#
F3
FUSE-2.5
1206
INIT#
3
R193
Q529
SST49LF004A
14
15
16
17
18
19
20
LAD0
LAD1
LAD2
LAD3
R875
300
0603
DTC144TKA
R1
LAD[0..3]
R874
470
0603
2
GND
9,16,18 LAD[0..3]
DVMAIN
+3V
1
0603
0603
0603
0603
1
1
2
R876
1
2
4,9,18,22,25,26,27,29
470K
0603
SUSB#
0/NA
0603
SYS BIOS Vendor List:
1
2
3
2
2
2
2
29
28
27
26
25
24
23
22
21
G
8.2K
8.2K
8.2K
8.2K
MODE
GNDA
VCCA
GND
VDD
OE#/INIT#
WE#/LFRAME#
NC
DQ7/RSV
1
4.7K
0603
1
1
1
1
A7/RSV
A6/RSV
A5/RSV
A4/RSV
A3/RSV
A2/RSV
A1/RSV
A0/RSV
LAD0/DQ0
2
R870
R871
R872
R873
5
6
7
8
9
10
11
12
13
2
4.7K
0603
2 0603
2 0603
2
1
1
S
R865 1 8.2K
R867 1 8.2K
R869
2
R195
GND
S
D 1
2
K
CD_LED#
18
+5V_P
2 10K
0603
FAN_SPEED
FAN_SPEED
R879 1
2 10K
0603
TEMP_ALERT#
15
5
8
6
7
4
9
PWM1
PWM2/SMBALERT
PWM3/ADDRESS ENABLE
TACH1
TACH2
TACH3
TACH4/ADDRESS SELECT/THERM
ADT7460
QSOP16B
D1+
D1D2+
D2GND
11
HDD_LED#
18
NUM#
18
CAP#
K
C806
0.1U
0603
50V
A
1
+VMAIN_INV
A
1
A
1
2
A
CL-190G
D17
C805
0.1U
0603
50V
NUM#
K
CAP#
K
2
+3V
R257 330
CL-190G
D18
GND
GND
2
R258 330
CPU_THERMDA
CL-190G
D19
GND
CPU_THERMDC
C807
2200P
0402
+/-20%
50V
18
SCROLL#
SCROLL#
K
Title
A
1
Inverter & BIOS & TouchPad & LED
2
R259 330
Size
C
CL-190G
Date:
5
1
2
GND
R256 330
1
CPU_THERMDA 3
CPU_THERMDC 3
2
Slave Address 0101110
3,10 TEMP_ALERT#
CPU_THERMDA
CPU_THERMDC
+5V
D16
+5V_P
3
13
12
11
10
2
CL-190G
0603
2
FAN#
FAN#
2 10K
1
18
R878 1
1
2
VCC
A
R877
14
1
+2.5VIN/SMBALERT
SDA
SCL
2
16
1
1
R255 330
+2.5V_DDR
U523
THRM_DATA
THRM_CLK
18 THRM_DATA
18 THRM_CLK
A
C249
0.1U
0603
50V
5
6
7
8
2N7002
D15
11
G
GND
100K
0603
D
Q23
U3
SI4835DY
SO8
4
D
S
SST49LF004A : 283467490001
+5V_P
J3
MA/11P/ST
291000011101
1
L6
VDD3
2
GND
R0A
R868
B
C803
0.1U
0603
50V
L5
C13
0.1U
0603
50V
U512
A8/RSV
A9/RSV
RESET#
VPP
VDD
R-C#/CLK
A10/GPI4
+3V
C802
4.7U
1206
16V
2
2 0603
1
R864 1 8.2K
2
2 0603
2 0603
1
1 8.2K
1 8.2K
1
BATT_R#
FA1
BATT_G#
PWRON_LED#
WIRELESS_LED#
18 BATT_R#
18 BATT_G#
R862
R863
1
+5V ENABLE_BKLT
BLADJ
5,18 BLADJ
4 PCICLK_BIOS
9 LPCBIOS_RST#
L37
120Z
2
Inverter
Q4
3
C15
0.1U
50V
0603
0603
0805C
1
2
0
2
ENABLE_BKLT
1
R200
3
1
R1
FWH
DTC144TKA
1
Q2
2
R15
10K/NA
0603
2
+5V
1
GND
4
3
2
Document
Number
Rev
01
411682810001
1
20
of
29
5
4
3
2
1
USB0_P
1
2
3
4
4
1
90Z/100M
CHOKE_ACM2012
+VCC_USB_3
A1
A2
A3
A4
C271
USB0_P
USB0_N
USB1_P
USB1_N
GND1
GND2
1
2
3
4
8
7
6
5
USB_P4_P
USB_P4_N
USB_P1_P
USB_P1_N
RP505
0*4/NA
RPSOA_8C_DFS
USB/4PX2/DIP
MOLEX
67298-2000
2
2
2
2
2
JO529 JO71 JO70
D
VCC
USB0USB0+ GND1
GND
GND2
USBP0+
USBP0USBP1+
USBP1-
10
10
10
10
USBP2+
USBP2USBP3+
USBP3-
10
10
10
10
CP505
22P*4/NA
1206
JO530 JO73 JO72
GND_USB
1
1
1
1
1
1
5
6
7
8
2
2
C137
47P/NA
0603
47P/NA
0603
2
1
1
USB0_N
VCC
USB0USB0+
GND
4
3
2
1
3
2
J507
+VCC_USB_1
L44
D
GND
GND_USB
USB2_P
USB2_N
USB3_P
USB3_N
USB1_P
GND_USB
GND_USB
1
2
3
4
USB_P2_P
USB_P2_N
USB_P3_P
USB_P3_N
8
7
6
5
4
3
2
1
CP506
22P*4/NA
1206
3
2
RP506
0*4/NA
RPSOA_8C_DFS
C
90Z/100M
CHOKE_ACM2012
5
6
7
8
4
1
L47
L28
1
USB1_N
0
C
2
GND
1
1
0603
C273
L29
1
2
2
C272
47P/NA
0603
47P/NA
0603
0
2
0603
GND_USB
GND
GND_USB
USB2_P
+5V_P
+VCC_USB_1
1
5
2
10
USBOC1#
B
GND1
GND2
GND
GND
GND
R804
560
0603
1%
C765
1000P
0603
2
GND
GND_USB
+5V_P
2
0805
3
4
VOUT0
VOUT1
+VCC_USB_2
1
5
R567
390
0603
RT9701-CBL
SOT25
10
USBOC3#
GND
1
R570
560
0603
1%
C763
1000P
0603
2
L30
1
C117
0
2
0603
47P/NA
0603
2
2
C118
47P/NA
0603
GND
2
1
GND
1
1
4
1
L41
90Z/100M
CHOKE_ACM2012
+VCC_USB_4
C528
+ 150U
7343
6.3V
2
2
3
VIN1
2
1
C686
1U
0603
USB3_P
VIN0
1
0
GND_USB
1
R574
U522
2
1
1
1
JO527 JO50 JO49
1
GND_USB
USB3_N
C766
+ 150U
7343
6.3V
R805
390
0603
RT9701-CBL
SOT25
+VCC_USB_3
1
VOUT1
1
VOUT0
2
1
VCC
USB0USB0+ GND1
GND
GND2
GND_USB
2
VIN1
C764
1U
0603
USB/4PX2/DIP
MOLEX
67298-2000
2
2
2
2
2
2
1
2
JO528 JO21 JO20
1
2
C104
47P/NA
0603
1
1
1
C107
47P/NA
0603
VIN0
1
A1
A2
A3
A4
4
1
+VCC_USB_4
USB2_N
3
2
90Z/100M
CHOKE_ACM2012
B
U521
2
0805
2
0
GND
4
1
L38
R585
VCC
USB0USB0+
GND
2
3
2
1
2
3
4
GND
1
J506
+VCC_USB_2
L31
1
A
GND
0
2
A
0603
GND_USB
GND_USB
GND
Title
USB
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
21
of
29
5
4
3
2
1
+3V
For Lan
5
6
7
8
2
SI4788CY
SO8
C508
10U
1206
10V
C506
1U
0603
2
C505
1U
0603
DRAIN3
DRAIN1
DRAIN2
GND
1
SOURCE3
SOURCE2
SOURCE1
VIN
2
1
+3V_ON
1
U501
4
3
2
1
+3V_P
SW1
GND
GND
GND
18,20
1
2
LID#
3
4
D
30V/0.1A
DT006-P11AA-A
2
D
R1
+5V
For USB
470
C10
1U
0603
1
GND
C11
10U
1206
10V
C9
1U
0603
SW2
2
2
SI4788CY
SO8
2
DRAIN3
DRAIN1
DRAIN2
GND
1
SOURCE3
SOURCE2
SOURCE1
VIN
5
6
7
8
1
+5V_ON
1
U1
4
3
2
1
+5V_P
18
GND
GND
PWRSW#
PWRSW#
1
3
2
4
5
GND
TC010-PSS11CET
GND
H8_AVREF
2
1
Q14
SI2301DS
G
R63
100K
0603
C96
4.7U
1206
16V
D
Q11
SI2301DS
2
G G
1
2
A
RLZ5.6B
PC72
10U
1206
10V
S
G
D3
AMS3107
SOT223
+5V_P
S
2
OUTPUT
D
D
S
3
K
INPUT
FUSE_1206
3216FF-1
1A-1206
GND
1
D
S
PWR_VDDIN
VDD5
U10
2
1
F2
1
GND
GND
GND
SW_VDD5
9,11
PCIRST#0
SW_VDD5
GND
1
0603
2 R77
0
1
0603
2 R84
0/NA
C
Q12
DTC144WK
2
1
18
3
C
GND
+1.8V
+1.8V_P
JO15
1
2
Q16
OPEN-SMT4
JP_SMT4_DFS
+5V
VDD3
SVDD3
+5V_P
+1.35V_P
S
D
S
+1.35V
D
1
2
GND/ADJ
OPEN-SMT4
1
JO505
1
2
R24
9.09K
0603
1%
OPEN-SMT4
JP_SMT4_DFS
ADEN#
R91
47K
0603
18,23
Q15
R1
GND
B
R97
2
1
DTC144TKA
2
H8_PWRON_RSM5V 18
0
0603
GND
286301117021
積甲
2
2
2 R21
6.81K
1%
1
0603
+1.5V_P
JO16
K
BAS32L
GND
+1.5V
2
1
D2
A
C20
2.2U
0805
+80-20%
1
+3V_P
JO506
1
2
AME1117
SOT223
+3V
SVDD3
1
VOUT
1
C275
2.2U
0805
+80-20%
2
C18
0.1U
0603
50V
3
2
2
OPEN-SMT4
JP_SMT4_DFS
SI2301DS
2
R92
100K
0603
VIN
G
SVDD3
U4
3
2
JO18 1
OPEN-SMT4
JP_SMT4
B
VDD5
2
OPEN-SMT4
JP_SMT4_DFS
1
1
1
JO17
2
OPEN-SMT4
JP_SMT4
JO12
1
2
G
1
1
JO11
1A
OPEN-SMT4
GND
+VCCP
+2.5V_DDR
+1.05V_P
+2.5V_DDR_P
1.05V
JO52
1
2
JO517
OPEN-SMT4
JP_SMT4_DFS
JO53
1
2
VDD1.5
VDD3
GND/ADJ
AME1117
SOT223
GND
R234
1
2
+1.25V_DDR_P
1
2.2U
0805
+80-20%
R13
10K
0603
C260
4,9,18,20,25,26,27,29
0603
SUSB#
1
+3V_ON
3
A
Q5
+5V_ON
DTC144TKA
GND
R235
+5V_P
OPEN-SMT4
JP_SMT4_DFS
+5V_PP
JO74
1
1
GND
2
1
GND
2
2
PC82
+ 220U
7343
2V
200
1%
1
JO54
2
VOUT
1
2
2
PC74
10U
1206
10V
C259
0.1U
0603
50V
A
1
+5V_P
VIN
R1
2
1
2
OPEN-SMT4
JP_SMT4_DFS
+1.25V_DDR
+3V_P
U16
3
OPEN-SMT4
JP_SMT4_DFS
1
OPEN-SMT4
JP_SMT4_DFS
JO521
2
2
1
2
1
1
2
40.2
0603
1%
286301117021
積甲
1A
OPEN-SMT4
JP_SMT4_DFS
JO75
2
GND
Title
Size
C
OPEN-SMT4
JP_SMT4_DFS
Date:
5
4
3
2
Power interface & Connector
Document
Number
Rev
01
411682810001
1
22
of
29
5
4
3
2
1
PWR_VDDIN
PD503
2
PD501
1
3
3
2
D
1
PD504
SPARKGAP_6
GND
1
2
1
2
3
D PQ10
S 2N7002
SOT23_FET
G
PC503
0.1U
0603
50V
BATT
24
GND
2
1
PC14
1000P
0603
25V
10%
1
18
1
I_LIMIT
PC22
0.01U
50V
10%
0603D
2
2
GND
1
PQ11
DTC144WK
SOT23AN_1
2
GND
PL2
120Z/100M
2012
PC501
1U
0805
10V
GND
GND
PF1
GND
6.5A/32VDC
2
B2
2
1
2
1
BATT
PC15
0.1U
0603
50V
24
PR19
499K
0603
1%
18
PC32
0.1U
0603
50V
B
2
2
2
BAT_V
PR34
100K
0603
1%
18
PR6
20K
0603
1%
GND
PC12
0.1U
0603
50V
2
GNDB
2
R/A-7P/2.5MM
SUYIN
25131A-07G1-C
1
1
BAT_T
PC19
0.1U
0603
50V
1
GND
PR7
4.99K
0603
1%
7
6
5
4
3
2
1
2
PJ502
B
1
1
1
2
2
SVDD3
B3
PL3
120Z/100M
2012
1
1
1
2
5
6
7
8
2
C
1
2
2
1
MAX4173FEUT-T
SOT26
PR501
10
0603
18,22
S
GND1
GND0
3
1
OUT
ADEN#
3
1
6
OPEN-SMT4
PR507
1M
0603
PU501
VCC
PR47
33K
0603
PJO501
D 2
C
RS+
RS-
PQ502
2N7002
S
1
LEARNING
D
S
G
GND
2
2
D
1
G
18
LEARNING
PQ4
AO4407
SO8
4
D
1
GND
4
5
PQ5
AO4407
SO8
4
GND
PC3
0.1U
0603
50V
2
PR55
226K
0603
5
6
7
8
SPARKGAP_6
1
1
1
1
100K
0603
PR504
100K
0603
1
2
3
JO502
1
1
JO501
PC4
1000P
0603
10%
2
2
A
2
PR42
2
2
PR505
4.7K
0805
PR506
4.7K
0805
2
PR503
470K
0603
DVMAIN
SBM1040
4
PD502
RLZ24D
MLL34B
1
K
PR502
.02
2512
1%
1
2
1
2
3
4
PC506
0.1U
0603
50V
3
2
G
PC505
1U
0805
25V
3
2
1
A4
2
D
PL502
120Z/100M
PC5022012
0.1U
0603
50V
1
S
2
A3
1
1
2
2
7A/24VDC
A2
2
24
D
PF501
1
ADINP
8
7
6
5
S
A1
1
PQ501
AO4407
SO8
2
1
1
2
OPEN-SMT4
1
JACK-2P
JO1
1
G
PJ501
2DC-S107B200
S
PL501
120Z/100M
2012
2
D
BAV70LT1
BAV70LT1
PR510
0
0603
2
GND
1
BAT_C
18
BAT_D
18
PR511
1
2
PD506
0
0603
2
VDD5
3
1
PD507
BAV99
2
VDD5
3
2
2
1
JO507
SPARKGAP_6
A
BAV99
JP501
SPARKGAP_6
A
1
1
GND
GND
GND
GND
Title
Size
C
Date:
5
4
3
2
ADINP & Discharge
Document
Number
Rev
01
411682810001
1
23
of
29
5
4
3
2
1
CHARGING
PQ6
AO4407
SO8
D
3
2
1
PL508
L2
1
L3
2
5
6
3
BATT
23
K
4
2
1
2
2
2
1
A
1
2
1
D 1
1
PQ503
D
2N7002 S
SOT23_FET
2
LI_OVP 13.006V
GND
PR64
1M
0603
PC54
150P
0603
2
4
PU8A
LMV393M
SSOP8
G LI_OVP
S
1
2
2
PR8
976K
0603
1%
2
C
GND
PC56
1
2 0.01U/NA
50V
0603
GND
10%
PR79
100K
0603D
PC62
1U
0805
10V
PC49
1000P
0603
10%
2
2
2 0.01U 10%
50V
0603
2
PR58
15K
0603
1%
PR73
124K
0603
1%
2
1
1
1
1
1
2
2
-
2
2
PR9
487K
0603
1%
GND
2
2
8
7
6
5
4
3
2
1
TL594C
SO16
PC535
PR513
33K
0603
1
+
PR62
13.7K
0603
0.1%
PC46
0.1U
0603
50V
PD2
BZV55C20
MLL34B
1
E1
C1
E2
GND
C2
RT
VCC
CT
OUTPUTCTRL
DTC
REF
FEEDBACK
2IN1IN2IN+
1IN+
2
2IN+
GND
PR514
100K
0603D
PR3
1M/NA
0603
1%
1
9
10
11
12
13
14
15
16
PC55
0.1U
0603
50V
PR4
20K
0603
1%
PR10
13.7K
0603
0.1%
PR63
47K
0603
1
1
3
PR74
10K
0603D
1%
PR512
1
PC533
2
PC59
REF
1
1
2
2
PR518
1
2 6.19K
1%
0603
0.1U
16V
0603
10%
PR75
2.49K
0603
1%
GND
GNDB
2
0.1U
50V
0603
2
.02
2512
1%
1
2
3
1
CHARGING
VDD5
PU5
1
D
G
1
1
1
2
2
18
8
1
GND
A
PQ13
MUN2137T1
SOT23AN_1
PC10
0.1U/NA
0603
25V
20%
2IN+
CHARGING
RLS4148
PQ12
D 2N7002
S SOT23_FET
S
CHARGING
L6
1
GND
1.25V
2
PC530
10U
1210
25V
1
K
1A-1206
FUSE_1206
PC27
0.1U
0603
50V
1
2
E
2
PC550
10U
1210
25V
PR56
130K
0603
0.1%
EC31QS04-TE12L
DC2010
PD3
PF2
1
2
K
PD508
A
2
C
PR38
100K
0603D
PQ9
MMBT2222A
B
1
+ PC525
100U
25V
4
PR53
4.7K
0603
2
PR51
4.7K
0603
GND
C
8
7
12.6V
L5
2
47UH
1
PC532
10U
1210
25V
1
1
1
PC531
0.01U
0603
50V
10%
2
120Z/100M
2012
1
PC527
0.01U
0603
50V
10%
2
1
2
PL506
L4 1
G
EC31QS04-TE12L
DC2010
PU505B
AO4807
SO8
1
K
2
PD509
PU505A
AO4807
SO8
1
L1 A
D
ADINP
S
23
D
8
7
6
5
1
2
PR72
63.4K/NA
0603
1%
B
18
1
I_CTRL
PJS501
2
B
1
2
SHORT-SMT3
PR69
0
0603
DVMAIN
PR77
750K
0603
1%
BATT_DEAD 18
8.56V
2
PR80
100K
0603
7
PU8B
LMV393M
SSOP8
1
4
+
6
2
8
PC64
0.1U
0603
5
PC65
0.1U
0603
50V
2
2
3
PQ14
SOT23N
SCK431LCSK-.5
1
1
2
1.25V
1
PR78
100K
0603
2
GND
1
1
PC63
0.1U
0603
50V
2
2
PR76
3.3K
0603
1
1
VDD5
A
GND
A
GND
Title
Charger
Size
C
Date:
5
4
3
2
Document
Number
Rev
01
411682810001
1
24
of
29
5
4
3
2
1
D
D
PL5
1
1
2
PC60
0.1U_NA
0603
50V
C
GND
2
PR92
34K
0603
1%
2
1
1
PU6
SI4800DY
SO8
2
PR93
20K
0603
1%
2
1
G
PC58
+ 220U
7343
4V
4
1
2
PC61
10U
1206
10V
+2.5V_DDR
+1.35V_P
S
D
3
2
1
1
PC57
0.1U
0603D
50V
2
1
2
C
2
120Z/100M
2012
GND
8
7
6
5
5
6
7
8
PC44
0.1U
0603D
50V
1
4
D
PC53
+ 220U
7343
4V
PC47
10U
1206
10V
PU7
SI4800DY
SO8
G
S
1
2
3
+1.5V_P
PC45
10U
1206
10V
2
2
1
1
PU14
1
2
PR94
20K
0603
1%
SC338
PSOP10_0.5MM
PR95
10K
0603
2
18 PWRON_1.35V_1.5V
+5V_PP
1
PR91
0/NA
0603
10
9
8
7
6
2
GND
2
SUSB#
IN
DRV2
ADJ2
EN2
PGD2
1
4,9,18,20,22,26,27,29
DRV1
ADJ1
EN1
PGD1
GND
1
1
2
3
4
5
GND
PC24
0.1U
0805
20%
GND
GND
TP5
TOUCHPAD_10
1
1
GND
TP6
TOUCHPAD_10
B
B
A
A
Title
Size
C
Date:
5
4
3
2
1.35V & 1.5V(SC338)
Document
Number
Rev
01
411682810001
1
25
of
29
5
4
3
2
1
D
D
PR82
0
0603
PU10
7
VDDQ
AVIN
VTT
PVIN
GND
GND1
GND2
GND3
GND4
GND5
PC90
22U
1210
10V
1
+DDR_VREF
+1.25V_DDR
2
+1.25V_DDR_P
PJL1
3
VSENSE
1
PC89
22U
1210
10V
2
PC92
0.1U
0603
50V
4
VREF
1
8
2
JP_NET20
1
9
10
11
12
13
1
6
SD
LP2996
SO8_GND_4
GND
PC85
+ 220U
7243
2V
2
GND
PC83
0.1U
0603
50V
2
5
0603
1
PL7
PC87 120Z/100M
1000P 2012
0603
25V
10%
2
PR83
0
0603
PR524
0
2
2
1
+2.5V_DDR
2
2
1
2
1
2
1
+2.5V_DDR
1
SUSB#
1
4,9,18,20,22,25,27,29
GND
C
C
GND
+1.8V_P
PU3
EN
IN
OUT
ADJ
8
5
PR37
4.99K
0603
1%
2
3
6
7
+3V_P
2
PL4
2
PC35
0.1U
0805
20%
PC34
10U
1210
10V
1
1
2
PC31
1U
0603
PR33
10K
0603
1%
PC36
10U/NA
1206
10V
GND
B
2
1
PC40
0.1U
0805
20%
2
120Z/100M
PC29
1000P 2012
0603
10%
2
2
B
1
1
2
1
AME8807
SO8
1
1
2
4
1
2
PR14
470
0603
1
1
SUSB#
GND0
GND1
GND2
GND3
4,9,18,20,22,25,27,29
GND
GND
GND
GND
A
A
Title
Size
C
Date:
5
4
3
2
1.8V&1.25V (LP2996)
Document
Number
Rev
01
411682810001
1
26
of
29
5
4
3
2
1
DVMAIN
PL6
2
1
1
1
2
PC81
0.1U
0603D
50V
JP_NET20
GND
GND
2
GND
1
2
6
5
3
10U
10V
1206
1
AO4900
SO8
1
2
PC86
0.1U
0805
20%
2
2
4
GND
GND
1
2
3
4
5
6
7
8
1
PC102
220P
0603
10%
PC103
100P
0603D
10%
2
2
1
1
1
1
180P/NA
0603D
5%
2
2
2
1
1
1
PC545
220U/NA
7343
4V
1
2
1
PC547
180P/NA
0603D
5%
PC96
1000P
0603
10%
PJS2
2
SHORT-SMT1
SGND2
1
2
PC542
+ 220U +
7343
4V
1
2
2
2
2
PR531
20K
0603
1%
PR532
332K
0603
1%
PR533
15K
0603
1%
1
B
PC543
220U
7343
4V
SENSE1.2-
2
1
21
1
2
PC100
100P
0603D
10%
PC541
10U +
1210
10V
PC546
SENSE1.2+
2
2
PR84
100K
0603
PR89
2K
0603
PR529
20K
0603
1%
1
1
PC548
180P/NA
0603D
5%
2
+3V_P
PC540
0.1U
0603D
50V
43.2K
0603
1%
1
1
PC101
220P
0603
10%
2
1
1
2
1
1
GND
PR526
EC10QS04
PC97
1000P
25V
10%
0603D
SENSE1.05+
PR528
1.13K/NA
0603D
+2.5V_DDR_P
.005
2512
1%
PD512
1000P GND
0603
10%
SENSE1.05-
C
2
S
2
1
PC95
PC98
4700P
0603 1
2
2.5V1
2
S
PC75
0.1U
0603D
50V
PU12
SI4832DY
SO8
D
G
4
2
PL511
4.7UH
D124C
2
1
2
1
1
2
1
2
2
2
PR522
1
K
G
NC1
SW2
TG2
RUN/SS2
SENSE2+
SENSE2NC0
VOSENSE2
A
AO4900
SO8
D
PC549
SW1
TG1
PGOOD
RUN/SS1
NC2
SENSE1+
SENSE1NC3
SGND1
SGND2
SGND3
SGND4
SGND5
5
6
7
8
8
7
PU9B
1
1
2
PL510
4.7UH
D124C
.01
2512
1%
PC77
+ 220U_NA
7343
2V
S
16
15
14
13
12
11
10
9
1
2
3
25
26
27
28
29
30
31
32
33
34
35
36
37
2
TSW1
2
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
2 1.05V_1 1
+1.05V_P
180P/NA
PC76
0603D
+ 220U
5%
7243
2V
PU11
SI4800DY
SO8
D
G
4
LTC3728L
HVQFN32_1
1
2
3
PR81
1
C
PC93
0.1U
0805
20%
PU13
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
3
S
24
23
22
21
20
19
18
17
1
G
2
PC79
1000P
0603D
25V
10%
TBG2
PC544
0.1U
0603D
50V
1
D
1
JP_NET20
2
0
0603D
TBG1
5
6
7
8
1
2
PU9A
PJL3
GND
BAW56
SOT23N
PC91
INTVCC12
1
PR523
+5V_PP
6.34K
0603
1%
PC94
1000P
0603D
25V
10%
GND
PD5
PR530
D
PJL2
PC538
10U
1210
25V
20%
1
PC88
10U
1210
25V
20%
2
PC84
10U
1210
25V
20%
1
1
PC539
0.1U
0603D
50V
2
2
PC80
0.1U
0603D
50V
1
1
2
DVMAIN_D2
2
120Z/100M
2012
2
1
D
GND
B
PR527
0
0603
29 VCCP_PWRGD
2
VDD5
D
VDD5
S
1
2
D
PR85
100K
0603
D
S
G
D PQ15
S 2N7002
SOT23_FET
2
PQ505
2N7002
SOT23_FET
G
S
PR525
1M
0603
D
S
1
2
SUSB#
INTVCC1
D PQ504
S 2N7002
SOT23_FET
G
4,9,18,20,22,25,26,29
1
PR88
10K
0603D
D
1
2
PR87
100K
0603
D
S
G
SUSC#
S
1
9,18,28
PR86
1M
0603
PQ16
2N7002
SOT23_FET
2
GND
GND
GND
A
A
Title
Size
C
Date:
5
4
3
2
+2.5V & 1.05V(LTC3728L)
Document
Number
Rev
01
411682810001
1
27
of
29
5
4
3
2
1
DVMAIN
D
D
PL1
2
JP_NET20
1
PC5
0.1U
0603D
50V
1
2
2
PJL4
+ PC504
100U
25V
1
PC508
10U
1210
25V
20%
2
1
PC507
10U
1210
25V
20%
2
GND
GND
2
1
GND
GND
PR1
PJL5
1
2
0
0603D
BG1
10U
10V
1206
1
1
AO4900
SO8
2
4
PC7
0.1U
0805
20%
PC6
0.1U
0603D
50V
3
1
2
PC516
0.1U
0603D
50V
PC515
10U/NA
1210
10V
PC518
+ 150U
7343
6.3V
2
EC10QS04_NA
PC517
+ 150U
7343
6.3V
2
K
PD505
S
3
2
1
2
PC23
180P/NA
0603D
5%
1
PC37
220P
0603
10%
PC38
100P/NA
0603D
10%
PR48
15K
0603
1%
SENSE2-
PC11
1000P
0603
10%
B
PJS1
2
2
PC30
PR30 180P/NA
20K
0603D
0603 5%
1%
1
2
1
1
2
1
1
21
PC25
100P
0603D
10%
PC26
220P
0603
10%
PR35
332K
0603
1%
2
2
1
2
1
1
SHORT-SMT1
S
2
D
S
G
PR90
2K
PR290603
20K
0603
1%
1
PC20
1
2
180P/NA
0603D
5%
PC28
180P/NA
0603D
5%
PR44
1.13K/NA
0603D
2
B
D
PQ1
2N7002
SOT23_FET
4
1
2
3
4
5
6
7
8
2
2
GND
G
1
PR15
107K
0603
1 1%
SI4832DY
SO8
D
+5V_PP
SENSE2+
2
PR12
63.4K
1 0603
1%
2
PC16
1000P
25V
10%
0603D
2
0.008
2512
1%
1
8
7
6
5
1
1
1
SENSE1-
PR509
2 5V_21
10UH
CDRH127-100MC
PU504
2
1
1
2
PC13
PC18
1000P
0603 1
2
10%
1000P
25V GND
10%
0603D
SENSE1+
S
1
PC512
0.1U
0603D
50V
PL504
16
15
14
13
12
11
10
9
A
1
1
1
PC511
10U
1210
10V
2
PC513
PC514
+ 220U_NA+ 220U
7343
7343
4V
4V
2
1
2
2
2
1
G
NC1
SW2
TG2
RUN/SS2
SENSE2+
SENSE2NC0
VOSENSE2
1
D
SW1
TG1
PGOOD
RUN/SS1
NC2
SENSE1+
SENSE1NC3
SGND1
SGND2
SGND3
SGND4
SGND5
2
AO4900
SO8
25
26
27
28
29
30
31
32
33
34
35
36
37
2
8
7
PU502B
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
2
10UH
CDRH127-100MC
1
1
.01
2512
1%
C
S
1
2
3
PL503
2 3V_1
2
PR508
1
+3V_P
4
LTC3728L
HVQFN32_1
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
GND
PU503
SI4800DY
SO8
D
G
PU2
24
23
22
21
20
19
18
17
GND
S
C
BG2
PC8
0.1U
0805
20%
2
G
2
D
1
6
5
PU502A
2
PC509
1000P
0603D
25V
10%
11
JP_NET20
5
6
7
8
+5V_PP
BAW56
SOT23N
PC9
INTVCC 2
1
3
2
PD1
2
GND
PC510
1000P
0603D
25V
10%
1
PC1
0.1U
0603D
50V
2
PC2
0.1U
0603D
50V
1
1
1
120Z/100M
2012
1
2
DVMAIN_D
2
2
1
PR43
0
0603
PR21
10K
0603D
GND
SGND
2
VDD5
2
1
GND
INTVCC
PR2
1
D
100K
0603
1%
D PQ3
S 2N7002
SOT23_FET
D
S
G
D PQ2
S 2N7002
SOT23_FET
G
SUSC#
2
S
9,18,27
PR5
1M
0603
1
GND
GND
A
A
Title
Size
C
Date:
5
4
3
2
3V & 5V(LTC3728L)
Document
Number
Rev
01
411682810001
1
28
of
29
4
PL507
120Z/100M
2012
1
2
1
1
2
1
2
1
2
PC536
+ 220U
7243
2V
PC69
+ 220U/NA
7243
2V
PC68
+ 220U
7243
2V
PC66
0.1U
0603
50V
2
1
1
2
2
PC70
+ 220U/NA
7243
2V
1
A
2
PC48
4700P
0603
2
EC31QS04-TE12L
DC2010
PC71
+ 220U
7243
2V
1
1
PC52
0.1U
0603
25V
20%
PC50
10U
1206
10V
PD510
EC31QS04-TE12L1
DC2010
2
PD511
1
S
A
S
K
K
S
PR61
200
0603
PR57
200
0603
PC67
0.1U
0603
50V
2
1
PU509
FDS7788
SO8
PC73
+ 220U
7243
2V
2
D
G
4
PC537
+ 220U
7243
2V
1
1
5
6
7
8
PU510
FDS7788
SO8
C
PC78
+ 220U
7243
2V
2
1
2
3
D
G
2
1
1
2
3
5
6
7
8
1
2
1
2
0.68UH
IHLP-5050CE
15%
2
VID5
2
VID3
1
2
2
VID4
1
1
1
2
1
2
2
PR31
56.2K
0603
1%
1000P
25V
0603
10%
+VCC_CORE
2
1
2
3
5
6
7
8
PU511
FDS7788/NA
SO8
4
D
G
4
1
2
3
1
+5V_PP
PC51
PR520
.001
2512C
1%
2
PC43
0.1U
0805
X7R
PD4
EC10QS04
GND
PR65
0
PR66
PR67
0603 0
PR70
0603 0
0603 0
0603 PR68
0
0603
5
6
7
8
S
2
1
45
44
PR60
0
0603
1
PC33
1000P
0603
25V
10%
4
S
1
2
3
GND5
GND4
PJL7
JP_NET20
2 1
PJL6
JP_NET20
GND
1
21
22
23
24
25
26
27
28
29
30
GND_A
2
2
1
1
1
PC519
10U
1210
25V
20%
PU506
AO4406
SO8
D
G
PL509
K
GND
CC
POS
NEG
FB
OAINOAIN+
CSP
CSN
DPSLP
PU507
AO4406
SO8
S
10
9
8
7
6
5
4
3
2
1
VCC
ILIM
REF
SHDN
S2
S1
S0
B2
B1
B0
11
12
13
14
15
16
17
18
19
20
+VCC_CORE
1
2
OAIN1
2 OAIN+
PR50 CSP+
PC41
CSN1K
100P
0603
0603
1%
10%
4
1
1
PU4
MAX1907
HVQFN40_1PR20
10K
43 0603
GND3
42
GND2
41
GND1
40
TON
39
TIME
38
CLKEN
37
IMVPOK
36
SYSPOK
35
SUS
34
V+
33
DH
32
LX
31
BST
G
A
2
1
1
PC42
0.1U
0805
X7R
PC17
1U
0805
10V
D5
D4
D3
D2
D1
D0
DD0
PGND
DL
VDD
1
2
PC39
47P
0603
10%
PR45
2.74K
PR40 0603
100K 1%
0603
1%
PU508
D
AO4406/NA
G
SO8
4
D
2
2
1
2
5
6
7
8
5
6
7
8
2
GND_A
C
PC520
10U
1210
25V
20%
GND
PR11
49.9K
0603
1%
GND_A
PC521
10U
1210
25V
20%
GND
1
2
3
2
PR13
10
0603
PC522
10U
1210
25V
20%
1
2
PR22
301K
0603
1% REF_CORE
1
2
1
1
PC523
10U
1210
25V
20%
2
+5V_PP
PC524
10U
1210
25V
20%
RUNPWROK
PC21
0.22U
16V
0603
10%
1
+ PC528
10U
25V
20%
1
2
BOOT MODE DAC =1.212V
PC526
0.1U
0603
50V
2
1
1
D
2
2
2
PL505
120Z/100M
2012
PC529
1000P
0603
10%
2
1
SUSPEND MODE DAC =0.748V
1
1
2
PR28
0
0603
2
1
2
1
2
PR23
0_NA
0603
DD_CPU
1
2
1
D
+5V_PP
1
1
PR27
0
0603
2
REF_CORE
2
DVMAIN
PR24
0
0603
1
1
2
PR26
0
0603
2
2
1
PR25
0
0603
1
3
2
5
2
VID2
PR71
0
0603
1
2
1
VID1
2
JS1
1
VID0
SHORT-SMT1
PR36
01
0603
PR49
2
0
0603
2
1
2 PR41
0
0603
2
GND
PR46
0
0603
CSP+
CSN-
GND_A
B
1
PR59
0
0603
PR54
510
0603
OAIN+
OAIN-
VID[0..5]
VID0
VID1
VID2
VID3
VID4
VID5
VDD5
PR18
1
PR17
100K
0603
RUNPWROK
2
+3V
100K
0603
PR16
D PQ8
S 2N7002
SOT23_FET
D
S
G
PR39
1M
0603
2
0
0603
CORE_CLKEN# 4
VRMPWRGD 9
VCCP_PWRGD 27
DPRSLPVR 9,10
STOP_CPU# 3,4,5,9
PQ7
2N7002
SOT23_FET
S
1
SUSB#
2
1.96K
0603
1%
S
D
G
1
2
D
1
PR32
4,9,18,20,22,25,26,27
2
2
1
VID[0..5]
1
1
PR52
1K
0603
1%
2
3
B
2
A
A
GND
Title
Size
C
Date:
5
4
3
2
CPU_CORE1(MAXIM1907)
Document
Number
Rev
01
411682810001
1
29
of
29
Reference Material
INTEL Banais Processor
INTEL, INC.
Intel Montara-GME GMCH
Intel, INC.
Intel 82801DBM ICH4-M
Intel, INC.
WINBOND W83L950D Universal Controller
WINBOND, LTD.
PhaseLink PLL207-151
PhaseLink,INC
VIA Rhine III VT6105LOM
VIA, INC
System Explode View
Technology Corp / MiTAC
8089P Hardware Specification
Technology Corp / MiTAC
183
w w w. p r e s t i g i o. c o m

9. Spare Part List

Transcription

Similar documents

CF-29 Schematic Diagram

7170 n/b maintenance

MAIN - Gardner, Inc.

Intel 852GM Chipset Platform