docElectronic Etch-a-Sketch Project Objectives Etch-a
download 
Report Transcription
Electronic Etch-a-Sketch Project Objectives Etch-a
Electronic Etch-a-Sketch Project Objectives Project Concept and Background Broad “brush” overview of the project Checkpoint Structure Details will be covered in the lab lectures Bells and Whistles NOTE: anything discussed in the lab lectures and project checkpoint write-ups supercedes what I describe here! The TAs know the project better than I do! CS 150 - Fall 2005 – Lec. #12: Course Project - 1 Etch-a-Sketch CS 150 - Fall 2005 – Lec. #12: Course Project - 2 Electronic Etch-a-Sketch AKA an electronic “paint” machine … Recent CS 150 projects: network streaming audio, network digital “telephone”, pong, video image processing, … audio and/or video a common theme This is a good CS 150 project because … It is NOT a processor architecture (take CS 152 for that!) Vast majority of digital designs involve interfacing with the real world, with real world timing constraints! Hardware Systems: Input, Processing, Output CS 150 - Fall 2005 – Lec. #12: Course Project - 3 Etch-a-Sketch One possible way to do it … Pen/brush position/size (and special effects) inputs State of the screen in frame buffer in SDRAM Modified by drawing semantics Refresh LCD screen from frame buffer in SDRAM CS 150 - Fall 2005 – Lec. #12: Course Project - 4 Electronic Etch-a-Sketch Implement this … CS 150 - Fall 2005 – Lec. #12: Course Project - 5 with this … CS 150 - Fall 2005 – Lec. #12: Course Project - 6 Etch-a-Sketch Block Architecture Calinx Board Video & Audio Ports Four 100 Mb Ethernet Ports AC ’97 Codec & Power Amp 8 Meg x 32 SDRAM Flash Card & Micro-drive Port Quad Ethernet Transceiver Checkpoint #4: Paint Engine Prototype Area Cursor Position Cursor Size Brush Color Xilinx Virtex 2000E Seven Segment LED Displays Calinx Board Checkpoint #1: N64 Game Controller Interface CS 150 - Fall 2005 – Lec. #12: Course Project - 7 Checkpoint #3: SDRAM Controller Arbiter CS 150 - Fall 2005 – Lec. #12: Course Project - 8 Checkpoint #1: N64 Interface Checkpoint #2: Video Encoding This week in lab! Pixel Array: Digital image represented by matrix of values, where each is a function of the information surrounding it in the image; single element in image matrix: picture element or pixel (includes info for all color components) Array size varies for different apps and costs: some common sizes shown Continually poll N64 and report state of buttons and analog joystick Issue 8-bit command Receive 32-bit response Each button response is 32 bit value containing button state and 8-bit signed horizontal and vertical velocities SIF, 82 Kpx Serial interface protocol Multiple cycles to perform each transaction Frames: Bits obtained serially--UART-like functionality Video, 300 Kpx Illusion of motion created PC/Mac, 1‡2 Mpx by successively flashing still Framing (packet start/stop) High-Definition Television (HDTV), 1 Mpx pictures called frames Bit encoding Checkpoint #2: NTSC Video Paint EngineSDRAM Interface Video Encoder & Decoder Workstation, 1 Mpx High-Definition Television (HDTV), 2 Mpx start | data | data | stop CS 150 - Fall 2005 – Lec. #12: Course Project - 9 CS 150 - Fall 2005 – Lec. #12: Course Project - 10 FIGURE 1 Composition of interface data stream Frame size, frame rate Pixel encodings: RGB, YUV/YCB (Luminance, Chrominance -brightness plus color difference signals) Subsampling to reduce data demands (compression trick) Inputs: ITU-R BT.601 Format (Digital Broadcast NTSC) 525 Frames/sec 29.97 Pixels/sec 13.5 M Viewable pixels/line 720 Viewable lines/frame 487 With 4:2:2 chroma sub-sampling, send 2 words/pixel (Cr/Y/Cb/Y) Words/sec = 27M Encoder runs off a 27MHz clock Control info (horizontal & vertical synch) is multiplexed on data lines Encoder data stream show to right See video tutorial documents on course documentation web page! Outputs: Component video, S-video to drive LCDs in lab Fortunately, Calinx board has a chip on-board that deals with much of the grungy details … 858 Lines per frame Luminance data, Y 736 718 719 720 721 (732) 857 (863) 0 1 2 Chrominance data, CR 359 360 368 ( 366 ) 0 1 Chrominance data, CB 359 360 368 ( 366 ) 0 1 Replaced by timing reference signal Replaced by digital blanking data Replaced by timing reference signal CB 0 Y0 CR 0 Y1 Interleaved even-odd frames (TV) vs. progress scan (computer and digital displays) Pixels per line First sample of digital active line Y 855(861) CB 428(431) Y 856(862) CR 428(431) Y 857(863) CB 0 Y0 CR 0 Y1 NTSC vs. PAL, HDTV, … Interfacing details for ITU-601 CB 368(366) Y 736(732) CR 368(366) Sample data for OH instant CB 359 Y 718 CR 359 Y 719 CB 360 Y 720 CR 360 Y 721 Video details fairly complex and involve many choices: ITU-R BT.656 Details CB 359 Y 718 CR 359 Y 719 Checkpoint #2: Video Encoding Last sample of digital active line Start of active video End of active video Timing reference signals Note 1 – Sample identification numbers in parentheses are for 625-line systems where these differ from those for 525-line systems. (See also Recommendation ITU-R BT.803.) CS 150 - Fall 2005 – Lec. #12: Course Project - 11 CS 150 - Fall 2005 – Lec. #12: Course Project - 12 D01 Checkpoint #2: Video Encoder Calinx On-Board Video Encoder Analog Devices ADV7194: ITU 601/656 in, Composite Video Out Supports: Paint engine processes pixels within frame buffer Drive ADV7194 video encoder device to output correct NTSC video Gain lots of experience reading data sheets Multiple input formats and outputs Operational modes, slave/master Dictates the 27 MHz operation rate Used in default mode: ITU-601 as slave Used throughout graphics subsystem CS 150 - Fall 2005 – Lec. #12: Course Project - 13 Checkpoint #3: SDRAM Interface s-video output Digital input side connected to Virtex pins Analog output side wired to on board connectors or headers I2C interface for initialization: Wired to Virtex CS 150 - Fall 2005 – Lec. #12: Course Project - 14 SDRAM READ Burst Timing Memory protocols Bus arbitration Address phase Data phase DRAM is large, but few address lines and slow Row & col address Wait states Synchronous DRAM provides fast synchronous access current block Little like a cache in the DRAM Fast burst of data Arbitration for shared resource CS 150 - Fall 2005 – Lec. #12: Course Project - 15 CS 150 - Fall 2005 – Lec. #12: Course Project - 16 Checkpoint #4: Paint Engine Checkpoint Structure and Schedule Fed a series of “brush” strokes and effects Checkpoint #1: Game Controller Interface (Week 7) Defined by color (including erase), brush shape (height, width), etc. Current brush positions All from N64 Controller interface NOTE: lots of buttons, and lots of opportunity for extra credit brush effects Renders “paint” into frame buffer within range of pixels at current cursor position Must arbitrate for SDRAM and carry out bus protocol Paint engine overlaps writing SDRAM with video interfacing reading SDRAM to drive LCD display Continuously feeding video interface from SDRAM subject to timing specifications CS 150 - Fall 2005 – Lec. #12: Course Project - 17 Checkpoint #2: LCD Interface (Week 8) Checkpoint #3: Memory Interface (Week 9, 10 -Spans Midterm II) Checkpoint #4: Paint Engine/Integration (Week 11, 12, 13+) Early Check-off: Wednesday before Thanksgivings (November 23) Standard Check-off: Wednesday, November 30 Project Final Report: December 7 CS 150 - Fall 2005 – Lec. #12: Course Project - 18 Possible Bells and Whistles Still thinking about this but here are some ideas; These are mostly implemented in the paint engine … Brush sound effects Brush effects, like spray paint, splashes, etc. Brush shapes, like square, oval, triangle Brush physics, soft vs. hard brush, brush angle, etc. (e.g., Japanese caligraphy) Color mixing rather than overwrite Your good idea here NOTE: We don’t necessary know how to implement these ourselves! NOTE: extra credit will be limited to 20% extra points and no extra credit unless the standard functionality works CS 150 - Fall 2005 – Lec. #12: Course Project - 19 CS 150 - Fall 2005 – Lec. #12: Course Project - 20
