# Introduction to the Design and Development of Mixed Signal

## Comments

## Transcription

Introduction to the Design and Development of Mixed Signal

Introduction to the Design and Development of Mixed Signal Integrated Circuits Tutorial 2 Prashant Bhadri Raghuram Srinivasan Sunday, August 7, 2005 15:30-18:30 pm IEEE International 45th Mid-West Symposium on Circuits and Systems Cincinnati, Ohio Copyright Information This presentation is an “Open Access” material and therefore please credit the presenters if you reproduce any of this information Presenter’s Information Education z B.S. in Electronics and Communication z M.S. in Electrical Engineering z Post-Doctoral Fellow at the Doheny Eye Institute, Keck’s School of Medicine University of Southern California, Los Angeles Research Focus z Engineering Solutions in Medical Domain z Analog, Digital, Mixed Signal Circuit Design, Testing and Analysis z Field Programmable Gate Arrays z Product Development of Medical Devices Prashant R Bhadri Doctoral Researcher University of Cincinnati Academic Achievements z 30 papers presented and published in journals, conferences, and magazines z 2 provisional patents z Recipient of Rindsberg Fellowship z Recipient of SPIE Travel Award Education z B.S. in Electrical Engineering z M.S. in Computer Engineering Research Focus z Improving Simulation Time using MultiThreading in a Frequency Extended VHDL-AMS z Analog, Digital, Mixed signal Circuit Design, Testing and Analysis z Formal Verification Methods to Analog and Mixed-Signal Systems Raghuram Srinivasan Doctoral Researcher University of Cincinnati Information Prashant R. Bhadri Raghuram Srinivasan Department of ECECS, College of Department of ECECS, College of Engineering, University of Cincinnati, Engineering, University of Cincinnati, PO Box-210030,Cincinnati, Ohio - 45221 PO Box-210030,Cincinnati, Ohio - 45221 Fax – (513)556-7326 Fax – (513)556-7326 Email: [email protected] Email: [email protected] Copy of the material available on: Distributed Processing Laboratory: www.ececs.uc.edu/~dpl Dr. Fred R. Beyette Homepage: www.ececs.uc.edu/~beyette Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers Motivation Major need for mixed-signal chips driven by consumer products Cell phones Music players Digital Cameras As frequency increases, digital circuits become more analog Clock distribution (PLL’s, pulse shapers, oscillators) Pad design (buffers, protection circuits) Interconnect (become more like transmission lines) Logic cells (become more like RF and microwave circuits) When Digital becomes Analog? Issues in Mixed-Circuit Design As feature size decreases, RF circuit issues become dominant in both digital and analog circuits Noise Coupling noise Component noise Power supply and ground noise Circuit parameters Impedance mismatches Gain Major need for analysis methods and tools Status of Mixed-Signal Design Current technology supports mixed-signal circuits on a chip Bi-CMOS CMOS extended with analog insulator layer Design tools just coming online Analog and Mixed-Signal (AMS) modeling and simulation AMS synthesis (still in research stage) Comparison of CMOS, Bipolar and Bi-CMOS Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005 Common Applications of Bi-CMOS Bi-CMOS circuits are used in places where devices with significant drive current can be used to significantly enhance system performance Many microprocessor designs utilize BiCMOS circuits in their bus controllers, floating point processing unit and the processor core where speed is critical Circuits where power consumption is a concern (ex. Cache Memory) are implemented in the less power hungry CMOS circuits Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005 Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers M-S Design Flow SPECIFICATION DESIGN TESTING VERIFICATION FABRICATION Component Flow Specifications Functional Descriptions, Algorithms + Functional Design Architecture Circuit Floorplan Physical Design - Blocks Abstraction Reference: Ken Kundert, Henry Chang, Dan Jeffries, Gilles Lamant, Enrico Malavasi, Fred Sendig, "Design of Mixed-Signal Systems-on-a-Chip", IEEE Trans. on CAD of ICs and Systems, Vol.19, No. 12, pp. 1561-1571, December 2000. System Domain Integrated circuit design: Complex activity Well-defined process The system is divided into functional blocks (subsystems) Defined first with respect to their interfaces between each other A series of design steps each follow modeling the results Simulation of the model assures the design meets the requirements Iterative Design Process Hardware System Design Flow Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 M-S Design vs. Digital Design Components – Analog/Digital Design Input – Behavioral/Structural Verification – VHDL/Spice/VHDL-AMS Synthesis – Analog is time consuming Fabrication & Testing – Separate steps for Analog and Digital Components Flow Description Results Specifications Layout Design Verification Design System Design Courtesy: Dr. Harold Carter Circuit Design Novel Issues in M-S Design Specification – Too many decision parameters Design – Diverse fields of specializations required Verification – Analysis of multiple domains Evaluation – Statistical analysis Fabrication – SOC fabrication Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers Definitions A set of requirements that need to be satisfied Requirements of a “Good” Specification: Unambiguous Avoid contradictions Realizable with current technology capabilities Specification Parameters Functional parameters - Throughput Analog parameters – Bandwidth, Gain, Threshold etc. Design parameters – Area, Power, etc. Types of components available Environment – Temperature, Pressure etc. Industry Standards provides the base specification Advantages of Clear Specification Quicker design cycle due to fewer errors Testing of components from respective specifications: ex: Virtuoso Aptivia Specification-driven environment Driving Design Cycles – HDL Models are capable of: Being subjected to behavioral analysis (simulation) Layout generation (ASIC, FPGA) Examples of Specification Tools Statecharts/Automata Formal Specification HDL’s: ObjectiveVHDL, SystemVerilog, HDL Monitors, OpenVera, Rosetta Software: SpecC, SystemC, Java Behavioral Models: VHDL-AMS/ VHDL/ Matlab Challenges in a M-S Environment Increased design parameters, increases constraints Multiple levels/domains of specification Constant updates due to technology advances System Specification In a product development environment, the specification document presents the first set of guidelines for an initial design of the system that would solve a given problem System specifications contain explicit details of the design: Size Speed Power Cost Functionality Constraints on available resources need to be taken into account before developing these for the system and the specification in turn imposes constraints on the design process Most standard designs detailed data sheets are available to design engineers Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 System Design Translation of the “Specs” into a micro-electronic circuit Before Beginning: Top Down / Bottom Up Level of Abstraction Type of Final Design – SOC/MS/Analog/Digital Availability of Resources Example M-S System Reference: http://www.techonline.com/community/tech_topic/bluetooth/33005 M-S Design Process Review Specification Design Control Circuitry Replace blocks in design with circuit components Check if IP/Parameterized models are available Power/Layout/Area aware design Characteristics of a “Good” Design Tradeoff between analog and digital components Reduced layout complexity Post-fab testability Flexibility in design modifications: Corrections Posterity Challenges in M-S Design Full custom design vs. IP reuse Multiple domains make controller design more complex Optimization choices much fewer Stricter Design Rules System Design Use of Hardware Description Languages (HDL’s) for describing a system in the Register Transfer Level (also called RTL) Higher levels of abstraction (e.g., behavioral level) are employed for larger designs; lower levels (e.g., gate level, transistor level) for smaller designs This shift from purely digital to Mixed-Signal (MS) systems has risen due to the high values of operating frequencies in communication circuits and shrinking feature sizes Design productivity is one of the major issues of concern in VLSI systems With the size of the chip decreasing exponentially, the complexity of the gates has been increasing exponentially but design methodologies have not kept up with the circuit complexity Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Design Hierarchy Bread Board Printed Circuit Board SMT ASIC Block Level Implementation Lakshminarayanan Ramasamy, “ ASIC System Development of MEMS Bio-Chip Analyzer with Calibration, Signal Capture and Display Circuit”, Masters Thesis, March 2005 PCB & SMT Implementation Lakshminarayanan Ramasamy, “ ASIC System Development of MEMS Bio-Chip Analyzer with Calibration, Signal Capture and Display Circuit”, Masters Thesis, March 2005 M-S Design Photoreceiver Flow Diagram* Photocurrent is generated that is amplified and processed Conversion of the signal from analog to digital with standard CMOS digital circuitry or use the analog signal directly to the next stage of the circuitry Various implementations of photoreceiver circuits is presented where the front end is an optical detector followed by amplifier and processing. *Prashant Bhadri et.al.,“Design and implementation of CMOS photoreceivers”, Proc. SPIE: Optical Information Systems II, October 2004, Vol. 5557, p. 173-184 Optical Detector Configurations CMOS Photodetector* Response to optical illumination in the visible to IR wavelength range Photodetectors fabricated through the MOSIS foundry service Types of photodetectors are: P-diffusion to N-well N-well to P-substrate Combination Bipolar Junction Phototransistor Reference: Prashant Bhadri et. al, “Implementation of CMOS photodetectors in optoelectronic circuits” Proc. IEEE: Lasers and Electro-Optics Society, The 15th Annual Meeting of the IEEE, November 2002, Vol. 2, p. 683 - 684 ASIC Circuit User threshold programmable photoreceiver that monolithically integrates at chip level with the Multi Technology-FPGA User programmed with the receiver threshold set to one of eight sensitivity levels The output from the photoreceiver cell can be stored in SRAM cells By decoding three programming bits (IN0, IN1, IN2) 8 different threshold levels can be established and hence the user can program the sensitivity of the receiver *Prashant Bhadri et.al.,“Design and implementation of CMOS photoreceivers”, Proc. SPIE: Optical Information Systems II, October 2004, Vol. 5557, p. 173-184 Layout Level Transimpedance Amp. Differential Amp. Threshold generation Metal Shielding Guard Rings N-well/p-substrate photo-diode Reference: Prosenjit Mal et.al.,“Development of a Multi-technology FPGA: A Reconfigurable Architecture for Photonic Information Processing” Proc. SPIE: Emerging Optoelectronic Applications, June 2004, Vol. 5363, p. 27-38 System Layout Reference: Prosenjit Mal et.al.,“Development of a Multi-technology FPGA: A Reconfigurable Architecture for Photonic Information Processing” Proc. SPIE: Emerging Optoelectronic Applications, June 2004, Vol. 5363, p. 27-38 Summary Top Level FPGA Design MTFPGA Chip Layout Commercial FPGA devices are electronic Need for incorporation of nontraditional multi technologies into CMOS VLSI systems Proposed a novel architecture that extends the flexibility, rapid prototyping and reusability benefits associated with conventional electronics into the multi-technology domain MTB Floor Plan Reference: Prosenjit Mal et.al.,“Development of a Multi-technology FPGA: A Reconfigurable Architecture for Photonic Information Processing” Proc. SPIE: Emerging Optoelectronic Applications, June 2004, Vol. 5363, p. 27-38 Circuit Design The circuits are designed as cell libraries and then simulated using one of many available circuit simulators These designs are close to the required specification values as a general idea is obtained during this step The challenges are in the form of shrinking chip design requirements, pushing the power and performance boundaries and the need to integrate most of the applications Due to the gradual evolution of the semiconductor process technology, new types of circuit architecture are being implemented As many of the innovative applications assume very low-cost implementations of circuit building blocks, low-cost technology such as CMOS Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules NMOS at bottom and PMOS at top All gates include well and substrate contacts Other Issues Noise Power Delay Chip Noise Circuit noise includes all the disturbances by the circuit’s topology Interconnect noise includes noise coming from capacitive or inductive coupling between interconnects Power supply noise, which refers to deviations of the supply and ground voltages from their nominal values Substrate noise in mixed-signal integrated circuits: For Example: The charge injected in the substrate by the logic gates during the transitions may interfere severely with the operation of sensitive analog circuits Reference: Bartolo’s Thesis, Chapter 1 Shot Noise In a transistor the major contributor to noise is called shot noise. The formula for shot noise in a diode is given as: Reference: Lowen, S.B et.al,“ Power-law shot noise”, Information Theory, IEEE Transactions on Volume 36, Issue 6, Nov. 1990 Page(s):1302 - 1318 Thermal Noise The noise generated by the agitation and interaction of electrons is called thermal noise. The internal kinetic energy of a particle can be expressed through its temperature. The kinetic energy of a body is zero at a temperature of absolute zero. The noise generated by a resistor, for example, is proportional to its absolute temperature as well as the bandwidth over which the noise is to be measured. Reference: Bing Wang,et.al; “MOSFET thermal noise modeling for analog integrated circuits”, Solid-State Circuits, IEEE Journal of Volume 29, Issue 7, July 1994 Page(s):833 - 835 ue 6, Nov. 1990 Page(s):1302 - 1318 Charge Injection Problem Solution When the switch is on, the voltage across the sampling capacitor tracks the timevarying input signal within the bandwidth. Some charges are present in the MOS channel, this is a result of forming a conducting channel under the MOS gate. When the switch is turned off, charges either flow to the input source or to the sampling capacitor and create a small voltage which . is a function of several parameters which include input impedance, source impedance, clock falling edge. Reference: http://kabuki.eecs.berkeley.edu/~gchien/thesis/Masters/appB/appendixB.pdf Clock Feed-through When the clock voltage on the gate switches between high and low, this voltage. drop is coupled into the signal via the capacitor divider. The clock feed-through can be corrected to the first order by using a differential signal path. As long as the error is present on both signal inputs and the same magnitude, it can be cancelled by taking the input differentially. This technique, once again, depends on the absolute matching of transistors. Reference: http://kabuki.eecs.berkeley.edu/~gchien/thesis/Masters/appB/appendixB.pdf Ground Bounce For significant flows the voltage drop across this inductor is given by: VB = L dI/dt For a 50 mA current change over 3 ns in a 3mm x 1 cm line VB = 50 mV which is enough “noise” to disrupt digital signal quality. Reference: http://klabs.org/richcontent/Tutorial/new_modules/ground_bounce.pdf Latch-up This spiking problem leads to a condition called latch-up Falling edge spike goes through C2 turning on transistor Q2 Current flow through Q2 causes voltage drop across RW1 and RW2 turning on transistor Q1 Current flow through Q1 causes voltage drop across RS1 and RS2 further turning on Q2 Rising edge spike has same effect starting with pass through C1 Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005 Solutions to Latch-up Slow the rise/fall time to reduce the size of the spikes Reduce the size of drain region to reduce C1 and C2. Reduce RW1 and RS2 by placing substrate and well contacts close to the transistor drains Place n+ and p+ regions around critical circuits. These features (called guard rings) are effective but take space and limit the ability to use poly as an interconnect layer Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005 Layout Design It is very important for a layout designer to understand the bounds of laying out a circuit as it depends on the type of the circuit designed This step characterizes a chip as a whole where a circuit is laid out, then extracted and its functionality checked During the extraction process a large number of parasitic including capacitances, inductances and resistances is obtained that lead to more complications in circuit design Therefore one of the fundamental limitations of high speed design is to have a strong understanding of layout extraction Most of the layouts are implemented using software tools like Magic, Cadence, and Tanner Tools etc Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Definitions Process of virtually simulating the design and checking conformance with the specs Advantages of Verification: Early error detection Fine tuning the design based on verification output Reliable time metrics can be obtained Verification in a M-S Environment Multiple domains, multiple abstraction levels Simulation cycle handles notion of time in discrete and continuous values Separate simulation engines, working with the same set of signals Output Analysis in Time/Frequency Spice Circuit Simulator First IC evaluation software Has inbuilt components models for circuit elements Allows different levels of models for varying accuracy requirements Provides accurate measurement for power and timing Supports only structural models Comparison of Spice and VHDL-AMS Parameter Behavioral Models Multiple Analysis Modes Digital Components Mixed Time Modeling Equation Set Analysis Power/Area Analysis VHDL-AMS Spice Evolution of M-S HDL’s MAST – Developed during the early 80’s, required expert users VHDL-AMS – First version of the LRM in 1993, shifted burden from user to simulator Verilog-AMS – Extension of Verilog Highlights of VHDL-AMS Inclusion of continuous valued “quantities” Allows design entry at the behavioral or structural levels No concept of components like Spice, only equation sets Analog solution based on numerical integration VHDL-AMS Simulator Design LIBRARIES VHDL-AMS SIMULATOR KERNEL DAE SOLVER FES TyVIS DIGITAL KERNEL LEXICAL ANALZER SPICE WARPED Kernel VHDL Challenges in M-S Verification Convergence – not always a guarantee Large variations in time steps Parasitic capacitances – model order and E.M effects “Ripple Effect”: Whole design needs to be verified during design modifications High Frequency Analysis support still primitive Verification Verification is the process by which the correctness of the design and implementation details is compared to the original specifications Hardware description languages model complex systems A/D components SOC’s have given rise to Analog and Mixed Signal (AMS) tools These tools combine methods from traditional circuit simulators like SPICE and digital simulation kernels like VHDL to deal with both of these components Any unsatisfactory or incorrect parameters can be detected and the design can be modified to correct the errors or approach certain tolerance levels Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Electronic Circuit Design Process A CMOS foundry takes a wafer of silicon and processes it into an array of circuits (called die). The wafer will also contain test structures, process monitoring plugs and alignment reticules. The individual die are diced from the wafer and packaged into a variety of electronic devices. Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005 MOSIS: The MOS Integration Service MOSIS WEBSITE The MOS Integration Service (MOSIS) provides a low cost method for implementing CMOS designs. The service works by purchasing fabrication runs from commercial CMOS foundries and distributing the cost over a larger number of circuit designers. For more information visit the MOSIS web page at www.mosis.org Wafer Cleaning Oxidation Epitaxial Growth Lithography Fabrication Process Description Implantation Diffusion NO Metal Layer? YES Fabricated Chip Metal Deposition Annealing Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005 Fabrication The chip is fabricated (generally on lightly doped p-type or n-type silicon wafer) using specific fabrication technology (i.e. TSMC 0.35µm or IBM 0.13µm process etc.) that has been specified at circuit design level or before A series of photolithographic mask layers are designed depending on type process and number of steps involved Subsequently, the whole design runs through several fabrication steps that involve oxidation, photo-lithography (developing photo-resist layers, exposing to UV and etching), implantation of p+ or n+ source/drain region, metallization for forming contacts and developing field oxide for isolation of transistors Fabrication processes are characterized by minimum feature size in a transistor, gate oxide thickness, no. of poly and metal layers available for interconnections, sheet resistances of different wells, doped regions, and metal and poly-silicon Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Testing Overview Block Diagram of the Photoreceiver Photoreceiver Testing Logic Analyzer Testing Photoreceiver Circuit Courtesy: Dr. Prosenjit Mal Photoreceiver Layout Example of Mixed Signal {Optical} Testing Laser Diode P1 LD Drive Cubicle Splitter P2 Optical Power Meter P3 Fiber Coupler Optical Fiber Computer (LabVIEW Program) P4 Detector/Receiver Multi-meter Power Source Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Example Optical input power changes from 0 – 1mW Most sensitive settings (000) switches around 450µW Least sensitive settings (111) switches around 675µW User can fine tune the range with Vadj Vadj can be changed 0 – 3.3V corresponds to input range shift of 90µW General M-S Tests Continuity Tests: Detecting on Chip ESD Validating Connectivity between Device and Tester Fault Elimination Breakdown Test: Current Limit Voltage Limit Power Supply Test: IDDQ Metal Errors – shorted traces Implant/Diffusion errors – shorted substrate Faulty ESD Clamps Open/Floating Wells Open/Floating Digital gate input Reference: Prof. Forrest Brewer www. bears.ece.ucsb.edu/class/ece224b/Lecture3mixedtest.ppt General M-S Tests (Contd.) Impedance Measurement Z=V/I (Usually Z=DV/DI) Force V, measure I (High Impedance) Force I, Measure V (Low Impedance) Defined Testing Levels Reduce possibility of DUT damage Increase accuracy of measurement Power Analysis Testing over Operation Range Voltage/Current/Freq Memory devices Processors Reference: Prof. Forrest Brewer www. bears.ece.ucsb.edu/class/ece224b/Lecture3mixedtest.ppt Testing To facilitate the testing process, a number of test structures are evenly distributed all over the chip Test station equipment includes pattern generator, logic analyzer, probe station, semi-conductor parameter analyzer, oscilloscope etc While pattern generator and logic analyzer are used for digital test pattern generations and measurements, other equipment facilitate probing of device parameters and analog data measurements The chip is run on through a number of test vector sets which are generated from computer using various test algorithms In conclusion, the circuit is verified for its functionalities and specifications. Also tests are run for a period of time to check any variation of performance Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers VHDL-AMS Overview Capabilities Language Overview Solution Cycle Solvability Discontinuities Predefined Attributes Conclusion References Half Wave Rectifier BEGIN -- behavior --diode equations if( vDiode >= (-1.0 * Vt)) USE eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use eqn1_2: ELSE iDiode == neg_sat; eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + saturation_current); END USE ; --resistor equation eqn2: v2 == 100.0 * i2; --voltage source equation eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15 ); END behavior ; Bouncing Ball Model ENTITY bouncing_ball IS END ENTITY bouncing_ball; ARCHITECTURE simple OF bouncing_ball IS QUANTITY v: real; QUANTITY s: real; CONSTANT G: real := 9.81; CONSTANT Air_Res: real := 0.1; BEGIN -- specify initial conditions using the break statement b1:BREAK v => 0.0, s => 30.0; b2:BREAK v => -0.7*v WHEN NOT(s'above(0.0)); velocity: v == s'dot ; acceleration: v'dot == -G; END ARCHITECTURE simple; ∑-∆ Modulator BEGIN comp1: compr port map(clk_enable , analog_vin, dac_out); and1: andComp port map(clk_in, clk_enable, enable_count); count1: counter port map(clear, enable_count, counter_op); da_conv: dac port map(counter_op, dac_out, electrical'reference); M-S Simulation Mixed representations of time, synchronization Multiple physical domains Conservative and non-conservative models Solvability, Convergence VHDL-AMS – VHDL 1076.1-1999 Superset of VHDL 1076 Analysis types – transient, noise, small signal frequency Solve Differential Algebraic Equations (DAE) Tolerances, discontinuity handling Language Overview Nature definitions Terminals and Quantities Quantity Attributes – Implicit quantities/signals Mixed-signal interfaces Mixed-signal descriptions of behavior Quantities . . . ARCHITECTURE sinebehavior OF sineSource IS QUANTITY Irsine THROUGH ta2 TO tb2; QUANTITY resistor: REAL; . . . Represents an unknown in the set of DAEs Continuous time waveform Pre-defined attributes create implicit quantities Types of Quantities ENTITY example IS PORT ( PORT QUANTITY interface_q: REAL; QUANTITY TERMINAL elec_p, elec_n: ELECTRICAL); END ENTITY example; BRANCH QUANTITY ARCHITECTURE simple OF example IS QUANTITY v1, v2 ACROSS i1, i2, i3 THROUGH elec_p TO elec_n; FREE QUANTITY QUANTITY free_q: REAL; . . . Terminal ENTITY diode IS . . . PORT ( TERMINAL anode, cathode: ELECTRICAL); END ENTITY diode; Represents a node in an electrical circuit Support for structural composition with conservative semantics Belongs to a NATURE Electrical Systems Environment PACKAGE electrical_system IS SUBTYPE voltage IS REAL TOLERANCE “default_voltage”; SUBTYPE current IS REAL TOLERANCE “default_current”; SUBTYPE charge IS REAL TOLERANCE “default_charge”; NATURE electrical IS voltage ACROSS -- across type current THROUGH -- through type electrical_ref REFERENCE; -- reference type ALIAS ground IS electrical_reference; NATURE electrical_vector IS ARRAY ( NATURAL RANGE <>) OF ELECTRICAL; END PACKAGE electrical_system; Nature Definition Electrical nature in package electrical system Represents a physical discipline/energy domain Each node is of a certain nature Defines the types of quantities incident on the terminal Subnature declaration – different tolerance levels Other nature definitions: thermal, translational, rotational, fluidic, magnetic, etc.. Relation between Elements Terminal Nature Structure Information Type Information Quantity Simultaneous Statement(1) ARCHITECTURE simple OF bouncing_ball IS . . . BEGIN . . . velocity: v == s'dot ; acceleration: v'dot == -G; . . . Expresses relationship between quantities – used by the analog solver May appear anywhere a concurrent statement may appear Simultaneous Statements(2) LHS and RHS – Floating point type One quantity must appear in each simultaneous statement Tolerance group determined by the quantities Other Forms of Simultaneous Statements Simultaneous IF statement Simultaneous CASE statement Simultaneous procedural statement – functions DAE Solvers and Tolerance z z z z DAE – Differential Algebraic Equations Solver – Uses numerical integration to reduce DAE’s to linear/non-linear equations Tolerance – Accept all solutions within a certain amount of variance Necessary to adjust for accuracy of numerical methods Simulation Cycle Analysis Syntax, Semantics Elaboration Flatten out processes & signals Digital/Analog Solver Simulation Sierra – VHDL-AMS Simulator SCRAM Intermediate Representation C++ VHDL-AMS TyVIS/SIERRA PLOTTER Graphical Operation Simulation Operation Analog/DAE Solver SEAMS: Simulation Environment for VHDL-AMS – Frey et al., 1998 Winter Simulation Conference Solvability General Solvability - # of equations equals # of unknown quantities For VHDL-AMS: #(Equations) = #(through quantities) + #(free quantities) + #(interface quantities of mode OUT) Each scalar simultaneous statement creates one equation Sample Solvability Problem ENTITY battery IS ENTITY battery IS PORT ( TERMINAL plus, minus: PORT ( TERMINAL plus, minus: electrical ); electrical ); END ENTITY battery; END ENTITY battery; ARCHITECTURE simple OF battery IS ARCHITECTURE simple OF battery IS CONSTANT v_nominal: REAL := 9.0; CONSTANT v_nominal: REAL := 9.0; QUANTITY v ACROSS plus TO minus; QUANTITY v ACROSS i THROUGH plus TO minus; BEGIN v = = v_nominal; END ARCHITECTURE simple; BEGIN v = = v_nominal; END ARCHITECTURE simple; Solvability – Simultaneous IF Statement ENTITY sfgAmp IS GENERIC ( gain: REAL := REAL’HIGH); PORT (QUANTITY input: IN REAL; QUANTITY output: OUT REAL); END ENTITY sfgAmp; ARCHITECTURE ideal OF sfgAmp IS BEGIN IF gain /= REAL’HIGH USE output = = gain * input; ELSE input = = 0.0; END USE; END ARCHITECTURE ideal; Same # in each USE clause Discontinuities BEGIN -- specify initial b1:BREAK v => 0.0, s => 30.0; b2:BREAK v => -0.7*v WHEN NOT(s'above(0.0)); velocity: v == s'dot ; acceleration: v'dot == -G; END ARCHITECTURE simple; BREAK ! Break Statement Prompts analog solver to reset its state Coincides with a digital event Explicitly say which event – to improve simulation speed Is also employed to specify initial conditions A model not having a BREAK at a discontinuity is erroneous! Predefined Attributes z Implicit signals/quantities created: Quantity Attributes Q’above(E), Q’dot, Q’integ, Q’slew(n1,n2) Frequency domain: Q’ztf( num, den, t, initial_delay), Q’ltf( num, den) z Signal Attributes S’ramp( n1, n2), S’slew( n1, n2) Summary Use VHDL-AMS for your M-S circuits! Some Sources: www.ececs.uc.edu/~dpl : University of Cincinnati www.syssim.ecs.soton.ac.uk: Southampton, UK www.dolphin.fr: Dolphin Systems - Smash www.mentor.com: Mentor Graphics – Advance MS References z z z z The System Designer's Guide to VHDL-AMS – Ashenden et al. Modeling Semicondutor Devices using the VHDL-AMS Language – KasulaSrinivas, MS Thesis, University of Cincinnati, 1998. Introduction to the VHDL-AMS Language – Christen et al., Tutorial Presented at DAC, 1999 VHDL 1076.1 LRM – IEEE Press, 2003 Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers Performance Evaluation using R-Software Introduction ‘R’ statistical software was initially introduced by Ross Ihaka and Robert Gentleman at Department of Statistics of University of Auckland, New Zealand during 1990s Since 1997: international “R-core” team of 15 people collaborated in an effort to make it an open source R is a language and environment for statistical computing and graphics. R provides a wide variety of statistical (linear and nonlinear modelling, classical statistical tests, time-series analysis, classification, clustering, . ...) and graphical techniques, and is highly extensible Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt 2. The R Project for Statistical Computing - http://www.r-project.org/ Highlights of R R is a language and environment for data manipulation, calculation and graphical display:R is similar to the award-winning S system, which was developed at Bell Laboratories by John Chambers et al. a large, coherent, integrated collection of intermediate tools for interactive data analysis, graphical facilities for data analysis and display either directly at the computer or on hardcopy a well developed programming language which includes conditionals, loops, user defined recursive functions and input and output facilities. Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt 2. The R Project for Statistical Computing - http://www.r-project.org/ The core of R is an interpreted computer language:It allows branching and looping as well as modular programming using functions. Most of the user-visible functions in R are written in R, calling upon a smaller set of internal primitives. It is possible for the user to interface to procedures written in C, C++ or FORTRAN languages for efficiency, and also to write additional primitives Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt 2. The R Project for Statistical Computing - http://www.r-project.org/ What R Does & Does Not ? Data handling and storage Not a database, but connects to DBMSs Matrix algebra Hash tables and regular expressions No graphical user interfaces, but connects to Java, TclTk High-level data analytic and statistical functions Language interpreter can be very slow, but allows to call own C/C++ code Graphics No spreadsheet view of data, but connects to Excel/MsOffice Programming language: loops, branching, subroutines No professional / commercial support Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt 2. The R Project for Statistical Computing - http://www.r-project.org/ Data Analysis and Presentation The R distribution contains functionality for large number of statistical procedures. Linear and generalized linear models Nonlinear regression models Time series analysis Classical parametric and nonparametric tests Clustering Smoothing Large set of functions which provide a flexible graphical environment for creating various kinds of data presentations. Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt 2. The R Project for Statistical Computing - http://www.r-project.org/ References z “The New S Language: A Programming Environment for Data Analysis and Graphics” by Richard A. Becker, John M. Chambers and Allan R. Wilks (the “Blue Book”) . z “Statistical Models in S” edited by John M. Chambers and Trevor J. Hastie (the “White Book”) z Internet site (via http://cran.r-project.org). Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt 2. The R Project for Statistical Computing - http://www.r-project.org/ WHAT IS A SYSTEM ? Factors System Inputs SYSTEM Responses Courtesy: Dr. Harold Carter System Outputs Experimental Research Define Define System System Define system outputs first Then define system inputs Finally, define behavior (i.e., transfer function) Identify Identify Factors Factors and and Levels Levels Identify system parameters that vary (many) Reduce parameters to important factors (few) Identify values (i.e., levels) for each factor Identify Identify Response(s) Response(s) Identify time or space effects of interest Design Design Experiments Experiments Identify factor-level experiments Courtesy: Dr. Harold Carter Create and Execute System; Analyze Data Define Define Workload Workload Workloads are inputs that are applied to system Workload can be a factor (but often isn't) Create Create System System Create system so it can be executed Real prototype Simulation model Empirical equations Execute Execute System System Execute system for each factor-level binding Collect and archive response data Analyze Analyze & & Display Display Data Data Courtesy: Dr. Harold Carter Analyze data according to experiment design Evaluate raw and analyzed data for errors Display raw and analyzed data to draw conclusions Examples ANALOG SIMULATION Which of three solvers is best? What is the system? Responses Fastest simulation time Most accurate result Most robust to types of circuits being simulated Factors Solver Type of circuit model Matrix data structure Courtesy: Dr. Harold Carter EPITAXIAL GROWTH New method using nonlinear temp profile What is the system? Responses Total time Quality of layer Total energy required Maximum layer thickness Factors Temperature profile Oxygen density Initial temperature Ambient temperature Generic Model for Network Protocol Data file “latency.dat” Latency 22 23 19 18 15 20 26 17 19 17 Courtesy: Dr. Harold Carter System: wireless network with new protocol Workload: 10 messages applied at single source Each message identical configuration Experiment output Roundtrip latency per message (ms) Data Distribution Box Plot Summary Latency Min. :15.00 1st Qu.:17.25 Median :19.00 Mean :19.60 3rd Qu.:21.50 Max. :26.00 Courtesy: Dr. Harold Carter Scatter Plot Mean: 19.6 ms Variance: 10.71 ms2 Std Dev: 3.27 ms Verify Model Preconditions Check randomness Use plot of residuals around mean Residuals appear random Courtesy: Dr. Harold Carter Check normal distribution Use quantile-quantile plot Pattern adheres consistently along ideal Q-Q line Confidence Intervals Sample mean vs Population mean CI: > 30 samples CI: < 30 samples Courtesy: Dr. Harold Carter Reference: Raj Jain, “The Art of Computer Systems Performance Analysis,” Wiley, 1991. T- Test Analysis t.test (dataset1,conf.level = 0.99) One Sample t-test data: dataset1 t = 18.9382, df = 9, p-value = 1.468e-08 alternative hypothesis: true mean is not equal to 0 99 percent confidence interval: 16.2366 22.9634 sample estimates: mean of x 19.6 Courtesy: Dr. Harold Carter t.test (dataset1,conf.level = 0.95) One Sample t-test data: dataset1 t = 18.9382, df = 9, p-value = 1.468e-08 alternative hypothesis: true mean is not equal to 0 95 percent confidence interval: 17.25879 21.94121 sample estimates: mean of x 19.6 Scatter and Line Plots Regression Plot Depth 1 2 3 4 5 6 7 8 9 10 Resistance 1.689015 4.486722 7.915209 6.362388 11.830739 12.329104 14.011396 17.600094 19.022146 21.513802 Residual Plot Normally Distributed Error Linear Regression Statistics model = lm(Resistance ~ Depth) summary(model) Residuals: Min 1Q Median 3Q Max -2.11330 -0.40679 0.05759 0.51211 1.57310 Coefficients: Estimate Std. Error t value Pr(>|t|) (Intercept) -0.05863 0.76366 -0.077 0.94 Depth 2.13358 0.12308 17.336 1.25e-07 *** --Signif. codes: 0 `***' 0.001 `**' 0.01 `*' 0.05 `.' 0.1 ` ' 1 Residual standard error: 1.118 on 8 degrees of freedom Multiple R-Squared: 0.9741, Adjusted R-squared: 0.9708 F-statistic: 300.5 on 1 and 8 DF, p-value: 1.249e-07 Courtesy: Dr. Harold Carter Comparing Two Sets of Data Example: Consider two wireless different access points. Which one is faster? Inputs: same set of 10 messages communicated through both access points. Approach: Take difference of data and determine CI of difference. If CI straddles zero, cannot tell which access point is faster. Response (usecs): Latency1 Latency2 22 19 23 20 19 24 18 20 15 14 20 18 26 21 17 17 19 17 17 18 Courtesy: Dr. Harold Carter CI95% = (-1.27, 2.87) usecs Confidence interval straddles zero. Thus, cannot determine which is faster with 95% confidence Plots with Error Bars Execution time of SuperLU linear system solution on parallel computer Ax = b For each p, ran problem multiple times with same matrix size but different values Determined mean and CI for each p to obtain curve and error intervals Courtesy: Dr. Harold Carter Statistical Point Analysis Output from Model Mean, Std Dev, Variance, Box Plot Check for Randomness Residual Analysis T-test Analysis Confidence Interval Check for Distribution Q-Q Plot Specification Compare Decision Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers Conclusions Increasing trend towards highly integrated systems, there is an ever growing demand for hardware based on SOC technology Development of these complex components places correspondingly multifarious demands on the design engineer, New CAD and simulation resources are providing system and chip designers with the design tools necessary for integrated CMOS hardware New CAD tools can be used with a standard design methodology to produce mixed technology designs Integrate analog, digital and mixed signal into a single device design that can be fabricated through a conventional CMOS fabrication process Design methodology and new CAD/simulation tools allow the design engineer to focus on the intricacies of mixed mode integrated circuit design (ex noise reduction, signal cross-talk, etc.) without loosing site of chip functionality or system level performance specification Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11 Outline of the Tutorial Motivation Overview Detailed Design Process Simulation with VHDL-AMS Evaluation Process Conclusions Acknowledgements Question and Answers Dr. Carla Purdy Dr. Harold W Carter Dr. Fred R Beyette Jr. Associate Professor Professor and Dept. Head Associate Professor Department of ECECS Department of ECECS Department of ECECS University of Cincinnati University of Cincinnati University of Cincinnati Aaron C. Barnes, M.S Alla S. Kumar L. Ramasamy, M.S Co-Director, Microsurgery Graduate Student Doctoral Researcher Advanced Design Lab Department of ECECS Department of ECECS Doheny Retina Institute University of Cincinnati University of Cincinnati Univ. of Southern California Question and Answers