Germanium FET for Low Power CMOS Technology Th-P.205 Th
Transcription
Germanium FET for Low Power CMOS Technology Th-P.205 Th
Th-P.205 Th-P.205 Negative Capacitance (NC) Germanium FET for Low Power CMOS Technology Yue Peng, Qinglong Li, Genquan Han#, Chunfu Zhang, and Yue Hao State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China # Email: [email protected]; [email protected] We study the ferroelectric material operating in the negative capacitance (NC) region, which could act as a step-up converter of the surface potential in a metal-oxide-semiconductor structure [1,2]. We calculate the ferroelectric dielectric Germanium (Ge) channel field effect transistor (FET) by coupling Pao-Sah double integral with the nonlinear Landau description of the field and polarization of ferroelectric insulator [3]. Fig. 1 shows the schematic diagram of the NC Ge channel FET with BaTiO3 ferroelectric dielectric. The resultant solution for surface potential Φs versus gate voltage Vg relations at the source side is depicted in Fig. 2. Fig. 3 presents the voltage drop across the ferroelectric film Vins as a function of the Vg. Fig. 4 shows the inversion charge density Qi versus the gate voltage Vg and electron-Fermi potential V. From Figs. 2 and 4, it can be clearly seen that surface potential Φs and inversion charge density Qi can be effectively amplified with the using of BiTiO3 material, which would contribute to the steepening of the Ge FET. (b) VG 0.2 CFE COX VS C Csource S 0.1 VD Cdrain Fig. 1 (a) Schematic diagram and (b) capacitance model of the NC-FET. 0.16 0.00 0.4 0.3 0.05 Vins (V) 0.5 Drain 0.20 Fermi potential V: 0.6 Ge Channel Source 2×1015cm-3 0.10 2 Gate 0.7 Qi (C/m ) BaTiO3 Surface Potential s (V) (a) Insulator -0.05 tins: 5 nm 50 nm 200 nm -0.10 -0.15 Fig. 2 surface potential Φs versus gate voltage at the source side. BaTO3 is used as the ferroelectric dielectric. The results show that the hysteresis loops sensitive to the ferroelectric-insulator thickness. 0.1 V 0.3 V 0.12 0.08 0.04 0.0 0.0 0.5 1.0 1.5 2.0 VG - VFB (V) 0V 0.2 V 0.0 0.1 0.2 0.3 0.4 0.00 0.0 VG (V) Fig. 3 Simulation results for Vins-VG relation with an insulator thickness of 50 nm. It is clearly to see that the Vins is negative when the VG varies from zero to 0.35 V. 0.2 0.4 VG (V) Fig. 4 Inversion charge density Qi versus gate voltage VG at a fixed V, which versus from 0 to 0.3 V in steps of 0.1 V. References [1] Sayeef Salahuddin, Supriyo Datta, Nano Lett. 8, 405-410 (2008). [2] Cheng-I Lin, Asif Islam Khan, Sayeef Sayeef Salahuddin, Chenming Hu, Tran. Elec. Device. , 99 1-3 (2015). [3] Han-Ping Chen, Vincent C. Lee, Atsushi Ohoka, Jie Xiang, Yuan Taur, Tran. Elec. Device. 58, 2401-2405 (2011).