ArrowARM Guide - Embedded Developer

Transcription

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FALL2007
ARROW ARM SOLUTIONS GUIDE
ARM Solutions c
www.arrownac.com/arm
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ARM SUPPORT
4
Arrow Services and Solutions
Table of Contents
ARM CORES
8
ARM7TDMI
10 ARM920T
12 ARM926EJ-S
14 ARM966E-S
16 ARM1136J(F)-S
18 ARM Cortex-A8
20 ARM Cortex-M3
It’s a fact. Arrow Electronics is the
only distributor and an approved training
center for ARM tools in North America.
Which means we can solve your
ARM-powered design challenges
efficiently and completely. Our broad
line card features more than a dozen
major silicon suppliers offering ARM
technology and our innovative services
can help you at every point in your
design cycle. Whether you need
support for ARM software development
or architecture, you can rely on Arrow
to deliver up-to-date and accurate
technical information from well-versed
industry experts. Arrow’s vast line card,
services, and unparalleled expertise
deliver comprehensive ARM solutions
that get you to market faster.
22 ARM CortexR4(F)
24 Intel XScale®
ARM SUPPLIERS
28 Atmel
AT91SAM7 | AT91SAM9
32 Freescale
i.MX27 | i.MX31
36 Intel®
Intel® Network Processors and Intel® Storage Processors
38 Luminary Micro
Stellaris® Family
42 NXP
LPC210x | LPC23xx and LPC24xx | LPC2478
48 STMicroelectronics
STM32, STR7 and STR9 Families | STM32 | STR710F |
STR750F | STR910FA | STR730F
60 Texas Instruments
DaVinci™
62 Windows Embedded
WindowsCE
TOOLS
66 IAR
IAR Embedded Workbench Version 4.41 for ARM
68 Keil
The Keil RealView Microcontroller Development Kit
71 ARM
RealView Tools by ARM
Arrow Electronics ARM Solutions
1-866-910-3650
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ARM Support from Concept through Production
Arrow solves your ARM challenges through outstanding technical support, training, and seminars designed to address your
specific ARM requirements. We’re here to help you navigate at every point in the design cycle.
Engineering Expertise—the Right Team
for the Job c
Arrow’s Field Applications Engineers (FAEs) provide expert
support for all your design requirements, no matter where you
are located. Our FAEs undergo monthly ARM training and
constantly deliver the latest technical overviews of ARM
technologies, so you can rest assured the information you
receive is accurate, up-to-date, and relevant.
The Industry’s ARM Training Center
c
Arrow is the “go-to source” for ARM training. It’s an
approved ARM training center in North America and the
only distributor for ARM tools. You can turn to us for relevant
technical information conveyed by seasoned
trainers because our team draws from the
world’s largest and most experienced pool
of ARM technology experts. Our field
trainers provide multi-day classes that
dive deep into ARM architectures and
surrounding development tools. These
classes can be conducted at any Arrow
branch or customer location and give you access to quality
technical training available only from Arrow and ARM.
To register or for more information, go to
www.arrownac.com/arm.
Arrow Technical Solutions Forum (ATSF):
ARM Seminar Series for High-End
Applications
ARM technology is widely used in high-performance applications
that require the most from
a processor yet need to
maintain a low power profile.
This seminar series is aimed
at applications that utilize media, complex user interfaces, and
computational-intensive applications on large data segments.
The higher end of the industrial, medical, transportation,
and other commercial markets is addressed, providing you
with valuable, effective solutions. For more information,
visit www.arrownac.com/atsf.
EmbeddedDeveloper.com
c
Finding the right ARM solution has never been easier.
With EmbeddedDeveloper.com, you can search ARM
devices by core type, peripheral sets, price, and many
other specifications. Compare and contrast device functions,
download specifications and datasheets, and even go to
the Arrow shopping
cart and buy the best
development tool
FIND. COMPARE. BUY.
solution on-line.
For information on Arrow’s ARM training and seminars, visit www.arrownac.com/arm or call 1-866-910-3650.
1-866-910-3650
c
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Innovative Arrow Services
Access to comprehensive ARM offerings and leading suppliers is complemented by Arrow services that go far beyond
getting you the components you need. Our engineering services, on-line development tool selection process, complimentary
development tool evaluation program, supply chain solutions, and custom logic solutions ensure the success of your design
from concept to production.
Arrow Consulting Engineering Services
c
The Arrow Consulting Engineering Services (ACES) program
puts you in touch with pre-screened, qualified, and certified
third-party solutions and design
services companies so you can
save time, effort, and resources.
The superior core competencies
of our partners allow them to
provide complete outsourced
designs—while allowing you to
focus on your core competency.
Supply Chain Solutions
For decades, Arrow has successfully managed one of the most
complex supply chains in the world, allowing us to offer
unmatched insight and expertise. Our services, which include
collaborative material planning tools, vendor managed inventory
programs, performance analysis services, materials management
programs, and electronic communication services, can support
your needs throughout a product’s entire lifecycle—from the
technical discovery stage to design and prototype development,
and through production and product end of life.
Custom Logic Solutions
Arrowdevtools.com
c
Find the best reference designs and evaluation tool solutions
with arrowdevtools.com—an on-line development tool selection
and purchasing
process that gives you
access to a vast range
of development tools.
This proprietary
parametric search engine allows you to narrow your tool search
quickly and intuitively to the unique tool you need to keep your
development on track. Browse and compare different solutions
and then conveniently and confidently purchase your tool for
immediate delivery from arrowdevtools.com on-line or through
Arrow’s sales team. Arrowdevtools.com offers everything you
need to move your project rapidly to completion.
TestdriveSM
c
c
Arrow’s Custom Logic Solutions group has partnered with
industry leaders to meet your custom logic needs with the
right combination of vendor technology, design services, and
intellectual property.
Solutions range from
small FPGAs to
structured ASICs, to
highly complex standard cell ASICs. More than 130 local
engineers and over 20 factory Custom Logic Solutions
engineers, as well as integrated staff from Arrow’s network of
design services partners, provide comprehensive design services that help you get to market quickly with the right product at
the lowest possible risk and cost. Custom Logic Solutions also
extends engineering support into the IP space, enabling you
to piece together complex SOCs (Systems On A Chip) without
having to be “experts at everything.”
c
Arrow’s Testdrive tool evaluation program helps you save time
and money on your designs. The program allows you to try tools
before you buy them, free of charge for 21 days. You can test a
vast selection of tools
from all the major
semiconductor suppliers
without impacting your
budget. Additionally,
Arrow’s Field Applications Engineers are familiar with the tools
offered through Testdrive and can work through any issues that
may arise, saving you precious resources and giving you access
to some of the industry’s leading expertise.
Global Programming Services
c
More and more companies are relying on programmable
devices to improve performance, simplify design, reduce chip
count, and ease manufacturing. To help you keep up with
constant advances in technology, Arrow has developed Global
Programming Services to support procurement and the actual
programming of your devices. Our services can give you greater
levels of scheduling flexibility, reduce internal coordination and
tracking, and avoid cost on capital equipment and staffing, to
get you to market faster.
For information on Arrow’s Innovative Services, visit www.arrownac.com/arm or call 1-866-910-3650.
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ARM7TDMI and ARM7TDMI-S
ARM 32-Bit RISC Core with 16-Bit System Costs
The ARM7TDMI core is the industry’s most widely used 32-bit embedded RISC microprocessor. The ARM7TDMI-S is a
synthesizable version of the ARM7TDMI. Optimized for cost- and power-sensitive applications, the ARM7TDMI solution
provides the low power consumption, small size, and high performance needed in portable, embedded applications.
The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best
combination of performance, power, and area characteristics. The ARM7TDMI core enables system designers to build
embedded devices requiring small size, low power, and high performance.
The ARM7 family also includes the ARM7TDMI processor, the ARM7TDMI-S processor, the ARM720T processor, and the
ARM7EJ-S processor, each of which has been developed to address different market requirements.
RISC Advantages
c
The ARM architecture is based on the Reduced Instruction Set
Computer (RISC) principles. The RISC instruction set and
related decode mechanism are much simpler than those of the
Complex Instruction Set Computer (CISC) designs. This
simplicity has the following advantages:
ETM Interface
Control
logic
EmbeddedICE-RT
logic
Thumb
decoder
• A high instruction throughput
• An excellent real-time interrupt response
The Instruction Pipeline
c
• The instruction pipeline
• Memory access
• Memory interface
• EmbeddedICE
The Instruction Pipeline
ARM7TDMI-S
• A small, cost-effective, processor macrocell
32-bit
ALU
High-performance
multiplier
Bus Interface Unit
Coprocessor
Interface
c
The ARM7TDMI core uses a pipeline to increase the speed of
the flow of instructions to the processor. This allows several
operations to take place simultaneously.
A three-stage pipeline is used, so instructions are executed in
three stages:
• Fetch (the instruction is fetched from memory)
• Decode (decoding of registers used in the instruction)
Memory Access
c
The ARM7TDMI core has a Von Neumann architecture with a
single 32-bit data bus carrying both instructions and data. Only
load, store, and swap instructions can access data from memory. This simplifies the internal logic of the processor memory
interface using less die area.
• Execute (register/s read from register bank; shift and ALU
operations; write register/s back to register bank)
Memory Interface
During normal operation, while one instruction is being executed,
its successor is being decoded and a third instruction is being
fetched from memory.
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c
The ARM7TDMI processor memory interface has been designed
to allow performance potential to be realized while minimizing the
use of memory. Speed-critical control signals are pipelined to
allow system control functions to be implemented in standard
low-power logic. These control signals facilitate the exploitation
of fast-burst access modes supported by many on-chip and
off-chip memory technologies.
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EmbeddedICE-RT Logic
c
The EmbeddedICE-RT logic provides integrated on-chip debug
support for the ARM7TDMI core. You use the EmbeddedICE-RT
logic to program the conditions under which a breakpoint or
watchpoint can occur.
On execution, 16-bit Thumb instructions are transparently
decompressed to full 32-bit ARM instructions in real time
without performance loss.
Applications c
The EmbeddedICE-RT logic contains a Debug Communications
Channel (DCC), which is used to pass information between the
target and the host debugger. The EmbeddedICE-RT logic is
controlled through the Joint Test Action Group (JTAG) test
access port.
• Industrial
• Automotive
• Personal audio (MP3, WMA, and AAC players)
Features c
Architecture c
The ARM7TDMI processor has two instruction sets:
• The 32-bit ARM instruction set
• The 16-bit Thumb® instruction set
Having both 32-bit ARM instructions and 16-bit Thumb instructions gives the ARM7TDMI processor two advantages: instruction compression and higher performance over typical 16-bit
architectures.
Microprocessor architectures traditionally have the same
width for instructions and data. In comparison with 16-bit
architectures, 32-bit architectures exhibit higher performance
when manipulating 32-bit data and can access a large address
space much more efficiently.
Typically, 16-bit architectures have higher code density than
32-bit architectures, but they have approximately half the
performance.
The Thumb instructions implement a 16-bit instruction set on a
32-bit architecture to provide:
• Higher performance than a 16-bit architecture
• Higher code density than a 32-bit architecture
The Thumb instruction set is a subset of the most commonly
used 32-bit ARM instructions. Thumb instructions are each
16 bits long and have a corresponding 32-bit ARM instruction.
This has the same effect on the processor model. Thumb
instructions operate with the standard ARM register
configuration, allowing excellent interoperability between
ARM and Thumb states.
• 32-/16-bit RISC architecture (ARM v4T)
• 32-bit ARM instruction set for maximum performance
and flexibility
• 16-bit Thumb instruction set for increased code density
• Unified bus interface; 32-bit data bus carries both
instructions and data
• Three-stage pipeline
• 32-bit ALU
• Very small die size and low power consumption
• Fully static operation
• Coprocessor interface
• Extensive debug facilities:
– EmbeddedICE-RT real-time debug unit
– JTAG interface unit
– Interface for direct connection to Embedded Trace
Macrocell (ETM)
Benefits c
• Generic layout can be ported to specific process
technologies
• ARM and Thumb instruction sets can be mixed with
minimal overhead to support application requirements for
speed and code density
• Small die size reduces overall SoC area, cost, and power
consumption
• EmbeddedICE-RT and optional ETM units enable
extensive, real-time debug facilities
Performance Characteristics c
Frequency* (MHz)
Area (mm2 )
Power** (mW/MHz)
0.18 µm
Speed Optimized
115
0.59
0.21
0.13 µm
Speed Optimized
133
0.26
0.06
0.090 µm
Speed Optimized
236
0.18
–
*Worst-case conditions—0.18 µm process—1.62V, 125°C, slow silicon; 0.13 µm process—1.08V, 125°C, slow silicon; 90 nm process—0.9V, 125°C, slow silicon
**Typical-case conditions—0.18 µm process—1.8V, 25°C, typical silicon; 0.13 µm process—1.2V, 25°C, typical silicon; 90 nm process—1V, 25°C, typical silicon
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ARM920T
High-Performance and Low-Power Platform OS
The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of
fetch, decode, execute, memory, and write stages. It can be provided as a standalone core that can be embedded into
more complex devices. The standalone core has a simple bus interface that allows you to design your own caches and
memory systems around it.
The ARM920T processor is a member of the ARM9TDMI family of general-purpose microprocessors, which includes:
• ARM9TDMI (core)
• ARM940T (core plus cache and protection unit)
• ARM920T (core plus cache and MMU)
ARM920T Application Support Features
c
The ARM9TDMI family of microprocessors supports both the
32-bit ARM and 16-bit Thumb® instruction sets, allowing you
to trade off between high performance and high code density.
The ARM920T processor supports the ARM debug architecture
and includes logic to assist in both hardware and software
debug. The ARM920T processor also includes support for
coprocessors, exporting the instruction and data buses along
with simple handshaking signals.
The ARM920T’s interface to the rest of the system is over
unified address and data buses. This interface enables
implementation of an Advanced Microcontroller Bus Architecture
(AMBA), an Advanced System Bus (ASB), or an Advanced
High-performance Bus (AHB) scheme either as a fully compliant
AMBA bus master, or as a slave for production test. The
ARM920T processor also has a Tracking ICE mode, which
allows an approach similar to a conventional ICE mode of
operation.
The ARM920T processor supports the addition of an
Embedded Trace Macrocell (ETM) for real-time tracing of
instructions and data.
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16K
Instruction
cache
16K
Data
cache
ARM9TDMI
core
MMU
ARM920T
The ARM920T processor is a Harvard cache architecture
processor that is targeted at multi-programmer applications
where full memory management, high performance, and low
power are all-important. The separate instruction and data
caches in this design are 16 KB each in size, with an eight-word
line length. The ARM920T processor implements an enhanced
ARM architecture v4 MMU to provide translation and access
permission checks for instruction and data addresses.
ETM Interface
MMU
Write buffer
Control Logic and Bus Interface Unit
Coprocessor
Interface
AMBA AHB Interface
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Applications
c
• Automotive infotainment
• Industrial connectivity
• Medical handheld
• Platform OS-based devices
• MMU which supports operating systems including
Symbian OS, Windows CE, Linux, and Palm OS
• Instruction and data caches: ARM920T = 16 K/16 K,
ARM922T = 8 K/8 K
• Industry-standard AMBA bus interface
• ETM interface for real-time trace capability with ETM9
• Next-generation smart phones,
communicators, and PDA’s
• 3G baseband and applications processor
Benefits
c
• Runs all major OS’s and existing middleware
• Digital still camera
• Audio and video decoding
• Single development toolkit for reduced development
costs and shorter development cycle time
• Set-top box
• Multiple sourcing from industry-leading silicon vendors
Features
• Code-compatible upward migration path to ARM10E
family
c
• 32-/16-bit RISC architecture (ARMv4T)
• Excellent debug support for SoC designers
and flexibility
• Instruction set can be extended by the use of
coprocessors
Frequency* (MHz)
Area with cache (mm2)
Cache size
Power with cache** (mW/MHz)
0.18 µM
Speed Optimized
190-200
11.80
16K/16K
0.80
0.13 µM
Speed Optimized
230-250
4.70
16K/16K
0.25
*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon
**Typical-case conditions—0.18 µm process–1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon
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ARM926EJ-S
ARM926EJ-S Jazelle-Enhanced Macrocell Processor
The ARM926EJ-S™ fully synthesizable processor features a Jazelle-enhanced 32-bit RISC CPU, flexible size
instruction and data caches, Tightly Coupled Memory (TCM) interfaces, and a Memory Management Unit (MMU).
It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for multi-layer AHB-based
systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit
multiplier, capable of single-cycle MAC operations. The instruction set includes 16-bit fixed-point DSP instructions to
enhance performance of many signal processing algorithms and applications as well as supports Thumb® and Java byte
code execution.
The ARM926EJ-S processor is a member of the ARM9 family of
general-purpose microprocessors. The processor is targeted at
multi-tasking applications where full memory management, high
performance, small die size, and low power are all important.
The ARM926EJ-S processor supports the ARM debug
architecture and includes logic to assist in both hardware
and software debug. The processor has a Harvard cached
architecture and provides a complete high-performance
processor subsystem, including:
• An ARM9EJ-S integer core
• An MMU
Instruction
TCM interface
Instruction
cache
Data
TCM interface
Data
cache
ARM9EJ-S
core
MMU
ARM926EJ-S
The processor supports the 32-bit ARM and 16-bit Thumb
instruction sets, enabling the user to trade off between high
performance and high code density. The ARM926EJ-S
processor includes features for efficient execution of Java byte
codes, providing Java performance similar to JIT, but without
the associated code overhead.
ETM9 Interface
MMU
Write buffer
Coprocessor
Interface
AMBA AHB interface
Instruction
Data
• Separate instruction and data AMBA AHB bus interfaces
• Separate instruction and data TCM interfaces
The ARM926EJ-S processor provides support for external
coprocessors, enabling the addition of other floating-point or
other application-specific hardware acceleration. The processor
implements ARM architecture version 5TEJ.
The ARM926EJ-S processor is a synthesizable macrocell. This
means that you can optimize the macrocell for a particular target
library, and you can configure the memory system to suit your
target application. You can individually configure the cache sizes
to be any power of two between 4 KB and 128 KB.
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The tightly coupled instruction and data memories are
instantiated externally to the ARM926EJ-S macrocell, providing
you with the flexibility to optimize the memory subsystem for
performance, power, and particular RAM type. The TCM
interfaces enable non-zero wait-state memory to be attached,
as well as provide a mechanism for supporting DMA.
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Applications
Benefits
c
c
• Automotive infotainment
• Runs all major OS’s and existing middleware
• Audio and video decoding
• Single-chip MCU, DSP, and Java solution
• Platform OS-based devices
• Support for leading Java run-times
• Next-generation smart phones, communicators,
and PDAs
• High-efficiency Java bytecode execution
• Ultra-low Java power consumption
• 3G baseband and applications processor
• Java JIT compiler performance without the
disadvantages
• Digital still camera
• Jazelle support code has no increase in VM size
Features
• 32/16-bit RISC architecture (ARMv5TEJ)
• Simple single-processor software structure, no need
for software partitioning across MCUs
• 32-bit ARM instruction set for maximum
performance and flexibility
• Single development toolkit for reduced development
• DSP instruction extensions and single-cycle MAC
• Code-compatible upward migration path through to
the latest cortex family of processors
c
• ARM Jazelle technology
• Process portable synthesizable design
• MMU which supports operating systems including
Symbian OS, Windows CE, and Linux
• Flexible instruction and data cache sizes
coprocessors
• Instruction and data TCM interfaces with
wait-state support
• EmbeddedICE-RT logic for real-time debug
• ARM-EDA Reference Methodology deliverables
significantly reduce the time to generate a specific
technology implementation of the core and to generate
industry-standard views and models
• Industry-standard AMBA bus AHB interfaces
• Optional MOVE coprocessor delivers video encoding
performance
Standard cells
Memories
Frequency* (MHz)
Area with cache (mm2 )
Area without cache (mm2 )
Cache size
Power without cache** (mW/MHz)
0.18 µM
Speed Optimized
SAGE-X
HSHD
200
6.5
3
8K/8K
–
–
0.13 µM
Speed Optimized
SAGE-HS
HSHD
276
2.78
1.61
8K/8K
–
–
90 nm
Area Optimized
SAGE-X
HSHD
238
2.39
1.45
8K/8K
0.48
0.36
Speed Optimized
Advantage-HS
Advantage
500
1.55
1.05
8K/8K
0.29
0.24
Area Optimized
Metro
Metro
250
0.85
0.50
8K/8K
0.14
0.11
*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon
**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon
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ARM966E-S
Embedded Core with Flexible Memory System and DSP Instruction Set Extensions
The ARM966E-S processor is targeted at a wide range of embedded applications where high performance, low system
cost, small die size, and low power are all important. The ARM966E-S macrocell is a fully synthesizable 32-bit RISC
processor aimed specifically at embedded hard real-time applications. The core implements the ARMv5TE instruction
set and features an enhanced 16 x 32-bit multiplier capable of single-cycle MAC operations, and 16-bit fixed point DSP
instructions to accelerate signal processing algorithms and applications.
The ARM966E-S processor provides a high-performance
processor subsystem that includes the ARM9E-S RISC integer
CPU core featuring:
• ARMv5TE 32-bit instruction set with improved
ARM/Thumb code inter-working and enhanced
multiplier designed for improved DSP performance
• ARM debug architecture with additional support for
real-time debug; this enables critical exception handlers
to execute while debugging the system
• Support for external TCM; a TCM interface is provided
for each of the external instruction and data memory
blocks; the TCM interfaces of the ARM966E-S processor
enable high-speed operation without incurring the
performance and power penalties of accessing the
system bus, while having a lower area overhead than a
cached memory system; the size of both the Instruction
and Data TCM blocks are implementor-specific to enable
tailoring of the hardware to the embedded application
• A simple fixed memory map for the local TCM, ideal
for real-time embedded control applications
ETM Interface
Instruction
TCM interface
ARM966E-S
The ARM966E-S processor has separate, directly connected
instruction and data Tightly Coupled Memory (TCM), which
have flexible sizes and run at the processor clock speed. The
ARM966E-S processor supports ARM’s real-time trace
technology with the optional ETM9 Embedded Trace Macrocell.
The ARM966E-S features a simple memory map providing an
area and power-efficient solution for applications that do not
require complex memory management support. The core
includes an AMBA AHB™ interface and a coprocessor
interface for connection to application acceleration hardware
such as the VFP9-S floating-point coprocessor.
ARM9E
core
Data
TCM interface
Write buffer
Coprocessor
Interface
AMBA AHB interface
• An AMBA AHB bus interface
• Support for external coprocessors enabling floatingpoint or other application-specific hardware acceleration
to be added
• Support for the use of a scan test methodology for
the standard-cell logic and Built-In-Self-Test (BIST)
for the TCM
Providing this complete high-frequency subsystem frees the SoC
designer to concentrate on design issues unique to their system;
the synthesizable nature of the device eases integration into
ASIC technologies.
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Applications
Benefits
c
c
• Automotive control: Powertrain with VFP9-S coprocessor
• Single-chip MCU and DSP solution
• Industrial control
• Deterministic performance from TCM memories
• Mass storage devices: hard disc drives and DVD drives
• Simple single-processor software structure; no need
for software partitioning across MCUs and eliminates
multi-MCU debugging
• Networking systems
• Wireless devices
• Single development toolkit: reduced development
• Digital still cameras
• Optimized for hard real-time applications
Features
c
• 32-/16-bit RISC architecture (ARMv5TE)
• Code-compatible upward migration path to
ARM10E family
and flexibility
coprocessors
• Tightly Coupled Memories (TCMs)
• EmbeddedICE-RT logic for real-time debug
• Floating point capability with VFP9-S coprocessor
• ARM-EDA Reference Methodology deliverables
significantly reduce the time to generate a specific
technology implementation of the core and to generate
industry-standard views and models
• ARM-Synopsys Reference Methodology compliant
deliverables
• Optional MOVE coprocessor delivers video encoding
performance
Core area, frequency range, and power consumption are
dependent on process, libraries, and optimizations. The
numbers quoted above are illustrative of synthesized cores
using general-purpose TSMC process technologies and
ARM Artisan standard-cell libraries and RAMs.
The speed-optimized implementations refer to the library
choices and synthesis flow decisions and tradeoffs made
in order to achieve the target frequency performance. The
area-optimized implementations refer to the library choices
and synthesis flow decisions and tradeoffs made in order to
achieve a target area density.
Standard cells
Frequency* (MHz)
Area (mm2)
Power** (mW/MHz)
0.18 µM
Speed Optimized
NA
200
2
0.70
0.13 µM
Speed Optimized
NA
250
1
0.25
90 nm
Speed Optimized
Advantage-HS
500
0.70
0.15
Area Optimized
Metro
250
0.35
0.07
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ARM1136J(F)-S
A High-Performance, Low-Power Processor with DSP and Media Extensions
The award-winning ARM1136J-S™ and ARM1136JF-S™ processors deliver up to 660 Dhrystone 2.1 MIPS in a 0.13 µm
process. Both processors feature the ARM v6 instruction set with media extensions, ARM Jazelle® technology for efficient
embedded Java execution, ARM Thumb® code compression, and an optional floating-point coprocessor. Media processing
extensions offer up to 1.9x the acceleration of media-processing tasks such as MPEG4 encode.
Instruction and data cache sizes are configurable, and optional Tightly Coupled Memories (TCMs) can be added to
accelerate interrupt handling and data processing. These processors feature AMBA® 2.0 AHB™ interfaces compatible
with a wide range of system IP and peripherals. The ARM1136JF-S processor also features an integrated floating-point
coprocessor, which makes it particularly suitable for embedded 3D-graphics applications.
The ARM1136JF-S processor incorporates an integer unit that
implements the ARM architecture v6. It supports the ARM and
Thumb instruction sets, Jazelle technology to enable direct
execution of Java bytecodes, and a range of SIMD DSP
instructions that operate on 16-bit or 8-bit data values in
32-bit registers.
Debug
Interface
The ARM1136JF-S processor is a high-performance, low-power,
ARM cached processor macrocell that provides full virtual memory capabilities.
Instruction
Cache
Features
c
• An integer unit with integral EmbeddedICE-RT logic
• An eight-stage pipeline
• Branch prediction with return stack
• Low-interrupt latency
• External coprocessor interface and coprocessors
14 and 15
M 1 1 3 6 J (F)AARRM
F - SS
TCRAM
VFP
Coprocessor
Controller
ARM1136J-S
core
Data
Cache
TCRAM
Memory Management
Instruction
Interface
Data
Interface
DMA
Peripheral
Port
• Instruction and Data Memory Management Units (MMUs),
managed using MicroTLB structures backed by a unified
Main TLB
• Instruction and data caches, including a non-blocking
data cache with Hit-Under-Miss (HUM)
• The caches are virtually indexed and physically
addressed, and have a 64-bit interface to both caches
• Level-one TCM that can be used as a local RAM with
DMA, or as SmartCache
• High-speed Advanced Microprocessor Bus Architecture
(AMBA) level two
• Vector Floating-Point (VFP) coprocessor support
In addition to the ARM1136J-S, ARM introduced a version that
includes a VFP coprocessor. This is designated as the
ARM1136JF-S.
1-866-910-3650
Core
c
The ARM1136JF-S processor is built around the ARM11 core
in an ARMv6 implementation that runs the 32-bit ARM, 16-bit
Thumb, and 8-bit Jazelle instruction sets. The processor contains
EmbeddedICE-RT logic and a JTAG debug interface to enable
hardware debuggers to communicate with the processor.
Registers
c
The ARM1136JF-S core contains:
• 31 general-purpose 32-bit registers
• Seven dedicated 32-bit registers
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Thumb Instruction Set
c
Thumb is an extension to the ARM architecture. It contains a
subset of the most commonly used 32-bit ARM instructions that
has been encoded into 16-bit wide opcodes, to reduce memory
requirements.
Memory System
c
The core provides a level-one memory system with
the following features:
• Separate instruction and data caches
• Separate instruction and data RAMs
DSP Instructions
c
The ARM DSP instruction set extensions provide the following:
• 16-bit data operations
• Saturating arithmetic
• 64-bit datapaths throughout the memory system
• Complete memory management
• 32-bit dedicated peripheral interface
• MAC operations
Applications
Multiply instructions are processed using a single-cycle 32x16
implementation. There are 32x32, 32x16, and 16x16 multiply
instructions (MAC).
• Automotive infotainment: in-car entertainment, DVD
players, and navigation equipment
Media Extensions
c
• Networking: control processors in network infrastructure,
switch, and router products
c
The ARMv6 instruction set provides media instructions to complement the DSP instructions. The media instructions are divided
into the following main groups:
• Additional multiplication instructions for handling 16-bit
and 32-bit data, including dual-multiplication instructions
that operate on both 16-bit halves of the source
registers; this group includes an instruction that improves
the performance and size of code for multi-word
unsigned multiplications
• Instructions to perform Single Instruction Multiple Data
(SIMD) operations on pairs of 16-bit values held in a
single register, or on quadruplets of 8-bit values held in a
single register; the main operations supplied are addition
and subtraction, selection, pack, and saturation
• Consumer: digital TVs, set-top boxes, game consoles,
and handheld digital media players
using general-purpose TSMC process technologies and
ARM Artisan standard-cell libraries and RAMs.
choices and synthesis flow decisions and tradeoffs made
in order to achieve the target frequency performance. The
The cache sizes are specified as InstructionCache/DataCache.
The area without cache numbers quoted exclude RAM area,
but include all logic including memory management, cache
control, and debug. The area with cache numbers quoted
includes the core, the specified instruction and data caches,
and all necessary RAMs.
90 nm
Standard cells
Memories
Frequency* (MHz)
Area with cache (mm2 )
Cache size
Power** with cache (mW/MHz)
Power** without cache (mW/MHz)
Speed Optimized
Advantage-HS
Advantage
620
2.50
1.80
16K/16K
0.45
0.37
Area Optimized
Metro
Metro
320
1.55
0.90
16K/16K
0.24
0.18
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ARM Cortex-A8
Processors for Complex OS and User Applications
The ARM Cortex™-A8 processor is the first applications processor based on the ARMv7 architecture and is the highest
performance, most power-efficient processor ever developed by ARM. With the ability to scale in speed from 600 MHz to
greater than 1 GHz, the ARM Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing
operation in less than 300 mW and performance-optimized consumer applications requiring 2000 Dhrystone MIPS.
The ARM Cortex-A8 processor is ARM’s first superscalar processor featuring technology for enhanced code density and
performance, NEON™ technology for multimedia and signal processing, and Jazelle® RCT (Runtime Compilation Target)
technology for efficient support of ahead-of-time and just-in-time compilation of Java and other bytecode languages.
The exceptional speed and power efficiency of the Cortex-A8
processor is enabled by new ARM Artisan® Advantage-CE
libraries supporting and implementing advanced leakage control.
DFT/Test
The processor is supported by a wide range of ARM
technologies for rapid system design including:
Debug
IFetch
ETM
IDecode
IExecute
Load store
®
• The RealView DEVELOP family of software
development tools
• The RealView CREATE family of ESL tools and models
• CoreSight™ debug and trace technology as well
as software library support through the OpenMAX
multimedia processing standard
• AMBA® 3 AXI high-performance SoC interconnect
L1
cache
interface
I-side
L1
RAM
The ARM Cortex-A8 processor’s sophisticated pipeline
architecture is based on dual, symmetric, in-order issue,
13-stage pipeline with advanced dynamic branch prediction
achieving 2.0 DMIPS/MHz.
• The in-order, dual-issue, superscalar microprocessor
core includes:
– 13-stage main integer pipeline
– 10-stage NEON media pipeline
– Dedicated Level 2 (L2) cache with programmable
wait states
– Global-history-based branch prediction
• The processor works in conjunction with a
power-optimized load store pipeline to deliver 2.0
DMIPS/MHz for power-sensitive applications
1-866-910-3650
Dependency
check and
issue
ALU1
Flags
RegBank
Load
store
ALU2
L1 cache
interface
D-side
L1
RAM
MAC
C O R T E X ™- A 8
c
Decode &
sequencer
TLB
Level 2
cache
Architectural Features
Prefetch
and
branch
prediction
TLB
Instruction and Data DMA arbitration
NEON
instruction
queue
L2 cache and preload engine
L2 cache
data RAM
Write
buffer
Decode
control
Issue and
forward
control
NEON
Floating
Point
Fill and eviction queue
BIU
NEON unit
L2 cache
tag RAM
NEON load
data queue
NEON
Load
Store
NEON
RegBank
VFPLite
NEON
Integer
AXI
• The ARM Cortex-A8 is ARMv7 architecture-compliant
and includes:
– Thumb®-2 technology for greater performance, energy
efficiency, and code density
– NEON signal processing extensions to accelerate
media codecs such as H.264 and MP3
– Jazelle RCT Java-acceleration technology to optimize
Just In Time (JIT) and Dynamic Adaptive Compilation
(DAC), and to reduce memory footprint by up to
three times
– TrustZone technology for secure transactions and
Digital Rights Management (DRM)
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• Integrated L2 Cache:
– Built using standard compiled RAMs
– Configurable size from 64 K-2 MB
– Programmable delay
• Optimized Level 1 (L1) Cache:
– Performance- and power-optimized
– Combines minimal access latency with hash way
determination to maximize performance and minimize
power consumption
• Dynamic Branch Prediction:
– Enabled by branch target and global-history buffers
– Achieves 95% accuracy across industry benchmarks
– Replay mechanism minimizes miss-predict penalty
• Memory System:
– Single-cycle load-use penalty for access to
the L1 cache
– Hash array in the L1 cache limits activation of the
memories to when they are likely to be needed
– Direct interface between the integrated, configurable
L2 cache and the NEON media unit for data streaming
– Banked L2 cache design that enables only one bank
at a time
– Support for multiple outstanding transactions to the
Level 3 (L3) memory to fully utilize the CPU
Frequency* (MHz)
Area without cache (mm2)
65 nm
Speed Optimized
600-800
<4
<3
< 0.5
*Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan
standard-cell libraries and RAMs.
Area is for core only (excluding NEON, Trace technology, and L2 cache). Frequency and power are for mobile applications. Frequency for consumer applications = 1 GHz. The speed-optimized implementations refer to the library choices and synthesis
flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.
**The 65 nm (LP) dynamic power measured is at 1.2V nominal and, hence, is higher than the 65 nm (GP) dynamic power, which is at 1.0V. However, the 65 nm (LP) leakage is significantly lower and this is the major consideration for mobile or
battery-operated devices that need to conserve power in standby mode.
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ARM Cortex-M3
Processors Optimized for Cost-Sensitive and Deeply-Embedded Applications
The ARM CortexTM-M3 processor has been developed to provide a high-performance, low-cost platform that meets the
needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor executes purely Thumb®-2 instructions, delivering the high performance
expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a
few kilobytes of memory for microcontroller class applications.
In addition to minimizing its memory requirement, the ARM
Cortex-M3 processor is also the smallest 32-bit core designed
by ARM at just 33k gates for the central processing core
(CM3Core) and 60k gates total, including many close system
peripherals. This design reduces silicon area requirements even
further, enabling the smallest of packages or the manufacturing
of devices on low-cost processes, such as 0.35 µM and
0.25 µM.
Outstanding Performance
ETM
ARM core
Memory
protection unit
DAP
Cortex-M3
The ARM Cortex-M3 processor also reduces the number of pins
required for debug from five to one, by implementing a new
debug interface technology—Single Wire Debug—that can
replace the current multi-pin JTAG port.
Configurable
NVIC
Data
watchpoints
Serial wire
viewer
Flash
patch
Bus Matrix
Code
interface
SRAM &
peripheral I/F
c
In addition to unparalleled performance, power consumption,
and memory utilization, the ARM Cortex-M3 processor also
achieves exceptional interrupt handling. By implementing the
register manipulations required for handling an interrupt in
hardware, this core achieves minimal clock overhead on
entering interrupts, and switches between pending or higher
priority interrupts in only six cycles. The design, which comes
with 32 interrupt channels as standard, can be configured to
between 1 and over 240 channels.
The ARM Cortex-M3 processor also includes an optional
Memory Protection Unit (MPU) to provide a privileged mode
of operation for complex applications.
Enabling Technology
c
The ARM Cortex-M3 processor has been designed “from
the ground up” to provide optimal performance and power
consumption within a minimal memory system. To achieve this,
the core executes only the Thumb-2 instruction set, which
delivers an unparalleled combination of ARM instruction set
performance with industry-leading code density. The design,
which is based on a three-stage pipeline Harvard architecture,
also maximizes memory utilization through the support of
unaligned date storage, and single-cycle atomic bit manipulation.
The exceptional performance of the ARM Cortex-M3 processor
is achieved through a highly revised architecture that also
implements many new technologies in this type of core, such
as hardware divide and single-cycle multiply.
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Benefits
using general-purpose TSMC process technologies and ARM
Artisan® standard-cell libraries and RAMs. Area numbers include
the CM3Core, the Nested Vectored Interrupt Controller (NVIC),
and Bus Matrix, but not the optional components including the
Memory Protection Unit, Embedded Trace Macrocell, Breakpoint
Unit, Data Watchpoint Unit, and Trace Port Interface Unit.
c
The ARM Cortex-M3 processor offers significant benefits
to system and software developers.
• Lower cost devices through smaller processing
core, system, and memories
• Ultra-low power consumption and integrated
sleep modes
• Outstanding processing performance for challenging
applications
choices and synthesis flow decisions and tradeoffs made in
order to achieve the target frequency performance. The
• Fast interrupt handling for critical control applications
• Platform security with optional integrated memory
protection unit
• Enhanced system debug for faster development
• No assembler code requirement to ease system
development
• Wide application envelope encompassing
ultra-low-cost microcontrollers and
high-performance SoC
0.18 µM
Standard cells
Frequency* (MHz)
Area (mm2 )
Power** (mW/MHz)
Speed Optimized
SAGE-X
100
0.86
0.19
0.13 µM
Area Optimized
Metro
50
0.70
0.14
Speed Optimized
SAGE-X
135
0.39
0.12
Area Optimized
Metro
50
0.30
0.09
*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon
**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon
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ARM Cortex-R4(F)
Embedded Processors for Real-Time Applications
The ARM Cortex™-R4 processor is the first deeply embedded processor to be based on the ARMv7 architecture and
is targeted at very high-volume, deeply embedded applications such as hard-disk drives, inkjet printers, and automotive
safety systems.
The ARM Cortex-R4 processor provides key savings in cost and power consumption for system developers, offering
substantially higher performance than any other processor with similar die size. Along with the ARM1156T2-S and ARM
Cortex-M3 processors, the ARM Cortex-R4 processor completes comprehensive coverage for the diverse needs of the
embedded microprocessor market. Furthermore, the ARM Cortex-R4 processor supports substantial synthesis time
configurability that enables designers to match the processor precisely to the application requirements.
The ARM Cortex-R4 processor is capable of running at clock
speeds of up to 400 MHz on typical 90 nm processes, and the
focus throughout the design is on efficiency and configurability.
Technical Innovations
Debug
Interface
Prefetch
& Branch
Prediction
Unit
VIC Port
ETM Interface
TCM
Arbiter
and
Interface
core
FPU
C o r t e x - R 4 (F)
F
In addition to the ARM Cortex-R4, ARM has introduced the
ARM Cortex-R4F, which contains a Floating Point Unit (FPU).
The ARM Cortex-R4F processor’s FPU performs floating-point
calculations that allow a greater dynamic range and accuracy
than fixed-point calculations. The FPU is backward compatible
with earlier ARM FPUs (VFP9/10/11), and is optimized for the
single-precision processing most commonly used in automotive
and control applications. The FPU is particularly useful in
sophisticated control applications, where algorithms are often
modeled in an environment such as Simulink or ASCET-SD,
and code is auto-generated using tools such as Real Time
Workshop Embedded Coder, ASCET-SE, or dSPACE
Targetlink.
Instruction
Cache
Memory
Protection
Unit FP exec 1 Data
Cache
AXI Master Interface
AXI Slave Interface
c
®
• Thumb -2 technology; an innovation that has enabled
partners to combine the minimal memory footprint of
16-bit Thumb code with the high performance of 32-bit
ARM code
• AMBA 3 AXI protocol; a set of major enhancements to
AMBA for high-performance on-chip interconnect, the
ARM Cortex-R4 processor integrates a 64-bit master port
as well as a 64-bit DMA port for direct access to the
Tightly Coupled Memories (TCM)
• A selective superscalar eight-stage pipeline that
provides more than 1.6 DMIPS/MHz in an efficient low
gate count implementation
• Non-Maskable Interrupts (NMI); many real-time
applications demand this and the ARM Cortex-R4
supports a configurable NMI pin
• CoreSight™ technology; a framework for complete
system debug and trace; this includes the ETM-R4
embedded trace macrocell and many other CoreSight
components
• A significantly improved local memory architecture
for TCM and DMA; TCM can now be unified into a
single logical address space and can run as fast as
cache memory
• Enhancements over the ARMv6 architecture include
improvements in interrupt handling and the memory
protection scheme; new instructions for managing
interrupts reduce the critical early-interrupt handler code,
and the worst-case interrupt latency is vastly improved to
only 20 clock cycles
• Performance monitoring support; very useful for refining
and tuning a system through advanced profiling of the
system performance
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• Architected support for parity in the caches and parity or
ECC in the TCMs; soft errors are an increasing concern in
embedded systems and either parity or ECC is now
essential in many systems
• Either one, two, or three TCM ports can be included
• A very efficient branch prediction and prefetch unit
provide a branch accuracy of more than 90% for
typical C code
• Dynamic Branch Prediction
- Enabled by branch target, global-history buffers,
and a function called return stack
- Achieves 90% accuracy across industry benchmarks
• The overall aim of the ARM Cortex-R4 processor is to
provide around 40% more efficiency than the ARM9
family whilst increasing the maximum clock speed,
supporting the use of low-power, dense RAMs for
cache and TCMs, and delivering an efficient
Thumb-2 engine
• A number of breakpoints and watchpoints can
be selected
• Single-cycle load-use penalty for access to the L1 cache
and TCM
• A single 64-bit AXI master port for easy integration into
the SoC interconnect
• An AXI slave port to allow direct access to TCMs by DMA
controllers and other processors in the system
Architectural Features
c
The ARM Cortex-R4 processor’s sophisticated pipeline
architecture is based on low-cost dual-issue pipeline, eight
stages with advanced dynamic branch prediction achieving
1.6 DMIPS/MHz; the ARM Cortex-R4 processor is fully ARMv7
architecture-compliant and includes:
• Thumb-2 technology for greater performance, energy
efficiency, and code density
• Hardware divide instructions for control applications
• Optimized level-one caches and TCM
• Synthesis optional cache controllers (with optional cache
parity) and TCM ports for flexibility
• Full wait and error support on TCM interfaces
• Flexible configuration at synthesis time of major
level-one features
• A Memory Protection Unit (MPU) can be removed or an
eight- or 12-region one selected
• Vectored Interrupt Controller (VIC) port for fast
connection to interrupt management peripherals
using general-purpose TSMC process technologies and ARM
Artisan standard cell libraries and RAMs.
choices and synthesis flow decisions and tradeoffs made in
order to achieve the target frequency performance. The
The cache sizes are specified as InstructionCache/DataCache.
The area without cache numbers quoted exclude RAM area,
but include all logic including memory management, cache
control, and debug. The area with cache numbers quoted
includes the core, the specified instruction and data caches
and all necessary RAMs.
Standard cells
Memories
Frequency* (MHz)
Cache size
Power** with cache (mW/MHz)
Power** without cache (mW/MHz)
0.13 µM
Area Optimized
SAGE-HS
HS
300
3.35
1.99
16K/16K
–
–
90 nm
Speed Optimized
Advantage-HS
Advantage
500
2.50
1.66
16K/16K
0.41
0.33
Area Optimized
Metro
Metro
210
1.50
0.80
16K/16K
0.22
0.16
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Intel XScale®
Designed to Enable High Performance, Low Power Consumption, and Systems Integration
The Intel XScale® core is based on an ARM processor family second-generation core and consists of innovative
custom circuits, a proprietary design, and proprietary process techniques. This unique core enables processors in the
Intel XScale® family to operate on very low current while in run and low-power modes.
Designed to enable high performance, low power consumption, and systems integration, the Intel XScale® core
empowers OEMs to develop smaller, more cost-effective, handheld devices with longer battery life, while providing the
performance to run MIPS-intensive multimedia applications such as audio encode/decode, video compression, and speech.
The Intel XScale® microarchitecture extends to set-top boxes, networking, intelligent I/O, and remote-access servers.
This unique processor engine design affords a substantial leadership position in the handheld device market segment
where high performance, low power, and integration-per-cost-effectiveness are all critical factors.
The Intel XScale® core targets the portable information device
segment, which consists of feature-rich handheld devices such
as (but not limited to) the following:
• Vertical application devices
• Palm-size devices
• Smart phones/3G+ multimedia phones
• PC companions
The processor is also packaged in a “smaller footprint, lower
cost” version focused on handheld and portable applications,
and a “higher performance” version for the PC companion and
vertical application device segments. In addition to handheld
segments, the Intel XScale® core also provides a market entry
to tethered applications such as screen phones, low-end
set-top boxes, web terminals, and other Internet appliances.
Features and Benefits of Intel XScale®
Microarchitecture c
• Superpipelined RISC technology achieves high speed
and ultra-low power with a seven-stage integer/eightstage memory superpipelined core
• Dynamic voltage management obtains the right blend
of performance and power with dynamic voltage and
frequency scaling “on the fly”
• Media processing technology achieves efficient media
processing with a multiply-accumulate coprocessor that
performs two simultaneous 16-bit SIMD multiplies with
40-bit accumulation
• Power management unit saves power with idle, sleep,
and quick wake-up modes
• 128-entry branch target buffer maintains pipeline
capacity with statistically correct branch choices
• 32 KB instruction cache achieves high performance and
low power consumption levels by keeping a local copy of
important instructions
• 2 KB data cache avoids “thrashing” of the data cache for
frequently changing data streams
• 32-entry instruction memory management unit enables
logical-to-physical address translation, access
permissions, and instruction-cache attributes
• Four entry fill and pend buffers obtain core efficiency by
allowing non-blocking and “hit-under-miss” operation
with data caches
• Performance monitoring unit analyzes hit rates with two
32-bit event counters and one 32-bit cycle counter
• Debug unit debugs programs with hardware
breakpoints and a 256-entry trace-history buffer
(for flow change messages)
• 32-bit coprocessor interface achieves a
high-performance interface between the core
and coprocessors
• 64-bit core memory bus with simultaneous 32-bit input
path and 32-bit output path obtains up to 4.8 GBytes/sec
@ 600 MHz bandwidth for internal accesses
• Eight-entry write buffer provides continuous core
execution while data is written to memory
• The Thumb instruction set supported selects the
16-bit Thumb instruction set from the current program
status register
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ARM Architecture Compatibility
c
The Intel XScale microarchitecture implements the integer
instruction set architecture specified in ARM Version 5TE.
“T” refers to the Thumb instruction set, and “E” refers to the
DSP-enhanced instruction set.
®
ARM Version 5 introduces a few more architecture features over
Version 4, specifically the addition of tiny pages (1 Kbyte), a new
instruction (CLZ) that counts the leading zeroes in a data value,
enhanced ARM-Thumb transfer instructions, and a modification
of the system-control coprocessor, CP15.
ARM DSP-Enhanced Instruction Set
c
The Intel XScale® microarchitecture implements the ARM
DSP-enhanced instruction set, which is a set of instructions
that boosts the performance of signal-processing applications.
New multiply instructions operate on 16-bit data values, and
new saturation instructions are available as well (see below).
• SMLAxy instruction is a 16x16+32 with a 32-bit result
• SMLAWy instruction is a 32x16+32 with a 32-bit result
• SMLALxy instruction is a 16x16+64 with a 64-bit result
• Additional functionality has been added to coprocessor
15; coprocessor 14 also added
• Enhancements were made to the event architecture,
instruction cache, and data-cache parity
DSP Coprocessor 0 (CP0)
c
The Intel XScale microarchitecture adds a DSP coprocessor
to the architecture for increasing the performance and the
precision of audio-processing algorithms. This coprocessor
contains a 40-bit accumulator and eight new instructions.
®
The 40-bit accumulator is referenced by several new instructions
that were added to the architecture; MIA, MIAPH, and MIAxy
are multiply/accumulate instructions that reference the 40-bit
accumulator instead of a register-specified accumulator. MAR
and MRA read and write the 40-bit accumulator.
Access to CP0 is always allowed in all processor modes when
bit 0 of the coprocessor access register is set. Any access to
CP0 when this bit is clear will cause an undefined exception.
Note that only privileged software can set this bit in the
coprocessor access register. Two new instruction formats
were added for coprocessor 0: multiply with internal
accumulate format, and internal accumulate access format.
• SMULxy instruction is a 16x16 with a 32-bit result
• SMULWy instruction is a 32x16 with a 32-bit result
Branch Prediction
• QADD adds two registers and saturates the result if an
overflow has occurred
• QDADD doubles and saturates one of the input registers
and then adds and saturates the result
• QSUB subtracts two registers and saturates the result if
an overflow has occurred
• QDSUB doubles and saturates one of the input registers
and then subtracts and saturates the result
Extensions to ARM Architecture
c
The Intel XScale® microarchitecture includes a few extensions to
the ARM Version 5 architecture to meet the needs of various
markets and design requirements. The following is a list of the
extensions that are discussed in the next subsections.
c
The Intel XScale microarchitecture implements dynamic
branch prediction for the ARM instructions B and BL, and for
the Thumb instruction, B. Any instruction that specifies the
PC as the destination is predicted as “not taken.” For example,
an LDR or an MOV that loads or moves directly to the PC will
be predicted “not taken” and incur a branch-latency penalty.
®
These instructions (ARM B, ARM BL, and Thumb B) enter into
the branch target buffer when they are “taken” for the first time.
(A “taken” branch refers to when they are evaluated to be true.)
Once in the branch target buffer, the Intel XScale®
microarchitecture dynamically predicts the outcome of these
instructions based on previous outcomes. A penalty of “zero”
for correct prediction means that the Intel XScale®
microarchitecture can execute the next instruction in the
program flow in the cycle following the branch.
• A DSP coprocessor (CP0) has been added that contains
a 40-bit accumulator and eight new instructions
Power Management
• New page attributes were added to the page table
descriptors; the C- and B-page attribute encoding
was extended by one additional bit to allow for
more encodings: write-allocate and mini-data
cache; an attribute specifying ECC for 1 MB regions
was also added
The Intel XScale microarchitecture defines three low-power
modes: idle, drowsy, and sleep. All state information is lost on
entering sleep mode. The only way to exit sleep mode is through
the reset sequence. State is retained in idle and drowsy modes.
Both idle and drowsy modes are exited by interrupt, even if the
interrupt is masked. A single coprocessor 14 register write is
used to enter any low-power mode.
c
®
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28 |
AT91SAM7 32-bit ARM-based Microcontrollers
Core: ARM7TDMI
The AT91SAM7 family of Flash microcontrollers are based on the 32-bit ARM7TDMI
RISC processor. They feature from 32Kbytes to 512Kbytes of embedded high-speed
Flash with sector lock capabilities and a security bit, and from 8Kbytes to 64Kbytes
of SRAM. The integrated proprietary SAM-BA Boot Assistant enables in-system
programming of the embedded Flash.
Its extensive peripheral set includes a USB 2.0 Full Speed Device Port, USARTs, SPI, SSC, TWI and an 8-channel 10-bit
ADC. Its Peripheral DMA Controller channels eliminate processor bottlenecks during peripheral-to-memory transfers. Its
System Controller manages interrupts, clocks, power, time, debug and reset, significantly reducing the external chip count
and minimizing power consumption.
The maximum Clock frequency is 55MHZ, in industrial temperature range and under the worse case conditions. Typical
core supply is 1.8V, I/Os are supplied at 1.8V or 3.3V and are 5V tolerant. An integrated Voltage Regulator permits single
supply at 3.3V. It is supported by an Evaluation Board and extensive application development tools.
AT91SAM7SE family expands on the AT91SAMS family with external memory bus. The External Bus Interface (EBI)
supports SDRAM and static memories including CompactFlash and ECC-enabled NAND Flash. Making it particularly
suited to applications requiring high performance, USB connectivity and extended on- and off-chip memory.
AT91SAM7X family adds integrated Ethernet, USB and CAN interface. Its extensive peripheral set includes a USB 2.0
Full Speed Device Port, Ethernet MAC 10/100 base T, CAN 2.0A and 2.0B compliant Controller, USARTs, SPI, SSC,
TWI and an 8-channel 10-bit ADC. Its Peripheral DMA Controller channels eliminate processor bottlenecks during
peripheral-to-memory transfers. Its System Controller manages interrupts, clocks, power, time, debug and reset,
significantly reducing the external chip count and minimizing power consumption.
AT91SAM7XC family adds integrated Ethernet, USB and CAN interface, and security features. Its extensive peripheral
set includes a USB 2.0 Full Speed Device Port, Ethernet MAC 10/100 base T, CAN 2.0A and 2.0B compliant Controller,
an AES128 encryption accelerator, a Triple DES, USARTs, SPI, SSC, TWI and an 8-channel 10-bit ADC. Its Peripheral
DMA Controller channels eliminate processor bottlenecks during peripheral-to-memory transfers. Its System Controller
manages interrupts, clocks, power, time, debug and reset, significantly reducing the external chip count and minimizing
power consumption.
Features
c
• Proven architecture based on ten years experience in ARM-based
standard products
• Predictable response to a real-time event within a specified number
of clock cycles
• Peripheral DMA eliminates bottlenecks in
memory-to-peripheral transfers
• Advanced interrupt control enhances real-time performance
• Single-instruction bit set/reset simplifies application code
• Embedded Flash memory for flexible code and reference
data storage
• Connectivity: USB, Ethernet, SPI, USART, etc.
• Security: AES/TDES accelerators, memory lock bits, etc.
1-866-910-3650
AT91SAM7
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Part
Number
Total
Flash
Total
RAM
Temp. °C
Package
Type
Core
Variant ID
Max
Frequency
A/D
Bits
A/D
Timer Timer
Channels Channels Bits
Serial Interface
Description
GPIO
Ethernet
USB
Peripherals
AT91SAM7A3
256
32
-40 to +85
LQFP 100
ARM7TDMI
60
10
16
9
16
2xSPI, 2xSSC, TWI
62
–
Device 2.0
–
AT91SAM7S256
256
64
-40 to +85
LQFP 64
ARM7TDMI
55
10
8
3
16
SPI, 2USART, UART, SSC. TWI
32
–
Device 2.0
–
AT91SAM7S128
128
32
-40 to +85
LQFP 64
ARM7TDMI
55
10
8
3
16
SPI, 2xUSART, UART, SSC. TWI
32
–
Device 2.0
–
AT91SAM7S64
64
16
-40 to +85
LQFP 64
ARM7TDMI
55
10
8
3
16
SPI, SSC. TWI
32
–
Device 2.0
–
AT91SAM7S32
32
8
-40 to +85
LQFP 48
ARM7TDMI
55
10
8
2
16
SPI, SSC. TWI
21
–
–
–
AT91SAM7S321
32
8
-40 to +85
LQFP 64
ARM7TDMI
55
10
8
3
16
SPI, SSC. TWI
32
–
Device 2.0
–
AT91SAM7SE512
512
32
-40 to +85
LQFP128, 144LFBGA
ARM7TDMI
48
10
8
3
16
SPI, SSC, 2xUSART, TWI
88
–
Device 2.0
–
AT91SAM7SE256
256
32
-40 to +85
LQFP128, 144LFBGA
ARM7TDMI
48
10
8
3
16
88
–
Device 2.0
–
AT91SAM7SE32
32
8
-40 to +85
LQFP128, 144LFBGA
ARM7TDMI
48
10
8
3
16
88
–
Device 2.0
–
AT91SAM7X256
256
64
-40 to +85
LQFP 100
ARM7TDMI
55
10
8
3
16
2xSPI, 2xUSART, UART, SSC. TWI
60
MAC 10/100
Device 2.0
–
AT91SAM7X128
128
32
-40 to +85
LQFP 100
ARM7TDMI
55
10
8
3
16
2xSPI, 2xUSART, UART, SSC. TWI
60
MAC 10/100
Device 2.0
–
AT91SAM7XC256
256
64
-40 to +85
LQFP 100
ARM7TDMI
55
10
8
3
16
2xSPI, SSC. TWI
60
MAC 10/100
Device 2.0
–
AT91SAM7XC128
128
32
-40 to +85
LQFP 100
ARM7TDMI
55
10
8
3
16
2xSPI, SSC. TWI
60
MAC 10/100
Device 2.0
–
Development Tools Matrix c
Tool Name
Description
Part Number
AT91SAM7S-EK
The AT91SAM7S-EK Evaluation Kit enables the evaluation of and code development for applications running on AT91SAM7S devices
AT91SAM7S-EK
AT91SAM7SE-EK
The AT91SAM7SE-EK Evaluation Kit enables the evaluation of and code development for applications running on AT91SAM7SE devices
AT91SAM7SE-EK
AT91SAM7X-EK
The AT91SAM7X-EK Evaluation Kit enables the evaluation of and code development for applications running on AT91SAM7X devices; contains crypto hardware - export restrictions apply
AT91SAM7X-EK
AT91SAM-ICE
CE is a JTAG emulator designed for all Atmel AT91 ARM7 cores
AT91SAM-ICE
AT91SAM7X-EK Development Board
For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650.
To research and compare and contrast ARM solutions, visit www.embedded-developer.com.
AT91SAM7 Family of Microcontrollers | ATMEL
ARM7 | Cortex-M3 | ARM9 | Cortex-R4 | XScale | ARM11 | Cortex-A8
Family Comparative Features c
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AT91SAM9 32-bit ARM-based Microcontrollers
Core: ARM926EJ-S
The AT91SAM9 family is a pin-compatible ARM926EJ-S-based microcontroller family
that shares the same programming model as ARM7-based controllers, allowing direct
migration between controllers based on different ARM cores.
AT91SAM9260 operates at 210MIPS with a 190MHz clock. It features 8Kbytes of
SRAM and 32K bytes of ROM with single cycle access at maximum processor or bus speed, together with an external bus
interface with controllers for SDRAM and static memories including NAND Flash and CompactFlash. Its extensive peripheral
set includes USB Full Speed Host and Device interfaces, a 10/100 Ethernet MAC, Image Sensor Interface, Multimedia Card
Interface (MCI), Synchronous Serial Controllers (SSC), USARTs, Serial Peripheral Interfaces (SPI), a three-channel 16-bit
Timer Counter, a Two Wire Interface (TWI) and four-channel 10-bit ADC and peripheral DMA channels maximize the data
throughput between these interfaces and the on- and off-chip memories.
AT91SAM9261 operates at 210MIPS with a 190MHz clock. It features 160Kbytes of SRAM and 32Kbytes of ROM
with single cycle access at maximum processor or bus speed, together with an External Bus Iinterface (EBI) with
controllers for SDRAM and static memories including NAND Flash and CompactFlash. Its extensive peripheral set
includes USB Full Speed Host and Device interfaces, an LCD Controller, MCI, SSC, USARTs, SPI, a three-channel
16-bit Timer Counter, a TWI and peripheral DMA channels maximize the data throughput between these interfaces
and the on- and off-chip memories.
AT91SAM9263, the newest member of the Atmel’s ARM9 microcontroller family, operates at 220MIPS with a 200MHz
clock. Its parallel bus architecture incorporating distributed DMA overcomes the bottlenecks that occur with conventional
MCUs in graphically-interfaced, data-intensive applications such as networked medical monitoring equipment and GPS
navigation systems. The AT91SAM9263 employs 27 DMA channels including Atmel’s 20-channel peripheral DMA controller
(PDC), a 9-layer bus matrix, and two additional busses for data- and instruction-tightly-coupled-memories to boost CPU
performance and provide on-chip data transfer rates of up to 41.6 Gbps. Two External Bus Interfaces (EBIs) support
gigabyte-plus external memories. On-chip human interface peripherals include a camera interface, TFT/STN LCD controller,
a 6-channel audio front-end interface (AC97), I2S and a 2D graphics co-processor that off-loads line draw, block transfer,
polygon fill, and clipping functions from the CPU. Networking peripherals include a 12 Mbps USB host and device, a 10/100
Ethernet MAC and a 1 Mbps control area network (CAN). There are also four USARTs, two 50 Mbps SPI, CompactFlash,
SDIO (MCI) and a TWI.
Features
c
• Proven architecture based on ten years’ experience in ARM-based
standard products
• Predictable response to a real-time event within a specified number
of clock cycles
• Peripheral DMA eliminates bottlenecks in
memory-to-peripheral transfers
• Advanced interrupt control enhances real-time performance
• Single-instruction bit set/reset simplifies application code
• Connectivity: USB, Ethernet, SPI, USART, LCD, etc.
• Code compatibility across all products
• WinCE, Linux, extensive compiler and application support
from industry-leading third parties
1-866-910-3650
AT91SAM9
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Part
Number
Total Total
Flash RAM
AT91RM9200
0
160
AT91SAM9260
0
4
AT91SAM9261
0
AT91SAM9263
0
Temp. °C
Package
Type
-40 TO +85 BGA256, PQFP208
Core
Variant ID
Timer
Bits
Serial Interface
Description
GPIO
Ethernet
USB
Peripherals
1
Host2.0
Device 2.0
EBI, MCI
180
0
0
6
16
SPI, TWI, 3xSSC,
4xUSART
–
-40 to +85 PQFP208, LFBGA 217 ARM926EJ-S
180
10
4
6
16
2xSPI, 4xUSART,
2xUART, SSC, 2xTWI
96
160
-40 to +85 LFBGA 217 BGA 256 ARM926EJ-S
180
0
0
3
16
SPI, 4xUSART, UART,
3xSSC, TWI
96
–
2xHost 2.0,
Device 2.0
–
80
-40 to +85
200
0
0
2 and 3
32 and 16 2xCAN, 2xMCI, 2xSSC, 160
AC97C, 3xUART, 2xSPI
1
3
LCD, DMA, 2D Graphics, ITU-R BT.601/656
TFBGA324
ARM920T
Max
A/D
A/D
Timer
Frequency Bits Channels Channels
ARM926EJ-S
MAC 10/100 2xHost 2.0,
Device 2.0
–
Tool Name
Description
Part Number
AT91RM9200-EK
The AT91RM200-EK Evaluation Kit supports the AT91RM9200 ARM9-based 32-bit RISC microcontroller and enables real-time code development and evaluation
AT91RM9200-EK
AT91SAM9260-EK
The AT91SAM9260-EK Evaluation Kit enables the evaluation of and code development for applications running on an AT91SAM9260 device
AT91SAM9260-EK
AT91SAM9261-EK
AT91SAM9261-EK
AT91SAM9263-EK
AT91SAM9263-EK
AT91SAM-ICE
SAM-ICE is a JTAG emulator designed for all Atmel AT91 ARM9 cores
AT91SAM-ICE
Each member of the AT91SAM9 family are supported by
Evaluation Boards and extensive third-party application
development tools. These boards support both Linux and
Windows CE. They have been developed for advanced
system-on-chip applications that require both high
computing performance and high data throughputs.
AT91SAM9263-EK Development Kit
AT91SAM9 Family of Microcontrollers | ATMEL
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i.MX27 Multimedia Applications Processors
Core: ARM926EJ-S™
Freescale’s i.MX family of applications processors delivers power to the people who demand
it: designers and users alike who want exceptional performance and long battery life from their
mobile devices. Design engineers capitalize on the amazing performance i.MX processors
achieve at low clock speeds and the high degree of integration to quickly deliver innovative
mobile devices to market. Consumers love the quick response of the user interface, the lifelike
video and audio capabilities and long play times for hours of work and entertainment use.
Freescale gives design engineers the power of choice with various i.MX processors, from the i.MXS for price sensitive
applications, and i.MXL, i.MX21S for mid-range devices, to i.MX21, i.MX27, i.MX31L and i.MX31 for high performance
mobile multimedia devices. By adding LCD control, DMA channels, memory interfaces, several communications units,
security, memory expansion and low operating voltage, the i.MX processors are also prime candidates for both
industrial instrumentation and healthcare-related applications.
i.MX27 is Freescale's highly anticipated and most recent addition to the i.MX family. Optimized for a broad spectrum of
mobile consumer and industrial applications, the i.MX27 processor combines Freescale's Smart Speed™ technology, an
H.264 hardware encoder/decoder, USB, Ethernet, security features and a powerful ARM926EJ-S core. With the addition
of an on-chip Ethernet MAC and the H.264 D1 resolution video codec to the performance-enhancing Smart Speed
architecture, the i.MX27 processor brings an increased level of video, graphics and connectivity to mobile multimedia
devices. The low-power video acceleration and applications software in a single chip gives designers the ability to
increase functionality and decrease power drain and footprint. The ability to capture video and play it back real-time
makes the i.MX27 particularly well-suited for the video and voice over Internet Protocol (V2IP) cordless and mobile
phone markets, and video surveillance.
Features
c
• ARM926EJ-S running at speeds up to 400 MHz
• The 6x3 Smart Speed crossbar switch enables designers to
achieve true parallelism, allowing a rich multimedia experience for
hours and hours on a single battery charge
• MPEG-4 and H.264/H.264 D1 resolution hardware
encoder/decoder with acceleration of image pre- and postprocessing, provides superb image and video quality for V2IP
and video-centric consumer handheld devices
• Proven power management techniques such as Dynamic Process
Temperature Compensation (DPTC) to optimize supply voltage as
a function of operating speed, process speed and temperature, as
well as a variety of different power saving modes to meet the
constraints of system power budget
• Support for 10 and 100 Mbps Ethernet/802.3 connectivity, a new
feature to the i.MX family
• External memory interface with support for multiple types of
memory, including 16/32-bit DDR and SDRAM, and the ability
to boot from 8/16-bit NAND flash
• High-Speed USB-OTG port for connection to a PC plus one
High-Speed USB Host and one Full-Speed USB Host for
interfacing with peripherals such as Wi-Fi® and Bluetooth™
1-866-910-3650
• System connectivity, including CSPIs, I2C, PCMCIA, ATA,
UARTs
• Board support packages for WinCE and Linux operating systems
• Extensive 3rd party ecosystem for hardware and software
tools and services
i.MX27 Block Diagram
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Part
Number
MCIMX27VOP4
Temp °C
Package
-20 to +85 404 MAPBGA 0.65mm
Core
Type
Max
Timer
Frequency Channels
ARM926EJ-S
400MHz
6
Timer
Bits
32
Serial Interface
Description
Expansion
2xI2C, 2xSSI/I2S, 3xCSPI, P-ATA, CF, SD/MMC,
6xUARTS, IR, 1-Wire
Memory Stick Pro
Ethernet
3D Graphics
USB
Peripherals
10/100
–
2.0 HS OTG
+ 2 Hosts
LCDC, H.264/MPEG-4 HW Enc/Dec, Image
Processing, Sensor Port, NAND Flash
Tool Name
Description
Part Number
i.MX27 ADS
Complete hardware development system with power management board and includes QVGA LCD, camera, and software board support packages (WinCE and Linux)
MCIMX27ADSE
i.MX27 LITEKIT
Low-cost development kit for basic evaluation and application development. Peripheral accessories and software available separately
MCIMX27LITEKIT
Example Application
Video and Voice over IP (V2IP)
i.MX27 Multimedia Applications Processors | Freescale Semiconductor
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i.MX31 Multimedia Applications Processors
Core: ARM1136JF-S™
Millions of units shipped and still gaining momentum. Based on an ARM1136JF-S core,
Freescale’s i.MX31 and i.MX31L processors, with speeds up to 532 MHz, a vector floating
point co-processor and L2-cache, are designed for any wireless device running computationally
intensive applications such as automotive entertainment systems, video and audio media
players, mobile gaming consoles and GPS systems, as well as smartphones, PDAs, ultra
portable handheld computers and other wireless mobile devices. The i.MX31 processor
includes leading power management, security management, digital rights management, hardware acceleration to support
2D and 3D graphics acceleration, and image processing technology, a formidable combination of features OEMs desire
to drive high-performance video, audio and 3D gaming content on wireless mobile devices.
In addition, Freescale’s i.MX31 multimedia applications processor is the engine in the Ford Sync™ in-car communications
and entertainment system. Based on Microsoft Auto software, the Sync system is designed to provide consumers the
convenience and flexibility to bring nearly any mobile phone or digital media player into their vehicle and operate it using
voice commands or the vehicle's steering wheel or radio controls. The 400 MHz version of the i.MX31 processor, with its
highly efficient memory system, is designed to provide ample processing power to run the Microsoft operating system,
handle audio signal processing for hands free phone operation, and perform all of the voice recognition functionality in the
Sync system. Additionally, USB connectivity on the i.MX31 chip enables high-speed data transfer between the Sync
system and a mobile phone or portable media device.
Features
c
• ARM1136JF-S CPU complex, running at speeds up to 532 MHz,
with hardware vector floating point unit, 128 KB L2 cache
controller, and Smart Speed switch
• Advanced power management techniques such as Dynamic
Voltage and Frequency Scaling (DVFS) to enable on-the-fly
frequency adjustment to meet the current system performance
requirements. By lowering the frequency it is possible to lower the
operating voltage and dramatically reduce the power consumption.
In addition, DPTC and a wide range of power saving modes help
designers meet their system power budget
• 2D/3D graphics acceleration for interactive console-like gaming
experience, providing support for OpenGL®ES and Java Mobile
3-D support (only available on i.MX31)
• Hardware accelerated VGA MPEG-4 encode for high quality, low
power video record
• Image Processing Unit (IPU) for video pre- and post-processing,
display management, and image re-size and rotation. The IPU
accelerates loop de-blocking for H.264 decode as well as encode,
and enables up to VGA 30fps video quality
• External memory interface with support for multiple types of
memory, including 16/32-bit DDR and SDRAM, and the ability to
boot from 8/16-bit NAND flash
• High-Speed USB-OTG port for connection to a PC plus one
High-Speed USB Host and one Full-Speed USB Host for
interfacing with peripherals such as Wi-Fi® and Bluetooth™
• System connectivity, including CSPIs, I2C, PCMCIA, ATA, UARTs
1-866-910-3650
• Board support packages for WinCE and Linux operating systems
• Extensive 3rd party ecosystem for hardware and software tools
and services
• Available in both 0.5mm and 0.8mm MAPBGA package
i.MX31 Block Diagram
SupplierPgs26-35(2)
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c
• High performance with 32-bit DDR and L2 cache
• Long battery life for mobile applications
• Ability to boot from NAND flash
• MPEG4 playback at 30 fps VGA resolution
• Interactive console-like gaming experience with OpenGL-ES based
graphics acceleration
• On chip LCDC eliminates the need for timing chips when using
certain displays
• Capture, process, and display of moving and still objects
• High level of integration simplifies overall board design and
lowers BOM cost
Part
Number
Temp °C
Package
Core
Type
Max
Timer
Frequency Channels
Timer
Bits
MCIMX31VKN5C
0 to +70
457 MAPBGA 0.5mm
ARM1136JF-S
532MHz
3
32
MCIMX31LVKN5C
0 to +70
457 MAPBGA 0.5mm
ARM1136JF-S
532MHz
3
MCIMX31CVKN5C -40 to +85 457 MAPBGA 0.5mm
ARM1136JF-S
532MHz
MCIMX31LCVKN5C -40 to +85 457 MAPBGA 0.5mm
ARM1136JF-S
MCIMX31VMN5C
0 to +70
457 MAPBGA 0.8mm
MCIMX31LVMN5C
0 to +70
Serial Interface
Description
Expansion
Ethernet
3D Graphics
USB
Peripherals
5xUARTS, FIR, 1-Wire
Memory Stick Pro
–
Integrated
2D/3D Graphics
2.0 HS OTG LCDC, MPEG-4 HW Encoder, Image Processing,
+ 2 Hosts
Sensor Port, NAND Flash
32
Memory Stick Pro
–
–
+ 2 Hosts
3
32
Memory Stick Pro
–
Integrated
2D/3D Graphics
+ 2 Hosts
532MHz
3
32
Memory Stick Pro
–
–
+ 2 Hosts
ARM1136JF-S
532MHz
3
32
Memory Stick Pro
–
Integrated
2D/3D Graphics
+ 2 Hosts
457 MAPBGA 0.5mm
ARM1136JF-S
532MHz
3
32
Memory Stick Pro
–
–
+ 2 Hosts
MCIMX31CVMN4C -40 to +85 457 MAPBGA 0.5mm
ARM1136JF-S
400MHz
3
32
Memory Stick Pro
–
Integrated
2D/3D Graphics
+ 2 Hosts
MCIMX31LCVMN4C -40 to +85 457 MAPBGA 0.5mm
ARM1136JF-S
400MHz
3
32
Memory Stick Pro
–
–
+ 2 Hosts
Tool Name
Description
Part Number
i.MX31 ADS
Complete hardware development system with power management board and includes QVGA LCD, camera, and software board support packages (WinCE and Linux)
MCIMX31ADSE/C
i.MX31 LITEKIT
Low-cost development kit for basic evaluation and application development. Peripheral accessories and software available separately
MCIMX31LITEKIT
i.MX31 Lite Kit
i.MX31 Application Development System
i.MX31 Multimedia Applications Processors | Freescale Semiconductor
Benefits
SuppliersPgs36-41(2)
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36 |
Intel ® Network Processors and Intel ® Storage
Processors
Core: Intel XScale® technology
Intel XScale® technology is available in two families: The Intel® network processors family
and the Intel® I/O processors family of devices. With a single architecture and integrated
design, the Intel® IXP4XX product line of network processors delivers scalable performance,
reduced power, and lower cost in packages optimized for residential and small/medium
enterprise network applications, as well as communications-based embedded applications.
Many storage, networking, and embedded applications require fast I/O throughput for
optimal performance. Intel I/O processors (IOP) allow applications to transfer data faster,
reduce communication bottlenecks, and improve overall system performance.
Features
c
1-866-910-3650
NPE C
MII/SMII
AES, DES
SHA-1/-256/
-384/-512, MO5
MII/SMII
PMU
(AHB)
IEEE
1588
Interrupt
Controller
Queue Flag Bus
Timers
Cryptography Unit
EAI, SHA
Queue Manager
8KB SRAM
HW RNG
DDR1-266
Controller
32-bit +
ECC
Bridge
Memory Port Interface
66.66 MHz Advanced Peripheral Bus
Bridge
133.32 MHz Advanced High-Performance Bus
Bus Interface Unit
UART
921KBaud
UART
921KBaud
GPIO
Controller
I2C
SSP
USB
Device v1.1
USB
PCI
Expansion Bus
Host 2.0** Controller Controller
**USB 2.0 Host supports low-speed (1.5 Mb/s) and full-speed (12 Mb/s) modes.
32-bit +
Parity
133.32 MHz Advanced High-Performance Bus
NPE B
1 MII or
Quad SMII
MII/Quad SMII
32-bit
• Intel’s groundbreaking new microarchitecture provides very high
processor performance with extremely low power consumption;
Intel XScale® technology provides the platform for the most
advanced designs in storage, infrastructure and embedded
communications
• Provides reduced overall system cost as well as ease of
connectivity to industry standard peripherals/devices
• Support for voice applications and connection to industry standard
WAN interface
• Improves performance and reliability
• I/O processors are available in single- or dual-chip configurations
this provides developers with pre-validated component sets,
simplified board designs, and board-space cost savings
• Offloads I/O processing functions, such as I/O interrupt
processing and parity calculations from a host processor; I/O
processors are also excellent general-purpose processors for
high-bandwidth applications that require integrated processors
with low power consumption and high-speed peripherals
• Faster time-to-market and support for multiple tool-chains and
operating systems on the Intel XScale® microarchitecture
HSS-1
c
HSS-0
Benefits
NPEA
MII/SMII
UTOPIA, AAL,
HSS, HDLC
UTOPIA-2/MII/SMII
16 GPIO
• Intel XScale® Microarchitecture running at up to 1200 MHz
• Intel® network processors: Peripherals - USB, up to 3 10/100
Ethernet MACs, PCI, DDR, Expansion Bus, UARTs, I2C, SSP
• Intel® network processors: Advanced Serial Interfaces including
a high speed serial port for connecting to T1/E1 or
SLICs/CODECs; UTOPIA-2 Support;
• Intel® network processors: Integrated support for cryptography,
time synchronization and ECC memory
• Intel I/O processors: Peripherals - PCIe/PCI-X, DDR2,
PBI, UARTs, I2C Optional 8 ports integrated SAS/SATA
Integrated Designs
• Intel I/O processors: I/O Processing Performance
• Comprehensive Set of Development Tools
Intel ® IXP46X Product Line Block Diagram
Intel XScale® Core
266/400/533/667 MHz
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
9/4/07
4:01 PM
Page 2
| 37
Part
Number
Total
RAM
IXP43X
external up to 1 GB
Temp °C Package Core
Max A/D A/D
Timer Timer
Type Variant ID Frequency Bits Channels Channels Bits
Serial Interface
Description
GPIO Ethernet
USB
Peripherals
-0 to +70
PBGA
XScale
667
0
–
4
32 High Speed UART, SSP/SSI, I2C 16
2 x 10/100 2x2.0 HS Host DDR I/II, 32-bit 33 MHz PCI, 16-bit Expansion Bus, UTOPIA 2,
DES/3DES/AES/SHA 1/SHA256/384/512, IEEE 1588
IXP42X external up to 256 MB -40 to +85
PBGA
XScale
533
0
–
4
32
2 High Speed UARTs
16
2 x 10/100 1x1.1 Device
FCBGA5
XScale
800
0
0
3
32
2xI2C
8
80219
external up to 1 GB
IOP331/2 external up to 2 GB
0 to +55
2
–
SDRAM, 32-bit 33 MHz PCI, 16-bit Expansion Bus,
SHA-1/MD5/ES/DES,/AES
–
PCI, DDR
PCI-X/PCIe, DDRII, 266 MHz 64-bit internal bus
0 to +95
FCBGA5
XScale
800
0
–
3
32
2xUARTs, 3xI C
8
–
–
IOP333
external up to 2 GB
0 to +95
FCBGA5
XScale
800
0
–
3
32
2xUARTs, 3xI2C
16
–
–
PCI-X/PCIe, DDRII, 333 MHz 64-bit internal bus
IOP348
external up to 2 GB
0 to +95
FCBGA5
XScale
1200
0
0
3
32
2xUARTs, 3xI2C
16
–
–
PCI-X, PCIe, SAS/SATAII, DDRII, 400 MHz 128-bit internal bus
IOP341/2 external up to 2 GB
0 to +95
FCBGA5
XScale
1200
0
–
3
32
2xUARTs, 3xI2C
16
–
–
PCI-X/PCIe, 1 or two XScale processor cores, DDRII, 400 MHz
128-bit internal bus
PBGA
XScale
667
0
–
4
32
2 High Speed UARTs
16
IXP46X
external up to 1 GB -40 to +85
3 x 10/100 1.1 Device, 2.0 DDR I, 32-bit 33 MHz PCI, 32-bit Expansion Bus, FS Host
SSP/SSI, I2C
UTOPIA 2, DES/3DES/AES/SHA1/ SHA256/384/512, IEEE 1588
Tool Name
Description
Part Number
Intel® IXDP465 Development Platform
Intel® IXDP465 Development Platform, optional T1/E1, Voice, and Ethernet Modules; includes 4 PCI expansion slots, 3 Ethernet ports, USB host and device, 2 UARTS
Intel® IXDP425 / IXCDP1100 Development Platform Intel® IXDP425 / IXCDP1100 Development Platform, Network processor base card with the Intel® IXP425 network processor at 533 MHz, Two Intel® LXT972A LAN PHY expansion cards,
One ADSL PHY expansion card, One voltage regulator expansion card, Two High-Speed Serial (HSS) ports, Two UART (DB-9) connectors, One USB connector, Four PCI bus connectors
KIXDP465AD
KIXDP425BD
Intel® KIXRP435 Development Platform
Intel® KIXRP435 Development Platform Includes 10/100 802.11a/g WLAN, 3x10/100 Ethernet, 2 Wideband FXS + 1 FXO, 2xUSB 2.0, UART, IR, RCA, Audio, Component Video, S-Video KIXRP435 - Hamoa
Intel® IQ80332 Software Development
and Processor Evaluation Kit
Features Intel® 82545EM Gigabit Ethernet Controller, Primary PCI- PCI Express* supports up to x8 lane, Secondary PCI is PCI-X, two UARTs, Two 7-segment hex LED displays in a dPCI
Express form factor
IQ80332
Intel® IQ80219 Development Kit
Intel® IQ80219 Development Kit featuring a primary PCI-X interface 133 MHz/64-bit or PCI 66 MHz/64-bit, Two Intel® 31244 Serial ATA I/O controllers, Intel® BW31154 PCI 133 MHz
transparent bridge,256MB DDR SDRAM with ECC, one PCI-X 64-bit/100 MHz expansion slot
IQ80219.DOM
Intel® EP80219 Development
Intel® EP80219 Development Kit features a 10/100 Ethernet controller, one GD31244 SATA controller, a serial port, and a mini-PCI connector for expansion, RTC, Power control,
and Temp Sensor
Intel® IOP342 I/O Processor
Development Kit (flex ATX)
1200 MHz Intel® IOP342 I/O Processor with two cores, 256 MB DDR2 Memory, 1 MB SRAM, 2 UARTs, 1 PCIe, 1 PCI-X, flex ATX form factor
IQ81342MC.Kit
Development Kit (PCIe HBA)
1200 MHz Intel® IOP342 I/O Processor with two cores, 256 MB DDR2 Memory, 1 MB SRAM, 2 UARTs, 1 PCIe, 1 PCI-X, PCIe HBA form factor
IQ81342SC.Kit
Development Kit (flex ATX)
1200 MHz Intel® IOP348 I/O Processor, 256 MB DDR2 Memory, 2 UARTs, 1 PCIe, 1 PCI-X, flex ATX form factor
IQ81348MC.Kit
Development Kit (PCIe HBA)
1200 MHz Intel® IOP348 I/O Processor, 256 MB DDR2 Memory, 2 UARTs, 1 PCIe, 1 PCI-X, PCIe HBA form factor
IQ81348SC.Kit
EP80219
The IQ81342MC.Kit board features a
1.2GHZ two core Intel® IOP342 I/O
processors processor. This board has
dual UARTs, Dual Gbit Ethernet and a
x8 PCI Express slot and a 64-bit PCI-X
slot for expansion, and fits in a
standard flex-ATX chassis.
Intel, the Intel logo, and Intel XScale are trademarks or registered trademarks of Intel Corporation or
its subsidiaries in the United States and other countries. *Other names and brands may be claimed as
the property of others.
Intel® Network Processors and Intel® Storage Processors | Intel®
9/4/07
4:01 PM
Page 3
38 |
Stellaris® Family
Core: Cortex™-M3
Luminary Micro, Inc. designs, markets, and sells the award-winning Stellaris family of ARM® Cortex™M3-based microcontrollers (MCUs). As ARM's lead partner for Cortex-M3 technology, Luminary Micro
delivers the world's first silicon implementation of the Cortex-M3 processor, providing 32-bit performance at 8-/16-bit cost. Luminary Micro's award-winning Stellaris family of microcontrollers incorporates the Cortex-M3 MCU core running up to 50 MHz. The Stellaris family features peripherals
designed specifically for intense industrial motor control, including motion control PWMs and
quadrature encoder inputs. With every peripheral provided directly to the pins without feature
multiplexing, the Stellaris family is favorably positioned for cost-conscious applications requiring
significant control processing and connectivity capabilities, including motion control, monitoring
(remote, fire/security, etc.), HVAC and building controls, power and energy monitoring and
conversion, network appliances and switches, factory automation, electronic point-of-sale machines,
test and measurement equipment, medical instrumentation, and gaming equipment.
Features
c
• 1.25 DMIPS/MHz—better than ARM7 and ARM9
• Single-cycle flash and single-cycle SRAM accesses for
maximum performance
• Deterministic, fast interrupt processing: always 12 cycles, or just
6 cycles with tail-chaining
• Single-cycle multiply instruction and hardware divide for fast control
algorithm performance
• All GPIOs can generate interrupts, are 5V-tolerant, and have
programmable drive strength and slew rate control
• Advanced motion control support in hardware and software
speeds time to market
• ARM Thumb™-2 mixed 16/32-bit instruction set for compact,
powerful code
• Extra on-chip debug support including data watchpoints and
flash patching
Benefits
c
• Advanced communication capabilities, including 10/100 Ethernet
MAC/PHY and CAN controllers
• Sophisticated motion control support in hardware and software
• Ease of development with the Stellaris Peripheral Driver Library’s
high-level API interface to the entire Stellaris peripheral set
• Requires half the flash (code space) of ARM7 applications
• 2-4 times faster than ARM7, 10x faster than 8051, and 8x faster
than PIC24F on MCU control applications
• Enter an instruction-set-compatible family that ranges from $1 to
1 GHz in the Cortex processor family – never upgrade again
• Cost-effective—utilize 32-bit performance for the same price as
current 8- and 16-bit microcontroller designs
1-866-910-3650
• No functional pin muxing – choose your part by the functions you
need for easy design-in
• No assembly code required – ever
• Real MCU GPIOs—all can generate interrupts, are 5V-tolerant, and
have programmable drive strength and slew rate control
Stellaris® Family Block Diagram
9/4/07
4:01 PM
Page 4
| 39
Part Total Total
Number Flash RAM
Temp. °C
Package
Type
Max.
Frequency
A/D
Bits
A/D
Channels
Timer
Channels
Timer
Bits
Serial Interface
Description
GPIO
Peripherals
LM3S101
8
2
-40 to +85
SOIC28
20
0
0
3
32
UART, SSI
18
1 AnaCmp, 1 CCP Pin, LDO Voltage Regulator
LM3S102
8
2
-40 to +85
SOIC28
20
0
0
3
32
UART, SSI, I2C
18
1 AnaCmp, 2 CCP Pins, LDO Voltage Regulator
LM3S301
16
2
-40 to +85
LQFP48
20
10
3
3
32
UART, SSI
33
2 AnaCmp, 2 PWM Pins, 2 CCP Pins, LDO Voltage Regulator
LM3S310
16
4
-40 to +85
LQFP48
25
0
0
4
32
2xUART, SSI
36
LM3S315
16
4
-40 to +85
LQFP48
25
10
4
4
32
2xUART, SSI
32
LM3S316
16
4
-40 to +85
LQFP48
25
10
4
4
32
2xUART, SSI, I2C
32
LM3S317
16
4
-40 to +85
LQFP48
25
10
6
4
32
UART, SSI
30
LM3S328
16
4
-40 to +85
LQFP48
25
10
8
4
32
2xUART, SSI, I2C
28
6 CCP Pins, LDO Voltage Regulator
LM3S601
32
8
-40 to +85
LQFP48
50
0
0
4
32
2xUART, SSI, I2C
36
3 CCP Pins, Quadrature Encoder, LDO Voltage Regulator
LM3S610
32
8
-40 to +85
LQFP48
50
10
2
4
32
2xUART, SSI, I2C
34
6 PWM Pins, 6 CCP Pins, LDO Voltage Regulator
LM3S611
32
8
-40 to +85
LQFP48
50
10
4
4
32
2xUART, SSI, I2C
32
6 PWM Pins, 6 CCP Pins, LDO Voltage Regulator
LM3S612
32
8
-40 to +85
LQFP48
50
10
2
4
32
2xUART, SSI, I2C
34
LM3S613
32
8
-40 to +85
LQFP48
50
10
4
4
32
2xUART, SSI, I2C
32
LM3S615
32
8
-40 to +85
LQFP48
50
10
2
4
32
2xUART, SSI, I2C
34
LM3S617
32
8
-40 to +85
LQFP48
50
10
6
4
32
2xUART, SSI
30
LM3S618
32
8
-40 to +85
LQFP48
50
10
6
4
32
2xUART, SSI
30
1 AnaCmp, 6 PWM Pins, 4 CCP Pins, Quadrature Encoder, LDO Voltage Regulator
LM3S628
32
8
-40 to +85
LQFP48
50
10
8
4
32
2xUART, SSI, I2C
28
4 CCP Pins, LDO Voltage Regulator
LM3S801
64
8
-40 to +85
LQFP48
50
0
0
4
32
2xUART, SSI, I2C
36
LM3S811
64
8
-40 to +85
LQFP48
50
10
4
4
32
2xUART, SSI, I2C
32
LM3S812
64
8
-40 to +85
LQFP48
50
10
2
4
32
2xUART, SSI, IvC
34
LM3S815
64
8
-40 to +85
LQFP48
50
10
2
4
32
2xUART, SSI, I2C
34
LM3S817
64
8
-40 to +85
LQFP48
50
10
6
4
32
2xUART, SSI
30
LM3S818
64
8
-40 to +85
LQFP48
50
10
6
4
32
2xUART, SSI
30
LM3S828
64
8
-40 to +85
LQFP48
50
10
8
4
32
2xUART, SSI, I2C
28
Part Number
Description
DB-LM3S101
DB-LM3S102
DB-LM3S801
DB-LM3S811
DB-LM3S815
DB-LM3S817
DB-LM3S818
DB-LM3S828
DB-LMS301
DK-LM3S101
DK-LM3S102
DK-LM3S301
DK-LM3S801
DK-LM3S811
DK-LM3S815
DK-LM3S817
DK-LM3S818
DK-LM3S828
EKC-LM3S811
EKI-LM3S811
EKK-LM3S811
IA-LM3S102
RA-LM3S102
Stellaris® Family Daughter Board for LM3S101
Stellaris® Family Daughter Board for LM3S310, LM3S601 and LM3S801
Stellaris® Family Daughter Board for LM3S315, LM3S316, LM3S611, LM3S613, and LM3S811
Stellaris® Family Daughter Board for LM3S610, LM3S612, LM3S615, LM3S615, LM3S812 and LM3S815
Stellaris® Family Daughter Board for LM3S618 and LM3S818
Stellaris® Family Development Kit for LM3S101
Stellaris® Family Development Kit for LM3S310, LM3S601 and LM3S801
Stellaris® Family Development Kit for LM3S315, LM3S316, LM3S611, LM3S613, and LM3S811
Stellaris® Family Development Kit for LM3S610, LM3S612, LM3S615, LM3S615, LM3S812 and LM3S815
Stellaris® Family Development Kit for LM3S317, LM3S617, and LM3S817
Stellaris® Family Development Kit for LM3S618, and LM3S818
Stellaris® Family Development Kit for LM3S328, LM3S628 and LM3S828
Stellaris® LM3S811 Evaluation Kit for CodeSourcery G++ GNU
Stellaris® LM3S811 Evaluation Kit for IAR Systems Embedded Workbench®
Stellaris® LM3S811 Evaluation Kit for Keil™ RealView® MDK-ARM
IAR Kickstart Kit for Stellaris® LM3S102 Microcontroller
Rowley CrossFire LM3S102 Evaluation Kit
Stellaris LM3S811 Evaluation Kit
Stellaris Family of Microcontrollers | Luminary Micro
9/4/07
4:01 PM
Page 5
40 |
Stellaris® Family
Core: Cortex™-M3
Luminary Micro has extended the award-winning Stellaris Cortex-M3-based microcontroller family
with Ethernet-enabled and CAN-enabled Stellaris devices. These new MCUs augment the worldclass benefits of the Stellaris family with real-time networking, larger on-chip memories, enhanced
power management, and expanded I/O capabilities.
The Stellaris family offers the first MCUs in the world featuring a fully-integrated 10/100 Mbps
Ethernet solution with ARM architecture compatibility. Stellaris Ethernet-enabled devices combine
both the Media Access Control (MAC) and Physical (PHY) layers, and are the only integrated 10/100 Ethernet MAC and
PHY available in an ARM architecture MCU.
Stellaris devices featuring Controller Area Network (CAN) incorporate Bosch CAN networking technology, the golden
standard in short-haul industrial networks.
Features
c
Stellaris Ethernet-enabled MCUs
• Integrated 10/100 Mbps Ethernet MAC and PHY
• Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 full and
half-duplex operation
• Automatic MDI/MDI-X cross-over correction
• Programmable MAC address
• Promiscuous mode support
• Power-saving and power-down modes
• 2KB Transmit FIFO / 2 KB Receive FIFO
• 25-50 MHz operation
• 64-256 KB single-cycle flash and 16-64 KB single-cycle SRAM
• Up to 46 GPIOs
Stellaris CAN-enabled MCUs
• Multiple Bosch-licensed CAN controllers supporting protocol
versions 2.0A & 2.0B
• Bit rates up to 1 Mb/s
• 32 message objects, each with own identifier mask
• Disable automatic retransmission mode for TTCAN
• Programmable loop-back mode for self-test operation
• 25-50 MHz operation
• 64-256 KB single-cycle flash and 16-64 KB single-cycle SRAM
• Up to 60 GPIOs
Benefits
c
• Only integrated Ethernet MAC+PHY available in an ARM
architecture MCU
• CAN controllers are Bosch-licensed; the golden standard in
short-haul industrial networks
1-866-910-3650
• Superior performance though single-cycle flash coupled with
inherently better code efficiency on the ARM Cortex-M3 core.
• Sophisticated Stellaris motion control technology - accelerating
motor design
Stellaris® Family Block Diagram
9/4/07
4:01 PM
Page 6
| 41
c
• Fast, Flexible, Accurate, and Smart analog capability
• Ease of development with the Stellaris Peripheral Driver Library’s
high-level API interface to the entire Stellaris peripheral set
• No functional pin muxing – choose your part by the functions you
need for easy design-in
• No assembly code required – ever!
• Real MCU GPIOs—all can generate interrupts, are 5V-tolerant,
and have programmable drive strength and slew rate control
Part Total Total Temp. °C Package
Max.
A/D
A/D
Timer
Number Flash RAM
Type Frequency Bits Channels Channels
LM3S2110
LM3S2139
LM3S2410
LM3S2412
LM3S2432
LM3S2533
LM3S2620
LM3S2637
LM3S2651
LM3S2730
LM3S2739
LM3S2939
LM3S2948
LM3S2950
LM3S2965
LM3S6100
LM3S6110
LM3S6420
LM3S6422
LM3S6432
LM3S6610
LM3S6633
LM3S6637
LM3S6730
LM3S6938
LM3S6952
LM3S6965
64
64
96
96
96
96
128
128
128
128
128
256
256
256
256
64
64
96
96
96
128
128
128
128
256
256
256
16
16
32
32
32
64
32
32
32
64
64
64
64
64
64
16
16
32
32
32
32
32
32
64
64
64
64
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
LQFP100
25
25
25
25
50
25
50
50
50
50
50
50
50
50
50
25
25
25
25
50
25
50
50
50
50
50
50
0
10
0
10
10
10
0
10
10
0
10
10
10
0
10
0
0
0
10
10
0
10
10
0
10
10
10
0
4
0
3
3
3
0
4
4
0
4
3
8
0
4
0
0
0
2
3
0
3
4
0
8
3
4
4
4
4
4
4
5
5
5
5
4
4
4
5
5
5
4
4
4
4
4
5
4
5
4
5
4
5
Timer
Bits
Ethernet
(#/speed)
CAN
(#)
Serial Interface
Description
GPIO
Peripherals
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1 (10/100 MAC+PHY)
1
1
1
1
1
1
2
1
1
1
1
1
2
2
2
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
UART, SSI, I2C
2xUART, SSI, I2C
UART, SSI, I2C
2xUART, SSI, I2C
2xUART, SSI, I2C
2xUART, SSI, I2C
UART, SSI, I2C
2xUART, SSI, I2C
3xUART, 2xSSI, I2C
UART, SSI, I2C
2xUART, SSI, I2C
3xUART, SSI, I2C
3xUART, 2xSSI, I2C
3xUART, 2xSSI, I2C
3xUART, 2xSSI, 2xI2C
UART, SSI
UART, SSI
UART, SSI
UART, SSI
2xUART, SSI, I2C
3xUART, SSI, I2C
2xUART, SSI, I2C
2xUART, SSI, I2C
UART, SSI
3xUART, SSI, I2C
3xUART, SSI, I2C
3xUART, SSI, 2xI2C
40
56
60
49
34
48
52
46
53
60
56
57
52
60
56
30
35
46
34
43
46
41
41
46
38
43
42
AnaCmp, 4 PWM Pins, 6 CCP Pins, LDO Voltage Regulator
AnaCmp, 6 PWM Pins, 6 CCP Pins, Quadrature Encoder, LDO Voltage Regulator
3 AnaCmp, - PWM Pins, 8 CCP Pins, LDO Voltage Regulator
3 AnaCmp, 6 PWM Pins, 6 CCP Pins, 2 Quadrature Encoder, LDO Voltage Regulator
AnaCmp, 4 CCP Pins, LDO Voltage Regulator
AnaCmp, 6 CCP Pins, LDO Voltage Regulator
2 AnaCmp, 6 PWM Pins, 4 CCP Pins, 2 Quadrature Encoder, LDO Voltage Regulator
Part Number
Description
®
EKC-LM3S6965
Stellaris LM3S6965 Evaluation Kit for CodeSourcery G++ GNU
EKI-LM3S6965
EKK-LM3S6965
EKC-LM3S2965
Stellaris® LM3S2965 Evaluation Kit for CodeSourcery G++ GNU
EKI-LM3S2965
EKK-LM3S2965
Stellaris LM3S2965 CAN Evaluation Kit & Stellaris LM3S6965
Ethernet Evaluation Kit
Stellaris Family of Microcontrollers | Luminary Micro
Benefits cont.
SuppliersPgs42-49
9/4/07
4:14 PM
Page 1
42 |
LPC210x 70 MHz, 32-bit microcontroller with
ARM7TDMI-S
Core: ARM7TDMI-S
These powerful yet cost-effective microcontrollers have up to 32 KB of zero
wait-state Flash and up to 8 KB of SRAM. Each has a 10-bit A/D converter with
eight channels and multiple serial interfaces.
The lowest-priced part, the LPC2101, starts at only USD $1.47 each for 10 Kpcs,
making it an attractive alternative to lower performing 8- or 16-bit MCUs. Blending
high performance (63 Dhrystone MIPs) with low power consumption in a tiny 7 mm x 7 mm LQFP48 package makes the
part ideal for almost any application.
These cost-effective processors are stuffed with a variety of peripherals, including 10-bit ADCs, 4 timers, and multiple
I2C, SPI, and UART interfaces. The series also features several new power-saving modes and fast general-purpose I/O,
allowing more flexibility for designers. The code and peripherals are fully compatible with all of the other members of
the NXP LPC2000 family, which has nearly 40 members and continues to grow.
Features
c
• 70-MHz, 32-bit ARM7 Core Architecture with AHB/APB interfaces
• Up to 32 KB of zero wait-state Flash
• Fast 70 MHz performance at 63 Dhrystone MIPs
• Tiny 7mm x 7mm LQFP packaging
• Stuffed with low-power features and advanced peripherals
• Incredibly low pricing starting at $1.47
Benefits
c
• Ideal upgrade for any application using lower performance
8- or 16-bit MCUs
• Ideal for almost any application
• Design flexibility
1-866-910-3650
LPC210x Block Diagram
SuppliersPgs42-49
9/4/07
4:14 PM
Page 2
| 43
Part
Number
Total
Flash
Total
RAM
Temp. °C
Package
Type
Core
Variant ID
Max
Frequency
A/D
Bits
A/D
Channels
Timer
Channels
Timer
Bits
Serial Interface
Description
GPIO
Ethernet
USB
Peripherals
LPC2101
8
2
-40 to +85
LQFP48
ARM7TDMI-S
70
10
8
7
32
2xUART, SPI, SSP
32
–
–
–
LPC2102
16
4
-40 to +85
LQFP48
ARM7TDMI-S
70
10
8
7
32
2xUART, SPI, SSP
32
–
–
–
LPC2103
32
8
-40 to +85
LQFP48
ARM7TDMI-S
70
10
8
7
32
2xUART, SPI, SSP
32
–
–
–
Tool Name
Description
Part Number
MCB2103 evaluation board from Keil The evaluation board connects to your PC using the serial port (for flash download with the NXP LPC2000 FLASH Utility) or the JTAG interface; it can be powered from a USB connector
(50mA typical) or from a 5V to 9V DC power supply; debugging is supported via the JTAG interface using the Keil ULINK USB-JTAG adapter and the _Vision IDE and Debugger
MCB2103
MCB2103 Keil Evaluation Board
NXP Family of Microcontrollers | NXP
ARM7 | Cortex-M3 | ARM9 | Cortex-R4 | Xscale | ARM11 | Cortex-A8
SuppliersPgs42-49
9/4/07
4:15 PM
Page 3
44 |
LPC23xx and LPC24xx 72 MHz, 32-bit
microcontrollers with ARM7TDMI-S core
Core: ARM7TDMI-S
The LPC23xx and LPC24xx use a high-performance 32-bit ARM7 core that operates
at up to 72 MHz. Each device has 512 KB of on-chip Flash. The LPC23xx offers up
to 58 KB of SRAM, while the LPC24xx offers up to 98 KB of SRAM. Both devices
have two AHB buses, so high-bandwidth peripherals like Ethernet and USB can run
simultaneously, without impacting the main application. The LPC24xx is also the only
ARM7 MCU with two-port USB capability; it has one USB device, and one USB
Host or OTG. This unique ability enables new advances for multiple communications applications by supporting compound (Host + device) USB functionality, such as a USB mini-hub.
Features
c
• On-chip RC-oscillator 4 Mhz trimmed to 1%
• Four 32-bit general purpose timers
• PWM block supporting 3-Phase Motor Control
• Watchdog timer from multiple clock source options
• 10-bit A/D converter and 10-bit D/A converter
• Low-power Real Time Clock with 2 KB SRAM and
battery back-up
• General Purpose DMA controller
• High-speed Serial: I2S (digital Audio), three I2C,
three SPI/SSP, four UARTs
Benefits
c
• Allows fast simultaneous communications operations
• Eliminates communication bandwidth bottlenecks
• Design flexibility
1-866-910-3650
LPC24xx Block Diagram
SuppliersPgs42-49
9/4/07
4:15 PM
Page 4
| 45
Part
Number
Total
Flash
Total
RAM
Temp.°C
Package
Type
Core
Max
Variant ID Frequency
A/D
A/D
Timer Timer
Bits Channels Channels Bits
Serial Interface
Description
GPIO
Ethernet
USB
Peripherals
LPC2468FET208
512
98
-40 to +85
TFBGA208
ARM7TDMI-S
72
10
8
4
32
2xSSP, I2S, 4xUART, 3xI2C
–
10/100
2.0 FS, OTG
2xCAN
LPC2468FBD208
512
98
-40 to +85
LQFP208
ARM7TDMI-S
72
10
8
4
32
2xSSP, I2S, 4xUART, 3xI2C
–
10/100
2.0 FS, OTG
2xCAN
LPC2378FBD144
512
58
-40 to +85
LQFP144
ARM7TDMI-S
72
10
8
4
32
SPI, 2xSSP, I2S, 4xUART, 3xI2C
–
10/100
2.0 FS, OTG
2xCAN
LPC2368FBD100
512
58
-40 to +85
LQFP100
ARM7TDMI-S
72
10
8
4
32
70
10/100
2.0 FS, OTG
2xCAN
LPC2366FBD100
256
58
-40 to +85
LQFP100
ARM7TDMI-S
72
10
8
4
32
70
10/100
2.0 high speed OTG + 2 hosts
2xCAN
LPC2364FBD100
128
34
-40 to +85
LQFP100
ARM7TDMI-S
72
10
8
4
32
70
10/100
2.0 high speed OTG + 2 hosts
2xCAN
Tool Name
Description
Part Number
Keil MCB2300 Evaluation Boards
The Keil MCB2300 Evaluation Boards introduce you to the NXP LPC23xx series of ARM microcontrollers and allow you to create and test working programs for this advanced architecture;
two versions of the board are available: the MCB2360 for the 100-pin LPC2368 and the MCB2370 for 144-pin LPC2378
MCB2300
Keil RealView Microcontroller Development Kit
The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard compilation
tools and sophisticated debugging support
MDK-ARM
Keil ULINK2
The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target hardware;
ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works with standard
Windows USB drivers
ULINK2
SuppliersPgs42-49
9/4/07
4:15 PM
Page 5
46 |
LPC2478 72 MHz, 32-bit ARM-based microcontroller
with integrated LCD support
Core: ARM7TDMI-S
These innovative and cost-effective microcontrollers support concurrent operations
of high-bandwidth peripherals with significant power savings. The large array of
peripherals supported by these devices in addition to the LCD interface include
10/100 Ethernet, USB host/OTG/device, two CAN channels, four UARTs, three
I2C buses, two-input and two-output I2S, SPI, SSP, RTC, ADC/DAC, SD/MMC
card interface, external interfaces to SRAM, SDRAM and NOR Flash.
The LPC2478 microcontroller is the industry’s only ARM7 Flash-based MCU offering integrated LCD support as well
as a Flashless version, the LPC2470.
Features
c
• 72-MHz, 32-bit ARM7 core with dual AHB interfaces
• 512 KB of fast 128-bit wide embedded Flash (LPC2478 only)
• LCD interface
• 10/100 Ethernet MAC interface with DMA
• USB 2.0 full-speed OTG/Device/OHCI plus PHY and DMA
• Two CAN 2.0B controllers with acceptance filtering
• External interfaces to SRAM, SDRAM, and NOR Flash
• 10-bit A/D converter and 10-bit D/A converter
Benefits
c
• Significant savings in cost, area, and power consumption
• Ideal for a wide range of industrial, consumer, retail and
medical systems using LCD panels and requiring network
or Internet connectivity
• LCD implementation allows code execution on-chip
1-866-910-3650
LPC247x Block Diagram
SuppliersPgs42-49
9/4/07
4:15 PM
Page 6
| 47
Part
Number
Total Total Temp. °C Package Core
Max
A/D
A/D
Timer Timer
Flash RAM
Type Variant ID Frequency Bits Channels Channels Bits
Serial Interface
Description
GPIO Ethernet
USB
Peripherals
LPC2470FBD208
0
98
-40 to +85 LQFP208 ARM7TDMI
72
10
8
4
32
4xUART(1xIrDA), 2xCAN,
2.0/OTG SPI, 2xSSP, 3xI2C, I2S
160
1
1
LCD (1024x768), 10/100 with MII/RMII and DMA,
USB 2.0/OTG w/PHY and DMA, SD/MMC
LPC2470FET208
0
98
-40 to +85 TFBGA208 ARM7TDMI
72
10
8
4
32
SPI, 2xSSP, 3xI2C, I2S
160
1
1
LPC2478FBD208
512
98
-40 to +85 LQFP208 ARM7TDMI
72
10
8
4
32
160
1
1
LPC2478FET208
512
98
-40 to +85 TFBGA208 ARM7TDMI
72
10
8
4
32
160
1
1
Tool Name
Description
Part Number
Keil RealView Microcontroller Development Kit
The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard
compilation tools and sophisticated debugging support
Keil ULINK2
The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target
hardware; ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works
with standard Windows USB drivers
MDK-ARM
ULINK2
SuppliersPgs42-49
9/4/07
4:15 PM
Page 7
48 |
STM32, STR7 and STR9 Families
Core: Cortex-M3, ARM7TDMI, ARM966E-S
STMicroelectronics brings the power of 32-bit ARM® processor cores to the world
of microcontrollers, opening endless opportunities to embedded system designers
by making control and connectivity applications easy and affordable. With a wide
range of embedded memories, peripherals and architectural enhancements, ST's
STM32, STR7 and STR9 families help scale designs to achieve the best fit for an
application. STM32, STR7 and STR9 families address needs, from low-end to
high-performance, with a common set of tools and software, thus reducing cost
and time to market.
Features
c
STM32 Cortex-M3
• Lowest voltage, power and cost
• Very high performance and integration
• 1.25 DMIPS/MHz Harvard Architecture
• Access Line - 36 MHz
• Performance line - 72MHz
• 2.0 to 3.6V operation
STR710 ARM7
• Performance up to 45 MIPs @ 50 MHz
• STR7’s biggest RAM (64 KB)
• External memory interface
1-866-910-3650
STR730 ARM7
• The most timers (20), CANs (3), UARTs (4), and I/Os (112)
• Well-suited for industrial applications
STR750 ARM7
• Peripherals include CAN, USB, 3xUARTs, and advanced timers
• Suitable for many general-purpose applications
STR910 ARM9E
• Highest performance (96 MHz ARM9E)
• Largest Flash/RAM memory size (544 KB/96 KB)
• Ethernet connectivity
• 2.7 to 3.6V I/O plus 1.8V core operation
SuppliersPgs42-49
9/4/07
4:15 PM
Page 8
| 49
STM32 Portfolio Diagram
STR7 and STR9 Portfolio Diagram
ST Family of Microcontrollers | STMicroelectronics
9/5/07
9:32 AM
Page 1
50 |
STM32
Core: Cortex-M3
The STM32 family of 32-bit Flash microcontrollers is based on the breakthrough ARM
Cortex-M3 core specifically developed for embedded applications. Benefiting from the
Cortex-M3 architectural enhancements the STM32 offers 1.25 Dhrystone MIPS/MHz and a
current consumption as low as 36mA at a full 72 MHz CPU speed executing directly from
Flash memory with all peripherals clocked. The STM32 uses the Thumb2 instruction set that
offers 30% to 45% less code size than an ARM7TDMI-based MCU yet is 35% faster. Two
product lines, Access and Performance, offer up to 128 K Flash memory at either 36 MHz for Access line and 72 MHz
for Performance line. These 2.0V to 3.6V devices also include very fast startup time, included reset supervisor, have very
low interrupt latency and single cycle multiply and hardware divide.
Features
c
• 1.25 DMIPS/MHz Harvard Architecture
• 0.19mW/MHz power consumption
• Thumb2 instruction set (includes Thumb instructions)
• Single cycle multiply and hardware division
• Up to two 12-bit 1µs ADCs that can be syncronized
• Fast interrupt controller embedded inside core
• Low voltage 2.0V to 3.6V full speed operation
• Startup from Stop less than 10µs
Benefits
c
• 30% improvement in performance over ARM7TDMI
• High dynamic power efficiency in run mode and extremely low
power in standby
• 32-bit high performance with compact 16-bit code density
• Very low interrupt latency down to 6 CPU cycles for inter-interrupts
• Enabled for battery powered applications
• Designed also for motor control
• Very few external components needed
• Serial Wire JTAG debug maximizes I/O
1-866-910-3650
STM32 Block Diagram
9/5/07
9:32 AM
Page 2
| 51
Part
Number
Total
Flash
Total
RAM
Temp. °C
Package
Type
Max.
Frequency
A/D
Bits
A/D
Channels
Timer
Channels
Timer
Bits
Serial Interface
Description
GPIO
STM32F101C6
STM32F101C8
STM32F101R6
USB
Peripherals
32 K
6K
-40 to +85 or 105
LQFP48
36
12
10
2
16
1xSPI, 1xI2C, 2xUSART
32
64 K
10 K
-40 to +85 or 105
LQFP48
36
12
10
3
16
32
2xWDG, RTC, Temp Sensor
32 K
6K
-40 to +85 or 105
LQFP64
36
12
16
3
16
49
STM32F101R8
64 K
10 K
-40 to +85 or 105
LQFP64
36
12
16
3
16
49
STM32F101RB
128 K
16 K
-40 to +85 or 105
LQFP64
36
12
16
3
16
49
STM32F101V8
64 K
10 K
-40 to +85 or 105
LQFP100
36
12
16
3
16
80
STM32F101VB
128 K
16 K
-40 to +85 or 105
LQFP100
36
12
16
3
16
80
STM32F103C6
32 K
10 K
-40 to +85 or 105
LQFP48
72
12
2 x 10
3
16
1xSPI, 1xI2C, 2xUSART, USB, CAN
32
Device 2.0
STM32F103C8
64 K
20 K
-40 to +85 or 105
LQFP48
72
12
2 x 10
4
16
32
Device 2.0
STM32F103R6
32 K
10 K
-40 to +85 or 105
LQFP64
72
12
2 x 16
3
16
49
Device 2.0
STM32F103R8
64 K
20 K
-40 to +85 or 105
LQFP64
72
12
2 x 16
4
16
49
Device 2.0
STM32F103RB
128 K
20 K
-40 to +85 or 105
LQFP64
72
12
2 x 16
4
16
49
Device 2.0
STM32F103V8
64 K
20 K
-40 to +85 or 105
LQFP100, BGA100
72
12
2 x 16
4
16
80
Device 2.0
STM32F103VB
128 K
20 K
-40 to +85 or 105
LQFP100, BGA101
72
12
2 x 16
4
16
80
Device 2.0
Tool Name
Description
IAR KickStart Kit™
IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware
and software you need to design, implement and test your STM32 application
STM3210B-SK/IAR
Part Number
Keil Starter Kit
The Keil starter kit is a complete solution for evaluating and starting application development with the STM32
STM3210B-SK/KEIL
Hitex Starter Kit
The Hitex Starter Kit for STM32 is a complete solution for evaluating and starting application development with STM32 microcontrollers
STM3210B-SK/HIT
Raisonance REva Starter Kit
The REva starter kit from Raisonance is a cost-effective and complete solution for evaluating and starting application development
STM3210B-SK/RAIS
Hardware Evaluation Board
A full-featured hardware platform to evaluate all features of the STM32; does not include software or JTAG dongle
STM3210B-EV/WS
REva Daughter Card
Daughter card to update STR7 REva kits to STM32
STM32103B-D/RAIS
STM32 Evaluation Board
STM32 Family of Microcontrollers | STMicroelectronics
9/5/07
9:32 AM
Page 3
52 |
STR710F
Core: ARM7TDMI
The STR710F series is loaded with many communication interfaces including USB,
CAN, ISO7816 and four UARTs. It is endowed with the biggest RAM of all STR7
MCUs (up to 64 KB) and implements an optional external memory interface. This
makes it a perfect fit for consumer, point of sales and high-end industrial applications.
The STR710F also features high performance, very low power, and very dense code,
and ST's latest 0.18µ embedded Flash technology.
Features
c
• Largest choice of peripherals and interfaces, including
USB and CAN
• Flexible power and clock management
• Superior RAM/FLASH ratio
• High-quality embedded Flash with 16 K extra Flash for
EE emulation (20 year retention at 85°C)
• Extensive package options including the space efficient
8x8 LFBGA64 and 10x10 LFBGA 144
• Extensive software and tool support including the complete
STR7 library for USB
Benefits
c
• Reduces system cost with all peripherals on one chip
• Allows full control over power consumption and
performance/power tradeoffs
• Unlimited possibilities - up to 64 K RAM, and always above
16 K even with smallest Flash option
• 16 K extra Flash reduces system cost with no need for
external EEPROM
• Software and tools support dramatically reduces development time
and increases ease-of-use
1-866-910-3650
STR710F Series Block Diagram
9/5/07
9:32 AM
Page 4
| 53
Part
Number
Total
Flash
Total
RAM
Temp. °C
Package
Type
Core
Variant ID
Max
Frequency
STR710FZ1
144
32
-40 to +85
BGA144, LQFP144
ARM7TDMI
66
STR710FZ2
STR711FR0
STR711FR1
STR711FR2
STR712FR0
STR712FR1
STR712FR2
STR715FR0
272
80
144
272
80
144
272
80
64
16
32
64
16
32
64
16
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
BGA144, LQFP144
BGA64, LQFP64
BGA64, LQFP64
BGA64, LQFP64
BGA64, LQFP64
BGA64, LQFP64
BGA64, LQFP64
BGA64, LQFP64
ARM7TDMI
ARM7TDMI
ARM7TDMI
ARM7TDMI
ARM7TDMI
ARM7TDMI
ARM7TDMI
ARM7TDMI
66
66
66
66
66
66
66
66
A/D
A/D
Timer
Bits Channels Channels
12
12
12
12
12
12
12
12
12
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Timer
Bits
Serial Interface
Description
GPIO
Ethernet
USB
Peripherals
16
4xUART, 2xSPI, 2xI2C, CAN, SC
48
—
Device 2.0
EMI
16
16
16
16
16
16
16
16
2
4xUART, 2xSPI, 2xI C, CAN, SC
48
—
Device 2.0
EMI
2
30
—
Device 2.0
—
2
30
—
Device 2.0
—
2
4xUART, 2xSPI, 2xI C, SC
30
—
Device 2.0
—
2
32
—
—
—
2
32
—
—
—
32
—
—
—
32
—
—
—
2
2
Tool Name
Description
Part Number
REva Starter Kit - Raisonance
The REva starter kit from Raisonance is a cost-effective and complete solution for evaluating and starting application development
STR71X-SK/RAIS
IAR KickStart Kit™ with STR711 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware
and software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface for
application board connection; with STR711 target MCU
STR711-SK/IAR
IAR KickStart Kit™ with STR712 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware
and software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface for
application board connection; with STR712 target MCU
STR712-SK/IAR
Hitex Starter Kit
The Hitex Starter Kit for STR7 is a complete solution for evaluating and starting application development with ST ARM core-based microcontrollers; includes: application board; Tantino, in-circuit
debugger/programmer, featuring USB host interface and industry standard JTAG interface; HiTOP5, 16K code-size limited version of Hitex’s full-featured Integrated Development Environment;
plus GNU C/C++ Compiler
STR710-SK/HIT
Keil STR710 kit
The Keil starter kit, available from Keil, is a complete solution for evaluating and starting application development with the STR7; the package includes: application board with user LEDs, push buttons,
switches, potentiometer and interfaces for device specific peripherals; ULink, in-circuit debugger/programmer; uVision3, the full-featured Integrated Development Environment; RealView Compilation Tools,
16K code-size limited version of the optimizing C/C++ compiler
STR710F Series
STR710 kit
IAR, Raisonance, & Hitex Starter Kits
STR710F Family of Microcontrollers | STMicroelectronics
9/5/07
9:32 AM
Page 5
54 |
STR750F
Core: ARM7TDMI
The STR750F microcontrollers are the latest series in the STR7 family. These MCUs bring the
best integration with a balanced peripheral set, USB, CAN, and key innovations like clock failure
detection and advanced motor control timers. The STR750F supports either 3.3V or 5V systems,
and it is also available in an extended temperature range (-40°C to +105°C). This makes it a
genuine general purpose microcontroller, suitable for a wide range of applications such as
appliance, brushless motor drive, USB peripheral, UPS, alarm systems, programmable logic
controller, circuit breakers, inverters, and medical and portable equipment.
Features
c
• Excellent low power performance through flexible clock
management and multiple low power modes with consumption
down to 10 µA in standby mode
• Innovative backup clock
• Fast startup and wakeup
• Auto wake-up
• Serial memory interface (SMI) and LIN support
• Single supply, 3.3V or 5V (3.3V for USB)
• Powerful timers and fast ADC
• Extensive firmware support and tools; the STR750F
library is freely distributed by ST
Benefits
c
• Easy adjustment of performance/power consumption ratio;
suitable for battery operated applications
• Additional security due to backup clock
• Fast startup and wakeup adds responsiveness
• Auto wakeup improve power-savings
• Less external hardware needed
• 3.3V or 5V supply gives additional flexibility for customers;
no need for external regulator; real 5V drive on the I/Os
when 5V is used
• Perfect fit for tri-phase motor control applications
• Extensive library dramatically reduces development time
and increases ease of use
1-866-910-3650
STR750F Block Diagram
9/5/07
9:32 AM
Page 6
| 55
Part
Number
Total
Flash
Total
RAM
Temp. °C
Package
Type
Core
Variant ID
Max.
Frequency
A/D
Bits
A/D
Channels
Timer
Channels
Timer
Bits
Serial Interface
Description
GPIO
Ethernet
USB
Peripherals
STR755FR0
80
STR752FR0
80
16
-40 to +85
LQFP64
ARM7TDMI
60
16
-40 to +85
LQFP64
ARM7TDMI
60
10
11
6
10
11
6
16
2xSSP, 3xHS-UART, I2C
38
–
–
RTC, Motor Control
16
2xSSP, 3xHS-UART, I2C, CAN
38
–
–
STR751FR1
144
16
-40 to +85
LQFP64
ARM7TDMI
60
10
11
RTC, Motor Control
6
16
38
–
Device 2.0
STR752FR1
144
16
-40 to +85
LQFP64
ARM7TDMI
60
10
11
RTC, Motor Control
6
16
38
–
–
RTC, Motor Control
STR755FR1
144
16
-40 to +85
LQFP64
ARM7TDMI
60
10
11
6
STR751FR2
272
16
-40 to +85
LQFP64, BGA64
ARM7TDMI
60
10
11
6
16
38
–
–
RTC, Motor Control
16
38
–
Device 2.0
STR752FR2
272
16
-40 to +85
LQFP64, BGA64
ARM7TDMI
60
10
11
6
16
RTC, Motor Control
38
–
–
RTC, Motor Control
STR751FR0
80
16
-40 to +85
LQFP64
ARM7TDMI
60
10
11
6
STR755FV2
272
16
-40 to +85 LQFP100, BGA100
ARM7TDMI
60
10
16
6
16
2xSSP, 3xHS-UART
38
–
Device 2.0
RTC, Motor Control
16
72
–
–
RTC, Motor Control
STR750FV2
272
16
-40 to +85 LQFP100, BGA100
ARM7TDMI
60
10
16
STR750FV1
144
16
-40 to +85 LQFP100, BGA100
ARM7TDMI
60
10
16
6
16
72
–
Device 2.0
RTC, Motor Control
6
16
72
–
Device 2.0
STR755FV1
144
16
-40 to +85
LQFP100
ARM7TDMI
60
10
RTC, Motor Control
16
6
16
72
–
–
RTC, Motor Control
STR750FV0
80
16
-40 to +85
TQFP100
ARM7TDMI
60
STR755FV0
80
16
-40 to +85
LQFP100
ARM7TDMI
60
10
16
6
16
72
–
Device 2.0
RTC, Motor Control
10
16
6
16
72
–
–
RTC, Motor Control
STR755FR2
272
16
-40 to +85
LQFP64, BGA64
ARM7TDMI
60
10
11
6
16
38
–
–
RTC, Motor Control
Tool Name
Description
STR750 Full Evaluation Board
STR750F full evaluation board with 2 x 16 LCD, LEDs, UART and CAN interfaces
Part Number
Hitex Starter Kit for STR750
Hitex starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain
STR750-EVAL
STR750-SK/HIT
IAR KickStart™ Kit for STR750 IAR KickStart™ starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain
STR750-SK/IAR
Keil Starter Kit for STR750
Keil starter kit with STR750F evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools
STR750-SK/KEIL
Raisonance REva starter kit for STR750F with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR750F daughter, 16 KB code-size limited version of the RIDE software
tool set and GNU C/C++ compiler for ARM
STR750-SK/RAIS
STR750 Motor Control Kit
This motor control kit is ready to run within minutes for PMSM and induction 3-phase motors using STR750F for vector control drive. PMSM motor included
STR750-MCKIT
ST750F Family of Microcontrollers | STMicroelectronics
9/5/07
9:32 AM
Page 7
56 |
STR910FA
Core: ARM966E-S
The STR910FA family of MCUs delivers up to 96 MIPS peak performance while
executing code directly from its Flash memory, executes single-cycle DSP instructions
within its ARM966E-S core, and includes Ethernet, USB, and CAN interfaces. These
features, combined with Flash memory sizes reaching 544 Kbytes and a vast 96 Kbyte
SRAM, make the STR910FA an ideal single-chip solution to transform embedded control
applications into low cost nodes on a local network, or on the Internet.
Features
c
• 96 MHz ARM966E-S CPU core with single-cycle DSP instructions
and independent internal 32-bit buses
• 10/100 Ethernet connectivity with optimized DMA data flow
• Plentiful SRAM and Flash memories
• Dual bank Flash
• Flexible power and clock management with multiple low
power modes
• Low power (< 1 µA) real-time clock with programmable
wake-up features
• Extensive firmware support and tools offering. The STR910FA
library is freely distributed from ST
• Analog capability with 10-bit ADC and full supervisor functions
Benefits
c
• Simultaneous access to both code and data, generating 96 MIPS
peak performance executing code from Flash memory, and at the
same time capable of up to 384 Mbytes/sec DMA data flow
between peripherals and SRAM
• Connect your product to a network and retain ample CPU
bandwidth to implement the embedded application
• Meet requirements of complex applications, real-time operating
systems (RTOSs), communication stacks and data storage
• Ideal for robust In-Application Programming (IAP) and
EEPROM emulation
• Tailor your system on the fly to balance performance and power
consumption as needed
• Ideal for battery operated applications
• Extensive firmware support dramatically reduces development time
and increases ease of use
• With so much inside, less is needed outside saving you space,
cost and logistic headaches
1-866-910-3650
STR910FA Block Diagram
9/5/07
9:33 AM
Page 8
| 57
Part
Number
Total
Flash
Total
RAM
Temp. °C
Package
Type
Core
Variant ID
Max
Frequency
A/D
Bits
STR911FAM44
544
96
-40 to +85
LQFP80
ARM966E-S
96
10
8
7
STR912FAW44
544
96
-40 to +85
LQFP128
ARM966E-S
96
10
8
STR912FAW42
288
96
-40 to +85
LQFP128
ARM966E-S
96
10
8
STR911FAM42
288
96
-40 to +85
LQFP80
ARM966E-S
96
10
A/D
Timer
Timer
Channels Channels Bits
8
Serial Interface
Description
GPIO
16
3xUART, 2x SPI, CAN, 2xFast I2C
7
16
7
16
7
16
Ethernet
USB
Peripherals
40
–
Device 2.0
RTC, Motor Control
80
MAC 10/100
Device 2.0
RTC, Motor Control, EMI
80
MAC 10/100
Device 2.0
2
40
–
Device 2.0
RTC, Motor Control
2
3xUART, 2x SPI, CAN, 2xFast I C
STR910FAW32
288
64
-40 to +85
LQFP128
ARM966E-S
96
10
8
7
16
3xUART, 2x SPI, CAN, 2xFast I C
80
–
–
RTC, Motor Control
STR910FAM32
288
64
-40 to +85
LQFP80
ARM966E-S
96
10
8
7
16
40
–
–
RTC, Motor Control
2
80
–
–
2
80
–
Device 2.0
2
STR911FAZ32
STR911FAW42
256
256
64
96
-40 to +85
-40 to +85
BGA144
LQFP128
ARM966E-S
ARM966E-S
96
96
10
10
10
10
7
7
16
16
3xUART, 2xSPI, CAN, 2xFAST I C
STR912FAW34
512
64
-40 to +85
LQFP128
ARM966E-S
96
10
10
7
16
80
MAC 10/100
Device 2.0
STR912FAW44
512
96
-40 to +85
LQFP128
ARM966E-S
96
10
10
7
16
3xUART, 2xSPI, CAN, 2xFAST I2C
80
MAC 10/100
Device 2.0
2
80
MAC 10/100
Device 2.0
2
80
MAC 10/100
Device 2.0
STR912FAZ42
STR912FAZ44
256
512
96
96
-40 to +85
-40 to +85
BGA144
BGA144
ARM966E-S
ARM966E-S
96
96
10
10
10
10
7
7
16
16
Tool Name
Description
Part Number
STR9 Full Evaluation Board
An open-design evaluation platform for STR910FA, which includes reference code and a range of hardware features for evaluation of device peripherals including USB, Ethernet, CAN, ADC and much more;
in addition to a JTAG standard interface for in-circuit debugging and programming, it includes an ETM interface for connection of a trace tool
IAR KickStart™ Kit for STR9
IAR KickStart starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain
STR91X-SK/IAR
Keil STR9 Starter Kit
Keil starter kit with STR9 evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools
STR91X-SK/KEI
Raisonance REva starter kit for STR9 with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR9 daughter board, 16 KB code-size limited version of the RIDE software
tool set and GNU C/C++ compiler for ARM
STR91X-SK/RAI
Hitex Starter Kit for STR9
Hitex starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain
STR91X-SK/HIT
STR910-EVAL
IAR KickStart Kit
STR910FA Family of Microcontrollers | STMicroelectronics
9/5/07
9:33 AM
Page 9
58 |
STR730F
Core: ARM7TDMI
STR730F Flash microcontrollers combine the industry standard ARM7TDMI® RISC
microprocessor with embedded Flash and powerful peripheral functions, including
up to 20 timers, 4xUARTs and 3xCANs. The STR730F MCUs are ideal for embedded applications requiring a compact yet powerful MCU, as well as versatile, scalable
solutions such as user interfaces, factory automation systems and appliances.
Additionally, the STR730F family features a single 5V power supply particularly
suited to industrial applications.
Features
c
STR730F Block Diagram
• Largest choice of peripherals and interfaces including
4xUART, up to 20 timers and up to 3xCAN
• Flexible power and clock management
• Five low-power modes
• Low-power voltage regulator
• Extensive software and tools including the complete
STR7 library supporting all standard peripherals and CAN
• Dual APB buses architecture
• Single 5V power supply
• 16-channel DMA
Benefits
c
• Reduces system cost with all peripherals in one chip
• Full control over your power consumption
and performance/power tradeoffs
• Precisely manage low-power vs. performance
• Built-in voltage regulator means fewer external components
• Software library dramatically reduces development time and
increases ease-of-use
• Increased overall performance due to dual buses
• Native 5V supply of industrial applications; no 3.3V
conversion needed
• DMA lowers CPU load, optimized access to memory
STR730F Family of Microcontrollers | STMicroelectronics
9/5/07
9:33 AM
Page 11
60 |
Digital Media Processors
Core: TMS320DM355: ARM9®, TMS320DM644x: ARM9 + TMS320C64x+™ DSP
Optimized for digital video systems, the DaVinci™ portfolio includes Digital Signal Processing
SoCs, multimedia codecs, Authorized Software Providers and frameworks providing the industry’s
first complete offering of an open platform.
The portfolio of DaVinci processors provides engineers with a choice of ARM® processors, DSP co-processors,
accelerators, peripherals or a combination of all to create a true SoC for digital video applications such as digital
cameras, video telephones, IP set-top boxes, automotive infotainment, video security, portable media players, medical
imaging and networked video for emerging applications.
Customers can quickly get started with development tools for a variety of application spaces and designs, including
low-cost starter kits, complete development kits and even reference designs. In addition to development tools, a complete
software infrastructure ranging from low-level drivers to application APIs, makes it possible for developers to implement
complex codecs such as H.264 and MPEG-4 into ARM-based digital video designs without having to focus resources
on writing and optimizing codecs and programming a DSP.
Features
c
• Broad portfolio of Digital Signal Processing SoCs, software,
development tools and support
• Providing a solution for digital video systems, DaVinci technology
accelerates time-to-market
• TI-developed digital media software is now widely available to
further accelerate design. The software portfolio includes
multimedia codecs such as H.264, MPEG-4, WMA9 and many
more; for a free evaluation, visit www.ti.com/digitalmediasoftware
• Supports several operating systems appropriate for different
applications, including open source Linux, MontaVista™ Linux,
Green Hills INTEGRITY™, Green Hills VelOSity, QNX Neutrino
and Microsoft Windows® CE
Benefits
c
• Save months of development time by leveraging integrated,
production-tested software and hardware components
• Real-time performance, simulation and emulation
• An open development platform enables OEM product differentiation
with a flexible, complete solution
• Lower system cost significantly and leverage IP across multiple
products
• Standard operating systems will allow developers with expertise
on these systems to work in an environment that is familiar
• Valued members of TI’s Third Party Network provide integral
components and tools that complement DaVinci technology; they
offer various levels of video system integration, optimization and
system expertise on DaVinci products worldwide
1-866-910-3650
IP netcam system block diagram based on the
DM644x processor
Video doorbell system block diagram based on the
DM355 processor
9/5/07
9:33 AM
Page 12
| 61
Device
CPUs
Frequency L1/ SRAM
(MHz)
(Bytes)
L2/ SRAM
(Bytes)
ROM
(Bytes)
External
Memory I/F
EDMA
Video Ports
(Configurable)
Serial
I/F
Connectivity
I/F
Program/
Data Storage
TMX320DM355ZCE
ARM9,
DaVinci
Video
216
270
TMS320DM6441ZWT
C64x+,
ARM9,
DaVinci
Video
TMS320DM6443ZWT
TMS320DM6446ZWT
Voltage (V)
Core I/O
Packaging
1 KU
Price1
–
–
8K
1 16-/8-Bit
EMIF,
1 16-Bit
MDDR/DDR2
64 Ch
1 Input,
1 Output
3 SPI,
2 ASP,
3 UARTs,
I2C
USB 2.0 HS
Async SRAM,
MDDR/DDR2 SDRAM,
NAND Flash,
SmartMedia/xD
1.3
1.8/
3.3
329 BGA
13 x 13 mm
14.25
16.90
513/405
(DSP)
256/202
(ARM)
112 K
(DSP)
40 K
(ARM)
64 K
(DSP)
16 K
(ARM)
1 16-/8-Bit
EMIFA
1 32-/16-Bit
DDR2
64 Ch
1 Input,
1 Output
ASP, I2C,
SPI,
3 UARTs
USB 2.0,
VLYNQ,
10/100 EMAC
Async SRAM,
DDR2 SDRAM,
NAND Flash,
SmartMedia/xD
1.2/
1.05
1.8/
3.3
361 BGA,
16 x 16 mm
27.05
C64x+,
ARM9,
DaVinci
Video
594
(DSP)
297
(ARM)
112 K
(DSP)
40 K
(ARM)
64 K
(DSP)
16 K
(ARM)
1 16-/8-Bit
EMIFA
1 32-/16-Bit
DDR2
64 Ch
1 Output
ASP, I2C,
SPI,
3 UARTs
USB 2.0,
VLYNQ,
10/100 EMAC
Async SRAM,
DDR2 SDRAM,
NAND Flash,
SmartMedia/xD
1.2
1.8/
3.3
361 BGA,
16 x 16 mm
33.84
C64x+,
ARM9,
DaVinci
Video
594
(DSP)
297
(ARM)
112 K
(DSP)
40 K
(ARM)
64 K
(DSP)
16 K
(ARM)
1 16-/8-Bit
EMIFA
1 32-/16-Bit
DDR2
64 Ch
1 Input,
1 Output
ASP, I2C,
SPI,
3 UARTs
USB 2.0,
VLYNQ,
10/100 EMAC
Async SRAM,
DDR2 SDRAM,
NAND Flash,
SmartMedia/xD
1.2
1.8/
3.3
361 BGA,
16 x 16 mm
39.49
1
Prices are quoted in U.S. dollars and represent year 2007 suggested resale pricing. All prices are subject to change. Customers are advised to obtain
the most current and complete pricing information from TI prior to placing orders. TI may verify final pricing prior to accepting any order.
New devices are listed in red.
Tool Name
Description
Part Number
TMS320DM355 Digital Video
Evaluation Module
The DM355 Digital Video Evaluation Module (DVEVM) allows developers to write production-ready application code for the ARM to begin immediate application development for the TMS320DM355
digital media processors
TMDXEVM355
TMS320DM644x Digital Video
Evaluation Module
The Digital Video Evaluation Module allows developers to write production-ready application code for the ARM and provides access to the DSP core using DaVinci APIs to begin immediate
application development for the TMS320DM6441, TMS320DM6443 and TMS320DM6446 digital media processors
TMDXEVM6446
Digital Video Software
Production Bundle
The Digital Video Software Production Bundle (DVSPB) provides the software needed to design complex DaVinci-based digital video systems quickly and efficiently; the DVSPB significantly
improves software integration and system visibility by incorporating tools such as Codec Engine, evaluation codecs, drivers and a production license for MontaVista Linux Pro 4.0, plus one year of
MontaVista Zone access with updates.
A DVSPB is recommended, coupled with a DVEVM, as a must-have for TI-supported ARM926 processor production design.
* Complete DVSPB plus Code Composer Studio™ IDE version 3.3 and Spectrum Digital XDS560™ emulator
TMDSDVSPBA9-L
TMDSDVSPBA9-3L*
New tools are listed in red.
TMS320DM355 Evaluation Module
Digital Media Processors | Texas Instruments, Inc.
DaVinci™ Digital Media Processors in Production Now c
ARM Tools-Pages62-72(2)
9/5/07
11:31 AM
Page 1
62 |
Windows CE
Core: ARM9, ARM11 and XScale
Windows® Embedded can help you turn your vision and ingenuity into superior business results by offering a great
combination of the creative tools and technology you need and the support and resources Microsoft® and its partners can
provide. Designed specifically for embedded developers who need to bring new devices to market in minimum time and
at the lowest possible cost, Windows Embedded CE 6.0 provides a 32-bit native hard real-time, small footprint operating
system, and powerful embedded development tools (Visual Studio 2005) with broad support for ARM9, ARM11, and
XScale based devices. CE 6.0 interoperates with industry standards and existing Microsoft desktop and server
technologies to help you create differentiated devices for a broad range of device categories, from commercial
devices to consumer electronics products.
CE 6.0 features a re-designed kernel to increase functionality for a richer set of user experiences by enabling a larger
number of applications to run simultaneously. CE 6.0 supports up to 32,000 simultaneous processes, with up to 2 GB
of virtual memory space for each process. A new file system supports larger storage media, large file sizes and
removable media encryption.
CE 6.0 supports a wide range of ARM processors (http://msdn2.microsoft.com/en-us/embedded/aa714536.aspx) from
leading ARM silicon partners. Board support packages are provided by Microsoft as well as Microsoft's IHV and ISV
partners (http://msdn2.microsoft.com/en-us/embedded/aa714506.aspx).
Features
c
• Advanced Graphics. CE 6.0 provides a variety of multimedia
capabilities including DirectX, Direct3D Mobile, and Win32 GDI
enabling advanced graphics in OEM applications and devices.
• Small footprint. The kernel itself is 300 K and scales as OEMs
customize their image to include device drivers, middleware and
higher level user applications.
• Unified Kernel. The redesigned Windows Embedded CE 6.0
kernel ow handles more than 32,000 simultaneous processes, each
with 2 GB of virtual memory space. The new file system supports
larger storage media and file sizes (up to 4 GB), and removable
media encryption. CE provides a multi-threaded, preemptive kernel
and support for multiple processor architectures.
• Drivers. Production-quality device drivers help decrease the
amount of modification needed for drivers to work with custom
hardware, and enhanced driver support in CE 6.0 helps ensure
easy portability. Drivers can be run in kernel mode for performance
or in user mode for robustness.
• Security. The redesigned one-tier security model is SDL compliant
and helps ensure that only trusted applications can run on your
embedded device.
• Device Performance. Improvements to the kernel architecture
have greatly reduced the overhead of system calls between base
OS services, resulting in improved operating system performance.
1-866-910-3650
• Native Windows Applications/Services. Microsoft Embedded
CE 6.0 supports many commonly requested applications, including
Microsoft Internet Explorer, Microsoft Windows Media Player,
NET Compact Framework 2.0 SP1, SQL Server Compact
Edition, and more.
MSWindows Block Diagram
9/5/07
11:31 AM
Page 2
| 63
c
• New Media and Communication Components:
– Network Media Devices. You now have the ability to build
networked media devices that can consume pictures, videos,
and music from a Windows PC via a home network.
– Digital Video Recorders. The DVR engine in CE 6.0
empowers you to build devices that can record multiple video
streams to a hard drive for later playback
– Cellular Networks. The new Cellcore components help enable
your CE 6.0 powered devices to easily make data connections
and initiate voice calls through cellular networks.
– Windows Network Projectors. Users can now connect their
Windows Vista™ laptop to a CE 6.0-based projector wirelessly
or over any IP network.
• Powerful Development Environment:
– Visual Studio 2005. Platform Builder for Windows Embedded
CE 6.0 has been created as a plug-in for Visual Studio 2005
and is customized for developing embedded operating systems
and components.
– Application Development Options. You can go native or
managed by choosing your preferred Microsoft development
technology—Win32, MFC, or the .NET Compact Framework
(C#, VB).
– Device Emulation. The new ARM-based device emulator
included with Platform Builder makes it easy to configure,
build, and test operating system images.
– Editors. Coding and building are faster. Windows Embedded
CE 6.0 editors now incorporate Intellisense technology, syntax
highlighting, and graphical bib and registry file editors.
– Improved Compilers. Based on Visual Studio 2005, the latest
compilers increase C++ language conformance; provide better
libraries; support CRT, ATL, and MFC; and offer improved
run-time security checks (/GS)
Benefits
c
• Rapid Time to Market and Reduced Development Cost.
Windows Embedded CE 6.0 helps speed development, saving
you time and money.
• Risk-free Evaluation. Once you download the fully functional
trial version, you can begin working with the operating system
and evaluating tools and the Windows Embedded CE OS for
180 days without making a purchase. Developers familiar with
Visual Studio and managed and native development can quickly
begin developing applications and drivers for CE 6.0.
• Coding Efficiencies. In addition to source code access,
Windows Embedded CE 6.0 includes a broad selection of
production-quality device drivers that help decrease the
amount of modification needed for drivers to work with
custom hardware.
• Opportunity for New Devices and Markets. With the rich
new media and communications components in Windows
Embedded CE 6.0, device makers can pursue exciting new
business opportunities.
• In the Field. With the new Cellcore Data components,
Windows Embedded CE 6.0 enables new types of devices to
establish data connections over cellular networks. For
example, a vending machine could make an inventory request
or a parking meter could accept credit card payments. Plus,
Cellcore Voice components enable devices to establish voice
calls over cellular networks.
– At Work. People will discover easier ways to get their
message across. Using the new Networked Projector
capabilities of CE 6.0, meeting attendees will be able to show
a presentation from a Windows Vista-based Notebook PC
without the need for special cables.
– At Home. Over a home network, CE 6.0-based devices can
browse photos, music, or video from Windows PCs and
present them on a television using the Network Media Device
capabilities of CE 6.0. With the Windows Embedded CE 6.0
Digital Video Recording Engine, set-top boxes or digital TVs
can record, pause, and rewind video streams from
multiple tuners.
• 10-year Product Support. Windows Embedded CE 6.0
provides the confidence of a 10-year Product Support
Lifecycle. And, when you purchase a royalty bearing license,
you receive IP indemnification (subject to the terms of your
license agreement with Microsoft).
Windows CE | Windows Embedded
Features cont.
9/5/07
11:31 AM
Page 4
9/5/07
11:31 AM
Page 5
66 |
IAR Embedded Workbench Version 4.41 for ARM ®
C/C++ Compiler and Debugger Tools for ARM
IAR Embedded Workbench® is a set of highly sophisticated and easy-to-use development tools
for programming ARM® embedded applications. It integrates the IAR C/C++ compiler, assembler,
linker, librarian, text editor, project manager, and C-SPY® debugger in one Integrated Development
Environment (IDE). With its built-in chip-specific code optimizer, IAR Embedded Workbench
generates very efficient and reliable FLASH/PROMable code for ARM devices. In addition to
this solid technology, IAR Systems provides professional, worldwide technical support.
The ARM Cortex-M3 processor offers significant benefits to
system and software developers.
• ARM7 (ARM7TDMI, ARM7TDMI-S, and ARM720T)
• ARM9 (ARM9TDMI, ARM920T, ARM922T, and ARM940T)
• ARM9E (ARM926EJ-S, ARM946E-S, and ARM966E-S)
• ARM11
• Cortex-M3
• Intel® XScale™ core
Key Components
c
• IDE with project management tools and editor
• Highly-optimizing ARM compiler supporting C and C++
• Configuration files for ARM chips from Analog Devices,
Atmel, Freescale, Intel, Luminary Micro, NXP,
STMicroelectronics, and Texas Instruments
• Extensive JTAG and RDI debugger support
• Optional IAR J-Link and IAR J-Trace hardware debug
probes
• Run-time libraries including source code
• Relocating ARM assembler
• Linker and librarian tools
• C-SPY debugger with ARM simulator, JTAG support,
and support for RTOS-aware debugging on hardware
• Evaluation edition of IAR PowerPac RTOS and file
system bundle
• RTOS plug-ins available from IAR Systems and
RTOS vendors
• Code templates for commonly used code constructs
• Sample projects for evaluation boards from many
different manufacturers
• User and reference guides, both printed and in
PDF format
• Context-sensitive online help
Highlights in the Current Version
c
• IAR PowerPac bundled evaluation edition of
RTOS and file system for ARM
• Live watch on target hardware
• Code coverage using IAR J-Trace
• Comprehensive Flash loader support
• I/O register definition files
• More than 400 sample projects for different
evaluation boards
Supported ARM Cores and Devices
c
IAR Embedded Workbench supports ARM7, ARM9, ARM9E,
ARM11, Cortex-M3, and Intel® XScale™ devices from these
manufacturers:
•
•
•
•
Analog Devices
Freescale Semiconductor
Luminary Micro
STMicroelectronics
•
•
•
•
Atmel
Intel
NXP
Texas Instruments
For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.
1-866-910-3650
9/5/07
11:31 AM
Page 6
| 67
Chip-Specific Support
c
• Ready-made C/C++ and assembler peripheral register
definition files
• Multiple code and data models (where applicable)
• Extensive set of language features for PROMable
embedded code, including memory keywords, intrinsic
functions, interrupt functions, memory-mapped I/O
ports, etc.
• Sample projects for evaluation boards from IAR Systems,
Analog Devices, ARM, Atmel, Freescale, Keil, LogicPD,
Luminary Micro, Nohau, NXP, Phytec, STMicroelectronics,
and Texas Instruments
• Support for 4 Gbyte applications in ARM and
Thumb® mode
• Each function can be compiled in ARM or Thumb mode
• Vector Floating Point (VFP) coprocessor code generation
• Flash loaders included for devices from Analog Devices,
Atmel, Freescale, Luminary Micro, NXP,
STMicroelectronics, and Texas Instruments
• ARM Angel debug monitor support
Embedded Focus
c
• Advanced generic and processor-specific optimizations
for speed and memory footprint
• Lightweight runtime library: user-configurable to match
the needs of the application; full source included
• Flexible memory handling allows detailed control of
code and data placement
• Unnecessary functions and variables are removed
• Application-wide type checking of C/C++ variables
and functions at link time
• Optional flexible checksum generation for image
runtime verification
• Automatic placement of code and data in non-contiguous
memory regions
• Powerful relocating macro assembler with a versatile set
of directives and operators
Embedded Debugging
c
• Fully integrated debugger for source and disassembly
level debugging
• Very fine granularity execution control (function
call-level stepping)
• Complex code and data breakpoints
• Versatile monitoring of data: locals, watch, auto,
live watch, and quick watch windows; register and
memory windows
• STL container awareness
• C/C++ call stack window that also shows the function
to be entered; double-click on any function in call
chain updates the editor, locals, register, watch, and
disassembly windows to display the state of that
particular function at the time of call
• Trace utility to examine execution history: moving around
in the trace window updates the editor and disassembly
windows to show the appropriate location
• Terminal I/O emulation
• Interrupt and I/O simulation
• C-like macro system to extend debugger functionality
• Application program system calls emulated by the host
• Code coverage and profiling performance analysis tools
• Support for the ARM Debug Communication Channel (DCC)
• Generic Flash loader with API guide
• Multiple Flash loaders supported
• Debugger software development kit for third-party
extensions such as real-time operating systems and
emulator drivers
• Command line debugger utility
Graphical IDE
c
• Hierarchical project presentation
• Multiple projects within the same workspace
• Dockable windows and multiple views
• Source browser
• Library tools included for creating and
maintaining libraries
• Integration with source code control systems
• Text editor with multi-byte character support:
context-sensitive help system; syntax coloring; unlimited
undo/redo; find; search; replace; incremental search;
bookmarks; error tags; previous/next navigation;
matching brackets; smart indentation; code breakpoint
set/clear/enable/disable; and multiple panes
• Command line build utility
Language and Standards
c
• The C programming language, as standardized by
ISO/ANSI C94, with selected features from C99
• Embedded C++ extended with templates, multiple and
virtual inheritance, namespaces, and other C++ features
that do not cause an overhead in size or speed; full
Embedded C++ library containing string, streams, etc.,
as well as the Standard Template Library (STL)
• IEEE-754 floating-point arithmetic
• MISRA C checker
• Supports a wide range of industry-standard debug and
image formats: compatible with most popular debuggers
and emulators, including ELF/DWARF where applicable
User Assistance
c
• Ready-made sample projects and project templates
• Context-sensitive online help with library function lookup
• Printed user guides with extensive step-by-step tutorials
• User friendly, detailed, and precise error messages
and warnings
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The Keil RealView Microcontroller Development Kit
Create Applications for ARM7, ARM9, or Cortex-M3 Based Microcontrollers
The RealView® Microcontroller Development Kit (MDK) shortens development cycles by
reducing the time spent configuring, testing, and debugging embedded applications.
The RealView MDK combines ARM RealView compilation tools with the Keil µVision®
Integrated Development Environment (IDE), providing developers with a feature-rich environment optimized for ARM-Powered® microcontrollers.
The Keil µVision IDE includes
c
• Project management and device and tool configuration
• A source code editor optimized for embedded systems
• Target debugging and Flash programming
• Accurate device simulation (CPU and peripheral)
RealView Microcontroller Development Kit
RealView
Real-Time Library
µVision Project Manager
RTX Source Code
C/C++ Compiler
Macro Assembler
RTX RTOS Libraries
ARM technology-based projects created under µVision are
automatically compiled and linked using the RealView
compilation tools.
The built-in microcontroller simulator models more than 50
ARM-Powered® devices, including the ARM instruction set,
on-chip peripherals, and the external signals used to
manipulate them.
ARM RealView compilation tools are recognized by the industry
for providing the best performance of all available ARM
technology-targeted compilers. Developed and tuned to deliver
the tightest code density, the compiler produces the smallest
code size, which leads to significant product cost savings.
The compiler generates optimized code for both the 32-bit
ARM and 16-bit Thumb® instruction sets while supporting
full ISO standard C and C++.
Project Configuration
c
The µVision IDE incorporates a device database of supported
ARM-Powered microcontrollers. In µVision projects, required
options are set automatically when you select the device from
the device database.
µVision displays only those options that are relevant to the
selected device and prevents the selection of incompatible
directives. Only a few dialogs are required to completely
configure all the tools (assembler, compiler, linker, debugger,
and Flash download utilities) and memory map for your
application.
Linker / Locator
Flash File System
µVision Debugger
Device Simulation
USB Device Interface
Target Hardware
Project Management
TCP/IP Suite
TCP, UDP, PPP, SLIP,
ARP, DNS Resolver,
Ethernet, DHCP Client,
HTTP Server with CGL
TFTP Server, SMTP Client
CAN Interface
c
File groups allow associated files to be grouped together. They
may be used to separate files into functional blocks or to identify
engineers in your software team.
Project targets allow you to create several programs from a
single project. You may require one target for testing and
another target for a release version of your application. Each
target allows individual tool settings within the same project file.
Editor
c
The µVision Editor includes all the standard features you
expect in a professional editor. Color syntax highlighting and
text indentation are optimized for editing C source files, while
document outlining allows you to collapse function blocks in
your source code. Most Editor functions are quickly accessed
from the toolbars.
While debugging, the Editor is available so you can easily make
changes to your source code.
For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.
1-866-910-3650
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Debugger
Accurate Device Simulation
c
The µVision Editor enables you to set simple breakpoints
using the context menu (or Editor toolbar) while creating your
C or assembler source. Breakpoints you set while editing are
activated when you start the µVision Debugger.
In addition to simple breakpoints, the µVision Debugger
supports complex breakpoints (with conditional or logical
expressions) and memory access breakpoints (with read/write
access from an address or range). The Debugger also
displays code coverage and execution profiling information
in the Editor windows.
RealView Real-Time Library
c
The RealView Real-Time Library (RL-ARM) enables networking,
communication, and real-time software. The RL-ARM is based
on a real-time kernel that simplifies the design and implementation of complex, time-critical applications. A Flash file system,
TCP/IP networking suite, and other communication protocols
are included.
c
The µVision Debugger simulates a complete ARM-Powered
microcontroller including the instruction set and on-chip peripherals. These powerful simulation capabilities provide serious
benefits and promote rapid, reliable embedded
software development.
• Simulation allows software testing on your desktop with
no hardware environment
• Early software debugging on a functional basis improves
overall software reliability
• Simulation allows breakpoints that are not possible with
hardware debuggers
• Simulation allows for optimal input signals (hardware
debuggers add extra noise)
• Signal functions are easily programmed to reproduce
complex, real-world input signals
• Single-stepping through signal processing algorithms is
possible; external signals stop when the CPU halts
• It is easy to test failure scenarios that would destroy real
hardware peripherals
Today, microcontroller applications require simultaneous
execution of multiple jobs or tasks. For such applications,
the RL-ARM allows task management and flexible scheduling
of system resources (CPU, memory, etc.).
The RL-ARM is a full-featured real-time kernel with task
priorities, round-robin, preemptive context switching, and
support for multiple instances of the same task function.
It is royalty-free and is fully integrated into µVision.
Third-Party Utilities
c
Third-party utilities extend the functions and capabilities of
µVision and are available from a wide variety of vendors.
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RealView Tools by ARM
Tools that Span the Complete Development Process
RealView® tools by ARM® are unique in their ability to provide solutions that span
the complete development process from concept to final product deployment. Each
member of the RealView portfolio has been developed closely alongside IP, ensuring
that it maximizes the IP’s performance.
RealView Development Suite
c
RealView Development Suite is the only complete, end-to-end
solution for software development that supports all ARM®
processors and ARM debug technology. These tools offer the
highest-performance ARM C/C++ compilers and support the
most advanced debug technology available today for bringing
up the latest SoC and ASIC designs.
Proven to deliver the highest return for the lowest risk on their
ARM-based ASICs, SoC, and FPGA designs, the RealView
Developer Suite is a trusted source for ARM development
solutions. Today, the majority of the four billion ARM-Powered™
devices worldwide have software created with RealView tools.
Investing in the RealView solution is the clear choice for a safe,
reliable, and high-performance design.
Eclipse Plug-ins for RealView Development
Suite c
RealView Development Suite integrates with the open-source
Eclipse IDE. This integration combines Eclipse’s outstanding
source code development tools and plug-in framework with the
best-in-class compilation and debug technology in the RealView
DEVELOP family of tools. The RealView Eclipse Plug-in enables
developers to use Eclipse as a project manager to create, build,
debug, and manage C and C++ projects for ARM targets. The
plug-in provides project stationery to simplify the creation of
ARM, Thumb®, and ARM/Thumb architecture-based projects,
and provides comprehensive configuration panels to specify
options for the RealView Development Suite.
Compilation Tools
New Features of RealView Development Suite
3.0 and SP1 c
Key features of the RealView Development Suite 3.0 solution
include support for the full line of ARM processors, including
the Cortex™-A8 processor, the Cortex-M3 processor, and
future Cortex family processors; support for CoreSight™
advanced debug and trace technology; an intrinsics compiler
for the NEON™ SIMD technology; an enhanced compiler
optimization engine that provides a 10 percent performance
improvement; and interoperability with GNU tools, enabling
optimal compilation of Embedded Linux applications and
optional integration with Eclipse.
RealView Development Suite 3.0 Service Pack 1 provides
a consolidation of enhancements since the original RealView
Development Suite 3.0 release, including preliminary support
for Cortex-R4, improved compilation times and DWARF3
debug data sizes, an expanded SIMD NEON assembler
with Programmer’s notation, an improved user interface that
debugs a multi-processor MPCore target, and expanded CortexM3 examples.
c
The compilation tools in RealView Development Suite are
recognized by the industry for providing the best performance
of all available ARM-processor targeted compilers. Developed
and tuned to deliver the tightest code density, the compilers
produce significantly smaller executables than other leading
tool suites. The compilers generate optimized code for the
32-bit ARM and 16-bit Thumb and Thumb-2 instruction sets
and support full ISO standard C and C++.
Debug Tools
c
Designed from the ground up to support complex single- and
multi-core SoC software development with Embedded OS, the
debugger in RealView Development Suite sets the standard for
creating and debugging deeply embedded applications. No other
debug environment provides interconnectivity with both the
RealView CREATE world of system-level modeling and the
RealView DEVELOP world of software development.
Add-om Options
c
The following components and abilities are offered by the
RealView Development Suite:
The following are available as add-on options to the RealView
Development Suite:
• Integrated Development Environment (IDE)
• A choice of IDEs
• RealView Development Suite can be integrated
with the Industry-standard Eclipse IDE through a
plug-in or CodeWarrior v5.7 IDE
• RealView SoC Designer
• RealView ICE and RealView Trace
• Real-Time System Model (RTSM) for ARM1176JZ(F)-S
• Eclipse IDE plug-in
• Plug-ins for popular DSP support
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Supported Platforms:
c
• Windows 2000, XP Professional
• Red Hat Enterprise Linux 3 and 4
• SPARC Solaris 9 and 10
RealView ICE
c
RealView ICE is ARM’s leading-edge JTAG run control
hardware unit, delivering the high performance required by
today’s developers working with sophisticated System-on-Chip
(SoC) devices and large software images.
RealView ICE provides a universal-ARM solution, i.e., one
unit supports all ARM CPUs in single, multi-core, homogenous,
and heterogeneous architectures, offering an unparalleled depth
and breadth of support for ARM processor-based devices.
RealView ICE is an essential tool in an ARM system debug
environment for connection and access to devices that contain
the EmbeddedICE® logic, Embedded Trace Macrocell™
(ETM™), and Embedded Trace Buffer(ETB™) components for
on-chip trace data storage. The unit has the ability to be
expanded with additional modules for extended functionality,
such as RealView Trace for trace data capture.
The recently released RealView ICE version 3.0 now enables
customers to connect to the new ARM Cortex family of
processors and devices containing the new CoreSight™
advanced debug and trace technology. RealView ICE and
Trace fully complement the RealView Development Suite
in providing best-in-class integrated tools for
hardware/software co-development of optimized
ASIC, SoC, and FPGA-based systems.
Other New Features
c
• JTAG run control for the new Cortex™-A8 and
Cortex-M3 processors
• CoreSight DK11 run control support for the ARM1136,
ARM1156, and ARM1176 processors
• TrustZone® secure and non-secure code views for the
Cortex-A8 and ARM1176 processors
RealView ICE can be connected to most types of host platforms
by Ethernet for extended and remote connection, or locally by
USB, to provide the optimum debug coupling and performance
with the RealView Debugger.
Main Features
• Support for variable JTAG clock frequencies, 2 kHz
to 20 MHz (standard cable) or 50 MHz (LVDS cable)
• Very low JTAG clock frequencies (sub-1 kHz) support
ASIC-emulation environments
• Wide target-voltage support, from 1.0V to 5.0V
• Tightly coupled, synchronized multi-core control
• ETM trace data capture with plug-in RealView
Trace module
• ETB trace data access via the JTAG port
• Debug using GDB and KGDB capability
• USB 1.1 and 2.0 compatible connection
(Windows platform only)
• Ethernet 10/100baseT remote and local host connection
Supported ARM Processors:
c
RVI-Supported cores include the following ARM processorbased families: ARM7™, ARM9™, ARM9E™, ARM10™,
ARM11™, and Cortex™
RealView Trace
c
RealView Trace interfaces with ARM on-chip trace data storage
Embedded Trace Macrocell (ETM™) components for the
ARM7™, ARM9™, ARM9E™, ARM10™, and ARM11™ core
families, and in conjunction with RealView Debugger. RealView
Trace provides non-intrusive real-time tracing of instructions,
data and profiling for performance analysis. It’s an optional
add-on expansion module for RealView ICE.
Main Features
c
• Non-intrusive real-time tracing of instructions and data up
to 250 MHz trace clock
• Up to eight million frames deep trace buffer (up to four
million frame deep buffer with time stamps)
• 4-/8-/16-bit data width trace port
• Trigger synchronization with external events
• Fully variable trigger position
• Fast on-the-fly trace data upload
• Shares RealView ICE connection to the host computer
• ETM trace ports modes supported
– ETM protocols v1.x, v2.x, v3.x for ETM7TM, ETM9TM,
ETM10TM, and ETM11TM
– Single and doubled-edged clocking
– Normal and multiplexed ports
• Time stamp (48-bit) 10 ns resolution with 32-day duration
c
• High-performance debug control
• Code download up to 1300 KBytes/sec with
the RealView Debugger
• High-speed single-stepping; up to 100 steps/sec
• JTAG Debug Communications Channel (DCC) support
Platforms supported are Windows 2000 and XP
Note: Cannot be used standalone. This product is designed to
be used in conjunction with a RealView ICE

ArrowARM Guide - Embedded Developer

Transcription

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