PowerPoint Presentation Template - STANDARD full

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PowerPoint Presentation Template - STANDARD full
PDK-based design automation enablement
for MEMS- and CMOS processes
DATE Exhibition Theatre
Session 11.8 - Launch of the Worldwide MEMS Design Contest
Jörg Doblaski
[email protected]
Director of Design Support X-FAB group
X-FAB Semiconductor Foundries AG
21 March 2016
Company Confidential
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Outline
About X-FAB
Process overview inertial sensor open-platform processes
CMOS design flow vs. MEMS design flow
PDK-based design flow enablement for MEMS
MEMS IP
Reference Kit for easy adoption
Summary
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About X-FAB
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Key Facts
The More than Moore Foundry.
• 20+ years of experience in pure-play foundry services for
analog/mixed-signal semiconductor applications
• Best-in-class design and engineering support
Technologies interfacing the real world
• Technologies for sensors, actuators and SoCs on modular
CMOS, SOI and MEMS processes engineered in Germany
• Flexible combination and integration of power, high-voltage,
analog, sensors and non-volatile memory features
• Dedicated MEMS foundry operations
Manufacturing excellence
•
•
•
•
5 wafer fab facilities in Germany, Malaysia and US
Capacity: 72,000 eight inch equiv. wafer starts per month
All production sites are automotive qualified
2,500 employees worldwide
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MEMS Offering
High-volume MEMS production on 6" & 8" wafers
Custom process manufacturing
• Wide range of process capabilities e.g.:
– Au, Pt, Cr, Ni, Cu, Mo deposition
– Piezoelectric materials (PZT, AlN)
– Eutectic bonding; thick Epi-silicon
micro-machining …
Open-platform technologies
• 3-axis accelerometers & gyroscopes
• Relative and absolute pressure sensors
• Design support including IP blocks
Integrated CMOS & MEMS manufacturing
Other supported applications include:
 Medical/Biotech
 Infrared Sensors
 Wafer Level Packaging
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 Micro-Mirrors
 RF MEMS
 Microphones
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Process overview inertial sensor
open-platform processes
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XMS10
surface–micromachined capacitive MEMS
foundry process
• SOI wafer based technology
• Sensor elements formed by Silicon DRIE process
• Releasing of movable parts using isotropic
Silicon etching
• Cost effective wafer level packaging by wafer
bonding
Sensor principle
• Detection of capacity changes, e.g. caused by
inertial forces
• Feasibility of electrical stimulation, e.g.
detection of Coriolis forces (Gyro's)
• Sensor capacity consists of interdigital
structures
• Element moving or finger bending in X-Y-plane
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XMS10
discrete surface mounted micromachined
devices
• Gyroscopes
• acceleration sensors
MEMS components:
•
•
•
•
•
•
•
comb structures
anchors
springs
moveable mass
stopper
Fixed-to-move transitions
bond pads
electrical connection using metal areas and
substrate
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XMS10: acceleration sensor
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Moveable mass
Comb
Springs
Anchor
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XMB10: 3-axis inertial sensor process
Triple axis inertial sensor using cavity SOI wafer based
technology
Recessed fingers enable sensing in Z-direction
100% efficient silicon mass possible
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Design flow: CMOS versus MEMS
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State-of-the-art CMOS design flow
Fully automated digital
implementation
• Synthesis of digital features
based on high level description
• Automated power- and timingaware placement and routing
Semi-automated
analog implementation
• Connectivity- and constraintdriven
• Layout automation using layout
generators (pcells) and analog
module generators
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Feature-rich CMOS PDK
Interface between foundry
process and EDA tools
PDK acts a process
abstraction
contains all data to work with
the digital, analog and mixedsignal design-flows
provides out-of-the-box
support of the latest design
flows
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PDK components: CMOS vs. MEMS
CMOS
MEMS
vs.
50%
D_
CELLS
IO_
CELLS
DIGITAL
RF_
CELLS
I/O
I_
CELLS
OTHER IP
Inertial
application specific CELL LIBRARIES
PRIMLIB
PRIMITIVE
LIBRARIES
XY_
CELLS
Pressure
OTHER IP
application specific CELL LIBRARIES
0%
BSIM3V3
MC
OCC
P_
CELLS
0%
10%
Assura
(PVS)
QRC
…
SIMULATION MODELS
Assura
(PVS)
QRC
DRC/LVS/RCX
DRC/LVS/RCX
30%
TECH_
XH035
TECHNOLOGY
LIBRARIES
xkit
.il
.cxt
TECH_
XMS10
Design Flow / User Ware
TECHNOLOGY
LIBRARIES
10%
xkit
.il
.cxt
Design Flow / User Ware
Status: 2012
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Missing MEMS PDK support
CMOS EDA tools expect a certain, CMOS-like process architecture
HV CMOS process
• device specific process layers
• only one dielectric layer per stack level
• polygon shapes with 90° or 135° angles
Inertial MEMS sensor process
• Different structures defined in the same
layer
• Multiple dielectric layers per stack level
• Circular shapes, fixed width, maximum
spacing…
MEMS EDA tools usually do not support a PDK interface
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Design flow: CMOS vs. MEMS
Digital CMOS
• automated
Analog HV CMOS
• Semi-automated
MEMS
?
• manual
• Artwork: The quality strongly
depends on the artist…
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[https://www.youtube.com/watch?v=ZHhu0qSrurE]
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PDK-based design flow
enablement for MEMS
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research project “Schematic-Based Design of MEMS for
Applications in Optics and Robotics”
• funding initial BMBF F&E 16M3093
Project objective: “develop the first ever universal design
methodology for MEMS to close the gap between electronics and
mechanics design, manufacturing, and subsequent integration
into products” [1]
Project partners:
*
[1] MEMS2015: Schematic Driven MEMS Design for Applications in Optics and Robotics. (n.d.). Retrieved January 29,
2016, from https://www.edacentrum.de/en/projects/MEMS2015
* Coventor: Associated partner
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MEMS PDK overview
Similar to CMOS: MEMS PDK components enabling design flow
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MEMS+ library customization
Generic MEMS+ Component Library
Design
Rules
Custom Library
Sub Schematics
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MEMS+ PDK Elements
New Plugin
Define
Layer
Set parameter
defaults
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Look
Parameter
Constrain
component
parameter
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MEMS+ PDK Elements (2)
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MEMS+ PDK: design flow enablement
MEMS+ PDK enables “lego-brick” design of MEMS
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Virtuoso PDK: Pcells
PRIMLIB with layout Pcells
•
•
•
•
Bond Pad
Crossing
Fixed-To-Move Transition
Frame
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Virtuoso PDK: Layout implementation
•
Import MEMS-base
structure
• Placement of Fixed-ToMove-Transitions
• Generate surrounding
TCOVER and MECH
• Generate metal at
TCOVER edges
• Route the sensor and
cut-off TCOVER at
crossings
• Place routed sensor into
the MEMS-frame
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Virtuoso PDK: DRC
checks process-specific layer-based
design rules
uses standard CMOS verification tool
(Cadence Assura)
support of design-rule-driven layout
Challenges:
structures, which are round or non-parallel to x- and y-axis?
• solution: rule check with tolerance
handle rules with fixed or maximum values?
• solution: complex rule implementation
device recognition without definition layers?
• Only partly implemented (fixed- and movable parts)
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Virtuoso PDK: LVS
MEMS core is considered to be LVS clean
• Both schematic and layout are generated within Coventor MEMS+
Final LVS after implementation of MEMS surrounding based on
the extraction capabilities of CMOS verification tools
• Extraction of fixed- and movable structures and electrical connections
• Open-Short-check between layout and schematic
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Virtuoso PDK: Parasitic Extraction
Process architecture cannot be
defined within one single PEX
process files
• At least 2 layers with different
dielectric properties at the same level
in the layer stack
• General problem with CMOS PEX Tools
PEX runset implementation with Cadence Quantus QRC
• 2 separate prozess files
• Supports extraction of parasitic capacitances and resistors in MEMS surrounding and
below the MEMS structure
• Extracted netlist can be used for post-layout simulation
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Inertial Sensor IP
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XMS10 MEMS IP
Ready-to-use accelerometer IP
Wafer-level packaged using wafer bonding
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MEMS-IP Cell Library
Cadence infrastructure for MEMS-IPs
• Library, Cells, Views, CDF Parameter &
Spectre/Verilog-A model library
 inertial sensor models für ACC001, ACC010
& ACC100 in XMS10 incl. corners tm, wc & wf
Spectre Library
typical mean
worst capacity
worst frequency
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Reference Kit for easy adoption of
new design flows
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Adoption of new design flows
The adoption of a new design flows needs some initial
investment…
EDA
provider
…which will pay back soon, due to higher performance,
reduced development time and better quality
EDA trainings and reference flows help, but are not sufficient
EDA
provider
XFAB
Reference
ReferenceFlow
- Tool1
Kit
- Tool2…
X-FAB Reference Kits close this gap!
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X-FAB A/MS Reference Kit
Overview
demonstration of supported design tools and flows
demonstration of advanced X-FAB design kit features
ready-to-use package
silicon-proven mixed-signal design
fast and easy adoption of new design flows
• detailed documentation
• full setup for all implementation steps
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X-FAB A/MS Reference Kit
Cadence A/MS Design Flow
Schematic XL
Constraint
Manager
MODGENS
Auto Placer
Guard Rings
VSR / Wire Editor
Circuit Prospector
Floorplanning
EDI Digital
Implementation
Timing-driven
Place & Route
AoT
Implementation
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Sensitivity
Analysis
Low-Power
Implementation
DRC, LVS, PEX
ADE
XL/GXL
Company Confidential
Sweeps &
Corners
Monte Carlo
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X-FAB MEMS Reference Kit
demonstration of MEMS design flow with Coventor MEMS+ and
Cadence Virtuoso
XMB10 MEMS+ and Virtuoso PDK
ACC100-like device as a demonstrator
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X-FAB MEMS Reference Kit
MEMS design flow
mechanical
Specification
electrical
Results
Viewer
Electrical
Design
Symbol
Schematic
Results
MEMS
Netlist
Netlist
Simulator
Layout
LVS
Re-Design
MEMS+ Core Design
MEMS+
CDS Import
PEX
.3dsch
MEMS+
behavioural
models
.mpdk
.proc
.mmdb
Primitive
Components
Layer
Definition
Material
Database
.tech
Layer
Definition
Design
Constraints
FAB PDK
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Netlist
Tape
Out
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DRC
.lib
MEMS
Primitives
PEX-Rules
LVS-Rules
Design-Rules
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Summary
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Summary
Feature-rich foundry MEMS-PDK for Cadence- and Coventor tools
• The MEMS-PDK acts as an process abstraction
– Process- and device parameters, material data base
– Design layers, design rules
encapsulates process information
less expert process knowledge required!
• The MEMS-PDK as an enabler of design automation
– interface to EDA tools
– Includes re-usable, predefined, process-specific components
– Pcells for layout generation
– Physical verification of implemented layout
less implementation effort, better quality
• MEMS PDK supports a continuous design flow using MEMS- and CMOS tools
X-FAB Reference Kits for easy adoption of the new design flows
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Thank you for your attention.

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