MOSIS - Nano Science and Technology Institute

SPICE BSIM3 Model Parameters
Extraction and Optimization for Low
Temperature Application
Henok Abebe
The MOSIS Service
USC Viterbi School of Engineering
Information Sciences Institute
Collaborators:
Vance Tyree
USC/ISI MOSIS, USA
Nankyung Suh Cockerham
USC/ISI MOSIS, USA
WCM 2009
MOSIS
Outline
MOSIS
• MOSIS Service.
• The room temperature SPICE model extraction and
optimization strategy .
• Room temperature simulation results.
• Model extraction and optimization for low temperature
application.
• Simulation results for temperature ranging from
-191 to 1250C .
• Conclusion
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What is MOSIS?
MOSIS
MOSIS is a low-cost prototyping and small-volume
production service for VLSI circuit development.
Since 1981, MOSIS has fabricated more than
50,000 circuit designs for commercial firms,
government agencies, and research and educational
institutions around the world.
URL: http://www.mosis.com
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The Customer Advantages
MOSIS
1. A Single Interface to the Semiconductor Industry
MOSIS provides designers with a single interface to the
constantly changing technologies of the semiconductor
industry. Mask generation, wafer fabrication, and device
packaging are contracted to leading industry vendors.
2. Low Cost
MOSIS keeps the cost of fabricating prototype quantities low
by aggregating multiple designs onto one mask set. This
allows customers to share overhead costs associated with
mask making and wafer fabrication.
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Advantages (continued)
MOSIS
3. Access to Technology
MOSIS provides access to a wide variety of semiconductor
processes offered by many different foundries:
AMIS (now part of ON Semiconductor),
austriamicrosystems, IBM, TSMC
4. Compatibility with Tools and Libraries
A variety of design flow (digital, analog, mixed-signal) can be
used with a number of different CAD tools, technology files,
design kits, libraries and IP to create designs for processes
accessed by MOSIS.
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Advantages (continued)
MOSIS
5. MOSIS provides electrical test data and SPICE
parameters for most wafer lots.
•Lot-specific parametric results and SPICE
device model parameters are extracted from
electrical measurements on wafers probed at
MOSIS.
•The MOSIS BSIM3v3 model parameters are
extracted using I-V data that are measured on a
large array of test transistors included in the
MOSIS process Monitor.
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MOSIS Process Monitor
MOSIS
• DC
Parametric Test Structures:
e.g. Contact resistance, sheet resistance, thin
and thick oxide transistor structures (N and P)
and variable ratio inverters.
• AC Parametric Test Structures
e.g. Area and fringe capacitors.
• Functional Test Structures for SPICE model
validation: Inverter and 31-stages ring
oscillator.
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MOSIS BSIM3V3 SPICE Model Support
MOSIS
1. AMIS 0.50 micron
2. AMIS 0.35 micron
3. AMIS 1.50 micron
4. TSMC 0.18 micron
5. TSMC 0.25 micron
SPICE level 3 model parameters
for classroom instructional purposes,
not for actual IC design work are
also available.
6. TSMC 0.35 micron
7. IBM 0.50 micron
8. IBM 0.35 micron
9. IBM 0.25 micron
10. IBM 0.18 micron
11. IBM 0.13 micron
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BSIM3V3 model extraction and optimization
strategy for room temperature application
MOSIS
•The models generated from our strategies serve the
IC design community at no cost, and the model
parameter sets give consistent accuracy, validated
against wafer electrical test data at MOSIS
•By simulating a design using MOSIS SPICE model
from several wafer lots, a designer can test his circuit
performance over past fabricated lots. Since typical
foundry processes are fairly stable, then simulation
using past history are useful for providing an
estimate of what circuit performance to expect in
future wafer lot.
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MOSIS
Strategy for room temperature (continued)
•Details on the MOSIS BSIM3V3 room temperature
model extraction and optimization strategy that is
friendly for automated production use is published in
2007:
H. Abebe, V. Tyree, H. Morris and P. T. Vernier, "SPICE BSIM3
model parameter extraction and optimization: Practical
consideration." IJEEE, Manchester University Press, Vol. 44,
Issue 03, pp 249-262, July (2007)
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Room temperature simulation results
Inverter gain simulation versus measured minimum,
maximum and mean percentage errors are shown for
different technologies. The minimum and maximum
are taken from single points in the data set, and the
mean represents the whole data set.
MOSIS
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Simulation results (continued)
31-stages ring oscillator simulation versus measured
minimum, maximum and mean percentage errors.
MOSIS
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Simulation results (continued)
MOSIS
Channel current versus gate voltage in a normal scale for Vds= 0.05 V and
Vbs= 0, -0.36,-0.72, -1.08, -1.44, -1.8 V. The solid lines are the simulated
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result, and the dashed lines are the measured data.
Simulation results (continued)
MOSIS
Channel current versus drain/source voltage in a normal scale forVgs =
1.01, 1.168, 1.326, 1.484, 1.642, 1.8 V and Vbs = 0 V. The solid lines are the
simulated result, and the dashed lines are the measured data.
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Simulation results (continued)
MOSIS
Output conductance in log scale versus drain/source voltage.
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Simulation results (continued)
MOSIS
Transconductance versus gate voltage.
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Model extraction and optimization for low
temperature application (T=-191oc)
MOSIS
1. The saturation velocity at temperature T is
T
− 1)
v sat (T ) = v sat (Tnom ) − AT (
Tnom
2. The threshold voltage model in BSIM3v3 is given by
Vth (T ) = Vth (Tnom ) + ( K T 1 + K T 1L / Leff
T
+ K T 2Vbseff )(
− 1)
Tnom
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Extraction and optimization (continued)
MOSIS
3. Source/Drain Parasitic Resistance
T
− 1)
Rdsw (T ) = Rdsw (Tnom ) + PRT (
Tnom
4. Carrier Mobility
T U TE
)
• μ 0 (T ) = μ 0 (Tnom )(
Tnom
T
• U i (T ) = U i (Tnom ) + U i1 (
− 1)
Tnom
where i=a, b and c.
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Extraction and optimization (continued)
MOSIS
Strategy 1: (Threshold and mobility parameters without
body bias effect)
This local strategy is applied for wide and long device only.
Target parameters: KT1, UTE, UA1 and UB1.
It requires Ids versus Vgs data with low Vds and varying Vbs.
Strategy 2: (Threshold and mobility parameters with
body bias effect)
This local strategy is applied for wide and long device only.
Target parameters: KT2 and UC1.
It requires Ids versus Vgs data with low Vds and varying Vbs.
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Extraction and optimization (continued)
MOSIS
Strategy 3: (Threshold and channel resistance parameters)
This local strategy is applied for wide and short device.
Target parameters: KT1L and PRT
It requires Ids versus Vgs data with low Vds and varying Vbs.
Strategy 4: (Low Bias Drain Saturated Current Parameters.)
This local optimization strategy uses only short channel devices.
Target parameter: AT.
It requires Ids versus Vds data with low |Vbs| and varying Vgs.
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Simulation results for temperature
T=-1910C
MOSIS
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NMOS device channel current versus source/drain voltage at -1910C.
for temperature T=-1910C
(continued)
PMOS device channel current versus source/drain voltage at -1910C
MOSIS
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for temperature T=-1910C
(continued)
PMOS device channel current versus gate voltage at -1910C.
MOSIS
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Simulation results for temperature
ranging from -191 to 1250C
Ring oscillator frequency (MHz)
150
Measured
Simulated
140
130
120
110
100
90
80
50
100
150
200
250
300
350
400
T(K)
%|error|
10
5
0
50
Error bar
Mean
100
150
200
250
T(K)
300
350
400
450
31-stages Ring oscillator frequency versus temperature.
MOSIS
Conclusion
MOSIS
• We believe the larger percentage error for high
temperature T=125oC compared to the low temperature
T=-191oC is due to the main uses of linear extrapolation
in the BSIM3v3 model to capture the temperature effect.
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