Chapter_3_Part_2

3.2 Shift Register
qBasic shift register function
qSerial in / serial out shift registers
qSerial in / parallel out shift registers
qParallel in / serial out shift registers
qParallel in / parallel out shift registers
qBidirectional shift registers
qShift register applications
Sequential Logic Circuits
Combinational
outputs
Memory outputs
Combinational
logic
Memory
elements
Inputs
Sequential circuit = Combinational logic + Memory Elements
Current State of A sequential Circuit:
Value stored in memory elements (value of state variables).
State transition:
A change in the stored values in memory elements thus changing
the sequential circuit from one state to another state.
Registers
qA register is a memory device that can be used to
store more than one-bit information
qA register is usually realized as several flip-flops
with common control signals that control the
movement of data to and from the register
qAn n-bit register is a collection of n D flip-flops
with a common clock used to store n related bits.
Example:
74LS175 4-bit register
74LS175
CLK
CLR
1D
2D
3D
4D
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
Shift Registers
qMulti-bit register that moves stored data bits
left/right ( 1 bit position per clock cycle)
q
q
RSI
Shift Left is towards MSB
Q3 Q2 Q1
Q0
0
1
1
1
Q3 Q2 Q1
LSI
1
1
Q0
1 LSI
Shift Right (or Shift Up) is towards LSB
Q3 Q2 Q1
Q0
0
1
1
1
Q3 Q2 Q1
RSI
0
1
Q0
1
Basic Shift Registers functions
qConsist of an arrangement of flip-flops
qImportant in applications involving storage and
transfer of data (data movement) in digital
system
qUsed for storing and shifting data (1s and 0s)
entered into it from an external source and
possesses no characteristic internal sequence of
states.
qD flip-flops are use to store and move data
The flip-flop as a storage element
Still remember the truth table for D flip flop?
D
1
0
CLK/C
↑
↑
Q
1
0
Q’
0
1
SET (stores as 1)
RESET (stores as 0)
When a 1 is on D, Q
becomes a 1 at triggering
edge of CLK or remains a
1 if already in the SET
state
When a 0 is on D, Q
becomes a 0 at triggering
edge of CLK or remains a
0 if already in the RESET
state
Types of shift register
1.
2.
3.
4.
Serial In / Serial Out Shift Registers (SISO)
Serial In /Parallel Out Shift Registers
(SIPO)
Parallel In / Serial Out Shift Registers
(PISO)
Parallel In / Parallel Out Shift Registers
(PIPO)
Basic data movement in shift
register
(Four bits are used for illustration. The bits move in the
direction of the arrows.)
Serial In, Serial Out Shift Register
(SISO)
SERIN
CLOCK
D
Q
CLK
D
SRG n
>
SI
SO
Q
For a n-bit SRG:
Serial Out = Serial In delayed by
n clock period
CLK
•
•
•
D
CLK
Q
4-bit shift register example:
Serial in: 1 0 1 1 0 0 1 1 1 0
Serial out: - - - - 1 0 1 1 0 0
SEROUT clock:
SISO
SISO
FF0
Clear
0
1010
0
101
0
10
1
1
0
Clear
1
FF1
0
0
0
0
1
0
FF2
0
0
0
0
0
1
FF3
0
0
0
0
0
0
0
00
000
0000
SISO
CLK
FF0
FF1
FF2
FF3
0
Clear
0
0
0
0
1
1011001110
0
0
0
0
2
101100111
0
0
0
0
3
10110011
1
0
0
0
4
1011001
1
1
0
0
5
101100
1
1
1
0
6
10110
0
1
1
1
0
7
1011
0
0
1
1
10
8
101
1
0
0
1
110
9
10
1
1
0
0
1110
10
1
0
1
1
0
01110
11
Clear
1
0
1
1
001110
SISO
SERIAL IN PARALLEL OUT SHIFT
REGISTER (SIPO)
SERIN
CLOCK
D
Q
1Q
CLK
D
Q
2Q
CLK
SRG n
>
SI
1Q
2Q
•
•
•
nQ
(PO)
Serial to Parallel Converter
•
•
•
D
CLK
Q
nQ
Example: 4-bit shift register
serin: 1 0 1 1 0 0 1 1 1 0
1Q: - 1 0 1 1 0 0 1 1 1
2Q: - - 1 0 1 1 0 0 1 1
3Q: - - - 1 0 1 1 0 0 1
4Q: - - - - 1 0 1 1 0 0
clock:
Can u see the difference?
SERIN
CLOCK
D
Q
1Q
CLOCK
CLK
D
SERIN
Q
2Q
D
Q
CLK
D
Q
CLK
CLK
•
•
•
•
•
•
D
CLK
Q
nQ
D
CLK
Q
SEROUT
SIPO
q Data bits entered serially (right-most bit first)
q Difference from SISO is the way data bits are taken
q out of the register – in parallel.
q Output of each stage is available
Example :
The states of 4-bit register (SRG 4) for the data input and
clocks waveforms.
Assume the register initially contains all 1s
PARALLEL IN SERIAL OUT SHIFT
REGISTER (PISO)
4 BIT PISO
When signal = 1,
àSHIFT
When signal = 0,
à LOAD
4 BIT PISO
When signal = 0,
àLOAD
G1 – G3
enabled
4 BIT PISO
When signal = 1,
àSHIFT
G4 – G6
enabled
4 BIT PISO
Can you try and trace the output for each FF stage until you get Q3?
EXAMPLE
1
0
1
Assume that the
signal has
values
011011 for 6
respective clock
cycle
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
0
0
1
0
1
0
1
0
CLK 1,
Signal = 0
G1 – G3
Will get value =
1
G4 – G6
Will get value =
0
Referring to the AND gate theory,
All gates that receives “0” values at shift/load can be ignored.
1
1
0
1
1
1
Now, AND the shift/load with respective Data bit, D0 – D3
0
1
0
1
0
1
0
1
CLK 2,
Signal = 1
G1 – G3
Will get value
=0
G4 – G6
Will get value
=1
Referring to the AND gate theory,
All gates that receives “0” values at shift/load can be ignored.
1
1
1
0
1
1
Now, AND the shift/load value with
Respective data that goes into G4, G5, G6
0
How do you put it in table?
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
Clk Shift/Load
Active
signal
Q0
Q1
Q2
Q3
0
Clear
Clear
0
0
0
0
1
0
LOAD
1
0
1
0
2
1
SHIFT
1
1
0
1
3
1
SHIFT
1
1
1
0
4
0
LOAD
1
0
1
0
5
1
SHIFT
1
1
0
1
6
1
SHIFT
1
1
1
0
Can you try and trace the output for each FF stage until
you get Q3?
PISO
PARALLEL IN PARALLEL OUT SHIFT
REGISTER (PIPO)
q
Immediately following simultaneous entry of all data bits,
it appear on parallel output.
PIPO
PIPO
Bi-directional Shift Registers
qData can be shifted left
qData can be shifted right
qA parallel load maybe possible
q74HC194 is a bidirectional universal shift register
Bi-directional UNIVERSAL Shift
Registers
11
1
Modes:
Hold
Load
Shift Right
Shift Left
10
9
7
6
5
4
3
2
CLK
CLR
S1
S0
LIN
D
C
B
A
RIN
74x194
R
QD
QC
QB
QA
L
12
13
14
15
4-bit Bi-directional Universal (4-bit) PIPO
Function
Hold
Shift right/up
Shift left/down
Load
Mode
S1 S0
0
0
0
1
1
0
1
1
Next state
QA* QB* QC*
QA QB QC
RIN QA QB
QB QC QD
A
B
C
QD*
QD
QC
LIN
D
Four-bit Johnson counters
Serial output
connected back
to serial input
n The complement
of the output
(Q’) is feedback
into 1st FF.
n
FIVE-bit Johnson counters
A 10-bit ring counter
n
Assume initial state :
0000000101
Shift Register Applications
q State Registers
o Shift registers are often used as the state register in a
sequential device. Usually, the next state is determined
by shifting right and inserting a primary input or output
into the next position (i.e. a finite memory machine)
o Very effective for sequence detectors
q Serial Interconnection of Systems
o keep interconnection cost low with serial interconnect
Shift Register Applications
q
Bit Serial Operations
o
o
o
Bit serial operations can be performed quickly through
device iteration
Iteration (a purely combinational approach) is expensive
(in terms of # of transistors, chip area, power, etc).
A sequential approach allows the reuse of combinational
functional units throughout the multi-cycle operation
EXAMPLE:
1. Serial Interconnection of Systems
2. The shift register as a time-delay device