G P S Locking the IC 910-H
Transcription
G P S Locking the IC 910-H
By Rex Moncur VK7MO GPS Locking the IC 910-H GPSDO 10 MHz PLL & 30.2 MHz Osc 30.2 MHz IC 910-H BLOCK DIAGRAM External Oscillator Input Circuit Mods to IC 910-H Internal Mods to IC 910-H 30.2 MHz Oscillator and PLL PLL Block Diagram PLL Construction 1 Hz 50 mHz Stability at 1296 MHz Receiver & Sig Gen locked to same GPS Receiver & Sig Gen locked to separate GPSs Tc = 3000 micro-seconds Phase Noise at 5 Hz = -45 dBc/Hz Tc = 20 micro-seconds Phase Noise at 5 Hz = -55 dBc/Hz 1296 MHz: Yellow = PLL with cheap Hi-Q Oscillator, Blue = HP Sig Gen Phase Noise v Loop Time Constant Phase Noise for both at 5 Hz = -70 dBc/Hz 10 Hz off 10 Hz off 1296 MHz: Yellow = Oven Oscillator, Blue = HP Sig Gen Phase Noise with Oven Oscillator -70 dBc/Hz -34 dBc/Hz • HP SigGen • 10 GHz DB6NT Trans. • 161 PLL with Oven Osc -70 dBc/Hz • RigLock with Hi-Q Osc -58 dBc/Hz • 161 PLL with Hi-Q Osc -55 dBc/Hz 5 Hz Phase Noise at 1296 MHz • Need a good quality oscillator to get lowest phase noise. • Hum can be a problem – mount in shielded box and bypass liberally with electrolytics. • Stability is better than 0.1 Hz at 1296 MHz and more than adequate for JT65a. • Accuracy is better than 1 Hz at 1296 MHz CONCLUSIONS