FINITE STATE MACHINES (FSM) DESCRIPTION IN VHDL

FINITE STATE MACHINES (FSM) DESCRIPTION IN VHDL

FINITE STATE MACHINES (FSM)
DESCRIPTION IN VHDL
Cristian Sisterna
UNSJ
FSM Review
2


A sequential circuit that is implemented in a fixed
number of possible states is called a Finite State
Machine (FSM).
Finite state machines are critical for realizing the
control and decision-making logic in a digital system.


Finite state machines have become an integral part of
the system design.
VHDL has no formal format for modeling finite state
machines.

FSM - DSDA
To model a finite state machine in VHDL certain
guidelines must be followed.
Cristian Sisterna
FSM Example
3
Realizar la descripción en VHDL de un receptor y transmisor serie
tipo RS-232. El dato recibido y el dato a transmitir debe tener el
siguiente formato:
1 bit de start
8 bits de datos
Paridad programable: paridad/no paridad, par/impar
1 bit de stop
Frecuencia de transmisión por defecto es de 9600 Bauds, pero
el código debe permitir también otras frecuencias como: 4800,
38400, 115200 Bauds.
FSM - DSDA
Cristian Sisterna
FSM Example
4
RS-232 Tx format
FSM - DSDA
Cristian Sisterna
State Machine State Diagram
5
FSM - DSDA
Cristian Sisterna
FSM General Schemes
FSM - DSDA
Cristian Sisterna
State Machine General Scheme 1
7
Inputs
Next
State
Next
State
Logic
Logic
Next
State
Current
Current
State
State
Logic
Logic
Current
State
Output
Output
Logic
Logic
Outputs
Clk
Rst
FSM - DSDA
Cristian Sisterna
State Machine General Scheme 2
8
Inputs
Next
Next
State
State
Logic
Logic
Next
State
Current
Current
State
State
Logic
Logic
Current
State
Output
Output
Logic
Logic
Synchr.
Sync
Output
Output
FFs
Logic
Outputs
Clk
Rst
FSM - DSDA
Cristian Sisterna
State Machine General Scheme 3
9
Synchr. and
Output Logic
Inputs
Next
Next
State
State
Logic
Logic
Next
State
Current
Current
State
State
Logic
Logic
Current
State
Output A
...
...
Synchr. and
Output Logic
Output Z
Clk
Rst
FSM - DSDA
Cristian Sisterna
State Machine - Special Case 1
10
Synchr.
Sync
Output
Output
FFs
Logic
Inputs
Next
Next
State
State
Logic
Logic
Next
State
Current
Current
State
State
Logic
Logic
Outputs
Current
State
Clk
Rst
FSM - DSDA
Cristian Sisterna
FSM – VHDL Considerations
FSM - DSDA
Cristian Sisterna
FSM VHDL General Design Flow
12
Specifications
Understand the
Problem
Traditional Steps
Draw the ASM or State
Diagram
Define an FSM
Enumerated Type
Define FSM
Signals
+
VHDL Steps
Select an Encoding
Technique (optional)
Write the VHDL
Code
FSM - DSDA
Cristian Sisterna
FSM Enumerated Type Declaration
FSM - DSDA
Cristian Sisterna
FSM Enumerated Type Declaration
14
Declare an enumerated data type with values (names) the states of
the state machine
-- declare the states of the state-machine
-- as enumerated type
Symbolic State
Names
type FSM_States is(IDLE,START,STOP_1BIT,PARITY,SHIFT);
Declare the signals for the next state and current state of the state
machine as signal of the enumerated data type already defined
for the state machine
-- declare signals of FSM_States type
signal current_state, next_state: FSM_States;
The only values that current_state and next_state can hold are:
IDLE,START,STOP_1BIT,PARITY,SHIFT
FSM - DSDA
Cristian Sisterna
FSM – Encoding Techniques
FSM Encoding Techniques
16
type FSM_States is(IDLE, START, STOP_1BIT, PARITY, SHIFT);
signal current_state, next_state: FSM_States;
State Assignment
 During synthesis each symbolic state name has to be
mapped to a unique binary representation


A good state assignment can reduce the circuit size
and increase the clock rate (by reducing
propagation delays)
The hardware needed for the implementation of
the next state logic and the output logic is directly
related to the state assignment selected
FSM - DSDA
Cristian Sisterna
FSM Encoding Schemes
17
An FSM with n symbolic states requires at least [log2 n ]
bits to encode all the possible symbolic values
Commonly used state assignment schemes:
 Binary: assign states according to a binary sequence
 Gray: use the Gray code sequence for assigning
states
 One-hot: assigns one ‘hot’ bit for each state
 Almost one-hot: similar to one-hot but add the all
zeros code (initial state)
FSM - DSDA
Cristian Sisterna
FSM Encoding Schemes
18
Binary
Gray
One-Hot
Almost One-hot
idle
000
000
00001
0000
start
001
001
00010
0001
stop_1bit
010
011
00100
0010
parity
011
010
01000
0100
shift
100
110
10000
1000
FSM - DSDA
Cristian Sisterna
Encoding Schemes in VHDL
19
During synthesis each symbolic state name has to be
mapped to a unique binary representation
How is the map process done ?
user attribute
(synthesis attribute)
explicit user-defined
assignment
FSM - DSDA
enum_encoding
(VHDL standard
default encoding
Cristian Sisterna
syn_encoding – Quartus & Synplify
20
•
syn_encoding is the synthesis user-attribute of Quartus
(Synplify) that specifies encoding for the states modeled by an
enumeration type
•
To use the syn_encoding attribute, it must first be
declared as string type. Then, assign a value to it, referencing
the current state signal.
-- declare the (state-machine) enumerated type
type my_fms_states is (IDLE,START,STOP_1BIT,PARITY,SHIFT);
-- declare signals as my_fsm_states type
signal nxt_state, current_state: my_fsm_states;
-- set the style encoding
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states : type is “one-hot”;
FSM - DSDA
Cristian Sisterna
syn_encoding - Quartus & Synplify
21
Possible values:
 default: assign an encoding style based on the number of states:
 Sequential encoding for 0 - 4 enumerated types
 One-hot encoding for 5 – 50 enumerated types
 Gray encoding for > 50 enumerated types
 sequential:
000 001 010 011 100 101 110 111
 one-hot: 0000001 00000010 00000100 . . .
 gray:
000 001 011 010 110 111 101 100
 johnson :
0000 0001 0011 0111 1111 1110 1100 1000
 safe: default encoding + reset logic to a known state
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states: type is “one-hot, safe”;

user-defined: assign an encoding style defined by the user
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states: type is “10 11 01 00”;
FSM - DSDA
Cristian Sisterna
Examples of Synthesis Reports (Quartus)
22
FSM - DSDA
Cristian Sisterna
Results for Different Encoding Schemes
23
Simple, 5 states, state machine
One-hot
safe
One-hot
Gray
Gray-Safe
Binary
Johnson
Total
combinatio
nal
functions
76
66
66
68
66
68
Dedicated
logic
registers
45
45
43
43
43
43
Max. frq.
352.24
340.95
331.02
335.01
338.34
311.72
FSM - DSDA
Cristian Sisterna
Results for Different Encoding Schemes
24
19 states, state machine
One-hot
safe
One-hot
Gray
Gray-Safe
Binary
Johnson
Total
combinati
onal
functions
556
523
569
566
561
573
Dedicated
logic
registers
215
215
201
201
201
206
Max. frq.
187.3
175.22
186.39
180.6
197.63
186.22
FSM - DSDA
Cristian Sisterna
Xilinx XST State Encoding Techniques
25
XST (the synthesis tool for ISE) supports the following
state encoding techniques:
Auto-State Encoding
One-Hot Encoding
Gray State Encoding
Compact State Encoding
Johnson State Encoding
Sequential State Encoding
Speed1 State Encoding
User State Encoding
FSM - DSDA
Cristian Sisterna
XST State Encoding Techniques
26
Declare the attribute as follows:
attribute fsm_encoding: string;
Specify as follows:
attribute fsm_encoding of {entity_name|signal_name }:
{entity |signal} is "{auto | one-hot | compact|
sequential| gray| Johnson | speed1|user}";
The default is auto
FSM - DSDA
Cristian Sisterna
Precision State Encoding Techniques
27
Possible values:
• Binary
Declare the attribute as follows:
attribute type_encoding_stype string;
• Onehot
• Twohot
• Gray
• Random
-- Declare the (state-machine) enumerated type
type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);
-- Set the type_encoding_style of the state type
attribute type_encoding_style of my_state_type:type is ONEHOT;
Note: precision is a synthesis tool available in some FPGA vendor’s software
FSM - DSDA
Cristian Sisterna
Precision State Encoding Techniques
28
type_encoding_style allows to fully control the state
encoding hard code the state code in the source code
-- Declare the (state-machine) enumerated type
type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);
-- Set the type_encoding attribute
attribute type_encoding_style of my_state_type:type is
("0001","01--","0000","11--","0010");
State
Table
Note: Precision allows to use ‘-’. It can be used to reduce the size of the circuit
FSM - DSDA
Cristian Sisterna
State Machine Coding: Residual States
29


If one-hot state coding is not used, the maximum
number of states is equal to 2**N, where N is the vector
length of the state vector
In state machines where not all the states are used,
there are three options:
Let chance decide what is to happen if the machine goes to
an undefined state
 Define what is to happen if the state machine goes to an
undefined state by ending the case statement with when
others
 Define all the possible states in the VHDL code

FSM - DSDA
Cristian Sisterna
State Machine Coding: Synplify Report
30
FSM - DSDA
Cristian Sisterna
State Machine Coding: XST Report
31
==============================================
*
Advanced HDL Synthesis
*
==============================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <rs232_tx/tx_current_state/FSM> on signal
<tx_current_state[1:3]> with sequential encoding.
----------------------------State
| Encoding
----------------------------idle
| 000
start
| 001
shift
| 010
parity
| 011
stop_1bit | 100
-----------------------------
FSM - DSDA
Cristian Sisterna
State Machine Coding: Quartus Report
32
FSM - DSDA
Cristian Sisterna
State Machine Coding: Simulation
33
FSM - DSDA
Cristian Sisterna
FSM Style Description Example
State Machine VHDL Coding Styles
35
Inputs
Next
Next
State
State
Logic
Logic
Current
Current
State
State
Logic
Logic
Next
State
Current
State
Output
Output
Logic
Logic
Outputs
CLK
RST
Coding Style
Current State
Next State Logic
Output Logic
Style E
Seq. Logic
Comb. Logic
Seq. Logic
Style A
Seq. Logic
Comb. Logic
Comb. Logic
Style C
Style D
Style B
FSM - DSDA
Seq. Logic
Comb. Logic
Seq. Logic
Comb. Logic
Seq. Logic
Cristian Sisterna
FSM: Clocked Process for Current State
36





The current_state clocked process decides when the state machine
should change state
This process is activated by the state machine’s clock signal
Depending on the current state and the value of the input signals,
the state machine can change state at every active clock edge
Current state gets the value of the next state on the active edge of
the clock
The next state value is generated in the next state process
(combinational process), depending on the values of current state
and the inputs
Cristian Sisterna
FSM - DSDA
FSM: Combinational Process
37
Next State and Output Logic





Assigns the output signals their value depending on the current state
Assigns the next state value depending on the current state and the
input’s value(s)
Next state logic and output logic is best modeled using case
statements are better for this process
All the rules of combinatorial process have to be followed to avoid
generating unwanted latches
For Mealy Machines if-then-else statement is used to create
the dependency between the current state, the input signals and
output signals
FSM - DSDA
Cristian Sisterna
State Machine: Reset behavior
38


Asynchronous reset: ensure that the state machine
is always initialized to a known valid state, before
the first active clock transition and normal operation
commences
No reset : there is no way to predict the initial value
of the state register flip-flops. It could power up
and become permanently stuck in an uncoded state.
FSM - DSDA
Cristian Sisterna
FSM Style Descriptions - Example
39
Moore FSM
X=0
X=0
S1
Z=1
S0
Z=0
X=1
X=1
Mealy FSM
X=0
Z=1
X=0
Z=0
S1
S0
X=1
Z=1
X=1
Z=0
FSM - DSDA
Cristian Sisterna
Style E - Moore State Machine
40
Comb. Next State Logic
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
process (state, X)
begin
case state is
when S0
=> Present State Logic
Seq.
if(X=‘0’) then
next_state
<= rst)
S0;
process (clk,
else(X=‘1’) then
begin
next_state <= S1;
if(rst = ‘1’) then
end if;
state <= S0;
when S1 =>
elsif (rising_edge(clk)) then
if ….
state <= next_state;
next_state <= .. ;
end if;
….
end process;
when others =>
….
end case;
end process;
Seq. Output Logic
state
Current
State Logic
Clk
Rst
FSM - DSDA
process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
Z <= ‘0’;
when S1 =>
Z <= ‘1’;
when others =>
Z <= ‘1’;
end case;
end process;
Output
Logic
Cristian Sisterna
Z
Style E - Moore State Machine
41
Comb. Next State Logic
Seq. Output Logic
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
Seq. Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk))
then
state <= next_state;
end if;
end process;
state
process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk))
then
case state is
when S0 =>
Z <= ‘0’;
when S1 =>
Z <= ‘1’;
when others =>
Z <= ‘1’;
end case;
end process;
Clk
Rst
FSM - DSDA
Cristian Sisterna
Z
Style E - Moore State Machine
42
-- VHDL code example for an FSM
library ieee;
use ieee.std_logic_1164.all;
entity my_fsm is
port(
x: in std_logic;
clk: in std_logic;
rst: in std_logic;
z: out std_logic );
end entity my fsm;
architecture beh of my_fsm is
-- fsm enumerated type declaration
type fsm_states is (S0, S1);
-- fsm signal declarations
signal next_state, state: fsm_states;
begin
-- current state logic
cst_pr: process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process cst_pr;
FSM - DSDA
-- next state logic
nxt_pr:process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process nxt_pr;
- - output logic
out_pr:process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
Z <= ‘0’;
when S1 =>
Z <= ‘1’;
when others => Z<= ‘1’;
end case;
end process out_pr;
end architecture beh;
Cristian Sisterna
Style E - Mealy State Machine
43
Comb.Next State Logic
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
Clk
Rst
Seq. Output Logic
Seq.Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk))
then
state <= next_state;
end if;
end process;
state
process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X = ‘0’) then
Z <=…;
else
Z <=... ;
end if;
when S1 =>
if (X = ‘1’) then
.... ;
else
.... ;
end if;
when others =>
Z<=‘0’;
end case;
end if;
end process;
Warning on Mealy Outputs !
FSM - DSDA
Cristian Sisterna
Z
Style A - Moore State Machine
44
Comb. Next State Logic
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
X
Comb.Output Logic
Seq. Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk))
then
state <= next_state;
end if;
end process;
state
process (state)
begin
Z <= ‘0’; -- default value
case state is
when S0 => Z <= ‘0’;
when S1 => Z <= ‘1’;
when others => Z <= ‘0’;
end case;
end process;
Clock
Reset
FSM - DSDA
Cristian Sisterna
Z
Style A – Moore Synthesis
45
FSM - DSDA
Cristian Sisterna
Style A - Mealy State Machine
46
Comb. Next State Logic
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
Comb. Output Logic
Seq. Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
process (state, X)
begin
case state is
when S0 =>
if (X = ‘0’) then
Z <=…;
else
Z <=... ;
end if;
when S1 =>
if (X = ‘1’) then
.... ;
else
.... ;
end if;
when others =>
Z<=‘0’;
end case;
end process;
Clock
Reset
FSM - DSDA
Cristian Sisterna
Z
Style A – Mealy Synthesis
47
Mealy
FSM - DSDA
Cristian Sisterna
Style A – Moore & Mealy State Machine
48
Comb.Output Logic Moore
Comb. Next State Logic
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
Clock
Reset
Hypothetical case
FSM - DSDA
Seq. Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
process (state)
begin
case state is
when S0 => Y <= ‘1’;
when S1 => Y <= ‘0’;
when others => Y <= ‘0’;
end case;
end process;
Y
Comb. Output Logic - Mealy
process (state, X)
begin
case state is
when S0 =>
if (X = ‘0’) then
Z <=…;
...
end if;
when S1 =>
if (X = ‘1’) then
.... ;
end if;
when others =>
Z<=‘0’;
end case;
end process;
Cristian Sisterna
Z
Style B - Moore State Machine
Seq. State, Next State and Output Logic
49
X
process(clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X=’0’) then
state <= S0;
elsif (X=’1’) then
state <= S1;
end if;
Z <=‘0’;
when S1 =>
if (X = ‘0’) then
...
end if;
Z <= ‘1’ ;
end case;
end if;
end process;
Z
Clk
Rst
FSM - DSDA
Cristian Sisterna
Style B - Mealy State Machine
50
Seq. State, Next State and Output Logic
X
process(clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X=’0’) then
state <= .... ;
Z <= ... ;
elsif (X=’1’) then
state <= .... ;
Z <= ... ;
end if;
when S1 =>
if (X = ‘0’) then
...
end if;
end case;
end if;
end process;
Z
Reset
Clock
FSM - DSDA
Cristian Sisterna
Style B – Moore Synthesis
51
FSM - DSDA
Cristian Sisterna
Style B – Mealy Synthesis
52
FSM - DSDA
Cristian Sisterna
Style C - Moore State Machine
53
Seq. Present State and Next State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
State <= S0;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if(X =’1’) then
state <=S1;
end if;
when S1 =>
if( X = ‘1’) then
state <=S0;
end if;
end case;
end if;
end process;
X
Comb. Output Logic
process (state)
begin
case state is
when S0 => Z <=‘0’;
when S1 => Z <=‘1’;
when others Z <=‘0’
end case;
end process;
Clk
Rst
FSM - DSDA
Cristian Sisterna
Z
Style C - Mealy State Machine
54
Seq. Present State and Next State Logic
Comb. Output Logic
process (clk, rst)
begin
if(rst = ‘1’) then
State <= S0;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if(X =’1’) then
state <=S1;
end if;
when S1 =>
if( X = ‘1’) then
state <=S0;
end if;
end case;
end if;
end process;
X
process (state, X)
begin
case state is
when S0 =>
if(X=’1’) then
Z <= ... ;
else
Z <= ... ;
end if;
when S1 =>
if(X=’1’) then
Z <= ... ;
else
Z <= ... ;
end if;
end case;
end process;
Clk
Rst
FSM - DSDA
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Z
Style C – Moore State Machine
55
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Style C - Mealy State Machine
56
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Style D - Moore State Machine
57
Comb. Next State and Output Logic
process (state, X)
begin
next_state <= state;
case state is
when S0 =>
if(X =’1’) then
next_state <=S1;
end if;
Z <=‘0’;
when S1 =>
if( X = ‘1’) then
next_state <=S0;
end if;
Z <=‘1’;
end case;
end process;
X
Z
Seq. Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
Clk
Rst
FSM - DSDA
Cristian Sisterna
Style D - Mealy State Machine
58
Comb. Next State and Output Logic
Z
process (state, X)
begin
next_state <= state;
Z <= ... ;
case state is
when S0 =>
if(X =’1’) then
next_state <= ... ;
Z <= ... ;
end if;
when S1 =>
if( X = ‘1’) then
next_state <= ... ;
Z <= ... ;
end if;
end case;
end process;
X
Seq. Present State Logic
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
Clk
Rst
FSM - DSDA
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Style D – Moore State Machine
59
FSM - DSDA
Cristian Sisterna
Style D - Mealy State Machine
60
FSM - DSDA
Cristian Sisterna
FSM Example
FSM - DSDA
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Another Example: Memory Controller FSM
62
Let’s try to obtain an state diagram of a hypothetical memory controller FSM that has the
following specifications:
The controller is between a processor and a memory chip, interpreting commands from the
processor and then generating a control sequence accordingly. The commands, mem, rw and
burst, from the processor constitute the input signals of the FSM. The mem signal is asserted to
high when a memory access is required. The rdwr signal indicates the type of memory access,
and its value can be either ’1’ or ’0’, for memory read and memory write respectively. The
burst signal is for a special mode of a memory read operation. If it is asserted, four
consecutive read operations will be performed. The memory chip has two control signals, oe
(for output enable) and we (for write enable), which need to be asserted during the memory
read and memory write respectively. The two output signals of the FSM, oe and we, are
connected to the memory chip’s control signals. For comparison purpose, let also add an
artificial Mealy output signal, we_mealy , to the state diagram. Initially, the FSM is in the idle
state, waiting for the mem command from the processor. Once mem is asserted, the FSM
examines the value of rdwr and moves to either the read1 or the write state. The input
conditions can be formalized to logic expressions, as shown below:

mem’ : represents that no memory operation is required (mem=‘0’)

mem.rdwr: represents that a memory read operation is required (mem=rdwr=‘1’).

mem.rdwr’: represents that a memory write operation is required (mem=‘1’; rdwr=‘0’)
Based on an example from the “RTL Hardware Design Using VHDL” book, By Pong Chu
FSM - DSDA
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Memory Controller FSM
63
Address Bus
Data Bus
Processor
Memory IC
mem
burst
oe
rdwr
Memory
Controller FSM
we
we_mealy
FSM - DSDA
Cristian Sisterna
Memory Controller FSM
64
mem’
idle
burst’
mem.rdwr’
mem.rdwr
we_mealy
read1
oe
burst
write
we
read2
oe
read3
oe
read4
oe
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Memory Controller FSM
65
idle
mem
rdwr
read1
oe
burst
we_mealy
write
we
read2
oe
read3
oe
read4
oe
FSM - DSDA
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Memory Controller FSM – VHDL Code
66


Entity-Architecture Declarations
FSM enumeration type declaration, FSM signal declarations
library ieee ;
use ieee.std_logic_1164.all;
entity mem_ctrl is
port (
clk, reset
: in std_logic;
mem, rdwr, burst: in std_logic;
oe, we, we_mealy: out std_logic
);
end mem_ctrl ;
architecture mult_seg_arch of mem_ctrl is
type fsm_states_type is
(idle, read1, read2, read3, read4, write);
signal crrnt_state, next_state: fsm_states_type;
begin
FSM - DSDA
Cristian Sisterna
Memory Controller FSM – VHDL Code
67

Current state process
−− current state procesee
cs_pr: process (clk, reset)
begin
if(reset = ’1’) then
crrnt_state <= idle ;
elsif(rising_edge(clk))then
crrnt_state <= next_state;
end if;
end process cs_pr;
FSM - DSDA
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Memory Controller FSM – VHDL Code
68

Next state process (1)
−− next−state logic
nxp:process(crrnt_state,mem,rdwr,burst)
begin
case crrnt_state is
when idle =>
if mem = ’1 ’ then
if rw = ’1’ then
next_state <= read1;
else
next_state <= write;
end if;
else
next_state <= idle;
end if;
when write =>
next_state <= idle;
FSM - DSDA
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Memory Controller FSM – VHDL Code
69

Next state process (2)
when read1 =>
if (burst = ’1’) then
next_state <= read2;
else
next_state <= idle;
end if;
when read2 =>
next_state <= read3;
when read3 =>
next_state <= read4;
when read4 =>
next_state <= idle;
when others =>
next_state <= idle;
end case;
end process nxp;
FSM - DSDA
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Memory Controller FSM – VHDL Code
70

Moore outputs process
FSM - DSDA
−− Moore output logic
moore_pr: process (crrnt_state)
begin
we <= ’0’; −− default value
oe <= ’0’; −− default value
case crrt_state is
when idle => null;
when write =>
we <= ’1’;
when read1 =>
oe <= ’1’;
when read2 =>
oe <= ’1’;
when read3 =>
oe <= ’1’;
when read4 =>
oe <= ’1’;
when others => null;
end case ;
end process moore_pr;
Cristian Sisterna
Memory Controller FSM – VHDL Code
71

Mealy output process
−− Mealy output logic
mly_pr: process(crrt_state,mem,rdwr)
begin
we_me <= ’0’; −− default value
case state_reg is
when idle =>
if (mem=’1’)and(rdwr =’0’)then
we_me <= ’1’;
end if;
when write => null;
when read1 => null;
when read2 => null;
when read3 => null;
when read4 => null;
end case;
end process mly_pr;
FSM - DSDA
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Memory Controller FSM – VHDL Code
72

Mealy output statement
−− Mealy output logic
we_me <= ’1’ when ((crrnt_state=idle) and (mem=’1’) and(rdwr=’0’))
else
’0’;
FSM - DSDA
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Another Example
FSM - DSDA
Cristian Sisterna
FSM Example – RS232
74
Realizar la descripción en VHDL de un receptor y transmisor serie
tipo RS-232. El dato recibido y el dato a transmitir debe tener el
siguiente formato:
1 bit de start
8 bits de datos
Paridad programable: paridad/no paridad, par/impar
1 bit de stop
Frecuencia de transmisión por defecto es de 9600 Bauds, pero
el código debe permitir también otras frecuencias como: 4800,
38400, 115200 Bauds.
FSM - DSDA
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FSM Example – RS232
75
RS-232 Tx format
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FSM Example – RS232
76
SysClock
Div.
Frec.
Parity
En
SysReset
Dato(7:0)
DatoSent
StartTx
FSM - DSDA
FSM
RS232 Tx Controller
DatoSerie
??
Cristian Sisterna
FSM Example – RTL Synthesis View
77
FSM - DSDA
Cristian Sisterna
FSM Example – Quartus State diagram
78
FSM - DSDA
Cristian Sisterna
FSM Example: Solution 2 - RTL Viewer
79
RTL Viewer
Double click
FSM - DSDA
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FSM Example: Solution 2- RTL Viewer
80
Double click
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FSM Example: Solution 2 – FSM Viewer
81
FSM - DSDA
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Synpsys FSM Viewer
82
In this case a clock enable is used.
FSM - DSDA
Cristian Sisterna
FSM Example – RS232 Other Approach
83
Div.
Frec.
SysClock
Parity
00
En
SysReset
DatoSerie
01
Dato(7:0)
E1
E0
DatoSent
StartTx
??
FSM
RS232 Tx Controller
Reg
Desplaz
amiento
10
Done
StartStopBit
Sel1, Sel0
FSM - DSDA
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Interacting State Machines
Interacting FSM
85
Controller FSM
Transmitter FSM
Ld_Tx’
CS1
TS1
Tx_busy’
TS4
Tx_busy
CS2
Ld_Tx
TS2
Tx_busy
CS3
Tx_busy
Tx_busy’
TS3
Tx_busy
Ld_Tx’
FSM - DSDA
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Interacting FSM
86
Controller
FSM
Processes
Inputs
Next
State
Process
Next
State
Current
State
Process
Output
Process
Outputs
Current
State
Tx_busy
Clk
Rst
Ld_Tx
Inputs
Next
State
Process
Next
State
Current
State
Process
Current
State
Output
Process
ctrl_tx.vhd
Outputs
Transmitter
FSM
Processes
FSM - DSDA
Cristian Sisterna
Interacting FSM
87
cntrl_fsm.vhd
Inputs
Next
State
Process
Next
State
Current
State
Process
Output
Process
Current
State
Outputs
Ld_Tx
Clk
Rst
Tx_busy
Inputs
Next
State
Process
Next
State
Current
State
Process
Current
State
Output
Process
Outputs
tx_fsm.vhd
FSM - DSDA
Cristian Sisterna