schem,mlb_ldo,k6

Transcription

schem,mlb_ldo,k6

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1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
1
ECN
DESCRIPTION OF REVISION
CK
APPD
DATE
2010-03-18
SCHEM,MLB_LDO,K6
D
D
PVT, 3/18/10
(.csa)
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
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B
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Contents
Sync
1
Table of Contents
07/20/2009
07/20/2009
07/20/2009
07/22/2009
07/20/2009
K24_MLB
7
FUNC TEST
08/19/2009
K24_MLB
5
Revision History
K69_MLB
4
BOM Configuration
TABLE_TABLEOFCONTENTS_HEAD
08/19/2009
K69_MLB
3
Power Block Diagram
05/20/2009
K17_MLB
2
System Block Diagram
(.csa)
K24_MLB
8
Power Aliases
K24_MLB
SIGNAL ALIAS
K24_MLB
9
10
CPU FSB
08/27/2009
07/20/2009
11/23/2009
07/28/2009
11/05/2009
08/06/2009
11/05/2009
T27_MLB
11
CPU Power & Ground
T27_MLB
12
CPU Decoupling
T27_MLB
13
eXtended Debug Port (mini-XDP)
T27_MLB
14
MCP CPU Interface
T27_MLB
15
MCP Memory Interface
T27_MLB
MCP PCIe Interfaces
T27_MLB
MCP Graphics
T27_MLB
16
17
18
MCP SATA, USB & Ethernet
MCP HDA, LPC & MISC
MCP89 GFX Core Rail Gating
T27_MLB
MCP Standard Decoupling
T27_MLB
25
26
08/06/2009
11/23/2009
11/23/2009
08/15/2009
08/06/2009
07/28/2009
07/28/2009
07/28/2009
06/19/2009
09/29/2009
07/28/2009
T27_MLB
28
SB Misc
11/23/2009
T27_MLB
24
MCP Graphics Support
T27_MLB
23
MCP89 Memory Rail Gating
11/23/2009
T27_MLB
20
MCP Power & Ground
11/05/2009
T27_MLB
19
T27_MLB
29
DDR3 SO-DIMM Connector A
T27_MLB
31
DDR3 SO-DIMM Connector B
T27_MLB
32
DDR3 BYTE/BIT SWAPS-K6
K18_MLB
33
FSB/DDR3 Vref Margining
T27_MLB
RIGHT CLUTCH CONNECTOR
T27_MLB
34
35
SecureDigital Card Reader
Ethernet PHY (Caesar II/IV)
08/20/2009
07/28/2009
07/20/2009
12/15/2009
T27_MLB
41
FireWire LLC/PHY (FW643E)
T27_MLB
FireWire Port & PHY Power
T27_MLB
42
43
FireWire Connector
T27_MLB
40
Ethernet Connector
09/30/2009
T27_MLB
39
07/28/2009
08/06/2009
T27_MLB
45
SATA Connectors
T27_MLB
External USB Connectors
T27_MLB
Internal USB Support
T27_MLB
SMC
T27_MLB
SMC Support
T27_MLB
LPC+SPI Debug Connector
T27_MLB
K6 SMBUS CONNECTIONS
T27_MLB
Voltage Sensing
T27_MLB
Current Sensing
T27_MLB
Thermal Sensors
T27_MLB
46
Date
Page
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47
48
49
50
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57
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59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Contents
Sync
56
07/20/2009
Fan
K24_MLB
WELLSPRING 1
T27_MLB
WELLSPRING 2
T27_MLB
Sudden Motion Sensor (SMS)
T27_MLB
SPI ROM
T27_MLB
AUDIO: CODEC/REGULATOR
AUDIO
AUDIO: LINE INPUT FILTER
AUDIO
AUDIO: HEADPHONE FILTER
AUDIO
AUDI0: SPEAKER AMP
AUDIO
AUDIO: JACK
AUDIO
AUDIO: JACK TRANSLATORS
AUDIO
DC-In & Battery Connectors
K24_MLB
PBus Supply & Battery Charger
T27_MLB
5V/3.3V SUPPLY
K24_MLB
1.5V/1.35V LVDDR3 Supply
T27_MLB
IMVP6 CPU VCore Regulator
K24_MLB
MCP VCore Regulator
T27_MLB
CPU VTT(1.05V) SUPPLY
K24_MLB
Misc Power Supplies
T27_MLB
Power Sequencing
T27_MLB
Power FETs
T27_MLB
LVDS CONNECTOR
K24_MLB
DISPLAYPORT SUPPORT
K69_MLB
DisplayPort Connector
K24_MLB
LCD Backlight Driver
K69_MLB
LCD Backlight Support
T27_MLB
CPU/FSB Constraints
T27_MLB
Memory Constraints
T27_MLB
MCP Constraints 1
T27_MLB
MCP Constraints 2
T27_MLB
Ethernet Constraints
T27_MLB
FireWire Constraints
T27_MLB
SMC Constraints
T27_MLB
K6/K69 Specific Constraints
T27_MLB
K6/K69 PCB Rule Definitions
T27_MLB
57
08/15/2009
58
08/03/2009
59
07/20/2009
61
10/21/2009
62
08/31/2009
63
07/17/2009
65
07/17/2009
66
07/17/2009
67
08/25/2009
68
08/27/2009
69
07/20/2009
70
07/29/2009
72
C
07/20/2009
73
08/06/2009
74
07/20/2009
75
08/18/2009
76
07/20/2009
77
09/30/2009
78
11/24/2009
79
08/27/2009
90
07/20/2009
93
08/12/2009
94
07/20/2009
97
08/27/2009
98
07/28/2009
100
08/03/2009
101
08/03/2009
102
08/03/2009
103
08/27/2009
104
11/23/2009
105
B
07/20/2009
106
07/28/2009
108
09/08/2009
109
08/06/2009
08/27/2009
48
08/27/2009
49
09/02/2009
50
09/02/2009
51
08/27/2009
52
08/21/2009
53
08/27/2009
54
09/30/2009
55
08/27/2009
A
A
DRAWING TITLE
SCHEM,MLB_LDO,K6
DRAWING NUMBER
Schematic / PCB #’s
PART NUMBER
DRAWING
QTY
Apple Inc.
DESCRIPTION
REFERENCE DES
CRITICAL
051-8563
1
SCHEM,MLB_LDO,K6
SCH
CRITICAL
820-2879
1
PCBF,MLB_LDO,K6
PCB
CRITICAL
BOM OPTION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
LAST_MODIFIED=Thu Mar 18 17:53:39 2010
TITLE=MLB
ABBREV=DRAWING
8
7
6
051-8563
REVISION
5
4
3
2
A.13.0
BRANCH
PAGE
1 OF 109
SHEET
1 OF 80
1
SIZE
D
8
7
6
5
4
3
2
1
U1000
J1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
FSB
D
D
J6950,U7000
64-Bit
1067/1333 MHz
DC/BATT
PG 10
MAIN
MEMORY
FSB INTERFACE
GPIOs
PG 18
POWER SUPPLY
PG 58,59
J2900
2 UDIMMs
DDR3-1067/1333MHZ
DIMM
PG 14
U5535,U5515
PG 25,26
CPU,MCP,TEMP SENSOR
PG 45
Misc
CLK
PG 18
U6100
SYNTH
J4501
SATA
Conn
HD
POWER PGSENSE
50
SPI
Boot ROM
PG 15,18
SPI
J5601
FAN CONN PGAND
CONTROL
46
PG 51
1.05V/3GHZ.
PG 18
PG 38
NVIDIA
J4500
SATA
Conn
ODD
C
1.05V/3GHZ.
PG 38
U4900
Fan Ser
Prt
ADC
B,0 BSB
MCP
SATA
SMC
LPC
PG 17
J5100
LPC+SPI Conn
C
PG 39
PG 46
PG 18
U1400
J9000
PWR
LVDS
CONN
CTRL
LVDS OUT
J3401
PG 68
RGB OUT
USB
PG 16
PG 17
TMDS OUT
J3401
PG 15
PCI-E
PG 29
B
UP TO 20 LANES3
AIR PORT
J4600, J4610
PG 38
CAMERA
J3500
EXTERNAL
USB
Connectors
PG 37
PG 29
J4890
Card reader
PG30
Blue Ray dec
PG38
0 1 2 3 4 5 6 7 8 9 10 11
HDMI OUT
DVI OUT
PG 70
J3401
IR
PG 47
(UP TO 12 DEVICES)
DISPLAY PORT
CONN
J4890
TRACKPAD/
KEYBOARD
PG 29
DP OUT
J9400
U5701
Bluetooth
B
J1300
SMB
SMB
CONN
PG 18
MAC
PCI
HDA
PG 12
PG 17
PG 18
U6201
Audio
Codec
PG 52
U6880
U3900
A
GB
E-NET
Line In
Filter
BMC5764M
PG 53
HEADPHONE
Filter
PG 54
U6633, U6623, U6613
Mic
Amp
Speaker
Amps
PG 53
PG 55
SYNC_MASTER=K69_MLB
SYNC_DATE=08/19/2009
PAGE TITLE
System Block Diagram
PG 31
DRAWING NUMBER
Apple Inc.
J4000
J3401
051-8563
REVISION
R
PCI-E
AirPort
J6750,6700
E-NET
Conn
Audio
Conns
PG 29
PG 32
PG 56
8
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6
5
4
3
2
A.13.0
BRANCH
PAGE
2 OF 109
SHEET
2 OF 80
1
SIZE
D
A
8
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2
1
K6 POWER SYSTEM ARCHITECTURE
PP18V5_DCIN_CONN
Q7080
02
PPDCIN_G3H_OR_PBUS
Q7085
V
8A FUSE
PPVBAT_G3H_CHGR_REG
D
01
ENABLE
PP3V42_G3H_REG 03
3.425V G3HOT
LT3470
VOUT
U6990
PBUS_VSENSE
SMC PWRGD
RN5VD30A-F
U5010
Q5315
PPBUS_G3H
04
D
PBUS_G3H_VSENSE
02
F7040
VIN
AC
DCIN(16.5V)
ADAPTER
IN
CPUVTTS0_EN
(S0)
CHGR_EN
(S5)
F6905
6A FUSE
A
VOUT
06-1
PWRBTN*
SMC_BATT_ISENSE
PBUS SUPPLY/
BATTERY CHARGER
31
PGOOD
A
PLTRST*
CPUVTTS0_PGOOD
V
01
CPU VCORE
02
IMVP_VR_ON_R
Q7055
CPUPWRGD(GPIO49)
CPU_RESET#
28
VR_PWRGOOD_DELAY
PGOOD
U7100
C
CHGR_BGATE
PWRGOOD
4.5V AUDIO
VIN MAX8840
U6200
PP4V5_AUDIO_ANALOG
RESET*
VOUT
U1000
11
11-1
32
P3V3S3_EN
PM_SLP_S4_L
Q7940
02
SMC
PP5V_S0_FET
P16
15
PM_SLP_S3_L
11-3
DDRREG_EN
P60
VIN
P5VS3_EN_L
04
U4900
RC
DELAY
U1400
SMC_PM_G2_EN
EN1
PP5V_S3_REG
VOUT2
EN2
3.3V
PGOOD1,2
Q7910
PP3V3_S3_FET
13
Q3450
VREG3
P3V3_S3_WLAN
P3V3S3_EN
LP8545
U9701
ENA
P5VS0_EN
07
(5.5A MAX CURRENT)
VIN
BKLT_EN
17
(13A MAX CURRENT)
TPS51125
U7201
P5VS3_EN_L
RC
DELAY
VOUT1
PP3V3_S5_REG
U7840
02
11-2
5V
(RT)
05
(S5)
P3V3S5_EN_L
P5V3V3_PGOOD
PPVOUT_SW_LCDBKLT
VOUT
P3V3ENET_EN_L
B
SMC
24
RSMRST_OUT(P15)
ALL_SYS_PWRGD
Q7930
EN
PM_WLAN_EN_L
16
VOUT
TPS62202
U7760
1.5V
ISL8009B
U7710
04-1
PP1V5R1V35_SW_MCP
02
VIN
=DDRREG_EN
=DDTVTT_EN
PM_SLP_S3_L
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
P1V8S0_EN
16-3
P1V5S0_EN
16-4
CPUVTTS0_EN
PBUSVSENSE_EN
(S0)
P5VS0_EN
(S0)
S3
16-6
P1V5S0_PGOOD
P5V3V3_PGOOD
PP1V5_S0_REG
MCPCORES0_PGOOD
CPUVTTS0_PGOOD
SLP_S4_L
SLP_S3_L
MCPPLLDO_PGOOD
TPS7470
U7740
21
SLP_S5_L
IMVP_VR_ON_R
RC
DELAY
P3V3S0_EN
PM_PWRBTN_L
RST*
SMC_RESET_L
SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
S0PGOOD_RST_L
PP1V05_S0_MCP_PLL_REG
1.5V
MCPDDROUT
0.75V
VOUT2
ST1S12G12R
U7720
PP1V5_S3_REG
(12A MAX CURRENT)
VOUT1
14
RST*
PP0V75_S0_REG
(1A MAX CURRENT)
TPS51116
U7300
PP1V2_ENET_REG
PP3V3_S0
V1
PP1V5_S0
V2
PP1V05_S0
V3
20
MCP_CORE
16-1
MCPCORES0_EN
VOUT
EN
PPMCPCORE_S0_R
R7525 PPMCPCORE_S0_REG
ISL88042
U7870
SYNC_MASTER=K69_MLB
PAGE TITLE
Power Block Diagram
DRAWING NUMBER
(25A MAX CURRENT)
Apple Inc.
051-8563
REVISION
A.13.0
16-2
VIN
16-5
7
6
B
25
IMVP_VR_ON(P16)
RSMRST_IN(P13)
PLT_RST*
PWR_BUTTON(P90)
P17(BTN_OUT)
1.2V
02
8
05
99ms DLY
10
PM_RSMRST_L
R
DDRVTT_EN
MCPCORES0_EN
16-1
S5
PP1V8_S0_REG
1.05V
Q7930
RSMRST_PWRGD
SMC_ONOFF_L
1.8V
P3V3S0_EN
Q7890,Q7891
PM_SLP_S3_L
SMC_ADAPTER_EN
09
PP0V9_S5_REG
ISL8009B
U7750
PWRGD(P12)
18
PP3V3_S0_FET
VIN
Q7890
AP_PWR_EN
A
C
CPU
PPBUS_G3H
EN
MCP89
CPU_PWRGD
30
U2850
U1400
VR_ON
25
PPVBAT_G3H_CHGR_R
29
26
FSB_CPURST_L
ISL9504B
LPC_RESET_L
RSMRST*
MCP_PS_PWRGD PWRGD
SMC_CPU_VSENSE
PPVCORE_S0_CPU
(44A MAX CURRENT)
SMC_CPU_ISENSE
VOUT
VIN
J6950
PPVBAT_G3H_CONN
MCP89
TPS51117
U7600
R7050
ISL6259
U7000
3S2P
PP1V05_S0
(8A MAX CURRENT)
(1.05V)
VIN
R7020
VOUT
CPUVTT
ENABLES
SMC_DCIN_ISENSE
(9 TO 12.6V)
EN_PSV
ISL9563A
U7500
5
4
3
2
BRANCH
PAGE
3 OF 109
SHEET
3 OF 80
1
SIZE
D
A
8
7
6
5
BOM Variants
4
3
2
1
Bar Code Labels / EEE #’s
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
639-1120
PCBA,MLB_LDO,BETTER,K6
K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DD23]
CRITICAL
CRITICAL
BOM OPTION
EEEE:DD23
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DD24]
CRITICAL
EEEE:DD24
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-1119
PCBA,MLB_LDO,BEST,K6
K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23
085-1634
K6 MLB_LDO DEVELOPMENT BOM
K6_DEVEL:PVT
TABLE_BOMGROUP_ITEM
BOM Groups
D
D
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K6_COMMON
COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15
K6_MISC
DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V
K6_PROGPARTS
BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG
K6_DEVEL:ENG
BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL
K6_DEVEL:PVT
LPCPLUS,XDP_CONN
K6_DEBUG:ENG
DEVEL_BOM,SMC_DEBUG:YES,XDP
K6_DEBUG:PVT
DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
K6_DEBUG:PROD
BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K6 BOARD STACK-UP
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Module Parts
PART NUMBER
C
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
SIGNAL
2
GROUND
3
SIGNAL(High Speed)
4
SIGNAL(High Speed)
BOM OPTION
337S3769
1
PDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550
U1000
CRITICAL
CPU:2.26GHZ
337S3680
1
PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU:2.4GHZ
337S3756
1
PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU:2.53GHZ
337S3761
1
PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA
U1000
CRITICAL
CPU:2.66GHZ
337S3797
1
IC,MCP89M-A01,31X31MM,BGA1168
U1400
CRITICAL
MCP89M:A01
337S3866
1
IC,MCP89M-A01,31X31MM,BGA1168
U1400
CRITICAL
MCP89M:A02
341S2731
1
IC,1MBIT,SPI FLASH,K17/18
U3990
CRITICAL
BCM5764M
343S0493
1
IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN
U3900
CRITICAL
BCM5764M
338S0753
1
IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12
U4100
CRITICAL
353S2896
1
IC,LP8545,LED BKLT CTRLR,LLP24
U9701
CRITICAL
338S0563
1
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900
CRITICAL
SMC:BLANK
341T0240
1
SMC EXTERNAL,K6
U4900
CRITICAL
SMC:PROG
335S0610
1
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM:BLANK
341T0238
1
EFI UNLOCKED,K6/K69
U6100
CRITICAL
BOOTROM:UNLOCKED
341S2589
1
IC,EFI,LOCKED,K6
U6100
CRITICAL
BOOTROM:LOCKED
338S0633
1
IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN
U4800
CRITICAL
IR:BLANK
341S2384
1
IC,ENCORE II,CY7C63803-LQXC
U4800
CRITICAL
IR:PROG
337S2983
1
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
U5701
CRITICAL
WELLSPRING:BLANK
341S2616
1
IC,TP PSOC,K17,K18
U5701
CRITICAL
WELLSPRING:PROG
5
GROUND
6
POWER
7
POWER
8
Programmable Parts
B
Top
C
GROUND
9
SIGNAL(High Speed)
10
SIGNAL(High Speed)
11
GROUND
BOTTOM
SIGNAL
Alternate Parts
B
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
152S0693
152S0778
ALL
CYNTEC AS ALTERNATE
152S0796
152S0685
ALL
CYNTEC AS ALTERNATE
157S0058
157S0055
ALL
DELTA AS ALTERNATE
104S0018
104S0023
ALL
DALE/VISHAY AS ALTERNATE
128S0093
128S0218
ALL
KEMET AS ALTERNATE
152S0874
152S0516
ALL
MAGLAYERS AS ALTERNATE
152S0847
152S0586
ALL
MAGLAYERS AS ALTERNATE
152S1025
152S1024
ALL
TOKO AS ALTERNATE
337S3769
337S3704
ALL
INTEL P7550 CPU AS ALTERNATE
152S1135
152S0586
ALL
TOKO AS ALTERNATE
516-0213
516-0201
ALL
MOLEX AS ALTERNATE
516S0790
516S0706
ALL
MOLEX AS ALTERNATE
376S0699
376S0360
ALL
SSM6P15FE AS ALTERNATE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
A
A
SYNC_MASTER=K24_MLB
PAGE TITLE
BOM Configuration
DRAWING NUMBER
DEVELOPMENT BOM
Apple Inc.
PART NUMBER
085-1634
8
QTY
DESCRIPTION
REFERENCE DES
1
K6 MLB_LDO DEVELOPMENT BOM
DEVEL
7
CRITICAL
R
BOM OPTION
CRITICAL
DEVEL_BOM
6
051-8563
REVISION
5
4
3
2
A.13.0
BRANCH
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7
6
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1
Revision History
D
D
C
C
B
B
A
A
SYNC_MASTER=K24_MLB
PAGE TITLE
Revision History
DRAWING NUMBER
Apple Inc.
051-8563
REVISION
R
NOTE: All page numbers are .csa, not PDF.
8
See page 1 for .csa -> PDF mapping.
7
6
5
4
3
2
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BRANCH
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8
7
6
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1
Functional Test Points
DEBUG VOLTAGE
RIGHT CLUTCH CONN
Fan Connectors
D
I12
I15
I16
TRUE
TRUE
TRUE
(NEED 2 TP)
PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
6 7 65
I303
46
I301
46
I302
(NEED TO ADD 3 GND TP)
I300
I299
MIC FUNC_TEST
I238
I237
I239
TRUE
TRUE
TRUE
I298
I293
BI_MIC_LO
BI_MIC_HI
BI_MIC_SHIELD
55 56
I297
55 56
I294
55 56
I288
I292
I227
I226
I228
I230
I229
I231
SPEAKER FUNC_TEST
SPKRAMP_L_N_OUT
TRUE
SPKRAMP_L_P_OUT
TRUE
SPKRAMP_R_N_OUT
TRUE
SPKRAMP_R_P_OUT
TRUE
SPKRAMP_SUB_N_OUT
TRUE
SPKRAMP_SUB_P_OUT
TRUE
I296
54 55
I291
54 55
I295
54 55
I290
54 55
I271
54 55
I289
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S3_BTCAMERA_F
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
PP5V_WLAN
PCIE_WAKE_L
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
USB_BT_CONN_P
USB_BT_CONN_N
AP_CLKREQ_Q_L
AP_RESET_CONN_L
I287
29
I285
15 29 74
I414
15 29 74
I280
29 74
I281
29 74
I282
29 79
I283
29 79
I376
29 79
I278
29 79
6 29
(NEED 2 TP)
I270
I416
15 24 29
I273
6 42 78
I274
6 42 78
I275
29 79
I417
29 79
I392
29
I391
29
I390
54 55
I388
I418
IPD_FLEX_CONN
I375
I374
I372
LVDS FUNC_TEST
I370
I259
C
I258
I260
I245
I407
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT
BKL_VSYNC
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LED_RETURN_1
BKL_ISEN2
BKL_ISEN3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
I371
6 67
I369
6 67
I368
67 70
I361
67 70
I366
8 67
I365
8 67
I363
8 67 74
I364
8 67 74
I362
8 67 74
I360
8 67 74
I359
8 67 74
I357
8 67 74
I358
67 79
I377
67 79
I378
I267
I265
I266
67 70
I354
I355
I349
(NEED 4 TP)
I348
6 8
I350
36 39
I352
36 79
I351
36 79
I353
36 74
I327
36 74
I328
I329
I343
SATA HDD/IR/SIL
I342
(NEED 3 TP)
I319
I314
I315
I318
I317
I307
I309
I311
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
PP5V_S3_IR_R
7 43
D
7 43
7
7 65
7 65 79
7
7 65 79
6 7 65
6 7
6 7
7
7 65 79
6 7
7 43
7
6 29
6 8
6 36
6 48
6 67
6 67
51
7 79
39 65
18 39 40 65
18 39 65 69
47 48
47 48
C
47 48
48
47 48
SPI DEBUG CONN
47 48
47 48
I421
47 48
I422
47 48
I423
47 48
I424
47 48
I425
6 42 78
I426
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V42_G3H
SPI_CS0_L
SPI_CLK
SPI_MOSI
SPI_MISO
SPIROM_USE_MLB
6 7
41 75
41 75
41 75
18 41 75
18 41 50
6 42 78
47 48
DC POWER CONN
47 48
TRUE
TRUE
(NEED 3 TP)
PP18V5_DCIN_FUSE
ADAPTER_SENSE
57
57
67 70
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I380
I304
SATA ODD CONN
I269
I381
47 48
KEYBOARD CONN
67 70
I347
B
I382
47 48
70
I346
I268
I419
6 48
I312
I345
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
6 7
67 70
I344
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S3
PP18V5_S3
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L
I383
70
I264
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I386
PPVCORE_S0_CPU
PPVCORE_S0_MCP
PP1V2_ENET
PP1V05_S0
PP1V5_S0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3
PP5V_S3
PP0V9_S5
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET
PP5V_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP18V5_S3
PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F
PP4V5_AUDIO_ANALOG
PP1V5R1V35_S3
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I341
6 36
I339
36 74
I340
36 74
I338
36 74
I336
36 74
I337
36
I333
36 38
I335
36
I334
I332
I330
I331
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S3
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
6 7
6 7
47
47
47
47
47
47
47
FSB SIGNALS WITH NOTEST
47
47
I396
NO_TEST=TRUE
I399
NO_TEST=TRUE
I398
NO_TEST=TRUE
I397
NO_TEST=TRUE
I403
NO_TEST=TRUE
I402
NO_TEST=TRUE
I400
NO_TEST=TRUE
I401
NO_TEST=TRUE
I404
NO_TEST=TRUE
I406
NO_TEST=TRUE
I405
NO_TEST=TRUE
47
47
47
47
47
47
47
47
47
47
FSB_A_L<35..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
FSB_DINV_L<3..0>
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>
B
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
47
47
47
47
47
47
47
47
BATT POWER CONN
I322
I321
I320
A
I305
TRUE
TRUE
TRUE
TRUE
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SYS_DETECT_L
PPVBAT_G3H_CONN
KBD BACKLIGHT CONN
6 42 78
6 42 78
I356
TRUE
KBDLED_ANODE
TRUE
SMC_KDBLED_PRESENT_L
I394
48
57
57 58
(NEED 3 TP)
A
48
SYNC_MASTER=K24_MLB
PAGE TITLE
FUNC TEST
BIL CONN
I326
I323
I324
I325
I308
TRUE
TRUE
TRUE
TRUE
TRUE
DRAWING NUMBER
T57 CONN
PP3V42_G3H
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BIL_BUTTON_L
SMC_LID_R
6 7
I408
6 42 78
I409
6 42 78
I410
39 40 57
I411
57
I413
I412
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S3
PP3V3_S3
T57_PWR_EN
T57_RESET
USB_T57_N
USB_T57_P
Apple Inc.
6 7
R
6 7
18
18
38 75
38 75
8
7
6
5
051-8563
REVISION
4
3
2
A.13.0
BRANCH
PAGE
7 OF 109
SHEET
6 OF 80
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D
8
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6
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"S0,S0M" RAILS
"G3H" RAILS
"S3" RAILS
61
=PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
(CPU VCORE PWR)
=PPVCORE_S0_CPU
63
LVDDR (1.5V/1.35V) Rails
6 43
=PPCPUVTT_S0_REG
=PP5V_S0_FET
66
PP5V_S0
PP1V05_S0
6 65
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
D
=PP1V05_S0_CPU
9 10 11 12 61
=PP1V05_S0_MCP_FSB
13 19 22
=PP1V05_S0_MCP_AVDD_UF
22
=PP1V05_S0_MCP_SATA_DVDD
19 22
=PP1V05_S0_MCP_PLL_UF_R
64
=PP1V05_FW_P1V0FWFET
34
=PP1V05_S0_FWPWRCTL
34
=PP1V05_SW_MCP_FSB
=PP1V05_S0_MCP_PE_DVDD
=PP1V05_S0_MCP_M2CLK_DLL
=PP1V05_S0_MCP_PLL_IFP
=PP1V05_S0_MCP_DP0_VDD
6 65
=PP5V_S0_HDD
36
=PP5V_S0_LPCPLUS
41
=PP5V_S0_FAN_RT
46
=PP5V_S0_CPU_IMVP
61
=PP5V_S0_KBDLED
48
=PP5VR3V3_S0_DPCADET
63
=PP5V_S0_BKL
70
=PP5V_S0_MCPREG
62
=PP5V_S0_MCPFSBFET
21
=PP3V3_S0_FET
PP3V3_S0
=PPMCPCORE_S0_REG
PPVCORE_S0_MCP
(MCP VCORE AFTER SENSE RES)
6 43
VOLTAGE=1.05V
MAKE_BASE=TRUE
60
=PP3V3_S0_SMBUS_SMC_B_S0
42
=PP3V3_S0_SMBUS_MCP_0
42
=PP3V3_S0_FAN_RT
46
=PP3V3_S0_AUDIO
51 55 56
=PP3V3_S0_IMVP
61
=PP3V3_S0_LCD
67
=PPVTT_S3_DDR_BUF
25
26
PPDDRVREF_S3
=PP1V5_S0_REG
6 65 79
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP3V3_S0_MCPTHMSNS
45
=PP3V3_S0_CPUTHMSNS
45
26
65
57
39 40
=PP3V3_S5_LPCPLUS
41
=PP3V42_G3H_BMON_ISNS
44
=PP3V42_G3H_ONEWIRE
57
60
PP3V3_G3_RTC
18 19 22
28
=PP3V42_G3H_OPA330
22
=PP3V3_S3_WLAN
29
=PP3V3_S3_MCP_GPIO
18
=PP3V3_S3_TPAD
47 48
=PP3V3_S3_SMS
49
=PP3V3_S3_CARDREADER
30
=PP3V3_S3_T57
38
=PP3V3_ENET_P1V2ENET
64
=PP18V5_DCIN_CONN
PPDCIN_S5_S5
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPBUS_G3H
=PPDCIN_S5_CHGR
58
PPBUS_G3H
6 43
VOLTAGE=12.6V
MAKE_BASE=TRUE
6
=PPBUS_S0_LCDBKLT
=PPVIN_S0_MCPCORE
71
62
=PPVIN_S3_DDRREG
=PP5V_S3_RTUSB
37
=PP5V_S3_IR
36 38
=PP5V_S3_MCPDDRFET
20
=PP5V_S3_SYSLED
40
=PP5V_S3_TPAD
48
=PP5V_S3_WLAN
29
=PP5V_S3_DDRREG
60
=PP5V_S3_AUDIO
51 53 55
=PP5V_S3_AUDIO_AMP
54
=PP5V_S3_P5VS0FET
60
=PPVIN_S5_3V3S5
=PPVIN_S3_5VS3
59
59
=PPBUS_S5_FWPWRSW
34
=PPBUS_S5_CPUREGS_ISNS_R
44
C
(BEFORE HIGH SIDE SENSING RES.)
66
=PP5V_S0_ODD
36
=PP5V_S3_BTCAMERA
29
=PP5V_S3_T57
38
=PP3V3_S0_ENETPHY
31
=PP3V3_S0_CPUVTTISNS
44
=PP3V3_S0_TPAD
48
(AFTER HIGH SIDE CPU VCORE
42
& CPU VTT SENSING RES.)
=PP3V3_S0_P1V8S0
64
70
44
=PP3V3_S0_MCPDDRISNS
47
=PP3V3_S3_PDCISENS
VOLTAGE=5V
MAKE_BASE=TRUE
25
=PP3V3_S0_PWRCTL
37
=PP3V3_S3_VREFMRGN
PP5V_S3
=PP5V_S3_REG
69
=PPSPD_S0_MEM_B
36
44
=PPBUS_S5_CPUREGS_ISNS
PPBUS_S5_IMVP_VTT_ISNS
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP
63
61
=PP3V3_S0_MCP_PLL_VLDO
=PP1V8R1V5_S0_AUDIO
51
=PP3V3_S0_FWPWRCTL
34
=PP1V5_S0_MCP_HDA_R
8
=PP3V3_S0_FWLATEVG
34 35
=PP1V5_S0_AUDIO_R
8
=PP3V3_S0_SDCONN
30
=PP3V3_S0_MCPCOREISNS
44
6
=PP3V3_S0_MCP_HDA_R
8
=PP3V3_S0_AUDIO_R
8
=PP3V3_S0_OPA333
22
"FIREWIRE" RAILS
"S5" RAILS
34
=PP3V3_FW_FET
PP3V3_FW
VOLTAGE=3.3V
MAKE_BASE=TRUE
16 23
=PP1V8_S0_AUDIO
"ENET" RAILS
=PP3V3_ENET_FET_R
8
PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_PLL_UF
~100mA
64
(BCM5764M)
=PP1V2_ENET_REG
(BCM57765)
PP3V3_S5
6
=PP3V3_ENET_MCP_RMGT 17 19 22
=PP3V3_ENET_MCP_PLL_MAC 22
=PP3V3_ENET_PHY
24 31 64
=PP3V3_ENET_PWRCTL
65
PP1V2_ENET
700 mA max output
=PP1V2_ENET_PHY_REG
64
UNUSED MCP PE0[3:0] AVDD/DVDD
=PP3V3_S5_REG
~400mA
=PP3V3_FW_FWPHY
6 65 79
B
33 34 35
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_ENET
300mA
22
59
VOLTAGE=3.3V
MAKE_BASE=TRUE
400mA
VOLTAGE=1.05V
MAKE_BASE=TRUE
19
40
=PP1V5_S0_SATARDRVR
=PP3V3R1V8_S0_MCP_IFP_VDD
19
=PP3V3_S0_SMC
10 11
PP1V8_S0
64 =PP1V05_S0_MCP_PLL_OR
19 22
=PP3V3_S0_BKL_VDDIO
VOLTAGE=1.8V
MAKE_BASE=TRUE
B
22
=PP1V5_S0_CPU
=PP1V5_S0_MCP_PLL_VLDO
=PP1V8_S0_REG
16 17 18
=PP3V3_S0_MCP_HVDD
=PPSPD_S0_MEM_A
PP1V5_S0
I1086
42
D
58 65
=PP3V3_S5_SMC
58
59
=PP3V3_S0_MCP_GPIO
65
=PP3V42_G3H_TPAD
6
42
=PP3V3_S0_DPCONN
VOLTAGE=0.75V
MAKE_BASE=TRUE
64
36
=PP3V3_S0_SMBUS_SMC_0_S0
=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_B
64
=PP3V3_S0_ODD
21
VOLTAGE=0.75V
MAKE_BASE=TRUE
60 28
41
19 22
PPDDRVTT_S0
C
19 22
64
=PP3V3_S0_DEBUGROM
=PPVCORE_S0_MCPGFXFET
=PPVTT_S0_DDR_LDO
60
57
=PP3V3_S0_P1V5S0
42
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
20
=PP3V3_S3_SMBUS_SMC_A_S3
12
=PP3V3_S0_MCP
40
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
14
PP3V3_S3
6 65 79
=PPVCORE_S0_MCP
LVDDR VRef/VTT (0.75V/0.675V) Rails
=PPVIN_S5_SMCVREF
25
26
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
16 23
6
=PP3V42_G3H_BATT
=PP3V3_S3_FET
7 22
66
PP3V42_G3H
VOLTAGE=3.42V
MAKE_BASE=TRUE
69
=PP5V_S0_CPUVTTS0
19 22
16 23
=PP3V42_G3H_REG
6 79
1.35V)
=PPLVDDR_S3_MEM_A
=PPLVDDR_S3_MEM_B
=PP1V5R1V35_S3_MCP_MEM
=PP1V5R1V35_S0_MCPDDRFET
=PPVIN_S0_DDRREG_LDO
0 mA
4250 mA
66
14 22
57
PP1V5R1V35_S3
VOLTAGE=1.5V
MAKE_BASE=TRUE
(OR
=PP3V3_S0_XDP
62
=PPDDR_S3_REG
60
VOLTAGE=5V
MAKE_BASE=TRUE
10 11
6
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PP1V2_ENET_PHY
31
=PP3V3_S5_MCP_GPIO
17 18
=PP3V3_S5_ROM
50
=PP3V3_S5_LCD
67
=PP3V3_S5_MCP
19 22
=PP3V3_S5_MCPPWRGD
24
=PP3V3_S5_P3V3S3FET
66
=PP3V3_S5_P3V3S0FET
66
=PP3V3_S5_P3V3ENETFET
66
=PP3V3_S5_DP_PORT_PWR
69
34
PPVP_FW
=PPBUS_FW_FET
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPVP_FW_PORT1
35
=PPVP_FW_PHY_CPS_FET
=PP3V3_S5_P0V9S5
64
=PP3V3_FW_P3V3FWFET
34
66
=PP3V3_S5_VMON
65
=PP3V3_S5_SMBUS_SMC_MGMT
42
=PP1V05_S0_MCP_PE_DVDD0
35
34
=PP1V0_FW_FET_R
PP1V05_FW
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V0_FW_FWPHY
33 34
=PP1V05_S0_MCP_PE_AVDD0
(SINCE PE0[3:0] IS NOT USED ON K6)
66
=PP0V9_ENET_FET
(CONNECTS TO MCP BALLS)
19
7
22
(CONNECTS TO THE DECAPS)
(CONNECTS TO MCP BALLS)
19
PP1V05_S0_MCP_PE_AVDD
22
(CONNECTS TO THE DECAPS)
PP0V9_ENET
VOLTAGE=0.9V
MAKE_BASE=TRUE
0.9V Rails
=PP0V9_ENET_MCP_RMGT
19 22
64
=PP0V9_S5_REG
PP0V9_S5
6
VOLTAGE=0.9V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
A
105 mA/241 mA
139 mA/
0 mA
=PP0V9_S5_MCP_VDD_AUXC
=PP0V9_ENET_P0V9ENETFET
19 22
66
SYNC_MASTER=K24_MLB
PAGE TITLE
Power Aliases
DRAWING NUMBER
Apple Inc.
051-8563
REVISION
R
8
7
6
5
4
3
2
A.13.0
BRANCH
PAGE
8 OF 109
SHEET
7 OF 80
1
SIZE
D
A
8
7
6
5
4
3
PCI-E ALIASES
15
=PEG_D2R_N<3:0>
NC_PEG_D2R_N<3:0>
15
=PEG_D2R_P<3:0>
NC_PEG_D2R_P<3:0>
NO_TEST=TRUE
Z0902
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
1
NO_TEST=TRUE
15
NC_PEG_R2D_C_P<3:0>
PEG_CLK100M_P
TP_PEG_CLK100M_P
74 15
D
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
TP_PEG_CLK100M_N
PEG_CLKREQ_L
TP_PEG_CLKREQ_L
74
NC_MCP_CLK27M_XTALOUT
CRT_IG_R_C_PR
NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE
1
74
USB ALIASES
BELOW CPU
74
CRT_IG_B_COMP_PB
75 17
75 17
CRT_IG_HSYNC
75 17
75 17
FAN STANDOFF
75 17
75 17
Z0905
75 17
STDOFF-4.5OD.98H-1.1-3.48-TH
75 17
16
MAKE_BASE=TRUE
MAKE_BASE=TRUE
16
MAKE_BASE=TRUE
16
MAKE_BASE=TRUE
16
MAKE_BASE=TRUE
16
16
16
ETHERNET ALIASES
16
16
PLACE_NEAR=U7980.A1:5MM
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
OMIT
OMIT
Z0907
3R2P5
1
1
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_FET_R
OUT
7
16
MAKE_BASE=TRUE
16
16
16
=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N
=MCP_IFPA_TXD_P<0..2>
=MCP_IFPA_TXD_N<0..2>
LVDS_IG_A_CLK_P
MAKE_BASE=TRUE
LVDS_IG_A_CLK_N
MAKE_BASE=TRUE
LVDS_IG_A_DATA_P<0..2>
MAKE_BASE=TRUE
LVDS_IG_A_DATA_N<0..2>
67 74
ENET_RXD_PD
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RXCLK_PD
OUT
17 76
OUT
17 76
OUT
17 76
OUT
17 76
ENET_CLK125M_RXCLK
OUT
17 76
ENET_RX_CTRL
OUT
17 76
MAKE_BASE=TRUE
ENET_MDIO
ENET_LOW_PWR
MLB MOUNTING (TO TOPCASE) SCREW HOLES
R0980 1
1
R0981
10K
OMIT
OMIT
Z0908
Z0909
Z0910
3R2P5
3R2P5
3R2P5
1
1
1
5%
1/16W
MF-LF
402
R0984 1
10K
2
2
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
1
1
10K
3R2P5
3R2P5
1
1
NC_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
NC_MCP_RGB_VSYNC
MAKE_BASE=TRUE
MAKE_BASE=TRUE
16
6 67 74
TP_MCP_RGB_DAC_RSET
=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<3>
=MCP_IFPB_TXC_P
=MCP_IFPB_TXC_N
=MCP_IFPB_TXD_P<0..3>
=MCP_IFPB_TXD_N<0..3>
16
LCD_IG_BKLT_PWM
LCD_IG_BKLT_EN
TP_MCP_RGB_DAC_VREF
NO_TEST=TRUE
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
NO_TEST=TRUE
5V ODD ALIASES
=PP5V_SW_ODD
=PP5V_SW_ODD_FET
PP5V_SW_ODD
MAKE_BASE=TRUE
LCD_BKLT_PWM
LCD_BKLT_EN
NO_TEST=TRUE
NC_MCP_RGB_DAC_RSET
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3> NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3> NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAP<0..3>NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<0..3>NO_TEST=TRUE
NO_TEST=TRUE
VOLTAGE=5V
70
MAKE_BASE=TRUE
71
36
36
=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA
LVDS_DDC_CLK
BACKLIGHT CONTROLLER ALIASES
6 67
MAKE_BASE=TRUE
LVDS_DDC_DATA
6 67
BI
OUT
OUT
NO STUFF
R0986
10K
2
5%
1/16W
MF-LF
402
PPBUS_SW_LCDBKLT_PWR
1
0
PLACE_NEAR=L9701.1:5MM
PPBUS_SW_BKL
2
C
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_SW_BKL
70
DISPLAY PORT ALIASES
17 76
17
18 31
16
DP_IG_ML0_P<0..3>
74
DP_IG_ML0_N<0..3>
74
DP_IG_HPD0
16
DP_IG_AUX_CH0_P
16
DP_IG_AUX_CH0_N
16
DP_AUX_CH_C_N
68
DP_AUX_CH_C_P
68
DP_CA_DET
68
DP_IG_ML_P<0..3>
DP_IG_ML_N<0..3>
DP_EXT_ML_P<0..3>
DP_EXT_ML_N<0..3>
69 79
MAKE_BASE=TRUE
69 79
MAKE_BASE=TRUE
DP_EXT_HPD
69
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
DP_EXT_AUX_CH_C_N
DP_EXT_AUX_CH_C_P
DP_EXT_CA_DET
MAKE_BASE=TRUE
CHARGER SIGNAL
68 74
MAKE_BASE=TRUE
68 74
MAKE_BASE=TRUE
69 79
58
MAKE_BASE=TRUE
IN
=CHGR_ACOK
SMC_BC_ACOK
MAKE_BASE=TRUE
69 79
OUT
39 40 57
MAKE_BASE=TRUE
69
MAKE_BASE=TRUE
R0982
OMIT
TP_MCP_RGB_HSYNC
16
5%
1/16W
MF-LF
402
16
MCP_RGMII_VREF
Z0912
NO_TEST=TRUE
16
67 74
6 67 74
R0910
MAKE_BASE=TRUE
OMIT
NO_TEST=TRUE
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
C
Z0911
TP_MCP_RGB_BLUE
MAKE_BASE=TRUE
71 70
OMIT
NO_TEST=TRUE
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
=PP3V3_ENET_FET
66
NC_MCP_RGB_GREEN
6
16
2
NC_MCP_RGB_RED
TP_MCP_RGB_GREEN
MAKE_BASE=TRUE
R0911
0
TP_MCP_RGB_RED
16
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
1
16
MAKE_BASE=TRUE
LVDS ALIASES
16
3R2P5
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Z0906
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
PP3V3_ENET_FET
D
NC_CRT_IG_HSYNC
CRT_IG_VSYNC
MAKE_BASE=TRUE
266
133
200
(166)
333
100
(400)
(RSVD)
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_USB_EXTCP
TP_USB_EXTCN
TP_USB_EXTDP
TP_USB_EXTDN
TP_USB_WMP
TP_USB_WMN
TP_USB_MINIP
TP_USB_MININ
FSB MHZ
0
1
0
1
0
1
0
1
MCP89 ALIASES
MAKE_BASE=TRUE
NC_CRT_IG_B_COMP_PB
UNUSED USB PORTS
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_WM_P
USB_WM_N
USB_MINI_P
USB_MINI_N
0
0
1
1
0
0
1
1
MAKE_BASE=TRUE
NO_TEST=TRUE
BELOW MCP
0
0
0
0
1
1
1
1
NC_CRT_IG_G_Y_Y
NO_TEST=TRUE
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MCP_CLK27M_XTALOUT
CRT_IG_G_Y_Y
13 BSEL<2..0>
TP_CPU_PECI_MCP
NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE
MAKE_BASE=TRUE
=MCP_BSEL<0:2>
CPU_PECI_MCP
13
MAKE_BASE=TRUE
NO_TEST=TRUE
74
CPU_BSEL<0:2>
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
74
72 9
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
PEG_CLK100M_N
MCP_TV_DAC_VREF
MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
15
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
Z0904
Z0903
74
MAKE_BASE=TRUE
=PEG_R2D_C_P<3:0>
74 15
ABOVE CPU
MCP_TV_DAC_RSET
NO_TEST=TRUE
NC_PEG_R2D_C_N<3:0>
NO_TEST=TRUE
LEFT OF CPU
74
MAKE_BASE=TRUE
=PEG_R2D_C_N<3:0>
NO_TEST=TRUE
CPU ALIASES
UNUSED CRT & TV-OUT INTERFACE
15
1
1
DACS ALIASES
UNUSED GPU LANES
HEATSINK STANDOFFS
2
5%
1/16W
MF-LF
402
R0983
10K
2
2
16
5%
1/16W
MF-LF
402
16
16
16
DP_IG_ML1_P<0..3>
DP_IG_ML1_N<0..3>
DP_IG_AUX_CH1_P
DP_IG_AUX_CH1_N
TP_DP_IG_ML1P<0..3>
TP_DP_IG_ML1N<0..3>
TP_DP_IG_AUX_CH1P
TP_DP_IG_AUX_CH1N
MCPCOREISNS SIGNAL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
62
MCPCORES0_VO
MCPCOREISNS_N
MAKE_BASE=TRUE
=MCPCOREISNS_N
44
=MCPCOREISNS_P
44
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R0920
16
DP_IG_HPD1
1
62
MCPCORES0_ISP_R
MCPCOREISNS_P
2
MAKE_BASE=TRUE
100K
402 5% MF-LF
1/16W
B
B
AUDIO ALIASES
EMI IO (SHORT) POGO PINS
HDA:1.5V
ZS0900
ZS0901
ZS0902
7
1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24
SM
SM
SM
7
1
1
R0912
=PP1V5_S0_AUDIO_R
HDA:3.3V
R0913
=PP3V3_S0_AUDIO_R
1
1
1
7
ZS0908
1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24 1.4DIA-SHORT-EMI-MLB-K19-K24
SM
SM
SM
1
1
A
=PP1V5_S0_MCP_HDA_R
ZS0909
7
R0914
HDA:3.3V
=PP3V3_S0_MCP_HDA_R
R0915
0
402
HDA:1.5V
ZS0903
0
402
1
0
402
1
0
402
2
PP3V3R1V5_S0_AUDIO
5% 1/16W MF-LF
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
=PP3V3R1V5_S0_AUDIO
2
51
5% 1/16W MF-LF
2
PP3V3R1V5_S0_MCP_HDA
5% 1/16W MF-LF
2
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP3V3R1V5_S0_MCP_HDA
18 22
5% 1/16W MF-LF
1
EMI TALL POGO PINS
A
SYNC_MASTER=K24_MLB
PAGE TITLE
ZS0904
ZS0905
ZS0906
ZS0907
SIGNAL ALIAS
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
SM
SM
1
1
DRAWING NUMBER
SM
Apple Inc.
1
051-8563
REVISION
R
8
7
6
5
4
3
2
A.13.0
BRANCH
PAGE
9 OF 109
SHEET
8 OF 80
1
SIZE
D
8
7
6
5
4
3
2
1
OMIT
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13
IN
72 13
OUT
72 13
IN
72 13
IN
72 13
IN
72 13
IN
72 13
IN
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
K3
H2
K2
J3
L1
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
A6 A20M*
A5 FERR*
C4 IGNNE*
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
D5
C6
B4
A3
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3
M4
N5
T2
V3
B2
F6
D2
D22
D3
STPCLK*
LINT0
LINT1
SMI*
DEFER*
DRDY*
DBSY*
BR0*
IERR*
INIT*
H1
E2
G5
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
H5
F21
E1
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
F1
D20
B3
LOCK* H4
72
BI
6 13 72
BI
13 72
BI
13 72
BI
13 72
BI
13 72
BI
13 72
FSB_BREQ0_L
BI
13 72
CPU_IERR_L
CPU_INIT_L
IN
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
F3
F4
G3
G2
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
HIT*
HITM*
G6
E4
FSB_HIT_L
FSB_HITM_L
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
=PP1V05_S0_CPU
7 10 11 12 61
R10001
54.9
1%
1/16W
MF-LF
402 2
D
13 72
6 13 72
IN
12 13 72
IN
13 72
IN
13 72
IN
13 72
IN
13 72
BI
6 13 72
BI
6 13 72
BI
12 72
BI
12 72
BI
12 72
BI
12 72
BI
12 72
OMIT
72 13 6
BI
R10011
72 13 6
BI
72 13 6
BI
1%
1/16W
MF-LF
402 2
72 13 6
BI
72 13 6
BI
72 13 6
BI
54.9
72 13 6
BI
IN
9 12 72
72 13 6
BI
IN
9 12 72
72 13 6
BI
OUT
9 12 72
72 13 6
BI
IN
9 12 72
72 13 6
BI
IN
9 12 72
72 13 6
BI
R10021
72 13 6
BI
72 13 6
BI
5%
1/16W
MF-LF
402 2
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
BI
OUT
12 24
12 72
68
THERMAL
PROCHOT*
THERMDA
THERMDC
THERMTRIP*
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
C7
PM_THRMTRIP_L
OUT
OUT
45 79
OUT
45 79
OUT
13 40 72
13 40 61 72
H CLK
BCLK0
BCLK1
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
D21
A24
B25
A22
A21
FSB_CLK_CPU_P
FSB_CLK_CPU_N
IN
13 72
72 13 6
BI
IN
13 72
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
72 13 6
BI
1
R1005
CPU JTAG Support
R1090
B
72 12 9
XDP_TMS
1
72 12 9
72 12 9
54.9 2
1
XDP_TDI
1%
1/16W
MF-LF
402
XDP_TDO
R1092
1
PLACE_NEAR=J1300.51:12.7 mm
1%
1/16W
MF-LF
2 402
54.9 2
1%
1/16W
MF-LF
402
R1091
1K
54.9 2
PLACE_NEARs:
R1005.2: U1000.AD26:12.7 mm
R1006.1: U1000.AD26:12.7 mm
C1014.1: U1000.AF26:12.7 mm
R1006
2.0K
1%
1/16W
MF-LF
2 402
NO STUFF
C1014 1
XDP_TCK
72 12 9
XDP_TRST_L
R1094
1
649
2
1%
1/16W
MF-LF
402
0.1uF
NO STUFF
10%
16V 2
X5R
402
R1010
1
72 12 9
BI
1
NO STUFF
54.9 2
1
BI
72 13 6
72 28
1%
1/16W
MF-LF
402
R1093
72 13 6
0
5%
1/16W
MF-LF
402
R10111
1K
5%
1/16W
MF-LF
402 2
2
NO STUFF
72 8
OUT
72 8
OUT
72 8
OUT
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
U1000
PENRYN
FCBGA
2 OF 4
DATA GRP 2
BI
72 13 6
ADS*
BNR*
BPRI*
DATA GRP 3
BI
72 13 6
FCBGA
1 OF 4
DATA GRP 0
72 13 6
PENRYN
DATA GRP 1
BI
U1000
CONTROL
72 13 6
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
XDP/ITP SIGNALS
BI
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP0
BI
72 13 6
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
BI
72 13 6
ICH
C
BI
72 13 6
RESERVED
D
72 13 6
MISC
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
COMP0
COMP1
COMP2
COMP3
R26
U26
AA1
Y1
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
E5
B5
D24
D6
D7
AE6
72
72
72
72
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
BI
6 13 72
IN
13 61 72
IN
13 72
IN
13 72
IN
12 13 72
IN
13 72
OUT
C
B
R10231
R10211
54.9
54.9
1%
1/16W
MF-LF
402 2
61
1%
1/16W
MF-LF
402 2
1
1
R1022
R1020
27.4
1
R1012
27.4
1%
1/16W
MF-LF
2 402
1K
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
PLACE_NEARs:
1%
1/16W
MF-LF
402
R1020.1: U1000.R26:12.7 mm
R1021.1: U1000.U26:12.7 mm
R1022.1: U1000.AA1:12.7 mm
R1023.1: U1000.Y1:12.7 mm
A
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU FSB
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
10 OF 109
SHEET
9 OF 80
1
A
8
7
6
5
4
3
2
A4
P6
A8
(CPU CORE POWER)
P21
OMIT
A11
=PPVCORE_S0_CPU
D
A7
AB20
A9
OMIT
AB7
U1000
AC7
A10
A12
FCBGA
A15
(SV
(SV
(SV
(LV
Design Target)
HFM)
LFM)
Design Target)
3 OF 4
A14
U1000
A16
PENRYN
R2
R5
FCBGA
A19
R22
4 OF 4
A23
R25
AF2
T1
B6
T4
B8
B11
T26
AC13
B13
U3
AC15
B16
U6
AC17
B19
U21
A20
AC18
B21
U24
B7
AD7
B24
V2
B9
AD9
C5
V5
B10
AD10
C8
V22
B12
AD12
C11
V25
B14
AD14
C14
W1
B15
AD15
C16
W4
B17
AD17
C19
W23
B18
AD18
C2
W26
B20
AE9
C22
Y3
Y6
VCC
C9
AE10
C25
C10
AE12
D1
Y21
C12
AE13
D4
Y24
C13
AE15
D8
AA2
C15
AE17
D11
AA5
C17
AE18
D13
AA8
C18
AE20
D16
AA11
AF9
D19
AA14
D10
AF10
D23
AA16
D12
AF12
D26
AA19
D14
AF14
E3
AA22
D15
AF15
E6
AA25
D17
AF17
E8
AB1
D18
AF18
E11
VCC
AF20
(CPU IO POWER 1.05V)
E14
=PP1V05_S0_CPU
E9
7 9 11 12 61
G21
E10
4500 mA (before VCC stable)
2500 mA (after VCC stable)
VSS
AB8
E16
AB11
E19
AB13
E21
AB16
V6
E13
J6
E24
AB19
E15
K6
F5
AB23
E17
M6
F8
AB26
E18
J21
F11
AC3
E20
K21
F13
AC6
F7
M21
F16
AC8
N21
F19
AC11
VCCP
F10
N6
F2
AC14
F12
R21
F22
AC16
F14
R6
F25
AC19
F15
T21
G4
AC21
F17
T6
G1
AC24
F18
V21
F20
W21
AA7
G23
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16
61 72
J2
AD19
OUT
61 72
J5
AD22
OUT
61 72
J22
AD25
OUT
61 72
J25
AE1
OUT
61 72
K1
AE4
OUT
61 72
K4
AE8
OUT
61 72
(CPU INTERNAL PLL POWER 1.5V)
=PP1V5_S0_CPU
(BR1#)
7 11
B26
AA9
VCCA
AA10
130 mA
C26
AA12
AA13
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AA15
AA17
AA18
AA20
AB9
AC10
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
=PPVCORE_S0_CPU
1
2
AB14
VCCSENSE
AF7
R1100
CPU_VCCSENSE_P
1%
1/16W
MF-LF
402
OUT
AB15
61 72
PLACE_NEAR=U1000.AF7:25.4 mm
AB17
AB18
VSSSENSE
AE7
PLACE_NEAR=U1000.AE7:25.4 mm
CPU_VCCSENSE_N
B
100
AB10
AB12
7 10 11
C
AB4
VSS
E12
F9
D
T23
AC12
A18
E7
B
A
A
A
A
P24
A17
D9
C
44
41
30.4
23
AC9
PENRYN
A13
7 10 11
1
2
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
R1101
M22
AF8
100
M25
AF11
N1
AF13
OUT
1
K23
61 72
1%
1/16W
MF-LF
402
N4
AF16
N23
AF19
N26
AF21
P3
B1
A25
(Socket-P KEY)
A
AF25
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU Power & Ground
DRAWING NUMBER
Apple Inc.
051-8563
R
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
11 OF 109
SHEET
10 OF 80
1
A
8
7
6
5
4
3
2
1
CPU VCore HF and Bulk Decoupling
4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
Place inside socket cavity on secondary side.
D
10 7
=PPVCORE_S0_CPU
CPU_CAP:15&CPU_CAP:12
NO STUFF
NO STUFF
CRITICAL
CRITICAL
CRITICAL
CRITICAL
1
C1200
1
22UF
C1201
1
22UF
20%
2 6.3V
X5R-CERM
603
C1202
1
22UF
1
22UF
20%
2 6.3V
X5R-CERM
603
20%
2 6.3V
X5R-CERM
603
C1203
NO STUFF
CRITICAL
CPU_CAP:15
CRITICAL
CRITICAL
C1204
1
22UF
20%
2 6.3V
X5R-CERM
603
D
20%
2 6.3V
X5R-CERM
603
C1205
22UF
20%
2 6.3V
X5R-CERM
603
1
C1206
22UF
20%
2 6.3V
X5R-CERM
603
NO STUFF
CRITICAL
1
C1207
22UF
20%
2 6.3V
X5R-CERM
603
NO STUFF
CRITICAL
NO STUFF
CRITICAL
1
C1208
22UF
20%
2 6.3V
X5R-CERM
603
1
C1209
22UF
20%
2 6.3V
X5R-CERM
603
NO STUFF
CPU_CAP:15
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
1
C1210
1
22UF
C1211
1
22UF
20%
6.3V
2 X5R-CERM
603
C1212
1
22UF
20%
6.3V
2 X5R-CERM
603
C1213
1
22UF
20%
6.3V
2 X5R-CERM
603
C1214
22UF
20%
6.3V
2 X5R-CERM
603
20%
6.3V
2 X5R-CERM
603
1
C1215
22UF
20%
6.3V
2 X5R-CERM
603
1
C1216
22UF
20%
6.3V
2 X5R-CERM
603
1
C1217
22UF
20%
6.3V
2 X5R-CERM
603
1
C1218
22UF
20%
6.3V
2 X5R-CERM
603
1
C1219
22UF
20%
6.3V
2 X5R-CERM
603
PLACEMENT_NOTE (C1240-C1243):
NO STUFF
CPU_CAP:15
CRITICAL
CRITICAL
CRITICAL
1
C1220
1
22UF
C1221
1
22UF
20%
6.3V
2 X5R-CERM
603
C1222
22UF
20%
6.3V
2 X5R-CERM
603
20%
6.3V
2 X5R-CERM
603
C
C
Place on secondary side.
CRITICAL
NO STUFF
1
CRITICAL
C1240
1
470UF-4MOHM
CRITICAL
C1241
1
470UF-4MOHM
20%
3 2 2.0V
POLY-TANT
D2T-SM
3
20%
2 2.0V
POLY-TANT
D2T-SM
CRITICAL
C1242
1
470UF-4MOHM
3
20%
2 2.0V
POLY-TANT
D2T-SM
C1243
470UF-4MOHM
3
20%
2 2.0V
POLY-TANT
D2T-SM
VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
10 7
=PP1V5_S0_CPU
BYPASS=U1000.B26::4 mm
C1250 1
1
10uF
B
C1251
0.01UF
20%
6.3V
X5R 2
603
10%
16V
2 CERM
402
B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
61 12 10 9 7
=PP1V05_S0_CPU
PLACEMENT_NOTE=Place C1260 between CPU & NB.
CRITICAL
C1260
1
1
20%
2.0V 2
POLY-TANT
D2T-SM2
C1261
0.1UF
330UF
3
20%
10V
2 CERM
402
1
C1262
0.1UF
20%
10V
2 CERM
402
1
C1263
0.1UF
20%
10V
2 CERM
402
1
C1264
0.1UF
20%
10V
2 CERM
402
1
C1265
0.1UF
20%
10V
2 CERM
402
1
C1266
0.1UF
20%
10V
2 CERM
402
A
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU Decoupling
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
12 OF 109
SHEET
11 OF 80
1
A
8
7
6
5
4
3
2
1
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
D
Use with 920-0620 adapter board to support CPU, MCP debugging.
D
MCP89-specific pinout
7
61 11 10 9 7
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP
CRITICAL
R1315 1
XDP_CONN
J1300
54.9
1%
1/16W
MF-LF
402 2
LTH-030-01-G-D-NOPEGS
F-ST-SM
2
72 9
72 9
72 9
72 9
BI
BI
BI
IN
72 9
IN
72 9
IN
C
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
3
OBSFN_C0
OBSFN_A1
6
5
OBSFN_C1
8
7
10
9
OBSDATA_C0
12
11
OBSDATA_C1
14
13
16
15
18
17
20
19
OBSFN_B0
22
21
OBSFN_B1
24
23
26
25
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
XDP
4
OBSDATA_A0
XDP_BPM_L<1>
XDP_BPM_L<0>
IN
CPU_PWRGD
1
27
OBSDATA_D0
30
29
OBSDATA_D1
32
31
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
OBSDATA_B2
34
33
36
35
38
37
1K
XDP_PWRGD
2
18
IN
18
OUT
75 42 18
BI
75 42 18
BI
72 9
OUT
OBSDATA_D3
39
42
41
ITPCLK#/HOOK5
VCC_OBS_AB
44
43
VCC_OBS_CD
HOOK2
46
45
RESET#/HOOK6
HOOK3
48
47
DBR#/HOOK7
50
49
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
XDP_TCK
52
51
TDO
54
53
TRSTn
TCK1
56
55
TDI
58
57
TMS
60
59
XDP_PRESENT#
NC
TCK0
XDP
C1300
18
OUT
18
C
72
XDP_CPURST_L
XDP_DBRESET_L
XDP_TDO
XDP_TRST_L
XDP_TDI
XDP_TMS
IN
13 72
IN
13 72
XDP
R1303
1
OUT
9 24
IN
9 72
OUT
9 72
OUT
9 72
OUT
9 72
1K
5%
1/16W
MF-LF
402
2
FSB_CPURST_L
9 13 72
IN
PLACEMENT_NOTE=Place close to CPU to minimize stub.
XDP
1
1
998-1571
0.1uF
10%
16V
X5R
402
FSB_CLK_ITP_P
FSB_CLK_ITP_N
ITPCLK/HOOK4
SCL
SDA
OUT
TP_XDP_OBSDATA_D2
TP_XDP_OBSDATA_D3
OBSDATA_D2
40
PM_LATRIGGER_L
JTAG_MCP_TCK
18
TP_XDP_OBSDATA_D0
TP_XDP_OBSDATA_D1
HOOK1
PWRGD/HOOK0
XDP_OBS20
5%
1/16W
MF-LF
402
JTAG_MCP_TDI
JTAG_MCP_TMS
OBSFN_D1
28
18
TP_XDP_OBSDATA_C2
TP_XDP_OBSDATA_C3
OBSFN_D0
OBSDATA_B1
IN
OUT
TP_XDP_OBSDATA_C0
TP_XDP_OBSDATA_C1
OBSDATA_C3
OBSDATA_B0
OBSDATA_B3
JTAG_MCP_TDO
JTAG_MCP_TRST_L
OBSDATA_C2
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
R1399
72 13 9
1
OBSFN_A0
2
C1301
0.1uF
2
10%
16V
X5R
402
B
B
Direction of XDP module
Please avoid any obstructions
on even-numbered side of J1300
A
SYNC_MASTER=T27_MLB
PAGE TITLE
eXtended Debug Port (mini-XDP)
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
13 OF 109
SHEET
12 OF 80
1
A
8
7
6
5
4
3
2
1
OMIT
U1400
MCP89M-A01
FBGA
(1 OF 11)
C
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
BI
72 9 6
72 9
B
22 19 13 7
1
1
R1410
R1415
54.9
72 40 9
72 9
8
IN
IN
IN
8
IN
8
IN
IN
72 9
IN
5%
1/16W
MF-LF
2 402
IN
72 9 6
IN
72 9 6
IN
72 9 6
IN
72 9
62
1%
1/16W
MF-LF
402 2
IN
BI
8
OUT
72 61 40 9
OUT
K33
K32
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
C36
D36
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
U38
T30
P28
N35
A35
T37
Y38
W35
Y36
U33
W34
Y37
Y35
AF38
AB35
Y34
AE38
AC36
AF36
AC38
AB36
AB38
AB37
AC34
AE36
AF37
AC37
AC35
AE37
AE35
AE33
U36
T36
U37
T38
T35
FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L
CPU_PECI_MCP
CPU_PROCHOT_L
AH34
U28
AE32
AE30
AE29
U29
W32
AB31
AC32
AC29
C34
A34
1
R1435
1%
1/16W
MF-LF
402 2
49.9
72 9
OUT
72 9
OUT
72
A
72
72
R1431
49.9
1%
1/16W
MF-LF
402 2
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
AB29
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
AH37
AC33
AC31
CPU_REQ0*
CPU_REQ1*
CPU_REQ2*
CPU_REQ3*
CPU_REQ4*
CPU_ADS*
CPU_BNR*
CPU_BR0*
CPU_DBSY*
CPU_DRDY*
CPU_HIT*
CPU_HITM*
CPU_LOCK*
CPU_TRDY*
CPU_PECI
CPU_PROCHOT*
CPU_THERMTRIP*
CPU_FERR*
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
CPU_RS0*
CPU_RS1*
CPU_RS2*
1%
1/16W
MF-LF
2 402
72
1
CPU_DSTBP3*
CPU_DSTBN3*
CPU_DBI3*
CPU_ADSTB0*
CPU_ADSTB1*
W37
W38
B34
OUT
CPU_DSTBP2*
CPU_DSTBN2*
CPU_DBI2*
W36
AB34
U35
T34
W33
72 9
CPU_DSTBP1*
CPU_DSTBN1*
CPU_DBI1*
AE34
U34
AE31
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
CPU_DSTBP0*
CPU_DSTBN0*
CPU_DBI0*
CPU_A3*
CPU_A4*
CPU_A5*
CPU_A6*
CPU_A7*
CPU_A8*
CPU_A9*
CPU_A10*
CPU_A11*
CPU_A12*
CPU_A13*
CPU_A14*
CPU_A15*
CPU_A16*
CPU_A17*
CPU_A18*
CPU_A19*
CPU_A20*
CPU_A21*
CPU_A22*
CPU_A23*
CPU_A24*
CPU_A25*
CPU_A26*
CPU_A27*
CPU_A28*
CPU_A29*
CPU_A30*
CPU_A31*
CPU_A32*
CPU_A33*
CPU_A34*
CPU_A35*
AB32
49.9
7
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
PM_THRMTRIP_L
CPU_FERR_L
R14301
8
K35
L37
T31
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IN
K34
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
BI
72 9
72 9
=PP1V05_S0_MCP_FSB
BI
72 9 6
72 9 6
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
FSB
D
72 9 6
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AH38
AH36
AH35
1
R1436
49.9
1%
1/16W
MF-LF
2 402
6
5
BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND
E34
E37
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
CPU_BPRI* Y31
CPU_DEFER* Y30
FSB_BPRI_L
FSB_DEFER_L
OUT
9 72
OUT
9 72
BCLK_OUT_CPU_N AF32
BCLK_OUT_CPU_P AF33
FSB_CLK_CPU_N
FSB_CLK_CPU_P
OUT
9 72
OUT
9 72
BCLK_OUT_ITP_N AF35
BCLK_OUT_ITP_P AF34
FSB_CLK_ITP_N
FSB_CLK_ITP_P
OUT
12 72
OUT
12 72
CPU_D0*
CPU_D1*
CPU_D2*
CPU_D3*
CPU_D4*
CPU_D5*
CPU_D6*
CPU_D7*
CPU_D8*
CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D16*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D20*
CPU_D21*
CPU_D22*
CPU_D23*
CPU_D24*
CPU_D25*
CPU_D26*
CPU_D27*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*
CPU_D40*
CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D54*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
CPU_D60*
CPU_D61*
CPU_D62*
CPU_D63*
N38
N36
P36
L36
N34
L35
P37
P38
H36
L34
K37
K36
K38
N37
H37
L38
N28
U30
N29
P34
T29
T32
U32
T33
P31
P30
N30
P33
N31
T28
P35
P29
H33
G34
L30
L31
L33
P32
N32
N33
H35
K31
H34
K30
L32
G33
H32
G35
C37
D37
H38
G38
G37
G36
B35
E35
B36
E36
C35
D34
E38
D38
BCLK_OUT_NB_N AF28
BCLK_OUT_NB_P AF29
72
72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
BI
6 9 72
D
C
B
FSB_CLK_MCP_N
FSB_CLK_MCP_P
Loop-back clock for delay matching.
BCLK_IN_P AF30
BCLK_IN_N AF31
CPU_A20M*
CPU_IGNNE*
CPU_INIT*
CPU_INTR
CPU_NMI
CPU_SMI*
CPU_PWRGD
CPU_RESET*
CPU_DPRSLPVR
CPU_SLP*
CPU_DPSLP*
CPU_DPWR*
CPU_STPCLK*
CPU_DPRSTP*
W30
AB30
AB28
W31
AC30
AC28
Y32
AE28
G1
Y33
AB33
U31
Y29
W29
4
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
PM_DPRSLPVR
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
9 72
OUT
9 72
OUT
9 72
OUT
9 72
OUT
9 72
OUT
9 72
OUT
9 12 72
OUT
61 72
OUT
9 72
OUT
9 72
OUT
9 72
OUT
9 72
OUT
9 61 72
=PP1V05_S0_MCP_FSB
NO STUFF
7 13 19 22
1
R1440
150
5%
1/16W
MF-LF
2 402
SYNC_MASTER=T27_MLB
OUT
9 12 72
PAGE TITLE
MCP CPU Interface
DRAWING NUMBER
Apple Inc.
051-8563
R
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
14 OF 109
SHEET
13 OF 80
1
A
7
6
5
4
3
2
OMIT
OMIT
U1400
U1400
MCP89M-A01
MCP89M-A01
FBGA
(2 OF 11)
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
C
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
73 27
BI
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
B
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
OUT
73 27
OUT
73 27
OUT
73 27
OUT
73 27
OUT
73 27
OUT
73 27
OUT
73 27
OUT
AP5
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AP7
AR8
AP8
AR4
AR5
AM8
AN8
AK11
AL11
AH13
AH14
AL10
AK10
AN11
AJ13
AK13
AK14
AJ16
AH16
AJ14
AL13
AM14
AN14
AK17
AL17
AN17
AJ19
AH17
AJ17
AM16
AM17
AN26
AH29
AK29
AL29
AM25
AM26
AL28
AK28
AM28
AP29
AL31
AN32
AP28
AN28
AN31
AM31
AR34
AM32
AL33
AL35
AP32
AP33
AM35
AL32
AJ35
AJ31
AH32
AH33
AJ34
AL34
AJ33
AJ32
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AR7
AM11
AL14
AN16
AJ29
AP31
AM34
AJ30
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
1
FBGA
(3 OF 11)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
AN7
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AM7
AN10
AM10
AN13
AM13
AL16
AK16
AH28
AJ28
AM29
AN29
AP34
AP35
AH31
AG31
MRAS0* AN19
MCAS0* AL19
MWE0* AL20
MEMORY PARTITION 0
D
73 27
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MBA0_2 AL25
MBA0_1 AN20
MBA0_0 AM19
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
MA0_15 AK26
MA0_14 AK25
MA0_13 AJ20
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
AJ26
AH25
AM20
AH26
AN23
AJ25
AM22
AM23
AN22
AL23
AK22
AK23
AL22
+VIO_M2CLK_DLL_1 AF24
+VIO_M2CLK_DLL_2 AG25
+VIO_PLL_MEM_1 AF25
+VIO_PLL_MEM_2 AG26
+VIO_PLL_FSB_1 AF26
+VIO_PLL_FSB_2 AG28
+VIO_PLL_CPU_1
+VIO_PLL_CPU_2
+VIO_PLL_CPU_3
+VIO_PLL_CPU_4
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AC26
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
27 73
73 27
BI
BI
27 73
73 27
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
BI
27 73
73 27
BI
73 27
BI
OUT
25 73
OUT
25 73
OUT
BI
73 27
BI
73 27
BI
73 27
BI
OUT
25 73
73 27
BI
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
25 73
OUT
OUT
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
25 73
25 73
7 22
22
AF27
MCLK0A_1_P AH23
MCLK0A_1_N AJ23
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
OUT
25 73
MCLK0A_0_P AJ22
MCLK0A_0_N AH22
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
OUT
25 73
OUT
25 73
MEM_A_CKE<1>
MEM_A_CKE<0>
73 27
25 73
25 mA
MCKE0A_1 AL26
MCKE0A_0 AN25
BI
25 73
AD26
AE26
MEM_A_ODT<1>
MEM_A_ODT<0>
BI
73 27
OUT
25 mA
MODT0A_1 AH20
MODT0A_0 AK19
BI
73 27
OUT
PP1V05_S0_MCP_PLL_FSBMEM
20 mA
70 mA
MEM_A_CS_L<1>
MEM_A_CS_L<0>
73 27
25 73
550 mA
MCS0A_1* AH19
MCS0A_0* AK20
BI
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
73 27
BI
25 73
73 27
BI
73 27
BI
OUT
25 73
73 27
OUT
OUT
25 73
73 27
OUT
22 20 19
OUT
25 73
OUT
25 73
=PP1V5R1V35_SW_MCP_MEM
R15101
40.2
OUT
20 25 73
OUT
20 25 73
1%
1/16W
MF-LF
402 2
73 27
OUT
73 27
OUT
73 27
OUT
73 27
AP1
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
OUT
73 27
OUT
73 27
OUT
73
73
AR3
AV4
AU4
AP3
AP2
AU3
AT4
AT5
AT7
AU8
AR10
AV5
AU5
AP10
AT8
AT10
AU10
AR13
AR14
AR11
AP11
AT11
AP13
AV14
AU14
AR17
AP17
AP14
AT13
AP16
AR16
AU26
AT26
AU29
AT29
AV25
AV26
AV28
AV29
AT31
AR32
AT34
AU34
AR29
AR31
AU32
AT32
AV35
AT35
AR37
AP38
AV34
AU35
AR36
AR38
AM36
AM37
AJ36
AL36
AP37
AP36
AJ38
AJ37
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT2
AU7
AV10
AT14
AR28
AV32
AT37
AM38
MCP_MEM_COMP_GND
MCP_MEM_COMP_VDD
AG23
AG22
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEMORY PARTITION 1
8
AR2
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AR1
AV7
AV8
AU11
AV11
AU13
AV13
AT28
AU28
AU31
AV31
AU36
AT36
AL38
AL37
MRAS1* AR19
MCAS1* AU17
MWE1* AT17
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MBA1_2 AR25
MBA1_1 AT19
MBA1_0 AR20
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
MA1_15 AP26
MA1_14 AR26
MA1_13 AV16
MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
AP25
AT23
AP20
AU23
AV22
AV23
AT22
AU22
AP23
AR23
AP22
AR22
AT20
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
BI
27 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
OUT
26 73
=PP1V5R1V35_S3_MCP_MEM
D
C
7
1
R1520
1K
5%
1/16W
MF-LF
2 402
MRESET0* AP4
MCLK1A_1_P AU20
MCLK1A_1_N AV20
MCLK1A_0_P AU19
MCLK1A_0_N AV19
MEM_RESET_L
OUT
25 26
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
26 73
OUT
26 73
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
26 73
OUT
26 73
MCS1A_1* AU16
MCS1A_0* AP19
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
26 73
OUT
26 73
MODT1A_1 AT16
MODT1A_0 AV17
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
26 73
OUT
26 73
MCKE1A_1 AU25
MCKE1A_0 AT25
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
20 26 73
OUT
20 26 73
B
MEM_COMP_GND
MEM_COMP_VDD
R15111
40.2
1%
1/16W
MF-LF
402 2
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Memory Interface
DRAWING NUMBER
Apple Inc.
051-8563
R
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009).
8
7
6
5
K6/K69 EDP currents used.
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
15 OF 109
SHEET
14 OF 80
1
A
8
7
6
5
4
3
2
1
OMIT
U1400
MCP89M-A01
8
29
D
31
34
34
PEG_CLKREQ_L
IN
AP_CLKREQ_L
W5
IN
W7
ENET_CLKREQ_L
IN
FW_CLKREQ_L
W8
OUT
FW_PWR_EN
W6
FBGA
(4 OF 11)
PEA_CLKREQ*/GPIO_49
PE0_REFCLK_P Y1
(IPU)
PE0_REFCLK_N W1
PEB_CLKREQ*/GPIO_50
(IPU)
PE1_REFCLK_P W3
PE1_REFCLK_N W2
PEC_CLKREQ*/GPIO_51
(IPU)
PE2_REFCLK_P U4
PED_CLKREQ*/GPIO_52
PE2_REFCLK_N U5
(IPU)
PE3_REFCLK_P U7
PEE_CLKREQ*/GPIO_53
(IPU)
PE3_REFCLK_N U6
34
IN
FW_PME_L
W9
PEF_CLKREQ*/GPIO_54
(IPU)
29 24 6
IN
PCIE_WAKE_L
U3
PE_WAKE*
(IPU-S5)
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
8
IN
74 33
IN
74 33
IN
74 29 6
IN
74 29 6
IN
74 31
IN
74 31
IN
22
22
=PEG_D2R_P<0>
=PEG_D2R_N<0>
AC1
AB1
PEG_CLK100M_P
PEG_CLK100M_N
OUT
8 74
OUT
8 74
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
OUT
29 74
OUT
29 74
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
OUT
31 74
OUT
31 74
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
33 74
OUT
33 74
PE4_REFCLK_P U9
PE4_REFCLK_N U8
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
PE5_REFCLK_P W10
PE5_REFCLK_N W11
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N
PE0_TX0_P AC3
PE0_TX0_N AC2
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
OUT
8
OUT
8
=PEG_D2R_P<1>
=PEG_D2R_N<1>
AC5
AC4
PE0_RX1_P
PE0_RX1_N
PE0_TX1_P AB2
PE0_TX1_N AB3
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
OUT
8
OUT
8
=PEG_D2R_P<2>
=PEG_D2R_N<2>
AC10
AC11
PE0_RX2_P
PE0_RX2_N
PE0_TX2_P AC6
PE0_TX2_N AC7
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
OUT
8
OUT
8
=PEG_D2R_P<3>
=PEG_D2R_N<3>
AB7
AB6
PE0_RX3_P
PE0_RX3_N
PE0_TX3_P AC8
PE0_TX3_N AC9
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
OUT
8
OUT
8
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
AB9
AB8
PE0_RX4_P
PE0_RX4_N
PE0_TX4_P AB4
PE0_TX4_N AB5
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
PCIE_FW_D2R_P
PCIE_FW_D2R_N
Y2
Y3
PE0_RX5_P
PE0_RX5_N
PE0_TX5_P Y5
PE0_TX5_N Y4
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
OUT
33 74
OUT
33 74
PCIE_AP_D2R_P
PCIE_AP_D2R_N
AB11
AB10
PE1_RX0_P
PE1_RX0_N
PE1_TX0_P Y7
PE1_TX0_N Y6
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
OUT
29 74
OUT
29 74
Y10
Y11
PE1_RX1_P
PE1_RX1_N
PE1_TX1_P Y9
PE1_TX1_N Y8
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
OUT
31 74
OUT
31 74
OUT
18 24
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PP3V3_S0_MCP_PLL_HVDD
50 mA
V11
V13
PP1V05_S0_MCP_PLL_PEXSATA
325 mA
100 mA
+3.3V_PLL_HVDD_1
+3.3V_PLL_HVDD_2
AH10
+VIO_PLL_PE
80 mA
AG11
AF12
AF13
+VIO_PLL_XREF_XS_1
+VIO_PLL_XREF_XS_2
+VIO_PLL_XREF_XS_3
120 mA
AH8
AH9
25 mA
AH11
(IPD) PEX_RST* U1
PCIE_RESET_L
NO STUFF
D
PE0 ports are Gen2-capable.
PE1 ports are Gen1-only.
PE0_RX0_P
PE0_RX0_N
PCI EXPRESS
C
IN
W4
4 RCs: 4x, x2, x1, x1
2 RCs: x1, x1
If PE0[3:0] are not used,
+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND
C
If PE0[4:5] and PE1[0:1] are not used,
+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND
1
R1600
10K
5%
1/16W
MF-LF
2 402
+VIO_PLL_SATA_1
+VIO_PLL_SATA_2
+VIO_PLL_H
PEX0_TERM_P U2
74
MCP_PEX0_TERMP
R16101
2.49K
1%
1/16W
MF-LF
402 2
B
B
PLACE_NEAR=U1400.U2:12.7 mm
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP PCIe Interfaces
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
16 OF 109
SHEET
15 OF 80
1
A
8
7
6
5
4
3
2
1
OMIT
D
D
U1400
MCP89M-A01
8
C
NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
IN
8
IN
36 16
OUT
16 8
BI
16 8
BI
8
BI
8
BI
22
TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF
22
B
23 7
RGB_DAC_RSET
RGB_DAC_VREF
D26
E26
DP0_3_P/TMDS0_TXC_P
DP0_3_N/TMDS0_TXC_N
DP_IG_ML0_P<2>
DP_IG_ML0_N<2>
DP_IG_ML0_P<1>
DP_IG_ML0_N<1>
DP_IG_ML0_P<0>
DP_IG_ML0_N<0>
G26
F26
F25
G25
E25
D25
DP0_2_P/TMDS0_TX0_P
DP0_2_N/TMDS0_TX0_N
DP0_1_P/TMDS0_TX1_P
DP0_1_N/TMDS0_TX1_N
DP0_0_P/TMDS0_TX2_P
DP0_0_N/TMDS0_TX2_N
DDC_CLK0/GPIO_38 F29
DDC_DATA0/GPIO_39 H25
DP_IG_ML1_P<2>
DP_IG_ML1_N<2>
DP_IG_ML1_P<1>
DP_IG_ML1_N<1>
DP_IG_ML1_P<0>
DP_IG_ML1_N<0>
E28
D28
A28
A29
C28
B28
DP1_2_P/TMDS0_TX3_P
DP1_2_N/TMDS0_TX3_N
DP1_1_P/TMDS0_TX4_P
DP1_1_N/TMDS0_TX4_N
DP1_0_P/TMDS0_TX5_P
DP1_0_N/TMDS0_TX5_N
DP_IG_HPD0
DP_IG_HPD1
SATARDRVR_A_EN
H26
J26
J25
HPLUG_DET0/GPIO_20
HPLUG_DET1/GPIO_21
HPLUG_DET2/GPIO_22
DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N
L28
K28
DDC_CLK2/DP_AUX_CH0_P
DDC_DATA2/DP_AUX_CH0_N
DP_IG_AUX_CH1_P
DP_IG_AUX_CH1_N
K25
K26
DDC_CLK3/DP_AUX_CH1_P
DDC_DATA3/DP_AUX_CH1_N
M23
N22
+3.3V_PLL_DP0_1
+3.3V_PLL_DP0_2
PP3V3_S0_MCP_PLL_DP_USB
210 mA
180 mA
60 mA
PP1V05_S0_MCP_PLL_CORE
160 mA
40 mA
60 mA
180 mA
160 mA
DP1_3_P/TMDS0B_TXC_P
DP1_3_N/TMDS0B_TXC_N
N21
M22
+3.3V_PLL_USB_1
+3.3V_PLL_USB_2
N23
L24
+VIO_PLL_IFPAB_1
+VIO_PLL_IFPAB_2
M25
N25
L26
M26
N24
L25
+VIO_PLL_CORE_LEG
+VIO_PLL_SPPLL0_1
+VIO_PLL_SPPLL0_2
+VIO_PLL_V
+VIO_PLL_NV_1
+VIO_PLL_NV_2
A22
A23
+VDD_IFPA
+VDD_IFPB
A26
B26
C26
+VIO_DP0_1
+VIO_DP0_2
+VIO_DP0_3
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
RGB_DAC_HSYNC D31
RGB_DAC_VSYNC E31
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
DP_IG_ML1_P<3>
DP_IG_ML1_N<3>
AUD_IP_PERIPHERAL_DET
MIKEY_MIC_LOAD_DET
RGB_DAC_RED C31
RGB_DAC_GREEN B31
RGB_DAC_BLUE A31
IFPA_TXC_P K22
IFPA_TXC_N L22
F28
G28
40 mA
20 mA
23 7
+3.3V_RGBDAC
C29
D29
DP_IG_ML0_P<3>
DP_IG_ML0_N<3>
30 mA
23 7
B29
FLAT PANEL
8
PP3V3_S0_MCP_DAC
140 mA
RGB
23
FBGA
(5 OF 11)
C22
B22
E22
D22
F22
G22
H22
J22
IFPB_TXC_P B23
IFPB_TXC_N C23
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
L23
K23
J23
H23
G23
F23
D23
E23
DDC_CLK1/GPIO_40 J28
DDC_DATA1/GPIO_41 G29
LCD_BKL_CTL/GPIO_57 A25
LCD_BKL_ON/GPIO_59 B25
LCD_PANEL_PWR/GPIO_58 C25
=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N
IN
16 56
IN
16
RGB DAC Disable:
8
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required
Connect +3.3V_RGBDAC pin to GND.
8
8
NOTE: No Composite/S-Video/Component Video support on MCP89
8
Interface Mode
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
OUT
8
=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA
OUT
8
(GMUX_INT)
LCD_IG_BKLT_PWM
LCD_IG_BKLT_EN
LCD_IG_PWR_EN
OUT
8
OUT
8
OUT
67
MCP_IFPAB_VPROBE
OUT
23 74
MCP_IFPAB_RSET
OUT
23 74
MCP_TMDS0_VPROBE
OUT
23 74
MCP_TMDS0_RSET
OUT
23 74
=MCP_IFPA_TXD_P<0>
=MCP_IFPA_TXD_N<0>
=MCP_IFPA_TXD_P<1>
=MCP_IFPA_TXD_N<1>
=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXD_N<2>
=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<3>
=MCP_IFPB_TXC_P
=MCP_IFPB_TXC_N
=MCP_IFPB_TXD_P<0>
=MCP_IFPB_TXD_N<0>
=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXD_N<1>
=MCP_IFPB_TXD_P<2>
=MCP_IFPB_TXD_N<2>
=MCP_IFPB_TXD_P<3>
=MCP_IFPB_TXD_N<3>
(or use as GPIOs).
8
BI
MCP Signal
TMDS/HDMI
LVDS
=MCP_IFPA_TXC_P/N
=MCP_IFPA_TXD_P/N<0>
=MCP_IFPB_TXC_P/N
=MCP_IFPB_TXD_P/N<0>
=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
(UNUSED)
(UNUSED)
TMDS_IG_TXD_P/N<3>
TMDS_IG_TXD_P/N<4>
TMDS_IG_TXD_P/N<5>
(UNUSED)
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
LVDS_IG_A_CLK_P/N
LVDS_IG_A_DATA_P/N<0>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
C
LVDS: Power +VDD_IFPx at 1.8V
TMDS: Power +VDD_IFPx at 3.3V
8
B
IFPAB_VPROBE L20
IFPAB_RSET K20
TMDS0_VPROBE H28
TMDS0_RSET F31
DDC Mode Pull-downs
NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then
only pull-ups are necessary.
A
R1710 100K
R1711 100K
1
1
2
2
5%
5%
1/16W MF-LF 402
1/16W MF-LF 402
DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N
8 16
8 16
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Graphics
GPIO Pull-Ups
=PP3V3_S0_MCP_GPIO
R1780
R1781
R1782
10K
10K
10K
1
1
1
2
2
2
DRAWING NUMBER
Apple Inc.
R
5%
5%
5%
1/16W MF-LF 402
1/16W MF-LF 402
1/16W MF-LF 402
SATARDRVR_A_EN
MIKEY_MIC_LOAD_DET
7
SIZE
D
A.13.0
7 17 18
BRANCH
16 36
16 56
16
8
051-8563
REVISION
6
5
4
3
2
PAGE
17 OF 109
SHEET
16 OF 80
1
A
8
7
6
5
4
3
2
1
OMIT
U1400
MCP89M-A01
FBGA
(6 OF 11)
IN
74 36
OUT
74 36
OUT
74 36
IN
74 36
IN
C20
B20
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ4
AJ5
SATA_A0_RX_N
SATA_A0_RX_P
USB1_P
USB1_N
J20
H20
USB2_P
USB2_N
C19
B19
USB3_P
USB3_N
G20
F20
USB4_P
USB4_N
E20
D20
USB5_P
USB5_N
E19
D19
USB6_P
USB6_N
G19
F19
USB7_P
USB7_N
J17
H17
USB8_P
USB8_N
J19
H19
USB9_P
USB9_N
C17
B17
USB10_P
USB10_N
E17
D17
USB11_N
USB11_P
G17
F17
USB_OC0*/GPIO_25
USB_OC1*/GPIO_26
USB_OC2*/GPIO_27_MGPIO_0
USB_OC3*/GPIO_28_MGPIO_1
A17
L17
K17
K19
USB_RBIAS_GND
L19
RGMII_VREF
C13
MCP_RGMII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
G13
H13
F14
D14
TP_ENET_TXD<0>
TP_ENET_TXD<1>
TP_ENET_TXD<2>
TP_ENET_TXD<3>
RGMII_TXCLK
RGMII_TXCTL
G14
E14
TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL
RGMII_MDC
RGMII_MDIO
F13
K13
TP_ENET_MDC
ENET_MDIO
BUF_25MHZ
J13
TP_MCP_CLK25M_BUF0_R
RGMII_RESET*
J14
TP_ENET_RESET_L
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
AJ3
AJ2
SATA_A1_TX_P
SATA_A1_TX_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
AH2
AH3
SATA_A1_RX_N
SATA_A1_RX_P
AJ6
AJ7
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
AH7
AH6
TP_SATA_C_D2RN
TP_SATA_C_D2RP
18 16 7
=PP3V3_S0_MCP_GPIO
1
R1800
100K
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
AL4
AL3
SATA_B1_TX_P
SATA_B1_TX_N
TP_SATA_D_D2RN
TP_SATA_D_D2RP
AL1
AL2
SATA_B1_RX_N
SATA_B1_RX_P
5%
1/16W
MF-LF
402 2
AH1
MXM_GOOD_L
AJ1
MCP_SATA_TERMP
74
SATA_LED*/GPIO_30
SATA_TERMP
1
R1805
2.49K
1%
1/16W
MF-LF
2 402
22 19 7
R18101
49.9
1%
1/16W
MF-LF
402 2
B
NC
NC
NC
NC
G4
E7
F7
F4
NC_1
NC_2
NC_3
NC_4
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
B14
C14
D16
F16
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
IN
ENET_CLK125M_RXCLK
ENET_RX_CTRL
E16
A14
RGMII_RXCLK
RGMII_RXCTL
IN
ENET_ENERGY_DET
H14
RGMII_INTR/GPIO_35
M16
+3.3V_PLL_MAC_DUAL
76 8
IN
76 8
IN
76 8
IN
76 8
IN
76 8
IN
76 8
31
22
PP3V3_ENET_MCP_PLL_MAC
20 mA
76
76
R18111
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
D13
E13
LAN
C
RGMII_COMP_VDD
RGMII_COMP_GND
OHCI0/EHCI0
IN
74 36
USB0_N
USB0_P
OHCI1/EHCI1
74 36
SATA_A0_TX_P
SATA_A0_TX_N
Internal 19.5K Pull-Downs on all USB pairs
OUT
AH4
AH5
USB
74 36
External A
USB_EXTA_N
USB_EXTA_P
AirPort (PCIe Mini-Card)
USB_MINI_P
USB_MINI_N
T57
NC_USB_T57_P
NC_USB_T57_N
External C
USB_EXTC_P
USB_EXTC_N
Watermelon
USB_WM_P
USB_WM_N
Camera/External E
USB_CAMERA_P
USB_CAMERA_N
SD Card/ExpressCard
USB_SDCARD_P
USB_SDCARD_N
External D
USB_EXTD_P
USB_EXTD_N
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
External B
USB_EXTB_P
USB_EXTB_N
IR
USB_IR_P
USB_IR_N
Bluetooth
USB_BT_N
USB_BT_P
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
Only USB8-11 support nV
USB JTAG in S3/S4/S5.
OUT
SATA
D
74 36
75
BI
37 75
BI
37 75
BI
8 75
BI
8 75
D
BI
BI
BI
8 75
BI
8 75
BI
8 75
BI
8 75
BI
29 75
BI
29 75
BI
30 75
BI
30 75
BI
8 75
BI
8 75
BI
47 75
BI
47 75
BI
37 75
BI
37 75
BI
38 75
BI
38 75
=PP3V3_S5_MCP_GPIO
1
R1851
29 75
BI
29 75
R1853
8.2K
5%
1/16W
MF-LF
2 402
R18501
R18521
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
8.2K
BI
1
8.2K
5%
1/16W
MF-LF
2 402
7 18
C
8.2K
USB_EXTA_OC_L 37
USB_EXTB_OC_L 37
USB_EXTC_OC_L
USB_EXTD_OC_L
OC2# Also for EXTE
OC3# Also for EXCARD
MCP_USB_RBIAS_GND
1
IN
8
R1860
887
1%
1/16W
MF-LF
2 402
BI
8 76
B
Internal MAC Disable:
49.9
1%
1/16W
MF-LF
402 2
Connect RGMII_RXD<0:3> together to 10K pull-down.
Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.
All other pins can be left TP or NC.
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP SATA, USB & Ethernet
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
18 OF 109
SHEET
17 OF 80
1
A
8
7
6
5
4
3
=PP3V3_S0_MCP_GPIO
OMIT
10K
5%
1/16W
MF-LF
1 402
FBGA
(7 OF 11)
D6
7 16 17 18
R1961
U1400
=PP3V3R1V5_S0_MCP_HDA
70 mA
HDA_SDATA_OUT E1
+VDD_HDA
75 18
R1950
HDA_SDOUT_R
49.9
56
1%
1/16W
MF-LF
402 2
OUT
E3
AUD_IPHS_SWITCH_EN
Output limited to +VDD_HDA.
Confirmed OK for this signal.
75
D3
MCP_HDA_PULLDN_COMP
HDA_BITCLK E4
HDA_SDATA_IN0
(IPD)
HDA_SDATA_IN1/GPIO_2
(IPD)
75 18
HDA_BIT_CLK_R
22
1
2
5%
1/16W
MF-LF
402
HDA
R19001
E2
HDA_SDIN0
IN
HDA_RESET* D1
75 18
75 18
HDA_SYNC_R
22
1
22
1
HDA_SDOUT
OUT
51 75
HDA_BIT_CLK
OUT
51 75
HDA_RST_L
OUT
51 75
HDA_SYNC
OUT
51 75
D
R1952
HDA_RST_R_L
2
5%
1/16W
MF-LF
402
R1953
HDA_SYNC D2
HDA_PULLDN_COMP
2
5%
1/16W
MF-LF
402
R1951
75 51
22
1
70 mA
D
1
2
MCP89M-A01
22 8
2
2
BUF_SIO_CLK Frequency
Frequency
5%
1/16W
MF-LF
402
BI
75 41 39
BI
75 41 39
BI
R1910
R1911
R1912
R1913
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
1
1
1
1
2
2
2
2
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
PP3V3_G3_RTC
R19201
49.9K
C
1%
1/16W
MF-LF
402 2
1
R1921
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
41 39
IN
39
IN
12
OUT
56
IN
39
IN
39
IN
24
IN
1%
1/16W
MF-LF
2 402
39
IN
24
IN
40
HDA Output Caps
C1950
C1952
1
10PF
B
1
10PF
5%
2 50V
CERM
402
SMC_WAKE_SCI_L
PM_LATRIGGER_L
AUD_I2C_INT_L
SMC_RUNTIME_SCI_L
D11
G11
B3
H2
SIO_PME*/GPIO_31
EXT_SMI*/GPIO_32
A20GATE/GPIO_55
KBRDRSTIN*/GPIO_56
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
J10
F10
PWRBTN* (IPU-S5)
RSTBTN* (IPU-S5)
RTC_RST_L
G16
RTC_RST*
PM_RSMRST_L
MCP_PS_PWRGD
C11
C2
H16
B7
20
OUT
MCP_MEM_VTT_EN
G10
MEMVTT_EN/GPIO_45
SM_INTRUDER_L
J16
INTRUDER*
18 75
18 6
OUT
21 18
OUT
50 41 18 6
BI
12
IN
12
OUT
12
IN
12
IN
12
IN
24
IN
24
OUT
24
IN
24
OUT
G5
H5
H10
J11
MGPU_PIO0/GPIO_6
MGPU_PIO1/GPIO_7
MGPU_PIO2/GPIO_23
MGPU_PIO3/GPIO_24
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
C10
D10
B10
E10
A10
JTAG_TDI (IPU)
JTAG_TDO
JTAG_TMS (IPU)
JTAG_TRST* (IPD)
JTAG_TCK
5%
1/16W
MF-LF
402 2
15 24
1
2
2
R1983 10K
R1984 10K
R1985 100K
R1987 100K
R1988 10K
R1989 10K
R1990 10K
R1991 10K
R1992 100K
R1993 100K
R1994 100K
R1995 100K
R1996 10K
R1997 100K
R1998 20K
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
2
1
2
1
2
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
SDCARD_RESET
T57_RESET
GFXVCORE_PWR_EN
SPIROM_USE_MLB
MCP_CPU_VTT_EN_L
MLB_RAM_VENDOR
T57_PWR_EN
LPCPLUS_GPIO
ODD_PWR_EN_L
MEM_EVENT_L
ENET_LOW_PWR
SMC_IG_THROTTLE_L
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID<3>
B16
C16
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
LPC_FRAME_L
1
0
LPC_RESET_L
OUT
18 24 75
LPC_CLK33M_SMC_R
OUT
24 75
MCP_CPU_VTT_EN_L
MLB_RAM_VENDOR
T57_PWR_EN
SMC_ADAPTER_EN
LPCPLUS_GPIO
MCP_MEM_VDD_SEL_1V5
H7
H6
G6
H4
ODD_PWR_EN_L
MEM_EVENT_L
ENET_LOW_PWR
SDCARD_RESET
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
MCP_VID3/GPIO_16
K3
K4
K5
K6
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID<3>
SPI_CS0*/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_08
SPI_DO/GPIO_09
E11
D7
F11
B8
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
BI
IN
BI
6 18
39 40 65
18 41
OUT
60
OUT
18 36
IN
IN
OUT
8 18 31
A4
B4
A5
B5
C5
65
OUT
18 62
OUT
18 62
OUT
18 62
OUT
18 62
OUT
41 75
45 79
OUT
12 42 75
BI
0
0
31.2 MHz
0
1
42.7 MHz
1
0
62.5 MHz
1
1
12 42 75
42 75
42 75
40
1
R1970
10K
5%
1/16W
MF-LF
2 402
MCP_SPKR:
0 = USER mode (Normal boot mode)
1 = SAFE mode (For ROMSIP recovery)
B
Connects to SMC for automatic recovery.
18 29 65
18
PM_CLK32K_SUSCLK_R
TEST_MODE_EN D4
PKG_TEST L16
PKG_TEST2 K16
OUT
OUT
ARB_DETECT_L
25.0 MHz
NOTE: 42 & 62 MHz use FAST_READ command.
Straps not provided on this page.
41 75
45 79
OUT
C
41 75
6 18 41 75
OUT
BI
1
Frequency SPI_DO SPI_CLK
OUT
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
0
SPI
SPI Frequency Select
6 39 65 69
6 18 39 40 65
OUT
LPC_FRAME#
LPC
NOTE: MCP89 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.
18 30
OUT
IN
NOTE: MCP89 A01 has
strong (~10K)
pull-downs on
these pins.
I/F
18 25 26 39
OUT
OUT
MCP_THMDIODE_P
MCP_THMDIODE_N
SUS_CLK/GPIO_34 H11
XTALIN_RTC
XTALOUT_RTC
18
MCP_SPKR
THERM_DIODE_P G3
THERM_DIODE_N G2
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64
18
OUT
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
BIOS Boot Select
OUT
24 75
MCP_TEST_MODE_EN
NO STUFF
R1959
1
R1931
100K
5%
1/16W
MF-LF
2 402
1
1
R1966
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R1975
1K
1%
1/16W
MF-LF
2 402
18 30
6 18
18 21
6 18 41 50
Platform-Specific Connections
18
R1965
18
6 18
75 24 18
IN
LPC_RESET_L
1
33
2
LPC_PWRDWN_L
OUT
39 41
PM_SLP_S5_L
OUT
39
5%
1/16W
MF-LF
402
18 41
18 36
65 40 39 18 6
18 25 26 39
IN
PM_SLP_S4_L
MAKE_BASE=TRUE
8 18 31
NOTE: MCP SLP_S5# signal has the
behavior of Intel’s SLP_S4# signal.
18 40
SYNC_MASTER=T27_MLB
PAGE TITLE
18 62
MCP HDA, LPC & MISC
18 62
DRAWING NUMBER
18 62
18 62
AP_PWR_EN
18 29 65
ARB_DETECT_L
18
SPI_MISO
6 18 41 75
7
2
39 41 75
K10
C8
A8
D8
G8
C7
SPKR/GPIO_1 H3
XTALIN
XTALOUT
Apple Inc.
051-8563
6
5
4
3
2
SIZE
D
REVISION
R
8
22
1
OUT
1
7 16 17 18
5%
5%
5%
5%
A11
B11
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
10K
1
MISC_VDDEN0/GPIO_47
MISC_VDDEN1/GPIO_48
MISC_VDDEN2/GPIO_17
MISC_VDDEN3/GPIO_18
MISC_VDDEN4/GPIO_19
MEM_VDD_SEL/GPIO_46
FANCTL0/GPIO_61
FANRPM0/GPIO_60/MGPIO_2
FANCTL1/GPIO_62
FANRPM1/GPIO_63/MGPIO_3
MCP_WAKE_DIS*
(IPU-S5)
MCP_MEMVDD_EN/GPIO_44
SMC_IG_THROTTLE_L
T57_RESET
GFXVCORE_PWR_EN
SPIROM_USE_MLB
R19301
7
2
2
LPC_CLK0 L5
BUF_SIO_CLK/GPIO_33 H1
7 17
1
1
(IPD) LPC_RESET* K7
MCP_WAKE_REQ*
A7
OUT
LPC_FRAME_R_L
24 MHz
14.31818 MHz
39 41
BI
HDA_SYNC
5%
1/16W
MF-LF
402
PWRGD_SB
PWRGD
MCP_MEM_VDD_EN
10PF
R1980 10K
R1981 10K
R1999 100K
R1986 100K
LPC_FRAME* L7
(IPD)
SLP_S3* C4
(IPD) SLP_RMGT* K9
(IPD)
SLP_S5* D5
PM_BATLOW_L
40 18
18 75
5%
2 50V
CERM
402
1
LPC_CLKRUN*/GPIO_42 (IPU)
LPC_SERIRQ
R1960
18 75
GPIO Pull-Ups/Downs
A
L6
IN
C1953
=PP3V3_S5_MCP_GPIO
=PP3V3_S3_MCP_GPIO
=PP3V3_S0_MCP_GPIO
PCIE_RESET_L
PM_CLKRUN_L
MCP_WAKE_REQ_L
18 75
1
C1951
LPC_DRQ0*/GPIO_43
(IPU)
OUT
39
5%
50V
CERM 2
402
1
K2
(IPU)
(IPU)
(IPU)
(IPU)
65 20
10PF
5%
50V
CERM 2
402
TP_MLB_RAM_SIZE
OUT
For EMI Reduction on HDA interface
HDA_RST_R_L
HDA_SYNC_R
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
49.9K
NOTE: MCP89 A01 has strong (~10K)
pull-downs on these pins.
HDA_SDOUT_R
HDA_BIT_CLK_R
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
(IPU-S5)
(IPU)
22 19 7
22
22
22
22
LPC
BI
75 41 39
LPC_SERIRQ L8
(IPU)
MISC
75 41 39
K1
L1
L2
L3
A.13.0
BRANCH
PAGE
19 OF 109
SHEET
18 OF 80
1
A
8
7
6
5
4
3
2
1
NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.
22 13 7
C
=PP1V05_S0_MCP_FSB
200 mA
W27
W28
Y27
Y28
22 7
MCP89M-A01
MCP89M-A01
AG14
AL7
AF18
AF21
AM1
AM4
AK8
AG13
AF16
AF22
AG20
AM5
AG19
AF23
AJ9
AF19
AG17
AL6
AG16
AH12
AM2
AF15
AM3
AL5
AL8
AF17
AJ11
AJ8
AF14
AJ10
AF20
4300 mA
FBGA
(9 OF 11)
=PPVCORE_S0_MCP
8450 mA (0.85V)
14 20 22
NOTE: VDD_COREx_SENSE signals should NOT
be used for remote sensing unless
COREA/COREB are powered by separate
regulators.
Instead connect regulator sense point
as close to COREB FET as possible.
TP_MCP_VDDCOREA_SENSEP
TP_MCP_VDDCOREA_SENSEN
7
7
7
7
200 mA (DVDD0 & DVDD1)
(PE0[3:0])
200 mA (DVDD0 & DVDD1)
(PE0[5:4], PE1[1:0])
500 mA (AVDD0 & AVDD1)
(PE0[3:0])
500 mA (AVDD0 & AVDD1)
(PE0[5:4], PE1[1:0])
B
22 7
22 7
22 7
22 18 7
=PP3V3_S0_MCP_HVDD
30 mA
=PP3V3_S0_MCP
250 mA
150 mA
PP3V3_G3_RTC
?? uA (G3)
5 mA (S0)
T3
AB22
AB20
R13
R7
T6
T13
R11
AB17
R10
AB18
T1
T2
AB21
R4
AB19
P13
R2
T8
R8
T4
R5
T7
T5
T9
U22
V22
W22
Y22
AA22
P12
P10
P11
L10
L9
+VDD_COREA_1
+VDD_COREA_2
+VDD_COREA_3
+VDD_COREA_4
+VDD_COREA_5
+VDD_COREA_6
+VDD_COREA_7
+VDD_COREA_8
+VDD_COREA_9
+VDD_COREA_10
+VDD_COREA_11
+VDD_COREA_12
+VDD_COREA_13
+VDD_COREA_14
+VDD_COREA_15
+VDD_COREA_16
+VDD_COREA_17
+VDD_COREA_18
+VDD_COREA_19
+VDD_COREA_20
+VDD_COREA_21
+VDD_COREA_22
+VDD_COREA_23
+VDD_COREA_24
+VDD_COREA_25
+VDD_COREA_26
+VDD_COREA_27
+VDD_COREA_28
+VDD_COREA_29
+VDD_COREA_30
+VDD_COREA_31
+VDD_COREA_32
+VDD_COREA_33
+VDD_COREB_1
+VDD_COREB_2
+VDD_COREB_3
+VDD_COREB_4
+VDD_COREB_5
+VDD_COREB_6
+VDD_COREB_7
+VDD_COREB_8
+VDD_COREB_9
+VDD_COREB_10
+VDD_COREB_11
+VDD_COREB_12
+VDD_COREB_13
+VDD_COREB_14
+VDD_COREB_15
+VDD_COREB_16
+VDD_COREB_17
+VDD_COREB_18
+VDD_COREB_19
+VDD_COREB_20
+VDD_COREB_21
+VDD_COREB_22
+VDD_COREB_23
+VDD_COREB_24
+VDD_COREB_25
+VDD_COREB_26
+VDD_COREB_27
+VDD_COREB_28
+VDD_COREB_29
+VDD_COREB_30
+VDD_COREB_31
+VDD_COREB_32
+VDD_COREB_33
+VDD_COREB_34
+VDD_COREB_35
+VDD_COREB_36
+VDD_COREB_37
+VDD_COREB_38
+VDD_COREB_39
+VDD_COREB_40
+VDD_COREB_41
+VDD_COREB_42
+VDD_COREA_SENSE
GND_COREA_SENSE
M4
M2
P4
N12
N4
N14
V20
N10
P3
P1
N11
N6
P6
N2
N9
N8
M10
N3
N1
M5
M7
P2
M8
M11
V19
N7
N16
P5
N5
N13
N15
P9
V17
V18
M14
M13
Y19
Y20
Y17
Y18
P7
P8
AF7
AF8
AE9
AE10
+VIO_PE_DVDD0_1
+VIO_PE_DVDD0_2
+VIO_PE_DVDD0_3
+VIO_PE_DVDD0_4
AE6
AE7
AE8
+VIO_PE_DVDD1_1
+VIO_PE_DVDD1_2
+VIO_PE_DVDD1_3
+VDD_COREB_SENSE U10
GND_COREB_SENSE T10
AC13
AB12
AC12
AD11
AD13
AB13
+VIO_PE_AVDD0_1
+VIO_PE_AVDD0_2
+VIO_PE_AVDD0_3
+VIO_PE_AVDD0_4
+VIO_PE_AVDD0_5
+VIO_PE_AVDD0_6
+VIO_SATA_AVDD_1
+VIO_SATA_AVDD_2
+VIO_SATA_AVDD_3
+VIO_SATA_AVDD_4
+VIO_SATA_AVDD_5
Y12
Y13
AA13
W12
W13
+VIO_PE_AVDD1_1
+VIO_PE_AVDD1_2
+VIO_PE_AVDD1_3
+VIO_PE_AVDD1_4
+VIO_PE_AVDD1_5
T11
T12
U13
+3.3V_HVDD_1
+3.3V_HVDD_2
+3.3V_HVDD_3
U11
U12
F5
E29
E5
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
L11
M17
M20
+VDD_DUAL_AUXC_1
+VDD_DUAL_AUXC_2
+VDD_DUAL_AUXC_3
A16
+3.3V_VBAT
+VIO_SATA_DVDD_1
+VIO_SATA_DVDD_2
+VIO_SATA_DVDD_3
+VIO_SATA_DVDD_4
+VIO_SATA_DVDD_5
+VIO_SATA_DVDD_6
+VIO_SATA_DVDD_7
+VIO_SATA_DVDD_8
+VIO_SATA_DVDD_9
+VIO_SATA_DVDD_10
+VIO_SATA_DVDD_11
+VIO_SATA_DVDD_12
AE1
AE2
AE3
AE4
AE5
AF1
AF2
AF3
AF4
AF5
AF6
AF9
AF10
AF11
AE11
AE12
AE13
+VDD_DUAL_RMGT_1 L12
+VDD_DUAL_RMGT_2 L13
+3.3V_DUAL_RMGT_1 A13
+3.3V_DUAL_RMGT_2 B13
+3.3V_DUAL_USB_1 A20
+3.3V_DUAL_USB_2 A19
+3.3V_DUAL_1 F8
+3.3V_DUAL_2 E8
=PPVCORE_SW_MCP_GFX
15350 mA (0.85V)
21 23
TP_MCP_VDDCOREB_SENSEP
TP_MCP_VDDCOREB_SENSEN
PP1V05_S0_MCP_SATA_AVDD
300 mA
100 mA
140 mA
300 mA
=PP3V3_S5_MCP
200 mA
22
7 22
7 22
AP21
M37
AM21
AU37
AC27
D18
B1
AD5
J2
AT1
AM30
C1
AT3
AP24
AM33
AE27
AJ24
AH18
AA8
AM18
B6
J32
AJ21
AK35
H15
D33
B18
M32
B2
E6
J5
K18
AN34
AD10
F34
V8
R35
AR9
AA2
AA10
R32
AG29
H8
AP12
AM12
AH21
V32
AR33
J7
AA32
AG34
AK37
K24
K21
J8
AG8
AN5
V2
AD32
AD2
D15
AG2
L15
AK32
AR12
AN35
AN37
FBGA
(10 OF 11)
GND_1
GND_68 AD7
GND_2
GND_69 B12
GND_3
GND_70 D12
GND_4
GND_71 E12
GND_5
GND_72 G12
GND_6
GND_73 A2
GND_7
GND_74 AL12
GND_8
GND_75 AM6
GND_9
GND_76 AD37
GND_10
GND_77 AG32
GND_11
GND_78 H12
GND_12
GND_79 AR35
GND_13
GND_80 H9
GND_14
GND_81 G24
GND_15
GND_82 V10
GND_16
GND_83 V5
GND_17
GND_84 AL30
GND_18
GND_85 G7
GND_19
GND_86 V29
GND_20
GND_87 AP15
GND_21
GND_88 AN2
GND_22
GND_89 AJ12
GND_23
GND_90 AR15
GND_24
GND_91 N20
GND_25
GND_92 D21
GND_26
GND_93 E21
GND_27
GND_94 G21
GND_28
GND_95 H21
GND_29
GND_96 AR27
GND_30
GND_97 AM27
GND_31
GND_98 AP27
GND_32
GND_99 AM15
GND_33
GND_100 AA31
GND_34
GND_101 AM9
GND_35
GND_102 AH24
GND_36
GND_103 K12
GND_37
GND_104 J31
GND_38
GND_105 E30
GND_39
GND_106 AK7
GND_40
GND_107 V7
GND_41
GND_108 M31
GND_42
GND_109 AU12
GND_43
GND_110 AP6
GND_44
GND_111 B37
GND_45
GND_112 A36
GND_46
GND_113 F35
GND_47
GND_114 L27
GND_48
GND_115 D35
GND_49
GND_116 AL24
GND_50
GND_117 AP30
GND_51
GND_118 AH15
GND_52
GND_119 B21
GND_53
GND_120 AV3
GND_54
GND_121 AT38
GND_55
GND_122 B38
GND_56
GND_123 AA21
GND_57
GND_124 AD4
GND_58
GND_125 A37
GND_59
GND_126 AP18
GND_60
GND_127 AN4
GND_61
GND_128 B24
GND_62
GND_129 D30
GND_63
GND_130 V4
GND_64
GND_131 AA7
GND_65
GND_132 AD34
GND_66
GND_133 AK4
GND_67
GND_134 R37
AU24
AU15
AG5
AD35
AJ18
AL18
AR24
AA5
G18
B9
AU9
AM24
H24
B30
AR21
D24
AU30
AK5
N18
E24
K15
M19
AH27
E18
AA34
AK31
K11
AU21
V34
AL21
AA11
M34
B27
V28
C38
D27
R34
J35
AK34
E15
AR30
AU33
J34
AH30
J4
AU27
AU1
AG10
E9
E27
L21
AU38
H18
B15
AA4
AJ15
L18
A3
G15
AL27
AV37
D9
L4
N19
H27
FBGA
(11 OF 11)
GND_135
GND_200 E33
GND_136
GND_201 M35
GND_137
GND_202 AV2
GND_138
GND_203 AK2
GND_139
GND_204 AU6
GND_140
GND_205 F37
GND_141
GND_206 C3
GND_142
GND_207 J37
GND_143
GND_208 V35
GND_144
GND_209 G27
GND_145
GND_210 AA35
GND_146
GND_211 AU18
GND_147
GND_212 AR6
GND_148
GND_213 AV36
GND_149
GND_214 B33
GND_150
GND_215 AJ27
GND_151
GND_216 G9
GND_152
GND_217 AG35
GND_153
GND_218 AG7
GND_154
GND_219 AD8
GND_155
GND_220 AU2
GND_156
GND_221 AP9
GND_157
GND_222 AD31
GND_158
GND_223 V37
GND_159
GND_224 AA37
GND_160
GND_225 AG37
GND_161
GND_226 AL15
GND_162
GND_227 AR18
GND_163
GND_228 L14
GND_164
GND_229 K14
GND_165
GND_230 F2
GND_166
GND_231 K27
GND_167
GND_232 AL9
GND_168
GND_233 AB26
GND_169
GND_234 M29
GND_170
GND_235 G30
GND_171
GND_236 R28
GND_172
GND_237 R29
GND_173
GND_238 R31
GND_174
GND_239 U17
GND_175
GND_240 K8
GND_176
GND_241 Y21
GND_177
GND_242 V31
GND_178
GND_243 U18
GND_179
GND_244 W21
GND_180
GND_245 U19
GND_181
GND_246 W18
GND_182
GND_247 U20
GND_183
GND_248 W17
GND_184
GND_249 V21
GND_185
GND_250 AA28
GND_186
GND_251 AA29
GND_187
GND_252 N17
GND_188
GND_253 AD28
GND_189
GND_254 AD29
GND_190
GND_255 AG4
GND_191
GND_256 W19
GND_192
GND_257 W20
GND_193
GND_258 AA26
GND_194
GND_259 AB27
GND_195
GND_260 AA17
GND_196
GND_261 AA18
GND_197
GND_262 AA19
GND_198
GND_263 AA20
GND_199
GND_264 U21
D
GND
D
G32
K29
D32
L29
Y26
V26
P27
T27
J29
N27
P26
F32
A32
H29
W26
U27
G31
C32
E32
M28
H30
U26
T26
H31
B32
R26
N26
OMIT
U1400
POWER II
=PP1V05_SW_MCP_FSB
2000 mA
POWER I
22 7
OMIT
U1400
MCP89M-A01
U1400
MCP89M-A01
FBGA
(8 OF 11)
+VDD_MEM_1
+VTT_CPU_1
+VDD_MEM_2
+VTT_CPU_2
+VDD_MEM_3
+VTT_CPU_3
+VDD_MEM_4
+VTT_CPU_4
+VDD_MEM_5
+VTT_CPU_5
+VDD_MEM_6
+VTT_CPU_6
+VTT_CPU_7
+VDD_MEM_7
+VTT_CPU_8
+VDD_MEM_8
+VTT_CPU_9
+VDD_MEM_9
+VTT_CPU_10
+VDD_MEM_10
+VTT_CPU_11
+VDD_MEM_11
+VTT_CPU_12
+VDD_MEM_12
+VTT_CPU_13
+VDD_MEM_13
+VTT_CPU_14
+VDD_MEM_14
+VTT_CPU_15
+VDD_MEM_15
+VTT_CPU_16
+VDD_MEM_16
+VTT_CPU_17
+VDD_MEM_17
+VTT_CPU_18
+VDD_MEM_18
+VTT_CPU_19
+VDD_MEM_19
+VTT_CPU_20
+VDD_MEM_20
+VTT_CPU_21
+VDD_MEM_21
+VTT_CPU_22
+VDD_MEM_22
+VTT_CPU_23
+VDD_MEM_23
+VTT_CPU_24
+VDD_MEM_24
+VTT_CPU_25
+VDD_MEM_25
+VTT_CPU_26
+VDD_MEM_26
+VTT_CPU_27
+VDD_MEM_27
+VDD_MEM_28
+VDD_MEM_29
+VTT_CPU2_1
+VDD_MEM_30
+VTT_CPU2_2
+VDD_MEM_31
+VTT_CPU2_3
+VTT_CPU2_4
OMIT
U1400
GND
OMIT
C
B
7 17 22
7 22
240 mA
40 mA
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Power & Ground
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
20 OF 109
SHEET
19 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
C2300 helps reduce input rail
droop during Q2300 turn-on.
7
=PP1V5R1V35_S0_MCPDDRFET
PLACE_NEAR=Q2300.9:2 mm
Q2300
CRITICAL
C2300
1
Part
STMFS4854N
STMFS485NST1G
Type
N-Channel
Q2300
Rds(on)
10 mOhm @3.2V
Loading
4.3 A (EDP)
100UF
CRITICAL
20%
6.3V
CERM-X5R 2
1206-1
9
D
20 7
DFN
NC 8
=PP5V_S3_MCPDDRFET
NC
C
1
VCC
SLG5AP031
MCP_MEM_VDD_EN
IN
2
TDFN
EN
R2305
560K
4
GND
1%
1/16W
MF
2 402
2 3
OUT
44
C
5
NC
D 5
7
S
6
MCPMEM_GATE
(G driven to VCC)
DONE
THRM
PAD
8
TP_MCPMEM_DONE
CNFG
1
1
MCPDDRFET_SENSE
OUT
44
PP1V5R1V35_SW_MCP
VOLTAGE=1.5V
MAKE_BASE=TRUE (OR 1.35V)
4250 mA
9
3
7
MCPDDRFET_KELVIN
K1
G
CRITICAL
MCPMEM_CNFG
KELVIN 6
S
0.1UF
20%
2 10V
CERM
402
U2305
65 18
C2305
SENSE
1
4 G
14 19 22
NV Requirements:
- Min Ramp-Up Time: 20 uS (10% to 90%)
- Max Ramp-Up Time: 65 uS (ENABLE to 90%)
- FET Ron <= 3.8 mOhms
<R1>
Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)
NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.
Gated Rail Savings: 120mW
DIMM CKE Clamps
CKE must be held low to keep memory in self-refresh.
Clamps enable before MCP89 MEMVDD rail switched off.
Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.
Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.
Q2355/Q2356 chosen for low output capacitance.
CRITICAL
B
20 7
Q2355
=PP5V_S3_MCPDDRFET
NTUD3170NZXXG
SOT-963
R23501
10K
5%
1/16W
MF-LF
402 2
MEM_A_CKE<0>
BI
14 25 73
6
MEM_A_CKE<1>
BI
14 25 73
D
MEMVTT_EN_L
5
G
S
Q2350
SSM3K15FV
3
B
4
D 3
SOD-VESM-HF
D
1
18
IN
G
2
S 2
G
S
MCP_MEM_VTT_EN
1
NO STUBS on CKE signals!
CRITICAL
Q2356
NTUD3170NZXXG
SOT-963
3
MEM_B_CKE<0>
BI
14 26 73
D
A
5
SYNC_MASTER=T27_MLB
G
PAGE TITLE
S
MCP89 Memory Rail Gating
4
6
MEM_B_CKE<1>
DRAWING NUMBER
BI
14 26 73
Apple Inc.
D
051-8563
R
2
G
S
1
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
23 OF 109
SHEET
20 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
C2400 helps reduce input rail
droop during Q2400 turn-on.
PLACE_NEAR=C2400.1:1 mm
7
XW2400
SM
=PPVCORE_S0_MCPGFXFET
1
2
MCPCORES0_VSEN_P
OUT
62 79
OUT
62 79
CRITICAL
1
C2400
100UF
20%
2 6.3V
CERM-X5R
1206-1
XW2401
SM
1
2
MCPCORES0_VSEN_N
7
=PP5V_S0_MCPFSBFET
Q2400
1
5
C
1
VCC
GFXVCORE_PWR_EN
IN
2
TDFN
EN
7
S
6
MCPGFX_GATE
(G driven to VCC)
DONE
THRM
PAD
8
TP_MCPGFX_DONE
C2406
820PF
10%
50V
2 CERM
402
GND
SI4838BDY
G
SO-8
S
Si4838BDY
Type
N-Channel
Rds(on)
3.2 mOhm @2.5V
Loading
15.35 A (EDP)
C
1
2
3
PPVCORE_SW_MCP_GFX
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCORE_SW_MCP_GFX
19 23
9
CNFG
4
1
3
4
Q2400
Part
D 5
G
CRITICAL
MCPGFX_CNFG
D
0.1UF
SLG5AP033
8
CRITICAL
C2405
20%
2 10V
CERM
402
U2405
18
6 7
NV Requirements:
- Min Ramp-Up Time: 100 uS (10% to 90%)
- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)
- FET Ron <= 2.5 mOhms
<C1>
Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)
NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.
Gated Rail Savings: 860mW
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP89 GFX Core Rail Gating
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
24 OF 109
SHEET
21 OF 80
1
A
7
6
5
4
3
MCP Non-GFX Core Power
19 7
2
1
MCP 1.05V PCIe Analog Power
L2560
=PPVCORE_S0_MCP
8450 mA (0.85V)
7
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
800 mA
1
PP1V05_S0_MCP_PE_AVDD
500 mA
VOLTAGE=1.05V
2
0603
C2500 1
1
10UF
C2501
4.7UF
20%
6.3V
X5R 2
603-1
20%
4V
2 X5R
402
1
C2502
1
1UF
C2503
0.22UF
10%
10V
2 X5R
402-1
20%
6.3V
2 X5R
402
1
C2504
0.1UF
20%
10V
2 CERM
402
1
C2505
1
0.1UF
C2506
1
0.1UF
20%
10V
2 CERM
402
C2507
1
0.1UF
20%
10V
2 CERM
402
C2508
C2560 1
0.1UF
20%
10V
2 CERM
402
1
10UF
C2561
1
4.7UF
20%
6.3V
X5R 2
603-1
20%
10V
2 CERM
402
20 19 14
1
4300 mA (1.5V)
2
C2567 1
1
4.7UF
C2511
0.1UF
20%
4V
X5R 2
402
1
C2512
1
0.1UF
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C2513
20%
10V
2 CERM
402
1
C2514
0.1UF
20%
10V
2 CERM
402
1
C2515
1
0.1UF
C2516
1
0.1UF
20%
10V
2 CERM
402
C2517
1
0.1UF
20%
10V
2 CERM
402
C2518
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
1
10UF
C2519
1
1
1UF
0.1UF
20%
10V
2 CERM
402
C2568
1
4.7UF
20%
6.3V
X5R 2
603-1
19 7
=PP1V05_SW_MCP_FSB
2000 mA
=PP1V05_S0_MCP_FSB
200 mA
19 13 7
7
C2520
1
10UF
C2521
4.7UF
20%
6.3V
X5R 2
603-1
1
C2522
1
1
1UF
C2524
1UF
10%
10V
2 X5R
402-1
20%
4V
2 X5R
402
C2523
PP1V05_S0_MCP_PLL_FSBMEM
70 mA
1
1
4.7UF
10%
10V
2 X5R
402-1
1UF
10%
10V
2 X5R
402-1
20%
4V
X5R 2
402
C2571
1
0.1UF
20%
4V
2
PLACE_NEAR=R2570.1:50 mil X5R
402
C2525
D
R2570
1
GND_MCP_PLL_FSB
0.33 2
CRITICAL
MIN_LINE_WIDTH=0.25
MM
VOLTAGE=0V
C2572
1
0.1uF
20%
10V
2 CERM
402
C2573
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
5%
1/16W
MF
0402
MCP 1.05V PCIe/SATA PLL Power
PP1V05_S0_MCP_PLL_PEXSATA
L2575
MCP 0.9V AUX Core Power
19 7
150 mA
19 7
1
2
140 mA
1
C2526
1
0.1uF
C2527
C2528
0.1uF
C2575 1
20%
10V
2 CERM
402
1
1
4.7uF
20%
10V
2 CERM
402
20%
4V
C2529
402
0.1uF
20%
4V
X5R 2
402
20%
10V
2 CERM
402
1
C2576
1
0.1UF
C2578
1
0.1uF
20%
10V
2 CERM
402
2
C2577
1
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
CRITICAL
1
MCP 1.05V SATA Digital Power
200 mA
19 7
2
C2584
C2580 1
1
4.7UF
4.7UF
20%
4V
X5R 2
402
1
C2531
1UF
10%
10V
2 X5R
402-1
1
C2532
1
1UF
C2533
0.1uF
10%
10V
2 X5R
402-1
20%
10V
2 CERM
402
1
C2534
0.1uF
20%
10V
2 CERM
402
1
C2535
C2536
0.1uF
1
1
4.7UF
20%
10V
2 CERM
402
402
0.1uF
7
14 7
550 mA
1
2
C2541
4.7UF
1
1
4.7UF
20%
4V
X5R 2
402
HTOL_SENSE:YES
HTOL_SENSE:YES
0.1UF
1K
S
3
-IN
20%
10V
2 CERM
402
+IN
V+
C2545
1
0.1uF
C2546
0.1uF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
1
C2547
C2548 1
0.1uF
1
4.7UF
20%
10V
2 CERM
402
C2549
0.1uF
20%
6.3V
CERM 2
603
20%
10V
2 CERM
402
402
MF-LF
402 2
10K
U2592
5%
1/16W
MF-LF
402 2
MIC5365-2.5V
1 VIN SC70 VOUT 5
3 EN
NC 4 LDO_ADJ
LDO:ADJ
19 18 7
C2550 1
4.7uF
20%
6.3V
CERM 2
603
1
C2551
0.1uF
PP3V3_G3_RTC
? uA (G3)
5 mA (S0)
C2552
4.7UF
10K
5%
1/16W
MF-LF
402
1UF
10%
10V
2 X5R
402
1
7
C2553 1
4.7uF
20%
6.3V
CERM 2
603
1
=PP3V3_ENET_MCP_PLL_MAC
20 mA
C2554
FERR-240-OHM-200MA
1
2
0402
0.1uF
C2555 1
20%
10V
2 CERM
402
4.7UF
20%
6.3V 2
CERM
603
PP3V3_ENET_MCP_PLL_MAC
20 mA
1
6
HTOL_SENSE:YES
1
SMC_N_FOLLOW
L2590
1
2
0402
C2590
1
1
2
2
43
GND_SMC_AVSS 39
40
44
MCP 3.3V PLL Power
PP3V3_S0_MCP_PLL_HVDD 15
MIN_LINE_WIDTH=0.4 MM 50 mA
VOLTAGE=3.3V
C2591
0.1UF
20%
10V
CERM
402
MCP 3.3V DP & USB PLL Power
PP3V3_S0_MCP_PLL_DP_USB
MIN_NECK_WIDTH=0.2 MM 210 mA
GND_MCP_PLL_DP_USB
C2596
0.1UF
R2595
1
20%
10V
2 CERM
402
1
C2597
0.1uF
20%
10V
2 CERM
402
0.33 2
VOLTAGE=0V
5
QTY
DESCRIPTION
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Standard Decoupling
5%
1/16W
MF
0402
DRAWING NUMBER
REFERENCE DES
CRITICAL
BOM OPTION
353S2971
1
IC,LDO,MIC5365,2.5V,150MA,2%,SC70-5,HFLF
U2592
CRITICAL
LDO:FIXED
353S2979
1
IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF
U2592
CRITICAL
LDO:ADJ
116S0004
1
RES,0402,0,5%,1/16W
R2596
CRITICAL
HTOL_SENSE:NO
4
0.22UF
20%
6.3V
X5R
CRITICAL
Apple Inc.
PART NUMBER
C2598
2 402
0.1UF
20%
2 10V
CERM
402
SMC_NB_MISC_ISENSE
OUT
1%
1/16W
MF-LF
402
2
20%
6.3V
CERM
603
1
C2556
7
17
VOLTAGE=3.3V
1
V-
VOLTAGE=3.3V
20%
6.3V 2
PLACE_NEAR=R2595.1:50 mil CERM
603
L2555
4.53K2
4
4.7UF
2
4.7UF
300 mA
-IN
B
R2598
V+
0.1UF
PP3V3_S0_MCP_HVDD
5%
1/16W
MF-LF
402
L2595
+IN
HTOL_SENSE:YES
CRITICAL
U2594 PLACEMENT_NOTEs:
OPA330
Place close to SMC
SC70-5
(For R and C)
HTOL_SENSE:YES
C2594
20%
10V
CERM
402
220-OHM-2.2A
CRITICAL
3
100K
2
1
SMC_P_FOLLOW
R2599
C2595 1
MCP 3.3V MAC PLL Power
5
HTOL_SENSE:YES
0603
MCP 3.3V MAC/SMU Power
100K 2
VOLTAGE=3.3V
IN
CRITICAL
1
3
FERR-240-OHM-200MA
SMC_P10
HTOL_SENSE:YES
39
D
1%
1/16W
MF-LF
402
2
1
20%
6.3V
CERM 2
603
20%
10V
2 CERM
402
1
R2591
MCP 2.0V-3.3V RTC Power
=PP3V3_S5_MCP
240 mA
C2592
2
GND
2
MCP 3.3V AUX/USB Power
1
D
0.1uF
20%
10V
2 CERM
402
1
MCP_PLL_LD0_EN
8
U2593
1
6
C2544
CRITICAL
OPA330
R2590
G
1
HTOL_SENSE:YES
SOT-563-HF
NTZD3152P
Q2592
G
SC70-5
CRITICAL
HTOL_SENSE:YES
HTOL_SENSE:YES
MCPHVDD:P3V3
R2593
R2596
0
1K 2
PP3V3_S0_LDO_R
1
2
1
260 mA
CRITICAL
5%
1%
1/16W
1/16W
MCPHVDD:P2V5
VOLTAGE=3.3V
Q2592
MF-LF
MF-LF
MCPHVDD:P2V5
NTZD3152P
1 C2593
402
402
1
SOT-563-HF
R2592
1UF
LDO:ADJ
HTOL_SENSE:YES
10K
10%
CRITICAL
1
10V
5%
R2594
2
OMIT_TABLE
X5R
MCPHVDD:P2V5
1/16W
S
20%
6.3V
CERM 2
603
19 17 7
4
5
5
1
MCP 3.3V/1.5V HDA Power
18 8 =PP3V3R1V5_S0_MCP_HDA
70 mA
4.7uF
A
V-
1
7
C2543 1
2
4
1%
1/16W
MF-LF
402
C2542
B
=PP3V3_S0_MCP
250 mA
20%
10V
CERM
402
2
=PP3V3_S0_OPA333
HTOL_SENSE:YES
19 7
20%
2 10V
CERM
402
160 mA
0.1UF
SMC_N_MIRROR
R2597
20%
10V
CERM
402
0.1uF
20%
6.3V
CERM 2
603
MCP 3.3V I/O Power
1
0.1UF
20%
2 10V
CERM
402
7
19 7
C2583
C2599
=PP3V3_S0_MCP_HVDD
30 mA
C2540 1
1
0.1uF
=PP3V42_G3H_OPA330
MCP 3.3V PCIe/SATA I/O PLL Power
19 7
C2582
20%
10V
2 CERM
402
20%
4V
X5R 2
402
MCP 1.05V Memory DLL Power
1
20%
10V
2 CERM
402
4V 2
C2537
C2581
0.1UF
20%
C2530 1
C
VOLTAGE=1.05V
0603
100 mA
20%
10V
CERM
402
MCP 1.05V Core/Misc PLL Power
PP1V05_S0_MCP_PLL_CORE
16
L2580
MCP 1.05V PCIE Digital Power
0.1UF
2
220-OHM-2.2A
7
325 mA
C2579
0603
4.7UF
C
15
VOLTAGE=1.05V
220-OHM-2.2A
MCP 0.9V MAC/SMU Power
14
VOLTAGE=1.05V
2
C2570
1
20%
10V
2 CERM
402
MCP 1.05V CPU/FSB/MEM PLL Power
0603
1
C2566
0.1UF
20%
10V
2 CERM
402
0.1UF
4.7UF
1
1
0.1UF
C2569
L2570
MCP S0 FSB (VTT) Power
C2565
20%
10V
2 CERM
402
20%
4V
2 X5R
402
CRITICAL
MCP CPU FSB (VTT) Power
1
20%
10V
2 CERM
402
220-OHM-2.2A
555 mA
C2564
0.1UF
10%
10V
2 X5R
402-1
VOLTAGE=1.05V
0603
C2510 1
C2563
MCP 1.05V SATA Analog Power
PP1V05_S0_MCP_SATA_AVDD 19
300 mA
30-OHM-5A
MCP Memory Power
1
10%
10V
2 X5R
402-1
L2567
D
C2562
1UF
20%
4V
2 X5R
402
7
39
8
3
051-8563
R
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
25 OF 109
SHEET
22 OF 80
1
A
8
7
6
5
4
3
2
1
MCP GFX Core Power
21 19
=PPVCORE_SW_MCP_GFX
15350 mA (0.85V)
C2600 1
10UF
20%
6.3V
X5R 2
603-1
1
C2601
4.7UF
20%
4V
2 X5R
402
1
C2602
1UF
10%
10V
2 X5R
402-1
1
C2603
1UF
10%
10V
2 X5R
402-1
1
C2604
1
0.22UF
C2605
0.22UF
20%
6.3V
2 X5R
402
20%
6.3V
2 X5R
402
1
C2606
0.1UF
20%
10V
2 CERM
402
1
C2607
0.1UF
20%
10V
2 CERM
402
1
C2608
0.1UF
20%
10V
2 CERM
402
1
C2609
0.1UF
20%
10V
2 CERM
402
1
C2610
0.1UF
20%
10V
2 CERM
402
1
C2611
0.1UF
20%
10V
2 CERM
402
1
MCP 3.3V RGBDAC Power
C2612
0.1UF
GND_MCP_DAC_P3V3
20%
10V
2 CERM
402
1
R2670
0
5%
1/16W
MF-LF
402 2
D
PP3V3_S0_MCP_DAC
140 mA
VOLTAGE=0V
MAKE_BASE=TRUE
16
If RGBDAC is used, requires ferrite (155S0382)
plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.
D
If RGBDAC is not used, tie to GND.
MCP 3.3V/1.8V IFP Interface Power
16 7
MCP 1.05V IFP PLL Power
180 mA (1.8V LVDS)
16 7
C2620 1
4.7uF
20%
6.3V 2
CERM
603
1
60 mA
C2621
C2630 1
0.1uF
4.7uF
20%
2 10V
CERM
402
20%
4V
X5R 2
402
1
C2631
0.1uF
20%
2 10V
CERM
402
MCP 1.05V DisplayPort Power
16 7
160 mA
C2640 1
4.7UF
20%
4V
X5R 2
402
1
C2641
0.1uF
20%
10V
2 CERM
402
C
C
74 16
74 16
MCP_TMDS0_RSET
MCP_TMDS0_VPROBE
NO STUFF
C2650
0.1UF
1
20%
10V
CERM 2
402
74 16
74 16
1
R2650
1K
1%
1/16W
MF-LF
2 402
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
NO STUFF
C2655
1
0.1UF
20%
10V
CERM 2
402
NO STUFF
1
R2655
1K
1%
1/16W
MF-LF
2 402
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Graphics Support
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
26 OF 109
SHEET
23 OF 80
1
A
8
7
6
5
4
3
C2810
R2810
RTC_CLK32K_XTALOUT
0
1
NO STUFF
Y2810
5%
1/16W
MF-LF
402 2
18
OUT
5%
50V
CERM
402
CRITICAL
10M
D
2
R2881
5%
1/16W
MF-LF
402
R2811 1
LPC Reset (Unbuffered)
12pF
1
RTC_CLK32K_XTALOUT_R
2
4
IN
1
Platform Reset Connections
RTC Crystal
18
2
75 18
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
IN
33
1
32.768K
C2811
1
7X1.5X1.4-SM
2
5%
1/16W
MF-LF
402
33
1
12pF
1
RTC_CLK32K_XTALIN
5%
50V
CERM
402
MCP 25MHz Crystal
R2816
MCP_CLK25M_XTALOUT_R
2
5%
1/16W
MF-LF
402
1
CRITICAL
1M
5%
1/16W
MF-LF
402
18
OUT
Y2815
25.0000M
SM-3.2X2.5MM
NC
NC
18 15
PCIE_RESET_L
IN
1
12pF
1
MCP_CLK25M_XTALIN
2
R2893
1
1
4
3
Y2820
25.0000M
2
CRITICAL
10M
5%
1/16W
MF-LF
402 2
OUT
2
OUT
34
PCA9557D_RESET_L
OUT
28
BKLT_PLT_RST_L
OUT
71
AP_RESET_L
OUT
29
SDCARD_PLT_RST_L
OUT
30
ENET_RESET_L
OUT
31 76
LPC_CLK33M_SMC
OUT
39 75
LPC_CLK33M_LPCPLUS
OUT
41 75
R2894
SM-3.2X2.5MM
NC
NC
2
R2892
0
C2821
2
5%
1/16W
MF-LF
402
27pF
1
C
0
5%
1/16W
MF-LF
402
1
BCM5764_CLK25M_XTALI
2
5%
1/16W
MF-LF
402
R2895
2
5%
50V
CERM
402
1
R2821
1
2
0
1
BCM5764_CLK25M_XTALO_R
2
5%
1/16W
MF-LF
402
0
1
1
NO STUFF
31
0
5%
1/16W
MF-LF
402
27pF
200
BCM5764_CLK25M_XTALO
=FW_RESET_L
D
5%
1/16W
MF-LF
402
C2820
R2820
IN
39
R2891
C2816
2
Caesar II (ENET) 25MHz Crystal
31
OUT
MAKE_BASE=TRUE
5%
50V
CERM
402
C
SMC_LRESET_L
2
5%
50V
CERM
402
3
1
NO STUFF
4
MCP_CLK25M_XTALOUT
1
2
IN
2
12pF
0
1
18
41
PCIE Reset (Unbuffered)
C2815
R2815
OUT
5%
1/16W
MF-LF
402
2
LPCPLUS_RESET_L
R2883
2
5%
50V
CERM
402
R2825
75 18
LPC_CLK33M_SMC_R
IN
1
33
2
5%
1/16W
MF-LF
402
R2826
33
1
Ethernet WAKE# Isolation
B
=PP3V3_ENET_PHY
1
Q2830
SOD-VESM-HF
OUT
PCIE_WAKE_L
S
29 15 6
D
2
3
B
R2830
R2829
5%
1/16W
MF-LF
402
75 18
22
PM_CLK32K_SUSCLK_R
IN
1
ENET_WAKE_L
=ENET_WAKE_L
MAKE_BASE=TRUE
2
7 31 64
10K
1
G
SSM3K15FV
2
5%
1/16W
MF-LF
402
IN
31
PM_CLK32K_SUSCLK
2
OUT
39 75
5%
1/16W
MF-LF
402
MCP S0 PWRGD & CPU_VLD
7
=PP3V3_S5_MCPPWRGD
System Reset Circuit
1
C2850
39
IN
PM_SYSRST_L
0.1UF
A
2
XDP
20%
10V
CERM
402
R2896
12 9
5
65 39
61
IN
IN
1
ALL_SYS_PWRGD
2
VR_PWRGOOD_DELAY
U2850 Y
XDP_DBRESET_L
1
0
5%
1/16W
MF-LF
402
74LVC1G08GW
SOT353
4
MCP_PS_PWRGD
B
IN
R2899
2
1
OMIT
R2897 1
33
5%
1/16W
MF-LF
402
10K pull-up to 3.3V S0 inside MCP
PM_SYSRST_DEBOUNCE_L
2
1
OUT
18
A
PAGE TITLE
SB Misc
C2899
2
DRAWING NUMBER
10%
10V
X5R
402
Apple Inc.
8
7
6
5
4
051-8563
3
2
SIZE
D
REVISION
R
2
SILK_PART=SYS RST
PLACEMENT_NOTE=Place R2897 on BOTTOM
3
18
1UF
0
5%
1/16W
MF-LF
402
SYNC_MASTER=T27_MLB
OUT
NO STUFF
A.13.0
BRANCH
PAGE
28 OF 109
SHEET
24 OF 80
1
A
8
Page Notes
7
6
5
4
3
2
1
Power aliases required by this page:
- =PPLVDDR_S3_MEM_A
- =PPDDRVTT_S0_MEM_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
7
DDR3 Plane Stitching Caps (Space evenly across plane split)
=PPLVDDR_S3_MEM_A
BOM options provided by this page:
(NONE)
C2900
D
7
1
C2901
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
2
1
2
2
1
C2910
2
C2911
C2912
2
2
C2913
2
C2914
2
C2915
2
C2916
2
C2917
2
C2918
2
C2919
2
C2920
2
C2921
2
C2922
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
1
1
1
1
1
1
1
1
1
1
1
2
C2923
D
0.1UF
1
20%
10V
CERM
402
=PPDDRVTT_S0_MEM_A
"Factory" (top) slot
73
MEM_A_CKE<0>
IN
75
NC
73 14
79
MEM_A_BA<2>
IN
77
81
73 14
73 14
83
MEM_A_A<12>
MEM_A_A<9>
IN
IN
85
87
73 14
73 14
89
MEM_A_A<8>
MEM_A_A<5>
IN
IN
91
93
73 14
73 14
95
MEM_A_A<3>
MEM_A_A<1>
IN
IN
97
99
C
73 14
IN
73 14
IN
101
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
103
105
73 14
IN
73 14
IN
73 14
IN
73 14
IN
107
MEM_A_A<10>
MEM_A_BA<0>
109
111
113
MEM_A_WE_L
MEM_A_CAS_L
115
117
73 14
73 14
119
MEM_A_A<13>
MEM_A_CS_L<1>
IN
IN
121
123
NC
125
127
27
27
=MEM_A_DQ<32>
=MEM_A_DQ<33>
BI
BI
129
131
133
27
BI
27
BI
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
135
137
139
27
BI
27
BI
=MEM_A_DQ<34>
=MEM_A_DQ<35>
141
143
145
27
BI
=MEM_A_DQ<40>
=MEM_A_DQ<41>
27
IN
=MEM_A_DM<5>
27
BI
147
149
151
153
155
B
27
BI
27
BI
=MEM_A_DQ<42>
=MEM_A_DQ<43>
157
159
161
27
BI
27
BI
=MEM_A_DQ<48>
=MEM_A_DQ<49>
163
165
167
27
BI
27
BI
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
169
171
173
27
27
=MEM_A_DQ<50>
=MEM_A_DQ<51>
BI
BI
175
177
179
27
27
=MEM_A_DQ<56>
=MEM_A_DQ<57>
BI
BI
181
183
185
27
=MEM_A_DM<7>
IN
187
189
27
BI
27
BI
=MEM_A_DQ<58>
=MEM_A_DQ<59>
191
193
195
7
=PPSPD_S0_MEM_A
MEM_A_SA<0>
197
199
MEM_A_SA<1>
201
203
C2940
1
2.2UF
A
20%
6.3V
CERM
402-LF
2
R2940
1
1
KEY
CKE0
CKE1
VDD
CRITICAL VDD
NC
A15
J2900
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DM4
DQS4*
DQS4
VSS
DQ38
VSS
DQ39
DQ34
DQ35
VSS
VSS
DQ44
DQ45
DQ40
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
VSS
DQS6
DQ54
VSS
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT
VTT
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 2 OF 2)
73 20 14
74
MEM_A_CKE<1>
IN
PPVREF_S3_MEM_VREFDQ_A
1
14 20 73
76
3
78
MEM_A_A<15>
MEM_A_A<14>
80
IN
14 73
C2930
IN
14 73
2.2UF
20%
6.3V
CERM
402-LF
82
84
MEM_A_A<11>
MEM_A_A<7>
86
IN
14 73
IN
14 73
1
2
1
2
MEM_A_A<6>
MEM_A_A<4>
92
IN
IN
14 73
MEM_A_A<2>
MEM_A_A<0>
98
IN
IN
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
104
14 73
110
116
IN
14 73
IN
14 73
122
MEM_A_BA<1>
MEM_A_RAS_L
IN
14 73
IN
14 73
MEM_A_CS_L<0>
MEM_A_ODT<0>
IN
14 73
IN
14 73
MEM_A_ODT<1>
IN
9
27
=MEM_A_DM<0>
IN
27
BI
27
BI
=MEM_A_DQ<2>
=MEM_A_DQ<3>
27
BI
27
BI
=MEM_A_DQ<8>
=MEM_A_DQ<9>
27
BI
27
BI
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
27
BI
27
BI
=MEM_A_DQ<10>
=MEM_A_DQ<11>
27
BI
27
BI
=MEM_A_DQ<16>
=MEM_A_DQ<17>
14 73
27
BI
27
BI
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
21
23
27
29
33
35
39
41
45
47
49
NC
PPVREF_S3_MEM_VREFCA_A
28
27
27
=MEM_A_DQ<18>
=MEM_A_DQ<19>
BI
BI
51
53
55
128
=MEM_A_DQ<36>
=MEM_A_DQ<37>
BI
BI
27
C2936
27
0.1UF
20%
10V
CERM
402
134
136
17
43
126
132
15
37
124
130
11
31
118
120
BI
14 73
112
114
20%
10V
CERM
402
7
25
106
108
27
14 73
100
102
0.1UF
BI
19
94
96
27
5
13
88
90
C2931
=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DM<4>
27
IN
1
1
C2935
27
2.2UF
2
2
27
20%
6.3V
CERM
402-LF
=MEM_A_DQ<24>
=MEM_A_DQ<25>
BI
BI
57
59
61
27
=MEM_A_DM<3>
IN
63
138
65
140
67
142
=MEM_A_DQ<38>
=MEM_A_DQ<39>
BI
27
27
BI
BI
27
27
BI
=MEM_A_DQ<26>
=MEM_A_DQ<27>
146
148
=MEM_A_DQ<44>
=MEM_A_DQ<45>
BI
27
BI
27
152
2
4
6
=MEM_A_DQ<4>
=MEM_A_DQ<5>
BI
27
BI
27
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
BI
27
BI
27
=MEM_A_DQ<6>
=MEM_A_DQ<7>
BI
27
BI
27
=MEM_A_DQ<12>
=MEM_A_DQ<13>
BI
27
8
10
12
14
16
18
20
22
24
BI
27
26
28
30
=MEM_A_DM<1>
MEM_RESET_L
IN
27
IN
14 26
=MEM_A_DQ<14>
=MEM_A_DQ<15>
BI
27
BI
27
=MEM_A_DQ<20>
=MEM_A_DQ<21>
BI
27
BI
27
32
34
36
C
38
40
42
44
46
=MEM_A_DM<2>
IN
27
48
50
52
=MEM_A_DQ<22>
=MEM_A_DQ<23>
BI
27
BI
27
=MEM_A_DQ<28>
=MEM_A_DQ<29>
BI
27
BI
27
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
BI
27
BI
27
=MEM_A_DQ<30>
=MEM_A_DQ<31>
BI
27
BI
27
54
56
58
60
62
64
66
68
70
72
KEY
516-0201
150
154
69
71
144
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
DQ1
CRITICAL
VSS
DQS0*
VSS
J2900
DM0
DQS0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
VSS
DQS2
VSS
DQ22
DQ23
DQ18
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
DQS3*
VSS
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 1 OF 2)
28
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
BI
27
BI
27
=MEM_A_DQ<46>
=MEM_A_DQ<47>
BI
27
BI
27
=MEM_A_DQ<52>
=MEM_A_DQ<53>
BI
27
BI
27
=MEM_A_DM<6>
IN
=MEM_A_DQ<54>
=MEM_A_DQ<55>
BI
27
BI
27
=MEM_A_DQ<60>
=MEM_A_DQ<61>
BI
27
BI
27
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
BI
27
BI
27
=MEM_A_DQ<62>
=MEM_A_DQ<63>
BI
27
BI
27
156
158
160
B
162
164
166
168
170
27
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
OUT
BI
IN
18 26 39
42
42
204
R2941
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
516-0201
SYNC_MASTER=T27_MLB
PAGE TITLE
DDR3 SO-DIMM Connector A
DRAWING NUMBER
SPD Addr: 0xA0(Wr)/0xA1(Rd)
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
29 OF 109
SHEET
25 OF 80
1
A
8
Page Notes
7
6
5
4
3
2
1
- =PPLVDDR_S3_MEM_B
- =PPDDRVTT_S0_MEM_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
7
DDR3 Plane Stitching Caps (Space evenly across plane split)
=PPLVDDR_S3_MEM_B
(NONE)
C3100
D
7
C3101
1
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
2
1
2
2
1
C3110
2
C3111
C3112
2
2
C3113
2
C3114
2
C3115
2
C3116
2
C3117
2
C3118
2
C3119
2
C3120
2
C3121
2
C3122
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
1
1
1
1
1
1
1
1
1
1
1
2
C3123
D
0.1UF
1
20%
10V
CERM
402
=PPDDRVTT_S0_MEM_B
"Expansion" (bottom) slot
NC
73 14
79
MEM_B_BA<2>
IN
77
81
73 14
73 14
83
MEM_B_A<12>
MEM_B_A<9>
IN
IN
85
87
73 14
73 14
89
MEM_B_A<8>
MEM_B_A<5>
IN
IN
91
93
73 14
73 14
95
MEM_B_A<3>
MEM_B_A<1>
IN
IN
97
99
C
73 14
IN
73 14
IN
101
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
103
105
73 14
IN
73 14
IN
73 14
IN
73 14
IN
107
MEM_B_A<10>
MEM_B_BA<0>
109
111
113
MEM_B_WE_L
MEM_B_CAS_L
115
117
73 14
73 14
119
MEM_B_A<13>
MEM_B_CS_L<1>
IN
IN
121
123
NC
125
127
27
27
=MEM_B_DQ<32>
=MEM_B_DQ<33>
BI
BI
129
131
133
27
BI
27
BI
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
135
137
139
27
BI
27
BI
=MEM_B_DQ<34>
=MEM_B_DQ<35>
141
143
145
27
BI
=MEM_B_DQ<40>
=MEM_B_DQ<41>
27
IN
=MEM_B_DM<5>
27
BI
147
149
151
153
155
B
27
BI
27
BI
=MEM_B_DQ<42>
=MEM_B_DQ<43>
157
159
161
27
BI
27
BI
=MEM_B_DQ<48>
=MEM_B_DQ<49>
163
165
167
27
BI
27
BI
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
169
171
173
27
27
=MEM_B_DQ<50>
=MEM_B_DQ<51>
BI
BI
175
177
179
7
27
=PPSPD_S0_MEM_B
27
=MEM_B_DQ<56>
=MEM_B_DQ<57>
BI
BI
181
183
185
2
27
R3140
=MEM_B_DM<7>
IN
189
10K
1
5%
1/16W
MF-LF
402
187
27
BI
27
BI
=MEM_B_DQ<58>
=MEM_B_DQ<59>
191
193
195
MEM_B_SA<0>
197
199
MEM_B_SA<1>
201
203
1
C3140
1
A
20%
6.3V
CERM
402-LF
R3141
205
10K
2.2UF
2
207
5%
1/16W
MF-LF
2 402
209
211
KEY
CKE0
CKE1
VDD
VDD
NC
A15
CRITICAL
A14
BA2
J3100
VDD
VDD
F-RT-BGA3
A11
A12/BC*
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
S0*
WE*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
EVENT*
SA0
VDDSPD
SDA
SA1
SCL
VTT
VTT
MTG PINS
MTG PIN
MTG PIN
MTG PIN
MTG PIN
74
MEM_B_CKE<1>
IN
1
14 20 73
76
3
78
MEM_B_A<15>
MEM_B_A<14>
80
IN
14 73
C3130
IN
14 73
2.2UF
20%
6.3V
CERM
402-LF
82
84
MEM_B_A<11>
MEM_B_A<7>
86
IN
14 73
IN
14 73
1
2
1
2
MEM_B_A<6>
MEM_B_A<4>
92
IN
IN
14 73
MEM_B_A<2>
MEM_B_A<0>
98
IN
IN
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
104
14 73
110
116
IN
14 73
IN
14 73
122
MEM_B_BA<1>
MEM_B_RAS_L
IN
14 73
IN
14 73
MEM_B_CS_L<0>
MEM_B_ODT<0>
IN
14 73
IN
14 73
MEM_B_ODT<1>
IN
9
27
=MEM_B_DM<0>
IN
27
BI
27
BI
=MEM_B_DQ<2>
=MEM_B_DQ<3>
27
BI
27
BI
=MEM_B_DQ<8>
=MEM_B_DQ<9>
27
BI
27
BI
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
27
BI
27
BI
=MEM_B_DQ<10>
=MEM_B_DQ<11>
27
BI
27
BI
=MEM_B_DQ<16>
=MEM_B_DQ<17>
14 73
27
BI
27
BI
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
21
23
27
29
33
35
39
41
45
47
49
NC
PPVREF_S3_MEM_VREFCA_B
28
27
27
=MEM_B_DQ<18>
=MEM_B_DQ<19>
BI
BI
51
53
55
128
=MEM_B_DQ<36>
=MEM_B_DQ<37>
BI
BI
27
C3136
27
0.1UF
20%
10V
CERM
402
134
136
17
43
126
132
15
37
124
130
11
31
118
120
BI
14 73
112
114
20%
10V
CERM
402
7
25
106
108
27
14 73
100
102
0.1UF
BI
19
94
96
27
5
13
88
90
C3131
=MEM_B_DQ<0>
=MEM_B_DQ<1>
=MEM_B_DM<4>
27
IN
1
1
C3135
27
2.2UF
2
2
27
20%
6.3V
CERM
402-LF
=MEM_B_DQ<24>
=MEM_B_DQ<25>
BI
BI
57
59
61
27
=MEM_B_DM<3>
IN
63
138
65
140
67
142
=MEM_B_DQ<38>
=MEM_B_DQ<39>
BI
27
27
BI
BI
27
27
BI
=MEM_B_DQ<26>
=MEM_B_DQ<27>
146
148
=MEM_B_DQ<44>
=MEM_B_DQ<45>
BI
27
BI
27
154
2
4
6
=MEM_B_DQ<4>
=MEM_B_DQ<5>
BI
27
BI
27
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
BI
27
BI
27
=MEM_B_DQ<6>
=MEM_B_DQ<7>
BI
27
BI
27
=MEM_B_DQ<12>
=MEM_B_DQ<13>
BI
27
8
10
12
14
16
18
20
22
24
BI
27
26
28
30
=MEM_B_DM<1>
MEM_RESET_L
IN
27
IN
14 25
=MEM_B_DQ<14>
=MEM_B_DQ<15>
BI
27
BI
27
=MEM_B_DQ<20>
=MEM_B_DQ<21>
BI
27
BI
27
32
34
36
C
38
40
42
44
46
=MEM_B_DM<2>
IN
27
48
50
52
=MEM_B_DQ<22>
=MEM_B_DQ<23>
BI
27
BI
27
=MEM_B_DQ<28>
=MEM_B_DQ<29>
BI
27
BI
27
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
BI
27
BI
27
=MEM_B_DQ<30>
=MEM_B_DQ<31>
BI
27
BI
27
54
56
58
60
62
64
66
68
70
72
KEY
516s0706
150
152
69
71
144
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
DQ1
CRITICAL
VSS
VSS
DQS0*
J3100
DQS0
DM0
F-RT-BGA3
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ29
DQ24
VSS
DQ25
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
(1 OF 2)
75
(2 OF 2)
73
MEM_B_CKE<0>
IN
DDR3-SODIMM
73 20 14
PPVREF_S3_MEM_VREFDQ_B
DDR3-SODIMM
28
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
BI
27
BI
27
=MEM_B_DQ<46>
=MEM_B_DQ<47>
BI
27
BI
27
=MEM_B_DQ<52>
=MEM_B_DQ<53>
BI
27
BI
27
=MEM_B_DM<6>
IN
=MEM_B_DQ<54>
=MEM_B_DQ<55>
BI
27
BI
27
=MEM_B_DQ<60>
=MEM_B_DQ<61>
BI
27
BI
27
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
BI
27
BI
27
=MEM_B_DQ<62>
=MEM_B_DQ<63>
BI
27
BI
27
156
158
160
B
162
164
166
168
170
27
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
OUT
BI
IN
18 25 39
42
42
204
MTG PIN
206
MTG PIN
208
MTG PIN
210
SYNC_MASTER=T27_MLB
MTG PIN
212
PAGE TITLE
DDR3 SO-DIMM Connector B
SPD Addr: 0xA2(Wr)/0xA3(Rd)
DRAWING NUMBER
516s0706
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
31 OF 109
SHEET
26 OF 80
1
A
8
7
6
MCP CHANNEL A DQS 0 -> DIMM A DQS 0
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
D
73 14
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DM<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DM<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
C
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DM<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<14>
=MEM_A_DQ<10>
=MEM_A_DQ<13>
=MEM_A_DQ<12>
=MEM_A_DQ<15>
=MEM_A_DQ<11>
=MEM_A_DM<1>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DM<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<17>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<21>
=MEM_A_DQ<16>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DM<2>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DM<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<29>
=MEM_A_DQ<26>
=MEM_A_DQ<31>
=MEM_A_DQ<27>
=MEM_A_DQ<28>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<30>
=MEM_A_DM<3>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DM<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<38> 25
=MEM_A_DQ<39> 25
=MEM_A_DQ<35> 25
=MEM_A_DQ<32> 25
=MEM_A_DQ<36> 25
=MEM_A_DQ<34> 25
=MEM_A_DQ<33> 25
=MEM_A_DQ<37> 25
=MEM_A_DM<4>
25
=MEM_A_DQS_N<4> 25
=MEM_A_DQS_P<4> 25
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DM<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQ<47>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<46>
=MEM_A_DM<5>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DQ<51>
=MEM_A_DQ<53>
=MEM_A_DQ<50>
=MEM_A_DQ<54>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQ<55>
=MEM_A_DQ<52>
=MEM_A_DM<6>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
73 14
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_DM<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
8
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<56>
=MEM_A_DQ<61>
=MEM_A_DQ<62>
=MEM_A_DQ<59>
=MEM_A_DQ<57>
=MEM_A_DQ<60>
=MEM_A_DQ<63>
=MEM_A_DQ<58>
=MEM_A_DM<7>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
7
=MEM_B_DQ<5>
=MEM_B_DQ<4>
=MEM_B_DQ<3>
=MEM_B_DQ<7>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
=MEM_B_DQ<6>
=MEM_B_DQ<2>
=MEM_B_DM<0>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
26
26
26
26
26
26
26
26
26
26
D
26
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DM<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DM<2>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
26
26
26
26
26
26
26
26
26
26
26
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DM<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<14>
=MEM_B_DQ<11>
=MEM_B_DQ<12>
=MEM_B_DQ<8>
=MEM_B_DQ<10>
=MEM_B_DQ<15>
=MEM_B_DQ<13>
=MEM_B_DQ<9>
=MEM_B_DM<1>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
26
26
26
26
26
26
26
26
26
26
26
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DM<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<28>
=MEM_B_DQ<24>
=MEM_B_DQ<26>
=MEM_B_DQ<30>
=MEM_B_DQ<25>
=MEM_B_DQ<29>
=MEM_B_DQ<31>
=MEM_B_DQ<27>
=MEM_B_DM<3>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
C
26
26
26
26
26
26
26
26
26
26
26
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DM<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<32>
=MEM_B_DQ<37>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<36>
=MEM_B_DQ<33>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DM<4>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
26
26
26
26
26
26
26
26
26
26
26
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DM<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<42>
=MEM_B_DQ<44>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
=MEM_B_DQ<47>
=MEM_B_DQ<45>
=MEM_B_DQ<46>
=MEM_B_DQ<43>
=MEM_B_DM<5>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
26
B
26
26
26
26
26
26
26
26
26
26
MCP CHANNEL B DQS 6 -> DIMM B DQS 6
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
A
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
73 14
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DM<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
B
1
73 14
2
73 14
3
73 14
4
=MEM_A_DQ<7>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<5>
=MEM_A_DQ<1>
=MEM_A_DQ<0>
=MEM_A_DQ<6>
=MEM_A_DQ<4>
=MEM_A_DM<0>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
73 14
5
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DM<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<49>
=MEM_B_DQ<53>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<48>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DM<6>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
26
26
26
26
26
26
26
26
26
26
26
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
25
73 14
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DM<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
6
=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQ<56>
=MEM_B_DQ<60>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<61>
=MEM_B_DM<7>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
26
26
SYNC_MASTER=K18_MLB
26
PAGE TITLE
DDR3 BYTE/BIT SWAPS-K6
26
26
DRAWING NUMBER
26
Apple Inc.
26
051-8563
R
26
26
SIZE
D
REVISION
A.13.0
BRANCH
26
26
5
4
3
2
PAGE
32 OF 109
SHEET
27 OF 80
1
A
8
7
7
6
5
4
3
2
NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.
=PP3V3_S3_VREFMRGN
OMIT
VREFMRGN:YES
R3300
SHORT2
1
NONE
NONE
NONE
402
60 7
PP3V3_S3_VREFMRGN_DAC
VOLTAGE=3.3V
VREFMRGN:YES
C3300 1
1
C3301
0.1UF
20%
10V
CERM 2
402
U3300
IN
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA
9 A0
Addr=0x98(WR)/0x99(RD)
10 A1
VOUTB 2
VREFMRGN_SODIMMB_DQ
VOUTC 4
VREFMRGN_SODIMMS_CA
B1
V+
A4
V-
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN:YES
1
1
1
R3320
C2
C3
PP3V3_S3_VREFMRGN_CTRL
B1
C
Addr=0x30(WR)/0x31(RD)
42
42
IN
BI
C4
VREFMRGN_DQ_SODIMMB_BUF
VREFMRGN:YES
1
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
1
100K
5%
1/16W
MF-LF
2 402
16
GND
NC
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
(RSVD
for FBVREF)
NC
VREFMRGN_CPUGTLREF_EN
VREFMRGN:YES
C3330 1
0.1UF
20%
10V
CERM 2
402
A2
B1
V+
A3
A4
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN:YES
8
1
B4
1
5%
1/16W
MF-LF
2 402
PCA9557D_RESET_L
C2
B1
V+
C3
C
PLACE_NEAR=R3331.2:1mm
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
116S0004
2
RES,MTL FILM,0,5%,0402,SM,LF
R3321,R3323
CRITICAL
VREFMRGN:NO
116S0004
2
RES,MTL FILM,0,5%,0402,SM,LF
R3331,R3333
CRITICAL
VREFMRGN:NO
200
2
PLACE_NEAR=J3100.126:2.54mm
VREFMRGN:YES
U3330
R3334
MAX4253
UCSP
C1
C4
VREFMRGN_CA_SODIMMB_BUF
VREFMRGN:YES
1
133
PPVREF_S3_MEM_VREFCA_B
VOLTAGE=0.75V
26
2
1%
1/16W
MF-LF
402
V-
B4
VREFMRGN:YES
Required zero ohm resistors when no VREF margining circuit stuffed
1
R3335
100K
BOM OPTION
5%
1/16W
MF-LF
2 402
VREFMRGN:YES
C3340 1
0.1UF
20%
10V
CERM 2
402
C2
B1
V+
C3
VREFMRGN:YES
U3340
MAX4253
R3342
UCSP
C1
C4
VREFMRGN_MEMVREG_BUF
VREFMRGN:YES
22.6K2
Page Notes
DDRREG_FB
1
1%
1/16W
MF-LF
402
V-
B4
B
OUT
60
OUT
9 72
VREFMRGN:YES
1
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
R3340
100K
5%
1/16W
MF-LF
2 402
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
A2
B1
V+
A3
VREFMRGN:YES
U3340
MAX4253
R3344
UCSP
A1
A4
VREFMRGN_CPUGTLREF_BUF
VREFMRGN:YES
V-
B4
VREFMRGN:YES - Stuffs VREF Margining
Circuitry.
VREFMRGN:NO - Bypasses VREF Margining
Circuitry.
8
25
2
1%
1/16W
MF-LF
402
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
A
1
133
PPVREF_S3_MEM_VREFCA_A
VOLTAGE=0.75V
R3333
RST* on ’platform reset’ so that system
watchdog will disable margining.
DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:
VREFMRGN:YES
100K
MEM A VREF DQ
2
1%
1/16W
MF-LF
402
V-
R3330
A
200
R3332
UCSP
A1
VREFMRGN:YES
IN
VREFMRGN:YES
U3330
MAX4253
1
24
26
2
1%
1/16W
MF-LF
402
RESET* 15
PAD
17
THRM
133
PPVREF_S3_MEM_VREFDQ_B
VOLTAGE=0.75V
R3331
R3325
U3310
1 SCL
2 SDA
VREFMRGN:YES
VREFMRGN:YES
PCA9557
3 A0
4 A1
5 A2
2
1%
1/16W
MF-LF
402
V-
1
QFN
(OD) P0 6
P1 7
P2 9
P3 10
P4 11
P5 12
P6 13
P7 14
200
R3324
UCSP
C1
CRITICAL
VREFMRGN:YES
VCC
20%
10V
CERM 2
402
D
VREFMRGN:YES
U3320
MAX4253
B4
0.1UF
25
2
1%
1/16W
MF-LF
402
OMIT
C3310 1
PPVREF_S3_MEM_VREFDQ_A
VOLTAGE=0.75V
R3323
VREFMRGN:YES
V+
VREFMRGN:YES
VREFMRGN:YES
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!
R3310
NONE
NONE
NONE
402
133
1%
1/16W
MF-LF
402
B4
5%
1/16W
MF-LF
2 402
VOLTAGE=3.3V
2
R3322
UCSP
A1
100K
SHORT2
1
200
VREFMRGN:YES
U3320
MAX4253
VREFMRGN_MEMVREG_FBVREF
VOUTD 5
GND
3
A2
A3
VREFMRGN_SODIMMA_DQ
MSOP VOUTA 1
DAC5574
42
1
1%
1/16W
MF-LF
402
C3320 1
CRITICAL
VREFMRGN:YES
8
VDD
42
R3321
VREFMRGN:YES
0.1UF
20%
2 10V
CERM
402
20%
6.3V 2
CERM
402-LF
D
=PPVTT_S3_DDR_BUF
10mA max load
VREFMRGN:YES
2.2UF
B
1
1
267
2
1%
1/16W
MF-LF
402
CPU_GTLREF
VREFMRGN:YES
1
R3345
100K
5%
1/16W
MF-LF
2 402
MEM B VREF DQ
MEM A VREF CA
B
2
C
3
0.75V (DAC: 0x3A)
0.300V - 1.200V (+/- 450mV)
0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
7
6
MEM B VREF CA
C
4
MEM VREG
CPU GTLREF (FSB)
D
5
1.5V (DAC: 0x3A)
1.998V - 1.002V (+/- 498mV)
0.000V - 1.501V (0x00 - 0x74)
+33uA - -33uA (- = sourced)
5
4
D
7
0.7V (DAC: 0x8B)
0.200V - 1.050V (+/- 500mV)
0.000V - 1.191V (0x00 - 0x5C)
+750uA - -528uA (- = sourced)
3
SYNC_MASTER=T27_MLB
PAGE TITLE
FSB/DDR3 Vref Margining
DRAWING NUMBER
Apple Inc.
051-8563
R
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
33 OF 109
SHEET
28 OF 80
1
A
8
7
6
5
4
3
2
1
5V S3 WLAN FET
MOSFET
TPCP8102
CHANNEL
P-TYPE
RDS(ON)
26 mOhm @4.5V
LOADING
0.8 A (EDP)
D
D
CRITICAL
Q3450
TPCP8102
FERR-120-OHM-1.5A
1
20347-325E-12
2
10%
10%
0.1uF
16V X5R 402
15 74
IN
15 74
6
2
PP5V_WLAN
PCIE_AP_D2R_P
PCIE_AP_D2R_N
1
2
OUT
6 15 74
OUT
6 15 74
4
74 6
5
74 6
8
79 6
2
1
1
23V1K-SM
C3420
10UF
2
2
=PP5V_S3_WLAN
1
C3451
1
C3450
0.1UF
2
10%
16V
X5R
402
P5VWLAN_SS
2
R3450
5%
1/16W
MF-LF
2 402
33K
1
PM_WLAN_EN_L
2
IN
65
5%
1/16W
MF-LF
402
10%
16V
X5R
402
PLACEMENT_NOTE=Place close to J3401.
R3451
10K
0.033UF
20%
10V
X5R
805
7
SYM_VER-1
PLACEMENT_NOTE=Place close to Q3450.
4
3
PCIE_CLK100M_AP_P
IN
15 74
1
2
PCIE_CLK100M_AP_N
IN
15 74
PLACEMENT_NOTE=Place close to Q3450.
9
(AP_CLKREQ_Q_L)
10
20%
10V
CERM
402
1
90-OHM-100MA
DLP11S
6
79 6
0.1uF
20%
10V
CERM
402
L3401
PCIE_AP_R2D_P
PCIE_AP_R2D_N
7
C3421
1
0.1uF
AIRPORT
CRITICAL
3
PP5V_WLAN_F
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
C3422
31
29
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
16V X5R 402
C3430
F-RT-SM
1
2 3
IN
7 8
1000 mA peak
750 mA nominal max
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
0.1uF
1
J3401
2
4 G
1
D
C3431
0402-LF
5 6
S
L3404
CRITICAL
518S0610
PCIE_WAKE_L
11
OUT
6 15 24
(AP_RESET_CONN_L)
12
13
14
C
15
16
17
NC
NC
6
18
19
42
BI
IN
VOLTAGE=5V
79 6
22
79 6
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
CRITICAL
23
24
79 6
25
79 6
L3402
90-OHM
USB_BT_CONN_P
USB_BT_CONN_N
2
1
=PP5V_S3_BTCAMERA
7
FERR-120-OHM-1.5A
ALS
CAMERA
42
20
21
C
L3405
275 mA peak
206 mA nominal max
PP5V_S3_BTCAMERA_F
I2C_ALS_SDA
I2C_ALS_SCL
C3452
0402-LF
1
0.1uF
20%
10V
CERM
402
2
DLP0NS
SYM_VER-1
4
3
USB_CAMERA_P
OUT
17 75
1
2
USB_CAMERA_N
OUT
17 75
26
27
28
29
30
BLUETOOTH
CRITICAL
32
L3403
90-OHM
DLP0NS
SYM_VER-1
4
3
USB_BT_P
BI
17 75
1
2
USB_BT_N
BI
17 75
B
B
PP5V_WLAN_F
29
Supervisor & CLKREQ# Isolation
=PP3V3_S3_WLAN
100K
5%
1/16W
MF-LF
402 2
1
R3453
6
CRITICAL
U3440
1%
1/16W
MF-LF
2 402
SLG4AP016V
P3V3WLAN_VMON
DLY
AP_RESET_CONN_L
4 RESET*
AP_CLKREQ_Q_L
7 IN
THRM
PAD
GND
5
R3454
MR* 3
AP_RESET_L
IN
EN 6
OUT 8
AP_PWR_EN
AP_CLKREQ_L
OUT
(OD)
9
1
A
20%
10V
2 CERM
402
TDFN
2 SENSE
+
0.7V -
DLY = 60 ms +/- 20%
6
C3440
0.1uF
VDD
392K
WF: Need pull-up?
1
1
R34401
7
IN
24
18 65
15
97.6K
1%
1/16W
MF-LF
2 402
SYNC_MASTER=T27_MLB
PAGE TITLE
RIGHT CLUTCH CONNECTOR
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
34 OF 109
SHEET
29 OF 80
1
A
8
7
6
5
4
3
2
1
Caesar IV Support
76 31
76 31
GL137
D
7
=PP3V3_S3_CARDREADER
R3511
1
0
BYPASS=U3500.15:16:5 mm
BYPASS=U3500.26:27:5 mm
BYPASS=U3500.35:34:5 mm
PP3V3_S3_CARDREADER_DVDD
GL137
2
5%
1/16W
MF-LF
402
VOLTAGE=3.3V
GL137
C3500 1
1
10UF
2
20%
1
0.1UF
20%
2 10V
CERM
402
603
L3500
GL137
C3502
1
0.1UF
6.3V 2
X5R
GL137
GL137
C3501
76 31
76 31
C3503
0.1UF
20%
2 10V
CERM
402
76 31
20%
2 10V
CERM
402
SDCONN_DATA<0>
R3550
0
BI
SDCONN_DATA<1>
R3551
0
SDCONN_DATA<2>
R3552
0
BI
SDCONN_DATA<3>
BI
SDCONN_DATA<4..7>
IN
SDCONN_CLK
76 31
OUT
SDCONN_CMD
31
OUT
SDCONN_WP
OUT
SDCONN_CD
76 31
1
BYPASS=U3500.6:5:5 mm
BYPASS=U3500.11:12:5 mm
PP3V3_S3_CARDREADER_AVDD
GL137
VOLTAGE=3.3V
GL137
C3514 1
1
10UF
GL137
C3504
603
20%
2 10V
CERM
402
R3554
VOLTAGE=1.8V
75 17
75 17
BI
BI
GL137_GPIO1
GL137_GPIO2
NO STUFF
R35091
10K
5%
1/16W
MF-LF
402 2
GL137
NC
1
R3510
LQFP
48 GPIO1
47 GPIO2
46 GPIO3
CRITICAL
GL137
19
5%
1/16W
MF-LF
2 402
R3503
1M
1
2
5%
1/16W
MF-LF
402
GL137
R3502
715
CRITICAL
GL137
0
1%
1/16W
MF-LF
402 2
Y3500
12.000M-100PPM
1
GL137
1
R35061
GL137_CLK12M_X1
GL137_CLK12M_X2
13 X1
14 X2
GL137_RREF
10 RREF
GL137_TESTMOD
17 TESTMOD
GL137_RESET_L
NO STUFF
18 EXTRSTZ* (IPU)
(IPD)
0.1UF
402
33PF
1
2
5%
33PF
1
30 76
1/16W MF-LF 402
SD_D<2>
30 76
5%
1/16W MF-LF 402
2
SD_D<3>
30 76
0
1
D
30 76
MAKE_BASE=TRUE
2
5%
5%
SD_CLK
30 76
SD_CMD
30 76
1/16W MF-LF 402
0 BCM57765
1
2
1/16W MF-LF402
MAKE_BASE=TRUE
SD_CD_L
30
30
R3555
2.2UF
20%
6.3V
CERM1 2
603
1
PP3V3_SW_SD_PWR
R3505
39K
0.1UF
MAX CURRENT = 800 MA
5%
1/16W
MF-LF
2 402
20%
10V
2 CERM
402
(IPU) XD_CDZ
XD_CE
(IPD) XD_WEZ
(IPD) XD_RBZ
(IPD) XD_WPZ
1
6
76 30
76 30
76 30
76 30
76 30
76 30
76 30
76 30
SD_CLK
SD_CMD
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
5
2
7
8
9
1
10
11
12
13
14
SD_CLK_R
30
SD_WP
30
SD_CD_L
15
16
4
GL137_PDMOD
NO STUFF
NC
31
NC
42
NC
44
NC
45
NC
J3500
3
76 30
40
43
37
29
28
30
32
38
3
41
2
23
CRITICAL
SD-CARD-K19-K24
F-RT-TH
76 30
D0
D1
D2
D3
D4
D5
D6
D7
2
VOLTAGE=3.3V
MAKE_BASE=TRUE
1
C3505
0
5%
1/10W
MF-LF
603
1
R3513
10K
5%
1/16W
MF-LF
402 2
18
GL137
19
R3504
1
0
17
20
2
5%
1/16W
MF-LF
402
C
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
NO STUFF
1
C3515
10PF
516-0225
5%
2 50V
CERM
402-1
NC
NC
PDMOD: POWER DOWN MODES
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE
B
GL137
Q3500
2
12
GL137
C3512
5
9
GL137
5%
BCM57765
=PP3V3_S0_SDCONN
5%
1/16W
MF-LF
402 2
(IPD) SD_WP
(IPD) SD_CMD
(IPU) PDMOD
(IPU) SD_CDZ
GND
8X4.5X1.4-SM
C3511
10K
(IPU) MS_INS 24
(IPD) MS_BS 33
20%
10V
CERM 2
2
R35121
CLK 39 76
C3513 1
5%
1/16W
MF-LF
2 402
36
25
15
26
35
GL137A
SK
NC
20 CS
NC
21 DO
NC
22 DI (IPD)
NC
10K
NO STUFF
B
U3500
7 DM
8 DP
USB_SDCARD_N
USB_SDCARD_P
34
5%
1/16W
MF-LF
2 402
16
27
10K
GL137
PMOSO
R3508
VDD5V
1
DVDD
4
VDD18O
NO STUFF
10K
C3507 1
NC
402
5%
1/16W
MF-LF
402 2
1/16W MF-LF 402
SD_WP
PP1V8_S3_CARDREADER
20%
R35071
1
1
10V
CERM 2
GL137
5%
2
BCM57765
30 76
SD_D<1>
MAKE_BASE=TRUE
7
0.1UF
C
1
SD_D<0>
1/16W MF-LF 402
BCM57765
6
AVDD 11
GL137
C3506 1
BCM57765
0
5%
2
SD_D<4..7>
R3556
Keep this net short!
BYPASS=U3500.4:5:5 mm
2
1
MAKE_BASE=TRUE
0.1UF
20%
2 10V
CERM
402
1
BCM57765
C3508
1
0.1UF
20%
6.3V 2
X5R
31
R3553
BI
0.22UH
0805-1
BCM57765
BI
D 3
SSM6N15FEAPE
5%
SOT563
50V
50V
CERM
402
CERM
402
5
18
IN
G
SDCARD_RESET
S 4
SDCARD_PLT_RST
GL137
Q3500
D 6
SSM6N15FEAPE
SOT563
2
24
IN
G
S 1
SDCARD_PLT_RST_L
A
SYNC_MASTER=T27_MLB
PAGE TITLE
SecureDigital Card Reader
DRAWING NUMBER
Apple Inc.
051-8563
R
ADDED SERIES RESISTOR TO SD_CMD, MAX CURRENT NUMBER CHANGED TO 800MA
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
35 OF 109
SHEET
30 OF 80
1
A
8
7
6
5
4
3
2
1
BCM57765 SR pins are internal 1.2V switching regulator.
If unused: Okay to float all 4 pins. (Broadcom not so sure now)
If used:
VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
64 31
R3915
=PP3V3_ENET_PHY
86mA (1000base-T, Caesar II)
64 31 24 7
0
1
CRITICAL
2
31
BCM57765
SM
D
31 64
CRITICAL
L3920
31 64
BCM57765_VDDO_PIN20
PP1V2_ENET_PHY_AVDDL
VOLTAGE=3.3V
R3900
FERR-600-OHM-0.5A
1
2 31 PP3V3_ENET_PHY_XTALVDDH
VOLTAGE=3.3V
BCM57765_SR_LX
BCM57765_SR_VFB
FERR-600-OHM-0.5A
5%
1/16W
MF-LF
402
L3900
TP_BCM57765_SR_VDDP
BCM57765_SR_VDD
64
BCM57765
1
0
2
5%
1/16W
MF-LF
402
C3900 1
0.1UF
31
C3921 1
VOLTAGE=1.2V
1
10%
16V
X7R-CERM 2
402
10%
2 6.3V
X5R-CERM
603
0.1UF
BCM57765_XTALVDDH
VOLTAGE=3.3V
L3905
C3926 1
1
0.1UF
C3905
10%
16V
X7R-CERM 2
402
10%
2 16V
X7R-CERM
402
CRITICAL
L3910
1
1
R3910
10%
2 16V
X7R-CERM
402
5%
1/16W
MF-LF
402 2
L3930
1
C3911
C3931
0.1UF
0.1UF
C3936 1
1
10%
16V
X7R-CERM 2
402
10%
2 6.3V
X5R
805
PCIE_ENET_D2R_P
C3951
2
74
10%
16V
X5R
402
C3955
74
74
0.1uF
74 15
74 15
IN
IN
PCIE_ENET_R2D_C_P
1
10%
16V
X5R
402
PCIE_ENET_R2D_C_N
C3956
0.1uF
1
R3943
OUT
74
2
BCM57765
31 24
=ENET_WAKE_L
(See note)
0
1
2
2
10%
16V
X5R
402
(IPD)
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
27 PCIE_TXD_N
28 PCIE_TXD_P
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
33 PCIE_RXD_P
34 PCIE_RXD_N
IN
IN
ENET_RESET_L
11 PERST*
(IPD)
OUT
ENET_CLKREQ_L
12 CLKREQ*
(OD)
74 15
76 24
BCM57765_WAKE_L
ENET_LOW_PWR
IN
Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
31
31
31
31
31
24
IN
24
OUT
0.1UF
VDDC 35
VDDC 61
29
32
39
45
51
WAKE* 13
U3900
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
BCM5764M
QFN-8X8
VERSION 2
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
IN
18 8
58 SMB_DATA
31 PCIE_REFCLK_P
30 PCIE_REFCLK_N
74 15
15
5%
1/16W
MF-LF
402
WAKE#
B
BCM57765_VMAIN_PRSNT
31
0.1uF
1
VDDIO 16
CRITICAL
OMIT
GPHY_PLLVDDL 36
5%
1/16W
MF-LF
2 402
(IPD)
OUT
10%
16V
X5R
402
AVDDL
PCIE_PLLVDDL
1K
2
VDDC 14
AVDDH
REGCTL12 15
10%
2 16V
X7R-CERM
402
0.1UF
7
20
56
62
1
10%
6.3V
X5R-CERM 2
603
4.7UF
3 LINKLED* (OD)
4 LOW_PWR
6 VDDC
10 UART_MODE
BCM5764_SCLK
BCM5764_MISO
BCM5764_MOSI
BCM5764_CS_L
66
64
65
63
TP_BCM5764_SPD100LED_L
TP_BCM5764_TRAFFICLED_L
2 SPD100LED*
67 TRAFFICLED*
BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
18 XTALI
19 XTALO
BCM5764_RDAC
38 RDAC
SCLK
SI
SO
CS*
C
NC
VOLTAGE=3.3V
BCM57765_MEDIA_SENSE
1.24K
BCM57765_CR_CMD
1
0.1UF
VCC
10%
2 16V
X7R-CERM
402
U3990
AT45DB011D
BCM5764_SCLK
2
SCK
31
BCM5764_CS_L
4
CS*
5
WP*
3
RESET*
OMIT
BCM5764_MOSI
SI 1
SO 8
BCM57765
1
R3990
GND
4.7K
5%
1/16W
MF-LF
2 402
7
A
31
BCM5764_MISO
BCM5764M
7
C3970 1
BI
32 76
4.7UF
BI
32 76
BI
32 76
BCM57765
R3972
C3972
0.1UF
10%
2 16V
X7R-CERM
402
BCM57765
0
1
ENET_ENERGY_DET
2
BCM57765
0
1
2
0
1
2
5%
1/16W MF-LF 402
SDCONN_CD
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
OUT
17 31
IN
30
30 76
25
24
23
22
52
53
54
55
SDCONN_DATA<0>
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>
SDCONN_DATA<5>
SDCONN_DATA<6>
SDCONN_DATA<7>
SMB_CLK
ENERGY_DET
DC5
SPD1000LED*
59
60
57
68
76
76
31
76
31
76
31
BCM57765_CR_DATA<4>
BCM57765_CR_DATA<5>
BCM57765_CR_DATA<6>
BCM57765_CR_DATA<7>
BCM57765_CE_L_MS_INS_L
BCM57765_CR_LED
R3975
R3976
R3977
R3978
0
0
0
0
1
1
1
1
2
2
2
2
BCM57765
31
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
BI
30 76
BI
30 76
BI
30 76
BI
30 76
BI
30 76
BI
30 76
BI
30 76
BI
30 76
B
All resistors above BOMOPTIONed BCM57765
31
SDCONN_WP
IN 30
BCM57765 supports both active-levels for WP.
TP_BCM57765_XD_DET
BCM5764M Support
13-WAKE*
64 31
BCM57765_SR_VFB
53-VMAIN_PRSNT
76 31
BCM57765_CR_DATA<5>
31
31
76 31
64 31
31
76 31
31
64 31
31
All parts below BOMOPTIONed BCM5764M
BCM5764M
R3980 0 1
2
BCM57765_CE_L_MS_INS_L
BCM57765_VMAIN_PRSNT
BCM57765_CR_DATA<6>
BCM57765_SR_LX
BCM57765_VDDO_PIN20
BCM57765_CR_DATA<7>
BCM57765_XTALVDDH
BCM57765_SR_VDD
BCM57765_SMB_CLK
R3981
R3982
R3983
R3984
R3985
R3986
R3987
R3988
R3989
R3998
R3999
5%
0
1
2
1K
1
2
4.7K
4.7K
1K
0
1
1
1
1
2
2
2
2
0
1
2
0
0
0
0
1
1
1
1
2
2
2
2
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
L3999
FERR-600-OHM-0.5A
2
BCM57765_CR_CMD PLACE_NEAR=U3900.26:2 mm 1
76 31
SM CRITICAL
Keep net short, BCM5764M
BCM5764M
1 C3998
with no stubs.
C3999 1
0.1UF
4.7UF
26-PCIE_VDDL
5
10%
16V
2 X7R-CERM
402
DC4
DC3
DC2
DC1
NC
VMAIN_PRSNT
VAUX_PRSNT
VDDC
R3997
6
BCM57765
1
30 76
1
5%
1/16W
MF-LF
2 402
C3971
0.1UF
10%
6.3V
X5R-CERM 2
603
31
4.7K
BCM57765
1
IN
NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures BCM57765 for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: BCM5764M requires SI pull-down instead of SO.
8
32 76
OUT
55-VDDC
17-VDDC
14-VDDC
06-VDDC
31
32 76
BI
SDCONN_CLK
20-XTALVDDH
SOIC-8S1
BI
SDCONN_CMD
59-SMB_CLK
58-SMB_DATA
54-VAUX_PRSNT
16-VDDIO
C3990
32 76
PLACE_NEAR=L3999.1:1 mm
BCM5764M pin-function
BCM57765_CR_LED
31
60-ENERGY_DET
1%
1/16W
MF-LF
2 402
32 76
BI
21
76 31
69
R3965
ROM contains MAC address, PCIe config
info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
=PP3V3_ENET_PHY
6
64 31 24 7
1
32 76
BI
R3973
R3974
BCM57765_SD_DETECT
THRM_PAD
PHY Non-Volatile Memory
CR_BUS_PWR is not for SD Card power,
just decoupling for BCM57765 CR I/Os.
BI
DC0
PCIE_VDDL 26
(IPD-BCM5764M)
10UF
PP3V3R1V8_SW_SD_VIO
NC 1
(IPD)
BCM57765_SMB_CLK
BCM57765_SMB_DATA
C3935
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
40
41
44
43
46
47
50
49
GPIO_0/SERIAL_DO 5
GPIO_1/SERIAL_DI 8
GPIO_2 9
(IPU)
74 15
1
4.7UF
C3916
C3915 1
VDDC 17
5%
1/16W
MF-LF
2 402
VDDIO
XTALVDDH
VDDIO
VDDIO
4.7K
R3942
0.1uF
OUT
SM
C3930
10%
2 6.3V
X5R-CERM
603
BIASVDDH 37
R3941
5%
1/16W
MF-LF
402 2
C3950
VOLTAGE=1.2V
1
10%
16V
X7R-CERM 2
402
BCM57765
PCIE_ENET_D2R_N
1
10%
2 16V
X7R-CERM
402
1
74 15
4.7UF
10%
2 6.3V
X5R-CERM
603
CRITICAL
42
48
1
4.7K
31 7
SM
C3925
BCM57765
R39401
=PP3V3_S0_ENETPHY
C3910
0.1UF
4.7K
BCM57765
VOLTAGE=1.2V
1
FERR-600-OHM-0.5A
1
2
PP1V2_ENET_PHY_GPHYPLL
FERR-600-OHM-0.5A
1
2
PP3V3_ENET_PHY_AVDDH
VOLTAGE=3.3V
D
FERR-600-OHM-0.5A
1
2
PP1V2_ENET_PHY_PCIEPLL
0.1UF
C
4.7UF
L3925
VOLTAGE=3.3V
SM
=PP1V2_ENET_PHY 7 31
396mA (1000base-T, Caesar II)
CRITICAL
FERR-600-OHM-0.5A
1
2
PP3V3_ENET_PHY_BIASVDDH
SM
2
SM
C3920
10%
16V
X7R-CERM 2
402
CRITICAL
1
10%
16V
X7R-CERM 2
402
PLACE_NEAR=U3900.26:1 mm
4
10%
2 6.3V
X5R-CERM
603
3
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
ENET_ENERGY_DET
=ENET_WAKE_L (See note)
24 31
=PP3V3_S0_ENETPHY
7 31
=PP3V3_ENET_PHY
7 24 31 64
402
402
402
402
402
402
402
402
17 31
PP3V3_ENET_PHY_XTALVDDH
31
=PP1V2_ENET_PHY
7 31
SYNC_MASTER=T27_MLB
PAGE TITLE
Ethernet PHY (Caesar II/IV)
DRAWING NUMBER
Apple Inc.
051-8563
R
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
39 OF 109
SHEET
31 OF 80
1
A
8
7
6
5
4
3
2
1
Page Notes
(NONE)
(NONE)
(NONE)
D
D
ENETCONN_CTAP
PLACE_NEAR=T4000.3:2.54 mm
1
C4000
1
0.1UF
10%
16V
X5R
402
2
C4002
1
0.1UF
2
C4004
1
C4006
0.1UF
10%
16V
X5R
402
2
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
2
CRITICAL
T4000
SM
12 79
ENETCONN_P<0>
2
11 79
ENETCONN_N<0>
3
10
ENET_CTAP0
76 31
BI
ENET_MDI_P<0>
1
76 31
BI
ENET_MDI_N<0>
CRITICAL
J4000
RJ45-M97-3
TX
F-RT-TH
9
TLA-6T213HF
C
4
9
C
10
ENET_CTAP1
76 31
BI
ENET_MDI_N<1>
5
8
79
ENETCONN_N<1>
76 31
BI
ENET_MDI_P<1>
6
7
79
ENETCONN_P<1>
1
2
3
RX
4
5
CRITICAL
6
7
T4001
76 31
76 31
BI
ENET_MDI_N<2>
1
BI
ENET_MDI_P<2>
2
SM
12 79
ENETCONN_N<2>
8
11 79
ENETCONN_P<2>
11
10
ENET_CTAP2
12
3
514-0636
TX
TLA-6T213HF
76 31
76 31
ENET_CTAP3
4
9
BI
ENET_MDI_N<3>
5
8
79
ENETCONN_N<3>
BI
ENET_MDI_P<3>
6
7
79
ENETCONN_P<3>
RX
7
4
9
2 10
1
6
5
7
4
9
2 10
1
NC
IO
NC
IO
NC
IO
NC
IO
5
NC
IO
NC
IO
NC
IO
NC
IO
6
SLP2510P8
ENET_ESD
CRITICAL
D4001
RCLAMP0524P
GND
D4000
RCLAMP0524P
GND
B
Transformers should be
mirrored on opposite
sides of the board
D4000.1:
D4000.5:
PLACE_NEAR=T4000.6:4 mm
D4001.1:
D4001.5:
R4000 1
R4001 1
75
75
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
R4002
1
75
2
2
R4003
75
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
CRITICAL
C4008
1000PF
ENET_BOB_SMITH_CAP
1
B
2
10%
2KV
CERM
1206
SLP2510P8
3
ENET_ESD
CRITICAL
3
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Ethernet Connector
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
40 OF 109
SHEET
32 OF 80
1
A
8
7
6
5
4
3
2
1
=PP3V3_FW_FWPHY
7 mA I/O
1
C4120
C4121
1
C4122
1
C4123
1
C4124
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
2
2
7 33 34 35
138 mA
2
2
1
2
L4130
120-OHM-0.3A-EMI
D
114 mA FireWire PHY
C4130
PP3V3_FW_FWPHY_VDDA
1
C4131
1UF
1UF
1UF
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
C4132
10%
6.3V
CERM
402
1
2
1
VOLTAGE=3.3V
1
2
L4110
34 7
L4135
120-OHM-0.3A-EMI
=PP1V0_FW_FWPHY
1
135 mA
120-OHM-0.3A-EMI
2
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
VOLTAGE=1.0V
0402-LF
1
C4110
1
1UF
2
10%
6.3V
CERM
402
2
17 mA PCIe SerDes
C4111
C4135
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
110 mA Digital Core
1
2
C4100
1
C4101
1
PP3V3_FW_FWPHY_VP25
C4136
1
VOLTAGE=3.3V
1
2
0402-LF
1UF
10%
6.3V
CERM
402
2
2
0 mA VReg PWR
1
C4102
1
C4103
1
C4104
1
C4105
1
C4106
C4141
1UF
1UF
1UF
1UF
1UF
1UF
1UF
0.1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
20%
10V
CERM
402
2
D
2
0402-LF
2
2
2
2
2
1
1
2
2
C4140
1UF
10%
6.3V
CERM
402
C
C
K12
L9
L6
L10
D8
L5
D6
D5
A12
M2
L11
L3
J1
G12
F1
C12
C1
N11
N3
M12
L1
K2
H12
H2
E10
E2
C13
B12
B1
A1
PLACEMENT_NOTE=Place C4170 close to U1400
C4170
1
0.1UF
VDD10
R4162 1
C4162
J2
L13
D12
D1
A10
H13
K13
2
J12
NC
0.33UF
2
N13
TP_FW643_OCR10_CTL
1
470K
5%
1/16W
MF-LF
402
M13
J13
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-1
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
CHIP RESET
NT-5 PERST*
M1
15 74
IN
15 74
10%
2
0.1UF
X5R
16V
X5R
16V
X5R
IN
15 74
OUT
15 74
OUT
15 74
402
402
PCIE_FW_D2R_P
10%
15 74
402
=PP3V3_FW_FWPHY
7 33 34 35
FW643_LDO
C2
D13
E1
D2
L2
R4165
=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L
G2
G1
OUT
34
OUT
34
1
H1
F2
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
1
1
R4166
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
R4164
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
B
NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
1394B physical plug detect.
WITH PLUG DETECT:
- Gate CLKREQ# based on PHY power
- TP (or NC) PME#
WITHOUT PLUG DETECT:
- Alias both signals to drop = prefix
IN
1
34
R4163
10K
OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS
10%
6.3V
CERM-X5R
402
N2
IN
16V
IN
402
PCIE_FW_D2R_N
2
1
X5R
MISCELLANEOUS
2
VREG_VSS
K6
5%
50V
CERM
402
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
FW643_TRST_L
K10
3
2
1%
1/16W
MF-LF
402
G13
NAND_TREE
REXT
XO
XI NT-9
L7
4
191
1%
1/16W
MF-LF
402 2
2
R4170
L8
F13
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
N1
NT-16 (IPD) SCIFCLK
NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
K9
1
2.94K
22PF
1
R4161 1
K1
R0
TPCPS
K8
SM-3.2X2.5MM
B10
1
0.1UF
5%
1/16W
MF-LF
2 402
K7
Y4150
24.576MHZ
2
NC
NC
B11
C4175
16V
PCIE_FW_R2D_C_P
10%
10K
K5
1
C4151
2
1%
1/16W
MF-LF
402
A2
TPBIAS0
TPBIAS1
TPBIAS2
K4
CRITICAL
5%
50V
CERM
402
C3
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
412
1
BI
B7
N9
N10
NT-19 (IPU) TRST*
POWER MANAGEMENT
NT-12 (IPD)
NT-13
J10
FW_CLK24P576M_XO
35
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
74
M3
FIXME!!! - TYPO IN SYMBOL REGCTL
J9
2
BI
FW643_R0
FW643_TPCPS
R4150
22PF
1
BI
A4
J5
C4150
2
35
35 34
B4
J4
1%
1/16W
MF-LF
402
BI
H10
200K
BI
35
H8
R4160 1
B
35
74
N6
NT-21 (IPU) TCK
NT-20 (IPU) TDI
(IPU) TDO
NT-18 (IPU) TMS
(OD)
NT-10 (IPD)
H7
=PPVP_FW_PHY_CPS
A6
B2
35
BI
B6
74
N5
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
1394 PHY
H6
77 35
BI
A9
H4
77 35
B9
G10
BI
G8
BI
G7
BI
77 35
A3
G6
35
77 35
B3
74
N7
M4
TEST CONTROLLER
G4
BI
A5
F10
35
B5
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
F8
BI
A8
F7
BI
77 35
B8
F6
77 35
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
REFCLKN
REFCLKP
PCI EXPRESS PHY
F4
BI
N8
2
BGA
E9
BI
77 35
E13
E5
77 35
E12
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
10%
1
C4176
E4
IN
C4171
VREG_PWR
FW643E
DS0 (IPD) NT-2
DS1 (IPD) NT-3
DS2 (IPD) NT-4
D10
IN
35
F12
VP25
U4100
D9
35
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
A11
ATBUSB
ATBUSH
ATBUSN
D7
IN
A13
D4
35
B13
VP
5%
1/16W
MF-LF
402
L12
NC
NC
NC
VDDH
VDD33
OMIT
CRITICAL
PCIE_FW_R2D_C_N
2
A
SYNC_MASTER=T27_MLB
PAGE TITLE
FireWire LLC/PHY (FW643E)
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
41 OF 109
SHEET
33 OF 80
1
A
8
7
6
5
4
Page Notes
D
Power aliases required
- =PPBUS_S5_FWPWRSW
- =PPBUS_FW_FET
- =PP3V3_FW_P3V3FWFET
- =PP3V3_FW_FET
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
- =PP3V3_S0_FWPWRCTL
- =PP1V05_S0_FWPWRCTL
- =PP1V05_FW_P1V0FWFET
- =PP1V0_FW_FET_R
- =PP1V0_FW_FWPHY
3
2
1
FireWire Port Power Switch
by this page:
(FW VP FET Input)
(FW VP FET Output)
(3.3V FET Input)
(3.3V FET Output)
(PHY 3.3V Power)
CRITICAL
Q4260
CRITICAL
FDC638P_G
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
5
4
2
(5KPD Bias Rail)
(1.0V FET Input)
(1.0V FET Output)
(PHY 1.0V)
R4262
R4260
10K
FWPORT_FASTOFF_L_DIV
- =FW_CLKREQ_L
- =FW_PME_L
(SYM-VER2)
SOT-363
S
5
1
=PPBUS_FW_FET
7
2
CRS08-1.5A-30V
10%
25V 2
X5R
402
D
3
Q4262
1
R4263
D
10
(NONE)
MINISMDC110H24 VOLTAGE=12.6V
FWPORT_PWREN_L_DIV
BSS8402DW
G
PPBUS_FW_FWPWRSW_D
2
0.1UF
5%
1/16W
MF-LF
2 402
4
1
C4260 1
300K
5%
1/16W
MF-LF
402 2
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6V
1
1
1
D4260
SM
1.1A-24V
6
=PPBUS_S5_FWPWRSW
7
CRITICAL
F4260
SM
5%
1/16W
MF-LF
402 2
3
FWPORT_FASTOFF_L
1
R4261
5%
1/16W
MF-LF
2 402
D
Q4262
=PP3V3_S0_FWLATEVG
BSS8402DW
G
7
(SYM-VER1)
D 3
1
Q4261
0.1UF
0.1UF
SOD-VESM-HF
1
C4290 1
NO STUFF
C4261 1
SSM3K15FV
35
=PP3V3_S0_FWPWRCTL
FWPORT_PWREN_L
SOT-363
S
G
S 2
10%
25V 2
X5R
402
24
IN
SLG4AP016V
5%
1/16W
MF-LF
1 402
34 15
15
IN
OUT
7 33
2
+ SENSE
- 0.7V
10K
DLY
FW_RESET_R_L
RESET* 4
3 MR*
FW_PWR_EN
FW_CLKREQ_L
6 EN
8 OUT
FW_RESET_L
OUT
DLY = 60 ms +/- 20%
=FW_CLKREQ_L
FW_CLKREQ_PHY_L
IN 7
(OD)
Pull-up provided by another page.
GND
5
=PP1V05_S0_FWPWRCTL
=PP1V0_FW_FWPHY
TDFN
R4283
C
7
R4290
5%
1/16W
MF-LF
2 402
U4290
2
FWPORT_PWR_EN
IN
1
100K
VDD
10%
25V 2
X5R
402
=FW_RESET_L
CRITICAL
1
2
IN
C
33
33
MAKE_BASE=TRUE
THRM
PAD
9
35 7
Supervisor & CLKREQ# Isolation
470K
6
FireWire Port 5K Pull-Down Detect
R42751
All FireWire devices require 5K pull-down on TPB pair.
Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.
1K
5%
1/16W
MF-LF
402 2
3.3V FW Switch
FW_PWR_EN_L
U4201
330K
Q4275
SOT-563
IN
FW_PWR_EN
2 G
5%
1/16W
MF-LF
402 2
3
S
Q4270
1
BC847CDXV6TXG
SOT563
6
3
FWDET_MIRROR
5
FW_P1_TPBIAS_R
C4270
2
4
U4201 & U4202
GND
10%
6.3V
CERM 2
402
0.1UF
BC847CDXV6TXG
SOT563
10%
16V
X5R 2
402
R42721
R42731
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
1.0V FW Switch
7
TPS22924
=PP1V05_FW_P1V0FWFET
A2
B2
CSP
VIN
VOUT
TPS22924C
Type
Load Switch
R(on)
18 mOhm Typ
50 mOhm Max
1UF
35 33 7
10%
6.3V 2
CERM
402
C2 ON
1
R4202
GND
0.549
1%
1/16W
MF
2 402
R4276
FW_PME_L OUT 15
Pull-up provided on another page.
3 CRITICAL
100K
5%
1/16W
MF-LF
2 402
FW_WAKE
NO STUFF
A
6
D
FW643_WAKE_L
C4276
Q4276
5
DMB53D0UV
SOT-563
1
4
SYNC_MASTER=T27_MLB
0.1UF
10%
16V
X5R 2
402
PAGE TITLE
FireWire Port & PHY Power
DRAWING NUMBER
2 G
MAKE_BASE=TRUE
Apple Inc.
CRITICAL
Q4276
S
051-8563
DMB53D0UV
SOT-563
TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.
5
4
3
2
SIZE
D
REVISION
R
1
6
7
1) 5K Pull-down Detect when FW_PWR_EN is low.
2) FW643 WAKE# (PME#) when PHY is powered.
1
10K
=FW_PME_L
LSI FireWire PHY requires 1.0V.
To avoid an extra power supply,
1.05V is used with a series R
to reduce voltage.
Dual-purpose output:
5%
1/16W
MF-LF
402 2
IN
VOLTAGE=1.05V
=PP1V0_FW_FET_R
=PP3V3_FW_FWPHY
R42771
33
B
Max Output: 2A
PP1V05_FW_FET
A1
B1
CRITICAL
C4202 1
FW_P1_TPBIAS
FireWire PHY WAKE# Support
7
Part
U4202
12K
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
8
=PP3V3_FW_FET
7
EDP = 0.14A (85C)
A1
B1
C2 ON
1UF
SOT-563
1
VOUT
CRITICAL
C4201 1
DMB53D0UV
FWDET_EMIT
1K
IN
CRITICAL
Q4270
CRITICAL
CSP
VIN
1
4
35 33
A2
B2
Q4275
5
TPS22924
=PP3V3_FW_P3V3FWFET
MAKE_BASE=TRUE
FW_5KPD_DET_RC
CRITICAL
B
7
FW_5KPD_DET_L
56K
5%
1/16W
MF-LF
2 402
DMB53D0UV
34 15
R42711
R4270
C1
D
1
CRITICAL
C1
6
A.13.0
BRANCH
PAGE
42 OF 109
SHEET
34 OF 80
1
A
8
Page Notes
7
6
4
FW643 TPCPS Leakage Protection
- =PPVP_FW_PORT1
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS
(To PHY)
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
3
2
Unused FireWire Ports
FW643 has internal leakage path from TPCPS pin to VDD33.
FET blocks current to TPCPS until VDD33 is powered.
Configures PHY for:
- Port "1" Bilingual (1394B)
BSS8402DW
SOT-363
470K
5%
1/16W
MF-LF
402
D
=PPVP_FW_PHY_CPS
G
R4311
1
VOLTAGE=12.6V
MAKE_BASE=TRUE
3
From Port
33
IN
FW_P0_TPBIAS
77 33
BI
FW_P0_TPA_P
BI
FW_P0_TPA_N
77 33
PPVP_FW_CPS
S
=PPVP_FW_PHY_CPS_FET
4
7
Q4300
(SYM-VER2)
35 34 33 7
- =FW_PHY_DS0
- =FW_PHY_DS1
- =FW_PHY_DS2
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
R4382 1
NO_TEST=TRUE
NC_FW0_TPAP
NO_TEST=TRUE
1%
1/16W
MF-LF
402
NC_FW0_TPAN
MAKE_BASE=TRUE
BI
FW_P0_TPB_P
BI
FW_P0_TPB_N
IN
FW_P2_TPBIAS
BI
FW_P2_TPA_P
BI
FW_P2_TPA_N
BI
FW_P2_TPB_P
1
10K
MAKE_BASE=TRUE
77 33
NO_TEST=TRUE
10K
2
2
NC_FW0_TPBP
MAKE_BASE=TRUE
R4380
1%
1/16W
MF-LF
402
FWPHY_DS0
NO_TEST=TRUE
=FW_PHY_DS0
MAKE_BASE=TRUE
NC_FW0_TPBN
MAKE_BASE=TRUE
FWPHY_DS1
NO_TEST=TRUE
=FW_PHY_DS1
MAKE_BASE=TRUE
To FW643
33
33
2
(NONE)
=PP3V3_FW_FWPHY
NC_FW0_TPBIAS
MAKE_BASE=TRUE
77 33
33
1
FireWire PHY Config Straps
Disabled per LSI instructions
(All unused port signals TP/NC)
5
D
5
CPS_EN_L_DIV
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
33
R4312
33
1
330K
5%
1/16W
MF-LF
402
33
BI
NC_FW2_TPBIAS
MAKE_BASE=TRUE
FWPHY_DS2
NO_TEST=TRUE
NC_FW2_TPAP
MAKE_BASE=TRUE
=FW_PHY_DS2
MAKE_BASE=TRUE
1
NO_TEST=TRUE
NC_FW2_TPAN
D
OUT
33
OUT
33
OUT
33
R4381
10K
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBP
MAKE_BASE=TRUE
NO_TEST=TRUE
2
1%
1/16W
MF-LF
402
NC_FW2_TPBN
FW_P2_TPB_N
MAKE_BASE=TRUE
NO_TEST=TRUE
2
CPS_EN_L
6
D
35 34 33 7
Q4300
=PP3V3_FW_FWPHY
2
BSS8402DW
G
SOT-363
S
(SYM-VER1)
1
C
C
CRITICAL
Cable Power
Termination
Place close to FireWire PHY
7
L4310
=PPVP_FW_PORT1
1
34 33
IN
Note: Trace PPVP_FW_PORT1 must handle up to 5A
FERR-250-OHM
2
FW_P1_TPBIAS
SM
1
PPVP_FW_PORT1_F
VOLTAGE=33V
C4314
0.01UF
1
C4360
2
0.33UF
2
10%
6.3V
CERM-X5R
402
10%
50V
X7R
402
(FW_PORT1_TPA_P)
(FW_PORT1_TPA_N)
"Snapback" & "Late VG" Protection
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
B
BI
FW_P1_TPA_N
1%
1/16W
MF-LF
402 2
C4350
J4310
1
0.1UF
10%
16V
X5R
402
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
1394B-M97
F-RT-TH
VCC
U4350
2
TPD4S1394
3
TP_FWLATEVG_VCLMP
LLP
VCLMP
MAKE_BASE=TRUE
77 33
BI
FW_P1_TPB_P
FW_PORT1_TPB_P
77 33
BI
FW_P1_TPB_N
FW_PORT1_TPB_N
34
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
R4362
R4350
MAKE_BASE=TRUE
FWPWR_EN
1
GND
100K
5%
1/16W
MF-LF
402
56.2
1%
1/16W
MF-LF
2 402
4
FWPORT_PWR_EN
CRITICAL
R4363
56.2
OUT
1%
1/16W
MF-LF
402 2
D1+
8
D1-
7
D2+
6
D2-
5
2
NC
220pF
2
5%
25V
CERM
402
VP
4
OUTPUT
TPB+
B
VP
SC/NC
NC
VG
TPA-
VG
5
TPATPA<R>
TPA+
TPA(R)
INPUT
TPA+
10
PLACE_NOTE=J4310.5:2 mm
10%
50V
X7R
603-1
1
4.99K
1%
1/16W
MF-LF
402
TPB<R>
7
3
(FW_PORT1_TPA_P)
C4319
R4364
TPB-
TPB+
6
11
1
(FW_PORT1_TPB_P)
(FW_PORT1_TPB_N)
1
13
2
514S0605
R4319
1M
2
5%
1/16W
MF-LF
2 402
CHASSIS
GND
12
0.1uF
C4364
TPB(R)
9
(GND)
(FW_PORT1_TPA_N)
FW_PORT1_AREF
FW_PORT1_TPB_C
1
TPB-
8
(PINS 5/6 AND 7/8 ARE
SWAPPED FOR BETTER ROUTING)
2
1
(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)
2
77 33
FW_P1_TPA_P
CRITICAL
56.2
1%
1/16W
MF-LF
2 402
BI
BILINGUAL
R4361
56.2
77 33
PORT 1
=PP3V3_S0_FWLATEVG
1
R4360
34 7
AREF needs to be isolated from all
local grounds per 1394b spec
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
A
SYNC_MASTER=T27_MLB
PAGE TITLE
FireWire Connector
DRAWING NUMBER
Apple Inc.
051-8563
R
CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
43 OF 109
SHEET
35 OF 80
1
A
8
7
6
5
ODD Power Control
Q4590
=PP5V_SW_ODD_FET
=PP5V_S0_ODD
=PP3V3_S0_ODD
Q4596
1
5%
1/16W
MF-LF
402
D 6
D
1
8
2
R4597
=PP5V_SW_ODD
10%
16V
CERM
402
2
2
1
4
3
74 6
36 7
6
5
74 6
8
7
10
9
79 6
12
11
79 6
14
13
16
15
2 G
=PP3V3_S0_ODD
D 3
3
74
39 6
1
2
74
0.01UF
OUT
SMC_ODD_DETECT
R45112
C
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
1
SATA 3GB/S REDRIVER, LOW POWER
U4510
CRITICAL
RDRV:8511
PIN
9
8
20
10
FERR-70-OHM-4A
PP5V_S0_HDD_FLT
1
VOLTAGE=5V
=PP5V_S0_HDD
C4501
2
J4501
C4502
42
20%
1 10V
CERM
402
=I2C_HDD_A_SCL
0
2
IN
=I2C_HDD_A_SDA
17 74
5%
1/16W
MF-LF
2 402
R4515
2
R4517
10K
5%
1/16W
MF-LF
1 402
5%
1/16W
MF-LF
1 402
SATARDRVR_A_B_SD
SATARDRVR_A_I2C_ADDR
SATARDRVR_A_A_SD
SATARDRVR_A_I2C_EN
(IPD)
(IPD)
(IPU)
(IPU)
5%
1/16W
MF-LF
402 1
10K
RDRV:8515 NO STUFF
2
NO STUFF
2
R4516
10K
5%
1/16W
MF-LF
1 402
36
36
36
36
NO STUFF
C
2
R4518
10K
5%
1/16W
MF-LF
1 402
19
1
A_EQ
(IPD)
SATARDRVR_A_I2C_SCL
36
SATARDRVR_A_I2C_SDA
36
RDRV:8515
R4514
0
2
18
1
B_EQ
(IPD)
5%
1/16W
MF-LF
402
SATA Redriver
54722-0224
F-ST-SM
1
10%
50V
CERM 2
402
NC
R4532
38 6
6
IR_RX_OUT
PP5V_S3_IR_R
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
74 6
74 6
74 6
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
RDRV:8511&RDRV:8515
(All 4 C’s)
SATA_HDD_R2D_N
C4516 1
SATA_HDD_R2D_P
0.01UF
17
18
C4515 1
19
20
0.01UF
21
22
2
C4532
0.1UF
10%
16V
2 X7R-CERM
402
R4510
10K
10% 16V
CERM 402
79
79
516S0687
79
FL4501
90-OHM-100MA
79
DLP11S
SYM_VER-1
3
4
79
SATA_HDD_R2D_UF_N
C4511 1
0.01UF
2
1
79
SATA_HDD_R2D_UF_P
SATA HDD Port
C4510 1
0.01UF
10%
6.3V
CERM-X5R 2
402
1
C4519
0.01UF
10%
2 16V
CERM
402
5%
1/16W
MF-LF
1 402
2
CRITICAL
RDRV:8511&RDRV:8515
(C4514,
C4514 1
C4519 & R4510) 1UF
2
10% 16V
CERM 402
VOLTAGE=5V
1
=PP1V5_S0_SATARDRVR
PLACE_NEAR=U4510.16:3mm
74 6
2
TQFN
A_INP
A_INN
SATA_HDD_R2D_RDRV_OUT_N
SATA_HDD_R2D_RDRV_OUT_P
SATARDRVR_A_EN
16
IN
4
5
B_OUTN
B_OUTP
36
36
79
SATA_HDD_D2R_RDRV_OUT_P
PS8515A-A2
1
2
36
10% 16V
CERM 402
CRITICAL
7
17
SATARDRVR_A_I2C_EN
SATARDRVR_A_I2C_ADDR
10
8
SATARDRVR_A_I2C_SCL
SATARDRVR_A_I2C_SDA
19
18
B_INN 12
B_INP 11
C4518 1
2
79
SATA_HDD_D2R_RDRV_OUT_N
C4517 1
SATA_HDD_R2D_RDRV_IN_N
79
SATA_HDD_R2D_RDRV_IN_P
SATA_HDD_D2R_UF_P
4
3
SATA_HDD_D2R_P
OUT
17 74
79
SATA_HDD_D2R_UF_N
1
2
SATA_HDD_D2R_N
OUT
17 74
B
10% 16V
CERM 402
C4513 1
2
SATA_HDD_R2D_C_N
IN
17 74
SATA_HDD_R2D_C_P
IN
17 74
10% 16V
CERM 402
0.01UF
A_SD 20
B_SD 9
SYM_VER-1
79
2
0.01UF
79
90-OHM-100MA
DLP11S
10% 16V
CERM 402
0.01UF
A_OUTP 15
A_OUTN 14
EN (IPU)
AUTOPW_EN
(IPD)
I2C_EN (IPD)
I2C_ADDR
(IPD)
SCL_CTL
SDA_CTL
C4512 1
2
10%
0.01UF
CERM
SATARDRVR_A_A_SD 36
SATARDRVR_A_B_SD 36
PS8515A:
x_SD pins are outputs (Signal Detect)
16V
402
GND THRM
PAD
3
13
NOTE: Internal pulls are ~150K
FL4502
(All 4 C’s)
RDRV:8511&RDRV:8515
VDD
SATA_HDD_D2R_RDRV_IN_P
SATA_HDD_D2R_RDRV_IN_N
36
7 36
RDRV:IN_DEVEL
CRITICAL
U4510
SATARDRVR_A_AUTOPWR_EN
2
10% 16V
CERM 402
6
16
C4531
1
21
SYS_LED_ANODE_R
0.001UF
5%
1/16W
MF-LF
402
IN
5%
1/16W
MF-LF
402
0.1UF
20%
1 10V
CERM
402
CRITICAL
42
PLACE_NEAR=L4500.2:2mm
0603
2
7
2
0.1UF
1
OUT
R4513
L4500
10
17 74
RDRV:8515
CRITICAL
=PP5V_S3_IR 2
SATA_ODD_D2R_N
10K
10K
R4520
5%
1/16W
MF-LF
402 2
PLACE_NEAR=J4501.9:3mm
38 7
OUT
10% 16V CERM 402
5%
1/16W
MF-LF
402 1
R45122
1
10K
NAME
A_PRE
B_PRE
A_BST#
B_BST#
NO STUFF
R45191
B
2
10K
RDRV:8515
NO STUFF
1
SATA_ODD_D2R_P
PS8511A / PS8515A Straps
BOMOPTIONs:
- RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!)
- RDRV:8515 stuffs PS8515A & associated parts
- RDRV:NO stuffs bypass path (neither IC or associated parts stuffed)
5%
1/16W
MF-LF
402
2
=PP1V5_S0_SATARDRVR
NO STUFF
338S0769
SYS_LED_ANODE 2
17 74
10% 16V CERM 402
C4526 1
SATA_ODD_D2R_C_N
PLACE_NEAR=J4500.9:4MM
S 4
PART NUMBER
40
C4525 1
SATA_ODD_D2R_C_P
PS8511A:
4.7
IN
D
ODD_PWR_EN_L
R4531
SATA_ODD_R2D_C_P
FL4525
516S0616
Indicates disc presence
6
2
10% 16V CERM 402
0.01UF
SYM_VER-1
36 7
5 G
17 74
5%
1/16W
MF-LF
402 2
SOT563
IN
C4521 1
SATA_ODD_R2D_UF_P
IN
90-OHM-100MA
DLP11S
33K
SSM6N15FEAPE
18
79
SATA_ODD_R2D_C_N
10% 16V CERM 402
0.01UF
R45901
S 1
ODD_PWR_EN
Q4596
1
2
CRITICAL
SATA_ODD_D2R_UF_N
SATA_ODD_D2R_UF_P
100K
5%
1/16W
MF-LF
402 2
C4520 1
SATA_ODD_R2D_UF_N
PLACE_NEAR=J4500.5:4mm
SATA_ODD_R2D_P
SATA_ODD_R2D_N
4
SOT563
79
0.01UF
4
ODD_PWR_SS
4
54722-0164
F-ST-SM
0.01UF
100K 2
SSM6N15FEAPE
1
SYM_VER-1
3
J4500
C4596
R4595
ODD_PWR_EN_LS5V_L
CRITICAL
FL4520
CRITICAL
G
10%
10V
CERM 2
402
5%
1/16W
MF-LF
402 2
36 7
1
90-OHM-100MA
DLP11S
5
0.068UF
100K
6 7
R4596
S
3
1 2
C4595 1
1
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.
2
SATA ODD Port
8
J4500 connection separated to
support debug sense resistor.
Alias together if no sense R.
8
23V1K-SM
D
3
CRITICAL
TPCP8102
7
4
338S0778 (PS8515A)
Addr: 0x94(Wr)/0x95(Rd)
(All 4 C’s)
RDRV:NO
C4580 1
0.01UF
C4581 1
0.01UF
A
C4585 1
0.01UF
C4586 1
0.01UF
Redriver Bypass Path
2
79
(ALL 4 R’S & C’S)
RDRV:NO
R4580 1
SATA_HDD_R2D_NORDRV_P
10% 16V
CERM 402
0
2
79
R4581 1
SATA_HDD_R2D_NORDRV_N
10% 16V
CERM 402
0
2
79
R4585 1
SATA_HDD_D2R_NORDRV_N
34
10% 16V
CERM 402
2
79
R4586 1
SATA_HDD_D2R_NORDRV_P
10% 16V
CERM 402
34
C4587 1
U4510 ADD NO STUFF IN PRODUCTION!!!!
47PF
C4588 1
47PF
J5401 PINOUTS ARE DIFFERENT FOR K6, DO NOT SYNC THIS PAGE FROM T27 DIRECTLY
8
7
6
5
4
3
2
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
SYNC_MASTER=T27_MLB
PAGE TITLE
SATA Connectors
2
1%
1/16W
MF-LF
402
DRAWING NUMBER
Apple Inc.
051-8563
R
2
5%
50V
CERM 402
2
D
A.13.0
2
5%
50V
CERM 402
SIZE
REVISION
BRANCH
PAGE
45 OF 109
SHEET
36 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
Port Power Switch
CRITICAL
7
17
OUT
65
IN
17
OUT
L4605
TPS2064DGN
2 IN
8
3
5
4
USB_EXTA_OC_L
=USB_PWR_EN
USB_EXTB_OC_L
7
OUT1
MSOP
OUT2
PP5V_S3_RTUSB_A_ILIM
6
CRITICAL
C4695
1
1
10UF
C4690 1
10UF
20%
6.3V 2
X5R
603
1
1
9
C4691
0.01uF
VOLTAGE=5V
20%
2 6.3V
POLY-TANT
CASE-B2-SM
0.1UF
C4617 1
20%
10V
2 CERM
402
10UF
20%
6.3V 2
X5R
603
C
1
79 75
USB
CRITICAL
F-RT-TH-M97-4
5
6
L4600
90-OHM-100MA
DLP11S
SYM_VER-1
CRITICAL
CRITICAL
J4600
20%
16V
CERM 2
402
100UF
20%
6.3V 2
X5R
603
GND TPAD
C4696
VOLTAGE=5V
PLACE_NEAR=J4600.1:3 mm
0603
C4605 1
PP5V_S3_RTUSB_B_ILIM
OC2*
EN2
FERR-220-OHM-2.5A
1
2
PP5V_S3_RTUSB_A_F
VOLTAGE=5V
OC1*
EN1
Left USB Port A
CRITICAL
Q4690
=PP5V_S3_RTUSB
USB_EXTA_MUXED_N
4
USB_EXTA_MUXED_P
1
PLACE_NEAR=D4600.2:2 mm
3 79 USB_LT1_N
1
2
3
4
C4616
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
79 75
2
79
USB_LT1_P
IO
NC
IO
NC
4 3 5 2
VBUS 6
GND 1
USB/SMC Debug Mux
7
RCLAMP0502N
SLP1210N6
SMC_DEBUG:YES
R4650
0.1UF
IN
41 40 39
OUT
9
20%
10V
CERM 2
402
CRITICAL
SMC_DEBUG:YES
VCC
5 M+
4 M-
10K
U4650
L4615
FERR-220-OHM-2.5A
1
2
PP5V_S3_RTUSB_B_F
(USB_EXTA_MUXED_N)
(USB_EXTA_MUXED_P)
Y- 2
BI
75 17
BI
USB_EXTA_P
USB_EXTA_N
7 D+
6 D8
0.01uF
TQFN
20%
16V
CERM 2
402
SEL 10
OE*
3
GND
SIGNAL_MODEL=USB_MUX
B
VOLTAGE=5V
PLACE_NEAR=J4610.1:3 mm
0603
C4615 1
PI3USB102ZLE
75 17
Left USB Port B
CRITICAL
5%
1/16W
MF-LF
2 402
Y+ 1
USB_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB
IN
39
J4610
USB
F-RT-TH-M97-4
5
6
L4610
DLP11S
SYM_VER-1
75 17
BI
USB_EXTB_N
4
3
79
USB_LT2_N
75 17
BI
USB_EXTB_P
1
2
79
USB_LT2_P
1
2
3
4
R4651
0
CRITICAL
CRITICAL
90-OHM-100MA
SMC_DEBUG:NO
1
D4600.4 PLACE_NEAR=J4600.3:2 mm
CRITICAL
1
C4650 1
SMC_RX_L
SMC_TX_L
514-0638
D4600
=PP3V42_G3H_SMCUSBMUX
41 40 39
C
7
8
4 3 5 2
IO
NC
IO
NC
5%
1/16W
MF-LF
402
B
7
8
2
VBUS 6
514-0638
GND 1
SMC_DEBUG:NO
R4652
1
0
D4610
2
RCLAMP0502N
5%
1/16W
MF-LF
402
SLP1210N6
CRITICAL
A
SYNC_MASTER=T27_MLB
PAGE TITLE
External USB Connectors
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
46 OF 109
SHEET
37 OF 80
1
A
8
7
6
5
4
3
2
1
IR Support
36 7
=PP5V_S3_IR
D
C4801 1
14
D
10%
16V
X7R-CERM 2
402
VCC
0.1UF
U4800
CY7C63803-LQXC
QFN
BI
75 17
BI
USB_IR_P
USB_IR_N
IR_VREF_FILTER
1
NC
NC
NC
NC
C4803
1UF
10%
2 10V
X5R
402-1
P1.0/D+
P1.1/DP1.2/VREG
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
8
9
10
20
21 NC
22
23
24
P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
R4800
IR_RX_OUT_RC
NC
1
C4804 1
0.001UF
THRML
PAD
100
2
IR_RX_OUT
IN
6 36
5%
1/16W
MF-LF
402
10%
50V
CERM 2
402
OMIT
CRITICAL
VSS
25
NC
NC
NC
NC
NC
NC
NC
NC
12
13
15
16
17
18
19
11
75 17
C
C
T57 Connector
T57
BS4890
STDOFF-3.6OD3.4H-SM
1
860-1287
CRITICAL
T57
7
=PP3V3_S3_T57
J4890
AXK720427G
F-ST-SM
21
T57
C4895
1
0.01uF
20%
16V
CERM 2
402
B
NC
75 6
BI
75 6
BI
IN
USB_T57_P
USB_T57_N
NC
NC_T57_RESET
6 VBUS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC_T57_PWR_EN
IN
=PP5V_S3_T57
NC
NC
B
7
T57
1
C4896
0.01uF
NC
NC
20%
16V
2 CERM
402
22
NC
IO
NC
IO
2 5 3 4
1
516S0824
1 GND
T57
D4890
RCLAMP0502N
SLP1210N6
BS4891
STDOFF-3.6OD3.4H-SM
1
860-1287
T57
CRITICAL
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Internal USB Support
DRAWING NUMBER
Apple Inc.
051-8563
R
K6 NOTES : D4890 CONNECTION IS DIFFERENT,CANNOT DIRECTLY SYNC FROM T27
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
48 OF 109
SHEET
38 OF 80
1
A
8
7
6
5
4
3
2
1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
40
40 7
PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC
D
D
C4902 1
22UF
65
IN
18
OUT
61
OUT
18
OUT
NC
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
40
40
44
SMC_P20
NC
NC
NC
SMC_P24
NC
SMC_BMON_MUX_SEL
NC
C
75 41 18
BI
75 41 18
BI
75 41 18
BI
75 41 18
BI
75 41 18
IN
24
IN
75 24
41 18
IN
BI
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
42
BI
OUT
40
OUT
48
OUT
41 40 39 37
OUT
41 40 39 37
42
IN
BI
NC
(DEBUG_SW_1)
(DEBUG_SW_2)
(OC)
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
SMC_PA0
SMC_PA1
PM_SYSRST_L
USB_DEBUGPRT_EN_L
MEM_EVENT_L
SMC_PA5
40
SYS_ONEWIRE
PM_BATLOW_L
P20
P21
P22
P23
P24
P25
P26
P27
NC
NC
(OC)
D4
A5
B4
A1
C2
B2
C1
C3
P40
P41
P42
P43
P44
P45
P46
P47
G2
F3
E4
P50
P51
P52
OUT
37
OUT
BI
B
57
BI
18
OUT
18
OUT
36 6
IN
(EXCARD_OC_L)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
B8
C9
B9
A10
C10
B10
C11
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_PB3 (See below)
40
SMC_PB4
40
SMC_PB6
SMC_GFX_OVERTEMP_L
40
40
IN
46
OUT
40
OUT
40
OUT
40
OUT
46
IN
40
IN
40
IN
40
IN
49
IN
49
IN
49
IN
40
IN
40
IN
40
IN
40
IN
40
IN
OMIT
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
L13
K12
K11
J12
K13
J10
J11
H12
P70
P71
P72
P73
P74
P75
P76
P77
N10
M11
L10
N11
N12
M13
N13
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P80
P81
P82
P83
P84
P85
P86
A7
B6
C7
D5
A6
B5
C6
SMC_WAKE_SCI_L
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
(OC) SMB_MGMT_CLK
P90
P91
P92
P93
P94
P95
P96
P97
J4
G3
H2
G1
H4
G4
F4
F1
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
(OC) SMB_0_S0_DATA
NC
NC
NC
NC
NC
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
G11
G13
F12
H13
G10
G12
H11
J13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
SMC_ADC14
SMC_ADC15
M10
N9
K10
L8
M9
N8
K9
L7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
H8S2117
LGA-HF
(2 OF 3)
OMIT
OUT
0.1UF
20%
2 10V
CERM
402
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
0.1UF
20%
2 10V
CERM
402
BYPASS=U4900.E1:D2:5 mm
1
OUT
C4906
6 65
R4999 PLACE_NEAR=C4920.1:2
SMC_ADAPTER_EN
1
IN
40
IN
6 40 57
IN
44
IN
43
IN
40
IN
40
IN
44
IN
43
IN
44
IN
22
OUT
18
4.7
5%
1/16W
MF-LF
402
18 40 65
2
SMC_VCL
mm
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
C4920 1
C4907 1
0.47UF
0.1UF
20%
10V
CERM 2
402
BYPASS=U4900.M12:L9:5 mm
VCC
AVCC
VCL AVREF
U4900
H8S2117
10%
6.3V
CERM-X5R 2
402
R49091
NC
E5
MD1
MD2
D1
H1
NMI
E3
ETRST
H3
AVSS
L9
10K
NC
5%
1/16W
MF-LF
402 2
LGA-HF
(3 OF 3)
OMIT
58 41 40
IN
40
40
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
A2
XTAL
EXTAL
1
R4901
10K
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
41
SMC_NMI
IN
41
IN
41
SMC_KBC_MDE
NC
U4900
NC
(EXCARD_CP)
LGA-HF
(1 OF 3)
N3
N1
M3
M2
N2
L1
K3
L2
40
24
H8S2117
P30
P31
P32
P33
P34
P35
P36
P37
40
26 25 18
A
D13
E11
D12
F11
E13
E12
F13
E10
A9
D9
C8
B7
A8
D8
D7
D6
40
49
P10
P11
P12
P13
P14
P15
P16
P17
C4905
E1
IN
B12
A13
A12
B13
D11
C13
C12
D10
0.1UF
20%
2 10V
CERM
402
1
L11
65 24
U4900
SMC_P10
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
22
C4904
B1
M1
H10
OUT
0.1UF
20%
2 10V
CERM
402
1
M12
40
C4903
18 41
IN
18 41
OUT
37 39 40 41
IN
37 39 40 41
BI
K1
J3
K2
J1
K4
K5
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_G3H_POWERON_L
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
M6
L5
M5
N4
L4
M4
SMC_SYS_LED
SMC_LID
40 47
IN
8 40 57
IN
40
IN
6 18 65 69
IN
6 18 40 65
IN
18
IN
24 75
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
N7
K8
K7
K6
N6
M7
L6
PH0
PH1
PH2
PH3
PH4
PH5
E2
F2
J2
A4
B3
C4
SMC_MCP_SAFE_MODE
R4902
VSS
10K
5%
1/16W
MF-LF
2 402
XW4900
SM
2
NOTE: P94 and P95 are shorted in some platforms.
1
R4998
10K
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
1
GND_SMC_AVSS
40
IN
40 41
IN
40 41
OUT
40 41
IN
40 41
IN
40
OUT
40
22 40 43 44
B
40 47 57
OUT
40
IN
40
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PH3
42
BI
42
BI
42
BI
42
BI
42
BI
SMC_PROCHOT
SMC_THRMTRIP
NC
BI
40
NC
NC
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
42
OUT
40
OUT
40
H8S2117-R:
(SMC_PECI)
(SMC_PECI_VREF)
(SMC_PECI_VSTP)
SYNC_MASTER=T27_MLB
PAGE TITLE
SMC
DRAWING NUMBER
Apple Inc.
SMC_PB3:
7
051-8563
6
5
4
3
2
SIZE
D
REVISION
R
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay.
8
C
1
42
IN
IN
SMC_TRST_L
NO STUFF
1
42
IN
BI
PE0
PE1
PE2
PE3
PE4
PF0
NC
NC
OUT
D2
L3
F10
B11
C5
(EXCARD_PWR_EN)
20%
6.3V 2
CERM
805
1
A.13.0
BRANCH
PAGE
49 OF 109
SHEET
39 OF 80
1
A
8
7
6
5
4
3
SMC Reset "Button", Supervisor & AVREF Supply
40 7
0.47UF
D
47 40 39
DFN
6 MR1* (IPU)
SN0903048
7 MR2* (IPU)
SMC_MANUAL_RST_L
OMIT
R5001
C5001
0
4 DELAY
OUT
PP3V3_S5_AVREF_SMC
0.01UF
5%
1/10W
MF-LF
2 603
SMC_RESET_L
RESET* 5
39
D
DMB53D0UV
SOT-563
1
1
10uF
C5026
0.01UF
72 61 13 9
BI
R5062
CPU_PROCHOT_L
1
10%
16V
2 CERM
402
20%
6.3V 2
X5R
603
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side
VOLTAGE=0V
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
3.3K 2
2 G
3
CPU_PROCHOT_L_R
Q5060
5
5%
1/16W
MF-LF
402
6 D
DMB53D0UV
SOT-563
S
4
1
Q5059
SSM6N15FEAPE
22 39 43 44
SOT563
1 S
NOTE: Internal pull-ups are to VIN, not V+.
G 2
SMC_PROCHOT
Debug Power "Buttons"
SMC_ONOFF_L
OMIT
OMIT
R50141
72 13 9
OUT
3 D
39 40 47
5%
1/10W
MF-LF
2 603
4 S
G 5
SMC_THRMTRIP
SILK_PART=PWR_BTN
PLACEMENT_NOTEs:
C
SMC Pull-ups
40 39 7
0
43
SMC_XTAL_R
2
44
2
44
5%
1/16W
MF-LF
402
CRITICAL
Y5010
5%
50V
CERM
402
1
20.00MHZ
5X3.2-SM
2
44
SMC_CPU_FSB_ISENSE
SMC_ADC14
OUT
39
SMC_ADC15
OUT
39
SMC_NB_CORE_ISENSE
OUT
39
OUT
39
MAKE_BASE=TRUE
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
SMC_MCP_DDR_ISENSE
SMC_NB_DDR_ISENSE
MAKE_BASE=TRUE
39
47 40 39
57 47 39
41 39 37
41 39 37
SMC_PA0
SMC_PA1
SMC_PB4
SMC_PB6
R5091
R5092
R5088
R5095
100K
100K
10K
10K
1
1
1
1
2
2
2
2
SMC_ONOFF_L
SMC_LID
SMC_TX_L
SMC_RX_L
R5070
R5071
R5073
R5074
10K
100K
10K
100K
1
1
1
1
2
2
2
2
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMS_INT_L
SMC_GFX_OVERTEMP_L
SMC_G3H_POWERON_L
R5077
R5078
R5079
R5080
R5081
R5087
R5093
R5094
R5098
10K
10K
10K
10K
10K
470K
10K
10K
100K
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
OUT
C5011
TP_SMC_GPU_1V8_ISENSE
15pF
1
SMC_EXTAL
SMC_MCP_VSENSE
MAKE_BASE=TRUE
15pF
1
39
39
C5010
R5010
39
SMC Aliases
SMC Crystal Circuit
39
SMC_ANALOG_ID
OUT
39
SMC_GPU_ISENSE
OUT
39
MAKE_BASE=TRUE
2
TP_SMC_GPU_ISENSE
MAKE_BASE=TRUE
5%
50V
CERM
402
TP_SMC_GPU_VSENSE
IN
40
SMC_GFX_THROTTLE_L
41 39
41 39
OUT
39
SMC_IG_THROTTLE_L
OUT
18
MAKE_BASE=TRUE
SMS_INT_L
41 39
SMC_GPU_VSENSE
MAKE_BASE=TRUE
39
41 39
57 39 6
57 39 8
40
=SMC_SMS_INT
39
MAKE_BASE=TRUE
B
18
IN
39
MCP_WAKE_REQ_L
SMC_G3H_POWERON_L
MAKE_BASE=TRUE
40 39
OUT
39 40
40 7
R5096
39
IN
SMC_MCP_SAFE_MODE
0
1
2
MCP_SPKR
OUT
39
R50311
Unused Pins
1
R5030
523
20
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
39
IN
SMC_FAN_1_CTL
39
65 39 18
TP_SMC_FAN_1_CTL
TP_SMC_FAN_1_TACH
39
IN
SMC_FAN_2_CTL
SMC_FAN_1_TACH
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
402
402
402
402
B
=PP3V3_S0_SMC
R5089
SMC_PA5
10K
1
2
5%
1/16W MF-LF 402
MAKE_BASE=TRUE
39
IN
R50321
1%
1/16W
MF-LF
402 2
6
5
4
D
B
E
MAKE_BASE=TRUE
Q5030
DMB54D0UV
SMC_RSTGATE_L
39
IN
SMC_P20
39
IN
SMC_P24
IN
SMC_P41
39
OUT
39
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
SYNC_MASTER=T27_MLB
SYS_LED_L
S
1
IN
402
402
402
402
PAGE TITLE
Q2
Q1
39
MF-LF
MF-LF
MF-LF
MF-LF
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
SOT-563
2
2
2
2
NO_TEST=TRUE
SMC_FAN_3_TACH
NO_TEST=TRUE
IN
39
OUT
1
1
1
1
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_3_TACH
1.47K
39
100K
10K
10K
100K
NO_TEST=TRUE
SMC_FAN_2_TACH
NO_TEST=TRUE
SMC_FAN_3_CTL
65 39 18 6
OUT
R5076
R5085
R5086
R5090
SMC_BS_ALRT_L
SMC_ADAPTER_EN
SMC_CASE_OPEN
PM_SLP_S4_L
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_2_TACH
SYS_LED_L_VDIV
39
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYS_LED_ILIM
8
5%
5%
5%
5%
SMC Pull-downs
=PP5V_S3_SYSLED
A
=PP3V3_S5_SMC
18
5%
1/16W
MF-LF
402
System (Sleep) LED Circuit
7
39
SOT563
Place R5014 on TOP side
Place R5015 on BOTTOM side
1
IN
Q5059
0
SILK_PART=PWR_BTN
SMC_XTAL
39
SSM6N15FEAPE
R5015
5%
1/10W
MF-LF
603 2
39
IN
PM_THRMTRIP_L
1
0
C
OUT
39
Q5060
D
VOLTAGE=3.3V
C5025
SILK_PART=SMC_RST
OUT
6
TO CPU
10%
16V
CERM 2
402
TO SMC
CPU_PROCHOT_BUF
39 41 58
PAD
GND
1
5%
1/16W
MF-LF
2 402
SMC_PROCHOT_3_3_L
REFOUT 8
THRM
2
1
5%
1/16W
MF-LF
2 402
U5010
10K
5%
1/16W
MF-LF
2 402
1K
VREF-3.3V-VDET-3.0V
SMC_TPAD_RST_L
SMC_ONOFF_L
IN
R5000
VIN
R5060
100K
1
3
V+
10%
6.3V
CERM-X5R 2
402
IN
1
R5061
C5020 1
47
=PP3V3_S0_SMC
1
9
7
1
SMC FSB to 3.3V Level Shifting
=PP3V3_S5_SMC
=PPVIN_S5_SMCVREF
Desktops: 5V
Mobiles: 3.42V
1
40 39 7
2
SMC_SYS_LED
G
2
C
39
3
SYS_LED_ANODE
7
OUT
SMC Support
TP_SMC_P20
MAKE_BASE=TRUE
DRAWING NUMBER
TP_SMC_P24
MAKE_BASE=TRUE
Apple Inc.
TP_SMC_P41
MAKE_BASE=TRUE
39
IN
SMC_PB3
39
IN
SMC_PH3
R
TP_SMC_PB3
MAKE_BASE=TRUE
TP_SMC_PH3
MAKE_BASE=TRUE
36
6
5
051-8563
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
50 OF 109
SHEET
40 OF 80
1
A
8
7
6
5
4
3
2
1
LPC+SPI Connector
CRITICAL
NO STUFF
J5100
D
D
55909-0374
7
7
75 39 18
75 39 18
BI
BI
75 41
75 41
75 39 18
IN
39 18
OUT
40 39
OUT
24
40 39
39
39
40 39 37
M-ST-SM
31
32
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
IN
OUT
IN
OUT
IN
LPC_AD<0>
LPC_AD<1>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
24 75
BI
18 39 75
BI
18 39 75
OUT
6 18 50
41 75
41 75
BI
18 39
IN
18 39
OUT
39 40
OUT
39 40
OUT
39 40 58
OUT
39
OUT
37 39 40
OUT
18
516S0573
C
C
SPI Bus Series Termination
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS
LPCPLUS
1
1
R5128
R5127
0
LPCPLUS
1
R5126
47
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
47
5%
1/16W
MF-LF
2 402
IN
SPI_CS0_R_L
IN
SPI_CLK_R
1
R5112
75 18
IN
SPI_MOSI_R
1
15
15
2
2
SPI_CLK
1
5%
1/16W
MF-LF
402
75 6
SPI_MOSI
75 18 6
OUT
47
1
5%
1/16W
MF-LF
402
B
47
R5123
SPI_MISO
1
15
47
2
47
2
SPI_MLB_CS_L
OUT
50 75
SPI_MLB_CLK
OUT
50 75
SPI_MLB_MOSI
OUT
50 75
SPI_MLB_MISO
IN
50 75
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R5122
2
R5125
1
R5121
75 6
1
R5120
SPI_CS0_L
5%
1/16W
MF-LF
402
R5111
75 18
15
1
41 75
41 75
LPCPLUS
5%
1/16W
MF-LF
2 402
R5110
75 18
41 75
41 75
2
5%
1/16W
MF-LF
402
2
B
5%
1/16W
MF-LF
402
EFI Debug ROM
7
=PP3V3_S0_DEBUGROM
EFI_DEBUG
R51011
0
5%
1/16W
MF-LF
402 2
A
NO STUFF
R51021
0
5%
1/16W
MF-LF
402 2
EFI_DEBUG
1
R5103
EFI_DEBUG
0
C5101
1
0.1UF
5%
1/16W
MF-LF
2 402
8
20%
10V
CERM 2
402
DEBUGROM_E2
DEBUGROM_E1
NO STUFF
1
R5104
0
EFI_DEBUG
VCC
U5101
3 E2
2 E1
M24M01-R
SO8N
SDA 5
=I2C_DEBUGROM_SDA
BI
6
=I2C_DEBUGROM_SCL
IN
CRITICAL SCL
7 WC*
E0/NC0 1
42
42
SYNC_MASTER=T27_MLB
5%
1/16W
MF-LF
PAGE TITLE
NC
LPC+SPI Debug Connector
VSS
4
DRAWING NUMBER
2 402
Apple Inc.
051-8563
R
Write: 0xAC/0xAE
Read: 0xAD/0xAF
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
51 OF 109
SHEET
41 OF 80
1
A
8
7
6
5
MCP89 SMBus "0" Connections
1K
U1400
(MASTER)
D
7
R52001
MCP89
5%
1/16W
MF-LF
402 2
75 18 12
SMBUS_MCP_0_CLK
75 18 12
SMBUS_MCP_0_DATA
1
R5201
1K
5%
1/16W
MF-LF
2 402
3
SMC "0" SMBus Connections
7
4
SO-DIMM "A"
SMC
J2900
(Write: 0xA0 Read: 0xA1)
U4900
(MASTER)
R52501
4.7K
5%
1/16W
MF-LF
402 2
=I2C_SODIMMA_SCL
25
39
SMB_0_S0_CLK
78
=I2C_SODIMMA_SDA
25
39
SMB_0_S0_DATA
78
7
1
R5251
4.7K
5%
1/16W
MF-LF
2 402
MCP Temp
SMC
EMC1412-A: U5535
(WRITE: 0X98 READ: 0X99)
U4900
(MASTER)
SMBUS_SMC_0_S0_SCL
R52801
Vref DACs
SO-DIMM "B"
J3100
(Write: 0xA2 Read: 0xA3)
28
=I2C_VREFDACS_SCL
28
=I2C_VREFDACS_SDA
NBC
=I2C_SODIMMB_SCL
26
=I2C_SODIMMB_SDA
26
=I2C_MCPTHMSNS_SCL
45
39
SMB_BSA_CLK
=I2C_MCPTHMSNS_SDA
45
39
SMB_BSA_DATA
U3310
(Write: 0x30 Read: 0x31)
R52701
1K
U4900
(MASTER)
28
=I2C_PCA9557D_SCL
=I2C_MIKEY_SCL
56
28
=I2C_PCA9557D_SDA
=I2C_MIKEY_SDA
56
5%
1/16W
MF-LF
402 2
39
SMB_A_S3_CLK
78 6
39
SMB_A_S3_DATA
78 6
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
1
R5271
1K
5%
1/16W
MF-LF
2 402
=I2C_DEBUGROM_SDA
70
=I2C_BKL_1_SDA
70
=SMBUS_CHGR_SCL
58
=SMBUS_CHGR_SDA
58
D
=SMBUS_BATT_SCL
57
=SMBUS_BATT_SDA
57
Trackpad
J5800
SMBUS_SMC_A_S3_SCL
=I2C_TPAD_SCL
48
=I2C_TPAD_SDA
48
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMC "Management" SMBus Connections
The bus formerly known as "Battery B"
7
I2C_ALS_SCL
29
I2C_ALS_SDA
29
=PP3V3_S5_SMBUS_SMC_MGMT
R52901
SMC
J3401
U9701
=I2C_BKL_1_SCL
ISL6259 - U7000
J6950 & J6955
(See Table)
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
LP8545 (Bklt)
U5101
(Write: 0xAC/0xAE
Read: 0xAD/0xAF)
41 =I2C_DEBUGROM_SCL
Battery Charger
Battery & BIL
ALS
EFI Debug Serial
1%
1/16W
MF-LF
2 402
Battery
=PP3V3_S3_SMBUS_SMC_A_S3
SMC
2.61K
MAKE_BASE=TRUE
NOTE: SMC RMT bus remains powered and may be active in S3 state
Mikey
U6880
Margin Control
R5281
1%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMC "A" SMBus Connections
7
1
2.61K
MAKE_BASE=TRUE
U3300
41
=PP3V42_G3H_SMBUS_SMC_BSA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
SMC "Battery A" SMBus Connections
=PP3V3_S0_SMBUS_SMC_0_S0
MAKE_BASE=TRUE
C
2
1
R5291
4.7K
U4900
(MASTER)
4.7K
5%
1/16W
MF-LF
402 2
39
SMB_MGMT_CLK
78
39
SMB_MGMT_DATA
78
5%
1/16W
MF-LF
2 402
C
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
HDD Margin Ctrl.
U4510
=I2C_HDD_A_SCL
36
=I2C_HDD_A_SDA
36
MCP89 SMBus "1" Connections
B
7
7
NO STUFF
MCP89
U1400
(Write: 0x?? Read: 0x??)
75 18
SMBUS_MCP_1_CLK
75 18
SMBUS_MCP_1_DATA
SMC "B" SMBus Connections
R52301
2.0K
5%
1/16W
MF-LF
402 2
NO STUFF
1
2.0K
0
5%
1/16W
MF-LF
402 2
4.7K
U4900
(MASTER)
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
MCP89 SMBus 1 is slave port to
access internal thermal diodes.
R52601
SMC
R5231
MAKE_BASE=TRUE
R52351
B
=PP3V3_S0_SMBUS_SMC_B_S0
5%
1/16W
MF-LF
402 2
39
SMB_B_S0_CLK
78
39
SMB_B_S0_DATA
78
1
R5261
4.7K
CPU Temp
EMC1413: U5515
5%
1/16W
MF-LF
2 402
SMBUS_SMC_B_S0_SCL
=I2C_CPUTHMSNS_SCL
45
=I2C_CPUTHMSNS_SDA
45
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
1
R5236
0
5%
1/16W
MF-LF
2 402
NOTE:
A
R5280/81 WAS 2K ON K24, VALUE NEEDS TO BE CHECKED
R5290/91 (VREF DAC, MARGIN CONTROL)WAS 4.7K ON K24, VALUE NEEDS TO BE CHECKED
SYNC_MASTER=T27_MLB
PAGE TITLE
K6 SMBUS CONNECTIONS
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
52 OF 109
SHEET
42 OF 80
1
A
8
7
6
5
4
3
2
1
CPU Voltage Sense / Filter
7 6
PPVCORE_S0_CPU
XW5309
SM
1
2
R5309
4.53K2
CPUVSENSE_IN
SMC_CPU_VSENSE
1
1%
1/16W
MF-LF
402
PLACE_NEAR=L7400.2:5 MM
1
39
OUT
C5309
0.22UF
20%
2 6.3V
X5R
402
D
GND_SMC_AVSS
Place RC close to SMC
D
22 39 40 43 44
MCP Voltage Sense / Filter
7 6
PPVCORE_S0_MCP
XW5359
SM
1
2
R5359
4.53K2
MCPVSENSE_IN
SMC_MCP_VSENSE
1
1%
1/16W
MF-LF
402
PLACE_NEAR=R7525.2:5 MM
1
40
OUT
C5359
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
22 39 40 43 44
C
C
PBUS Voltage Sense Enable & Filter
Q5315
NTUD3169CZ
SOT-963
N-CHANNEL
6
D
65
IN
=PBUSVSENS_EN
2
PBUSVSENS_EN_L
R53161
100K
G
1%
1/16W
MF-LF
402 2
S
Enables PBUS VSense
divider when high.
1
3
PBUS_G3H_VSENSE
D
5
7 6
R53851
27.4K
G
1%
1/16W
MF-LF
402 2
S
PPBUS_G3H
4
RTHEVENIN = 4573 Ohms
P-CHANNEL
B
SMC_PBUS_VSENSE
R53151
1
100K
R5386
1%
1/16W
MF-LF
402 2
5.49K
1%
1/16W
MF-LF
402 2
PBUSVSENS_EN_L_DIV
1
OUT
39
B
C5385
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
22 39 40 43 44
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Voltage Sensing
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
53 OF 109
SHEET
43 OF 80
1
A
8
7
6
5
4
3
2
MCP MEM VDD Current Sense / Filter
7
MCP VCore Current Sense Filter
=PP3V3_S0_MCPDDRISNS
R5416
7
=PP3V3_S0_MCPCOREISNS
62
IN
4.53K2
MCPCORES0_IMON
1%
1/16W
MF-LF
402
0.1uF
20%
10V
CERM 2
402
20
20
IN
IN
MCPDDRFET_KELVIN
1
MCPDDRFET_SENSE
3
+IN
V+
-IN
V-
OPA330
8
=MCPCOREISNS_N
IN
5 IN-
INA214
SC70
OUT 6
2
8
R54101
=MCPCOREISNS_P
(Sense R "input")
4 IN+
R54112
5%
1/16W
MF-LF
402 2
GND
0
Sense R is R7525, 1mOhm
Max Vdiff = 24.8mV
5%
1/16W
MF-LF
402 1
MCPDDR_SENSE_E
(100V/V)
REF 1
40
D
0.22UF
R5415
MCPCORE_IOUT
1
Gain: 100x
Scale:
10A / V
Max VOut: 2.48V
2
0
IN
OUT
C5472
20%
2 6.3V
X5R
402
20%
2 10V
CERM
402
U5420
(Sense R "output")
MCPDDR_SENSE_AMP
C5420
1
0.1uF
V+
SC70-5
4
1
3
U5400
5
SMC_MCP_CORE_ISENSE
1
C5400 1
D
1
0
GND_SMC_AVSS 22 39
PLACEMENT_NOTEs:
2
5%
1/16W
MF-LF
402
40 43 44
Place close to SMC
(For R and C)
NOTE: Do not stuff R5415 and
R7593 at the same time!
NO STUFF
1
2
10%
2 16V
X5R
402
2SA2154MFV-YAE
SOD
1
MCPDDR_SENSE_B
R5417
3
4.53K2
MCPDDR_SENSE_C
SMC_MCP_DDR_ISENSE
1
1%
1/16W
MF-LF
402
1
R5412
118
OUT
40
C5435
1
0.22UF
20%
6.3V
2 X5R
402
PLACEMENT_NOTEs:
1%
1/16W
MF-LF
402 2
C
C5434
0.1UF
Q5401
Place close to SMC
(For R and C)
GND_SMC_AVSS
C
22 39 40 43 44
MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter
7
CPU VCore Load Side Current Sense / Filter
=PP3V3_S0_CPUVTTISNS
R5471
61
CRITICAL
0.01
0.5%
MF
0612-1
1
1W
ISNS_CPUVTT_N
INA213
5 IN-
C5417
ISNS_CPUVTT_P
79
4 IN+
=PPBUS_S5_CPUREGS_ISNS
SMC_CPU_ISENSE
OUT 6
(50V/V)
R5418
4.53K2
CPUVTT_IOUT
1%
1/16W
MF-LF
402
PLACEMENT_NOTEs:
2
SMC_CPU_FSB_ISENSE
1
REF 1
GND
1
R5480
Place close to SMC
(For R and C)
OUT
Place close to SMC
(For R’s and C)
40
1
17.4K
PLACEMENT_NOTEs:
2
4
SC70
1%
1/16W
MF-LF
402
20%
2 10V
CERM
402
U5402
79
6.19K2
1
0.1uF
V+
1
3
R5492
7
IMVP6_IMON
=PPBUS_S5_CPUREGS_ISNS_R
3
7
IN
39
C5470
0.22UF
1%
1/16W
MF-LF
402 2
20%
6.3V
2 X5R
402
GND_SMC_AVSS
1
OUT
22 39 40 43 44
C5436
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
22 39 40 43 44
B
B
Battery (BMON) Current Sense, MUX & Filter
7
=PP3V42_G3H_BMON_ISNS
R5481
BMON:ENG
1
3
PLACEMENT_NOTE=Place near sense resistor
V+
IN
CHGR_CSO_R_P
5 IN-
INA213
SC70
C5418
C5459 1
20%
2 10V
CERM
402
OUT 6
58
BMON:ENG
0.1uF
U5403
Charger/Load side
78 58
0.1uF
BMON_INA_OUT
20%
10V
CERM 2
402
IN
CHGR_CSO_R_N
4 IN+
(50V/V)
Battery side
PLACEMENT_NOTEs:
SC70
1 B1
SEL 6
2 GND
IN
VER 1
ISL6259 Gain: 36x
INA213 Gain: 50x
5%
1/16W
MF-LF
402
For engineering, stuff BMON_ENG
For production, stuff BMON_PROD
1%
1/16W
MF-LF
402
1
1
R5423
100K
5%
1/16W
MF-LF
2 402
SMC_BATT_ISENSE
1
BMON:ENG
BMON:PROD
2
1
OUT
39
C5487
0.22UF
Place close to SMC
(For R and C)
39
45.3K2
BMON_AMUX_OUT
A
0
SMC_DCIN_ISENSE
20%
2 6.3V
X5R
402
GND_SMC_AVSS
22 39 40 43 44
R5401
4
B0
CHGR_BMON
From charger
IN
0
3
2
58
SMC_BMON_MUX_SEL
VCC 5
R5431
A
4.53K2
1
U5413
NC7SB3157P6XG
GND
NOTE: Monitoring current from
battery to PBUS (battery discharge)
across R7008
CHGR_AMON
BMON:ENG
1
REF 1
IN
1%
1/16W
MF-LF
402
BMON:ENG
78 58
DC-IN (AMON) Current Sense Filter
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
1
OUT
39
C5490
0.022UF
10%
2 16V
CERM-X5R
402
GND_SMC_AVSS
22 39 40 43 44
SYNC_MASTER=T27_MLB
PAGE TITLE
Current Sensing
PLACEMENT_NOTE=Place R5431 next to U5413
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
54 OF 109
SHEET
44 OF 80
1
A
8
7
6
5
4
3
2
1
CPU T-Diode Thermal Sensor
D
7
47
1
2
5%
1/16W
MF-LF
402
79 9
D
R5515
=PP3V3_S0_CPUTHMSNS
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
0.1uF
BI
DFN
10K
2
2
5%
1/16W
MF-LF
402
8
CPUTHMSNS_D2_P
4 DP2/DN3
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
42
5 DN2/DP3
GND
6
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
42
C5520 1
3
0.0022uF
1
10%
50V
CERM 2
402
BC846BMXXH
SOT732-3
79
7
R5517
2 DP1
THERM*/ADDR
3 DN1CRITICAL ALERT*
CRITICAL
2
EMC1413
10%
50V
CERM 2
402
1
10K
1%
1/16W
MF-LF
402
CPU_THERMD_N
Fin-Stack Temperature
Q5501
R5516 1
U5515
0.0022uF
CPU Thermal Diode
C5515
20%
2 10V
CERM
402
1
VDD
C5521 1
79 9
1
CPU_THERMD_P
BI
CPUTHMSNS_THERM_L
CPUTHMSNS_ALERT_L
THRM_PAD
11
CPUTHMSNS_D2_N
PLACEMENT_NOTE=Place U5515 near CPU
Local sensor for CPU Proximity
PLACEMENT_NOTE=Place Q5501 near Fin Stack
C
C
MCP T-Diode Thermal Sensor
7
=PP3V3_S0_MCPTHMSNS
R5535
1
47
5%
1/16W
MF-LF
402
79 18
2
PP3V3_S0_MCPTHMSNS_R
VOLTAGE=3.3V
C5522
1
50V
CERM 2
402
BI
MCP_THMDIODE_N
42
BI
42
BI
=I2C_MCPTHMSNS_SDA
=I2C_MCPTHMSNS_SCL
20%
2 10V
CERM
402
1
VDD
U5535
MCP Thermal Diode 0.0022uF
10%
79 18
C5535
0.1uF
MCP_THMDIODE_P
BI
B
1
EMC1412-A
MSOP
2 DP
3 DN
7 SMDATA
8 SMCLK
R5536 1
1
R5537
10K
10K
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
THERM*/ADDR
4
MCPTHMSNS_THERM_L
ALERT*
6
MCPTHMSNS_ALERT_L
B
CRITICAL
GND
5
PLACEMENT_NOTE=Place U5535 near MCP
Local sensor for MCP Proximity
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Thermal Sensors
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
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1
A
8
7
6
5
4
3
2
1
D
D
7
=PP5V_S0_FAN_RT
7
=PP3V3_S0_FAN_RT
CRITICAL
R5660 1
C
47K
5%
39
1/16W
MF-LF
402
R5665
47K 2
1
SMC_FAN_0_TACH
6
J5601
C
78171-0004
NC
M-RT-SM
5
2
1
FAN_RT_TACH
2
5V DC
TACH
3
5%
1/16W
MF-LF
402
4
NC
MOTOR CONTROL
GND
6
R5661 1
100K
518S0521
39
1
G
6
FAN_RT_PWM
3
D
SOD-VESM-HF
2
SMC_FAN_0_CTL
Q5660
SSM3K15FV
2
S
5%
1/16W
MF-LF
402
B
B
A
SYNC_MASTER=K24_MLB
PAGE TITLE
Fan
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
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SHEET
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1
A
8
7
6
5
PSOC USB CONTROLLER
48 47 7
D
2
1.5
BYPASS=U5701.49:50:11 mm
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.49:50:5 mm
PP3V3_S3_PSOC
1
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
IC
USB INTERFACES TO MLB
SPI HOST TO Z2
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
R5704
=PP3V3_S3_TPAD
1
C5704
1
100PF
C5705
1
0.1UF
5%
2 50V
CERM
402
4
PIN NAME
CURRENT
3
R_SNS
V_SNS
2
POWER
TMP102
V+
10UA
80UA
2.55 KOHM 0.0255 V
0.204 V
3V3 LDO
VDD
VOUT
60MA (MAX)
10 OHM
60MA (MAX) 0.2 OHM
0.6
0.012
V
V
36E-3 W
0.72E-3 W
PSOC
VDD
8MA (TYP) 1.5 OHM
14MA (MAX)
0.012
0.021
V
V
96E-6 W
294E-6 W
18V BOOSTER
VIN
4MA (MAX) 4.7 OHM
0.0188 V
75.2E-6 W
Keyboard Connector
0.255E-6 W
16.32E-6 W
48 47 7
47 7
47
4.7UF
47
47
47
47
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
47
48 6
47
47
47
6 47
47
6 47
47
6 47
R5714
6 47
6 47
47
WS_KBD15_C
1
43
44
45
46
47
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
24
2
79
USB_TPAD_N
1
24
6 47
47
Z2_CLKIN
TP_P7_7
2
79
USB_TPAD_R_N
1
10K
47
2
47
1%
1/16W
MF-LF
402
47
47
47
47
6 47
47
R5710
6 47
6 47
40 39
6 47
OUT
SMC_ONOFF_L
C5710
6 47
1
1
0.1UF
6 47
1K
47
2
6 47
6 47
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
5%
1/16W
MF-LF
402
47 6
47 6
20%
10V
CERM 2
402
6 47
47 6
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
3
C5702
1
100PF
5%
2 50V
CERM
402
C
2
1
PLACEMENT_NOTE=NEAR J5713
NC
6 47
31
F-RT-SM
6 47
518S0637
6 47
6 47
6 47
SMC Manual Reset & Isolation
6 48
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
(PP3V3_S3_PSOC)
1
5%
1/16W
MF-LF
402
WS_KBD16N
47
25
J5713
5%
1/16W
MF-LF
402
75 17
47
26
CRITICAL
USB_TPAD_R_P
R5702
47
27
FF14-30A-R11B-B-3H
R5701
USB_TPAD_P
D
28
57
WS_KBD4
WS_KBD5
WS_KBD6
TP_ISSP_SDATA_P1_0
ISSP SDATA/I2C SDA
TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
75 17
WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
C5703
0.1UF
10%
2 16V
X7R-CERM
402
1
Keys ANDed with PSOC power to isolate when PSOC is not powered.
C5701
4.7UF
47 7
=PP3V42_G3H_TPAD
20%
2 6.3V
X5R
603
48 47 7
BYPASS=U5701.22:19:5 mm
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11
=PP3V3_S3_TPAD
CRITICAL
mm
1
VDD
10%
2 16V
X7R-CERM
402
0.1UF
U5750
B
C5750
1
49
50
51
52
53
54
55
48
P7_7
24
P7_0
25
P1_0
26
P1_2
27 P1_4
28
P1_6
48 6
47
2
R5715
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
WS_KBD1
WS_KBD2
6
WS_KBD3
6
WS_KBD4
6
WS_KBD5
6
WS_KBD6
6
WS_KBD7
6
WS_KBD8
6
WS_KBD9
6
WS_KBD10
6
WS_KBD11
6
WS_KBD12
6
WS_KBD13
6
WS_KBD14
6
6 WS_KBD15_CAP
6 WS_KBD16_NUM
WS_KBD17
6
WS_KBD18
6
WS_KBD19
6
WS_KBD20
6
WS_KBD21
6
WS_KBD22
6
WS_KBD23
6
6 WS_KBD_ONOFF_L
23
48 6
337S2983
22 VDD
48 6
(SYM-VER2)
21 D-
48 6
MLF
20 D+
48 6
CY8C24794
19 VSS
48 6
U5701
18 P1_1
48 6
CRITICAL
OMIT
17 P1_3
48 6
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
48 6
C
NC
TP_P4_5
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
48 6
P2_3
2 P2_1
3
P4_7
4
P4_5
5 P4_3
6
P4_1
7
P3_7
8
P3_5
9
P3_3
10
P3_1
11
P5_7
12
P5_5
13 P5_3
14
P5_1
16 P1_5
48 6
1
15 P1_7
WS_CONTROL_KEY
Z2_KEY_ACT_L
470
47
1%
1/16W
MF-LF
402
6 47
NC
47
32
29
47
48 6
NC
47 6
C5706
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
=PP3V3_S3_TPAD
=PP3V42_G3H_TPAD
30
20%
2 6.3V
X5R
603
10%
2 16V
X7R-CERM
402
1
B
SLG4AP006
47 6
WS_LEFT_SHIFT_KBD
2 IN_A1
TDFN
(IPD)
3 IN_A2
OUT_A 4
WS_LEFT_SHIFT_KEY
47
OUT_B 8
WS_LEFT_OPTION_KEY
47
(IPD)
TPAD Buttons Disable
7 IN_A3_B2
(IPD)
47 6
BUTTON_DISABLE
(IPD)
D 3
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
THRM
PAD
GND
9
Q5701
SSM3K15FV
6 IN_B1
5
47
WS_LEFT_OPTION_KBD
SMC_TPAD_RST_L
SOD-VESM-HF
NO STUFF
OUT
40
Q5702
57 40 39
IN
SMC_LID
G
S 2
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
D 3
SOD-VESM-HF
CRITICAL
C5755
1
1
SSM3K15FV
1
VDD
10%
2 16V
X7R-CERM
402
1
0.1UF
U5755
G
S 2
SLG4AP015V
2 IN_A1
TDFN
R5720
(IPD)
OUT_A* 4
3 IN_A2
SMC_TPAD_RST
1
0
2
(IPD)
A
47 6
WS_CONTROL_KBD
5%
1/16W
MF-LF
402
7 IN_A3_B2
(IPD)
OUT_B 8
6 IN_B1
WS_CONTROL_KEY
47
SYNC_MASTER=T27_MLB
WELLSPRING 1
THRM
PAD
DRAWING NUMBER
9
5
GND
PAGE TITLE
(IPD)
Apple Inc.
051-8563
R
8
7
6
5
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1
A
8
7
6
5
4
3
2
1
BOOSTER +18.5VDC FOR SENSORS
D
D
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
CRITICAL
PP5V_S3_P18V5S3
D5802
SOD-323
=PP5V_S3_TPAD
R5805
2
0
P18V5S3_SW
2
1
R5806
PP18V5_S3_R
2
PP5V_S3_P18V5S3_VIN
1
VOLTAGE=5V
5%
1/16W
MF-LF
402
C5818
1
R5812
FB
47 6
C5819
2.2UF
C
10%
THRML
16V
2 X5R
PAD
603
9
402
Z2_BOOST_EN
5
47 6
25V 2
X5R
1
R5813
6 48
48 6
603-1
47 6
71.5K
SW
1%
1/16W
MF-LF
2 402
1
R5811
8
100K
GND
10%
16V
X7R-CERM 2
47 6
1UF
CRITICAL
C5817
PGND
0.1UF
1
CTRL
1%
1/16W
MF-LF
2 402
6
1
DO
1
47 6
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
PP18V5_S3
M-ST-SM
2
10%
QFN
7
C5816
3
J5800
55560-0228
=PP3V3_S3_TPAD
47 7
47 6
TPS61045
NC
CRITICAL
6 48
47 6
1%
1/16W
MF-LF
2 402
P18V5S3_FB
4
PP18V5_S3
VOLTAGE=18.5V
2
1M
5%
50V
CERM 2
402
U5805
L
0
5%
1/16W
MF-LF
402
1
1
39PF
VIN
1
VOLTAGE=18.5V
SWITCH_NODE=TRUE
B0520WSXG
VLF3010AT-SM-HF
2
7
1
VOLTAGE=5V
IPD Flex Connector
CRITICAL
L5801
3.3UH-870MA
NC
6 48
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
6 47
6 47
6 47
6 47
6 47
6 47
6 47
42
42
C
516S0689
Keyboard Backlight Driver & Detection
7
B
=PP5V_S0_KBDLED
CRITICAL
KB_BL
=PP3V3_S0_TPAD
470K
BI
SMC_SYS_KBDLED
1
If LOW, keyboard backlight present
If HIGH, keyboard backlight not present
5%
1/16W
MF-LF
2 402
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
R5854
4.7K
LED 5
6
KB_BL
KB_BL
5%
1/16W
MF-LF
402 2
KBDLED_ANODE
4
R5855
U5850
NO STUFF
10
518S0691
1%
1/16W
MF-LF
2 402
KBDLED_CAP
CAP 4
THRML
GND
PAD
J5815 pin 1 is grounded
on keyboard backlight flex
1
DFN
10K
1
3
CRITICAL
LT3491
R58521
SMC_KDBLED_PRESENT_L
2
SW 3
6 CTRL
KB_BL
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
F-RT-SM
6
10V 2
X5R
402-1
FF18-4A-R11AD-B-3H
VIN
10%
7
39
1
1UF
5%
1/16W
MF-LF
402 2
SWITCH_NODE=TRUE
1098AS-SM
KB_BL
C5850
J5815
1
R58531
B
CRITICAL
KB_BL
10UH-0.58A-0.35OHM
1
2
KBDLED_SW
2
7
Keyboard Backlight Connector
L5850
BYPASS=U5850.1:2:2 MM
KB_BL
1
C5855
1UF
10%
35V
2 X5R
603
(SMC_KBDLED_PRESENT_L)
A
SYNC_MASTER=T27_MLB
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER
Apple Inc.
051-8563
R
K6 NOTES : C5850 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27
8
7
6
5
4
3
2
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1
A
8
7
6
5
4
3
2
1
D
D
C
C
Analog SMS
B
=PP3V3_S3_SMS
R5921 pulls up SMS_PWRDN
to turn off SMS when pin
is not being driven by SMC
R5921 1
10K
C5926
1
1
10UF
5%
1/16W
MF-LF
402 2
20%
4V
X5R
603
14
7
C5922
2
2
10%
16V
X5R
402
U5920
AP344ALH
+Y
LGA
39
IN
SMS_ONOFF_L
SMS_PWRDN
MAKE_BASE=TRUE
SMS_SELFTEST
1
FS
VOUTX
12
SMS_X_AXIS
OUT
39
5
PD
ST
VOUTY
10
SMS_Y_AXIS
OUT
39
OUT
39
2
VOUTZ
15
1
R5922
10K
5%
1/16W
MF-LF
402
8
SMS_Z_AXIS
RES
NC
4
RES CRITICAL
NC
NC
NC
3
NC
C5923
1
0.01UF
6
9
Front of system
+X
+Z (up)
NC
NC
NC
NC
NC
GND
11
13
16
NC
NC
NC
10%
16V
CERM
402
C5924
1
0.01UF
2
10%
16V
CERM
402
C5925
1
Circle indicates pin 1 location when placed
in correct orientation
0.01UF
2
10%
16V
CERM
402
2
7
2
B
Desired orientation when
placed on board top-side:
VDD
0.1UF
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Sudden Motion Sensor (SMS)
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
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REVISION
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1
A
8
7
6
5
4
3
2
1
D
D
7
=PP3V3_S5_ROM
SPI:31MHZ&SPI:62MHZ
SPI:41MHZ&SPI:62MHZ
10K
C
75 41
41 18 6
IN
IN
IN
C6100 1
8
R6101
3.3K
5%
1/16W
MF-LF
402 2
75 41
1
20%
10V
CERM 2
402
10K
U6100
5%
1/16W
MF-LF
2 402
32MBIT
SOP
SI/SIO0 5
MX25L3205DM2I-12G
SPI_MLB_CLK
6 SCLK
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
SPI:25MHZ&SPI:41MHZ
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
R6151
VCC
0.1UF
5%
1/16W
MF-LF
2 402
1
CRITICAL
1 CE*
C
SPI_MLB_MOSI
IN
41 75
SPI_MLB_MISO
OUT
41 75
OMIT
SO/SIO1 2
3 WP*/ACC
7 HOLD*
R61521
SPI:25MHZ&SPI:31MHZ
GND
1
R6153
4
R61501
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
MCP89 SPI Frequency Select
Frequency SPI_MOSI SPI_CLK
B
25.0 MHz
0
0
31.2 MHz
0
1
41.7 MHz
1
0
62.5 MHz
1
1
B
NOTE: 42 & 62 MHz use FAST_READ command.
A
SYNC_MASTER=T27_MLB
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
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1
A
8
7
6
5
4
3
2
1
AUDIO CODEC
APPLE P/N 353S2355
L6201
U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL
FERR-220-OHM
7
1
=PP1V8R1V5_S0_AUDIO
IN
=PP5V_S3_AUDIO
2
C6210
D
1
1
C6211
4.7UF
0.1UF
20%
4V
X5R-1
402
10%
16V
X5R
402
2
2
VOLTAGE=1.5V
=PP3V3R1V5_S0_AUDIO
1UF
1
C6218
10UF
C6221
1
R6210
2.67K
2
1
1
10UF
20%
6.3V
X5R
603-1
20%
6.3V
X5R
603-1
2
2
VBIAS_DAC
CS4206_FP
CS4206_FN
29
44
41
OUT AUD_GPIO_0
2
53
OUT AUD_GPIO_1
12
54
OUT AUD_GPIO_3
56
IN
AUD_SENSE_A
56 55 51 7
IN
=PP3V3_S0_AUDIO
NC TP_AUD_GPIO_2
GPIO3 = SPKR AMP SHDN CONTROL
25
46
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTU6201
CS4206ACNZC
HPREF
1
1
2.2UF
C6226
20%
6.3V
CERM
402-LF
0.1UF
10%
16V
X5R
402
2
HDA_BIT_CLK
IN
HDA_SYNC
HDA_SDIN0
OUT
75 18
IN
75 18
IN
1
1
2
2
10UF
20%
6.3V
X5R
603-1
CRITICAL
GND_AUDIO_CODEC
38
40
AUD_HP_PORT_L
AUD_HP_PORT_R
39
AUD_HP_PORT_REF
2
31
45
FLYP
FLYC
FLYN
MICBIAS
16
VCOM
28
LINEIN_L+
LINEIN_CLINEIN_R+
21
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
VREF+_ADC
27
CS4206_VREF_ADC
NC
4
TP_AUD_DMIC_CLK
NC
42
20%
6.3V
CERM
402-LF
2
TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
43
34
36
37
30
32
33
CS4206_FLYN
VL_HD
1
VL_IF
6
BITCLK
AUD_SDI_R
8
5
11
47
AUD_SPDIF_OUT_CHIP
48
51 53 55
51 52 55 56
OUT
53
OUT
53
IN
55
NC
NC
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
CRITICAL
3
6 51
C6213
GND_AUDIO_HP_AMP
SENSE_A
10
2
10%
16V
X5R
402
20%
16V
TANT-POLY
2012-LLP
13
2.2UF
5%
1/16W
MF-LF
402
HDA_SDOUT
HDA_RST_L
TP_AUD_SPDIF_IN
NC
22
2
1
0.1UF
2
15
C6223
R6211
75 18
2
10%
16V
X5R
402
35
C
IN
10UF
C6214
0.1UF
2
LINEOUT_L1+
LINEOUT_L1LINEOUT_R1+
LINEOUT_R1-
CS4206_FLYP
CS4206_FLYC
C6222
75 18
10%
10V
X5R
402-1
C6217
IN
1
GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
/SPDIF_OUT2
GPIO2
GPIO3
14
1
75 18
1
C6215
QFN
55
GPIO0 = ANALOG SW CONTROL
GPIO1 = HP AMP CONTROL
10%
16V
X5R
402
C6220
10UF
CRITICAL
1%
1/16W
MF-LF
402
24
CRITICAL
PP4V5_AUDIO_ANALOG
IN
1
0.1UF
2
9
51 6
20%
16V
TANT-POLY
2012-LLP
GND_AUDIO_HP_AMP
1
8
D
PP4V5_AUDIO_ANALOG
C6216
C6219
55 53 51
7 51 53 55
PP1V8R1V5_S0_AUDIO_DIG
0402
AUD_CODEC_MICBIAS
OUT
54
OUT
54
OUT
54
OUT
54
OUT
54
OUT
54
OUT
56
FR SPKR AMP. SIG. SOURCE
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
C
CS4206_VCOM
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
22
23
IN
52
IN
52
IN
52
IN
56
IN
56
IN
56
IN
56
SYNC
SDI
SDO
RESET*
SPDIF_IN
SPDIF_OUT
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
17
19
20
EXT MIC CODEC INPUT
BI MIC CODEC INPUT
R6212
1
DMIC_SCL
2
5%
1/16W
MF-LF
402
7
DGND THRM_PAD AGND
26
AUD_SPDIF_OUT
OUT
49
55
39
C6224
1
1
2
2
1UF
20%
16V
TANT
0603-SM
C6225
NOSTUFF
10UF
1
20%
16V
TANT-POLY
2012-LLP
100K
B
2
56 55 52 51
R6213
5%
1/16W
MF-LF
402
B
VOLTAGE=0V
GND_AUDIO_CODEC
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456
NOTES ON CODEC I/O
L6200
VOLTAGE=5V
FERR-220-OHM
55 53 51 7
IN
=PP5V_S3_AUDIO
IN
=PP3V3_S0_AUDIO
1
2
TPS71745
4V5_REG_IN
6
IN
4V5_REG_EN
4
EN
0402
2.21K
1
SON
OUT
1
PP4V5_AUDIO_ANALOG
OUT
DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
6 51
CRITICAL
R6200
56 55 51 7
VOLTAGE=4.5V
U6200
NR/FB
3
NC
5
4V5_NR
2
1%
1/16W
MF-LF
402
GND
1
2
C6200
1UF
2
10%
10V
X5R
402
1
1
C6202
C6201
1UF
XW6200
SM
1
2
1
10%
16V
X7R-CERM
402
10%
10V
X5R
402
C6203
1UF
0.1UF
2
2
10%
10V
X5R
402
GND_AUDIO_CODEC
2
51 52 55 56
NOSTUFF
A
R6201
1
0
SYNC_MASTER=AUDIO
PAGE TITLE
2
AUDIO: CODEC/REGULATOR
5%
1/16W
MF-LF
402
DRAWING NUMBER
Apple Inc.
XW6201
SM
1
VOLTAGE=0V
2
R
GND_AUDIO_HP_AMP
7
6
5
4
3
2
SIZE
D
A.13.0
51 53 55
8
051-8563
REVISION
BRANCH
PAGE
62 OF 109
SHEET
51 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
FC_LP = 43KHZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6301
R6301
55
IN
AUD_LI_L
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
2.2UF
7.87K2
AUD_LI_L_DIV
1
1
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
2
20%
10V
X5R-CERM
402
C
NOSTUFF
1
C6303
820PF
10%
2 50V
CERM
402
AUD_LI_P_L
51
OUT
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
C
1
R6302
21.5K
1%
1/16W
MF-LF
2 402
CRITICAL
C6302
2.2UF
1
2
20%
10V
X5R-CERM
402
55
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_REF
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
51
1
R6300
10
CRITICAL
1%
1/16W
MF-LF
2 402
C6312
2.2UF
1
56 55 51
IN
GND_AUDIO_CODEC
NOSTUFF
1
2
20%
10V
X5R-CERM
402
C6313
820PF
10%
50V
2 CERM
402
B
1
R6312
B
21.5K
1%
1/16W
MF-LF
2 402
CRITICAL
C6311
R6311
55
IN
AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
7.87K2
1
1%
1/16W
MF-LF
402
2.2UF
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1
2
20%
10V
X5R-CERM
402
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
51
A
A
PAGE TITLE
AUDIO: LINE INPUT FILTER
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
63 OF 109
SHEET
52 OF 80
1
8
7
6
5
4
3
2
1
FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).
D
D
L6520
FERR-120-OHM-1.5A
=PP5V_S3_AUDIO
1
55 51 7
HP/LO AMP
APN: 353S1637
AUD_PP5V_F
2
0402-LF
1
2
C6520
1
NO STUFF
C6521
1
0.1UF
10UF
R6521
10%
16V
X7R-CERM
402
20%
6.3V
X5R
603
0
2
5%
1/16W
MF-LF
402
12
2
VDD
AUD_LO_AMP_INL_M
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
6
53
CRITICAL
AUD_LO_AMP_INR_M
8
INL
INR
AUD_GPIO_1_R
5
SHDN*
53
U6500
MAX9724A
1
0.1UF
10%
16V
X7R-CERM
402
NC
2
R6500
55 53 51
IN
PVSS
C6524
2
1
R6523
10%
10V
X5R
402
2.21K
1%
1/16W
MF-LF
2 402
10%
10V
X5R
402
GND_AUDIO_HP_AMP
55 53 51
1
R6524
2.21K
1
1%
1/16W
MF-LF
2 402
C6523
C
1UF
1UF
2
53 55
1UF
C6522
2
OUT
CRITICAL
1
3
CRITICAL
1
53 55
MAX9724_C1P
1
CRITICAL
1
OUT
10
MAX9724_SVSS
5%
1/16W
MF-LF
402
39
5%
1/16W
MF-LF
402
AUD_LO_AMP_OUTR
11
MAX9724_C1N
100K
2
AUD_HP_ZOBEL_L
C
R6522
SVSS
1
4
C6500
PGND
CRITICAL
9
THRM
PAD
5%
1/16W
MF-LF
402
AUD_HP_PORT_L
C1P
C1N
SGND
2
2
0
1
7
IN
AUD_GPIO_1
13
53 51
IN
OUTL
OUTR
TQFN
R6520
51
AUD_LO_AMP_OUTL
2
10%
10V
X5R
402
GND_AUDIO_HP_AMP
R6510
1
39
5%
1/16W
MF-LF
402
NC
MAX9724 GAIN/FILTER COMPONENTS
2
AUD_HP_ZOBEL_R
AV_PB = -1V/V, FC_LPF = 35.2KHZ
CRITICAL
C6510
CRITICAL
1
C6530
0.1UF
10%
16V
X7R-CERM
402
53 51
IN
330PF
1
2
2
5%
50V
COG
402
AUD_HP_PORT_R
R6531
1
13.7K
2
1%
1/16W
MF-LF
402
B
R6530
AUD_HP_PORT_L
53 51
AUD_LO_AMP_INL_M
B
AUD_LO_AMP_OUTL
13.7K
1
IN
2
53
OUT
53 55
OUT
53 55
1%
1/16W
MF-LF
402
R6532
AUD_HP_PORT_R
53 51
IN
13.7K
1
AUD_LO_AMP_INR_M
AUD_LO_AMP_OUTR
2
53
1%
1/16W
MF-LF
402
R6533
1
13.7K
2
1%
1/16W
MF-LF
402
CRITICAL
C6531
330PF
1
2
5%
50V
COG
402
A
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: HEADPHONE FILTER
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
65 OF 109
SHEET
53 OF 80
1
A
8
7
6
5
SATELLITE
4
3
2
1
& SUB TWEETER AMPLIFIER
APN:353S2524
SATELLITE
169 HZ < FC < 282 HZ
SUB
80 HZ < FC < 132 HZ
GAIN
6DB
D
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
C6607
CRITICAL
1
B1
1UF
10%
10V
X5R
402
CRITICAL
L6610
51
AUD_LO2_N_R
IN
1
2
CRITICAL
L6611
AUD_LO2_P_R
1
SPKRAMP_INR_P
1
2
50V
A2
B3
1
50V
0
AUD_GPIO_3
1
R6611
C
100K
R6610
2
2
5%
1/16W
MF-LF
402
54
6 55
GND
2
CERM
402
IN
6 55
SPKRAMP_R_N_OUT
C2 SD*
10%
51
SPKRAMP_R_P_OUT
CRITICAL
0402
C
20%
6.3V
TANT1
2012-LLP
WLCSP OUT+ C3
OUT_ A3
C1 INA1 IN+
SSM2315_R_N
SSM2315_R_P
CERM
402
0.0027UF
2
2
U6610
10%
C6611
FERR-1000-OHM
IN
1
SPKRAMP_INR_N
PVDD
SSM2315
0.0027UF
0402
51
VDD
C6601
47UF
2
C6610
FERR-1000-OHM
1
B2
54 7
5%
1/16W
MF-LF
402
SPKRAMP_SHDN
54 7
=PP5V_S3_AUDIO_AMP
CRITICAL
L6620
IN
1
AUD_LO1_N_R
2
0.022UF
SPKRAMP_INSUB_N
1
2
0402
L6621
51
IN
1
AUD_LO1_P_R
2
SSM2315
SPKRAMP_SUB_N_OUT
WLCSP OUT+ C3
OUT_ A3
C1 INA1 IN+
6 55
6 55
CRITICAL
25V
C6621
X7R
0402
FERR-1000-OHM
SPKRAMP_SUB_P_OUT
20%
6.3V
TANT
CASE-AL1
U6620
2
SSM2315_SUB_N
SSM2315_SUB_P
CRITICAL
10%
PVDD
C2 SD*
0.022UF
1
SPKRAMP_INSUB_P
GND
2
A2
B3
51
10V
X5R
402
C6603
100UF
2
VDD
10%
C6620
FERR-1000-OHM
1
1UF
CRITICAL
B2
C6608
B1
1
0402
10%
25V
X7R
0402
54
SPKRAMP_SHDN
B
B
54 7
=PP5V_S3_AUDIO_AMP
51
IN
AUD_LO2_N_L
1
2
SPKRAMP_INL_N
1
L6631
50V
CERM
402
FERR-1000-OHM
51
IN
AUD_LO2_P_L
10V
X5R
402
2
10%
1
2
SPKRAMP_INL_P
SSM2315_L_N
SSM2315_L_P
CRITICAL
B2
VDD
10%
C6630
0.0027UF
0402
1
1UF
CRITICAL
L6630
FERR-1000-OHM
B1
CRITICAL
C6609
SSM2315
C1 INA1 IN+
SPKRAMP_L_P_OUT
C6605
47UF
PVDD
U6630
2
1
2
20%
6.3V
TANT1
2012-LLP
SPKRAMP_L_N_OUT
WLCSP OUT+ C3
OUT_ A3
6 55
6 55
CRITICAL
C6631
C2 SD*
0.0027UF
1
GND
2
A2
B3
0402
10%
50V
CERM
402
54
SPKRAMP_SHDN
A
SYNC_MASTER=AUDIO
PAGE TITLE
AUDI0: SPEAKER AMP
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
66 OF 109
SHEET
54 OF 80
1
A
8
7
6
5
4
3
2
1
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX
AUD_SPDIF_OUT
IN
51
HS_MIC_HI
OUT
56
HS_MIC_LO
OUT
56
L6701
FERR-1000-OHM
1
56 51 7
2
=PP3V3_S0_AUDIO
0402
L6702
FERR-1000-OHM
1
D
2
D
0402
XW6702
SM
CRITICAL
AUD_CONNJ1_MIC
SPDIF-TXRX-K24
L6703
F-RT-TH
CRITICAL
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
2 AUD_HP_PORT_REF
1
APN:514-0671
J6700
FERR-120-OHM-1.5A
1
AUD_CONNJ1_SLEEVE
6
SM
1
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
2
1
3
51 53
XW6701
0402-LF
5
GND_AUDIO_HP_AMP
2
AUD_CONN_GND
2
51
OUT
XW6700
SM
1
AUD_LI_GND
2
52
CRITICAL
L6704
FERR-220-OHM
1
(AUD_CONN_GND)
AUD_CONN_L
2
4
BI
55
BI
55
55
0402
AUDIO
A - VIN
B - VCC
C - GND
CRITICAL
7
L6705
8
FERR-220-OHM
9
1
POF
R6700
1
10
SHELL
C6700
CRITICAL
1UF
11
10%
2
12
SHIELD
PINS
AUD_CONN_R
2
0402
OPERATING VOLTAGE 3.3
2
DZ6705
6.3V
CERM
402
DZ6703
6.8V-100PF
C
402
CRITICAL
DZ6704
DZ6701
1
1
MIC CONNECTOR
56
CRITICAL
APN:518S0520
J6701
78171-0003
1
402
1
1
1
C6701
100PF
2
OUT
4
56
5%
1/16W
MF-LF
402
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
56 6
56 6
5%
2
C
M-RT-SM
AUD_J1_TIPDET_R
4.7
6.8V-100PF
402
402
1
OUT
R6701
2
DZ6700
6.8V-100PF
6.8V-100PF
AUD_J1_SLEEVEDET_R
2
CRITICAL
2
2
CRITICAL
10K
5%
1/16W
MF-LF
402
6.8V-100PF
402
13
1
CRITICAL
2
50V
56 6
CERM
402
1
2
3
GND_CHASSIS_AUDIO_JACK
VOLTAGE=0V
5
CHASSIS GND STITCHES
XW6710
SM
1
2
XW6711
SM
1
CRITICAL
SPEAKER CONNECTOR
2
J6702
78171-0002
R6760
M-RT-SM
0
1
APN:518S0519
2
5%
1/16W
MF-LF
402
54 6
IN
54 6
IN
3
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
1
2
4
53 51 7
54 6
=PP5V_S3_AUDIO
IN
SPKRAMP_SUB_P_OUT
NO STUFF
1
C6760
33PF
B
2
R6716
53
0
1
OUT
2
AUD_LO_AMP_OUTL_SWITCH
1UF
5%
1/16W
MF-LF
402
2
10%
10V
X5R
402
OUT
2
U6700
C4 NC1
C1 NC2
5%
1/16W
MF-LF
402
52
0
1
IN
1
WLP
COM1 B4
2
A4 NO1
A1 NO2
R6718
AUD_LI_L
AUD_LI_L_SWITCH
2
2
R6712
54 6
IN
24K
54 6
IN
5%
1/16W
MF-LF
402
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
2
33PF
54 6
1
0.0033UF
10%
50V
CERM
402
C3
C6711
B3
AUD_LI_R_SWITCH
2
5%
1/16W
MF-LF
402
1
R6713
6
1
55
GND
0
1
5%
50V
CERM
402
NO STUFF
C6763
AUD_CONN_R
A2 NEG
R6719
AUD_LI_R
4
33PF
2
IN
2
3
1
NO STUFF
C6762
CRITICAL
EN* B2
5%
50V
CERM
402
1
BI
SWITCH_CP
5
33PF
55
COM2 B1
C2 CB
5%
1/16W
MF-LF
402
52
M-RT-SM
NO STUFF
C6761
BI
MAX14560EWC+
AUD_LO_AMP_OUTR_SWITCH
B
J6703
1
AUD_CONN_L
VCC
0
1
CRITICAL
78171-0004
R6717
AUD_LO_AMP_OUTR
53
5%
50V
CERM
402
APN: 353S2803
C6710
A3
AUD_LO_AMP_OUTL
1
IN
APN:518S0521
5%
50V
CERM
402
SPKRAMP_R_N_OUT
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
24K
2
2
5%
1/16W
MF-LF
402
AUD_GPIO_0
51
IN
1
A
R6721
100K
2
R6715
AUD_CONN_GND
55
0
5%
1/16W
MF-LF
402
GND STUFFING OPTIONS FOR CMOS SWITCH
56 52 51
1
GND_AUDIO_CODEC
2
7
ANALOG AUDIO IO SWITCH
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER
AUD_SWITCH_GND
GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED
GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
Apple Inc.
VOLTAGE=0V
051-8563
R6714
1
0
R
R6727
2
1
0
2
5%
1/16W
MF-LF
402
6
5
4
3
2
SIZE
D
REVISION
A.13.0
NOSTUFF
5%
1/16W
MF-LF
402
8
5%
1/16W
MF-LF
402
BRANCH
PAGE
67 OF 109
SHEET
55 OF 80
1
A
8
7
6
5
4
3
2
1
CODEC OUTPUT SIGNAL PATHS
FUNCTION
VOLUME
CONVERTER
PIN COMPLEX
MUTE CONTROL
DET ASSIGNMENT
HP/LINE OUT
0X02 (2)
0X02 (2)
0X09 (9,A)
GPIO_0 AND GPIO_1
0X09 (A)
LINE IN
0X05 (5)
0X05 (5)
0X0C (12)
GPIO_0 AND GPIO_1
SATELLITES
0X04 (4)
0X04 (4)
0X0B (11)
GPIO_3
N/A
SUB
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
SPDIF OUT
N/A
0X08 (8)
0X10 (16)
N/A
0X0D (B)
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ
0X09 (A)AND UI ELEMENT
MIKEY
L6880
VOLTAGE=3.3V
FERR-1000-OHM
56 55 51 7
1
=PP3V3_S0_AUDIO
2
PP3V3_S0_HS_RX
DRC MIKEY
0402
CODEC INPUT SIGNAL PATHS
NOSTUFF
1
FUNCTION
CONVERTER
PIN COMPLEX
VREF
DET ASSIGNMENT
BUILT-IN MIC
0X06 (6)
0X0D (13,B,RIGHT)
MIC_BIAS (80%)
N/A
HEADSET MIC
0X06 (6)
0X0D (13,V22,B,LEFT)
MIKEY
MIKEY
R6885
10K
C6880
5%
1/16W
MF-LF
2 402
D
1
3
D
APN:353S2256
CRITICAL
MIKEY
1UF
MIKEY
10%
AVDD
6.3V
2
CERM
402
U6880
CD3275
PULLUPS ON MCP PAGE
DRC
42
IN
=I2C_MIKEY_SCL
42
BI
=I2C_MIKEY_SDA
6
SCL
MICBIAS
1
HS_MIC_BIAS
5
SDA
DETECT
2
HS_SW_DET
MIKEY
CRITICAL
1
18
IN
AUD_IPHS_SWITCH_EN
8
NOSTUFF
R6880
OUT AUD_SENSE_A
51
INT*
ENABLE
GND
1
2
MIKEY
1
APN:376S0613
R6801
300K
2
AUD_OUTJACK_INSERT_L
2
5%
1/16W
MF-LF
402
1
R6806
1
39.2K
20.0K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
AUD_PORTA_DET_L
D
Q6800
402
MIKEY
CRITICAL
Q6801
D
3
Q6801
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
D
6
51
1
OUT AUD_MIC_INP_L
S
5
G
S
2
4
G
S
51
1
1
OUT AUD_MIC_INN_L
0.1UF
20%
CERM
2
MIKEY
2.2K
5%
1/16W
MF-LF
2
2
402
2.2K
HS_MIC_HI_RC
1
HS_MIC_HI
2
MIKEY
IN
55
IN
55
5%
1/16W
1
R6883
MIKEY
1
MIKEY
1
C6884
5%
1/16W
MF-LF
402
0.0082UF
2
MF-LF
402
100K
2
10%
25V
X5R
402
10V
402
R6882
R6884
10%
25V
X5R
402
0.1UF
4
C6801
C
402
2
MIKEY
CRITICAL
C6886
G
1
1
MF-LF
C6883
AUD_J1_DET_RC
5
R6881
1
1%
47K
2
2
1/16W
NC
51 52 55 56
MIKEY
1K
SOT563
5%
1/16W
MF-LF
402
10%
CERM
0.1UF
SSM6N15FEAPE
1
2
MIKEY
GND_AUDIO_CODEC
3
R6802
AUD_J1_TIPDET_R
16V
402
56 55 52 51
AUD_PORTB_DET_L
NC
GND_AUDIO_CODEC
0.01UF
MF-LF
R6805
20%
6.3V
TANT
402
C6881
1/16W
1
C6882
2.2UF
100K
56 PP3V3_S0_AUDIO_F
IN
HS_RX_BP
THM
5%
56 55
10
BYPASS
9
AUD_I2C_INT_L
11
PORT B DETECT(SPDIF DELEGATE)
OUT
4
PORT A DETECT (HEADPHONES)
7
18
10%
X7R
2
C6885
27PF
25V
402
2
CRITICAL
5%
CERM
50V
402
C
CRITICAL
XW6880
SM
56 55 52 51 GND_AUDIO_CODEC
1
HS_MIC_LO
2
R6803
220K
56 PP3V3_S0_AUDIO_F
1
1
220K
2
56 55
IN
2
AUD_J1_SLEEVEDET_INV
5%
1/16W
MF-LF
402
R6804
D
Q6800
5%
1/16W
MF-LF
402
6
56 55 AUD_J1_SLEEVEDET_R
SSM6N15FEAPE
PORT B RIGHT(BUILT-IN MIC)
SOT563
AUD_J1_SLEEVEDET_R
R6850
1
C6802
2
G
S
2
R6851
100
1
51
0.01UF
IN
2.4K
1
AUD_CODEC_MICBIAS
2
10%
16V
CERM
402
1%
1/16W
MF-LF
402
MIC_BIAS_FILT
1
1
2
1%
1/16W
MF
402-1
CRITICAL
C6852
2.2UF
2
20%
6.3V
TANT
402
CRITICAL
L6850
C6850
FERR-1000-OHM
0.1UF
51
1
OUT AUD_MIC_INP_R
10%
25V
X5R
402
C6851
0.1UF
1
OUT AUD_MIC_INN_R
1
VOLTAGE=3.3V
SM
EXTRACTION NOTIFICATION CKT
L6862
IN
6 55
5%
1/16W
MF-LF
402
1
1
2
2
C6853
IN
6 55
IN
6 55
C6854
0.001UF
50V
402
10%
CERM
27PF
5%
CERM
50V
402
L6851
B
FERR-1000-OHM
R6853
BI_MIC_LO_F
2.4K
1
2
BI_MIC_LO
2
1
BI_MIC_SHIELD
2
FERR-1000-OHM
=PP3V3_S0_AUDIO
BI_MIC_HI
CRITICAL
1%
1/16W
MF
402-1
XW6851
56 PP3V3_S0_AUDIO_F
IN
2
0402
56 55 51 7
R6852
CRITICAL
100K
2
1
BI_MIC_HI_F
2
10%
25V
X5R
402
B
1
0402
CRITICAL
51
2
1
HP=80HZ
2
0402
1
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
R6864
1
220K
C6861
0.1UF
10V
402
20%
CERM
2
2
5%
1/16W
MF-LF
402
1
R6865
100K
Q6802
D
2
5%
1/16W
MF-LF
402
R6861
6
0
SSM6N15FEAPE
AUD_PERPH_DET_R
1
2
SOT563
2
G
S
Q6802
1
15K
5%
1/16W
MF-LF
402
A
3
S
4
OUT
16
SSM6N15FEAPE
SOT563
R6860
1
56 55 AUD_J1_TIPDET_R
D
5%
1/16W
MF-LF
402
TIPDET_FILT
2
5
1
0.1UF
2
G
C6860
AUD_J1_TIPDET_INV
20%
10V
CERM
402
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: JACK TRANSLATORS
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
68 OF 109
SHEET
56 OF 80
1
A
8
7
6
5
4
3
2
1
MagSafe DC Power Jack
CRITICAL
J6900
CRITICAL
78048-0573
F6905
M-RT-SM
6AMP-24V
1
1
6 PP18V5_DCIN_FUSE
3
=PP18V5_DCIN_CONN
7
1206-1
1
4
D
2
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
2
=PP3V42_G3H_ONEWIRE
C6905
7
D
0.01UF
2
R6900
518S0656
C6908
0.1UF
SMC_BC_ACOK_VCC
R6929
2.0K
1
SOT665
TC7SZ08AFEAPE
A
VCC
Y
1
B
SC70-5
SYS_ONEWIRE
4
PLACEMENT_NOTE=PLACE NEAR U6901
U6901
U6900
BI
2
20%
10V
CERM
402
4
1
MAX9940
2
39
2
5
402
MF-LF
1/16W
5%
NOSTUFF
100K
5%
1/16W
MF-LF
402
1
20%
50V
CERM
603
1
6 ADAPTER_SENSE
2
5
SMC_BC_ACOK
3
8 39 40
EXT 5
INT
NC
3
2
GND
NC
1-Wire OverVoltage Protection
3.425V "G3Hot" Supply
Supply needs to guarantee 3.31V delivered to SMC VRef generator
C
C
R6905
BIL CONNECTOR
1
1
2
5%
1/8W
MF-LF
805
PPDCIN_G3H_OR_PBUS_R
P3V42G3H_BOOST
VOLTAGE=18.5V
DIDT=TRUE
C6990
1
C6994
VIN
10UF
10%
25V
X5R
805
3
PPDCIN_G3H_OR_PBUS
6
58
BOOST
20%
6.3V
X5R
402
U6990
2
516S0523
1
CRITICAL
0.22uF
LT3470A
J6955
CRITICAL
CPB6312-0101F
L6995
2
F-ST-SM
33UH
=PP3V42_G3H_REG
7
14
NC
7
SHDN*
NC
SW
4
BIAS
2
FB
THRM
PAD
1
DFN
CRITICAL
5
GND
1
P3V42G3H_SW
SWITCH_NODE=TRUE
DIDT=TRUE
Vout = 3.425V
250MA MAX OUTPUT
57 42
<Ra>
1
C6995
22pF
2
5%
50V
CERM
402
R6995
(Switcher limit)
1
TO SMC
348K
1%
1/16W
MF-LF
402
57 42
40
39 6
=SMBUS_BATT_SDA
4
3
BI
=SMBUS_BATT_SCL
6
5
8
7
1
C6952
1
100
C6954
200K
1
2
SMC_LID
39 40 47
402
5%
1
NC
9
12
11
16
15
1
NC
C6951
47PF
20%
6.3V
CERM
805
R6961
=PP3V42_G3H_BATT
6 SMC_LID_R
MF-LF
C6999
2
7
1/16W
CRITICAL
2
<Rb>
1%
1/16W
MF-LF
402
1
BI
SMC_BIL_BUTTON_L
22UF
R6996
2
10
P3V42G3H_FB
B
13
2
CDPH4D19FHF-SM
9
8
1
C6953
0.001UF
47PF
10%
50V
CERM
402
5%
50V
CERM
402
2
1
5%
50V
CERM
402
10%
25V
X5R
402
2
C6955
0.001UF
1
0.1UF
2
10%
50V
CERM
402
2
2
2
B
Vout = 1.25V * (1 + Ra / Rb)
518-0359
BATTERY CONNECTOR
CRITICAL
J6950
BAT-K24
M-RT-TH
1
2
3
5
6
7
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
A
42 57
CRITICAL
58 6 PPVBAT_G3H_CONN
D6950
9
1
8
C6950
1
10
11
10%
25V
X5R
402
C6960
1
RCLAMP2402B
2
10%
25V
X5R
603-1
R6950
1
10K
SC-75
5%
1/16W
MF-LF
402
1UF
0.1UF
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
42 57
6 SYS_DETECT_L
2
4
2
2
3
P1
P2
P3
P4
P5
P6
P7
P8
P9
12
13
SYNC_MASTER=K24_MLB
PAGE TITLE
DC-In & Battery Connectors
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
69 OF 109
SHEET
57 OF 80
1
A
7
6
5
This node is powered
through body diodes:
* DCIN through Q7080.
* PBUS through Q7085,
Charger TOP FETs and
Q7055.
Reverse-Current Protection
Q7080
SO-8
PPDCIN_G3H_OR_PBUS
SI7149DPCRITICAL
Q7085
CRITICAL
SO-8
S
PPDCIN_G3H_INRUSH
G
4
470K
0.1UF
5%
1/16W
MF-LF
402
2
10%
25V
X5R
402
R7085
1
2
2
1%
1/16W
MF-LF
402
CHGR_SGATE_DIV
CHGR_AGATE_DIV
1
CRITICAL
D7005
2
D
5
2
C7085
100K
1
1
1
R7080
VOLTAGE=18.5V
D
3
3
5
1
1
SI7149DP
57
VOLTAGE=18.5V
2
D
D
2
G
=PPDCIN_S5_CHGR
3
Inrush Limiter
S
FROM ADAPTER
7
4
4
8
R7086 1
R7081
62K
332K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
BAT30CWFILM
(CHGR_SGATE)
MIN_LINE_WIDTH=0.3
mm
SOT-323
1
R7005
CHGR_DCIN_D_R
20
1
2
mm
R7021
(CHGR_DCIN)
10
1
5%
1/16W
MF-LF
402
2
ACIN pin threshold is 3.2V, +/- 50mV
1
Divider sets ACIN threshold at 13.55V
2
30mA max load
1
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
42
IN
42
BI
65
IN
Float CELL for 1S
NO STUFF1
R7013
1K
1%
1/16W
MF-LF
402 2
1
R7015
78
220K
78
5%
1/16W
MF-LF
2 402
R7011
3 ACIN
CHGR_ACIN
1
5 ICOMP
7 VCOMP
8 VNEG
18 CSOP
17 CSON
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
C7050
1UF
9.31K
CHGR_VCOMP_R
1%
1/16W
MF-LF
2 402
2
C7015
10%
16V
X5R
402
1
10%
10V
X5R
402
10%
25V
X5R
402
2
0.1UF
2
2
10%
25V
X5R
402
SGATE
AGATE
CSIP
CSIN
CHGR_DCIN
26
1
28 78
27 78
BOOT 25
UGATE 24
PHASE 23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
LGATE 21
CHGR_LGATE
CRITICAL
D
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
20%
25V
POLY-TANT
CASE-D2-SM
20%
25V
POLY-TANT
CASE-D2-SM
4
1
C7025
G
C7036
1UF
10%
25V
X5R
603-1
10%
25V
X5R
603-1
2
C7037
1
0.001UF
10%
50V
X7R
402
2
C
LFPAK-SM
0.22UF
2
f = 400 kHz
10%
10V
CERM
402
S
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
CRITICAL
2
1
SWITCH_NODE=TRUE
BGATE
AMON
36V/V
BMON
(OD)
ACOK
16
9
15
14
CHGR_BGATE
CHGR_AMON
CHGR_BMON
=CHGR_ACOK
OUT
44
OUT
44
OUT
8
DIDT=TRUE
8AMP-24V
2
1
7
NO STUFF
180
PPVBAT_G3H_CHGR_REG
2
VOLTAGE=12.6V
CRITICAL
1
5
RJK0305DPB
2
1
XW7000
1
2
3
1
C7045
0.001UF
2
10%
50V
X7R
402
R7050
C7039
Q7055
0.01
470PF
2
20%
25V
POLY-TANT
CASE-D2-SM
CRITICAL
NO STUFF
LFPAK-HF
C7040
22UF
CHGR_PHASE_RC
CRITICAL
353S2929
SI7137DP
0.5%
1W
MF
0612-1
10%
50V
CERM
402
SM
2
=PPBUS_G3H
1206
5%
1/10W
MF-LF
603
4
(GND)
SO-8
1
2
3
4
PPVBAT_G3H_CHGR_R
B
TO/FROM BATTERY
VOLTAGE=12.6V
1
1
2
IHLP4040DZ-SM
R7039 1
2
PPVBAT_G3H_CONN
6 57
VOLTAGE=12.6V
G
2
TO SYSTEM
F7040
4.7UH-9.5A
3
3% TOLERANCE
20V/V
CRITICAL
L7030
1
DIDT=TRUE
GATE_NODE=TRUE
Max Current = 8A
Q7035
3.01K
1
1UF
RJK0332DPB-01
DIDT=TRUE
R7016 1
2
C7035
Q7030
B
1%
1/16W
MF-LF
402
22UF
2
1
C7031
5
DCIN 2
470PF
10%
50V
CERM
402
CRITICAL
1
22UF
20
2
C7021
C7030
D
CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL
2
0.1UF
1
CRITICAL
1
5
1
1UF
1
VOLTAGE=18.5V
VDDP
CRITICAL
VHST
SMB_RST_N
SCL
U7000
TQFN
SDA
VFRQ
CELL
ISL6259
SMC_RESET_L
IN
VDD
12
13
11
10
4
6
C7022
1
PGND
41 40 39
0
2
S
5%
1/16W
MF-LF
2 402
58
(AGND)
1K
R7002
100K
R7000
R7012 1
1
22
GND_CHGR_AGND
19
NO STUFF
2
4 2
PPDCIN_G3H_CHGR
C7001
THRM_PAD
10%
10V
X5R
402
1%
1/16W
MF-LF
2 402
0.5%
1W
MF-LF
0612
CHGR_CSI_R_N
78
5%
1/16W
MF-LF
402
VOLTAGE=5.1V
1UF
30.1K
1
1
10
R7020
0.020
R7022
PP5V1_CHGR_VDDP
2
5%
1/16W
MF-LF
402
=PP3V42_G3H_CHGR
CRITICAL
3 1
CHGR_CSI_R_P
78
3
C7002
R7010
4.7
1
29
C
1
10%
10V
CERM
402
R7001
PP5V1_CHGR_VDD
VOLTAGE=5.1V
65 7
C7020
0.047UF
Input impedance of ~40K meets
sparkitecture requirements
2
5%
1/16W
MF-LF
402
2
3
(CHGR_AGATE)
MIN_LINE_WIDTH=0.3
4
CHGR_VNEG_R
1
C7016
(CHGR_CSO_P)
R7051
2.2
1
2
78 44
(CHGR_CSO_N)
R7052
0
1
2
78 44
5%
470PF
2
10%
50V
CERM
402
5%
(PPVBAT_G3H_CHGR_R)
CHGR_CSO_R_P
1/16W
MF-LF
402
CHGR_CSO_R_N
1/16W
MF-LF
402
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
1
2
C7042
C7011
0.033UF
0.01UF
10%
16V
X5R
402
10%
16V
CERM
402
1
1
2
2
C7000
C7005
1UF
0.22UF
10%
10V
X5R
402-1
20%
25V
X5R
603
1
C7026
1
* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
0.001UF
10%
50V
CERM
402
2
58
2
GND_CHGR_AGND
VOLTAGE=0V
A
SYNC_MASTER=T27_MLB
PAGE TITLE
PBus Supply & Battery Charger
DRAWING NUMBER
Apple Inc.
051-8563
R
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
8
7
6
5
4
3
2
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REVISION
A.13.0
BRANCH
PAGE
70 OF 109
SHEET
58 OF 80
1
A
8
7
6
5
4
3
2
1
5V_S3/3.3V_S5 POWER SUPPLY
D
D
VOUT = (2 * RA / RB) + 2
VOUT = (2 * RC / RD) + 2
<RA>
<RB>
<RD>
XW7203
Place XW7203 by Pin1 OF L7260.
SM
5V_S3_VFB_XW7203
2
R7268
R7269
R7270
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1
1
<RC>
R7267
15.0K
ROUTING NOTE:
10K
2
1
10K
2
1
6.49K
2
ROUTING NOTE:
XW7204
Place XW7204 by Pin 2 of L7220.
SM
1
3V3S5_VFB_R7270
2
2
1
59
GND_5V3V3S5_SGND
ROUTING NOTE:
XW7205
SM
65
C
=P5V3V3_REG_EN
2
Place XW7205 by C7252.
1
C
=PPVIN_S3_5VS3
59 7
R7273
ROUTING NOTE:
XW7202
C7272
100K
5%
1/16W
MF-LF
402
1UF
SM
2
10%
2 25V
X5R
603-1
1
2
5V3V3S5_REG3
=PPVIN_S3_5VS3
=PPVIN_S5_3V3S5
5VS3_3V3S5_VREF
1
CRITICAL
C7260
5
0.1UF
CRITICAL
10%
16V
X5R
402
D
Q7260
G
4
2
B
3 2 1
21
20
5V_S3_LL
19
5V_S3_DRVL
24
5V_S3_VO1
CRITICAL
=PP5V_S3_REG
VBST1
CRITICAL
U7200
DIDT=TRUE
5V_S3_DRVH
5
PCMB104E4R7-SM
5V_S3_VFB
2
5V_S3_ENTRIP
1
D
CRITICAL
VREF
DRVH1
QFN
LL1
DRVL1
VO1
2
20%
50V
CERM
402
C7290
10UF
20%
2 6.3V
X5R
603
SIS426DN
C7291
2
9
DRVH2
10 3V3S5_DRVH
R7220
PP5V_S5_LDO
VOLTAGE=5V
C7220 10%
16V
402 5% 1/16W MF-LF
1
3V3S5_VBST
0
DIDT=TRUE
0.1UF
2 3V3S5_VBST_R 2
DIDT=TRUE
X5R
2
PWRPK-12128
G
2
DRVL2
1
VO2
VFB2
ENTRIP2
R7271
WPAK
G1
CRITICAL
DIDT=TRUE
S1/D2
11 3V3S5_LL
12 3V3S5DRVL
7
6
VCLK
18
PGOOD
23
7
1
EN0
GND THRM_PAD
2
CRITICAL
59
6
G2
1
MAX CURRENT = 9.1A
2
3V3S5VO2
B
CRITICAL
4.7UH-10A
S2
3V3S5_ENTRIP
=PP3V3_S5_REG
7
PCMC063T-SM
CRITICAL
NC
13 5V3V3_REG_EN
C7273
1
20%
6.3V
2 X5R
603
GND_5V3V3S5_SGND
R7272
1
C7251
2
1%
1/16W
MF-LF
402
C7250
10UF
150UF
75K
10UF
1
2 6.3V
X5R
603
C7253
0.001UF
20%
20%
6.3V
POLY
B1A-SM
2
20%
50V
CERM
402
2
1
VOLTAGE=0V
6
PWM FREQ. = 375 KHZ
L7220
DIDT=TRUE
5 3V3S5_VFB
1
1%
1/16W
MF-LF
402
20%
50V
CERM
402
RJK0384DPA
1
DIDT=TRUE
ENTRIP1
86.6K
D
2
1
DIDT=TRUE
S
3
20%
16V
POLY
B1A-SM
Q7220
D1
1 402
10%
25V
X5R
603-1
C7242
0.001UF
39UF-0.027OHM
4
220UF
20%
6.3V
ELEC
D1A-SM
17
VBST2
25
0.001UF
1
VREG5
LL2
VFB1
15
C7293
1
VREG3
1
C7240
Q7261
1
2
8
1
C7241
1UF
603
TONSEL
2
4.7UH-13A-15MOHM
7
22
5V_S3_VBST
DIDT=TRUE
1
10%
10V
2 CERM
402
1
2 CERM
VIN
14
SKIPSEL
DIDT=TRUE
L7260
0.22UF
4
1
PWRPK-1212-8-SM
S
C7271
5
1
SIS424DN
MAX CURRENT = 13.3A
PWM FREQ. = 300 KHZ
CRITICAL
20%
10V
10%
25V
2 X5R
603-1
2
2
C7281
1UF
20%
16V
POLY
B1A-SM
3
2
C7280
39UF-0.027OHM
20%
50V
CERM
402
7
C7270
1UF
3
0.001UF
1
16
C7282
1
TPS51125
1
4
59 7
1
1
2
XW7201
SM
Q7221
PLACE_NEAR=U7200.25:1 MM
SSM6N15FEAPE
P5V3V3_PGOOD
65
SOT563
ROUTING NOTE:
=P5VS3_EN_L
65
2
G
S
IN
Q7221
1
D
Place XW7201 between Pin 15 and Pin 25 of U7200.
3
SSM6N15FEAPE
SOT563
A
=P3V3S5_EN_L
65
IN
5
G
S
SYNC_MASTER=K24_MLB
4
PAGE TITLE
5V/3.3V SUPPLY
DRAWING NUMBER
Apple Inc.
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
R
NOTE: DONT SYNC THIS PAGE FROM T27
8
7
6
5
4
3
051-8563
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
72 OF 109
SHEET
59 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
=PPVIN_S3_DDRREG
7
7
=PPVIN_S0_DDRREG_LDO
CRITICAL
1
C7330
C7355 1
20%
16V
POLY
B1A-SM
2
10UF
20%
6.3V
X5R 2
603
7
4.7
VOLTAGE=5V
V5IN
23
14
15
10%
10V 2
X5R
402-1
V5FILT
6 COMP
IN
OUT
28 7
7
U7300
10mA max load
=PPVTT_S0_DDR_LDO
XW7360
SM
1
2
Vout = VTTREF
DRVL 19
2 VTTSNS
C7360
22UF
1
20%
6.3V
X5R-CERM 2
603
NC
NC
CRITICAL
1
C7361
22UF
VDDQSET 9
VTTGND
20%
6.3V
2 X5R-CERM
603
DDRREG_DRVH
GATE_NODE=TRUE
DIDT=TRUE
DDRREG_LL
SWITCH_NODE=TRUE
DIDT=TRUE
DDRREG_DRVL
GATE_NODE=TRUE
DIDT=TRUE
THRM_PAD GND
1
5%
1/16W
MF-LF
402
2
DDRREG_VBST_R
1
2
1
MIN_LINE_WIDTH=0.6 mm 10%
16V
DIDT=TRUE
X5R
28
CRITICAL
PCMB065T-SM
1
SIS426DN
0.001UF
f = 400 kHz
10%
2 50V
X7R
402
PLACE_NEAR=L7330.2:1 MM
C7345
C7341 1
2
XW7345
SM
20%
6.3V
X5R 2
603
20%
2.5V 2
TANT
CASE-B2-SM
3
1
10UF
330UF
CRITICAL
S
1 2
C7346
CRITICAL
PWRPK-12128
G
DDRREG_FB
1
20%
2 2.5V
TANT
CASE-B2-SM
Q7335
4
C7340
330UF
D
(DDRREG_LL)
(DDRREG_DRVL)
=PPDDR_S3_REG 7
Vout = 1.501V / 1.352V
19A MAX OUTPUT
2
5
402
1
PGND CS_GND
XW7335
SM
DDRREG_CSGND
(DDRREG_CSGND)
1
2
1
R7320
1
1
2
Vout = 0.75V * (1 + Ra / Req)
SEL_1V5=0: Req = Rb
SEL_1V5=1: Req = Rb || Rc
B
10%
50V
2 X7R
402
<Ra>
(DDRREG_FB)
10%
16V 2
X5R
402
LVDDR3:YES
LVDDR3:YES
1
<Rc>
GND_DDRREG_SGND
VOLTAGE=0V
C7320
0.001UF
1%
1/16W
MF-LF
2 402
0.033UF
1
15.0K
(DDRREG_VDDQSNS)
XW7300
SM
C7350
C
L7330
1.0UH-13A-5.6MOHM
0.1UF
DDRREG_CS
CS 16
7 NC0
12 NC1
1
CRITICAL
LL 20
24 VTT
DDRREG_VTTSNS
DIDT=TRUE
DRVH 21
SYM (2 OF 2)
Vout = VDDQSNS/2
DDRREG_VBST
0
CRITICAL
1 2 3
C7325
R7325
QFN
5 VTTREF
S
DDRREG_VDDQSNS
VBST 22
TPS51116
=PPVTT_S3_DDR_BUF
SIS424DN
PWRPK-1212-8-SM
MODE 4
18
65
Q7330
G
VDDQSNS 8
10 S3
VTT Enable
11 S5
VDDQ/VTTREF Enable
13 PGOOD VDDQ PGOOD
3
IN
=DDRVTT_EN
=DDRREG_EN
DDRREG_PGOOD
25
65
CRITICAL
D
4
(DDRREG_DRVH)
VLDOIN
CRITICAL
C
5
17
5%
1/16W
MF-LF
402 2
0.001UF
10%
50V
2 X7R
402
1%
1/16W
MF-LF
402 2
1
1UF
10%
10V 2
X5R
805
100K
C7333
10K
C7305
1
4.7UF
R7380
1
10%
25V
2 X5R
603-1
20%
16V
POLY
B1A-SM
R73101
=PP3V3_S3_PDCISENS
C7300
2
C7332
1UF
39UF-0.027OHM
PP5V_S3_DDRREG_V5FILT
2
5%
1/16W
MF-LF
402
1
1
C7331
R7305
=PP5V_S3_DDRREG
1
7
CRITICAL
1
39UF-0.027OHM
R7322
75K
R73211
LVDDR3:YES
18.7K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
<Rb>
B
DDRREG_P1V5_L
LVDDR3:YES
Q7322
SSM3K15FV
D 3
SOD-VESM-HF
1
18
IN
MCP_MEM_VDD_SEL_1V5
G
S 2
(GND_DDRREG_SGND)
Use LVDDR3 for 1.5V/1.35V support or LVDDR3_NOT for fixed 1.5V operation.
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
114S0331
1
RES,15K,1%,1/16W,MF-LF,0402
R7321
A
CRITICAL
SYNC_MASTER=T27_MLB
BOM OPTION
LVDDR3:NO
PAGE TITLE
1.5V/1.35V LVDDR3 Supply
DRAWING NUMBER
Apple Inc.
051-8563
R
NOTE: DONT SYNC THIS PAGE FROM T27. C7330 AND C7331 IS CHANGED TO OSCON CAPS
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
73 OF 109
SHEET
60 OF 80
1
A
8
7
6
4
=PP5V_S0_CPU_IMVP
7
PP5V_S0_IMVP6_VDD
2
1
R7412
10
5%
1/16W
MF-LF
402
D
61 7
2
=PPVIN_S5_CPU_IMVP
1UF
DPRSLPVR
1
10%
16V
X5R
402
10%
10V
2 X5R
805
R7420
5%
1/16W
MF-LF
402
PM_DPRSLPVR
C7496
1
PSI*
OPERATION MODE
0
1
1
2-PHASE CCM
0
1
0
1-PHASE CCM
1
0
1
1-PHASE DCM
VOLTAGE=12.6V
1
0
0
R7421
1UF
10
10%
10V
X5R
402
5%
1/16W
MF-LF
402
1
1
GND_IMVP6_SGND
72 10
CRITICAL
402
1
CPU_NTC:YES
41
CPU_VID<2>
CPU_VID<1>
39
72 10
72 10
CPU_VID<0>
37
CPU_DPRSTP_L
46
72 10
R7445
72 10
1%
1/16W
MF-LF
2 402
0.01uF
10%
16V
CERM
402
C
42
499
ERT-J0EV474J
C7410
1
CPU_VID<5>
72 10
2
IMVP6_NTC_R
72 13 9
72
2
R7406
CPU_PROCHOT_L
1
5%
1/16W
MF-LF
402
1
40 13 9
72
2
5%
1/16W
MF-LF
402
VID1
VID0
DPRSTP*
39
FROM SMC
IMON
24
2
VR_PWRGOOD_DELAY
OUT
2
C7406
2
10%
50V
CERM
402
IMVP6_BOOT2
IMVP6_UGATE1
R7400
34
61
IMVP6_PHASE1
61
IMVP6_LGATE1
1%
1/16W
MF-LF
402
24
61
IMVP6_ISEN1
UGATE2 27
61
IMVP6_UGATE2
LGATE1
PGND1
PHASE2
CLK_EN*
VR_ON
PGND2
1
1
R7409
1K
2
1%
1/16W
MF-LF
402
6
61
IMVP6_SOFT
7
61
IMVP6_RBIAS
4
1
61
IMVP6_VDIFF
13
2
61
IMVP6_FB2
IMVP6_FB
12
IMVP6_COMP
IMVP6_VW
10
61
R7413
61
1K
61
1%
1/16W
MF-LF
402
IMVP6_VDIFF_RC
VR_TT*
61
IMVP6_PHASE2
30
61
IMVP6_LGATE2
ISEN2 23
RBIAS
VO
CRITICAL
Q7402
DIDT=TRUE
IMVP6_ISEN2
61
61
IMVP6_VSUM
IMVP6_OCSET
18
61
IMVP6_VO
61
IMVP6_DROOP
17
61
IMVP6_DFB
1
FB
VSEN
COMP
9
RTN
R7418
15
1K
4.02K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VW
NC
TPAD
49
61
2
2
C7431
0.001UF
10%
50V
CERM
402
61
R7417
1
C7429
180pF
2
IMVP6_COMP_RC
2
5%
25V
CERM
402
2
R7414
2
R7410
1
1
PLACE_NEAR=U7400.21:1 MM
1
C7434
0.033UF
10%
16V
X5R
402
2
SM
1
4
SM
2
1
CRITICAL
SM
2
1
2
10%
50V
CERM
402
XW7413
IMVP_VO2
RJK0208DPA
G
C7423
0.001UF
2
CRITICAL
Q7403
DIDT=TRUE
WPAK
XW7412
2 402
MF-LF
1/16W
5%
IMVP_VSUM2
R7407
1
C7428
1
1
0.22UF
2
1
2
R7405
(THIS NET SHOULD CONNECT
TO U7400.29 WITH MIN LOOP AREA)
1
2
1%
1/16W
MF-LF
402
C7404
10K
IMVP6_VO_R
1
1
CRITICAL
B
0.22UF
1%
1/16W
MF-LF
402
11K
10%
10V
CERM
402
2
R7415
1%
1/16W
MF-LF
402
10%
10V
CERM
402
R7443
3.65K
R7431
10KOHM-5%
(IMVP6_ISEN2)
0603-LF
2
1%
1/16W
MF-LF
402
2
(IMVP6_VSUM)
ERT-J1VR103J
(IMVP6_VO)
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
2
C7421
10%
6.3V
CERM-X5R
402
1
R7423
1
10
R7422
10
1%
1/16W
MF-LF
2 402
2
1%
1/16W
MF-LF
402
CPU_VCCSENSE_P
10 72
CPU_VCCSENSE_N
10 72
61
61
IMVP6 CPU VCORE REGULATOR
61
61
61
A
61
61
MIN_LINE_WIDTH
MIN_NECK_WIDTH
MIN_LINE_WIDTH
1.5 MM
0.25 MM
61
0.25 MM
0.25 MM
61
1.5 MM
0.25 MM
61
1.5 MM
0.25 MM
61
0.25 MM
0.20 MM
61
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
MIN_NECK_WIDTH
61
0.25 MM
0.25 MM
61
0.25 MM
0.20 MM
61
0.25 MM
0.25 MM
61
0.25 MM
0.25 MM
0.25 MM
0.20 MM
61
IMVP6_OCSET
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
MIN_LINE_WIDTH
0.25 MM
MIN_NECK_WIDTH
0.20 MM
0.25 MM
0.20 MM
0.50 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
61
IMVP6_RTN
IMVP6_VSEN
6
5
4
PAGE TITLE
IMVP6 CPU VCore Regulator
DRAWING NUMBER
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
K6 NOTES : Q7400-Q7403 CHANGED BACK TO K24 FETS DUE TO LAYOUT
K6 NOTES : BOM OPTION ADDED TO NTC
7
SYNC_MASTER=K24_MLB
Apple Inc.
3
051-8563
2
SIZE
D
REVISION
R
61
8
1%
1/16W
MF-LF
402
1 2 3
61
61
3.65K
1
R7430
2
0.22uF
XW7400
61
R7401
(IMVP6_COMP)
OMIT
61
1
2.61K
2
0.001UF
2
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
2
1
50V
CERM
402
10%
1%
1/16W
MF-LF
402
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
61
10%
50V
CERM
402
1
S
C7433
1%
1/16W
MF-LF
402
97.6K
61
0.001UF
5
1%
1/16W
MF-LF
402
6.81K
10%
50V
CERM
402
C7422
1
MPCG1040-SM
R7416
1
10%
CERM
402
50V
0.001UF
2
C7411
1UF
10%
25V
X5R
603-1
L7401
13.7K
2
2
C7407
1
(IMVP6_PHASE2)
DIDT=TRUE
D
1
5%
50V
CERM
402
C7432
(IMVP6_VW)
1
20%
16V
POLY-TANT
CASE-D2E-SM
0.36UH-26A-1.05MOHM
1 2 3
(IMVP6_VO)
0.001UF
220PF
20%
16V
POLY-TANT
CASE-D2E-SM
68UF
2
10%
50V
CERM
402
2
14
GND_IMVP6_SGND
1
G
1
C7416
1
1
C7413
CRITICAL
C7408
68UF
D
4
CRITICAL
C7401
S
NO STUFF
FB2
11
21
1
5
0.001UF
GND
10%
50V
CERM
402
2
61
=PPVIN_S5_CPU_IMVP
RJK0365DPA-02
VDIFF
C7414
1
C
(KEEP THIS NET AS SHORT AS POSSIBLE)
19
VSUM
OCSET 8
SOFT
VOLTAGE=0V
2
0.22UF
10%
10V
CERM
402
2
1%
1/16W
MF-LF
402
B
2
C7403
(IMVP6_ISEN1)
(GND)
29
R7411
61
1
2
NTC
25
470PF
1
(KEEP THIS NET AS SHORT AS POSSIBLE)
28
1
(IMVP6_FB)
1
X5R
402
10K
(GND)
33
2
X5R
402
WPAK
255
2
2
(THIS NET SHOULD CONNECT
TO U7400.33 WITH MIN LOOP AREA)
PGOOD
5
IMVP6_NTC
LGATE2
DFB
1
0.001UF
1
61
DROOP 16
1
1
R7404
0.1UF
10%
25V
10%
25V
3V3
47
44
IMVP_VR_ON
IN
1%
1/16W
MF-LF
402
1
0.1UF
61
5%
1/16W
MF-LF
402
PSI*
147K
0.015uF
1
0
1
35
32
10%
50V
CERM
402
2
1 2 3
C7415
C7427
26
PHASE1
0.001UF
2 402
MF-LF
1/16W
5%
IMVP_VSUM1
2 IMVP6_BOOT2_RC
IMVP6_BOOT1
UGATE1
C7420
1
XW7411
IMVP_VO1
R7425
DIDT=TRUE
7
SM
2
1
XW7410
WPAK
61
ISEN1
DPRSLPVR
48
(NC)
R7408
10%
16V
X7R
402
RJK0208DPA
G
61 7
IMVP6_VR_TT
C7405
VID2
3
68
CPU_NTC:YES
4
BOOT1 36
BOOT2
=PPVCORE_S0_CPU_REG
2
SM
2
1
S
QFN
VID3
2
44 IMVP6_IMON
U7400
VID4
45
R7499 1
2
VID5
CRITICAL
Q7401
DIDT=TRUE
CRITICAL
38
CPU_PSI_L
IN
OUT
=PP1V05_S0_CPU
10 9 7
12 11
IN
VID6
40
IMVP_DPRSLPVR
9
CPU_NTC:YES 0
43
CPU_VID<6>
CPU_VID<4>
CPU_VID<3>
72 10
1
2
1
CRITICAL
D
DIDT=TRUE
31
PVCC
DIDT=TRUE
R7426
470K
22
VDD
D
MPCG1040-SM
IMVP6_BOOT1_RC
2
1
20
VIN
IMVP6_VSEN
R7427
4.02K
(IMVP6_PHASE1)
1-PHASE DCM
5%
1/16W
MF-LF
402
CPU_NTC:YES
1%
1/16W
MF-LF
402
1
R7447
IMVP6_RTN
CPU_NTC:YES
PWM FREQ. = 300 KHZ
MAX CURRENT = 65.2A
L7400
0
5%
1/16W
MF-LF
2 402
2
0.36UH-26A-1.05MOHM
1 2 3
DIDT=TRUE
2.0K
2
10%
50V
CERM
402
LOAD LINE SLOPE = -2.1 MV/A
R7424
C7430
61
1
PP3V3_S0_IMVP6_3V3
2
2
5
ISL9504BCRZ
1
0.001UF
1UF
10%
25V
X5R
603-1
RJK0365DPA-02
DIDT=TRUE
=PP3V3_S0_IMVP
20%
16V
POLY-TANT
CASE-D2E-SM
C7419
1
C7418
1
68UF
S
VOLTAGE=3.3V
7
CRITICAL
C7417
20%
16V
POLY-TANT
CASE-D2E-SM
Q7400
G
4
CRITICAL
C7409
68UF
CRITICAL
D
DIDT=TRUE
1UF
10%
16V
X5R
402
2
1
WPAK
PPVIN_S5_IMVP6_VIN
2
DPRSTP*
C7435
4.7UF
1
2
5
VOLTAGE=5V
C7426
10
IN
3
=PPVIN_S5_CPU_IMVP
61 7
1
72 13
5
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SHEET
61 OF 80
1
A
8
7
6
5
7
D
7
4
3
PP5V_S0_MCPREG_VDD
1
VOLTAGE=5V
D
CRITICAL
IN
18
IN
18
IN
18
65
IN
IN
0
1
R7590
R7591
R7592
R7594
0
0
0
0
1
1
2
1
2
1
2
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
MCPCORES0_VSEN
MCPCORES0_RTN
1%
1/16W
MF-LF
2 402
R7566
20
79 21
IN
MCPCORES0_VSEN_N
1
22
PGOOD
VID0
VID1
VID2
VID3
MCPCORES0_BOOT
BOOT 17
DIDT=TRUE
MCPCORES0_PHASE
PHASE 19
5%
10V
CERM-X7R 2
603
SWITCH_NODE=TRUE
DIDT=TRUE
MCPCORES0_COMP
5 COMP
MCPCORES0_FB
6 FB
MCPCORES0_VDIFF
7 VDIFF
R75721
1
R7571
100
150K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
1
C7576
0.1UF
10%
2 16V
X7R-CERM
402
C7577
0.001UF
10%
50V
2 X7R
402
1
10%
50V 2
X7R
402
C7580
330PF
1
B
5%
50V
COG
402
R7577
150K 2
1
2
MCPCORES0_COMP_C
1%
1/16W
MF-LF
402
1
R7576
6.98K
1%
1/16W
MF-LF
2 402
10%
2 50V
X7R
402
CRITICAL
R7525
CRITICAL
0.001
L7560
1 2 3
1%
1W
MF
0612
0.56UH-31A
1
(MCPCORES0_PHASE)
PPMCPCORE_S0_R
2
VOLTAGE=1V
FDU1040D-SM
1
3
2
4
CRITICAL
1
C7566
4
8
OCSET 3
ISP 13
ISN 11
VSS
10UF
MCPCORES0_VO
0.001UF
C
(MCPCORES0_VO)
MCPCORES0_ISP
MCPCORES0_ISN
1%
1/16W
MF-LF
402
MCPCORES0_ICOMP
1
R7573 C7573 1
10K
1%
1/16W
MF-LF
2 402
47PF
5%
50V
CERM 2
402
R7500
1
R7575
2
10%
50V
2 X7R
402
9.76K2
1
1
1
1
20%
2V 2
TANT
CASE-B4-SM
R7569
MCPCORES0_OCSET
10%
50V
2 X7R
402
GND_MCPCORES0_AGND
C7569
C7568 1
270UF
20%
4V
X5R 2
603
(MCPCORES0_ISN)
0.001UF
270UF
C7567 1
S
THRM_PAD
C7578
62
CRITICAL
WPAK
GATE_NODE=TRUE
DIDT=TRUE
C7565
=PPMCPCORE_S0_REG 7
MAX CURRENT: 30.4A
(Q7560 Limit)
f = 300 kHz
20%
2 2V
TANT
CASE-B4-SM
RJK0208DPA
G
1 2 3
PGND
1
20%
2 4V
X5R
603
CRITICAL
MCPCORES0_LGATE
LGATE 21
1%
1/16W
MF-LF
2 402
XW7561
SM
VOLTAGE=0V
C7563
RJK0365DPA-02
Q7565
(MCPCORES0_VW)
C7579 1
1
0.001UF
10%
2 25V
X5R
603-1
Q7560
G
22.1K
0.001UF
1UF
10UF
ICOMP 10
(MCPCORES0_RTN)
C7561
WPAK
D
2
1
4
S
C7570
10%
2 50V
X7R
402
1
CRITICAL
5
VR_ON
AF_EN
FDE
VSEN
RTN
4 VW
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
D
NC
MCPCORES0_VW
C7560 1
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
5
0.22UF
5%
1/10W
MF-LF
1 603
CRITICAL
VO 12
0.001UF
1%
1/16W
MF-LF
402
0
C7564 1
MCPCORES0_UGATE
UGATE 18
(MCPCORES0_VSEN)
1
R7568
20
31
24
25
26
27
23
29
30
32
8
9
C7541 1
GATE_NODE=TRUE
DIDT=TRUE
VIN 14
2
1%
1/16W
MF-LF
402
10%
16V
2 X5R
402
R7565
(MCPCORES0_UGATE)
QFN
28 IMON
MCPCORES0_FDE
100
C
1
2 SOFT
NC
=MCPCORES0_EN
=PPMCPCORE_S0_REG
62 7
MCPCORES0_VSEN_P
MCPCORES0_SOFT
MCP_VID0_REG
MCP_VID1_REG
MCP_VID2_REG
MCP_VID3_REG
2
R7563
IN
1 RBIAS
1/16W MF-LF 402
1
79 21
PVCC
U7500
MCPCORES0_RBIAS
MCPCORES0_IMON_R
2
1UF
VDD
NO STUFF
5%
MCPCORES0_PGOOD
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID<3>
10%
2 16V
X5R
402
C7562
CRITICAL
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
DIDT=TRUE
2
33
OUT
18
R7593
MCPCORES0_IMON
1UF
15
65
OUT
C7550
20
44
1
1
CRITICAL
C7540 1
MCPCORES0_BOOT_R
2
5%
1/10W
MF-LF
603
ISL9563B
1K
5%
1/16W
MF-LF
402 2
2.2
16
R7561
1
=PPVIN_S0_MCPCORE
=PP5V_S0_MCPREG
R7560
1
2
100
2
8
MCPCORES0_ISP_R
1%
1/16W
MF-LF
402
C7575 1
47PF
5%
50V
CERM 2
402
(MCPCORES0_ICOMP)
C7581
B
100PF
1
2
(MCPCORES0_COMP)
5%
50V
CERM
402
VID<3:0>
VOLTAGE
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
0.9750V
0.9625V
0.9500V
0.9375V
0.9250V
0.9125V
0.9000V
0.8875V
0.8750V
0.8625V
0.8500V
0.8375V
0.8250V
0.8125V
0.8000V
0.7875V
(MCPCORES0_FB)
C7582
R7578
1
200
1%
1/16W
MF-LF
402
2
4700PF
MCPCORES0_VDIF_C
R7579
3.01K2
1
2
(MCPCORES0_VDIFF)
10%
100V
CERM
402
1
1%
1/16W
MF-LF
402
A
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP VCore Regulator
DRAWING NUMBER
Apple Inc.
051-8563
R
K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27
8
7
6
5
4
3
2
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REVISION
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SHEET
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1
A
8
7
6
5
4
3
2
1
CPUVTT POWER SUPPLY
D
7
D
=PPVIN_S0_CPUVTTS0
CRITICAL
2
C7630
1
C7695
68UF
1UF
20%
16V
POLY-TANT
CASE-D2E-SM
10%
25V
X5R
603-1
2
C7696
1
0.001UF
20%
50V
CERM
402
2
2
1
Q7620
D1
C
C
RJK0384DPA
1
WPAK
G1
S1/D2
7
L7620
6
7
=PPCPUVTT_S0_REG
2.2UH-8.0A
G2
7
=PP5V_S0_CPUVTTS0
1
CRITICAL
2
C7601
MF-LF
402
1
1UF
10%
10V
X5R
402-1
10
1%
1/16W
R7603
V5FILT
1
2
2
CRITICAL
1%
1/16W
MF-LF
10%
10V
X5R
805
402
65
IN
=CPUVTTS0_EN
1
EN_PSV
OUT
CPUVTTS0_PGOOD
6
PGOOD
(=PPCPUVTT_S0_REG)
3
VOUT
5
VFB
TON
VBST
2
14
CPUVTTS0_TON
DRVH
13
LL
12
11
TRIP
DRVL
THRM_PAD
9
DIDT=TRUE
1
2
1
10%
16V
X5R
402
DIDT=TRUE
CPUVTTS0_LL
DIDT=TRUE
CPUVTTS0_DRVL
PGND
CPUVTTS0_VSNS
DIDT=TRUE
1
8
15
7
B
1
CPUVTTS0_VBST_R
SM
CPUVTTS0_DRVH
GATE_NODE=TRUE
GND
XW7665
C7603
0.1UF
DIDT=TRUE
SWITCH_NODE=TRUE
CPUVTTS0_TRIP
2
5%
1/16W
MF-LF
402
CPUVTTS0_VBST
GATE_NODE=TRUE
CPUVTTS0_VFB
0
1
TPS51117RGY_QFN14
65
2
2
R7680
U7600
SYM
2
QFN
1
226K
C7604
4.7UF
V5DRV
R7604
8.87K
2
NO STUFF
R7670
8.45K
1%
1/16W
MF-LF
402
2
XW7600
1%
1/16W
MF-LF
402
C7670
1
1
C7665
10UF
2
20%
6.3V
X5R
603
1
CRITICAL
2
C7660
2
C7661
0.001UF
20%
50V
CERM
402
1
330UF
20%
2.5V
TANT
CASE-B2-SM
2
B
100PF
5%
50V
CERM
402
2
<Ra>
SM
1
VOUT = 1.066V
15A MAX OUTPUT
F = 360 KHZ
PCMB065T-SM
PP5V_S0_CPUVTTS0_V5FILT
VOLTAGE=5V
4
2
PLACEMENT_NOTE=Place XW7665 next to L7620
301
5
3
R7601
1
4
S2
2
XW7601
(GND)
SM
PLACE_NEAR=U7600.15:1MM
PLACE_NEAR=U7600.7:1MM
1
R7671
1
20.0K
2
1%
1/16W
MF-LF
402
ROUTING NOTE:
<Rb>
GND_CPUVTTS0_SGND
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
CPUVTTS0_VOUT
(=PPCPUVTT_S0_REG)
A
SYNC_MASTER=K24_MLB
PAGE TITLE
CPU VTT(1.05V) SUPPLY
DRAWING NUMBER
Apple Inc.
051-8563
R
K6 NOTES : Q7620 CHANGED BACK TO K24 FETS DUE TO LAYOUT
8
7
6
5
4
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REVISION
A.13.0
BRANCH
PAGE
76 OF 109
SHEET
63 OF 80
1
A
8
7
6
5
4
1.2V ENET Switcher
3
2
1
BCM57765 Internal Switcher Support
(This may be required to use BCM57765)
7
BCM57765
CRITICAL
BCM5764M
=PP3V3_ENET_P1V2ENET
R7730
L7720
2.2UH-1.2A
P1V2ENET_SW
4
CRITICAL
BCM5764M
2
U7720
XW7721
SM
ST1S12G12R
65
IN
TSOT23-5L
1
=P1V2ENET_EN
EN
5
C7720
1
31 24 7
=PP3V3_ENET_PHY
C7721
BCM57765
C7730
20%
6.3V
2 CERM
805
2
20%
6.3V
CERM 2
805
P1V2ENET_FB
=PP1V2_ENET_PHY_REG
PLACEHOLDER!
31
CRITICAL
BCM57765
0
VOLTAGE=3.3V
MAKE_BASE=TRUE
TP_BCM57765_SR_VDDP
31
BCM57765
1
1
4.7UF
BCM57765_SR_LX
1
SWITCH_NODE=TRUE
DIDT=TRUE
2
C7735
0.1UF
10uF
PP1V2_ENET_PHY_VFB
2
VOLTAGE=1.2V
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
BCM57765
C7731
0
1
PCAA031B-SM
20%
10V
2 CERM
402
20%
6.3V
CERM 2
603
R7735
2.2UH-1.2A
31
D
7
BCM57765
L7735
PP3V3_ENET_PHY_VDDP
2
5%
1/16W
MF-LF
402
BCM5764M
1
BCM57765_SR_VDD
R7731
22UF
22UF
VOLTAGE=3.3V
MAKE_BASE=TRUE
BCM57765
1
FB/VO
BCM5764M
PP3V3_ENET_PHY_VDD
2
5%
1/16W
MF-LF
402
2
GND
SW
1
3
0
1
7
Vout = 1.2V
Max Current = 0.7A
F = 1.7MHZ
PCAA031B-SM
SWITCH_NODE=TRUE
DIDT=TRUE
VIN
D
1
=PP1V2_ENET_REG
BCM57765_SR_VFB
31
BCM57765
1
20%
6.3V 2
X5R
603
1
C7736
0.1UF
20%
10V
2 CERM
402
353S2769
1.05V S0 MCP PLL LDO
MCPPLL_R:REG
7
=PP1V05_S0_MCP_PLL_UF_R
R7745
0
1
2
5%
1/16W
MF-LF
402
C
=PP1V05_S0_MCP_PLL_OR
C
7
1.5V S0 Regulator
7
=PP3V3_S0_P1V5S0
CRITICAL
1
C7710
22UF
CRITICAL
20%
CERM
6.3V
805
2
L7710
2.2UH-3.25A
P1V5S0_SW
1
VIN
1
SWITCH_NODE=TRUE
DIDT=TRUE
U7710
C7711 1
ISL8009B
47PF
DFN
65
65
IN
=P1V5S0_EN
2 EN
OUT
P1V5S0_PGOOD
3 POR
VFB 6
4 SKIP
RSI 5
B
CRITICAL
GND
7
=PP1V5_S0_REG
2
5%
50V
CERM 2
402
LX 8
P1V5S0_FB
1
R7711
100K
1%
1/16W
MF-LF
2 402
CRITICAL
<Ra>
1
BOMOPTIONs:
C7715
22UF
MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.
MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.
TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.
TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.
20%
2 6.3V
CERM
805
1
R7712
THRM_PAD
9
7
Vout = 1.508V
MAX CURRENT = 1.5A
f = 1.6MHZ
IHLP1616BZ-SM
113K
1%
1/16W
MF-LF
2 402
B
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
MCP 0.9V S5 (AUXC) Switcher
7
=PP3V3_S5_P0V9S5
1
1.8V S0 Switcher
22UF
1
CRITICAL
C7760
CRITICAL
L7760
1
10UH-0.55A-330MOHM
VI
PCAA031B-SM
1
10uF
20%
6.3V 2
X5R
603
A
IN
=P1V8S0_EN
3
FB
EN
C7762
SOT23-5
2
SW 5
GND
2
P1V8S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
ISL8009B
DFN
65
CRITICAL
IN
=P0V9S5_EN
OUT
P0V9S5_PGOOD
3 POR
VFB 6
4 SKIP
RSI 5
20%
6.3V
2 X5R
603
GND
7
SWITCH_NODE=TRUE
DIDT=TRUE
1
=PP0V9_S5_REG
C7751
1
1
5%
50V
CERM 2
402
LX 8
P0V9S5_FB
R7751
25.5K
1%
1/16W
MF-LF
2 402
1
1
20%
6.3V
2 CERM
805
CRITICAL
<Ra>
C7755
22UF
R7752
THRM_PAD
9
7
Vout = 0.902V
MAX CURRENT = 1.5A
f = 1.6MHZ
2
IHLP1616BZ-SM
47PF
2 EN
10uF
TPS62202
4
65
1
L7750
2.2UH-3.25A
P0V9S5_SW
U7750
65
U7760
CRITICAL
6.3V
20%
CERM
805
1
VIN
7
Vout = 1.8V
MAX CURRENT = 0.3A
F = 1MHZ
=PP3V3_S0_P1V8S0
C7750
2
=PP1V8_S0_REG
7
CRITICAL
200K
SYNC_MASTER=T27_MLB
1%
1/16W
MF-LF
2 402
PAGE TITLE
Misc Power Supplies
<Rb>
DRAWING NUMBER
Apple Inc.
Vout = 0.8V * (1 + Ra / Rb)
051-8563
R
K6 NOTES : C7710 AND C7750 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
77 OF 109
SHEET
64 OF 80
1
A
8
7
6
5
S5 Rail Enables & PGOOD
65 7
State
39 6
IN
79 7 6
U7840
SLG4AP012
SMC_PM_G2_EN
2 IN_A
MAKE_BASE=TRUE
(OD,IPU)
Run (S0)
1
1
1
Sleep (S3)
1
1
0
Soft-Off (S5)
1
0
0
Battery Off (G3Hot)
0
0
0
(OD,IPU)
DLY > 10 ms
2:1 +
1.3V -
S5PGOOD_DLY
7 DLY_1C
220PF
59
P0V9S5_EN
=P0V9S5_EN
OUT
64
MAKE_BASE=TRUE
10K
5%
1/16W
MF-LF
402 2
VFRQ:SLPS4
PM_SLP_S4_L
69 65 39 18 6
SSM3K15FV
PM_SLP_S3_L
58
D
VFRQ:LOW
D 3
1
R7860
SOD-VESM-HF
10K
0
1
OUT
1
5%
1/16W
MF-LF
2 402
G
S 2
CHGR_VFRQ_GATE
2
5%
1/16W
MF-LF
402
THRM
PAD
5
Q7860
R7863
0.033UF
(OD,IPU)
CHGR_VFRQ
VFRQ:SLPS4&VFRQ:SLPS3
2
VFRQ:SLPS3
10%
16V
2 X5R
402
OUT_B 8
DLY
0
1
5%
1/16W
MF-LF
402
C7801
1
GND
5%
25V
2 CERM
402
R78611
65 40 39 18 6
OUT
1
=PP3V42_G3H_CHGR
58 7
VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH
R7864
=P3V3S5_EN_L
MAKE_BASE=TRUE
OUT_A 3
6 IN_B
C7841
P3V3S5_EN_L
OUT_A* 4
(IPD)
PP3V3_S5
Threshold: ??
1
PM_SLP_S3_L
Internal pull-ups 100K +/- 20%
TDFN
=P5V3V3_REG_EN
OUT
WLAN Enable Generation
9
D
59
PM_SLP_S4_L
VDD
20%
10V
CERM 2
402
2
ISL6259 Frequency Select
SMC_PM_G2_ENABLE
CRITICAL
1
0.1uF
3
Power Control Signals
=PP3V42_G3H_PWRCTL
C7840 1
4
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
RSMRST_PWRGD
OUT
MAKE_BASE=TRUE
PM_WLAN_EN_L
39
Q7890
PP5V_S0
7 6
S0PGOOD_ISL
D 6
SSM6N15FEAPE
S3 Rail Enables
S 1
AC_OR_S0_L
PP3V3_S0_VMON
68K
Q7890
=P5VS3_EN_L
OUT
1
IN
C7813
40 39 18
S 4
1 S
G 2
79 65 7 6
79 65 7 6
S 4
69 65 39 18 6
65 7 6
PM_SLP_S3_L
IN
R7812
1
P3V3S3_EN
2
=P3V3S3_EN
OUT
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
66
NO STUFF
1
0.47UF
18
R7811
R78101
100K
DDRREG_EN
=P3V3ENET_EN
=P0V9ENET_EN
MAKE_BASE=TRUE
OUT
66
OUT
66
0.1uF
=DDRREG_EN
OUT
C7810
OUT
1
PP3V3_S0
PP1V5_S0
PP1V05_S0
3 V2MON
5 V3MON
6 V4MON
GND
7
1%
1/16W
MF-LF
2 402
P1V2ENET_EN
MAKE_BASE=TRUE
R78511
S0PGOOD_BJT
R7823
VMON_3V3_DIV
OUT
1K
1
64
5%
1/16W
MF-LF
402 2
MR*
1
RST*
8
100
79 65 7 6
PM_SLP_S3_R_L
R78791
100K
R7881
2
R7880
2
R7882
2
R7883
33K
22K
15K
10K
5%
1/16W
MF-LF
1 402
5%
1/16W
MF-LF
1 402
5%
1/16W
MF-LF
1 402
5%
1/16W
MF-LF
1 402
5%
1/16W
MF-LF
402 2
2
R7884
OUT
66
=PBUSVSENS_EN
OUT
43
PP1V5_S0
5%
1/16W
MF-LF
1 402
7.15K
=P3V3S0_EN
OUT
66
=P1V8S0_EN
OUT
64
P1V5S0_EN
=P1V5S0_EN
64
OUT
62
=CPUVTTS0_EN
OUT
63
MAKE_BASE=TRUE
CPUVTTS0_EN
MAKE_BASE=TRUE
C7881
0.47UF
10%
6.3V
2 CERM-X5R
402
1
C7880
0.47UF
10%
6.3V
2 CERM-X5R
402
1
C7882
0.47UF
10%
6.3V
2 CERM-X5R
402
1
C7883
0.47UF
10%
6.3V
2 CERM-X5R
402
1
2
ALL_SYS_PWRGD
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
2
VMON_Q2_BASE
S0PGOOD_BJT
1
10
B
2
5%
1/16W
MF-LF
402
Q1
2
NC
NC
CRITICAL
S0PGOOD_BJT
8
7
VMON_Q3_BASE
Q2
Q7820
Q3
ASMCC0179
2
1
DFN2015H4-8
Q4
2
VMON_Q4_BASE
Worst-Case Thresholds:
Q2: 0.XXXV
Q3: 0.640V
Q4: 0.660V
353S2809
VMON_EMITTER
S0PGOOD_BJT
R78271
100
5%
1/16W
MF-LF
402 2
SYNC_MASTER=T27_MLB
C7884
PAGE TITLE
Power Sequencing
0.47UF
10%
6.3V
2 CERM-X5R
402
DRAWING NUMBER
Apple Inc.
VTT Rail Enable
IN
MCP_MEM_VDD_EN
VTT rail must ramp up in about
the same time as MEMVDD rail (Q2300).
=DDRVTT_EN
MAKE_BASE=TRUE
OUT
60
K6 HAS A PULL UP ON DDRREG_PGOOD. REMOVED ALIAS TO TP SIGNAL
8
7
24 39
R7828
S0PGOOD_BJT_L
051-8563
6
5
4
3
2
SIZE
D
REVISION
R
20 18
OUT
S0PGOOD_BJT
3.3V w/Divider: 2.345V
OUT
=MCPCORES0_EN
MAKE_BASE=TRUE
MCPCORES0_EN
1K
1
R7822
MAKE_BASE=TRUE
1
PP1V05_S0
1
MAKE_BASE=TRUE
A
1K
1
S0PGOOD_BJT
P1V8S0_EN
10
5%
1/16W
MF-LF
402
R7825
65 7 6
5.1K
P3V3S0_EN
1
S0PGOOD_BJT
=P5VS0_EN
MAKE_BASE=TRUE
2
R7872
S0PGOOD_RST_L
353S2718
5%
1/16W
MF-LF
402
1
5%
1/16W
MF-LF
402
MCPPLLLDO_PGOOD
C
NO STUFF
5
R7859
2
CPUVTTS0_PGOOD
IN
NC
S0PGOOD_BJT
S0 Rail Enables
PM_SLP_S3_L
IN
THRM_PAD
R7824
IN
63
5%
1/16W
MF-LF
402
15K
65 39 18 6
69
MCPCORES0_PGOOD
1%
1/16W
MF-LF
402 2
15.0K
=P1V2ENET_EN
IN
150K
R7821
5%
1/16W
MF-LF
402 2
10%
6.3V
2 CERM-X5R
402
P1V5S0_PGOOD
62
R78261
S0PGOOD_BJT
1
15K
0.47UF
P5V3V3_PGOOD
IN
=PP3V3_S5_VMON
S0PGOOD_BJT
PP3V3_S0
R78501
37
IN
64
U7870
ISL88042IRTJJZ
TDFN
(IPU)
=PP3V3_ENET_PWRCTL
60
VDDA
VDD
20%
10V
CERM 2
402
CRITICAL
S0PGOOD_ISL
59
S0 Rail PGOOD (BJT Version)
79 65 7 6
=USB_PWR_EN
1
5%
1/16W
MF-LF
402 2
B
PM_SLP_RMGT_L
IN
7
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
C7870
ENET Rail Enables
C7812
10%
6.3V
2 CERM-X5R
402
5.1K 2
1
S0PGOOD_ISL
Worst-Case Thresholds:
VDD:
2.9140V
V2MON: 3.000V
V3MON: 0.610V
V4MON: 0.610V
PM_SLP_S4_L
0
R78711
SMC_ADAPTER_EN
IN
10%
2 10V
CERM
402
SOT563
65 40 39 18 6
5 G
VOLTAGE=3.3V
20.0K
SOT563
59
0.068UF
SSM6N15FEAPE
S0PGOOD_ISL
Q7891
SSM6N15FEAPE
SOT563
NO STUFF
5 G
6 D
SSM6N15FEAPE
MAKE_BASE=TRUE
Q7891
D 3
4
5%
1/16W
MF-LF
402 1
5%
1/16W
MF-LF
402 2
S0 Rail PGOOD (ISL Version)
6
AP_PWR_EN
IN
10K
1%
1/16W
MF-LF
402 2
3
29 18
R78132
D 3
R78201
R7870
7
2 G
P5VS3_EN_L
=PP3V3_S0_PWRCTL
10K
=PP3V42_G3H_PWRCTL
C
7
1
SOT563
9
65 7
S0 Rail PGOOD Circuitry
29
OUT
Pull-up is with power FET.
2
P0V9S5_PGOOD
IN
4
64
A.13.0
BRANCH
PAGE
78 OF 109
SHEET
65 OF 80
1
A
8
7
6
3.3V S3 FET
5
4
3
2
3.3V ENET Switch
CRITICAL
Q7910
FDC638P_G
=PP3V3_S3_FET
6
5
2
1
4
R79121
1
10K
D
R7910
P3V3S3_EN_L
1
Q7903
SSM3K15FV
G
1
IN
47K
0.01UF
P3V3S3_SS
2
A2
B2
Q7910
=P3V3ENET_EN
IN
1
2
10%
16V
CERM
402
2.0 A @85C
Loading
0.606 A (EDP)
=PP3V3_ENET_FET
A1
B1
1UF
U7980
10%
6.3V
CERM 2
402
S 2
3.3V S0 FET
Load Switch
R(on)
18 mOhm Typ
50 mOhm Max
I(max)
2 A
Loading
0.4 A (EDP)
C7990
CRITICAL
1
100K
C7931
R7930
P3V3S0_EN_L
1
Q7905
47K
2
10%
2 16V
X5R
402
D
1
100K 2
1
MOSFET
FDC606P
Type
P-Channel
Rds(on)
35 mOhm @2.5V
ID(max)
2.7 A @85C
R7992
2
Loading
10%
16V
CERM
402
Q7990
1
SI2312BDS
G
SOT23
S
Q7991
D 6
2
=PP0V9_ENET_FET
SSM6N15FEAPE
69.8K
R7991
P0V9ENET_EN_L
1.895 A (EDP)
1
10K
1%
1/16W
MF-LF
402
D 3
2
G
S 1
C7991
Q7990
10%
16V
CERM 2
402
2
P0V9ENET_EN_L_RC
SSM6N15FEAPE
65
IN
S 2
5
=P3V3S0_EN
65
IN
G
C
1
0.01UF
SOT563
G
7
SOT563
1%
1/16W
MF-LF
402 2
Q7991
CRITICAL
D
P0V9ENET_SS
5%
1/16W
MF-LF
402
1
0.01UF
P3V3S0_SS
3
20%
10V
CERM 2
402
R7990
Q7930
C7930
5%
1/16W
MF-LF
402
D 3
SOD-VESM-HF
7
3
0.033UF
5%
1/16W
MF-LF
402 2
7
G
R79321
=PP3V3_S0_FET
1 2 5 6
4
S
=PP3V3_S5_P3V3S0FET
1
D
1
0.1UF
FDC606P_G
SOT-6
SSM3K15FV
TPS22924C
Type
=PP0V9_ENET_P0V9ENETFET
Q7930
C
Part
0.9V ENET FET
=P3V3S3_EN
7
7
8
GND
C7980 1
65 mOhm @2.5V
ID(max)
VOUT
C2 ON
P-Channel
Rds(on)
CSP
VIN
CRITICAL
FDC638P
MOSFET
Type
C7910
TPS22924
3
10%
16V
2 X5R
402
5%
1/16W
MF-LF
402
D 3
SOD-VESM-HF
65
C7911
7
65
0.033UF
5%
1/16W
MF-LF
402 2
U7980
7
C1
SM
=PP3V3_S5_P3V3S3FET
7
1
MOSFET
SI2312BDS
Type
N-Channel
Rds(on)
37 mOhm @2.5V
ID(max)
3.25 A @85C
Loading
0.140 A (EDP)
S 4
=P0V9ENET_EN
5V S0 FET
CRITICAL
Q7940
TPCP8102
23V1K-SM
=PP5V_S0_FET
B
1
Q7945
1
IN
G
47K
5%
1/16W
MF-LF
402
D 3
SOD-VESM-HF
65
2
7
Q7940
Part
TPCP8102
Type
P-Channel
Rds(on)
14 mOhm @4.5V
Loading
1.675 A (EDP)
4
C7940
R7940
P5VS0_EN_L
SSM3K15FV
G
10%
16V 2
X5R
402
5%
1/16W
MF-LF
402 2
5 6 7 8
0.033UF
47K
D
C7941 1
R79421
S
=PP5V_S3_P5VS0FET
1 2 3
7
0.01UF
P5VS0_SS
1
2
B
10%
16V
CERM
402
S 2
=P5VS0_EN
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Power FETs
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
79 OF 109
SHEET
66 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
LCD
CONNECTOR
LVDS CONNECTOR:518S0650
16
LCD_IG_PWR_EN
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED
ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
1
R9014
CRITICAL
1K
J9000
5%
1/16W
MF-LF
2 402
20474-030E-11
F-RT-SM
31
CRITICAL
C9015
U9000
0.001UF
FPF1009
1 ON
7
=PP3V3_S5_LCD
MFET-2X2-8IN
3 VIN_2
C
GND
6
C9009
0.1UF
2
VOUT_1 4
PP3V3_LCDVDD_SW
VOUT_2 5
VOLTAGE=3.3V
THRM
PAD
7
1
32
2
1
1
C9011
0.1UF
1
2
2
6
L9008
0402-LF
CRITICAL
1
C9012
10UF
7
=PP3V3_S0_LCD
6
3
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3V
70 6
2
0402-LF
20%
6.3V
2 X5R
603
120-OHM-0.3A-EMI
10%
16V
2 X5R
402
10%
16V
X5R
402
10%
50V
X7R
402
2
FERR-120-OHM-1.5A
2 VIN_1
1
1
0.001UF
10%
50V
X7R
402
L9004
C9010
1
4
5
BKL_VSYNC
6
PP3V3_S0_LCD_F
VOLTAGE=3.3V
7
(LVDS DDC POWER)
74 8 6
LVDS_IG_A_DATA_N<0>
74 8 6
LVDS_IG_A_DATA_P<0>
C
8
9
10
1
1
R9008
100K
2
8 6
LVDS_DDC_CLK
8 6
LVDS_DDC_DATA
5%
1/16W
MF-LF
402
2
R9009
74 8 6
LVDS_IG_A_DATA_N<1>
11
100K
74 8 6
LVDS_IG_A_DATA_P<1>
12
5%
1/16W
MF-LF
402
74 8 6
LVDS_IG_A_DATA_N<2>
14
74 8 6
LVDS_IG_A_DATA_P<2>
15
13
16
CRITICAL
L9080
79 6
LVDS_CONN_A_CLK_F_N
17
90-OHM-200MA
AMC2012-SM
79 6
LVDS_CONN_A_CLK_F_P
18
LVDS I/F
SYM_VER-1
19
74 8
LVDS_IG_A_CLK_N
4
1
74 8
LVDS_IG_A_CLK_P
3
2
70 6
PPVOUT_SW_LCDBKLT
20
NC
C9020
21
1
0.001UF
10%
50V
X7R
402
22
2
23
NC
24
LED BKLT I/F
25
26
27
28
70 6
LED_RETURN_1
70
LED_RETURN_2
70
LED_RETURN_3
70 6
LED_RETURN_4
70 6
LED_RETURN_5
33
70 6
LED_RETURN_6
34
29
30
NC
B
B
A
SYNC_MASTER=K24_MLB
PAGE TITLE
LVDS CONNECTOR
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
90 OF 109
SHEET
67 OF 80
1
A
8
7
6
5
4
3
2
1
D
D
C9300
0.1UF
DP_IG_AUX_CH_P
1
74 8
DP_AUX_CH_C_P
2
8
D
G 2
S 4
6
DP_EXT_DDC_CLK
S
OMIT
G
SIGNAL_MODEL=DP_AUXCH_FET
5
OMIT
1
D 3
10%
16V
X5R
402
Q9300
C9303
SSM6N16FE
Q9300
0.0033UF
SOT563
376S0857
SSM6N16FE
10%
50V
CERM
402
SOT563
C9301
0.1UF
DP_IG_AUX_CH_N
1
74 8
DP_AUX_CH_C_N
2
8
6
D
G 2
S 4
DP_EXT_DDC_DATA
S
C
1
D 3
10%
16V
X5R
402
OMIT
C
5
Q9302
G
OMIT
SSM6N16FE
SOT563
376S0857
Q9302
SSM6N16FE
SOT563
DP_CA_DET
IN
8
B
B
PART NUMBER
QTY
376S0859
2
DESCRIPTION
REFERENCE DES
CRITICAL
XSTR,FT,N-CH,DUAL,SOT-563
Q9300,Q9302
CRITICAL
BOM OPTION
A
SYNC_MASTER=K69_MLB
PAGE TITLE
DISPLAYPORT SUPPORT
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
93 OF 109
SHEET
68 OF 80
1
A
8
7
6
5
4
3
2
1
Port Power Switch
CRITICAL
L9400
65 39 18 6
=PP3V3_S5_DP_PORT_PWR
IN
5
PM_SLP_S3_L
OUT
IN
4
OC*
EN
PP3V3_S0_DPILIM
1
TP_DPPWR_OC_L
3
1
VOLTAGE=3.3V
2
0603
1
GND
2
C9400
9
CERM
402
IO
NC
1
5
10
6
IO
NC
IO
NC
3
3
4
7
CRITICAL
1
C9480
C9481
1
0.1UF
22UF
2
SLP2510P8
IO
NC
20%
16V
2
1
SLP2510P8
PP3V3_S0_DPPWR
VOLTAGE=3.3V
0.01UF
2
CRITICAL
D9410
RCLAMP0524P
FERR-120-OHM-3A
TPS2051B
SOT23
7
D
D9410
RCLAMP0524P
GND
U9480
DP_ESD
CRITICAL
GND
D
DP_ESD
CRITICAL
20%
6.3V
X5R-CERM-1
603
2
20%
10V
CERM
402
C9487
1
100UF
2
C9485
1
C9486
0.1UF
20%
6.3V
POLY-TANT
CASE-B2-SM
2
20%
10V
CERM
402
10UF
2
20%
6.3V
X5R
603
R9420
1
100K
5%
CRITICAL
HDMI_CEC
1/16W
J9400
MF-LF
402
DSPLYPRT-M97-1
2
F-RT-THSM
1
C
1M
5%
BOT ROW
TOP ROW
TH PINS
SM PINS
1/16W
MF-LF
FL9403
2
402
2
4
12-OHM-100MA
TCM1210-4SM
4
79 8
IN
DP_EXT_ML_P<3>
C9414
IN
DP_EXT_ML_N<3>
C9415
1
2
79
DP_EXT_ML_C_P<3>
79
DP_EXT_ML_C_N<3>
10%
16V
X5R
SYM_VER-2
6
1
8
402
0.1uF
79 8
79
1
2
10%
16V
X5R
3
2
79
DP_EXT_ML_F_P<3>
DP_EXT_ML_F_N<3>
402
10
12
14
0.1uF
79 8
BI
DP_EXT_AUX_CH_C_P
16
BI
DP_EXT_AUX_CH_C_N
18
79 8
20
69 7
7
=PP3V3_S0_DPCONN
R9442
5%
100K
1/16W
5%
MF-LF
1/16W
402
1
GND
AUX_CHP
AUX_CHN
DP_PWR
13
R9421
DP_EXT_ML_C_P<0>
C9410
FL9401
1
SYM_VER-2
2
9
79
DP_EXT_ML_F_P<1>
11
79
DP_EXT_ML_F_N<1>
3 79
DP_EXT_ML_C_N<0>
C9411
402
DP_EXT_CA_DET
2
2
22
2
IO
NC
IO
NC
10%
79
DP_EXT_ML_C_P<1>
C9412
79
DP_EXT_ML_C_N<1>
C9413
79
DP_EXT_ML_C_P<2>
C9416
79
DP_EXT_ML_C_N<2>
C9417
1
16V
2
DP_EXT_ML_P<1>
X5R
IN
8 79
IN
8 79
IN
8 79
IN
8 79
IN
8 79
402
FL9402
3
12-OHM-100MA
TCM1210-4SM
1
79
DP_EXT_ML_F_P<2>
79
DP_EXT_ML_F_N<2>
SYM_VER-2
1
10%
16V
2
DP_EXT_ML_N<1>
X5R
402
10%
16V
2
DP_EXT_ML_P<2>
X5R
402
0.1uF
4
17
1
10%
16V
2
DP_EXT_ML_N<2>
X5R
402
10%
16V
0.1uF
2
3
1
X5R
402
21
1
10
DP_ESD
CRITICAL
DP_ESD
D9411
RCLAMP0524P
3
D9400
3
SLP2510P8
RCLAMP0504F
SC70-6-1
D
Q9440
B
1
0.1uF
2
CRITICAL
DP_CA_DET_Q_L
1
8 79
514-0637
GND
D
G
DP_EXT_ML_N<0>
IN
402
5%
MF-LF
2N7002DW-X-G
S
2
X5R
1/16W
2
9
SOT-363
16V
SLP2510P8
6
Q9440
DP_EXT_ML_P<0>
SHIELD PINS
RCLAMP0524P
1
2
10%
0.1uF
4
7
19
1
100K
402
2N7002DW-X-G
5
6
SOT-363
S
G
DP_CA_DET_Q
5
1
6
4
R9422
1
2
Cable Adapter
1M
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
IO
NC
IO
NC
B
4
7
GND
DP to DVI/HDMI
5
(CA) has 100k
3
5%
4
pull-up to DP_PWR.
1/16W
3
MF-LF
402
2
=PP3V3_S0_DPCONN
R9445
1
R9444
10K
5%
10K
1/16W
5%
MF-LF
402
8
4
79
12-OHM-100MA
TCM1210-4SM
5
15
SYM_VER-2
0.1uF
3
GND
ML_LANE2P
ML_LANE2N
RETURN
D9411
1
MF-LF
2
69 7
1
0.1uF
CRITICAL
1
100K
OUT
79
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
C
12-OHM-100MA
TCM1210-4SM
DP_EXT_ML_F_P<0>
DP_EXT_ML_F_N<0>
79
DP_ESD
=PP5VR3V3_S0_DPCADET
R9443
8
FL9400
DP_EXT_ML_F_P<0>
R9425
OUT
1
1/16W
MF-LF
2
402
DP_EXT_HPD
2
6
D
Q9441
2N7002DW-X-G
SOT-363
S
G
2
DP_HPD_Q_L
3
1
D
Q9441
A
2N7002DW-X-G
SOT-363
S
G
5
DP_HPD_Q
SYNC_MASTER=K24_MLB
PAGE TITLE
4
R9423
1
DP Source must pull
DisplayPort Connector
down HPD input with
100K
DRAWING NUMBER
greater than or equal
5%
Apple Inc.
1/16W
to 100K (DPv1.1a).
MF-LF
402
2
R
8
7
6
051-8563
5
4
3
2
SIZE
D
REVISION
A.13.0
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PAGE
94 OF 109
SHEET
69 OF 80
1
A
8
7
6
5
4
3
2
1
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
D
7
0
1
=PPBUS_SW_BKL
8
D
R9701
=PP5V_S0_BKL
2
CRITICAL
5%
1/16W
MF-LF
402
BOOST_VOL:HI
CRITICAL
L9701
1
1217AS-2SM
1
10UF
C9713
0.1UF
10%
2 25V
X5R
402
10%
25V 2
X5R
805
NO STUFF
1
PPBUS_SW_LCDBKLT_PWR_SW
2
CRITICAL
C9712 1
D9701
SOD-123
33UH-1.8A-110MOHM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE
5%
1/16W
MF-LF
402 2
VOLTAGE=50V
OMIT
1
C9796
10%
50V
2 X7R-CERM
402
0
5%
1/16W
MF-LF
2 402
PPVOUT_SW_LCDBKLT
220PF
R9702
0
2
RB160M-60G
1
R9703
1
1
C9797
10UF
1
6 67
OMIT
C9799
10UF
10%
2 50V
X5R
1210
10%
2 50V
X5R
1210
PPVIN_SW_BKL_R
7
=PP3V3_S0_BKL_VDDIO
C9711 1
C9710 1
0.1UF
10%
16V 2
X5R
402
1UF
10%
25V 2
X5R
603-1
VOLTAGE=5V
PP5V_S0_BKL_VLDO
VOLTAGE=5V
1
C9714
0.01UF
10%
2 16V
CERM
402
8
1UF
VDDIO
2
20%
6.3V
X5R
603
R9753
IN
=I2C_BKL_1_SCL
1
42
BI
=I2C_BKL_1_SDA
1
71 8
0
2
2
5%
1/16W
MF-LF
402
1
R9704
8
IN
LCD_BKLT_PWM
33
5%
1/16W
MF-LF
402
1
33PF
OUT1
12
3 ISET
OUT2
13 6
BKL_ISEN2
BKL_SCL
10 SCLK
OUT3
14 6
BKL_ISEN3
BKL_SDA
11 SDA
OUT4
16
BKL_ISEN4
BKL_PWM
2 PWM
OUT5
17
BKL_ISEN5
7 FAULT
OUT6
18
BKL_ISEN6
VSYNC
19
BKL_VSYNC_R
20 FILTER
BKL_EN
2
R9715
100K
4 EN
NO STUFF
1
C9723
0.1UF
10%
2 25V
X5R
402
5%
2 50V
CERM
402
B
21
TP_BKL_FAULT
1%
1/16W
MF-LF
1 402
C9704
24
FB
5 FSET
BKL_ISET
301K 2
1%
1/16W
MF-LF
402
SW
BKL_FLTR
2
R9731
6 GD
NC
BKL_FSET
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R9757
1%
1/16W
MF-LF
402
R97161
90.9K
1%
Fpwm=9.62kHz 1/16W
MF-LF
see spec for others
402 2
BKLT:PROD
OMIT
CRITICAL
1 GND_SW
42
0
LLP
47.0K2
1
R9741
10K
U9701
R9740
BKL_FLTR_R
1
C
R9717
BKL_ISEN1
1
R9755
10K
5%
1/16W
MF-LF
2 402
THRM
PAD
R9714
1
0
2
LED_RETURN_2
5%
1/16W
MF-LF
402
0
1
5%
1/16W
MF-LF
2 402
0
2
LED_RETURN_3
5%
1/16W
MF-LF
402
6 67
OUT
67
OUT
67
OUT
6 67
OUT
6 67
OUT
6 67
BKLT:PROD
IN
6 67
R9720
1
1
OUT
R9719
R9754
XW9710
SM
GND_BKL_SGND
LED_RETURN_1
BKLT:PROD
1
16.2K
1%
1/16W I_LED=23.2mA
MF-LF
2 402
2
R9718
BKL_VSYNC
1
0
5%
1/16W
MF-LF
402
BKLT:PROD
NO STUFF
1
25
1
VIN
LP8545SQX
10UF
NO STUFF
9 GND_S
C9740
VLDO
2
10%
6.3V
X5R
402
NO STUFF
15 GND_L
1
23
C9741
C
22
NO STUFF
2
0
2
LED_RETURN_4
5%
1/16W
MF-LF
402
B
BKLT:PROD
VOLTAGE=0V
R9721
I_LED=610*1.23/Riset
(EEPROM should set EN_I_RES=1)
1
0
2
LED_RETURN_5
5%
1/16W
MF-LF
402
BKLT:PROD
R9722
1
0
5%
1/16W
MF-LF
402
2
LED_RETURN_6
FOR LP8543:
STUFF R9741
NO STUFF R9740, C9740, C9741, R9754
A
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
103S0198
3
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
R9717,R9718,R9719
CRITICAL
BOM OPTION
BKLT:ENG
103S0198
3
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
R9720,R9721,R9722
BKLT:ENG
371S0580
1
SCHOTTKY BARRIER DIODE RB160M-40
D9701
138S0673
2
CAP, 50V, 1210, X5R, 10UF+/-10%
C9797,C9799
10.2 ohm resistors for current
measurement on LED strings.
BOOST_VOL:LOW
CRITICAL
SYNC_MASTER=K69_MLB
PAGE TITLE
LCD Backlight Driver
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
97 OF 109
SHEET
70 OF 80
1
A
8
7
6
5
4
3
2
1
D
CRITICAL
Q9806
D
FDC638APZ_SBMS001
SSOT6-HF
=PPBUS_S0_LCDBKLT
5
2AMP-32V
PPBUS_S0_LCDBKLT_FUSED
2
2
1
C9802
R9808
1
10%
16V
X5R
402
1%
1/16W
MF-LF
402
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
43 mOhm @4.5V
LOADING
0.65 A (EDP)
2
LCDBKLT_EN_DIV
1
MOSFET
0.1UF
301K
2
PPBUS S0 LCDBkLT FET
1
VOLTAGE=12.6V
3
0402-HF
8 70
VOLTAGE=12.6V
4
1
6
F9800
7
R9809
147K
2
1%
1/16W
MF-LF
402
LCDBKLT_EN_L
Q9807
D
3
S
4
SSM6N15FEAPE
SOT563
5
C
8
IN
LCD_BKLT_EN
G
C
LCDBKLT_DISABLE
Q9807
D
6
S
1
SSM6N15FEAPE
SOT563
2
24
IN
G
BKLT_PLT_RST_L
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
LCD Backlight Support
DRAWING NUMBER
Apple Inc.
051-8563
R
7
6
5
4
3
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A.13.0
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REVISION
.
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98 OF 109
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1
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FSB (Front-Side Bus) Constraints
3
2
1
CPU / FSB Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
FSB_DSTB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
*
=2x_DIELECTRIC
?
FSB_DSTB
*
=3x_DIELECTRIC
?
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
?
D
FSB_ADDR
*
?
=STANDARD
FSB_ADDR
TOP,BOTTOM
?
=3x_DIELECTRIC
FSB_ADSTB
*
?
=2x_DIELECTRIC
FSB_ADSTB
TOP,BOTTOM
?
=4x_DIELECTRIC
FSB_1X
*
?
=STANDARD
FSB 4X Signal Groups
FSB_1X
TOP,BOTTOM
?
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Intel Design Guide recommends FSB signals be routed only on internal layers.
FSB 1X Signals
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=50_OHM_SE
=STANDARD
C
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET
LAYER
*
WEIGHT
=STANDARD
?
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
?
CPU_AGTL
TOP,BOTTOM
CPU_8MIL
*
?
8 MIL
CPU_COMP
*
25 MIL
?
CPU_GTLREF
*
25 MIL
?
SR DG recommends at least 25 mils, >50 mils preferred
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=50_OHM_SE
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
8 MIL
?
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DATA_GROUP1
FSB_DATA_GROUP1
FSB_DSTB1
FSB_DSTB1
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DATA_GROUP2
FSB_DATA_GROUP2
FSB_DSTB2
FSB_DSTB2
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DATA_GROUP3
FSB_DATA_GROUP3
FSB_DSTB3
FSB_DSTB3
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_ADDR_GROUP0
FSB_ADDR_GROUP0
FSB_ADSTB0
FSB_50S
FSB_50S
FSB_50S
FSB_ADDR
FSB_ADDR
FSB_ADSTB
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_ADDR_GROUP1
FSB_ADSTB1
FSB_50S
FSB_50S
FSB_ADDR
FSB_ADSTB
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_1X
FSB_BREQ0_L
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_CPURST_L
FSB_1X
FSB_1X
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_ADS_L
FSB_BREQ0_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_ASYNC
CPU_BSEL
CPU_FERR_L
CPU_ASYNC
CPU_INIT_L
CPU_ASYNC_R
CPU_ASYNC_R
CPU_PROCHOT_L
CPU_PWRGD
CPU_ASYNC
CPU_ASYNC
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_FROM_SB
CPU_DPRSTP_L
CPU_ASYNC
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
FSB_CLK_CPU
FSB_CLK_CPU
FSB_CLK_ITP
FSB_CLK_ITP
FSB_CLK_MCP
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
(See above)
CPU_50S
CPU_50S
CPU_AGTL
CPU_AGTL
PM_DPRSLPVR
IMVP_DPRSLPVR
MCP_CPU_COMP
MCP_CPU_COMP
MCP_CPU_COMP
MCP_CPU_COMP
MCP_50S
MCP_50S
MCP_50S
MCP_50S
MCP_FSB_COMP
MCP_FSB_COMP
MCP_FSB_COMP
MCP_FSB_COMP
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_50S
CPU_50S
CPU_27P4S
CPU_50S
CPU_27P4S
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L
XDP_BPM_L5
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_8MIL
CPU_8MIL
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
D
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
9 13
9 13
9 13
9 13
9 13
9 13
6 9 13
6 9 13
6 9 13
C
9 12 13
9 13
9 13
CPU_AGTL
FSB_DATA_GROUP0
FSB_DATA_GROUP0
FSB_DSTB0
FSB_DSTB0
9 13
8 9
9 13
9 13
9 13
9 13
9 13
9 13 40 61
9 12 13
9 13
9 13
9 13 40
9 13
9 13
9 13 61
9 13
9 13
9 13
12 13
12 13
13
13
B
MCP_FSB_COMP
*
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4
FSB Clock Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CLK_FSB_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
?
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
?
CLK_FSB
*
CLK_FSB
TOP,BOTTOM
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
(FSB_CPURST_L)
CPU_VCCSENSE
CPU_VCCSENSE
A
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_IERR_L
B
9
13 61
61
13
13
13
13
9 28
9
9
9
9
9 12
9 12
9 12
9 12
9 12
9 12
9 12
12
10 61
10 61
10 61
SYNC_MASTER=T27_MLB
PAGE TITLE
CPU/FSB Constraints
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
100 OF 109
SHEET
72 OF 80
1
A
8
7
6
5
Memory Bus Constraints
4
3
2
1
Memory Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
SPACING_RULE_SET
LAYER
WEIGHT
MEM_CLK2MEM
*
=4:1_SPACING
?
MEM_CTRL2CTRL
*
=2:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
NV DG says 3x inner, 4x outer
D
MEM_CMD2CMD
*
?
=1.5:1_SPACING
MEM_A_CLK
MEM_A_CLK
MEM_70D
MEM_70D
MEM_CLK
MEM_CLK
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CKE
MEM_A_CNTL
MEM_A_CNTL
MEM_40S
MEM_40S
MEM_40S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK
MEM_B_CLK
MEM_70D
MEM_70D
MEM_CLK
MEM_CLK
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE
MEM_B_CNTL
MEM_B_CNTL
MEM_40S
MEM_40S
MEM_40S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
14 25
14 25
14 20 25
14 25
14 25
14 25
14 25
D
14 25
14 25
14 25
MEM_CMD2MEM
*
=3:1_SPACING
?
MEM_DATA2DATA
*
=1.5:1_SPACING
?
MEM_DATA2MEM
?
=3:1_SPACING
*
MEM_DQS2MEM
*
?
=3:1_SPACING
MEM_2OTHER
*
?
25 MIL
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
MEM_CLK
MEM_CMD
*
MEM_CLK2MEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
MEM_CMD
MEM_DATA
*
MEM_CMD2MEM
MEM_CLK
MEM_DQS
*
MEM_CLK2MEM
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
*
MEM_CTRL2MEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
C
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
*
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
*
MEM_CTRL2MEM
MEM_CTRL
MEM_DQS
*
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
*
MEM_DATA2DATA
MEM_DATA
MEM_DQS
*
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
*
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
*
*
MEM_2OTHER
MEM_DQS
MEM_CTRL
*
MEM_DQS2MEM
MEM_DQS
MEM_CMD
*
MEM_DQS2MEM
MEM_DQS
MEM_DATA
*
MEM_DQS2MEM
MEM_CTRL
*
*
MEM_2OTHER
MEM_CMD
*
*
MEM_2OTHER
MEM_DATA
*
*
MEM_2OTHER
MEM_DQS
*
MEM_DQS2MEM
MEM_DQS
*
*
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
CMD/CTRL signals should be matched within 150 ps.
All memory signals maximum length is 1.030 ps.
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
B MCP MEM COMP Signal Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_MEM_COMP
*
=40_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
?
MCP_MEM_COMP
*
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
C
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 26
14 26
MEM_DQS
14 27
NET_SPACING_TYPE1
14 27
A
14 20 26
14 26
14 26
14 26
14 26
14 26
14 26
14 26
14 27
14 27
14 27
14 27
B
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
SYNC_MASTER=T27_MLB
PAGE TITLE
Memory Constraints
14 27
DRAWING NUMBER
14
14
Apple Inc.
051-8563
R
MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
101 OF 109
SHEET
73 OF 80
1
A
8
7
6
5
PCI-Express
4
3
2
1
MCP89 Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
CLK_PCIE_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
NET_TYPE
PHYSICAL
SPACING
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
MCP_PEX_COMP
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
MCP_PEX0_TERMP
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_SYNC
CRT_SYNC
MCP_DAC_RSET
MCP_DAC_VREF
CRT_50S
CRT_50S
CRT_50S
CRT_50S
CRT_50S
CRT
CRT
CRT
CRT_SYNC
CRT_SYNC
MCP_DAC_COMP
MCP_DAC_COMP
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
TMDS_IG_TXC
TMDS_IG_TXC
TMDS_IG_TXD
TMDS_IG_TXD
DP_90D
DP_90D
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<5..0>
TMDS_IG_TXD_N<5..0>
DP_EXT_ML
DP_EXT_ML
DP_EXT_AUX_CH
DP_EXT_AUX_CH
DP_90D
DP_90D
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
MCP_TMDS0_RSET
MCP_TMDS0_VPROBE
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_IG_A_DATA3
LVDS_IG_A_DATA3
LVDS_IG_B_CLK
LVDS_IG_B_CLK
LVDS_IG_B_DATA
LVDS_IG_B_DATA
LVDS_IG_B_DATA3
LVDS_IG_B_DATA3
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_DV_COMP
SATA_HDD_R2D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
PEG_R2D
WEIGHT
=3X_DIELECTRIC
?
SPACING_RULE_SET
LAYER
WEIGHT
=4X_DIELECTRIC
?
PCIE
*
PEG_D2R
PCIE
TOP,BOTTOM
D
CLK_PCIE
*
20 MIL
?
MCP_PEX_COMP
*
8 MIL
?
D
PCIE_AP_R2D
NEED PCIe Gen1/Gen2 notes!
PCIE_AP_D2R
PCIE_ENET_R2D
Analog Video Signal Constraints
PCIE_ENET_D2R
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CRT_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRT
*
?
20 MIL
PCIE_FW_R2D
CRT
CRT
*
CRT_2CRT
CRT_2CRT
*
?
15 MIL
PCIE_FW_D2R
CRT_2CLK
*
?
50 MIL
CRT_2SWITCHER
*
?
250 MIL
6 29
6 29
15 29
15 29
6 15 29
6 15 29
31
31
15 31
15 31
15 31
15 31
31
31
33
33
15 33
15 33
15 33
15 33
33
33
CRT_SYNC
*
=4x_DIELECTRIC
?
MCP_DAC_COMP
*
=2x_DIELECTRIC
?
MCP_PE0_REFCLK
C
MCP_PE1_REFCLK
CRT signal single-ended impedence varies by location:
- 37.5-ohm from MCP to first termination resistor.
- 50-ohm from first to second termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.
MCP_PE2_REFCLK
MCP_PE3_REFCLK
MCP_PEX_CLK_COMP
Digital Video Signal Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DP_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
LVDS_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
*
20 MIL
Y
20 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
*
=3x_DIELECTRIC
?
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
LVDS
B
*
=3x_DIELECTRIC
SATA Interface Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
?
SATA
*
=3x_DIELECTRIC
?
SATA_TERMP
*
8 MIL
?
8 15
C
15 29
15 29
15 31
15 31
15 33
15 33
15
8
8
8
8
8
8
8
?
LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.
NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.
DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max trace length: LVDS 10 inches, DP 8.5 inches.
8 15
SATA
TOP,BOTTOM
SATA intra-pair matching should be 1 ps.
Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R
MCP_SATA_TERMP
MCP_TMDS0_RSET
MCP_TMDS0_VPROBE
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_TERMP
MCP_SATA_TERMP
8
8
8 68
8 68
16 23
16 23
B
8 67
8 67
6 8 67
6 8 67
16 23
16 23
17 36
17 36
6 36
6 36
17 36
17 36
6 36
6 36
17 36
17 36
6 36
6 36
17 36
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Constraints 1
17 36
36
DRAWING NUMBER
36
Apple Inc.
17
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
102 OF 109
SHEET
74 OF 80
1
A
8
7
6
5
LPC Bus Constraints
4
3
2
1
MCP89 Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
LPC_AD
LPC_FRAME_L
LPC_RESET_L
LPC_55S
LPC_55S
LPC_55S
LPC
LPC
LPC
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC_55S
CLK_LPC_55S
CLK_LPC
CLK_LPC
CLK_LPC
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_MINI_P
USB_MINI_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
USB_T57_P
USB_T57_N
USB_EXTC_P
USB_EXTC_N
USB_SDCARD_P
USB_SDCARD_N
USB_WM_P
USB_WM_N
18 39 41
18 39 41
18 24
SPACING_RULE_SET
LAYER
WEIGHT
LPC
*
=1.5x_DIELECTRIC
?
CLK_LPC
*
=2x_DIELECTRIC
?
18 24
24 39
24 41
D
USB_EXTA
USB 2.0 Interface Constraints
USB_MINI
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
USB_EXTD
MCP_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
*
=2x_DIELECTRIC
USB_BT
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
USB
USB_CAMERA
?
USB
TOP,BOTTOM
=4x_DIELECTRIC
?
USB_TPAD
USB_IR
SMBus Interface Constraints
USB_EXTB
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
USB_T57
SMB_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_EXTC
WEIGHT
USB_SDCARD
SMB
*
=2x_DIELECTRIC
?
USB_WM
C HD Audio Interface Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MCP_USB_RBIAS
DIFFPAIR NECK GAP
HDA_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
(SMBUS_SMC_MGMT_SCL)
(SMBUS_SMC_MGMT_SDA)
MAXIMUM NECK LENGTH
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB
SMB
SMB
SMB
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
17 37
D
17 37
37 79
37 79
8 17
8 17
8 17
8 17
17 29
17 29
17 29
17 29
17 47
17 47
17 38
17 38
17 37
17 37
6 38
6 38
8 17
8 17
17 30
17 30
8 17
8 17
17
C
12 18 42
12 18 42
18 42
18 42
SPACING_RULE_SET
LAYER
HDA_BIT_CLK
WEIGHT
HDA
*
=2x_DIELECTRIC
?
MCP_HDA_COMP
*
8 MIL
?
HDA_SYNC
HDA_RST_L
HDA_SDIN0
SIO Signal Constraints
HDA_SDOUT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
18 51
18
18 51
18
18
18 51
18 51
18 51
18
MCP_HDA_PULLDN_COMP
SPACING_RULE_SET
LAYER
WEIGHT
=1.5x_DIELECTRIC
?
MCP_SUS_CLK
CLK_SLOW_55S
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_CLK
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI
SPI
SPI
SPI
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_CS_L
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI
SPI
SPI
SPI
SPI_ALT_CLK
SPI_ALT_MOSI
SPI_ALT_MISO
SPI_ALT_CS_L
18
18 24
24 39
CLK_SLOW
*
SPI_MOSI
SPI Interface Constraints
SPI_MISO
SPI_CS0
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
B
SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=1.5x_DIELECTRIC
?
SPI
*
A
18 41
6 41
18 41
6 41
6 18 41
18 41
6 41
B
41 50
41 50
41 50
41 50
41
41
41
41
SYNC_MASTER=T27_MLB
PAGE TITLE
MCP Constraints 2
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
103 OF 109
SHEET
75 OF 80
1
A
8
7
6
5
MCP RGMII (Ethernet) Constraints
4
3
2
1
RGMII Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_MII_COMP
*
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
ENET_MII_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
ENET_MII_55S
MCP_BUF0_CLK
MCP_BUF0_CLK
MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_RXCLK
ENET_RXD_STRAP
ENET_RXD_STRAP
ENET_RXD
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL
ENET_TXCLK
ENET_TXD
ENET_TXD
ENET_TXD
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MII_55S
ENET_MII
ENET_RESET_L
SPACING_RULE_SET
WEIGHT
MCP_BUF0_CLK
LAYER
*
=3:1_SPACING
?
ENET_MII
*
12 MIL
?
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
17
17
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_MDI_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
8 17
D
8 17
8 17
8 17
8 17
SPACING_RULE_SET
LAYER
WEIGHT
25 MIL
?
ENET_MDI
*
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
24 31
SD Card Interface Constraints
Ethernet Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SD_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SD_INTERFACE
*
=3X_DIELECTRIC
?
ENET_MDI
NET_TYPE
PHYSICAL
SPACING
ENET_MDI_100D ENET_MDI
ENET_MDI_100D ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
31 32
31 32
SD Card Net Properties
C
SD_DATA
SD_DATA_R
SD_CLK
SD_CMD
NET_TYPE
SPACING
PHYSICAL
SD_55S
SD_55S
SD_55S
SD_INTERFACE
SD_INTERFACE
SD_INTERFACE
SD_D<4..0>
SDCONN_DATA<4..0>
BCM57765_CR_DATA<4>
SD_55S
SD_55S
SD_55S
SD_INTERFACE
SD_INTERFACE
SD_INTERFACE
SD_D<7..5>
SDCONN_DATA<7..5>
BCM57765_CR_DATA<7..5>
SD_55S
SD_55S
SD_55S
SD_INTERFACE
SD_INTERFACE
SD_INTERFACE
SD_CLK
SD_CLK_R
SDCONN_CLK
SD_55S
SD_55S
SD_55S
SD_INTERFACE
SD_INTERFACE
SD_INTERFACE
SD_CMD
SDCONN_CMD
BCM57765_CR_CMD
C
30
30 31
31
30
30 31
31
30
30
30 31
30
30 31
31
NOTE: SD_D<7..5> are different to support
BCM5764M/BCM57765 co-layout.
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
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REVISION
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A
8
7
6
5
FireWire Interface Constraints
4
3
2
1
FireWire Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
FW_P0_TPA
FW_100D
FW_TP
FW_P0_TPA
FW_100D
FW_TP
FW_P0_TPB
FW_100D
FW_TP
FW_P0_TPB
FW_100D
FW_TP
FW_P1_TPA
FW_100D
FW_TP
FW_P1_TPA
FW_100D
FW_TP
FW_P1_TPB
FW_100D
FW_TP
FW_P1_TPB
FW_100D
FW_TP
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
*
=3:1_SPACING
?
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
33 35
33 35
33 35
33 35
33 35
33 35
33 35
33 35
D
D
Port 2 Not Used
C
C
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
FireWire Constraints
DRAWING NUMBER
Apple Inc.
051-8563
R
CANNOT SYNC THIS PAGE FROM T27, FW CONSTRAINTS CHANGED TO 100OHM DIFF
8
7
6
5
4
3
2
SIZE
D
REVISION
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105 OF 109
SHEET
77 OF 80
1
A
8
7
6
5
4
3
2
1
SMC SMBus Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
SPACING
PHYSICAL
D
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
6 42
6 42
42
42
42
42
6 42
6 42
D
42
42
SMBus Charger Net Properties
NET_TYPE
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_P
CHGR_CSO_N
CHGR_CSO_R_P
CHGR_CSO_R_N
58
58
58
58
58
58
44 58
44 58
C
C
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
106 OF 109
SHEET
78 OF 80
1
A
8
7
6
5
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
SENSE_1TO1_55S
*
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
THERM_1TO1_55S
*
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
3
Misc Net Properties
DIFFPAIR NECK GAP
4
(PCIE_AP)
2
Power Net Properties
NET_TYPE
PHYSICAL
SPACING
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_LT1_P
USB_LT1_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_LT2_P
USB_LT2_N
ENET_MDI_100D
ENET_MDI_100D
ENETCONN
ENETCONN
ENETCONN_P<3..0>
ENETCONN_N<3..0>
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_HDD_D2R_RDRV_IN_P
SATA_HDD_D2R_RDRV_IN_N
SATA_HDD_R2D_RDRV_IN_P
SATA_HDD_R2D_RDRV_IN_N
SATA_HDD_D2R_RDRV_OUT_P
SATA_HDD_D2R_RDRV_OUT_N
SATA_HDD_R2D_RDRV_OUT_P
SATA_HDD_R2D_RDRV_OUT_N
SATA_HDD_D2R_NORDRV_P
SATA_HDD_D2R_NORDRV_N
SATA_HDD_R2D_NORDRV_P
SATA_HDD_R2D_NORDRV_N
CPUTHMSNS_D2
6 29
6 29
DIFFPAIR
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
SENSE
*
=2:1_SPACING
?
D
THERM
*
?
=2:1_SPACING
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_TPAD)
(USB_TPAD)
(USB_CAMERA)
(USB_CAMERA)
AUDIO
*
?
=2:1_SPACING
CPU_THERMD
37 75
37 75
MCPTHMSNS_D2
37
37
MCP_THMDIODE
47
47
SENSE_DIFFPAIR
6 29
6 29
6 29
6 29
SENSE_DIFFPAIR
37
37
SPACING_RULE_SET
LAYER
WEIGHT
ENETCONN
*
25 MILS
?
SPACING_RULE_SET
LAYER
WEIGHT
GND
*
=STANDARD
?
MEM_POWER
*
=STANDARD
?
32
SENSE_DIFFPAIR
32
36
36
6 36
SENSE_DIFFPAIR
6 36
SPACING_RULE_SET
LAYER
WEIGHT
GND_P2MM
*
0.20 MM
1000
PWR_P2MM
*
0.20 MM
1000
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
GND
*
GND_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_POWER
*
PWR_P2MM
MEM_CMD
GND
*
GND_P2MM
MEM_CMD
MEM_POWER
*
PWR_P2MM
C
MEM_CTRL
GND
*
GND_P2MM
MEM_DATA
GND
*
GND_P2MM
MEM_CTRL
MEM_POWER
*
PWR_P2MM
MEM_DATA
MEM_POWER
*
PWR_P2MM
MEM_DQS
GND
*
GND_P2MM
MEM_DQS
MEM_POWER
*
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_FSB
GND
*
GND_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
GND
*
GND_P2MM
*
GND_P2MM
GND
*
GND_P2MM
USB
GND
*
GND_P2MM
CLK_PCIE
SB_POWER
*
PWR_P2MM
CPU_COMP
GND
*
GND_P2MM
SATA
CPU_GTLREF
GND
*
GND_P2MM
CPU_VCCSENSE
GND
*
GND_P2MM
SATA
SB_POWER
*
PWR_P2MM
USB
SB_POWER
*
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
LVDS
GND
*
GND_P2MM
36
SENSE_DIFFPAIR
36
36
36
36
SENSE_DIFFPAIR
36
36
SENSE_DIFFPAIR
36
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MCP_THMDIODE_P
MCP_THMDIODE_N
ISNS_1V5_S3_P
ISNS_1V5_S3_N
ISNS_1V5_S3_R_P
ISNS_1V5_S3_R_N
ISNS_AIRPORT_P
ISNS_AIRPORT_N
ISNS_AIRPORT_R_P
ISNS_AIRPORT_R_N
ISNS_HDD_P
ISNS_HDD_N
ISNS_HDD_R_P
ISNS_HDD_R_N
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
ISNS_LCDBKLT_R_P
ISNS_LCDBKLT_R_N
ISNS_ODD_P
ISNS_ODD_N
ISNS_ODD_R_P
ISNS_ODD_R_N
ISNS_CPUVTT_P
ISNS_CPUVTT_N
MCPCORES0_VSEN_P
MCPCORES0_VSEN_N
MEM_POWER
PP1V5R1V35_S3
SB_POWER
SB_POWER
SB_POWER
GND
PP3V3_S5
PP3V3_S0
PP1V5_S0
GND
45
45
9 45
9 45
18 45
18 45
D
44
44
21 62
21 62
36
36
I277
36
36
36
36
6 7
C
6 7 65
6 7 65
6 7 65
36
Graphics Net Properties
GND
36
NET_TYPE
SPACING
PHYSICAL
PCIE
1
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
ENET_MDI
GND
*
GND_P2MM
(DP_EXT_ML)
B
(DP_EXT_AUX_CH)
Audio Net Properties
NET_TYPE
PHYSICAL
SPACING
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_CONN_A_CLK_P
LVDS_CONN_A_CLK_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_DATA_P<2..0>
LVDS_CONN_A_DATA_N<2..0>
LVDS_CONN_B_CLK_P
LVDS_CONN_B_CLK_N
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_DATA_P<2..0>
LVDS_CONN_B_DATA_N<2..0>
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_EXT_ML_P<3..0>
DP_EXT_ML_N<3..0>
DP_EXT_ML_C_P<3..0>
DP_EXT_ML_C_N<3..0>
DP_EXT_ML_F_P<3..0>
DP_EXT_ML_F_N<3..0>
DP_EXT_AUX_CH_C_P
DP_EXT_AUX_CH_C_N
DP_AUX_CH_SW_P
DP_AUX_CH_SW_N
6 67
6 67
NET_TYPE
PHYSICAL
SPACING
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUD_SPKRAMP_LIN_P
AUD_SPKRAMP_LIN_N
AUD_SPKRAMP_SUBIN_P
AUD_SPKRAMP_SUBIN_N
AUD_SPKRAMP_RIN_P
AUD_SPKRAMP_RIN_N
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
SSM2315L_P
SSM2315L_N
SSM2315S_P
SSM2315S_N
SSM2315R_P
SSM2315R_N
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
AUDIO
AUDIO
AUDIO
AUDIO
BI_MIC_P
BI_MIC_N
HS_MIC_P
HS_MIC_N
8 69
SPK_OUT
8 69
69
SPK_OUT
69
69
SPK_OUT
69
8 69
8 69
B
MCP Fanout Constraint Relaxations
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
0.09 MM
5.8 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.25 MM
250 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MEM_40S
*
OVERRIDE
OVERRIDE
MCP_DV_COMP
TOP
OVERRIDE
OVERRIDE
MCP_MEM_COMP
TOP
OVERRIDE
OVERRIDE
MCP_MII_COMP
TOP
OVERRIDE
OVERRIDE
MCP_USB_RBIAS
TOP
OVERRIDE
OVERRIDE
MCP_DV_COMP
*
OVERRIDE
OVERRIDE
A
SYNC_MASTER=T27_MLB
PAGE TITLE
K6/K69 Specific Constraints
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
108 OF 109
SHEET
79 OF 80
1
A
8
7
6
5
4
3
2
1
K6/K69 Board-Specific Physical & Spacing Constraints
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
15.2
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
DEFAULT
*
0.1 MM
?
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DEFAULT
*
Y
=50_OHM_SE
0.080 MM
12.7 MM
0 MM
0 MM
*
*
BGA
STANDARD
*
=DEFAULT
?
BGA_P1MM
*
0.1 MM
?
BGA_P2MM
*
Y
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
*
0.2 MM
?
*
BGA
BGA_P2MM
CLK_FSB
*
BGA
BGA_P2MM
*
0.3 MM
?
CLK_LPC
*
BGA
BGA_P2MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
SPACING_RULE_SET
LAYER
WEIGHT
TOP,BOTTOM
Y
1.5:1_SPACING
*
0.15 MM
?
2:1_SPACING
*
0.2 MM
?
2.5:1_SPACING
*
0.25 MM
?
3:1_SPACING
*
0.3 MM
?
4:1_SPACING
*
0.4 MM
?
SPACING_RULE_SET
LAYER
WEIGHT
0.105 MM
?
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_PCIE
*
BGA
BGA_P2MM
CLK_SLOW
*
BGA
BGA_P2MM
FSB_DSTB
FSB_DSTB
BGA
BGA_P3MM
DIFFPAIR NECK GAP
D
55_OHM_SE
BGA
D
MEM_40S
BGA_P3MM
PHYSICAL_RULE_SET
BGA_P1MM
MEM_CLK
STANDARD
AREA_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
SPACING_RULE_SET
0.090 MM
0.090 MM
55_OHM_SE
*
Y
LAYER
ALLOW ROUTE
ON LAYER?
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
Y
0.115 MM
0.115 MM
50_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.100 MM
1.5X_DIELECTRIC TOP,BOTTOM
40_OHM_SE
*
Y
0.126 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
27P4_OHM_SE
*
Y
0.222 MM
0.222 MM
2X_DIELECTRIC
TOP,BOTTOM
0.140 MM
?
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
?
5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
?
1.5X_DIELECTRIC
*
0.095 MM
?
2X_DIELECTRIC
*
0.126 MM
?
3X_DIELECTRIC
*
0.189 MM
?
4X_DIELECTRIC
*
0.252 MM
?
5X_DIELECTRIC
*
0.315 MM
?
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
C
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.151 MM
0.109 MM
=STANDARD
0.224 MM
0.090 MM
C
0.200 MM
0.200 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.095 MM
0.234 MM
0.234 MM
0.112 MM
0.112 MM
0.220 MM
0.220 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
Y
0.075 MM
0.075 MM
0.244 MM
0.244 MM
100_OHM_DIFF
TOP,BOTTOM
Y
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
110_OHM_DIFF
TOP,BOTTOM
Y
0.077 MM
0.077 MM
0.330 MM
0.330 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
70_OHM_DIFF
TOP,BOTTOM
Y
0.185 MM
0.185 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
90_OHM_DIFF
Y
0.095 MM
90_OHM_DIFF
TOP,BOTTOM
Y
PHYSICAL_RULE_SET
LAYER
100_OHM_DIFF
B
B
A
SYNC_MASTER=T27_MLB
PAGE TITLE
K6/K69 PCB Rule Definitions
DRAWING NUMBER
Apple Inc.
051-8563
R
8
7
6
5
4
3
2
SIZE
D
REVISION
A.13.0
BRANCH
PAGE
109 OF 109
SHEET
80 OF 80
1
A

schem,mlb_ldo,k6

Transcription

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