xCORE-200 USB sliceKIT Hardware Manual

Transcription

Document Number: XM009855A
Publication Date: 2016/3/24
XMOS © 2016, All Rights Reserved.
SYNOPSIS
This document pertains to the 1V1 revision of the XP-SKC-XU216 sliceKIT Core Board.
XM009855A
2/31
3/31
Table of Contents
1 Overview
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
sliceKIT System Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Slot naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Core Board
2.1
Power Supply . . . . . . . . . . . . . . . . . . . .
2.2
Debug . . . . . . . . . . . . . . . . . . . . . . . .
2.3
XU216 Device Boot Procedure . . . . . . . . . . .
2.4
xCONNECT Links . . . . . . . . . . . . . . . . . .
2.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Clocking . . . . . . . . . . . . . . . . . . . . . . .
2.7
Loop-back Port . . . . . . . . . . . . . . . . . . .
2.8
Type-3/ Type-7 Slot . . . . . . . . . . . . . . . . .
2.9
Slot Pinouts and Testpoints . . . . . . . . . . . .
2.9.1 USB SLOT TOP SIDE PINOUT TABLE . . . . .
2.9.2 USB SLOT BOTTOM SIDE PINOUT TABLE . .
2.9.3 Type-3 SLOT TOP SIDE PINOUT TABLE . . .
2.9.4 Type-3 SLOT BOTTOM SIDE PINOUT TABLE
2.9.11 System Services Slot Signals . . . . . . . . .
2.10 xCORE-200 USB sliceKIT schematics . . . . . . .
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3 USB sliceCARDs
26
3.1
XU216 USB Slice Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2
USB AB Slice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 New Designs Based on sliceKIT
4.1
USB . . . . . . . . . . . . .
4.1.1 USB Device (B) . . . .
4.1.2 USB Host (A) . . . . .
4.1.3 Multi Mode USB . . .
4.2
Portmap . . . . . . . . . .
4.3
QSPI Routing Control . . .
4.4
Debug Interface . . . . . .
XM009855A
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29
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1 Overview
IN THIS CHAPTER
· Introduction
· sliceKIT System Layout
1.1
Introduction
This document covers the hardware design of the xCORE-200 USB sliceKIT Core
Board (XP-SKC-XU216).
The Core Board contains a fully pinned out 500MHz, 16-core XU216-512-FB236
device, with its GPIOs connected to three expansion connectors (termed Slots) to
interface with expansion cards (called sliceCARDs) that plug into the slots. The
Core Board has specialist Slot, for USB connectivity. The Core Board also contains
all circuitry necessary for operating and debugging the XMOS system. Multiple
sliceKIT Core Boards can be interconnected to form a multi XMOS device system
with bi-directional 5-bit xCONNECT Links being present between the boards. The
xCORE-200 USB Core Board is only capable of being the start of a chain i.e. the
chain master.
Type 4
testpoints
Type 4
slot
12V
input
Type 3/7
testpoints
Type 3/7
slot
J14
J12
xCORE-200
XU216
USB
slot
Figure 1:
xCORE-200
USB sliceKIT
Core board
XM009855A
J5
J16
Type 6
testpoints
Type 6
slot
xSYS
1.2
5/31
sliceKIT System Layout
Figure 1 shows the layout of the xCORE-200 USB Core Board. Each of the four slots
has a specific numbering - 3/7, 4, 6 and USB (labelled U), printed on the Core Board
silkscreen. The slot 4 contains 24 xCORE GPIO; the slots 3/7 , 6 contain 20 xCORE
GPIO. The USB Slice slot contains 8 xCORE GPIO along with the USB differential data
signals.
All Slots are 36 pin PCI express style connectors in either socket or edge finger
(plug) types.
3/7 and 4 Slots are pinned out from Tile 1 of the XU216 and the USB (U) and 6 Slots
from Tile 0.
1.2.1
Slot naming conventions
xCORE-200 devices like the XU216-512-FB236 used on the xCORE-200 USB sliceKIT
Core Board, include dedicated 32 bit ports in addition to the 1, 4, 8 and 16 bit ports
supported on XS1 sliceKIT Core Boards. To support the additional ports, a numeric
naming convention is used on xCORE-200 sliceKIT Core Boards instead of the
symbols used previously. The following table shows the new and old conventions.
XM009855A
XS1 Symbol
xCORE-200 Number
Description
U
A
STAR
TRIANGLE
SQUARE
CIRCLE
DIAMOND
–New–
–New–
U
A
1
2
3
4
5
6
7
USB
Analog
1, 4, 8, 16-bit
1, 4, 8, 16-bit
1, 4, 8, 16-bit
1, 4, 8, 16-bit
1, 4, 8, 16-bit
32-bit ports
32-bit ports
ports
ports
ports
ports
ports
2 Core Board
IN THIS CHAPTER
· Power Supply
· Debug
· XU216 Device Boot Procedure
· xCONNECT Links
· Reset
· Clocking
· Loop-back Port
· Type-3/ Type-7 Slot
· Slot Pinouts and Testpoints
· xCORE-200 USB sliceKIT schematics
The xCORE-200 USB Core Board includes the xU216-512-FB236 device and support
circuitry. The device GPIO are connected to the Slots, with test points available for
each signal.
The Core Board is powered by a 12V external power supply, provided with the kit.
An xTAG debug adapter can be connected to the xSYS connector, providing a
debug link from a USB host.
2.1
Power Supply
Power input to the sliceKIT Core Board is via a standard barrel jack connector. A
standard 12V external power supply should be used to power the board. Each Core
Board requires its own 12V supply. This input supply is used to generate the main
5V board supply via a DC-DC converter.
The 5V board supply is fed to all the GPIO Slot connectors as well as powering the
Core Board itself. A 3V3 I/O supply is generated by a DC-DC converter from the 5V
main supply, and a 3V3 analogue supply is generated by an LDO converter from
the 5V main supply.
The Core Board provides 3V3 and 5V at 0.25A to each slot for a total of approximately 2W per slice.
The 12V supply is provided to the USB Slot connector for local conversion for USB
charger supplies.
XM009855A
2.2
7/31
Debug
Debug of the system is via the xSYS Connector. The JTAG signals are connected as
shown below.
XTAG
TCK
TMS
TDI
0
TDO
1
TCK
TMS
TDI
PRSNT_N
TDI
TDO
TCK, TMS
SQUARE SLOT
U16
TDO
1
0
Figure 2:
JTAG Chain
A presence detect signal is present on both the Type-3 Slot connector to allow
detection of a connected board and subsequent automatic switching of the JTAG
chain. In a system of multiple Core Boards, the Master is the source of the JTAG
chain so the system can only be debugged from the master. Other boards see no
devices in the JTAG chain.
The use of xSCOPE is covered in the xCONNECT Links section (2.6).
2.3
XU216 Device Boot Procedure
Master Core Boards boot from the QSPI flash, while slave Core Boards boot from
xCONNECT link XL0 from the next connected Core Board.
To allow re-use of the QSPI boot pins (ports 1B, 1C, 4B) as signal GPIO pins for
the Type-6 slot, Jumper J12 and a latched bus switch is used which connects the
xCORE QSPI pins to either the QSPI Flash or to the sliceCARD Slots. The switch
is controlled by X0D30 and X0D31. Once the device has booted X0D31 is used
to enable or disable the QSPI interface, X0D30 should then transition from low to
high to latch the selection. The QSPI selection state is then maintained until the
system is reset.
Once this sequence is completed the selection has been latched, therefore X0D30
and X0D31 will be available in the J5 header.
XM009855A
8/31
Reset
D30 = 0
D31 = X
SPI = EN
BOOT
D30 = 0
D31 = X
SPI = EN
Figure 3:
QSPI Select
Flow Diagram
Disable
Enable
D30 =_^
D31 = 1
SPI = DIS
D30 =_^
D31 = 0
SPI = EN
D30, D31, D0,
D4, D5,D6,D7 and D10
available
D30 and D31 available
D0, D4, D5, D6,D7 &
D10
used by SPI
If the SPI is not disabled, sliceCARDs in the Type-6 slot may not function as
expected. If there are no sliceCARDs in the Type-6 slot, then it does not matter
whether the SPI has been disabled or not. Therefore, applications which require
runtime access to the QSPI flash should either leave the Type-6 slot unpopulated or
check to ensure that the Card which is in there will be unaffected by the operation
of the Flash. The applications which reuse the QSPI GPIOs should remove the
Jumper - J12 during flashing of the device for proper operation.
The xTAG debug adapter system can use the boot mode select signal to force all
devices in the chain (master and slave Core Boards) to boot from JTAG (don’t boot)
for debug purposes.
If not in this mode, the devices will boot from SPI or xCONNECT link as appropriate.
2.4
xCONNECT Links
The Type-7 slot contains two 5-bit xCONNECT Links, XL1 and XL2, which can be
used for chaining sliceKIT Core Boards together.
2.5
Reset
The whole system is held in reset until all power supplies are stable, and reset is
connected to all sliceCARDs so any circuitry on them can be reset. It also indicates
to the sliceCARDs that their power input is stable. The reset from the xTAG debug
adapter resets the whole system, if required for debugging.
XM009855A
2.6
9/31
Clocking
There are two clock sources available on the Core Board. One provides a 25MHz
system clock, the other is a 24MHz clock provided to the XU216 device.
The system clock from a Master Core Board is fed automatically to all of the slave
Core Boards so the whole system will operate synchronously.
The system clock is also fed to each of the sliceCARD slots.
2.7
Loop-back Port
Jumper J16 can be used to enable a loop-back between a 1-bit port on Tile0
and Tile1. With the loop-back enabled port X0D39 is connected to X1D12, and
disconnected from the Header J5. With the loop-back disabled X0D39 is connected
to the Header J5.
2.8
Type-3/ Type-7 Slot
The GPIOs connected to the Type-3 slot can be changed to an alternative Type-7
configuration by setting the jumper J14. For Type-3 slot GPIO J14 should be
connected between Pin 1---Pin 2 ‘; for “ Type-7 “ GPIOs J14 should be connected
between “Pin 2—Pin 3‘.
The Type-7 configuration exposes 20 bits of the 32-bit port, which can be useful
for applications requiring a wide bus; the Type-3 configuration exposes more 1-bit
ports.
2.9
Slot Pinouts and Testpoints
The signal assignments for the connectors on the Core Board and sliceCARDs can
be seen in the following tables, with the related testpoints.
XM009855A
2.9.1
XM009855A
USB SLOT TOP SIDE PINOUT TABLE
PCIE A (TOP)
SIGNAL
FUNCTION
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
KEY
A12
A13
A14
A15
A16
A17
A18
GND
GND
USB DN
USB DP
GND
GND
X0D33
X0D32
GND
X0D27
X0D26
KEY
3V3
GND
5V
5V
GND
12V
12V
POWER SUPPLY GROUND
POWER SUPPLY GROUND
USB DATA NEGATIVE
USB DATA POSITIVE
POWER SUPPLY GROUND
POWER SUPPLY GROUND
P4E3 P8C7 P16B7
P4E2 P8C6 P16B6
POWER SUPPLY GROUND
P4E1 P8C1 P16B1
P4E0 P8C0 P16B0
MECHANICAL KEY
3.3V POWER SUPPLY
POWER SUPPLY GROUND
5.0V POWER SUPPLY
5.0V POWER SUPPLY
POWER SUPPLY GROUND
12.0V POWER SUPPLY
12.0V POWER SUPPLY
10/31
2.9.2
XM009855A
USB SLOT BOTTOM SIDE PINOUT TABLE
PCIE B (BOT)
SIGNAL
FUNCTION
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
KEY
B12
B13
B14
B15
B16
B17
B18
GND
GND
GND
GND
GND
GND
NC
X0D35
X0D36
X0D0
X0D11
KEY
RESET
GND
VBUS
VBUS
GND
12V
12V
POWER SUPPLY GROUND
POWER SUPPLY GROUND
POWER SUPPLY GROUND
POWER SUPPLY GROUND
POWER SUPPLY GROUND
POWER SUPPLY GROUND
NOT CONNECTED
P1L0
P1M0 P8D0 P16B8
P1A0
P1D0
MECHANICAL KEY
xCORE-200 RESET
POWER SUPPLY GROUND
VBUS POWER SUPPLY IN
VBUS POWER SUPPLY IN
POWER SUPPLY GROUND
12.0V POWER SUPPLY
12.0V POWER SUPPLY
11/31
2.9.3
12/31
Type-3 SLOT TOP SIDE PINOUT TABLE
PCIE B (TOP)
SIGNAL
FUNCTION
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
KEY
B12
B13
B14
B15
B16
B17
B18
DEBUG
TCK
GND
TDI
3V3
X1D2
X1D3
GND
X1D4
X1D10
X1D5
KEY
X1D14
X1D15
CLK
X1D22
GND
X1D16
X1D17
xSYS DEBUG SIGNAL
xSYS TCK SIGNAL
POWER SUPPLY GROUND
xSYS TDI SIGNAL
POWER SUPPLY 3.3V
P4A0 P8A0 P16A0
P4A1 P8A1 P16A1
POWER SUPPLY GROUND
P4B0
P8A2 P16A2
P1C0
P4B1
P8A3 P16A3
MECHANICAL KEY
P4C0 P8B0
P16A8
P4C1 P8B1
P16A9
MAIN SYSTEM CLOCK
P1G0
POWER SUPPLY GROUND
P4D0 P8B2
P16A10
P4D1 P8B3
P16A11
J13
Figure 4:
J13: Type-3
Slot
Testpoints
XM009855A
X1D2
X1D3
X1D4
X1D10
X1D5
X1D14
X1D15
X1D22
X1D16
X1D17
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
NA
X1D8
X1D9
X1D1
X1D6
X1D7
X1D20
X1D21
X1D13
X1D18
X1D19
P32A20
P32A21
P32A22
P32A23
P32A28
P32A29
2.9.4
13/31
Type-3 SLOT BOTTOM SIDE PINOUT TABLE
PCIE A (BOT)
SIGNAL
FUNCTION
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
KEY
A12
A13
A14
A15
A16
A17
A18
NC
5V
TMS
TDO
PRSNT
X1D8
X1D9
X1D1
X1D6
GND
X1D7
KEY
X1D20
X1D21
GND
X1D13
RST_N
X1D18
X1D19
NOT CONNECTEDNAL
POWER SUPPLY 5V
xSYS TMS SIGNAL
xSYS TDO SIGNAL
SYSTEM PRESENT SIGNAL (ACTIVE
P4A2 P8A6 P16A6
P4A3 P8A7 P16A7
P1B0
P4B2
P8A4 P16A4
POWER SUPPLY GROUND
P4B3
P8A5 P16A5
MECHANICAL KEY
P4C2 P8B6
P16A14
P4C3 P8B7
P16A15
POWER SUPPLY GROUND
P1F0
xCORE-200 RESET (ACTIVE LOW)
P4D2 P8B4
P16A12
P4D3 P8B5
P16A13
J13
Figure 5:
J13: Type-3
Slot
Testpoints
XM009855A
X1D2
X1D3
X1D4
X1D10
X1D5
X1D14
X1D15
X1D22
X1D16
X1D17
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
NA
X1D8
X1D9
X1D1
X1D6
X1D7
X1D20
X1D21
X1D13
X1D18
X1D19
LOW)
P32A26
P32A27
P32A24
P32A25
P32A30
P32A31
2.9.5
14/31
PCIE B (TOP)
SIGNAL
FUNCTION
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
KEY
B12
B13
B14
B15
B16
B17
B18
DEBUG
TCK
GND
TDI
3V3
X1D57
X1D56
GND
X1D55
X1D49
X1D54
KEY
X1D69
X1D68
CLK
X1D61
GND
X1D67
X1D66
xSYS DEBUG SIGNAL
xSYS TCK SIGNAL
POWER SUPPLY GROUND
xSYS TDI SIGNAL
POWER SUPPLY 3.3V
P32A8
P32A7
POWER SUPPLY GROUND
P32A6
P32A0
P32A5
MECHANICAL KEY
P32A18
P32A17
MAIN SYSTEM CLOCK
P32A10
POWER SUPPLY GROUND
P32A16
P32A17
J8
Figure 6:
J8: Type-7
Slot
Testpoints
XM009855A
X1D57
X1D56
X1D55
X1D49
X1D54
X1D69
X1D68
X1D61
X1D67
X1D66
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
NA
X1D51
X1D50
X1D58
X1D53
X1D52
X1D63
X1D62
X1D70
X1D65
X1D64
2.9.6
15/31
PCIE A (BOT)
SIGNAL
FUNCTION
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
KEY
A12
A13
A14
A15
A16
A17
A18
NC
5V
TMS
TDO
PRSNT
X1D51
X1D50
X1D58
X1D53
GND
X1D52
KEY
X1D63
X1D62
GND
X1D70
RST_N
X1D65
X1D64
NOT CONNECTED
POWER SUPPLY 5V
xSYS TMS SIGNAL
xSYS TDO SIGNAL
SYSTEM PRESENT SIGNAL (ACTIVE LOW)
P32A2
P32A1
P32A9
P32A4
POWER SUPPLY GROUND
P32A3
MECHANICAL KEY
P32A12
P32A11
POWER SUPPLY GROUND
P32A19
P32A14
P32A13
J8
Figure 7:
J8: Type-7
Slot
Testpoints
XM009855A
X1D57
X1D56
X1D55
X1D49
X1D54
X1D69
X1D68
X1D61
X1D67
X1D66
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
NA
X1D51
X1D50
X1D58
X1D53
X1D52
X1D63
X1D62
X1D70
X1D65
X1D64
2.9.7
16/31
PCIE B (TOP)
SIGNAL
FUNCTION
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
KEY
B12
B13
B14
B15
B16
B17
B18
NC
X1D0
GND
X1D11
3V3
X1D26
X1D27
GND
X1D28
X1D34
X1D29
KEY
X1D36
X1D37
CLK
X1D24
GND
X1D38
X1D39
NOT CONNECTED
P1A0
POWER SUPPLY GROUND
P1D0
POWER SUPPLY 3.3V
P4E0 P8C0 P16B0
P4E1 P8C1 P16B1
POWER SUPPLY GROUND
P4F0 P8C2 P16B2
P1K0
P4F1 P8C3 P16B3
MECHANICAL KEY
P1M0
P8D0 P16B8
P1N0
P8D1 P16B9
MAIN SYSTEM CLOCK
P1I0
POWER SUPPLY GROUND
P1O0
P8D2 P16B10
P1P0
P8D3 P16B11
J9
Figure 8:
J9: Type-4
Slot
Testpoints
XM009855A
X1D0
X1D11
X1D26
X1D27
X1D28
X1D34
X1D29
X1D36
X1D37
X1D24
X1D38
X1D39
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
NA
X1D12
X1D23
X1D32
X1D33
X1D25
X1D30
X1D31
X1D42
X1D43
X1D35
X1D40
X1D41
2.9.8
17/31
PCIE A (BOT)
SIGNAL
FUNCTION
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
KEY
A12
A13
A14
A15
A16
A17
A18
NC
5V
X1D12
X1D23
GND
X1D32
X1D33
X1D25
X1D30
GND
X1D31
KEY
X1D42
X1D43
GND
X1D35
RST_N
X1D40
X1D41
NOT CONNECTED
POWER SUPPLY 5V
P1E0
P1H0
POWER SUPPLY GROUND
P4E2 P8C6 P16B6
P4E3 P8C7 P16B7
P1J0
P4F2 P8C4 P16B4
POWER SUPPLY GROUND
P4F3 P8C5 P16B5
MECHANICAL KEY
P8D6 P16B14
P8D7 P16B15
POWER SUPPLY GROUND
P1L0
P8D4 P16B12
P8D5 P16B13
J9
Figure 9:
J9: Type-4
Slot
Testpoints
XM009855A
X1D0
X1D11
X1D26
X1D27
X1D28
X1D34
X1D29
X1D36
X1D37
X1D24
X1D38
X1D39
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
NA
X1D12
X1D23
X1D32
X1D33
X1D25
X1D30
X1D31
X1D42
X1D43
X1D35
X1D40
X1D41
2.9.9
18/31
PCIE B (TOP)
SIGNAL
FUNCTION
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
KEY
B12
B13
B14
B15
B16
B17
B18
NC
NC
GND
NC
3V3
X0D2
X0D3
GND
X0D4_EXT
X0D10EXT
X0D5_EXT
KEY
X0D14
X0D15
CLK
X0D38
GND
X0D16
X0D17
NOT CONNECTED
NOT CONNECTED
POWER SUPPLY GROUND
NOT CONNECTED
POWER SUPPLY 3.3V
P4A0 P8A0 P16A0
P4A1 P8A1 P16A1
POWER SUPPLY GROUND
P4B0
P8A2 P16A2
P1C0
P4B1
P8A3 P16A3
MECHANICAL KEY
P4C0 P8B0
P16A8
P4C1 P8B1
P16A9
MAIN SYSTEM CLOCK
P1O0
P8D2 P16B10
POWER SUPPLY GROUND
P4D0 P8B2
P16A10
P4D1 P8B3
P16A11
J4
Figure 10:
J4: Type-6
Slot
Testpoints
X0D2
X0D3
X0D4_E XT
X0D10_E XT
X0D5_E XT
X0D14
X0D15
X0D38
X0D16
X0D17
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
X0D8
X0D9
X0D1_E XT
X0D6_E XT
X0D7_E XT
X0D20
X0D21
X0D37
X0D18
X0D19
NA
J11
Figure 11:
J11: Type-6
Slot
Testpoints
XM009855A
X0D50
X0D63
X0D62
X0D58
X0D53
X0D52
X0D51
X0D70
X0D64
X0D65
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
NA
X0D57
X0D56
X0D61
X0D54
X0D55
X0D68
X0D69
X0D49
X0D66
X0D67
P32A20
P32A21
P32A22
P32A23
P32A28
P32A29
2.9.10
19/31
PCIE A (BOT)
SIGNAL
FUNCTION
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
KEY
A12
A13
A14
A15
A16
A17
A18
NC
5V
NC
NC
GND
X0D8
X0D9
X0D1_EXT
X0D6_EXT
GND
X0D7_EXT
KEY
X0D20
X0D21
GND
X0D37
RST_N
X0D18
X0D19
NOT CONNECTED
POWER SUPPLY 5V
NOT CONNECTED
NOT CONNECTED
POWER SUPPLY GROUND
P4A2 P8A6 P16A6
P4A3 P8A7 P16A7
P1B0
P4B2
P8A4 P16A4
POWER SUPPLY GROUND
P4B3
P8A5 P16A5
MECHANICAL KEY
P4C2 P8B6
P16A14
P4C3 P8B7
P16A15
POWER SUPPLY GROUND
P1N0
P8D0 P16B8
P4D2 P8B4
P16A12
P4D3 P8B5
P16A13
J4
Figure 12:
J4: Type-6
Slot
Testpoints
X0D2
X0D3
X0D4_E XT
X0D10_E XT
X0D5_E XT
X0D14
X0D15
X0D38
X0D16
X0D17
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
X0D8
X0D9
X0D1_E XT
X0D6_E XT
X0D7_E XT
X0D20
X0D21
X0D37
X0D18
X0D19
NA
J11
Figure 13:
J11: Type-6
Slot
Testpoints
XM009855A
X0D50
X0D63
X0D62
X0D58
X0D53
X0D52
X0D51
X0D70
X0D64
X0D65
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
NA
X0D57
X0D56
X0D61
X0D54
X0D55
X0D68
X0D69
X0D49
X0D66
X0D67
P32A26
P32A27
P32A24
P32A25
P32A30
P32A31
2.9.11
20/31
System Services Slot Signals
On all Slots, TDO is always out of the sliceKIT Core Board, TDI is always in to the
Core Board.
MSEL, TCK, TMS, RST_N are all inputs to the Core Board from the xSYS Connector
and outputs from the Core Board on the Type-3 Slot.
DEBUG is bidirectional. PRSNT_N is used on the Type-3 Slot to detect another Core
Board is connected. This signal is used to switch the JTAG chain signals.
CLK and RST_N are output from all Slots.
XM009855A
PIR201
PIR202
PIR1 02 PIR1202
PIR1302
3V3
PIR601 COR11PIR1 01 COR12PIR1201 COR13PIR1301
PIR602
COPROD7
PROD7
JUMPER
GND
100N
PIR3102
3V3
COR31PIR3101
COR6
PIU10 3
1
A2
3
6
PIU506
TCK
TMS
3A
2A
1A
PIR501
PIR502
3V3
GND
4
GNDPIU504
2
3YPIU502
5
2YPIU505
7
1YPIU507
8
VCCPIU508
2
GNDPIU202
4
Y2PIU204
6
Y1PIU206
5
VCCPIU205
3V3
X1D12
GND
OE_N
33R
PIR1002
BRD_RST_N
TMS_BUF
TCK_BUF
RST_N_OUT
DEBUG_N_OUT
33R
PIR902
COR9
R9
PIR901
3V3
3V3
USB_D_N
USB_D_P
X0D39
XS2_TDO
TD_RETURN
PIR2501
PIR2502
COU1C
U1C
V9
U12
P14
F7
A14
6
1
0
3V3
GND
2
GNDPIU402
COR23
4
R23
QPIU404 PIR2301
5
VCCPIU405
33R
PIR2302
A15
MODE0PIU10A15
B15
MODE1PIU10B15
C6
RST_NPIU10C6
A5
TCKPIU10A5
B5
TMSPIU10B5
B4
TDOPIU10B4
C4
TDIPIU10C4
C5
DEBUG_N PIU10C5
B6
TRST_NPIU10B6
TCK
TMS
TDO
BRD_RST_N
TDI
DEBUG_N_IN
TDO MUXING & LOGIC DECOUPLING
NC7SZ157
1
PIU401
I1
3
PIU403
I0
PIU406 S
COU4
U4
XS2_XU216-512-FB236
PIU10A14 NC
PIU10F7 NC
PIU10P14 NC
PIU10U12 NC
W9
PIU10W9 USB_RTUNE
A6
PIU10A6 CLK
U9
PIU10U9 USB_VBUS
U10
PIU10U10 USB_ID
V10
PIU10V10
USB_DP
PIU10V9 USB_DM
3V3
PIR302
COR25
43R2
COR3
R3
PRSNT_SLV_N
GND
PIR301
XS2_CLK
VBUS_IN
Cross Core IO Selection
4
BPIU904
5
VCCPIU905
SN74CBT1G125
GND
COR10
R10
PIR1001
GND
3
PIU903
1
PIU901
OE_N
A
COU9
U9
2
PIU902
4
BPIU704
5
VCCPIU705
SN74CBT1G125
3
PIU703
1
PIU701
COU7
U7
2
A
PIU702
GND
X0D39_EXT
JTAG/RESET/DEBUG BUFFERING
NC7NZ17
PIU503
1
PIU501
COU5
U5
3
PIU203
PIU201 A1
1K
COR5
R5
SN74LVC1G06DCKT
4
PIU1004
COU2
U2
NC7WZ07
GND
2
PIU1002
PIU10 5
COU10
U10
100N
PIC6502
100N
PIC6402
3V3
COC65
C65
PIC6501
COC64
C64
PIC6401
BRD_RST_N
DEBUG_N_IN
RST_N_IN
GND
10K
COR2
R2
Jumper 3 Pin
R6
PIR101
COC44
C44
PIC4 02
10K
1K
R12
1
PIJ1601
2
PIJ1602
3
PIJ1603
10K
PIC4 01
R13
COJ16
J16
R11
10K
PIR102
COR1
R1
10K
R31
5
3
3V3
10K
XM009855A
R25
Figure 14:
xCORE-200
USB sliceKIT
schematic (1
of 5)
10K
C16
33R
PIC1602
100N
100N
GND
PIC30 2
C30
3V3
PIR2102
C31
XS2_TDO
PIC3102
100N
PIC160 COC16 PIC30 1 COC30 PIC310 COC31
PIR2101
COR21
R21
USB_D_P
USB_D_N
TDO
RST_N_OUT
CLK_OUT2
XS2_TDO
TMS_BUF
TCK_BUF
DEBUG_N_OUT
RST_N_OUT
CLK_OUT0
CLK_OUT1
TDI
X1D12
Sheet 1 of 5
TOP
Sheet Name
XP-SKC-XU216.PrjPcb
Project Name
Copyright © XMOS Ltd 2012
XS2_CLK
CLK_OUT0
CLK_OUT1
CLK_OUT2
TDI
TMS
TCK
DEBUG_N_IN
BRD_RST_N
RST_N_IN
X0D39_EXT
X0D39
TD_RETURN
PRSNT_SLV_N
Date 27-08-2015
Size
A3
PWR
XP-SKC-XU216_Power.SchDoc
BRD_RST_N
POR
XS2_CLK
CLK_OUT0
CLK_OUT1
CLK_OUT2
TDI
TMS
TCK
DEBUG_N
BOARD_RST_N
RST_N_IN
X0D39_EXT
X0D39
Clock
XP-SKC-XU216_Clock.SchDoc
USB_D_P
USB_D_N
TDO
RST_N_OUT
CLK_OUT0
X1D12
PRSNT_SLV_N
Tile0
XP-SKC-XU216_TILE0.SchDoc
TDO
TMS
TCK
DEBUG_N
RST_N_OUT
CLK_OUT0
CLK_OUT1
Tile1
XP-SKC-XU216_TILE1.SchDoc
Rev
1V1
2.10
3V3
21/31
xCORE-200 USB sliceKIT schematics
0R1
100N
100N
COC35
C35
3V3_IO
C22
3V3_IO
GND
PIC3501
PIC3502
PIR2702
C3
U1D
C4
C5
C78
XS2_XU216-512-FB236
B13 NC
PIU10B13
PIU10B14
PIU10C13
PIU10C14
C14
NC
C13 NC
B14
NC
A2
PIU10A2 VDDIOL
A3
PIU10A3
VDDIOL
B2
PIU10B2
VDDIOL
B3
PIU10B3 VDDIOL
C3
PIU10C3
VDDIOL
V3
PIU10V3
VDDIOL
W2
PIU10W2 VDDIOL
V2
PIU10V2 VDDIOL
B18
PIU10B18
VDDIOR
B19 VDDIOR
PIU10B19
A18
PIU10A18 VDDIOR
V17
PIU10V17 VDDIOR
V18
PIU10V18
VDDIOR
W17 VDDIOR
PIU10W17
W18
PIU10W18 VDDIOR
PIU10F12
F12
VDD
F8
PIU10F8
VDD
F9
PIU10F9 VDD
G14 VDD
PIU10G14
G6
PIU10G6
H14 VDD
PIU10H14 VDD
H6
PIU10H6 VDD
J14
PIU10J14
VDD
J6
PIU10J6
K14 VDD
PIU10K14 VDD
K6
PIU10K6
VDD
L14
PIU10L14
VDD
L6
PIU10L6
M14 VDD
PIU10M14
VDD
M6
PIU10M6
N14 VDD
PIU10N14
VDD
N6
PIU10N6 VDD
P11
PIU10P11
VDD
P12
PIU10P12
VDD
P13
PIU10P13 VDD
P6
PIU10P6 VDD
P7
PIU10P7
VDD
P8
PIU10P8
VDD
F11
PIU10F11
VDD
C79
1U
1U
GND
C19
C18
100N
1V0_CORE
100N
C7
100N
C8
100N
C9
100N
C10
100N
COFB1
100N
PIC7201
PIC720
PIC6301
PIC6302
5V
10N
C20
C21
PIC3602
GND
47U
PIC3702
47U
100N
GND
PIC4602
PIC4701
PIC4702
100N
100N
100N
COC46
COC47
C46
C47
3V3
100N
PIC4601
C36
C37
PIC3601COC36
PIC3701 COC37
GND
100N
10U
3V3
C6
C38
C12
100N
100N
C48
100N
C32
100N
100N
C33
100N
PIC4801 COC48PIC3201 COC32PIC3 01COC33
PIC4802 PIC320
PIC3 02
100N
G2
X1D49
G3
X1D50
H3 X1D51
H2
PIU10H2 X1D52
H1
PIU10H1 X1D53
J1
PIU10J1
X1D54
J2 X1D55
PIU10J2
J3
PIU10J3 X1D56
K3 X1D57
PIU10K3
K2
PIU10K2
X1D58
L3
PIU10L3
X1D61
X1D49
X1D50
X1D51
X1D52
X1D53
X1D54
X1D55
X1D56
X1D57
X1D58
X1D61
X1D62
X1D63
X1D64
X1D65
X1D66
X1D67
X1D68
X1D69
X1D70
C52
C53
1V0_CORE
C54
C55
XS2_XU216-512-FB236
PIU10M3
M3 X1D66
N2
PIU10N2 X1D67
N3
PIU10N3 X1D68
P2
PIU10P2
X1D69
P1 X1D70
PIU10P1
M2
PIU10M2
X1D65
PIU10M1
PIU10L1
PIU10L2
L2 X1D62
L1
X1D63
M1 X1D64
PIU10H3
PIU10G2
PIU10G3
F1
PIU10F1 X1D34
F2
PIU10F2
X1D35
F3
PIU10F3
X1D36
P3
PIU10P3 X1D37
R1
PIU10R1
X1D38
R2
PIU10R2
X1D39
COU1B
COU1D
U1B
F19
X1D00
E19
PIU10E19
X1D01
T17
PIU10T17 X1D02
R17 X1D03
PIU10R17
T18
PIU10T18
R18 X1D04
PIU10R18 X1D05
R19
PIU10R19 X1D06
P17
PIU10P17
X1D07
F17
PIU10F17
F18 X1D08
PIU10F18 X1D09
C7
PIU10C7
X1D10
C8
PIU10C8
X1D11
U7
PIU10U7
W8 X1D12
PIU10W8
X1D13
V12
PIU10V12
W12 X1D14
PIU10W12
X1D15
T2
PIU10T2 X1D16
R3
PIU10R3
X1D17
T3
PIU10T3
X1D18
U3
PIU10U3 X1D19
W11
PIU10W11 X1D20
V11
PIU10V11
X1D21
V1
PIU10V1
X1D22
W3
PIU10W3 X1D23
U13
PIU10U13 X1D24
V13
PIU10V13
X1D25
PIU10F19
X1D34
X1D35
X1D36
X1D37
X1D38
X1D39
X1D0
X1D1
X1D2
X1D3
X1D4
X1D5
X1D6
X1D7
X1D8
X1D9
X1D10
X1D11
X1D12
X1D13
X1D14
X1D15
X1D16
X1D17
X1D18
X1D19
X1D20
X1D21
X1D22
X1D23
X1D24
X1D25
B10
X1D26
C10
X1D27PIU10C10
B9
X1D28PIU10B9
A9
X1D29PIU10A9
C9
X1D30PIU10C9
A8
X1D31PIU10A8
B8
X1D32PIU10B8
B7
X1D33PIU10B7
C12
X1D40PIU10C12
A11
X1D41PIU10A11
B11
X1D42PIU10B11
C11
X1D43PIU10C11
PIU10B10
C13
100N
C14
C15
100N
GND
100N
C42
47U
47U
100N
1U
C67
1U
C68
C70
10N
C71
10N
10N
GND
1U
1U
1U
22U
C74
GND
22U
C73
1V0_CORE
GND
10N
C75
10N
C76
10N
22U
22U
PIC6701COC67
PIC6801COC68
PIC6901 COC69
PIC70 1 COC70
PIC710 COC71PIC7301 COC73
PIC7401 COC74
PIC7501 COC75
PIC7601COC76
PIC6702 PIC6802 PIC6902 PIC70 2 PIC7102
PIC7302 PIC7402 PIC7502 PIC7602
C69
100N
1V0_CORE
100N
PIC6201
PIC620
COC58
COC60
C58
C60 COC61
C61 COC62
C62
PIC610
PIC6102
10N
10N
1V0_CORE
C51
C50
10N
PIR40 1
PIR40 2
X1D26
X1D27
X1D28
X1D29
X1D30
X1D31
X1D32
X1D33
X1D40
X1D41
X1D42
X1D43
Jumper 3 Pin
1
2
PIJ1402
3
PIJ1403
PIJ1401
J14
COJ14
JUMPER
GND
COR40
PRSNT_SLV_N
SQUARE_SEL
COPROD6
PROD6
10N
10N
GND
10N
C57
C56
PIC510 COC51
PIC5201 COC52
PIC5301 COC53
PIC5401COC54
PIC5 01COC55
PIC5601 COC56
PIC5701 COC57
PIC3901 COC39
PIC40 1 COC40
PIC410 COC41
PIC4201 COC42
PIC20 1 COC20PIC210 COC21 PIC50 1 COC50
PIC50 2 PIC5102 PIC520 PIC5302 PIC5402 PIC5 02 PIC5602 PIC5702
PIC3902 PIC40 2 PIC4102 PIC420 PIC20
PIC210
C41
47P
COC1
COC72
COC63
C1
C72
C63
C40
PIC10
PIC102
PIFB101
PIFB102
1V0_CORE
C39
GND
3V3
3V3
PIC3801COC38PIC601 COC6PIC701 COC7PIC801 COC8PIC901 COC9PIC10 COC10PIC1 01 COC11PIC1201COC12PIC1301COC13PIC140 COC14PIC150 COC15PIC5801 PIC60 1
PIC3802 PIC602 PIC702 PIC802 PIC902 PIC10 2 PIC1 02 PIC120 PIC1302 PIC1402 PIC1502 PIC5802 PIC60 2
GND
100N
C2
C11
A1
GNDPIU10A1
A19
GNDPIU10A19
G10
GNDPIU10G10
G12
GNDPIU10G12
G8
GNDPIU10G8
H10
GNDPIU10H10
H11
GNDPIU10H11
H12
GNDPIU10H12
H13
GNDPIU10H13
H7
GNDPIU10H7
H8
GNDPIU10H8
H9
GNDPIU10H9
J10
GNDPIU10J10
J12
GNDPIU10J12
J8
GNDPIU10J8
K10
GNDPIU10K10
K11
GNDPIU10K11
K12
GNDPIU10K12
K13
GNDPIU10K13
K7
GNDPIU10K7
K8
GNDPIU10K8
K9
GNDPIU10K9
L10
GNDPIU10L10
L12
GNDPIU10L12
L8
GNDPIU10L8
PIU10M10
GND M10
M11
GNDPIU10M11
M12
GNDPIU10M12
M13
GNDPIU10M13
PIU10M7
GND M7
M8
GNDPIU10M8
M9
GNDPIU10M9
N10
GNDPIU10N10
N12
GNDPIU10N12
N8
GNDPIU10N8
W1
GNDPIU10W1
W19
GNDPIU10W19
U11
USB_VSSACPIU10U11
F14
PLL_AGNDPIU10F14
F13
PLL_AVDDPIU10F13
P9
USB_VDDPIU10P9
P10
USB_VDDPIU10P10
U8
USB_VDD33PIU10U8
A12
OTP_VCCPIU10A12
B12
OTP_VCCPIU10B12
F10
VDDIOTPIU10F10
PIC180 COC18PIC190 COC19PIC2 01COC22
PIC201COC2PIC301COC3PIC401 COC4PIC501 COC5
PIC7801 COC78
PIC7901 COC79
PIC1802 PIC1902
PIC2 0 PIC202 PIC302 PIC402 PIC502 PIC7802 PIC7902
3V3_IO
PIR2701
COR27
R27
3V3
1V0_CORE
0R1
COC34
C34
GND
PIC3401
PIC3402
PIR2 02
FB1
PIR2 01
R40
XM009855A
10K
Figure 15:
xCORE-200
USB sliceKIT
schematic (2
of 5)
1V0
COR22
R22
6
PIU1406
2B2
11
X1D3
X1D55
5
6
X1D69
X1D14
SQUARE_SEL
X1D22
X1D61
X1D15
X1D68
3 1B2
GND
4B2
1
S
15 OE_N
13
74CBTLV3257
PIU22015
PIU2201
PIU22013
14
PIU22014 4B1
10
11 3B1
2B2
PIU22010 3B2
PIU22011
PIU2206
PIU2205
2B1
2
X1D5
PIU2203
X1D54
1B1
U22
COU22
74CBTLV3257
PIU2202
GND
4B2
4B1
3B2
3B1
2B1
1
15 S
OE_N
PIU14015
PIU1401
13
PIU14013
SQUARE_SEL
14
PIU14014
X1D10
10
PIU14010
PIU14011
PIU1405
X1D49
X1D4
5
X1D56
1B2
3
PIU1403
2
PIU1402
1B1
X1D2
2
PIJ1502
4
PIJ1504
6
PIJ1506
8
PIJ1508
10
PIJ15010
12
PIJ15012
14
PIJ15014
16
PIJ15016
3V3
GND
3V3
GND
8
GNDPIU2208
12
4APIU22012
9
3APIU2209
7
2APIU2207
4
1APIU2204
16
VCCPIU22016
GND
8
GNDPIU1408
12
4APIU14012
9
3APIU1409
7
2APIU1407
4
1APIU1404
16
VCCPIU14016
IDC_HEADER_MAL
1
PIJ1501
3
PIJ1503
5
PIJ1505
7
PIJ1507
9
PIJ1509
11
PIJ15011
13
PIJ15013
15
PIJ15015
COJ15
J15
POX1D12
X1D12
U14
COU14
3V3_IO
3V3_IO
1V0_CORE
1V0
1V0_CORE
X1D57
3V3
X1D12
X1D22/X1D61
X1D15/X1D68
X1D14/X1D69
X1D5/X1D54
X1D10/X1D49
X1D4/X1D55
X1D3/X1D56
X1D2/X1D57
PIJ70A5
SQUARE_SEL
X1D20
X1D63
X1D7
X1D52
X1D6
X1D53
X1D1
X1D58
B1
B2
B3
B4
B5
B6
PIJ60B6
B7
PIJ60B7
B8
PIJ60B8
B9
PIJ60B9
B10
PIJ60B10
B11
PIJ60B11
5
6
11
3B1
2B2
OE_N
1B1
GND
4B2
1
S
15 OE_N
13
74CBTLV3257
PIU23015
PIU2301
PIU23013
14
PIU23014 4B1
10
11 3B1
2B2
2B1
PIU23010 3B2
PIU23011
6
5
PIU2306
PIU2305
3 1B2
2
PIU2303
PIU2302
U23
COU23
74CBTLV3257
PIU13015
1
15
4B2
PIU1301 S
13
PIU13013
14
PIU13014
4B1
10
PIU13010
3B2
PIU13011
PIU1306
PIU1305 2B1
1B2
1B1
A17
A18
3V3
3V3
GND
8
GNDPIU2308
12
4APIU23012
9
3APIU2309
7
2APIU2307
4
1APIU2304
16
VCCPIU23016
GND
8
GNDPIU1308
12
4APIU13012
9
3APIU1309
2A
7
PIU1307
4
1APIU1304
16
VCCPIU13016
X1D42
X1D43
X1D31
X1D32
X1D33
X1D25
X1D30
X1D12
X1D23
X1D35
RST_N_OUT
X1D40
X1D41
5V
X1D20/X1D63
X1D7/X1D52
X1D6/X1D53
X1D1/X1D58
X1D9/X1D50
X1D8/X1D51
X1D17/X1D66
X1D16/X1D67
GND
PIJ60A18
PIJ60A17
PCIE_36_SKT
COU13
U13
3
2
PIU1303
A13
A14
A15
A16
PIJ60A16
PIJ60A15
PIJ60A14
PIJ60A13
KEY
A12
PIJ60A12
PIJ60B17
B17
B18
PIJ60B18
B16
PIJ60B16
PIJ60B15
PIJ60B14
PIJ60B13
B13
B14
B15
A1
A2
A3
A4
A5
A6
PIJ60A6
A7
PIJ60A7
A8
PIJ60A8
A9
PIJ60A9
A10
PIJ60A10
A11
PIJ60A11
PIJ60A5
PIJ60A3
PIJ60A4
PIJ60A2
PIJ60A1
B12
PIJ60B12
PIJ60B5
PIJ60B3
PIJ60B4
COJ6
J6
SOCKET 4 SLOT
PIJ60B2
X1D20/X1D63
X1D21/X1D62
GND
PIJ70A14
PIJ70A13
PCIE_36_SKT
PIJ60B1
GND
3V3
5V
A13
A14
A15
X1D13/X1D70
PIJ70A15
A16
RST_N_OUTPORST0N0OUT
PIJ70A16
RST_N_OUT
A17
X1D18/X1D65
PIJ70A17
A18
X1D19/X1D64
PIJ70A18
A12
PIJ70A12
A4
PIJ70A4
POTMS
TMS
POTDO
TDO
A5
PRSNT_SLV_NPOPRSNT0SLV0N
PRSNT_SLV_N
A6
X1D8/X1D51
PIJ70A6
A7
X1D9/X1D50
PIJ70A7
A8
X1D1/X1D58
PIJ70A8
A9
X1D6/X1D53
PIJ70A9
A10
PIJ70A10
A11
X1D7/X1D52
PIJ70A11
PIJ70A3
PIJ70B5
GND
PIU1302
GND
X1D38
X1D39
X1D24
X1D36
X1D37
SQUARE_SEL
X1D9
X1D50
X1D8
X1D51
X1D17
X1D66
X1D16
X1D67
POCLK0OUT1
CLK_OUT1
X1D28
X1D34
X1D29
X1D26
X1D27
X1D11
X1D0
A1
A2
A3
PIJ70A2
PIJ70A1
B4
PIJ70B4
KEY
COJ7
J7
PIJ70B3
PIJ70B2
B1
B2
B3
SOCKET 3/7 SLOT
PIJ70B1
B5
X1D2/X1D57 PIJ70B6
B6
X1D3/X1D56 PIJ70B7
B7
B8
PIJ70B8
X1D4/X1D55 PIJ70B9
B9
X1D10/X1D49 PIJ70B10
B10
X1D5/X1D54 PIJ70B11
B11
3V3
B12
B13
B14
PIJ70B14
POCLK0OUT0
CLK_OUT0
B15
B16
PIJ70B16
B17
B18
POTDI
TDI
POTCK
TCK
PODEBUG0N
DEBUG_N
5
11
SQUARE_SEL
X1D19
X1D64
GND
14
16
PIJ13016
18
PIJ13018
20
PIJ13020
PIJ904
8
10
12
14
PIJ9014
16
PIJ9016
18
PIJ9018
20
PIJ9020
22
PIJ9022
24
PIJ9024
3B2
3B1
2B2
2B1
1B2
1B1
4B2
X1D19/X1D64
X1D18/X1D65
X1D13/X1D70
X1D21/X1D62
TILE 1
Sheet
Sheet Name
Date: 27-08-2015
A2
2
XP-SKC-XU216.PrjPcb
Project Name
of
Copyright (c) 2012 XMOS Ltd.
GND
8
GNDPIU1908
12
4APIU19012
9
3APIU1909
7
2APIU1907
4
1APIU1904
3V3
COMECH5
MECH5
NPTH_2MM8
X1D12
X1D23
X1D32
X1D33
X1D25
X1D30
X1D31
X1D42
X1D43
X1D35
X1D40
X1D41
16
VCCPIU19016
PIJ9012
PIJ9010
X1D8
X1D9
X1D1
X1D6
X1D7
X1D20
X1D21
X1D13
X1D18
X1D19
X1D51
X1D50
X1D58
X1D53
X1D52
X1D63
X1D62
X1D70
X1D65
X1D64
Size:
74CBTLV3257
NA
2
4
6
PIJ906
7
9
11
PIJ9011
13
PIJ9013
15
PIJ9015
17
PIJ9017
19
PIJ9019
21
PIJ9021
23
PIJ9023
PIJ909
PIJ908
PIJ902
PIJ903
1
3
5
PIJ905
PIJ907
PIJ901
1
S
15 OE_N
PIU19015
PIU1901
13
PIU19013
8
10
PIJ13010
12
PIJ13012
PIJ13014
COJ9
J9
NA
2
4
PIJ1304
PIJ1308
7
9
PIJ1309
11
PIJ13011
13
PIJ13013
15
PIJ13015
17
PIJ13017
19
PIJ13019
PIJ1302
6
PIJ1306
1
3
PIJ1307
COJ13
J13
5
PIJ1305
PIJ1303
PIJ1301
PIU19014 4B1
14
10
PIU19010
PIU19011
X1D65
X1D18
6
PIU1906
PIU1905
NA
12
14
16
PIJ8016
18
PIJ8018
20
PIJ8020
PIJ8014
PIJ8012
10
PIJ8010
PIJ808
6
8
2
PIJ802
4
PIJ804
11
13
15
PIJ8015
17
PIJ8017
19
PIJ8019
PIJ8013
PIJ8011
9
PIJ809
PIJ807
5
7
PIJ806
1
COJ8
J8
3
PIJ803
PIJ805
PIJ801
U19
COU19
3
2
PIU1903
PIU1902
X1D13
X1D70
X1D21
X1D62
X1D0
X1D11
X1D26
X1D27
X1D28
X1D34
X1D29
X1D36
X1D37
X1D24
X1D38
X1D39
X1D2
X1D3
X1D4
X1D10
X1D5
X1D14
X1D15
X1D22
X1D16
X1D17
X1D57
X1D56
X1D55
X1D49
X1D54
X1D69
X1D68
X1D61
X1D67
X1D66
5
1V1
Revision:
22/31
2M2
2
PIU2705
3V3
PIU2703
2M2
GND
33P
PIX202
24M
ABLS
PIC4501 COC45
PIC4502
PIX201
C45
PIR2802
COX2
X2
PIR2801
COR28
R28
33P
C49
33P
100N
GND
PIC4302
C43
COU11
U11
2
A
NC7SZ125
PIU2602
1
PIU2601
OE_N
COU26
U26
NC7NZ34
COR18
2
R18
PIR1801
3YPIU1102
3V3
GND
3
GND
PIU2603
COR19
4
R19
PIR1901
YPIU2604
5
VCCPIU2605
GND
4
GNDPIU1104
COR16
5
R16
PIR1601
2YPIU1105
COR15
R15
PIR1501
3V3
2A
3
7
1YPIU1107
8
VCCPIU1108
6
PIU1106
3A
PIU1103
1
PIU1101
1A
GND
PIC4301 COC43
3V3
OSC_24M
PIC4901 COC49
PIC4902
PIR3401
PIR3402
GND
COR34
PIU2704
NC7SZU04
4
C26
OSC_25M
PIC2601 COC26
PIC2602
PIR20 1
PIR20 2
470R
GND
COR20
COU27
U27
GND
PIU2702
PIX102
25M
ABLS
PIX101
33P
PIR1702
COX1
X1
PIR1701
COR17
R17
COC27
C27
GND
PIC2701
PIC2702
PIU803
4
PIU804
NC7SZU04
COU8
U8
GND
2
PIU802
PIU805
5
3
5
3
R20
XM009855A
R34
Figure 16:
xCORE-200
USB sliceKIT
schematic (3
of 5)
470R
3V3
33R
PIR1902
33R
PIR1802
33R
PIR1602
33R
PIR1502
POXS20CLK
XS2_CLK
POCLK0OUT0
CLK_OUT0
POCLK0OUT1
CLK_OUT1
POCLK0OUT2
CLK_OUT2
C25
100N
Sheet 3 of 5
CLOCK
Sheet Name
XP-SKC-XU216.PrjPcb
Project Name
GND
100N
C24
PIC2401 COC24PIC2501 COC25
PIC2402 PIC2502
3V3
Date 27-08-2015
Size
A4
GND
100N
C23
PIC2301 COC23
PIC2302
3V3
Rev
1V1
23/31
16
9
12 4A
X0D5
X0D6
GND
V7
X0D08
X0D6_EXT
74CBTLV3257
GND
SPI_LATCH_SEL
QSPI_D2
QSPI_D1
1
SPIU601
15
OE_NPIU6015
13
4B2PIU6013
14
4B1PIU6014
X0D5_EXT
11
3B1PIU6011
10
3B2PIU6010
QSPI_D0
X0D4_EXT
6
2B2PIU606
QSPI_CS_N
5
2B1PIU605
X0D1_EXT
POBOARD0RST0N
BOARD_RST_N
COR7
PIR701
PIR702
3V3
XS2_XU216-512-FB236
3
1B2PIU603
2
1B1PIU602
COU6
U6
K18 X0D61
K17
PIU10K17 X0D62
J17
PIU10J17 X0D63
J18
PIU10J18
X0D64
J19 X0D65
PIU10J19
H19
PIU10H19 X0D66
H18
PIU10H18 X0D67
H17
PIU10H17
X0D68
G17 X0D69
PIU10G17
G18
PIU10G18 X0D70
X0D61
X0D62
X0D63
X0D64
X0D65
X0D66
X0D67
X0D68
X0D69
X0D70
PIU10K18
P19
PIU10P19
X0D49
P18 X0D50
PIU10P18
N17
PIU10N17 X0D51
N18
PIU10N18 X0D52
M17
PIU10M17
X0D53
M18 X0D54
PIU10M18
M19
PIU10M19 X0D55
L19 X0D56
PIU10L19
L18
PIU10L18
X0D57
L17
PIU10L17 X0D58
U18
PIU10U18
U17 X0D18
PIU10U17 X0D19
W14
PIU10W14
X0D20
V14
PIU10V14
X0D21
U14
PIU10U14
U16 X0D22
PIU10U16
X0D23
E18
PIU10E18
E17 X0D24
PIU10E17
X0D25
C18
PIU10C18 X0D26
C19
PIU10C19
X0D27
C17
PIU10C17
X0D28
A17
PIU10A17 X0D29
C16
PIU10C16 X0D30
C15
PIU10C15
X0D31
B17
PIU10B17
X0D32
B16
PIU10B16 X0D33
D17
PIU10D17 X0D34
D18
PIU10D18
X0D35
B1
PIU10B1
X0D36
C1
PIU10C1 X0D37
C2
PIU10C2
X0D38
D2
PIU10D2
X0D39
D3
PIU10D3 X0D40
E3
PIU10E3
X0D41
E2
PIU10E2
X0D42
E1
PIU10E1 X0D43
X0D49
X0D50
X0D51
X0D52
X0D53
X0D54
X0D55
X0D56
X0D57
X0D58
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
X0D26
X0D27
X0D28
X0D29
X0D30
X0D31
X0D32
X0D33
U5
X0D11
V16
X0D12
V15
W15 X0D14
X0D15
V19
X0D16
U19
PIU10U19
X0D17
PIU10V19
PIU10W15
PIU10V15
U15 X0D13
PIU10U15
PIU10V16
PIU10U5
V8
PIU10V8
X0D09
PIU10V7
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
S=0 => A=B1
S=1 => A=B2
BRD_RST_N
X0D02
X0D11
X0D8
X0D9
SPI MUXING & FLASH
PIU608
8 GND
PIU6012
PIU609
3A
7 2A
PIU607
X0D4
1A
VCC
4
PIU604
PIU6016
3V3
X0D1
COU1A
U1A
W6
SPI_LATCH_OUT
U2
X0D01PIU10U2
V4
X0D04PIU10V4
W5
X0D05PIU10W5
V5
X0D06PIU10V5
U6
X0D07PIU10U6
U1
X0D10PIU10U1
8
PIU2108
9
PIU2109
2Q_N
2Q
D
13
2C_NPIU21013
11
2CPPIU21011
12
2DPIU21012
HEADER_RA
COR3
3V3
3
0R
14
Q
Q
D
1
1C_NPIU2101
3
1CPPIU2103
2
1DPIU2102
74LV74PW
C
S
4
1S_NPIU2104
U21A
COU21A
COU21B
BRD_RST_N
GND
1Q_N
1Q
VCC
GND
3V3
AFTER BOOT SELECT ENABLE AND BRING LATCH HIGH
STATE WILL REMAIN UNTIL SYSTEM RESET
7
6
PIU2107
PIU2106
5
PIU2105
GND
C29
PIC7 02 100N PIC2802 100N PIC2902 100N
C28
PIR3801
PIR3802
GND
COR38
X0D30
PORST0N0IN
RST_N_IN
PIC7 01 COC77PIC2801 COC28PIC2901COC29
PIU21014
X0D31 = SPI EN/DIS
X0D30 = LATCH
PIR3902
GND
3V3
2
GNDPIU2502
4
Y2PIU2504
3V3
100N
COC17
C17
GND
PIC170
PIC1702
6
RST_N_IN
Y1PIU2506
C77
X0D43
3V3
A2
5
VCCPIU2505
3V3
GND
9
PADPIU1209
4
GNDPIU1204
8
VCCPIU1208
GND
PIR14202
X0D40
X0D41
COR143
R143
33R
PIR14301
PIR14302 X0D42
PIR14201
COR142
R142
33R
XTAG and XLINK Connections
A1
3V3
NC7WZ07
PIU2503
R39
COR39
PIR3901
10N
C59
GND
1
COU25
U25
PIU2501
PIC5901 COC59
PIC5902
X0D31
PIR3 01
PIR3 02
3V3
IS25LQ016B_JK
COU12
U12
QSPI_CS_NPIU1201
1
CE_N
QSPI_D0 PIU1205
5 SI(IO0)
QSPI_D1 PIU1202
2
SO(IO1)
QSPI_D2 PIU1203
3
WP_N(IO2)
QSPI_D3 PIU1207
7
HOLD_N(IO3)
QSPI_CLK PIU1206
6 SCK
RST_N_XTAG
PIR401
10
2S_NPIU21010
74LV74PW
C
S
NA
BRD_RST_N
Q
1
2
U21B
JUMPER
Q
COR4
PIR402
3V3
4
6
PIJ106
8
PIJ108
10
PIJ1010
12
PIJ1012
14
PIJ1014
16
PIJ1016
18
PIJ1018
20
PIJ1020
PIJ104
2
PIJ102
COJ1
J1
PIJ103
3
TDI PIR801
5
PIR802
PIJ105
TMS
7
PIJ107
TCK PIR1401
9
PIR1402
PIJ109
DEBUG_N
11
PIJ1011
COR14
R1433R
TDO
13
PIJ1013
RST_N_XTAG PIJ1015
15
17
PIJ1017
19
PIJ1019
COR8
R8 33R
1
PIJ101
COJ12
J12
PIJ1202
PIJ1201
COPROD5
PROD5
SPI_LATCH_SEL
SPI_LATCH_OUT
X0D1
X0D4
X0D5
X0D6
X0D7
X0D10
R4
V6
PIU10V6
X0D03
1K
PIU10W6
R7
R33
U4 X0D0
PIU10U4
18K
10K
X0D2
X0D3
R38
XM009855A
100K
Figure 17:
xCORE-200
USB sliceKIT
schematic (4
of 5)
X0D0
16
GND
X0D10_EXT
74CBTLV3257
GND
1
SPIU301
15
OE_NPIU3015
13
4B2PIU3013
14
4B1PIU3014
10
3B2PIU3010
11
3B1PIU3011
SPI_LATCH_SEL
QSPI_CLK
QSPI_D3
X0D7_EXT
5
2B1PIU305
6
2B2PIU306
3
1B2PIU303
2
1B1PIU302
COU3
U3
POX0D39
X0D39
POX0D390EXT
X0D39_EXT
PODEBUG0N
DEBUG_N
POTCK
TCK
POTMS
TMS
POTDI
TDI
POTDO
TDO
S=0 => A=B1
S=1 => A=B2
GND
GND
4A
8
PIU308
3A
PIU3012
12
9
PIU309
2A
7
PIU307
X0D10
VCC
4
PIU304
1A
PIU3016
3V3
X0D7
GND
100N
C66
PIC6 01 COC66
PIC6 02
3V3
X0D39
X0D39_EXT
DEBUG_N
TCK
TMS
TDI
TDO
4
6
8
10
PIJ508
PIJ5010
PIJ506
PIJ504
2
PIJ502
COJ5
J5
X0D28
1
PIJ501
X0D29
3
PIJ503
X0D30
5
PIJ505
X0D31
7
PIJ507
X0D39_EXTPIJ509
9
X0D50
X0D63
X0D62
X0D58
X0D53
X0D52
X0D51
X0D70
X0D64
X0D65
1
3
5
PIJ1105
7
PIJ1107
9
PIJ1109
11
PIJ11011
13
PIJ11013
15
PIJ11015
17
PIJ11017
19
PIJ11019
PIJ1103
PIJ1101
NA
2
4
6
PIJ1106
8
PIJ1108
10
PIJ11010
12
PIJ11012
14
PIJ11014
16
PIJ11016
18
PIJ11018
20
PIJ11020
PIJ1104
PIJ1102
COJ11
J11
NA
X0D57
X0D56
X0D61
X0D54
X0D55
X0D68
X0D69
X0D49
X0D66
X0D67
X0D8
4
X0D9
6
X0D1_EXT
PIJ406
8
X0D6_EXT
PIJ408
10
X0D7_EXT
PIJ4010
12
X0D20
PIJ4012
14
X0D21
PIJ4014
16
X0D37
PIJ4016
18
X0D18
PIJ4018
20
X0D19
PIJ4020
PIJ404
2
PIJ402
COJ4
J4
X0D2
1
PIJ401
X0D3
3
PIJ403
X0D4_EXT PIJ405
5
X0D10_EXTPIJ407
7
X0D5_EXT PIJ409
9
X0D14
11
PIJ4011
X0D15
13
PIJ4013
X0D38
15
PIJ4015
X0D16
17
PIJ4017
X0D17
19
PIJ4019
3V3
USB_D_P
POUSB0D0P
USB_D_P
USB_D_N
POUSB0D0N
USB_D_N
X0D32
X0D33
5V
X0D16
X0D17
X0D38
X0D14
X0D15
X0D26
X0D27
POCLK0OUT0
CLK_OUT0
A1
A2
A3
B12
A14
A15
KEY
GND
COMECH2
MECH2
NPTH_2MM8
COJ3
J3
B10
B9
PIJ30B10
PIJ30B9
A7
A6
PIJ30A6
A5
PIJ30A5
A4
PIJ30A4
A3
PIJ30A3
A2
PIJ30A2
A1
PIJ30A1
PIJ30A7
PIJ30B7
B7
B6
PIJ30B6
B5
PIJ30B5
B4
PIJ30B4
B3
PIJ30B3
B2
PIJ30B2
B1
PIJ30B1
B8
PIJ30B8
B11
PIJ30B11
PIJ30A10
PIJ30A9
A8
PIJ30A8
A11
PIJ30A11
A10
A9
PIJ30B15
PIJ30B18
PIJ30B17
PIJ30B16
B18
B17
B16
B15
B14
PIJ30B14
B13
PIJ30B13
B12
PIJ30B12
USB Slot
PIJ30A18
X0D20
X0D21
X0D7_EXT
X0D8
X0D9
X0D1_EXT
X0D6_EXT
GND
TILE 0
Sheet
Sheet Name
Date: 27-08-2015
A2
4
XP-SKC-XU216.PrjPcb
Project Name
of
Copyright (c) 2012 XMOS Ltd.
COMECH9
MECH9
NPTH_2MM8
COMECH8
MECH8
NPTH_2MM8
Size:
X0D11
X0D0
X0D36
X0D35
RST_USB
12V VBUS_IN
RST_N_OUT
X0D37
RST_N_OUT
PORST0N0OUT
RST_N_OUT
X0D18
X0D19
GND
PIJ20A18
PIJ20A17
A17
A18
A16
PIJ20A16
PIJ20A15
PIJ20A14
5V
PIJ30A17
PIJ30A16
A18
A17
A16
A15
PIJ30A15
A14
PIJ30A14
A13
PIJ30A13
A12
PIJ30A12
12V
A12
A13
PIJ20A13
PIJ20A12
PCIE_36_SKT
PIJ20B18
PIJ20B17
B17
B18
B16
PIJ20B16
PIJ20B15
PIJ20B14
B14
B15
B13
PIJ20B13
PIJ20B12
PIJ20A11
PIJ20A10
PIJ20B11
PIJ20A9
PIJ20A7
PIJ20A8
PIJ20A6
PIJ20A5
A5
A6
A7
A8
A9
A10
A11
A4
PIJ20A4
PIJ20A3
PIJ20A2
PIJ20A1
PIJ20B10
KEY
COJ2
J2
PIJ20B9
PIJ20B7
PIJ20B8
PIJ20B6
PIJ20B5
B5
B6
B7
B8
B9
B10
B11
B4
PIJ20B4
PIJ20B3
PIJ20B2
B1
B2
B3
SOCKET 6 SLOT
PIJ20B1
GND
X0D4_EXT
X0D10_EXT
X0D5_EXT
X0D2
X0D3
3V3
5
1V1
Revision:
24/31
COR124
COR127
4
6
PIU1606
EN
5
PIU1605
VIN_A
PIU1604 VIN_SW
ST1S06
COU16
U16
GND
PIU1602 PIU1607
GND
1
FBPIU1601
3
SWPIU1603
3V3_PG
COU17
U17
ADM1085
1
PIU1701 ENIN
3
PIU1703
VIN
2U2
3V3
PIR12601
PIR12602
PIR12 01
15P
GND
PIC12 02
PIC12 01
22U
GND
PIC120 1
PIC120 2
100U
C110
COR123
GND
PIC101
PIC102
PIC1 01
PIC1 02
C111
PIC1 201
PIC1 20
COR1 4
C112
POPOR
POR
GND
PIR12301
1U
GND
PIC1601
PIC1602
GND
10U
COC160
C160
12V
GND
10U
C117
100K
GND
100N
COU15
U15
RT8293B
EN
9
5V_PG
PIR1 901
PIR1 902
PIC1401
PIC1402
2N2
6
PIU1806
EN
5
PIU1805 VIN_A
4
PIU1804
VIN_SW
COU18
U18
ST1S06
GND
PIU1802 PIU1807
COC114
C114
GND
COR1 9
6
COMPPIU1506
5
FBPIU1505
3
SWPIU1503
1
BOOTPIU1501
PIC1301
PIC1302
PID201
COD2
D2
1
FBPIU1801
CO3V3
3V3
CO1V0
1V0
CO5V
5V
GND
PIGND501
PI1V001
PI3V301
PI5V01
5V 3V3 1V0
PIR12 01
PIR12102
PIR1 701
PIR1 702
GND
COR12
COR1 7
PIL202
2U2
PIC1501
PIC1502
COR13
22U
PIR13 01
PIR13102
PIR12801
PIR12802
GND
COR128
PIC1601
PIC1602
22U
PID401
COD7
D7
GND
PIR12901
PIMTH101
PIMTH201
COMTH1
MTH1
PTH_M3
COMTH2
MTH2
PTH_M3
COPROD4
PROD4
PCB FEET 6MM
COPROD3
PROD3
PCB FEET 6MM
COPROD2
PROD2
PCB FEET 6MM
PID701
PID702
PIR130 1
PIR130 2
GND
PIMTH401
PIMTH301
PTH_M3
COMTH4
MTH4
COMTH3
MTH3
PTH_M3
COFM5
FM5
FIDUCIAL
COFM4
FM4
FIDUCIAL
COFM3
FM3
FIDUCIAL
GREEN
GREEN
GND
COR129 COR130
COPROD1
PROD1
PCB FEET 6MM
GND
PIC12301
PIC12302
PIR12902
3V3
COC123
C123
GND
22U
PID402
PIR1 501
PIR1 502
5V
GND
COR1 5
COD4
D4
COC115
COC116
C115
C116
GND
PIL402
COL4
L4
3
SWPIU1803 PIL401
6U8
COL2
L2
PIL201
100N
5V TO 3V3 DC-DC CONVERTER
COGND5
GND5
PID202
COC113
C113
1N4148W
VREF = 0.8V
VOUT = 0.8 x (1 + 18/5.6) = 3.37V
4U7
COC122
C122
GND
PIC12 01
PIC12 02
5V
PIU1509 GND_9
4
PIU1504
GND_4
8
PIU1508
SS
7
PIU1507
2
PIU1502
VIN
GND
PIC1 701 COC117
PIC1 702
PIR1 401
PIR1 402
COC110COC111COC112
PIR12302
COC120
C120
1V0
120R
XXA
COC121
C121
GND
COR126
COR12
PIL302
GND
5
CEXTPIU1705
2
GNDPIU1702
4
ENOUTPIU1704
6
VCCPIU1706
100N
PIC1 802
GND
COC118
C118
PIC1801
3V3
PIL301
PIR12 02
COD3
D3
SMBJ22A
GND
PID302
PID301
COL3
L3
B240A
VREF = 0.8V
VOUT = 0.8 x (1 + 4.7/18) = 1.01V
3V3_PG
GND
PIR12701
PIR12702
PIR12401
PIR12402
1V0
4U7
GND
PIC1 901
PIC1 902
COC119
C119
5V
GND
100N
COC109
C109
2
GND
7
GND_PAD
12V
R114
PIFB302
33K
PIFB301
4K7
18K
R119
COFB3
FB3
2
GND
7
GND_PAD
PID101
1K
R117
R121
PID102
R122
R126
PIF102
R123
62K
11K8
PIC1091
PIC1092
3A
18K
5K6
COD1
D1
COF1
F1
R128
R131
PIF101
1K
R115
2K2
PJ-002A
1
PIJ1001
3
PIJ1003
2
PIJ1002
3K9
10K
R124
R127
R129
1K
R130
XM009855A
5
PIU2005 CD
1N
1
PIU2401 GND
1
COR132
PIR13201
PIR13202
3V3_PG
5V_PG
10K
Sheet 5 of 5
POWER
Sheet Name
XP-SKC-XU216.PrjPcb
Project Name
2
RESET_NPIU2402
4
NCPIU2004
RST_OUT PIU2001
Date 27-08-2015
Size
A3
COU24
U24
APX809-44SA
3
PIU2403 VCC
GND
5V
GND
3
COC129
C129 PIU2003 GND
GND
PIC12901
PIC1290
NCP303LSN30
COU20
U20
2
PIU2002 INPUT
3V3
3V3
R132
Figure 18:
xCORE-200
USB sliceKIT
schematic (5
of 5)
COJ10
J10
Rev
1V1
25/31
3 USB sliceCARDs
IN THIS CHAPTER
· XU216 USB Slice Pinout
· USB AB Slice
USB sliceCARDs connect to the PCI-E 36 pin connector J3 on the XU216 Core Board.
They have a unique key design in order to prevent them being plugged in to non
USB slice slots and prevent non USB slices being plugged in to a USB slice slot.
The detail for the key design and the PCI-E 36 card edge finger can be seen in the
figure below:
PAQ102
PAQ101
COQ1
PAJ20A1
PAJ20B1
PAJ20A2
PAJ20B2
PAJ20B3
PAJ20A3
COC17
PAC1702 PAC1701
COTP2
PAU501
PAU508
PAU502
PAU507
PAU503
PAU506
PAU504
PAU505
COU5
PATP201
PAU30 PAU302 PAU301
PAR1002
PAR902
PAR1001
PATP101
COTP1
PAR801
COR8
PAR2002
COR20
COMECH2
Figure 19:
USB Slice
Detail
XM009855A
PAJ20B7
PAJ20A7
PAJ20A8
PAJ20B8
COR15
COMECH1
PAJ20A9
PAJ20B9
PAMECH101
PAJ20A11
PAJ20B11
PAJ20A10
PAJ20B10
COR10
PAJ20B12
PAJ20A12
PAJ20A13
PAJ20B13
COC10
PAC1002 PAC1001
PAJ20A14
PAJ20B14
PAJ20A15
PAJ20B15
COJ2
PAR802
PAR2001
PAJ20A6
PAJ20B6
PAR1502 PAR1501
COR9
PAU304 PAU305 PAU306
PAR601
PAR901
PAJ20A4
PAJ20B4
PAJ20A5
PAJ20B5
COR13
PAR1301 PAR1302
PAJ20A16
PAJ20B16
PAJ20B17
PAJ20A17
PAJ20A18
PAJ20B18
3.1
27/31
XU216 USB Slice Pinout
The table below details the pinout of the USB slice connector from the XU216 Core
Board:
PCIE A
SIGNAL
FUNCTION
PCIE B
(TOP)
Figure 20:
USB Slice
Pinout
XM009855A
SIGNAL
FUNCTION
(BOT)
A1
GND
POWER
GROUND
SUPPLY
B1
GND
POWER
GROUND
SUPPLY
A2
GND
POWER
GROUND
SUPPLY
B2
GND
POWER
GROUND
SUPPLY
A3
USB DN
USB DATA NEGATIVE
B3
GND
POWER
GROUND
SUPPLY
A4
USB DP
USB DATA POSITIVE
B4
GND
POWER
GROUND
SUPPLY
A5
GND
POWER
GROUND
SUPPLY
B5
GND
POWER
GROUND
SUPPLY
A6
GND
POWER
GROUND
SUPPLY
B6
GND
POWER
GROUND
SUPPLY
A7
X0D33
RESERVED FOR MFI
B7
NC
NOT CONNECTED
A8
X0D32
RESERVED
B8
X0D35
I2C SDA
A9
GND
POWER
GROUND
B9
X0D36
I2C SCL
A10
X0D27
USB SEL 2
B10
X0D0
RESERVED
A11
X0D26
USB SEL 1
B11
X0D11
VBUS OUT ENABLE (H)
KEY
KEY
MECHANICAL KEY
KEY
KEY
MECHANICAL KEY
A12
3V3
3.3V POWER SUPPLY
B12
RST_USB
xCORE-200 RESET
A13
GND
POWER
GROUND
B13
GND
POWER
GROUND
A14
5V
5.0V POWER SUPPLY
B14
VBUS IN
VBUS FROM USB HOST
A15
5V
5.0V POWER SUPPLY
B15
VBUS IN
VBUS FROM USB HOST
A16
GND
POWER
GROUND
SUPPLY
B16
GND
POWER
GROUND
A17
12V
12.0V POWER SUPPLY
B17
12V
12.0V POWER SUPPLY
A18
12V
12.0V POWER SUPPLY
B18
12V
12.0V POWER SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
3.2
28/31
USB AB Slice
The USB AB slice consists of a USB A connector, USB B connector and a high-speed
2:1 switch to select between them.
By default the USB data signals from the B type connector are routed to the U8
device on the U16 board. When the USB B connector is being routed the LED next
to the connector is illuminated. In order to route the USB data signals from the A
type connector the USB_SEL line should be bought high. When the USB A connector
is being routed the LED next to the connector is illuminated.
5V is supplied to the USB A connector, from a local power supply, to provide
VBUS to connected devices. This supply can be disabled by bringing the signal
VBUS_OUT_EN low.
The figure below shows the layout of the USB A/B slice:
COMTH1
COMTH3
PAMTH101
COJ3
PAJ306
COR14
PAD301 PAD302
COD3
PAR1401 PAR1402
PAQ201
COQ2
PATP401COTP4
PATP401
PAJ101
PAJ102
PAJ103
PAC1101 PAC1102
PAC1902
PAC1901
COC11
PAD402
PAJ305
PAJ304 PAJ303
PAJ301 PAJ302
PAQ202
PAQ203
PAJ105
PAMTH301
COD4 PAD401
PAFB101
PAC2101
PAC2102
PAR1601
COC21
PAR1602
COR16
PAQ102
PAQ103
COC18
PAQ101
COC19PAFB102 COFB1
PAC1801
PAC1802
COC20
COJ1
COR17
PAU601
PAU602
PAU6010
PAU603
PAU604
COQ1
PAR1701
PAC2002
PAC2001
PAR1702
PAU609
PAU608
PAU607
PAU605
PAU606
COU6
COR5
PAR501 PAR502 PAR101 PAR102 COR1
PAC902 PAC901
PAR201 PAR202 COR2
COC9
PAU202 PAU201 PAC401
PAC402
PAC1401 PAC1402
COC14
COC4
COU2 PAU203
PAJ104
PAJ106
COC16 PAC1601 PAC1602
COC15 PAC1501 PAC1502
COU4
COR11
PAR1102 PAR1101
PAU405
PAU404
PAU406
PAU403
PAU407
PAU402
PAR1801 PAR1802
PAU401
PAR1202 PAR1201
PAU408
PAC1201 PAC1202
PAC1301 PAC1302
COR18
PAJ20B1
PAJ20A1
PAJ20A2
PAJ20B2
COC12 COR12
COC13
PAJ20B3
PAJ20A3
PAJ20B4
PAJ20A4
COC17
COC1
COC7 PAC701
PAC702 PAC102 PAC101
PAC602 PAC202 PAC201
COC6 PAC601
COC2
PAC1702 PAC1701
PAU501
COTP3 COTP2
PAHS101
COHS1 COC8
PAU101
PAU102
COL1
PAL102
PAL101
PAU103
PAU108
PAU109
PAU104
COU1
PAU106
PAC501 PAC502
PAU105
COC5
COR7
PAU507
PAU503
PAU506
PAU504
PAU505
COU5
PATP301 PATP201
PAR901 PAR1002
COU3
PAR902 PAR1001
COR9
PAC801 PAC802
PAU107
PATP101
PAR602 PAR601
COR6 COTP1
PAR701 PAR802
COC3
COD2 PAD202
PAD201
COMTH2
Figure 21:
USB AB Slice
XM009855A
PAMTH201
PAD102
PAD101
COD1
PAC302
PAC301
COR4
PAJ20A5
PAJ20B5
PAR1301 PAR1302
PAJ20A6
PAJ20B6
PAJ20A7
PAJ20B7
PAR1502 PAR1501
PAJ20A8
PAJ20B8
COR15
COMECH1
PAJ20A9
PAJ20B9
PAJ20A10
PAJ20B10
PAJ20A11
PAJ20B11
PAMECH101
COR10
PAJ20B12
PAJ20A12
PAJ20A13
PAJ20B13
COC10
PAJ20A14
PAJ20B14
PAJ20A15
PAJ20B15
PAC1002 PAC1001
COJ2
PAJ20A16
PAJ20B16
PAJ20A17
PAJ20B17
PAJ20A18
PAJ20B18
PAR702 PAR801
COR3
PAR301 PAR302
PAU508
PAU502
COR13
PAR402
COR8
PAR401
PAR2001 PAR2001
PAR1901
PAR1902 PAR2002
PAR2002
COR20
COR19 COMECH2
4 New Designs Based on sliceKIT
IN THIS CHAPTER
· USB
· Portmap
· QSPI Routing Control
· Debug Interface
There are a number of sections of the design of the sliceKIT platform that have
been optimized for flexibility to cover as many use cases as possible. Therefore
some consideration may be required in what to leave out or change in a custom
design. Some of the important points to consider are dealt with in this section.
Some general points to consider when implementing your own design are:
· Always check the datasheet of the xCORE device. In the case where the reference
design and datasheet conflict, the datasheet presides.
· XMOS datasheets contain additional hardware design requirements and guidelines that are not covered in this document, which users of XMOS hardware
reference designs must ensure are followed.
· The presence of a third party device in an XMOS hardware reference design does
not make any statement about its general availability. You must make your own
arrangements to ensure that all components can be sourced in the required
volumes.
4.1
USB
The xCORE-200 USB sliceKIT platform has been designed to allow for a number of
options when it comes to USB connectivity. In a custom design it is highly unlikely
that a high-speed connector will be required, hence the USB slice connector can be
removed and your own connectivity option can be implemented.
For all USB implementations the following points should be considered:
· Keep USB data lines as short as possible
· The USB data differential pair should have a characteristic impedance of 90R
· Common mode chokes, vias, connectors and stubs should be avoided if at all
possible to maximise signal integrity
· For further information refer to ‘High Speed USB Platform Design Guidelines‘_
The xCORE-200 Core Board USB design is a compromise to allow for maximum
XM009855A
30/31
flexibility in use. Therefore it should not be used as a reference for custom designs
that require full USB compliance.
4.1.1
USB Device (B)
For a simple device only configuration a USB B connector (standard, mini or micro
size) should be connected directly to the USB data lines of the XU216 device. If the
device is to be bus powered an ESD device can be added to clamp the data lines
to VBUS and ground and the connection to the XU216 VBUS pin can be omitted.
If the device is to be self powered then the data lines should only be clamped to
ground, and the VBUS input should be connected to the XU216 VBUS pin to detect
host connection.
4.1.2
USB Host (A)
To implement a host only connection a USB A connector should be directly connected to the USB data lines of the XU216 device. The VBUS power supply will need
to be provided locally. An ESD device can be added to clamp the data lines to VBUS
and ground.
4.1.3
Multi Mode USB
For more complex configurations requiring a number of host and/or device connections to be available one or more high speed capable USB bus switches can be
used, with the routing being controlled using one of the wider ports available on
the XU device. There are many options for deciding which port to route to (and
consequently which code to boot) from a user input switch to sensing connections
and deciding priority.
4.2
Portmap
Due to the flexibility of the I/O on an xCORE-200 device the location of the signals
routed to the XU216 can be easily optimized for your own layout.
As a general rule any 1-bit port pin can be easily swapped with any other. The only
fixed 1-bit port pins are those connected to the SPI bus of the code flash device.
The location of signals on the 4-bit ports can be swapped with other signals on
the same port, and the ports as a whole can be swapped, however care should be
taken to ensure that all signals on the same port should be in the same direction
i.e. all outputs or all inputs.
4.3
QSPI Routing Control
In order to maximize the functionality of the sliceKIT platform all of the ports used
by the boot flash can also used by the system after boot. In order to allow for this
the QSPI 1-bit ports are latched to either the flash device or to the I/O.
XM009855A
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If your design does not make use of all of the 1-bit ports then the slave select line
should be left to only control the QSPI interface and the rest of the QSPI 1-bit ports
can be reused.
4.4
Debug Interface
During the development phase of a new design it is highly recommended that
the full XSYS debug interface, including the xSCOPE xCONNECT link, should be
included. This allows for full programming and debug interfaces.
Once the design is stable the xSCOPE xCONNECT link can be omitted, and if space
is a concern the main JTAG signals can be bought out to a custom header, or test
points.
For high volume builds it is possible to omit the debug interface altogether, however
this will require another method of programming the flash e.g. preprogrammed
before placement.
For single device designs most of the switching and buffering devices for the JTAG
chain can be omitted.
Copyright © 2016, All Rights Reserved.
Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and
is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in
relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation
thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any
such claims.
XMOS and the XMOS logo are registered trademarks of Xmos Ltd. in the United Kingdom and other countries,
and may not be used without written permission. All other trademarks are property of their respective owners.
Where those designations appear in this book, and XMOS was aware of a trademark claim, the designations
have been printed with initial capital letters or in all capitals.
XM009855A

xCORE-200 USB sliceKIT Hardware Manual

Transcription

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