High Density FOWLP for Mobile Applications IME Technical

High Density FOWLP for Mobile Applications IME Technical

IME Technical Proposal
High Density FOWLP
for Mobile Applications
22 April 2014
High Density FOWLP Consortium Forum
Packaging driver for portable / mobile applications
Key drivers/needs
•Smaller form-factor  lower profile, substrate-less
•Higher performance  higher speed, more I/O
•Higher integration  multi chip integrated platform
•Low cost  less processing step, low cost materials
IC-2
IC-1
IC-3
Packaging solutions options
Current
Stacked chip approach
Side-by-side
Conventional PoP, with TMV
Substrate based side-by-side package
PoP with conventional FOWLP
Thin core /coreless subst. with side-by-side die within package
Proposed
package
PoP with high density FO
Multi-chip integrated on low cost high density WLP
Low cost, high density, integrated packaging solutions is needed
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
-No substrate
-Lower profile
-Short interconnect
-Wafer level process
-Lower cost
Flip-Chip BGA
with substrate
Low Cost
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Price per pin(c$)
High Density Multi-Chip Packaging : Cost Comparison
IME’s High Density
Fan-Out WLP
Conventional
Fan-Out WLP
300mm, double RDL
Cost Effective Because :
• Removing Flip-chip BGA substrate
• Minimizing No of RDL layers with Fine L/S (2um/2um)
• Integrating Multi-Chips with Wafer Level Processing
300mm, single RDL
High Density
50
100
350
750
1,500
3,000
I/O counts
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
5,000
Fan-Out Wafer-Level Technology: RDL size vs I/O count
I/O Count
3000
RDL- 1st Fan-Out WLP
(L/S: 2 µm/2 µm)
2000
1000
500
Mold-1st Fan-Out WLP
(L/S: <5 µm/5 µm)
300
100
Current Fan-Out WLP
(L/S: >5 µm/5 µm)
200
100
300
2
Total Silicon Die Area (mm )
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
IME approach on High Density FOWLP
“Mold-first” FOWLP
“RDL-first” FOWLP
Sacrificial layer
Formation of RDL and UBM on Carrier
IC
IC
Chip placement on molding tape on mold frame
Carrier
Die-to-Wafer Bonding
Wafer level molding
IC
Release from mold frame
IC
Wafer Molding
IC
IC
RDL and bumping processing
Support Carrier Removal & bumping
Singulation
IC
IC
Singulation
Target App
Smart phone
Target App
Tablet
Package
15 mm x 15 mm, I/O ~1000, Thickness ~450 µm
Package
20 mm x 20 mm, I/O ~2000, Thickness ~450 µm
Benefits
Existing infrastructure in FOWLP manufacturing
Benefits
Fine Pitch RDL with L/S ≤ 2 µm/2 µm
Challenges
Die shift, wafer warpage, RDL L/S < 10 µm/10 µm
Challenges
Require support wafer
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
Test Vehicle Specs from Industry Feedback
TV 1
TV 2
Mold-1st FOWLP*
RDL-1st FOWLP*
Specifications
• RDL L/S ≤ 5 µm/5 µm, 2 layers
• Package size : 15 mm x 15 mm
• Package I/O count: ~1000
• No of chips: 2 chips /package
• Reliability : MSL3, TCOB 1000
Specifications
• RDL L/S ≤ 2 µm/2 µm, minimum 2 layers
• Package size : 20 mm x 20 mm
• Package I/O count: ~2000
• No of chips: 3 chips / package
• Reliability: MSL3, TCOB 1000
Note: * Spec to be finalized after member’s inputs
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
Challenges & Proposed Solution
Topography with multi-layer
fine RDL
Die shift causing misalignment
Chip-to-Mold non-planarity
•Mold tape and Pick & place process
•Spin-coated dielectric / laminated
dielectric films for surface planarity
Reliability of large FOWLP
•Creep fatigue analysis and life
prediction modeling
•Solder joint design enhancement
•Improved lithography techniques to
compensate die shift
• Establish Design guidelines based
on tool, material & process tolerance
to minimize die shift
Wafer warpage and
moldable UF void
• Mold Compound material, process
and design optimization
• Overmold and die thickness
• Molding void prediction by mold
simulation and design optimization
•PR and photo-dielectric with higher
planarity and smaller via opening
•Cu density uniformity and
incorporating Cu dummy structures
•Sacrificial and carrier removal process
Routability & SI/PI design
•Routing of 2K-3K I/O and reduce
RDL layer
•SI/PI and PDN design for multi-layer
fine RDL
•Develop EDA methodology for PDK
Challenge
Proposed solution
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
Project objective
Development of high density fan-out wafer level package with fine pitch
multi-layer redistribution layer technology, including the following:
Design of Test Vehicle
• High I/O FOWLP with fine RDL routability
• Electrical design, characterization, and PDK development
• Integrated high-Q inductor and antenna
Mold-first and RDL-first fabrication process flow
• Fabrication process development
• Lithography process development
• Photo-resist and dielectric materials
Modeling and Characterization
Sym.
Coupling
Coupling
Sym.
• Die shift and moldable underfill void analysis and prediction
• Structural, material and process analysis for wafer warpage
Coupling
Sym.
• Board level reliability for
large FOWLP
Sym.
Sym.
1/4 global model & submodel
S1
S2
Test vehicle assembly build, Reliability & FA
Sym.
High Density FOWLP Consortium Forum
Sym.
•Test vehicle fabrication and assembly build
•Package and board level reliability testing
•Failure mechanism analysis
Sym.
© 2014 A*STAR Institute of Microelectronics and Proprietary
IME High Density FOWLP Consortium
Member’s Inputs
 Product Roadmap
 Technology, Design requirements
 Performance, reliability
requirements
 Advanced materials, process and
equipments
IME
 300 mm Fab, FOWLP engineering line
 Mold 1st & RDL 1st fabrication process flow
 Design guidelines for reliable FOWLP
 EDA Flow and Fan-Out PDK
OSAT
 Demonstration test vehicle
 Reliability, FA
IME
IDM/
Design,
modeling
and
materials
Fabless
Fine RDL
development
Foundry
Equipment
High
Density
FOWLP
Consortium
Materials
Member benefits
1. End-to-End solution for High Density, Low cost FOWLP for mobile/tablet applications
2. Fan-Out Technology platform for supply chain members to drive and co-develop next
generation FOWLP
3. Extensive foreground data availability based on Member’s requirements.
High Density FOWLP Consortium Forum
© 2014 A*STAR Institute of Microelectronics and Proprietary
Deliverables
 Low cost multi chip, high I/O FOWLP package solution with 2 µm/2 µm RDL line/spacing
 Innovative wafer level fabrication for mold 1st and RDL 1st approach
Fabrication: Mold 1st & RDL 1st
Test vehicle design
• SI/PI prediction with multi-layer RDL
• Manufacturable process flow for
• Parasitic RLC extraction for fine RDL
fine L/S(2 µm/2 µm) RDL
• EDA flow with PDK and Routing Analysis
• Litho process for die shift and topography
• Integrated high-Q inductor and antenna
compensation
• Identify material for carrier and adhesive
of RDL first process
Modeling and design solutions
Assembly, reliability and FA
Sym.
• Design guideline to minimize die
• Assembly flow for 20 mm x 20 mm FOWLP
Shift < 3 µm, wafer warpage < 0.5 mm
Sym.
1/4 global model & submodel
for RDL
process
• Stress analysis of multi-layer fine RDL
Sym.
• Package level
reliability
to meet MSL3
Sym.
Coupling
• Solution for void free moldable underfill
1st
Coupling
Coupling
Sym.
Sym.
• Board
TCOB of
S1 level reliability to meet
S2
1000 cycles and JEDEC drop test
• Failure mechanism of board level reliability
• Design guidelines for reliable FOWLP
of < 20 mm x 20 mm for TCOB
1/8 global model & submodel
High Density FOWLP Consortium Forum
Sym.
Sym.
PBGA solder joint distribution
2D model (2D)
© 2014 A*STAR Institute of Microelectronics and Proprietary