DANH MỤC CÔNG TRÌNH KHOA HỌC ĐÃ CÔNG BỐ

ĐẠI HỌC QUỐC GIA TP HỒ CHÍ MINH
TRƯỜNG ĐẠI HỌC KHOA HỌC TỰ NHIÊN
Khoa Điện tử -Viễn thông
DANH MỤC CÔNG TRÌNH KHOA HỌC ĐÃ CÔNG BỐ
Tên tác giả: NGUYỄN ĐỨC PHÚC
Đơn vị công tác: Bộ môn Máy tính – Hệ thống nhúng, khoa Điện tử Viễn thông
Số
TT
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nơi tổ chức
Vai trò thực hiện
Nơi công bố
1
Nghiên cứu xây dựng giải thuật mã
hóa – mật mã (RSA và ZUC) dùng
trong việc truyền dữ liệu video và cài
đặt phần cứng chuyên dụng phục vụ
cho các ứng dụng về an ninh thông tin.
Từ 10/2013,
Sở KHCN
TPHCM
Thành viên nhóm thực
hiện
Đề tài nghiên cứu khoa
học cấp sở Khoa Học
Công Nghệ TP.HCM
2
Hardware-Software Co-design of an
Embedded System for Noise
Cancellation
11/2013
TPHCM, Việt
Nam
Đồng tác giả
3
A Simple Computer Based on 32-bit
Micropressor and Integrated
Development Environment for
Educational Purpose
11/2012
Đại học Khoa
Học Tự
Nhiên
Đồng tác giả
Hội nghị quốc tế IEICE
về kiểm tra và thiết kế
mạch tích hợp lần IV
(ICDV 2013)
Hội nghị khoa học
Đại học Khoa Học
Tự Nhiên TPHCM
Lần 8
4
An FPGA Implementation of
Ultra-WideBandBased Transceiver
System
5
A Novel Hardware Architecture for
High-throughput and Multiplierless
FFT Processor Using CORDIC
Method
TPHCM
11/2012
Đại học Khoa
Học Tự
Nhiên
03/2012
Okinawa,
Nhật Bản
Đồng tác giả
Hội nghị khoa học
Đại học Khoa Học
Tự Nhiên TPHCM
Lần 8
Đồng tác giả
Cuộc thi thiết kế vi mạch
quốc tế LSI Contest, tổ
chức tại Okinawa, Nhật
Bản
THE INSTITUTE OF ELECTRONICS,
INFORMATION AND COMMUNICATION ENGINEERS
IEICE ICDV 2013
Hardware-Software Co-design of an Embedded System for Noise Cancellation
Duc-Phuc NGUYEN, Cao-Quyen TRAN, Khac-Minh HO, Minh-Triet LUU,
Huu-Thuan HUYNH, Trong-Tu BUI
University of Science, 227 Nguyen Van Cu St., Ward.4, Dist.5,
Ho Chi Minh City, Vietnam
E-mail: { ndphuc, bttu, hhthuan }@fetel.hcmus.edu.vn
Abstract: Adaptive Noise Cancellation (ANC) systems can effectively suppress noise in non-stationary conditions.
However, the drawback of ANC systems is that we need at least two microphones - one for input speech and one for reference
noise. In this paper, we present the hardware-software co-design of Noise Cancellation (NC) based on Spectral Subtraction
(SS) algorithm. By using SS method, noise is estimated during non-speech activities and then it is subtracted from speech in
speech activities. Experimental results have proved that high performance is obtained by using the proposed NC system. In
addition, it can process the input speeches with low SNR ratio ranging widely from -1dB to +20dB.
Keyword: Spectral Subtraction Algorithm, Hardware-Software Co-design, Noise Cancellation.
requirement.
1. Introduction
Acoustic noise background can significantly degrade
In order to overcome the limitations of the original SS
the performance of audio applications such as speech
methods, a NC system imp lemented in the approach of
recognition, speech authentication etc. It should be
hardware-software co-design has been proposed in this
maintained at an acceptable level so that the qualities of
paper. Hardware is implemented to execute processes that
the application will not be affected. ANC is widely used in
take high computational effort. Processes that take less
today speech enhancement application due to the fa ct that
computational effort is executed by software. Several
it can suppress non-stationary background noise without
advantages are obtained when following the approach of
any apriori knowledge of speech and noise. However,
hardware-software co-design. The implemented hardware
besides
speech
can be integrated into various kind of SoC and software
contaminated by acoustic background noise, ANC also
can be written in any appropriate programming language
employs a reference input which correlat ed with noise in
supported by this SoC. Besides, software c an be improved
primary input [1]-[2]. Moreover, if low level signal in
if the performance of the recent version is not optimized.
primary input presents in reference input, it will degrade
The remaining of this paper is organized as followed. In
the performance of ANC significantly. In addition, after
section 2, the SS algorithm is presented. In section 3,
subtracting noise from speech, ANC still leaves residual
detail of the NC architecture is described. The advantages
noise in the resulted speech [3].
of hardware-software co-design are also taken into
the
primary
input
which
contains
An alternative method for NC is SS algorithm. The main
consideration in this section. Section 4 shows the
principle of SS is to achieve enhanced speech by
experimental results. Finally, conclusion is presented in
subtracting estimated noise spectrum from the spectrum of
section 5.
speech
2. Spectral Subtraction Algorithm
affected
limitations
by noise.
when
appl ying
However,
SS
there
algorithm
are
to
two
speech
enhancement.
1. SS method works only with stationary noise,
assuming
that
By applying spectral
subtraction
algorithm,
noise
spectral is subtracted which results in enhanced speech.
background
noise
does
not
change
frequently over time [4].
Assuming that clean speech s(n) is contaminated with
noise d(n), the result speech x(n) can be written as:
x(n) = s(n) + d(n)
(1)
2. The crucial techniques in a typical NC system are
Discrete Fourier Transform (DFT) and Inver se Discrete
Fourier
Transform
(IDFT)
which
require
a
lot
of
computation and execution time. For this reason, a
powerful processor is employed to satisfy real -time
The objective of noise cancellation is to find the enhanced
speech 𝑠̂ from the given x(n) [4]. We also make the
assumption that d(n) is uncorrelated with s(n) which
means that the magnitude spectrum of x(n) is the sum
Copyright ©2013 by IEICE
magnitude spectrum of s(n) and d(n) [5]-[6]. Let X(k), S(k)
computational effort. If we realize these operations in
and D(k) are the spectrum of x(n), s(n) and d(n)
software, a high performance microprocessor is needed.
respectively. So that,
On the other hand when we implement these operations in
(2)
hardware, a high performance microprocessor is not
The estimated spectrum of 𝑆(𝑘) is 𝑆̂(𝑘) and is given as
necessary but speed and accuracy are still guaranteed.
X(k) = S(k) + D(k)
the result of X(k) and spectrum gain G(k):
to remove the estimated noise spectrum from the spectrum
𝑆̂(𝑘) = 𝑋(𝑘)𝐺(𝑘)
(3)
𝐺 = (1 −
√𝜆
of input speech, which takes fewer computational effort.
For this reason, processing step is implemented in
The spectrum gain is expressed as:
𝛽
Besides, the main task of SS method (processing step) is
𝛼
(4)
) ; 0 < 𝛼 < 1 ; 𝛽 ≥ 1.
Where, α, β are correction factor and λ is a priori SNR
(Signal to Noise Ratio) and is derived as:
𝛾−1
If non − negative
𝑦={
0
Otherwise
(5)
and γ is a posteriori SNR,
𝐸(|𝑥𝑘2 |)
𝛾=
𝐸(|𝐷𝑘2 |)
(6)
software. This process can be executed in any embedded
microprocessor. In addition, based on practical result, the
methods of removing noise spectrum from speech can be
improved by changing modifying software.
Another
advantage
of
using
hardware -software
co-design approach in this system comes from NE. The
responsibility of NE is to detect non -speech periods and
update the estimated noise spectrum, assuming that this
period contains only background noise. In order to do that,
NC compares the output spectrum of FFT with a threshold
3. Noise Cancellation Architecture
The proposed NC architecture is illustrated in Fig.1.
The recorded speech is obtained by a microphone and goes
through three following steps: (1) pre -processing, (2)
processing and (3) post-processing step. In pre-processing
step, recorded speech including clean speech an d acoustic
background noise is digitized by ADC, windowed with the
length of 64 samples and subsequently transformed into
the frequency domain by employing FFT (Fast F ourier
Transform). Estimated spectrum of noise is also obtained
by Noise Estimator (NE) in this step. After that, estimated
noise spectrum is then subtracted from recorded speech
spectrum which results in the spectrum of estimated clean
speech. Finally, clean speech is obtained by transforming
the result of processing step back into time -domain. IFFT
(Inverse Fast Fourier Transform) is employed in this step.
value which can be configured to NE by software in run
time. By frequently updating noise threshold during run
time, high performance is obtained even in the condition
of non-stationary background noise.
The NC architecture is targeted to the Altera FPGA
Cyclone IV E (EP4CE115F29C7). This device is a part of
DE2 115 board which includes audio codec interface with
the sampling frequency of 32Khz. Hardware of the
proposed NC is written in Verilog HDL. As illustrated in
Fig.2,
these
two
components,
along
with
NIOSII
embedded microprocessor, audio codec and SDRAM are
integrated to the standard Avalon Bus creating NC system.
Embedded software is written in C language and stored in
SDRAM. The system operates at the frequency of
100MHz.
Figure.1 - Spectral subtraction algorithm block -diagram
The proposed NC system is implemented in both
hardware and software. When implementing NC in the
approach
of
hardware-software
co-design,
several
advantages are achieved. Operation such as FFT/IFFT and
Noise Estimation always process with a high regularity to
all
input
audio
frames.
They
also
take
a
high
Figure.2 - The architecture of the proposed NC system
The processing flow is illustrated as fo llowed:
1. NIOS II microprocessor imports sample data from
audio codec via audio codec controller.
2. CPU pushed every 64-sample data to FFT/IFFT
component. After processed, spectrum of this 64 -sample
lowest SNR ratio of -1dB instead of +10dB in [7].
data is obtained.
3. The result spectrum in step 3 is pushed into NE. NE
determines whether this spectrum belongs to speech
activities or non-speech activities. If it comes from
non-speech
activities,
estimated
noise
spectrum
is
updated.
4. Estimated noise spectrum is removed from the
resulted spectrum in step 2. The estimated spectrum of
Figure.3 - Clean speech
enhanced speech is obtained in this step.
5. CPU imports the estimated spectrum of enhanced
speech to FFT/IFFT components to convert this spectrum
back into time-domain.
6. NIOS II export enhanced speech to audio codec via
audio codec controller.
4. Experimental Result
The proposed NC system is synthesized by Quartus II
software and targeted to Altera FPGA Cyclone IV E
(EP4CE115F29C7). Table 1 shows the hardware resources
employed in this system. It can be seen that, the hardware
utilization of the proposed NC is very small.
Figure.4 - (a) Input speech with SNR=5dB, (b) Speech after
Table.1 - Hardware resource
Available resources
Combinational logic
Register
Memory
Embedded multiplier
Used resources
3,443/114,480
1,000/114,480
77,728/3,981,321
12/532
noise cancelling
Ultilization
3%
1%
2%
2%
Clean speech is recorded in the laboratory environment.
Next, observed speeches are created by adding several
acoustic background noise level. Then, the proposed NC
system is employed to suppress background noise from
observed speeches. Clean speech is illustrat ed in Fig.3. It
can be seen that, between two speech periods (high
amplitude period), there is a non -speech period (small
amplitude
section).
In
Fig.4a
and
Fig.5a,
acoustic
background noise is added to the clean speech creating
Figure.5 - (a) Input speech with SNR= -1dB, (b) Speech after
input speech with the SNR ratio of +5dB and -1dB
respectively.
NE
updates
noise
spectrum
noise cancelling.
during
The proposed NC system can operate at real -time with
non-speech periods because these periods contain only
an
background noise. Then, noise spectrum is removed from
performance digital signal processor. The reason is high
speech in speech period resulting in estimated clean
computational techniques such as FFT/IFFT and noise
speech. Fig.4b and 5b illustrate the estimated clean speech.
estimation are implemented in hardware. In order to
Even though the amplitude of estimated clean speech is
emphasize the advantage of hardware -software co-design
smaller than the actual clean speech, the information of
method, the same SS method was also written in C
speech is still guaranteed. Besides, residual noise is
language and executed by NIOS II microprocessor [8].
maintained at a low level after noise suppression. The
Obviously, it is unable to run at real-time because the
proposed NC system can process the input speech with
majority of execution time was taken to compute FFT and
embedded
microprocessor
instead
of
a
high
IFFT. Table 2 compares the performance of the proposed
conventional SS-based NC, a spectral subtraction noise
NC system with the embedded software NC system.
cancellation
NC
architecture
Pre-processing
latency
Processing
latency
Post-processing
latency
Total
Embedded
NC
software
Our
proposed
NC system
Speed
up
17.43 ms
2.11 ms
8.23
1.98 ms
1.98 ms
1
15.47 ms
2.08 ms
7.4
34.88 ms
6.17 ms
5.65
The latency in pre-processing and post-processing also
includes the execution time of audio codec (2ms). NC
software takes approximately 17.5ms to compute FFT and
estimated noise spectrum and takes 13.5ms to compute
IFFT. On the other hand, the result of FFT - estimated
noise spectrum and IFFT can be provided immediately by
using the proposed NC system - at maximum, a period of
200 clock pulses is required for each operation. Besides,
the latency of processing-step only takes 1.98ms which is
smaller than the operation of audio codec (2ms). For this
reason, the requirement of realtime is guaranteed .
Table 3 compares the execution time of the NC system
proposed in this paper with the ANC system proposed in
[9]. Although the ANC operates at higher frequency and
the microprocessor is more powerful, the execution time
of our proposed NC is 6 times faster.
Table.3 - Execution time comparation
Features
Microprocessor
Our proposed
NC
Embedded NIOS
II
The ANC
proposed in [9]
TMS320C6713
DSP
100
225
6,17
38.95
Operation
speed (MHz)
Execution time
(ms)
implemented
in
the
approach
of
hardware-software co-designed has been proposed in this
Table.2 - Execution time and speed up
An additional experiment was also carried out to
evaluate performance of the NC hardware. When the NC
hardware operates at the speech of 1MHz independently, it
only takes 0.2 ms for the NC hardware to calculate the
input speech spectrum and the estimated noise spectrum.
The same amount of time is needed for post-processing
step. For this reason, the requirement for realtime is still
guaranteed when integrating this hardware into other SoC
rather than Altera Media Computer with an embedded
NIOS II microprocessor.
5. Conclusion
In order to overcome the limitations of ANC and
paper. Processes that take a lot of computation and operate
with a high regularity are implemented in hardware.
Software executes processes that take fewer computational
effort.
For
this
reason,
the
employment
of
high
performance digital signal processor is not necessary.
Experimental results show that, the proposed NC system
can suppress noise at the speed of 5.68 times faster than
the embedded software NC system. The quality of
estimated speech can be guaranteed even if the SNR ratio
of the input speech is very low ( -1dB). Besides, by
updating noise threshold during run time, non -stationary
background noise can also be suppressed. In addition,
after noise suppressing, residual noise is maintained at a
low level.
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