As Published on EN

Operational Amplifier Stability
Part 9 of 15: Capacitive Load Stability: Output Pin Compensation
by Tim Green
Linear Applications Engineering Manager, Burr-Brown Products from Texas Instruments
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Part 9 of this series is the fifth verse of our familiar electrical engineering tune, “There must be six
ways to leave your capacitive load stable.” The six ways are: Riso, High Gain & CF, Noise Gain,
Noise Gain & CF, Output Pin Compensation, and Riso w/Dual Feedback. In Part 9, here, we cover
Output Pin Compensation. This stability technique is NOT the same as an output op amp snubber
network, which is often used on the output of power operational amplifiers (with all-npn output stages)
to stop undesired, high-frequency oscillations when driving capacitive loads. Details of the use of the
snubber network will be discussed in a later part of this article series.
on
EN
-G
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Sometimes, in the real world, we do not always have access to the –input and/or +input of the op amp
to allow us to use other compensation tricks in our analog tool box. Here we will derive the Output Pin
Compensation technique for both emitter-follower output op amps and also CMOS RRO op amps. The
emitter-follower application will entail a reference output on a unique 4 - 20 mA building block
integrated circuit. The CMOS RRO application involves a difference amplifier used in the feedback for
a power supply. Both of these definition-by-example cases are real-world applications where we will
conclude our only stability option is Output Pin Compensation. In addition to first-order analysis and
TINA Spice simulation, real-world implementation has been completed with as-predicted results.
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Bipolar Emitter-Follower: Output Pin Compensation
Pu
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Our bipolar emitter-follower Output Pin Compensation case is shown in Fig. 9.1. The XTR115/XT116
is a two-wire, 4 - 20 mA IC that can translate an input voltage change into an analog 4 - 20 mA signal.
Since the 4 - 20 mA transmitter is intended to drive long wires, it needs a wide operating voltage range
of 7.5 V to 36 V. Additionally, the XTR115/XTR116 has a sub-regulator to provide 5 V to power
sensor conditioning circuitry and a precision reference of 2.5 V (XTR115) or 4.096 V (XTR116).
As
The 4 - 20 mA signal range is a well-established industrial standard intended to transmit analog signals
over long distances (over 1 mile or 1.6 km) in noisy environments, such as factories, where 50 Hz or
60 Hz large voltage noise is prevalent. Since the standard is a current controlled transmission, it is
immune to voltage noise coupling into its two wires. Power and signal are transmitted over the same
two wires. Since the useable analog signal range is defined as 4 - 20 mA, up to 4 mA is allowed to
power the signal conditioning circuitry and excite a sensor at the transmitter end of the two wires.
Power is provided by the receiver which also receives the analog 4 - 20 mA signal, which has been
scaled to correspond to a sensor’s measurement of real-world parameters such as pressure from a
bridge pressure sensor. At the receiver end, the 4 - 20 mA signal is often converted to a voltage (1 V to
5 V) across a resistor (250 ) to be read by an ADC.
Often times in such a 4 - 20 mA sensor transmitter a microcontroller is used to read and apply
linearization constants to the real-world sensor. The microcontroller must be low power to allow some
current to excite the sensor since our total conditioning circuit current budget must be less than 4 mA.
The MSP430F2003 provides a low-voltage, low-quiescent current microcontroller and has an on-board
ADC to read the bridge changes. After the microcontroller applies its linearization constants it talks to
the DAC8832, a low-power DAC to create the required analog input voltage to the XTR115/XTR1116.
The DAC8832 is buffered by a zero-drift, low-power, single-supply op amp, OPA333. Since we have
an absolute system we can power everything from the accurate VREF pin of the XTR115/XTR116.
We choose the XTR115 (2.5-V VREF) since the MSP430F2003 can only operate from 1.8 V to 3.3 V.
Now the on-board ADC of the MSP430F2003, as well as the DAC8832, will use the precision 2.5-V
reference of the XTR115. Our total, typical conditioning circuit quiescent current is 562 A, which
leaves up to 3.4 mA to excite our bridge sensor. Our only challenge now is that we need to add many
local bypass capacitors for good, high-frequency bypass near the many ICs powered from the VREF
pin of the XTR115. Will the XTR115 VREF pin be stable?
Transmitter
0.1 μF
V REF
V REF
0.1μF
0.1 μF
V REF
0.1 μF
C5
STABLE
V REF
C2
C1
A V cc
MSP430F2003
C3
VREF V DD
DAC8832
A DC
0.1 μF
-G
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DV cc
I RET
-
+
OPA333
DV ss
A V ss
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on
EN
IRET
Pu
bl
V REF
As
Bridge
Pressure
Sensor
C4
ne
t
V REF
IRET
Fig. 9.1: 4 - 20-mA Bridge Sensor Application
Receiver
V LO O P
In Fig. 9.2 we detail the key specifications for the ICs used in our 4 - 20 mA bridge sensor conditioner
application.
XTR115/XTR116
2-Wire 4-20mA Current Loop Transmitter
DAC8832
16-Bit, Ultra-Low Power, Voltage-Output, Digital-to-Analog Converter
Parameter
Supply Voltage Range
Quiescent Current
Specification
7.5V to 36V
240uA typical
Parameter
Resolution
Supply
SubRegulator
5V
Quiescent Current
5uA typical
VREF for Sensor Excitation
2.5V (XTR115), 4.096V (XTR116)
Linearity Error
+/-0.5LSB typical
+/-0.05% typical
Differential Linearity Error
+/-0.5 typical
+/-20ppm/C typical
Gain Error
+/-+/-1LSB typical
VREF Drift
VREF PSR +/-1ppm/V (V+ = 7.5V to 36V)
VREF vs Load
VREF Noise
Span Error
NonLinearity Error
Package
+/-100ppm/mA (IREF = 0mA to 2.5mA)
10uVpp typical (0.1Hz to 10Hz)
0.05% typical
0.003% typical
SO-8
Gain Drift
+/-0.1ppm/C typical
Zero Code Error
Zero Code Drift
Package
+/-0.25LSB typical
+/-0.05ppm/C
QFN-14
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VREF Accuracy
Specification
16 Bit
2.5V to 5.5V
MSP430F2003
1.8V, microPower CMOS Operational Amplifier, Zero-Drift Series
1.8V, microPower CMOS Operational Amplifier, Zero-Drift Series
Parameter
Supply Voltage
Quiescent Current
Offset Voltage
Parameter
Supply Voltage
Quiescent Current
Architecture
A/D Converter
Watchdog Timer
Flash
RAM
Port 1
Port 2
Interface
Clock
Package
EN
on
Offset Drift
Input Bias Current
Input Voltage Noise
Input Voltage Range
Gain-Bandwidth Product
Slew Rate
Voltage Output Swing from Rail
Package
Specification
1.8V to 5.5V
17uA typical
2uV typical
0.02uV/C typical
+/-70pA typical
1.1uVpp (0.1Hz to 10Hz)
(V-)-0.1V to (V+)+0.1V
350kHz
0.16V/us
30mV typical (RL=10k)
SOT23-5, SC70-5, SO-8, DFN-8
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OPA333
Specification
1.8V to 3.6V
300uA typical (Active Mode, 1MHz)
16-bit RISC
16-Bit Sigma-Delta
1k Byte + 256 Byte
128 Byte
8 I/O
Xtal or 2 I/O
Universal Serial (SPI, I2C), Port 1
Internal, External 32kHz crystal
TSSOP-14, DIP-14, QFN-16
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Fig. 9.2: Key Specifications For 4 - 20-mA Conditioning Circuit ICs
As
Pu
bl
The XTR115 VREF pin is the output of an emitter-follower output topology as shown in Fig. 9.3.
Fig. 9.3: XTR115 VREF Pin: Emitter-Follower Output Op Amp
Fig. 9.4 shows the equivalent circuit of the XTR115 VREF pin. VREF is a buffered 1.25-V bandgap
reference which is amplified by x2 to yield the XTR115 2.5V reference output. The emitter-follower
output stage has an Ro of 4.7 k. This information, along with values for RF and RI and the Aol curve
of U1, were obtained from the factory as it is not given in the data sheet. Our total capacitive load, CL,
is seen to be 500 nF. Ro will interact with CL to form a second pole, fpu1, in the modified Aol curve
for the XTR115 VREF op amp. Note that we have no access to the –input or +input of U1 since it is
internal to the XTR115. This leaves us with only one pin to compensate the amplifier for stability (the
output pin: VREF). Also note that we want the VREF pin to remain extremely accurate, and so putting
any resistance in series with this pin before CL is not an acceptable solution.
Op Amp Aol Curve is Modified by
extra pole (fpu1) due to Ro and CL
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CL = C1+C2+C3+C4+C5
RF114k
-G
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s.
fpu1 = 1/(2 *Ro*CL)
fpu1 = 1/(2 *4.7k*500nF)
fpu1 = 67.73Hz
U1!OPAMP
RI114k
-
Ro4.7k
VREF
++
EN
V+24V
Vbg 1.25V
C1100nF
C3100nF
C4100nF
C5100nF
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on
XTR115 VREF Equiv alent Circuit
VREF = 2.5V
C2100nF
Fig. 9.4: XTR115 VREF Pin: Capacitive Load, Equivalent Schematic
Pu
bl
We will use the TINA Spice circuit of Figure 9.5 to examine the Aol curve of the op amp and the
modified Aol curve due to CL. We use our Spice ac analysis trick by using LT, short at dc and an open
at ac frequencies of interest, and CT, open at dc and a short at ac frequencies of interest.
As
CT1TF
RF114k
LT1TH
Aol = VOA/VM
Modif ied Aol = VREF/VM
VM
VOA
Ro4.7k
RI114k
U1!OPAMP
Vbg1.25V
VT
+
1/Beta = VT/VM
Loop Gain = VREF/VT
VREF
++
V+24V
CL500nF
Fig. 9.5: Ac Stability Check: Original Circuit
Fig. 9.6 shows the op amp Aol curve and the modified Aol curve due to CL. At fcl1, we see a
40 dB/decade rate-of-closure which is unstable by our first-order stability criteria. Our predicted fpu1
due to CL was 67.73 Hz which from inspection looks to be correct in this plot.
T
100.00
80.00
60.00
Aol
40.00
Modified Aol
fcl1
Gain (dB)
20.00
0.00
ne
t
1/Beta
STABLE
-G
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-20.00
-40.00
-60.00
-80.00
1
10
EN
-100.00
100
1k
10k
100k
1M
10M
on
Frequency (Hz)
Fig. 9.6: Aol And Modified Aol: Original Circuit
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A loop-gain plot in Fig. 9.7 confirms our concerns with phase margin almost zero (0.442°!) at fcl1.
T 100
80
Loop Gain
40
20
0
-20
As
Gain (dB)
Gain:
Loop A:(5.79k;-167.74m) B:(5.76k;-82.95m)
Phase :
Loop A:(5.79k;436.85m) B:(5.76k;442.2m)
Pu
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60
a
-40
-60
-80
-100
1
10
100
fcl1
1k
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
b
180
135
Loop Gain
Phase [deg]
90
STABLE
45
0
-45
-90
1
10
100
1k
Frequency (Hz)
Fig. 9.7: Loop-Gain Plot: Original Circuit
In Figure 9.8 we do a transient stability test by injecting a small square wave into our closed loop
circuit with CL of 500 nF attached.
RF114k
VM
VOA
Ro4.7k
RI 114k
U1!OPAMP
VREF
++
VG1
-G
en
iu
s.
+
CL500nF
ne
t
V+24V
Vbg 1.25V
50mVp
100Hz
EN
Fig. 9.8: Transient Stability Test: Original Circuit
T
is
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on
Our transient stability plots in Figure 9.9 indicate, again, that our circuit is not stable. Our op amp
output never settles in response to a small step change. Note that VOA is transitioning about 2.5 V,
indicating that our dc levels are correct for this circuit.
1.00m
-1.00m
1.25268
As
VM
Pu
bl
VG1
1.24740
2.84161
STABLE
VOA
2.23870
2.50422
VREF
2.49348
0.00
1.00m
Time (s)
Fig. 9.9: Transient Stability Plots: Original Circuit
2.00m
In Fig. 9.10 we identify the technique for Output Pin Compensation for bipolar emitter-follower output
amps. First we modify the op amp’s original Aol curve with fpu1, the pole due to Ro and CL (see
Curve 1). Once this curve is created, we plot a second curve (Curve 2) which starts where the Curve 1
intersects 0 dB. From this starting point we plot back at -20 dB/decade to a point which is one decade
above fp1 (the op amp Aol low frequency pole) where we change the slope to -40 dB/decade. At fp1
frequency we change the slope back to –20 dB/decade until we intersect the dc Aol value of the op
amp. This proposed modified Aol curve (Curve 2) meets all of our rule-of-thumb criteria by keeping
poles and zeros within one decade of each other to keep loop gain phase from dipping below 45°
within the loop-gain bandwidth. Our proposed modified Aol curve (Curve 2) will also meet our firstorder stability criteria of 20 dB/decade rate-of-closure at fcl2.
120
First pass at stability:
fp1
100
Aol
ne
t
Create Modified Aol with Ro, RCO, CCO
(Curve 2) which is less in frequency at all
points than Modified Aol with Ro, CL (Curve 1).
fpu1
80
fpc2
1/ intersects with Modified Aol from Ro, RCO,
CCO (Curve 2). Therefore CL effect is never
seen for loop gain stability!
Gain (dB)
60
Proposed
Modified Aol
40
fzc1
2
1
fcl1
EN
20
0
fcl2
on
Acl
is
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-20
10dB
fp2
fpc4
Modified Aol due
to CL and RO
-40
1
10
STABLE
1K
10K
Frequency (Hz)
Curve 2
100K
fpu2 1M
10M
STABLE
As
Curve 1
100
Pu
bl
-60
-G
en
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s.
fpc1
Fig. 9.10: Output Pin Compensation: Bipolar Emitter-Follower
Fig. 9.11 shows how we will get our proposed modified Aol curve by using RCO and CCO. There will
be an additional pole we will have to also consider since, at some high frequency, CCO will become a
short and CL and RCO will form an additional high-frequency pole. If this pole occurs beyond fcl2, we
will still be okay.
VT
+
CT1TF
RF114k
LT1TH
Aol = VOA/VM
VM
Modif ie d Aol = VREF/VM
1/Beta = VT/VM
Lo op Gain = VREF/VT
VOA
RI114k
U1!OPAMP
Ro4.7k
VREF
++
V+24V
RCO75
CL500nF
-G
en
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s.
ne
t
Vbg1.25V
CCO22uF
Fig. 9.11: Ac Stability Check: Output Pin Compensation
on
EN
Since we know Ro and CL we can use the formulae in Fig. 9.12, in conjunction with our proposed
modified Aol curve in Fig. 9.10 (Curve 2), to compute our compensation components RCO and CCO
along with the extra high-frequency pole formed by RCO and CL.
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Ro = 4.7k _ , RCO = 75 _ , CCO = 22 F, CL = 500nF
fpc1 = 1/[2 *(Ro+RCO )*CCO]
Pu
bl
fpc1 = 1/[2 *(4.7k _ +75_ )*22 F] = 1.5Hz
As
fpc2 = fp1 = 10Hz
(Low frequency pole from op amp Aol curve)
fzc1 = 1/(2 *RCO*CCO)
fzc1 = 1/(2 *75 _ *22 F) = 96.5Hz
fpc3 = 1/[2 *(Ro//RCO)*CL]
fpc3 = 1/{2 *[(Ro*RCO)/( Ro+RCO )]*CL}
If: RCO < 10*Ro and CCO > 10*CL
Then: fpc3 ~ 1/[2 *RCO*CL]
fpc3 ~ 1/[2 *75 _ *500nF] = 4.2kHz
fpc4 = fp2 = 1MHz
(High frequency pole from op amp Aol curve)
Fig. 9.12: Output Pin Compensation Formulae: Bipolar Emitter-Follower
In Fig. 9.13 we plot our predicted curves using Output Pin Compensation. Since our closed-loop op
amp inside the XTR115 runs at a gain of x2 (6 dB), the closed-loop VREF/VIN curve will remain flat
until it intersects with our modified Aol at fcl2, where it will then follow the modified Aol curve on
down since loop gain has gone to zero.
120
fp1
fpc1
100
Aol
80
fpc2
1/
20
fzc1
fcl2
STABLE
fpc3
0
fp2
VREF/VIN
-20
-40
1
10
100
EN
-40 dB/decade
slope
1K
10K
Frequency (Hz)
100K
1M
10M
fpc4
is
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on
-60
ne
t
Final
Modified Aol
40
-G
en
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s.
Gain (dB)
60
Pu
bl
Fig. 9.13: Final Predicted Curves: Output Pin Compensation
As
Fig. 9.14 is the result of our ac stability analysis TINA Spice simulation using the circuit of Fig. 9.11.
At fcl2 it looks like 20 dB/decade rate-of-closure, but we should look at a phase plot for more detail.
T
100
80
Aol
60
40
Gain (dB)
fcl2
1/Beta
20
0
Final
Modified Aol
???
STABLE
???
-20
-40
ne
t
-60
-G
en
iu
s.
-80
-100
10
1
100
1k
10k
100k
1M
10M
Frequency (Hz)
EN
Fig. 9.14: Aol And Modified Aol: Output Pin Compensation
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Our loop gain plot shown in Figure 9.15 confirms that our Output Pin Compensation will yield a stable
circuit. At fcl2 we have a 40º phase margin with phase not dipping much below 45º inside the loop
gain bandwidth. If we wanted to we could adjust Output Pin Compensation values slightly to gain
more phase margin at fcl2.
T 100
80
Gain :
Loop A:(4.96k; 8.14m) B:(4.95k; 27.84m)
Phase:
Loop A:(4.96k; 40.37) B:(4.95k; 40.41)
Loop Gain
60
Pu
bl
40
Gain (dB)
a
20
0
-20
As
-40
-60
-80
-100
1
10
100
fcl2
1k
10k
100k
1M
10M
10k
100k
1M
10M
Frequency(Hz)
b
180
135
STABLE
Loop Gain
Phase [deg]
90
45
0
-45
-90
1
10
100
1k
Frequency(Hz)
Fig. 9.15: Loop Gain: Output Pin Compensation
The circuit in Fig. 9.16 uses our transient stability test to check our final circuit using Output Pin
Compensation.
RF114k
VM
VOA
Ro4.7k
RI114k
U1!OPAMP
VREF
++
V+24V
Vbg1.25V
VG1
CL500nF
ne
t
+
RCO75
1mVp
-G
en
iu
s.
1kHz
CCO22uF
EN
Fig. 9.16: Transient Stability Test: Output Pin Compensation
on
Our transient stability test results in Fig. 9.17 confirm our loop-gain check that our Output Pin
Compensation produced a stable circuit. A small overshoot and one undershoot with no excessive
ringing looks close to a typical 45° phase margin compensated circuit.
1.00m
is
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d
T
Pu
bl
VG1
-1.00m
1.25174
1.24845
2.84662
As
VM
VOA
2.22992
2.50229
VREF
2.49564
0.00
1.00m
Time (s)
Fig. 17: Transient Stability Plot: Output Pin Compensation
2.00m
The TINA Spice circuit in Fig. 9.18 allows us to see if our final VREF/VIN closed-loop ac response is
as we predicted in Fig. 9.13.
RF114k
VOA
Ro4.7k
RI114k
U1!OPAMP
V+24V
Vbg1.25V
RCO75
+
CL500nF
ne
t
VIN
VREF
++
AC
1Vpk
-G
en
iu
s.
CCO22uF
Fig. 9.18: VREF/VIN Ac Circuit: Output Pin Compensation
20
0
VREF/VIN
-40
Pu
bl
Gain (dB)
-20
is
he
d
T
on
EN
From Fig, 9.13 we estimate fcl2 to be at around 5 kHz and thus expect a sharp roll-off at this point for
VREF/VIN. In Fig. 9.19 we see the closed-loop ac response is as predicted. There is a slight peaking
which, for this application, causes no concern but if we desired to reduce it we would need to go
through one more pass of our Compensation and increase the phase margin at fcl2 to greater than 40°.
-60
-100
1
As
-80
10
100
1k
fcl2
10k
100k
1M
10M
10k
100k
1M
10M
Frequency(Hz)
0
Phase [deg]
-45
VREF/VIN
-90
-135
-180
-225
1
10
100
1k
Frequency(Hz)
Fig. 9.19: VREF/VIN Ac Response: Output Pin Compensation
CMOS RRO: Output Pin Compensation
Our CMOS RRO Output Pin Compensation case is shown in Fig. 9.20. This real-world power supply
application uses an OPA569 power op amp as a programmable power supply. For accurate power
supply voltage across the load a difference amplifier, INA152, is used to monitor the voltage
differentially across the load.
The closed-loop system then will correct for any losses due to wire drops in either the positive or
negative connection from the programmable power supply to the load. The current limit on the
OPA569 is set for 2 A. In our actual application this power supply has flexible configurations, and as a
result can end up with up 10 nF of capacitance on the output of the difference amplifier.
Sense
U1INA152
CX10nF
-
U2OPA569
N
O M
M 1
R
on
1
R
Iset
Pu
bl
+ +
Vadjust3.3V
Imon
En
VCC
As
CF100nF
is
he
d
RI100k
VCC
0
5
7
T
E
S
R
+
EN
k
6
7
.
5
3.299 971V
???
STABLE
???
+
Ref
VFB
-
-G
en
iu
s.
3.299 972V
VDIFF
ne
t
Is this going to result in a stable operation of our programmable power supply?
VCC5V
VOUT
3.299 844V
Iflag
Ta
lf g
M
1
RLoad1.8
2
R
Figure 9.20: Programmable Power Supply Application
In Fig. 9.21 are the key specifications for the ICs used in our programmable power supply application.
INA152
Single Supply Difference Amplifier
OPA569
Rail-to-Rail I/O, 2A Power Amplifier
Parameter
Supply Voltage
Quiescent Current
Offset Voltage
Parameter
Thermal Protection
Adjustable Current Limit
Current Limit Warning Flag
Temperature Warning Flag
Shutdown w/Output Disable
Current Monitor Pin
Supply Voltage
Quiescent Current
Offset Voltage
ne
t
Specification
Shutdown at +150C
+/-0.2A to +/-2.2A
Normal = V+, Current Limit = VLow = >+147C, High =<+130C
>(V-)+2.5V = enabled, <(V-)+0.8 = disabled
Imonitor = Iout/450
2.7V to 5.5V
9mA typical, 0.01mA in Shutdown
+/-0.5mV typical
Offset Drift +/-1.3uV/C typical
Input Bias Current
+/-1pA typical
Input Voltage Noise
8uVpp (0.1Hz to 10Hz)
Input Voltage noise
12nV/rt-Hz (1kHz)
Input Voltage Range
(V-)-0.1V to (V+)+0.1V
Gain-Bandwidth Product
1.2MHz
Slew Rate
1.2V/us
Voltage Output Swing from Rail
150mV typical (Iout=+/-2A)
Package
SO-20 Power Pad
-G
en
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s.
Specification
2.7V to 20V
500uA typical
+/-250uV typical
Offset Drift +/-3uV/C typical
Input Impedance Differential
80k typical
Input Impedance Differential
80k typical
Common Mode Rejection
94dB typical
Output Voltage Noise
2.4uVpp (0.1Hz to 10Hz)
Output Voltage noise
10nV/rt-Hz (10kHz)
Input Voltage Range
2(V-) to 2(V+)-2V
Bandwidth
800kHz
Slew Rate
0.4V/us
Gain
1V/V typical
Gain Error +/-0.01% typical
Gain Drift +/-1ppm/C typical
NonLinearity +/-0.002%FS
Voltage Output Swing from Rail
20mV typical (RL=10k)
Package
MSOP-8
Fig. 9.21: Key Specifications For Programmable Power Supply ICs
As
Pu
bl
is
he
d
on
EN
The INA152 difference amplifier we use for feedback is a CMOS RRO topology (see Fig.9.22).
Fig. 9.22: INA152 Difference Amplifier: CMOS RRO
We use the TINA Spice circuit in Fig. 9.23 to check for stability of our programmable power supply.
Our dc output is set by Vadjust to be 3.3 V and a small transient square wave will be applied to look
for overshoot and ringing.
VDIFF
U1INA152
CX10nF
+
Ref
k
6
7
.
5
0
5
7
T
E
S
R
N
O
M
R
RI 10k
-
+
VCC
CF1nF
Iset
Imon
M
1
1
R
VOUT
Iflag
ne
t
VFB
-
Sense
U2OPA569
VG1
+
M
1
VCC
D C = 0V
VCC5V
Transient:
RLoad1.8
Ta
lf g
En
Vadjust 3.3V
2
R
100mVpk
1kH z
EN
10ns rise & f all
-G
en
iu
s.
+ +
Fig. 9.23: Transient Stability Test: Original Circuit
T
is
he
d
on
In Fig. 9.24 the results of our transient stability test are clearly undesirable. This is not a circuit we
want to go to production without some additional stability compensation.
3.50
3.03
3.41
As
VFB
3.18
100.00m
STABLE
Pu
bl
VDIFF
VG1
-100.00m
3.42
VOUT
3.17
0.00
350.00u
Time (s)
Fig.9.24: Transient Stability Plot: Original Circuit
700.00u
The TINA Spice circuit in Fig. 9.25 is used to see if the instability in our original circuit is due to the
CX load on the output of the INA152. We will use a transient stability test for a quick check.
VDIFF
2.50005V
-
Sense
U1INA152
CX10nF
+
+
Ref
VCC
VCC
-G
en
iu
s.
ne
t
VCC5V
Vdc2.5V
DC = 0V
Trans ient:
100mVpk
+
EN
1kHz
10ns rise & fall
RLoad1.8
VG1
on
Fig. 9.25: Difference Amplifier Feedback: Original Circuit
Fig. 9.26 confirms our theory of CX causing instability on the difference amplifier INA152.
Pu
bl
VDIFF
is
he
d
2.68
T
STABLE
As
2.26
100.00m
VG1
-100.00m
0.00
350.00u
Time (s)
700.00u
Fig. 9.26: Transient Plots: Difference Amp Feedback, Original Circuit
The difference amplifier consists of an op amp and four precision ratio-matched resistors. This
presents us with a challenge for analysis since we do not have direct access to the –input or +input of
the internal op amp. In Fig. 9.27 we see the equivalent circuit for the difference amplifier and a clever
way we can measure the Aol. We will use LT to break open the feedback for any ac frequencies of
interest and still retain an accurate dc operating point (LT is short for dc, open for ac frequencies of
interest). By connecting the Ref pin of the INA152 to the VIN+ pin we create a non-inverting input
amplifier. By placing LT between Sense and VOA we will essentially be driving the op amp open loop
at any ac frequency of interest. VM, the internal node for the INA152 op amp will be at zero for ac
frequencies of interest. VP will simply be VG1 and we easily can measure Aol = VOA/VG1. Note that
we scale the dc operating point by setting VdcBias to 1.25 V to yield 2.5 V on VOA for dc.
V15V
+V
7
At DC LT = Short
VOA dc = VdcBias (1+R2/R1)
VOA dc = 1.25 (1 + 40k/40k) = 2.5V
INA152_TG
R240k
VM
-
VP
+
5
Sense
LT1TH
INA152OpAmp
6
-G
en
iu
s.
VOA
At any f requency of interest LT f orces op amp
open loop and VM is esentially 0V AC.
VP = VG1 since VIN+ and Ref are connected to VG1
ne
t
R140k
2
VIN-
Theref ore:
Aol = VOA/VG1
VdcBias1.25V
3
R340k
1
R440k
VIN+
VG1
Ref
+
4
AC = 1Vpk
EN
DC = 0V
on
-V
is
he
d
Figure 9.27: INA152 Aol Test Circuit Concept
Pu
bl
We translate our INA152 Aol Test Circuit Concept of Figure 9.27 into a TINA Spice circuit here (see
Fig. 9.28. We know that the TINA Spice macro-model for the INA152 is a Bill Sands [Consultant,
Analog & RF Models, http://www.home.earthlink.net/%7Ewksands/ ] macro-model and, thus, will
accurately match the real silicon.
Aol = VOA/VG1
As
LT1T
-
Sense
VOA
U1INA152
+
+
V15
VdcBias1.25
VG1
Ref
+
DC = 0V
AC = 1Vpk
Fig. 9.28: TINA Spice INA152 Aol Test Circuit
2.499925V
Fig. 9.29 gives us the detailed Aol curve for the INA152 from our TINA Spice simulation. Note that
there is a second pole in the Aol curve at about 1 MHz with some higher-order poles beyond that based
on the Aol phase curve which, beyond 1 MHz, shows a slope steeper than –45°/decade.
T 120
INA152 Op Amp Aol
100
80
Gain (dB)
60
40
20
0
-20
-40
-60
1
10
100
1k
10k
100k
1M
10M
0
ne
t
Frequency(Hz)
fp1=3.64Hz
-45
INA152 Op Amp Aol
45 degree/decade slope
-G
en
iu
s.
Phase [deg]
-90
-135
-180
fp2? = 1MHz
-225
-270
-360
10
1
100
1k
EN
-315
10k
100k
1M
10M
on
Frequency(Hz)
is
he
d
Fig. 9.29: INA152 Aol TINA Spice Results
As
Pu
bl
Since we know the INA152 is a CMOS RRO difference amplifier, in addition to the Aol curve, we will
need Zo to attempt any analytical stability analysis. In Fig. 9.30 we develop a Zo Test Circuit Concept.
Similar to our Aol Test Circuit of Fig. 9.28, we can force the internal op amp of the INA152 to be open
loop for any ac frequencies of interest through the use of LT and the circuit connections as shown.
Now we will drive the output with an ac current source, set to 1 Apk, and measure Zo directly by the
voltage at VOA.
V15V
+V
7
At D C L T = Sho rt
VOA dc = Vd cBias (1+R 2/R 1)
VOA dc = 1.25 (1 + 40k/40 k) = 2 .5 V
IN A152 _TG
2
R140k
VIN-
R240k
5
Sense
-
VP
+
Sinc e IT = 1 Apk
Zo = VOA
LT1TH
INA152OpAmp
VM
At an y freque ncy o f interest LT force s op amp op en lo op
6
VOA
VdcBias1.25V
3
R340k
R440k
VIN+
1
Ref
IT
4
DC = 0A
AC = 1Apk
-V
Fig. 9.30: INA152 Zo Test Circuit Concept
In Fig. 9.31 we build our TINA Spice INA152 Zo Test Circuit. A quick dc analysis confirms we are at
the proper dc operating point for the INA152. It is always a good idea to perform a dc analysis before
running an ac one in Spice to confirm that the circuit is not saturated at either supply rail -- causing an
erroneous ac analysis results.
-
LT 1T
Sense
VF1
U1INA152
+
+
Ref
ne
t
VdcBias 1.25
2.499925V
IG1
-G
en
iu
s.
V15
EN
Fig. 9.31: INA152 Zo TINA Test Circuit
T 100k
on
Zo :
1
Pu
bl
100
Phase [deg]
VOA A:(4.052664;-45.24079) B:(76.172667;-45.321206)
is
he
d
Zo (ohms)
1k
10
a
100
1k
10k
100k
1M
Frequency (Hz)
b
As
0
VOA A:(4.052664;22.546871k) B:(76.172667;2.165303k)
Phase :
10k
-45
-90
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Fig. 9.32: INA152 TINA Zo Curves
The results of our TINA Zo test in Fig. 9.32 show a typical CMOS RRO response for Zo. We see a
zero at fz = 76.17 Hz and a pole at fp = 4.05 Hz.
T
a
100k
Zo :
VOA A:(552.168823k; 1.448248k)
Zo (ohms)
10k
1k
100
1
10
100
1k
10k
100k
1M
10M
1M
10M
Frequency(Hz)
ne
t
-45
-G
en
iu
s.
Phase [deg]
0
-90
10
1
100
1k
10k
100k
Frequency(Hz)
EN
Fig. 9.33: INA152 Tina Ro Measurement
on
In Fig. 9.33 we measure Ro from our Zo curves created by TINA Spice. Ro = 1.45 k.
is
he
d
From our measured Zo plots we know Ro, fz, and fp. This information allows us to build our
equivalent Zo model for the INA152 (see Fig. 9.34).
As
Pu
bl
RO = 1.45k _
fz = 76.16Hz
fp = 4.05Hz
-IN
+IN
RX
CO
+
-
VOUT
+
Aol
+
-
RO
GM2
GMO
-
fz =
2*
1
*RO*CO
76.16Hz =
fp =
2*
1
4.05Hz =
2 * *1.45k*CO
CO = 1.44 F
1
*RX*CO
1
2 * *RX* 1.44 F
RX = 27.29k _
Fig. 9.34: INA152 Zo Model
We can use our TINA Spice simulator to quickly check the accuracy of our equivalent Zo model
against the actual INA152 Zo. The equivalent Zo model results are shown in Fig. 9.36 with a
comparison shown in Fig. 9.35. We see that our equivalent Zo model is close enough to proceed with
our stability analysis.
RX27.29k
RO1.45k
VOA
CO1.44uF
IT
ne
t
D C =0A
-G
en
iu
s.
AC = 1Apk
fz
fp
INA152 Measured
76.16Hz
4.05Hz
Equivalent Model
71.2Hz
4.56Hz
EN
Zo
T 100.00k
Zo :
on
Fig. 9.35: Zo Equivalent Model Vs INA152 Zo
is
he
d
VOA A:(4.56; 19.11k) B:(71.2; 2.18k)
Phase :
VOA A:(4.56; -45.14) B:(71.2; -45.21)
As
1.00k
100.00
1
Phase [deg]
10
a
0
RO = 1.45k ohm
Pu
bl
Zo (ohms)
10.00k
100
1k
10k
100k
1M
10M
Frequency(Hz)
b
-45
-90
1
10
100
1k
10k
100k
Frequency(Hz)
Fig. 9.36: TINA Plots: Equivalent ZO Model for INA152
1M
10M
We can now analyze the effect of load capacitance, CL, on the output of the INA152 using our Zo
equivalent model. We see an additional pole in the Aol curve at 10.98 kHz as shown in Fig. 9.37.
RX 27.29k
RX has no effect on fp2 since its
im pedance is shunted by CO at
frequencies > 4.05Hz
CO 1.44μF
VOUT
-
+IN
+
Aol
+
-
fp2 =
GM2
RO
1.45k
-
1
*Ceq *RO
fp2 =
2*
1
= 10.98kHz
*10nF *1.45k
-G
en
iu
s.
2*
CL
10nF
GMO
ne
t
+
-IN
CL
CO
on
EN
where: Ceq = CO * CL
CL<1.44 μF CL dominates: Ceq
CO + CL
CL>1.44 μF CO dominates: Ceq
remember:
1) capacitors in series are like resistors in parallel
2) XC = 1/sC
3) XCeq = 1/sCO +1/sCL
4) Ceq = 1/XCeq
is
he
d
Fig. 9.37: Computing The Pole (fp2) Due To Zo And CL
IG1
As
D C =0A
Pu
bl
In Fig. 9.38 we add the CL of 10 nF to our equivalent Zo model for the INA152.
RO1.45k
RX27.29k
VOA
CL10nF
CO1.44uF
AC = 1Apk
Fig. 9.38: TINA Circuit For Analysis Of fp2
From Fig. 9.39 we see the simulation results place fp2 at 11.01 kHz, which is close enough to our
predicted 10.98 kHz to proceed forward.
T 80
Gain (dB)
60
40
Gain:
VOA A:(11.01k;60.17)
Phase :
20
VOA A:(11.01k;-44.85)
0
1
10
100
1k
10k
Frequency (Hz)
1M
10M
a
ne
t
0
-45
-G
en
iu
s.
Phase [deg]
100k
fp2
-90
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
on
EN
Fig. 9.39: fp2 Plot For Zo And CL = 10 nF
LT1T
Pu
bl
is
he
d
-
VdcBias1.25
As
VG1
DC = 0 V
Aol = VOA/VG1
Sense
VOA
U1INA152
+
+
Ref
CL10n
V15
+
AC = 1Vpk
Fig. 9.40: TINA Circuit For Modified Aol Curve With CL = 10 nF
Now we can run a TINA simulation the actual INA152 with CL = 10 nF and compare it to our
predicted response using the circuit of Fig. 9.40.
The TINA simulation results in Fig. 9.41 show a low-frequency pole due to the INA152 op amp
original Aol at 3.4 Hz (fp1) and a second pole due to Zo and CL = 10 nF at fp2 = 11.02 kHz.
Remember, we predicted fp2 = 10.9 kHz by first-order analysis and fp2 = 11.01 kHz by equivalent Zo
model simulated with CL = 10 nF.
T
120
100
Modified Aol Curve due to CL
80
Gain (dB)
60
40
Gain :
20
VOA A:(3.4; 107.03) B:(11.02k; 37.11)
Phase :
0
VOA A:(3.4; -43.15) B:(11.02k; -135.39)
-20
-40
-60
10
1
100
1k
10k
100k
1M
10M
1M
10M
Frequency(Hz)
a
0
b
-45
fp1
ne
t
-135
fp2
-180
-G
en
iu
s.
Phase [deg]
-90
-225
-270
-315
-360
1
10
100
1k
10k
100k
Frequency(Hz)
EN
Fig. 9.41: TINA Plots For Modified Aol Curve With CL = 10 nF
T
on
120
is
he
d
100
80
Pu
bl
40
fpc2
fp2
Final
Modified Aol
As
Gain (dB)
60
20
INA152 Aol
fzc1
1/Beta
0
Modified Aol
w/CL = 10nF
-20
-40
-60
1
10
100
1k
10k
F
fcl
100k
1M
10M
(H )
Fig. 9.42: Output Pin Compensation: CMOS RRO
In Fig. 9.42 we identify the technique for Output Pin Compensation for CMOS RRO op amps. The
graphical part of this technique will be similar to that for bipolar emitter-follower op amps. First we
modify the op amp’s original Aol curve with fp2, the pole due to Zo and CL (Fig. 9.41). Once this
curve (modified Aol with CL = 10 nF) is created we plot a second curve (final modified Aol) which
starts where the modified Aol with CL = 10 nF curve intersects 0 dB. From this starting point we plot
back at –20 dB/decade to a point which is one decade less than the zero dB intersection of the modified
Aol curve with CL = 10 nF (100 kHz).Here at fzc1 we change the slope to –40 dB/decade. At fpc2 we
intersect the original INA152 Aol curve. This proposed final modified Aol curve meets all of our ruleof-thumb criteria by keeping poles and zeros within one decade of each other to keep loop-gain phase
from dipping below 45° within the loop-gain bandwidth. Our proposed final modified Aol curve also
meets our first-order stability criteria of 20 dB/decade rate-of-closure at fcl.
Fig. 9.43 details the formulae based on Zo and the desired final modified Aol curve. In addition, we
notice another high-frequency pole due to RCO interacting with CL when CCO becomes a short.
-
+IN
Aol
+
+
-
VOUT
-G
en
iu
s.
+
-IN
ne
t
CO 1.44μF
CCO
GM2
RO
1.45k
-
GMO
CL
10nF
100nF
Assume: CCO > 10*CL
Set: fpc2 = 1kHz, fzc1 = 10kHz
2*
1
*Ceqo*RO
fpc2 =
on
fpc2 =
EN
RCO
150
Pu
bl
is
he
d
where: Ceqo = CCO * CL
CCO + CL
CCO < 1.44μF CCO dominates: Ceqo
fzc1 =
2*
1
*Ceqo*RCO
As
where: Ceqo = CCO * CL
CCO + CL
CCO < 1.44μF CCO dominates: Ceqo
2*
1
* CCO *1.45k
= 1kHz
CCO = 109.76nF use 100nF
CCO
fzc1 =
2*
1
= 10kHz
* 100nF*RCO
RCO = 159.15 use 150
CCO
At High Frequency CCO becomes a short
Another pole, fpc3 is formed by RCO and CL
fpc3 =
2*
1
*CL*RCO
fpc3 =
2*
1
* 10nF*150
= 106kHz
Fig. 9.43: Output Pin Compensation Formulae: CMOS RRO
In Fig. 9.44 we build a TINA Spice circuit to confirm our formulae, which predict effects on the Aol
curve due to Zo, CCO, RCO, and CL.
RX27.29k
VOA
CL10nF
IG1
DC=0A
RO1.45k
RCO150
CO1.44uF
AC = 1Apk
CCO100nF
Fig. 9.44: TINA Circuit For Modified Aol Effects By Zo, CCO, RCO, CL
T 80.00
ne
t
VOA
-G
en
iu
s.
Gain (dB)
60.00
40.00
20.00
0.00
10
100
1k
10k
100k
1M
10M
EN
1
Frequency (Hz)
fpc3=105.80kHz
is
he
d
-45.00
fpc2=1.23kHz
-90.00
10
100
fzc1=10.25kHz
1k
10k
100k
1M
10M
Frequency (Hz)
As
1
Pu
bl
Phase [deg]
on
0.00
Fig. 9.45: Modified Aol Effects By Zo, CCO, RCO, CL
In Fig. 9.45 we see the results of simulation to check our formulae for Aol modification due to Zo,
CCO, RCO, and CL. Predicted fpc2 = 1 kHz, actual fpc2 = 1.23 kHz. Predicted fzc2 = 10 kHz, actual
fzc2 = 10.25 kHz. Predicted fpc3 = 106 kHz, actual fpc3=105.80 kHz. Based on our equivalent Zo
model our predictions match close enough to the simulated results.
Based on our analysis of Fig. 9.43 and simulation confirmation we can create a final modified Aol
prediction as shown in Fig. 9.46. The final closed-loop response, Vout/Vin, is predicted to be flat until
loop gain goes to zero at fcl upon which it is expected to follow the modified Aol curve as shown.
T
120
100
80
Gain (dB)
60
fpc2
40
INA152 Aol
Final
Modified Aol
20
1/Beta
fzc1
fpc3
0
Modified Aol
w/CL = 10nF
-G
en
iu
s.
-20
-40
-60
10
1
100
ne
t
Vout/Vin
1k
fcl
10k
100k
1M
10M
Frequency (Hz)
EN
Fig. 9.46: Final Modified Aol Predictions
is
he
d
on
Our ac stability test circuit using our final Output Pin Compensation is shown in Fig. 9.47. The result
will be a modified Aol curve due to the Output Pin Compensation and CL.
LT1T
Pu
bl
-
Sense
VOA
As
Aol = VOA/VG1
U1INA152
+
+
Ref
RCO150
CL10n
V15
VdcBias1.25
CCO100n
VG1
+
DC = 0 V
AC = 1Vpk
Fig. 9.47: Ac Stability Circuit: Output Pin Compensation
The results of our final modified Aol using the Output Pin Compensation technique are shown in this
Fig. 9.48 and match our first-order predictions from Fig. 9.46.
T 120.00
20dB/decade
100.00
80.00
Gain (dB)
Straight line Approximation
Final Modified Aol
60.00
40dB/decade
40.00
20dB/decade
20.00
0.00
40dB/decade
-20.00
-40.00
-60.00
1
10
100
1k
10k
100k
1M
10M
1M
10M
Frequency(Hz)
0
ne
t
-45
-90
-G
en
iu
s.
Phase [deg]
-135
-180
-225
-270
-315
1
10
100
EN
-360
1k
10k
100k
Frequency(Hz)
on
Fig. 9.48: Ac Stability Plots: Output Pin Compensation
is
he
d
We will use the circuit of Fig. 9. 49 to run a transient stability test with our final Output Pin
Compensation in place.
Pu
bl
VDIFF
CX10nF
2.50005V
U1INA152
+
Ref
RCO150
As
-
Sense
+
VCC
CCO100nF
VCC
VCC5V
Vdc 2.5V
D C = 0V
Trans ient:
100m Vpk
+ VG1
RLoad1.8
1kH z
10ns rise & f all
Fig. 9.49: Transient Stability Test: Output Pin Compensation
Our transient stability results (Fig. 9.50) assure us that we have properly chosen the right compensation
values for the Output Pin Compensation technique on this CMOS RRO difference amplifier.
T
2.63
VDIFF
ne
t
2.35
100.00m
-G
en
iu
s.
VG1
-100.00m
350.00u
0.00
700.00u
EN
Time (s)
Fig. 9.50: Transient Stability Results: Output pin Compensation
CX10nF
2.50005V
is
he
d
VDIFF
on
TINA circuit of Fig. 9.51 enables confirmation of predicted Vout/Vin transfer function of Fig. 9.46.
-
Sense
U1INA152
Pu
bl
RCO150
+
+
Ref
VCC
CCO100nF
VCC
As
VCC5V
Vdc2.5V
VG1
DC = 0V
AC = 1Vpk
+
RLoad1.8
Fig. 9.51: Vout/Vin Ac Response Circuit: Output Pin Compensation
In Fig. 9.52 we see the Vout/Vin ac closed-loop response for our INA152 circuit compensated by the
Output Pin Compensation technique. A comparison with Fig. 9.46 shows predicted response matching
the simulated results with a roll-off in the closed-loop response plot beginning just above 35 kHz.
T
20
0
Gain (dB)
-20
Vout/Vin
Gain :
-40
VDIFF
A:(35.571848k; 1.228223)
VDIFF
A:(35.571848k; -45.236075)
Phase :
-60
-80
-100
1
10
100
1k
10k
100k
Frequency(Hz)
1M
10M
1M
10M
fcl
a
0
-45
ne
t
-180
-225
-G
en
iu
s.
Phase [deg]
-90
-135
-270
-315
-360
1
10
100
1k
10k
100k
EN
Frequency(Hz)
Fig. 9.52: Vout/Vin Ac Response: Output Pin Compensation
on
In Figure 9.53 we return to our original CMOS RRO application and add the Output Pin Compensation
on the INA152, and close the entire loop to check for stability using our transient stability test.
3.299 971V
is
he
d
VDIFF
U1INA152
CX10nF
Pu
bl
RCO150
As
CCO100nF
-
CF1nF
+
VCC
N
O M
M 1
R
T
E
S
R
RI10k
+
Ref
k
6
VFB 3.299 971V0
7
5
.
7
5
-
Sense
1
R
Iset
Imon
VOUT
3.299 843V
Iflag
U2OPA569
+ +
En
Vadjust3.3V
VG1
+
100 m Vpk
1kH z
VCC
VCC5V
Ta
lf g
M
1
RLoad1.8
2
R
10n s rise & f a ll
Fig. 9.53: Programmable Power Supply: Output Pin Compensation
Fig. 9.54 confirms that by fixing the capacitive load instability on the output of the INA152 through
Output Pin Compensation we were able to create a stable programmable power supply.
T
3.45
VDIFF
3.11
3.41
VFB
3.18
100.00m
VG1
ne
t
-100.00m
3.42
-G
en
iu
s.
VOUT
3.16
300.00u
0.00
600.00u
Time (s)
EN
Fig. 9.54: Programmable Power Supply: Transient Stability With Output Pin Compensation
A Word About Tantalum Capacitors
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When capacitor values exceed about 1 F, many times Tantalum capacitors are used for their larger
values of capacitance in a relatively small size. Tantalum capacitors are not just pure capacitance. They
also have an ESR or resistive component along with smaller parasitic inductances and resistances (Fig.
9.55). The most dominant component after their capacitance is their ESR. When using the Output Pin
Compensation technique for stability ensure ESR < RCO/10 to guarantee that RCO is the dominant
resistance to set the zero in the modified Aol curve.
The Real Tantalum Capacitor
Check ESR < RCO/10
Fig. 9.55: A Word About Tantalum Capacitors And Output Pin Compensation
About the Author
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After earning a BSEE from the University of Arizona in 1981, Tim Green has worked as an analog and
mixed-signal board/system level design engineer for over 24 years, including brushless motor control,
aircraft jet engine control, missile systems, power op amps, data acquisition systems and CCD
cameras. Tim's recent experience includes analog & mixed-signal semiconductor strategic marketing.
Currently he is the Linear Applications Engineering Manager for Texas Instruments, Tucson, AZ.