for nano-cmos ic design - Computer Engineering Research Group

Transcription

M ILLIMETRE -WAVE D EVICE C HARACTERIZATION
FOR NANO -CMOS IC D ESIGN
by
Alain Marc Mangan
A THESIS SUBMITTED IN CONFORMITY WITH THE REQUIREMENTS
FOR THE DEGREE OF M ASTER OF A PPLIED S CIENCE
G RADUATE D EPARTMENT OF E LECTRICAL AND C OMPUTER E NGINEERING
U NIVERSITY OF T ORONTO
c BY A LAIN M ARC M ANGAN 2005
Millimetre-Wave Device Characterization
for nano-CMOS IC Design
Master of Applied Science, 2005
Alain Marc Mangan
Graduate Department of Electrical and Computer Engineering
University of Toronto
Abstract
At the 90-nm node, silicon technologies have reached a point where the transistor fT and fMAX
simultaneously exceed 150 GHz, with a 1.2 V supply. With low fabrication costs for high volumes
of circuits, RF-CMOS technologies are ideally suited to realize exciting new high bandwidth consumer products that operate in the mm-wave regime. Before this can happen, models of both active
and passive devices will require a high degree of accuracy from DC, all the way up to mm-wave
frequencies.
This thesis presents new techniques that help leverage the power of measurements to characterize and model devices of nano-CMOS technologies well into the mm-wave regime. In particular,
two new de-embedding techniques are devised in order to improve measurement accuracy, and reduce wafer area consumption. Moreover, the measured characteristics of various microstrip lines,
varactors, and n-MOSFETs fabricated in a 90-nm RF-CMOS technology are analyzed in order to
identify optimal geometries for high frequency design. An extraction methodology for a scalable
physical model of accumulation-mode MOS varactors is also included.
ii
Acknowledgment
I would like to thank Prof. Sorin Voinigescu for his guidance, which was essential in building my
knowledge of device characterization. I also wish to express my gratitude to Dr. M. T. Yang of the
R & D SPICE department at TSMC, without whom it would not have been possible to fabricate test
structures in a 90-nm RF-CMOS process. Others who deserve my thanks include my collegues,
particularly Altan Hazneci for the meandering microstrip design, Michael Gordon for their measurement, and Kenneth Yau for implementing LabView routines that simplified instrument control
and data acquisition. I am also greatful to external collaborators from Quake Technologies, namely
Dr. Mihai Tazlaunau for having measured the microstrip line test structures fabricated in the 130nm RF-CMOS technology, and Dr. Douglas McPherson for his many suggestions and insight on
transmission lines. Finally, I would like to thank Quake Technologies for access to measured data
and equipment.
This work was supported by Micronet, CITO, Quake Technologies, and an Ontario Graduate
Scholarship (OGS).
iii
Table of Contents
Abstract
ii
Acknowledgment
iii
Table of Contents
iv
List of Tables
viii
List of Figures
ix
1
Introduction
1
1.1
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.3
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.4
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.5
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2
Current Calibration and De-Embedding Techniques
5
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
2.2
Calibration Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
2.3
De-Embedding Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.3.1
Y Parameter Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
2.3.2
Two-Step Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
iv
TABLE OF CONTENTS
2.4
3
4
5
Minimizing Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
New Technique for De-Embedding Transmission Lines
12
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Comparison to the State-Of-the-Art . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1
Inversion of a Transmission Matrix . . . . . . . . . . . . . . . . . . . . . 14
3.3.2
De-Embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3
Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4
Generalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
Comparison to the Y Parameter De-Embedding Technique . . . . . . . . . . . . . 23
3.5
Comparison to Other Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
New De-Embedding Technique for Other Test Structures
26
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2
Comparison to the State-Of-the-Art . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3
Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4
Preliminary Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5
Alternative Extraction of Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6
Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7
Test Structure Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Experimental
41
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2
Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3
5.2.1
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.2
Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.3
Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Open De-Embedding Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
v
TABLE OF CONTENTS
5.3.1
6
5.4
Short De-Embedding Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5
Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.6
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Characterization and Model Extraction
53
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2
Microstrip Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3
6.4
7
Open-Ended Stubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.1
90-nm RF-CMOS Test Structures . . . . . . . . . . . . . . . . . . . . . . 54
6.2.2
Technology Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2.3
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Accumulation-Mode MOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.1
Fabricated Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.2
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.3
Effective Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.4
Parameter Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.5
Physical Model Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . 68
n-MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4.1
Fabricated Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4.2
Biasing and Sizing for Optimal Performance . . . . . . . . . . . . . . . . 71
Conclusion
74
7.1
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
A Effective Characteristics of One Port Networks
76
B T and Π Network Models
79
vi
TABLE OF CONTENTS
C Transistor Figures of Merit
80
C.1 Transition Frequency, fT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
C.2 Unilateral Power Gain, U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
C.3 Maximum Oscillation Frequency, fMAX . . . . . . . . . . . . . . . . . . . . . . . 82
D Varactor Parameter Extraction
83
E List Of Symbols
85
References
88
vii
List of Tables
3.1
Technique Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Open/Short/Inductor Measurement Setups . . . . . . . . . . . . . . . . . . . . . . 43
5.2
Transmission Line Measurement Setups . . . . . . . . . . . . . . . . . . . . . . . 49
6.1
Effective Capacitance Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2
Extracted Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
viii
List of Figures
2.1
Typical VNA measurement setup for device characterization. . . . . . . . . . . . .
2.2
Typical example of ground-signal-ground (GSG) contact pads used for coplanar
6
probing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.3
Y parameter de-embedding of the DUT. . . . . . . . . . . . . . . . . . . . . . . .
8
2.4
Y parameter de-embedding of the short test structure. . . . . . . . . . . . . . . . .
9
2.5
Simple model of a one port capacitor measurement. . . . . . . . . . . . . . . . . . 10
3.1
Composition of a microstrip line test structure. . . . . . . . . . . . . . . . . . . . . 13
3.2
Arbitrary linear two port network. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Decomposing a linear two port network. . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
Inverting the transmission matrix of a linear two port network. . . . . . . . . . . . 15
3.5
Multiplying a transmission matrix by its inverse. . . . . . . . . . . . . . . . . . . . 15
3.6
Two transmission line test structures. . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
Multiplying the transmission matrix of line 2 with the matrix inverse of line 1. . . . 17
3.8
Representing Y l2 −l1 with lumped pads. . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Model of VNA measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . . 22
′
3.10 Model of calibrated measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Comparison of extracted characteristic impedance. . . . . . . . . . . . . . . . . . 24
4.1
Illustration of de-embedding techniques based on transmission matrices. . . . . . . 27
ix
LIST OF FIGURES
4.2
Transmission coefficients of a 3.68 mm microstrip line test structure. The model
was constructed using extracted values of ZC , γ, and YL obtained from (4.9). . . . . 30
4.3
Comparison between the pad impedance measured directly from a pad structure,
and extracted from transmission line measurements using (4.9). . . . . . . . . . . . 30
4.4
Model of a transmission line test structure measurement. . . . . . . . . . . . . . . 31
4.5
Simulation of the effective pad impedance, ZL . . . . . . . . . . . . . . . . . . . . 32
4.6
Effective characteristic impedance simulated using the test structure model in Fig.
′
4.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.7
Transmission coefficients of a 3.68 mm microstrip line test structure. The model
was constructed using extracted values of ZC and γ, in conjunction with the pad
impedance measured directly from a pad structure. . . . . . . . . . . . . . . . . . 32
4.8
Π two port network model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9
Splitting a short transmission line segment into two half length lines. . . . . . . . . 34
4.10 Splitting a short transmission line test structure into two sections. . . . . . . . . . . 35
4.11 Transmission coefficients of a 3.68 mm microstrip line test structure. The model
was constructed using extracted values of ZC and γ, in conjunction with the half
structure matrices obtained from (4.18) and (4.19). . . . . . . . . . . . . . . . . . 36
4.12 Reflection coefficients of a 3.68 mm microstrip line test structure modeled using
the open pad structure and the split short test structure measurements. . . . . . . . 36
4.13 Reflection coefficients of a 3.68 mm microstrip line test structure modeled using
the open pad structure and the split short test structure measurements. . . . . . . . 36
4.14 Pad capacitance extracted from the open pad structure and the split short test structure measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.15 Proposed test structure for transmission line based de-embedding technique. . . . . 40
5.1
Comparison of capacitance extracted from measurements of an open structure
(pads + open-ended interconnect). . . . . . . . . . . . . . . . . . . . . . . . . . . 44
x
LIST OF FIGURES
5.2
Characteristic impedance and effective permittivity of a microstrip line having a
configuration similar to those of the open structure stubs. . . . . . . . . . . . . . . 46
5.3
Expected open-ended stub capacitance, as estimated from the microstrip line measurements corresponding to Fig 5.2. . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4
Comparison of series interconnect resistance extracted from measurements of a
short structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5
Comparison of the inductor Q after two-step de-embedding. . . . . . . . . . . . . 48
5.6
Comparison of the effective series resistance of an inductor after two-step deembedding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.7
An overlay of the attenuation constants from all the lines measured with the GSGSG probes (setup B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.8
An overlay of the attenuation constants from all the lines measured with the GSG
probes (setup C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.9
Comparison of attenuation constant extracted from transmission line measurements. 50
5.10 Comparison of characteristic impedance extracted from transmission line measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.11 Comparison of propagation delay extracted from transmission line measurements. . 51
5.12 Low frequency comparison of characteristic impedance extracted from transmission line measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.13 Low frequency comparison of propagation delay extracted from transmission line
measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1
Micrograph of the 8 transmission lines implemented in the 90-nm technology.
Both the long (600 µm) and the short (100 µm) lines are present. . . . . . . . . . . 54
6.2
Mesh pattern used for (a) metal 1 slotted ground planes (b) metal 2 slotted ground
planes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3
Micrograph of a slotted ground plane. . . . . . . . . . . . . . . . . . . . . . . . . 55
xi
LIST OF FIGURES
6.4
Characteristic impedance as a function of frequency for transmission lines fabricated with a metal 9 conductor in the 90-nm process. . . . . . . . . . . . . . . . . 56
6.5
Characteristic impedance as a function of frequency for transmission lines fabricated with a metal 8 conductor in the 90-nm process. . . . . . . . . . . . . . . . . 56
6.6
Propagation delay as a function of frequency for transmission lines fabricated with
a metal 9 conductor in the 90-nm process. . . . . . . . . . . . . . . . . . . . . . . 56
6.7
Propagation delay as a function of frequency for transmission lines fabricated with
a metal 8 conductor in the 90-nm process. . . . . . . . . . . . . . . . . . . . . . . 56
6.8
Effective permittivity as a function of frequency for transmission lines fabricated
with a metal 9 conductor in the 90-nm process. . . . . . . . . . . . . . . . . . . . 58
6.9
Effective permittivity as a function of frequency for transmission lines fabricated
with a metal 8 conductor in the 90-nm process. . . . . . . . . . . . . . . . . . . . 58
6.10 Cross-section of a typical backend used in advanced IC technologies. . . . . . . . . 59
6.11 Attenuation as a function of frequency for transmission lines fabricated with a
metal 9 conductor in the 90-nm process. . . . . . . . . . . . . . . . . . . . . . . . 60
6.12 Attenuation as a function of frequency for transmission lines fabricated with a
metal 8 conductor in the 90-nm process. . . . . . . . . . . . . . . . . . . . . . . . 60
6.13 Technology comparison of the attenuation in lines designed with the topmost conductor and a metal 1 ground plane. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.14 Technology comparison of the attenuation in lines designed with the topmost conductor and a metal 2 ground plane. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.15 Attenuation as a function of frequency for transmission lines fabricated in the 130nm process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.16 Characteristic impedance as a function of frequency for transmission lines fabricated in the 130-nm process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.17 Propagation delay as a function of frequency for transmission lines fabricated in
the 130-nm process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
xii
LIST OF FIGURES
6.18 Effective permittivity as a function of frequency for transmission lines fabricated
in the 130-nm process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.19 Measurement vs. simulation for characteristic impedance. . . . . . . . . . . . . . . 64
6.20 Measurement vs. simulation for attenuation. . . . . . . . . . . . . . . . . . . . . . 64
6.21 Measurement vs. simulation for the ratio of power being transferred over an effective de-embedded length of 500 µm. . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.22 Micrograph of the accumulation-mode MOS varactor test structures fabricated in
the 90-nm RF-CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.23 Cross-section of the accumulation-mode MOS varactor. . . . . . . . . . . . . . . . 65
6.24 Effective capacitance measured from MOS varactors of various gate lengths. . . . . 67
6.25 Effective capacitance measured from MOS varactors of various gate widths. . . . . 67
6.26 Effective quality factor measured at 40 GHz from MOS varactors of various gate
lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.27 Effective quality factor measured at 40 GHz from MOS varactors of various gate
widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.28 Accumulation-mode MOS varactor model. . . . . . . . . . . . . . . . . . . . . . . 68
6.29 Simplified accumulation-mode MOS varactor model. . . . . . . . . . . . . . . . . 68
6.30 Measured vs. simulated effective capacitance for MOS varactors of various gate
lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.31 Measured vs. simulated effective capacitance for MOS varactors of various gate
widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.32 Measured vs. simulated effective quality factor sampled at 40 GHz for MOS varactors of various gate lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.33 Measured vs. simulated effective quality factor sampled at 40 GHz for MOS varactors of various gate widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.34 Micrograph of the n-FET test structures fabricated in the 90-nm RF-CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
xiii
LIST OF FIGURES
6.35 Measured fT as a function of drain current per unit gate width for Wf = 1 µm
MOSFETs of different gate lengths. . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.36 Measured fT as a function of drain current per unit gate width for L = 65 nm
MOSFETs of different gate widths. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.37 Measured fMAX as a function of drain current per unit gate width for Wf = 1 µm
MOSFETs of different gate lengths. . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.38 Measured fMAX as a function of drain current per unit gate width for L = 65 nm
MOSFETs of different gate widths. . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.39 Measured fT as a function of drain current per unit gate width for devices of different threshold voltages. The devices were fabricated in a 130-nm technology. . . 73
6.40 Measured fMAX as a function of drain current per unit gate width for devices of
different threshold voltages. The devices were fabricated in a 130-nm technology. . 73
A.1 BiCMOS cascode topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
A.2 Degenerate one port network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
A.3 One port inductor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
A.4 One port capacitor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
B.1 T two port network model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
B.2 Π two port network model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
C.1 MOSFET test structure in common source configuration. . . . . . . . . . . . . . . 80
D.1 Measured Cv,max + Cf vs. gate area normalized per unit finger for Wf = 2 µm
varactors of varying gate lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
D.2 Measured Cv,max + Cf vs. finger width normalized per unit finger for L = 215 nm
varactors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
D.3 Measured Rgc + Rg + Rch vs. number of squares per gate finger for Wf = 2 µm
varactors of varying gate lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
xiv
LIST OF FIGURES
D.4 Measured Rgc + Rch vs. 1/Wf normalized per unit finger for L = 215 nm varactors. 84
D.5 Measured source/drain resistance vs. gate length normalized per unit finger for
Wf = 2 µm varactors of varying gate lengths. . . . . . . . . . . . . . . . . . . . . 84
D.6 Measured source/drain resistance vs. 1/Wf normalized per unit finger for L =
215 nm varactors of varying gate widths. . . . . . . . . . . . . . . . . . . . . . . . 84
xv
Chapter 1
Introduction
1.1
Background
C
ONTINUOUSLY increasing demand for random access memories (RAM) has driven down
the minimum feature size and (metal) pitch of photolithographic technologies. As the
footprint of memory cells is reduced, higher densities are achieved, which translate to a lower
cost-per-byte. Eventually, microprocessor companies began to exploit the new technologies in
order to reduce their cost-per-function and integrate more functionality on a single die. By 2003,
microprocessors were established as the second force driving CMOS technology scaling [1].
In addition to reducing the cost of circuits, technology scaling caused a few other desirable
side-effects. With every new node, the reduction in device and interconnect dimensions decreased
the associated parasitic capacitances, reducing gate-delay and power dissipation. When CMOS
technologies reached the 0.5 µm node, the field intensity limit for silicon was attained within the
MOSFET channel, leading to hot electron effects. Further technology scaling therefore necessitated a constant field scaling scheme, whereby the MOSFET dimensions are scaled vertically as
well as laterally [2]. To maintain a constant field intensity within the channel, the power supply is
also lowered accordingly, further increasing the power savings from node to node.
Today, n-FET devices fabricated at the 90-nm node achieve fT and fMAX values beyond
1
CHAPTER 1. INTRODUCTION
150 GHz using 1.2 V power supplies. Advanced CMOS technologies are therefore great vehicles
for low-cost, low power, high frequency integrated circuits. With the increasing demand for higher
bandwidths, CMOS is an ideal contender to realize inexpensive consumer products for wireless interconnectivity, local area networks (LAN) and storage area networks (SAN). The present transistor speed is able to accommodate 10-Gb/s Ethernet products, and future technologies might enable
practical solutions for even higher data rate applications. Such interrest has been demonstrated recently through publications of 40-Gb/s broadband circuits [3–5] and components of 60-GHz radio
systems [6–9].
1.2
Motivation
The Achilles heel of deep submicrometer technologies is mask production costs, which increases
with every node. Currently, a mask set for a 90-nm technology exceeds 1.2 Million US dollars.
After the initial mask costs, circuits can quickly be mass-produced with little extra cost. Two
conditions are therefore necessary to make deep submicrometer designs cost-efficient: a) circuits
must be sold in large quantities b) designs must work on the first try, in order to avoid extra mask
costs. Device characterization addresses the latter issue.
As circuits move to higher operating frequencies, they become increasingly sensitive to nonidealities such as device parasitics, distributed effects, and process variations. This is particularly
true for tuned circuits, which can be rendered useless if the operating frequency is off typically
by 10 %. To understand these non-idealities, high-frequency (> 50 GHz) measurements of both
active and passive devices, including interconnect, are required. S parameter measurements in particular provide much insight on device operation, help determine process parameters, and identify
shortcomings within the models used for simulation. As will be shown in Section 6.4, S parameter
measurement results can also uncover more robust design techniques which are immune to process
variations and, to a certain extent, model inadequacies. Finally, S parameter measurements can
facilitate the extraction of models and validate their accuracy all the way up to mm-wave frequen-
2
cies.
Since integrated circuit (IC) technologies are driven by logic circuits, they are presently not
well established for mm-wave design. High-frequency models for passive devices are often not
provided, and little effort has been placed on mm-wave characterization. In fact, most models do
not even capture the basic geometry dependence of fT and fMAX . Much work is needed to harness
the full potential of nano-CMOS technologies.
1.3
Objectives
The objective of this thesis is to present new techniques that help leverage the power of measurements to model devices in nano-CMOS technologies well into the mm-wave regime. Considerable
focus will also be placed on the physical interpretation of the results, in order to better model and
exploit the layout/geometry dependence of electrical parameters.
1.4
Contributions
This thesis makes several contributions to the field of device characterization. Among the most
significant are the following:
- A new transmission line de-embedding technique.
- A new area/cost-efficient de-embedding technique applicable to any device or circuit.
- New insight on the impact of ground planes on the performance of microstrip lines used in
integrated circuits.
- A solution to modeling microstrip lines in BEOLs (back end of line) that have complicated
multi-dielectric compositions.
- A technique to extract physical/scalable MOS varactor models.
- Various methods to help verify the calibration and identify problems with the measurement
itself.
3
1.5
Outline
The thesis is organized as follows. First, the state-of-the-art calibration and de-embedding techniques will be presented in Chapter 2. The techniques will be used to improve the device measurements presented in subsequent chapters. In Chapter 3, the theory behind a new de-embedding
technique designed to improve the accuracy of transmission line measurements will be presented.
The technique will then be extended for other device measurements in Chapter 4. In the following
chapter, simple test structures will be used to verify the calibration and identify other potential
problems with the measurement. Finally, in Chapter 6, the measured characteristics of microstrip
lines, accumulation-mode MOS varactors, and n-MOSFETs will be plotted and discussed to help
in selecting the optimal layout geometry. Models will also be extracted from the measured characteristics of microstrip lines and MOS varactors, which are seldom covered by the foundry’s
design kit. Note that the transmission line de-embedding technique (Chapter 3) was submitted for
publication, along with the measurement results of Section 6.2 [10].
4
Chapter 2
Current Calibration and De-Embedding
Techniques
2.1
Introduction
The tool of choice for high frequency device characterization is the vector network analyzer
(VNA). To enable the available accuracy of the VNA, calibration and de-embedding techniques
are required. The aim of this chapter is to introduce the reader to the state-of-the-art techniques.
The chapter is organized as follows. The two most accurate calibration techniques will first
be introduced. Either technique can be used to characterize nano-CMOS devices. In Section 2.3,
current de-embedding techniques will be listed, and those used in subsequent chapters will be described. In the final section, it will be explained why test structure parasitics should be minimized
despite the availability of de-embedding techniques.
2.2
Calibration Techniques
The calibration technique is essential in obtaining accurate device measurements. Calibrations
compensate for the contributions of the measurement system and move the S parameter reference
planes up to the probe tips (Fig. 2.1). The choice of the calibration technique and its execution can
5
CHAPTER 2. CURRENT CALIBRATION AND DE-EMBEDDING TECHNIQUES
Figure 2.1: Typical VNA measurement setup for device characterization.
make a significant difference in the resulting accuracy.
Presently, the two most accurate calibration techniques available are variants of Line-ReflectMatch (LRM) [11, 12] and Line-Reflect-Line (LRL) [11, 13, 14]. It is believed that LRL is the
most accurate of the two [12, 14, 15]. However, LRL is impractical for low frequency measurements due to the long transmission line standards required. They are also only applicable over an
8:1 frequency rage, requiring more complex multi-line methods to calibrate over broader ranges.
Since the reference impedance of LRL calibrations is set to the characteristic impedance (ZC )
of the line standards, the accuracy for practical applications is limited to the technique available
to measure ZC . Conversely, LRM is more easily applied to both broadband, and low frequency
6
measurements [16–18]. Also, the smaller size of the required calibration standards makes it less
expensive since more sets can be integrated on a single substrate. The main disadvantage of the
LRM technique is that it requires a well defined, frequency independent load standard, which is
difficult to manufacture.
Note that, over time, various parameters in the test set will drift, gradually invalidating the
calibration. Consequently, calibrations should typically be updated every 2-3 hours to maintain the
measurement accuracy.
2.3
De-Embedding Techniques
Figure 2.2: Typical example of ground-signal-ground
(GSG) contact pads used for coplanar probing.
After the measurement setup is calibrated up to the probe tips, the test structures used to access
the device under test (DUT) will still alter the measured characteristics, especially when devices
are as small as those required for mm-wave design. For example, “large size” MOSFETs of W =
20 µm have very small gate-source and gate-drain capacitances of Cgs ≈ Cgd ≈ 6-15 fF at the
90-nm node. With probe-pad (Fig. 2.2) capacitance values easily exceeding 15 fF, techniques are
required to remove the effects of test structure parasitics from device measurements. Techniques
which account for test structure parasitics are called de-embedding techniques.
7
Purely lumped de-embedding techniques were first introduced to remove the effects of parallel
capacitance and losses [19], followed by enhancements that also deal with the series contributions
[20]. The fundamental technique was later extended to more elaborate “three-step” [21, 22] and
“four-step” [23, 24] methods. In order to avoid the high frequency limitations of lumped solutions, parasitic contributions have also been modeled by fitting equivalent circuit parameters to
test structure measurements [25]. Techniques which are more promising for measurements at mmwave frequencies attempt to limit assumptions of lumped parasitics to the pads only [26–28].
Sections 2.3.1 and 2.3.2 will quickly describe the Y parameter and two-step de-embedding
techniques. The techniques will later be used for device characterization.
2.3.1 Y Parameter Technique
Y parameter de-embedding is the simplest method accounting for the test structure parasitics [19].
It makes use of an open test structure measurement to remove the parallel parasitic contributions,
which should mostly be attributed to the pads. In practice, the open test structure is a duplicate of
the device structure, only with the device itself having been removed. The technique is formulated
under the assumption that a test structure measurement can be modeled using the leftmost circuit of
Fig. 2.3, where the series impedances are negligible. The Y parameter de-embedding is therefore
performed using:
Figure 2.3: Y parameter de-embedding of the DUT.
′′
′
Y DUT ≡ Y DUT − Y open ,
where
8
(2.1)
′
Y DUT is the measured Y parameter matrix of the DUT test structure,
Y open is the measured Y parameter matrix of the DUT open structure, and
′′
Y DUT is the measured Y parameter matrix of the DUT after Y parameter de-embedding.
The reader is referred to [29] for more insight on Y parameters and the parallel connection of
linear two port networks.
2.3.2 Two-Step Technique
Improving on the Y parameter de-embedding technique, a two-step algorithm was developed to
remove the series parasitics with the help of an additional test structure, known as a short [20].
As with the open structure, the short is a duplicate of the device structure, with the device being
replaced by a short circuit grounding both signal leads. After the parallel parasitics are removed
from both the device and the short (Fig. 2.4) test structure measurements using the Y parameter
technique, the series parasitics are removed with the help of Z parameters, in an analogous fashion:
Figure 2.4: Y parameter de-embedding of the short test structure.
′
Y short ≡ Y short − Y open , and
′′
Z DUT ≡ Z DUT − Z short ,
where
′
Y short is the measured Y parameter matrix of the short test structure,
9
(2.2)
(2.3)
Y short is the measured Y parameter matrix of the short after Y parameter de-embedding,
Z DUT is the measured Z parameter matrix of the DUT after the two-step de-embedding,
′′
′′
−1
Z DUT ≡ Y DUT
, and Z short ≡ Y −1
short .
The entire two-step de-embedding algorithm can be expressed as a single equation:
′
′
Z DUT = (Y DUT − Y open )−1 − (Y short − Y open )−1 .
2.4
(2.4)
Minimizing Parasitics
In spite of there being methods to de-embed the test structure contributions, there remains two
important reasons to minimize the associated parasitics remain. First, the models used as a basis
for the de-embedding technique rarely (if ever) describe the measurements perfectly. The assumptions limiting the technique will inevitably leave residual parasitics which are easily mitigated by
minimizing the overall test structure parasitics. An equally important reason to minimize parasitics
follows from the fact that measurement errors are always present due to the physical limitations of
the equipment. After de-embedding, certain device characteristics can be obscured by relatively
small measurement errors, even if the de-embedding technique models the measurements perfectly.
To help illustrate this point, it will be assumed that a one port capacitor measurement can be modeled exactly by the equivalent circuit of Fig. 2.5, where Cpad = 100 fF and CDUT = 20 fF. With a
10% error in measuring Cpad , the Y parameter technique would easily result in a 50% error on the
de-embedded value of CDUT .
Figure 2.5: Simple model of a one port capacitor measurement.
Since calibrations are bound by the same physical limitations that impede de-embedding techniques, parasitics should also be minimized in the measurement setup. The choice of cables,
10
connectors, and probes is therefore very important in achieving a good measurement. Since losses
increase with frequency, lower loss components are needed as the measurement frequency increases. Reflections should also be minimized in order for the probing signal to remain as strong
as possible.
11
Chapter 3
New Technique for De-Embedding
Transmission Lines
3.1
Introduction
This chapter presents a new de-embedding technique designed to improve the accuracy of transmission line measurements. In Chapter 6, the technique will be applied to various microstrip line
measurements, in order establish a link between physical line parameters and circuit performance.
This chapter is organized as follows. In Section 3.2, the state-of-the-art will be presented,
and used to differentiate the new technique from older ones. Next, the theoretical basis for the
technique will be given, including a general treatment of the transmission matrix inverse. In the
final section, experimental results will be used to compare the new technique to Y parameter deembedding. Note that the contents of this chapter was submitted for publication [10].
3.2
Comparison to the State-Of-the-Art
Ideally, a de-embedding technique would not make assumptions about the behavior of a DUT or
its parasitic embedding structure. In practice, assumptions are always necessary. A popular starting point with current techniques is to use lumped equivalent circuits to model parasitic structures
12
CHAPTER 3. NEW TECHNIQUE FOR DE-EMBEDDING TRANSMISSION LINES
[19, 30–32]. In [33], a nearly ideal method of de-embedding the propagation constant (γ) is presented. With an implicit use of the trace matrix identity, it can be applied to pad structures of
arbitrary composition. Building on this robust γ extraction, an accurate method of de-embedding
the characteristic impedance (ZC ) was later developed for lines whose RLGC parameter G is
small, and C is frequency independent [34]. To address lossy lines, a technique requiring 5 test
structure measurements models utilizes a distributed pad model in order to de-embed ZC [35]. A
completely different technique applies the calibration comparison method [36] to determine the
characteristic impedance [37].
The new technique presented in this chapter is an alternative that relies on the symmetry of the
test structures. Similar to what is proposed in [32], the new technique requires only two transmission line test structures, but is not limited to length ratios of 2:1. With regards to the extraction
of the propagation constant, the new technique is equivalent to that in [33], thus maintaining the
state-of-the-art. It also has the ability to account for the pad-line discontinuities (ZD from Fig. 3.1).
Figure 3.1: Composition of a microstrip line test structure.
13
3.3
Theory
The heart of the proposed de-embedding technique consists of inverting the measured transmission
matrix of a test structure. Thus, to facilitate its derivation and highlight some of its limitations, a
brief overview of the transmission matrix inversion operation follows.
3.3.1 Inversion of a Transmission Matrix
Consider a linear two-port network described by the transmission matrix T , which in general, may
be lossy and asymmetric (Fig. 3.2).
Figure 3.2: Arbitrary linear two port network.
Assuming that we can find sections of T which interact solely at an effective “single point”
(their ports) with both their neighbors, and that none of the neighbors on the right are coupled to
those on the left, except through the sections in question, we can express T as a product of these
sections:
T = T 1 × T 2 × . . . × T n,
Figure 3.3: Decomposing a linear two port network.
where
{T i } are the transmission matrices of the sections, and
14
(3.1)
port 1 of T i+1 is connected to port 2 of T i .
Given that the inverse of T is:
−1
−1
T −1 = T −1
n × T n−1 × . . . × T 1 ,
(3.2)
we see that taking the inverse of a transmission matrix is equivalent to flipping it along the xaxis, section-by-section and taking the inverse of each individual section. The net effect can be
visualized with the help of Fig. 3.4, where gray is used to identify an inverted matrix.
Figure 3.4: Inverting the transmission matrix of a linear
two port network.
When transmission matrix T is multiplied with its inverse (T T −1 ), port 2 of T is effectively
connected to port 1 of T −1 (Fig. 3.5).
Figure 3.5: Multiplying a transmission matrix by its inverse.
Due to the symmetry with respect to the line x = x0 , T cancels out with T −1 , section by
section, until the identity matrix is obtained, indicating that neither the effects of T , nor those of
T −1 are observed. Ports 1 and 2 of the resulting two-port are essentially shorted together.
15
Figure 3.6: Two transmission line test structures.
3.3.2 De-Embedding
Consider two transmission line test structures of length ℓ1 and ℓ2 , where ℓ1 < ℓ2 (Fig. 3.6). If
properly designed, the structures will be perfectly symmetric about the y axis. By definition, the
symmetry signifies that swapping ports 1 and 2 will not change the resulting S, Z, or Y matrices:
S li = Swap(S li ), Z li = Swap(Z li ), Y li = Swap(Y li )
(3.3)
where
the subscript li is used to identify line i, and
Swap() swaps ports 1 and 2 of an S, Z, or Y matrix:
Swap
a11 a12 a21 a22
≡
a22 a21 a12 a11
(3.4)
Extrapolating Fig. 3.1 reveals that the transmission matrix of either test structure can be decomposed into a cascade of 5 two-port networks comprising of both sets of pads, both pad-line
discontinuities (ZD ), and the intrinsic device. To simplify the derivation, the pad-line discontinuity
will be lumped together with the pads, without loss of generality. Consequently, the transmission
16
′
matrix of test structure li , T li , can be represented as the following product:
′
T li ≡ T P1 T li T P2 ,
(3.5)
where
T li is the transmission matrix of the intrinsic transmission line of structure i,
T P1 is the transmission matrix of the left pad, and
T P2 is the transmission matrix of the right pad.
With this simple expression describing the test structures, we will derive an equation for the
′
′
intrinsic transmission line. First, consider multiplying T l2 with the inverse of T l1 (Fig. 3.7).
Figure 3.7: Multiplying the transmission matrix of line 2
with the matrix inverse of line 1.
′
′
−1 −1
T l2 × T l1−1 = T P1 T l2 T P2 × T −1
P2 T l1 T P1
−1
= T P1 T l2 T −1
l1 T P1
′
≡ T P1 T l2 −l1 T −1
P1 ≡ T l2 −l1 ,
(3.6)
where T l2 −l1 is the transmission matrix of an intrinsic transmission line of length ℓ2 − ℓ1 .
Assuming that the left pad can be modeled solely by a lumped admittance, YL , we get:
T P1 ≡
"
1 0
YL 1
#
, and therefore T −1
P1 =
17
"
1
0
−YL 1
#
.
(3.7)
For the remainder of the chapter, this will be referred to as the lumped pad assumption. Under
′
the lumped pad assumption, T l2 −l1 can be expressed as a parallel combination of the intrinsic
transmission line and the parasitic lumped pads:
′
′
′′
Y l2 −l1 ≡ T to Y{T l2 −l1 } ≡ Y l2 −l1 + Y PP ,
(3.8)
where
T to Y{} denotes the conversion to Y parameters,
′′
Y l2 −l1 is an approximation for the Y parameters of the intrinsic device (Y l2 −l1 ), which is
exact only if the lumped pad assumption holds, and
Y PP is the Y parameter matrix of both sets of pads (See Fig. 3.8).
Y PP ≡
"
YL
0
0 −YL
#
.
(3.9)
′
Figure 3.8: Representing Y l2 −l1 with lumped pads.
′′
Since the intrinsic device is symmetric, its Y parameters (Y l2 −l1 ) can be isolated by connecting
′
Y l2 −l1 in parallel with a port-swapped version of itself, thus canceling out the effects of the pads:
′
′′
Y l2 −l1
′
Y
+ Swap(Y l2 −l1 )
≡ l2 −l1
.
2
(3.10)
Ignoring its ability to remove the effects of the pad-line discontinuity, the lumped pad assumption would therefore appear to produce a de-embedding technique very similar to that in [19].
18
However, a more thorough analysis, presented in section 3.3.4, will show there is more to the
technique.
3.3.3 Extraction
Having isolated the network parameters of the intrinsic line, we can extract the line characteristics.
Assuming that a lossy transmission line of length ℓ2 − ℓ1 can be modeled by [38]:
T l2 −l1 ≡
≡
"
A B
#
≡ Y to T{Y l2 −l1 }
C
D
"
#
cosh γ(ℓ2 − ℓ1 ) ZC sinh γ(ℓ2 − ℓ1 )
ZC−1 sinh γ(ℓ2 − ℓ1 ) cosh γ(ℓ2 − ℓ1 )
" ′′ ′′ #
A B
′′
′′
≈ T l2 −l1 ≡
≡ Y to T{Y l2 −l1 },
′′
′′
C D
(3.11)
we can extract the characteristic impedance (ZC ) and the propagation constant (γ):
ZC =
r
B ′′
cosh−1 A
[Ω]
,
and
γ
=
,
C ′′
ℓ2 − ℓ1
′′
(3.12)
where
Y to T{} denotes the conversion to ABCD parameters, and
′′
T l2 −l1 is only an approximation for the true parameters, T l2 −l1 , when the lumped pad assumption fails.
Knowing γ, the attenuation constant (α), propagation delay (τ ), and effective permittivity (ǫeff )
can be calculated as:
Np
dB
α ≡ Re{γ}
≈ 8.686Re{γ}
,
m
m
2
1 hsi
c
,
τ≡
, and ǫeff ≡
up m
up
where
19
(3.13)
(3.14)
up ≡
ω
β
m
is the phase velocity of the wave,
β ≡ Im{γ} rad
is the phase constant, and
m
s
c is the speed of light in free space.
3.3.4 Generalization
The lumped pad assumption is key to the formulation of the new de-embedding technique. It
provides a simple solution to removing the pad contributions. In this section, we will show that
the validity of the technique, summarized by (3.6) and (3.10), is not completely limited by the
′′
′′
lumped pad assumption. For one, the de-embedded quantities A and D in fact represent the
real transmission line network parameters, A and D, irrespective of the pad composition. This
characteristic is the result of an implicit application of the matrix trace identity exploited in [33].
We will also show that this property can be employed to extract the correct network parameters, A
and D, irrespective of calibration accuracy.
Let us therefore reconsider (3.6), before the lumped pad assumption is made. Transmission
′
matrix T l2 −l1 is defined by a set of ABCD parameters:
′
T l2 −l1 ≡
"
′
′
′
′
A B
C D
#
,
"
D −|T l2 −l1 |
(3.15)
which can be expressed in terms of Y parameters:
′
Y l2 −l1
1
≡ T to Y{T l2 −l1 } = ′
B
′
′
−1
′
′
A
#
,
(3.16)
where |M | is the determinant of M .
It is widely known that, for reciprocal two-ports, Y12 = Y21 [39]. In terms of transmission
′
′
parameters, T , this property of reciprocal networks translates into |T | = 1. Given that T l1 and T l2
′
represent reciprocal networks, it is easy to show that |T l2 −l1 | = 1 with (3.6). Substituting (3.16)
20
′
and |T l2 −l1 | = 1 in (3.10), without reference to the lumped pad assumption, we have:
′′
Y l2 −l1
′
1
=
2B ′
"
′
D −1
−1 A
′
#
1
+
2B ′
"
′
A −1
−1 D
′
#
.
(3.17)
′
′
Since A + D is the trace (tr() ≡ sum of the entries on the main diagonal) of T l2 −l1 , we can
write:
′′
Y l2 −l1 ≡
"
′′
′′
′′
′′
y11 y12
y21 y22
#
1
=
2B ′
"
tr(T l2 −l1 )
′
−2
−2
tr(T l2 −l1 )
′
#
.
(3.18)
In terms of transmission parameters, we have:
′′
T l2 −l1 ≡
"
′′
′′
′′
′′
A B
C D
#
1
= ′′
y21
′′
"
′′
−1
′′
′′
y22
−|Y l2 −l1 | y11
#
,
(3.19)
′′
resulting in the following expression for A and D :
′
tr(T l2 −l1 )
.
A =D =
2
′′
′′
(3.20)
Now, if we apply the matrix identity:
tr(N M N −1 ) = tr(M )
(3.21)
′
directly to matrix T l2 −l1 , we get:
′
tr(T l2 −l1 ) tr(T P1 T l2 −l1 T −1
P1 )
=
2
2
A+D
tr(T l2 −l1 )
=
.
=
2
2
(3.22)
Since the intrinsic transmission line is a symmetric device, Y11 is equal to Y22 , making its
transmission parameters A and D equal. Substituting (3.22) back into (3.20), while applying this
21
property of symmetric networks yields:
′′
′′
A =D =A=D
(3.23)
Thus, given reciprocal transmission line test structures and a symmetric intrinsic device, para′′
′′
meters A and D , extracted with the proposed de-embedding, technique remain valid irrespective
of whether the lumped pad assumption holds or not. The implicit exploitation of the trace identity
therefore renders (3.10) equivalent to the technique from [33] in its calculation of A and D.
Parasitic contributions from the measurement setup should also be considered. Today, many
calibration techniques exist which can remove the contribution of the measurement setup up to the
probe tips. In most cases, a two-port network measurement can be described by error boxes in
cascade with the DUT, such as depicted in Fig. 3.9 [11, 13].
Figure 3.9: Model of VNA measurement setup.
Ideally, calibrations would move the measurement plane precisely up to the probe tips, at ports
1 and 2 of the DUT. In reality, limitations of the calibration techniques will leave residual parasitics
which can again be modeled as error boxes (Fig. 3.10).
Figure 3.10: Model of calibrated measurement.
Let us therefore apply the trace identity to measurements with non-ideal calibrations. If we
22
consider the measurement of both the long and short transmission line test structures, we have:
′
M i ≡ T li ≡ T P1 T li T P2 , for lines i = 1, 2.
(3.24)
The equivalent transmission matrix measured by the calibrated VNA is given by:
′′
′
′
′
′
M i ≡ E M i F = E T P1 T li T P2 F .
(3.25)
If we apply the trace identity to the result of non-ideal measurements processed through (3.6),
we get:
′′
′′
′
′
−1
−1
tr(M 2 × M 1 −1 )= tr([E T P1 ]T l2 T −1
])
l1 [T P1 E
≡ tr(N T l2 −l1 N −1 )
= tr(T l2 −l1 ).
(3.26)
Again, due to the symmetry of the intrinsic device, the transmission parameters A = D =
tr(T l2 −l1 )/2 are isolated despite inadequate calibration. Also interesting to note is that, at the
′
′
limit, we can let E = E and F = F , showing that the trace property also yields valid results for
uncalibrated measurements.
The preceding derivations clearly reveal the true power of the proposed de-embedding technique. Through an implicit use of the trace identity, the new technique will yield the correct value
of γ, irrespective of pad composition. In fact, γ will be immune to non-idealities in the calibration.
3.4
Comparison to the Y Parameter De-Embedding Technique
The most significant advantage of the Y parameter de-embedding technique is that a single pad
structure is required to de-embed any number of lines. In comparison, the technique proposed in
this paper requires two test structures per transmission line, though the results from Section 6.2
23
indicate that pairs as short as 100 µm and 600 µm are sufficient. Nonetheless, with the high cost of
silicon area in deep-submicrometer technologies, it is important to justify the additional expense.
In order to do so qualitatively, a 3.68 mm long meandering microstrip test structure was fabricated
along with a 100 µm short line and a simple open pad structure. The measured characteristic
impedance is presented in Fig. 3.11 for both de-embedding techniques. The results of a direct
extraction without de-embedding are also included as a point of reference.
65
Characteristic Impedance, |ZC| (Ω)
Y parameter de-embedding
Proposed technique
No de-embedding
60
55
50
45
0
10
20
30
40
50
60
70
Frequency (GHz)
Figure 3.11: Comparison of extracted characteristic impedance.
The comparison of extracted characteristic impedance shows a dramatic improvement when
the proposed technique is used. On the other hand, the Y parameter de-embedding technique does
not appear to improve the extraction of ZC in any respect. It simply inverts the resonance effect
present in the unprocessed measurement. Considering the improvements in extracting ZC , the area
overhead is certainly justifiable for characterization purposes, at least in this particular case.
3.5
Comparison to Other Techniques
Table 3.1 lists some important properties of the available de-embedding techniques. When accuracy is important, test structures of two different line lengths should be fabricated in order to take
advantage of the state-of-the-art γ extraction [33].
24
Technique
Table 3.1: Technique Comparison
Silicon Area
Utilizes the
Type
(Test structure count state-of-the-art
for n devices)
γ extraction [33]
Y parameter [19, 30]
Heymann et al. [31]
Song et al. [32]
Mondal and Chen [33]
Marks and Williams [34]
Winkel et al. [35]
Williams et al. [37]
ZC and γ
ZC and γ
ZC and γ
γ only
ZC only
ZC only
ZC only
Proposed technique
ZC and γ
n+1
n
2n
2n
2n
2n + 3
2n or 3n or 4n ...
(multiline)
2n
25
Restricted
to low loss
lines
Length ratio
restricted to
ℓ2 /ℓ1 = 2
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
No
N/A
N/A
Yes
No
No
No
No
Yes
No
No
Chapter 4
New De-Embedding Technique for Other
Test Structures
4.1
Introduction
The limits of the two-step de-embedding technique are being pushed at mm-wave frequencies [25].
Moreover, the large overhead due to de-embedding structures and increasing mask costs make the
technique very expensive to characterize 90-nm technologies. This chapter presents a new deembedding technique based on transmission lines, and designed to replace the two-step method.
The chapter is organized as follows. In Section 4.2, the state-of-the-art will be presented, and
used to differentiate the new technique. Next, a step-by-step methodology for the new technique
will be proposed, using only the concepts presented in Chapter 3. In Section 4.4, an attempt to
validate the technique will point to model limitations, and demand further improvement. The
following section will address the problem using a novel Y parameter based splitting technique.
The chapter will then conclude with an enhanced methodology based on the improvements, and
guidelines for designing better test structures.
26
CHAPTER 4. NEW DE-EMBEDDING TECHNIQUE FOR OTHER TEST STRUCTURES
4.2
Comparison to the State-Of-the-Art
The proposed de-embedding technique models the parasitic interconnect as transmission lines. A
technique based on transmission lines can easily scale measurements of the parasitic interconnect
to any length used in the test structures. This translates into a significant reduction in area overhead
when compared to the purely lumped solutions. Only one set of transmission line test structures is
necessary to de-embed all other test structure measurements. Such a solution is more cost-effective
for characterization, which is not intended for mass production. Modeling parasitic interconnect as
transmission lines should also improve the measurement accuracy at mm-waves. Moreover, since
the de-embedding process involves cascading the inverse transmission matrices of the parasitics
(Fig. 4.1), it can easily be applied to de-embed noise parameter measurements [26, 40].
Figure 4.1: Illustration of de-embedding techniques
based on transmission matrices.
Improving on what is presented in [27], the new technique de-embeds transmission line measurements as described in Chapter 3, which was shown to be superior to the Y parameter subtraction used in [26–28]. The proposed test structure also provides a solid ground connection,
eliminating the need to de-embed the parasitics associated with narrow ground connections [28].
All of the losses associated with the ground return path are captured by the transmission line measurements. The solution is also shown to be much less sensitive to the contact impedance between
probes and pads.
27
4.3
Methodology
′
′
1) Measure the S parameters of the long (S l2 , of length ℓ2 ) and short (S l1 , of length ℓ1 )
′
transmission line test structures, as well as those of the DUT (S DUT ). Convert all to
transmission parameters:
′
′
′
′
T l2 = S to T{S l2 }, T l1 = S to T{S l1 },
(4.1)
′
′
and T DUT = S to T{S DUT }.
(4.2)
where S to T{} denotes the conversion from S to transmission parameters.
′′
2) Isolate the network parameters of the de-embedded transmission line (Y l2 −l1 , of length
ℓ2 − ℓ1 ) using the technique described in Chapter 3:
′
′
′
T l2 −l1 ≡ T l2 × T l1−1 ,
′
′′
Y l2 −l1 ≡
(4.3)
′
Y l2 −l1 + Swap(Y l2 −l1 )
,
2
(4.4)
where
′
′
Y l2 −l1 ≡ T to Y{T l2 −l1 },
T to Y{} denotes the conversion from transmission to Y parameters, and
Swap() swaps ports 1 and 2 of an S, Z, or Y matrix:
Swap
a11 a12 a21 a22
≡
a22 a21 a12 a11
.
(4.5)
3) Extract the characteristic impedance and propagation constant of the line:
ZC =
r
B ′′
cosh−1 A
, and γ =
C ′′
ℓ2 − ℓ1
′′
28
(4.6)
from the de-embedded transmission parameters:
"
′′
A B
′′
C D
′′
′′
#
′′
′′
≡ T l2 −l1 ≡ Y to T{Y l2 −l1 }.
(4.7)
4) Extract the lumped admittance of the pads, YL . From Chapter 3, we know that under the
lumped pad assumption,
′
′′
Y l2 −l1 ≡ Y l2 −l1 +
"
YL
0
0 −YL
#
.
(4.8)
′′
Given that Y l2 −l1 is symmetric, YL can be isolated in a manner complementary to (4.4):
"
YL
0
0 −YL
#
′
′
Y
− Swap(Y l2 −l1 )
= l2 −l1
.
2
(4.9)
5) Construct transmission matrices capturing the parasitic contributions of the interconnect
and pads found at both ports of the DUT:
T IP1 ≡
T IP2 ≡
"
1 0
#"
cosh γℓI1
ZC sinh γℓI1
#
ZC−1 sinh γℓI1 cosh γℓI1
Y 1
" L
#
#"
cosh γℓI2 ZC sinh γℓI2
1 0
ZC−1 sinh γℓI2
cosh γℓI2
,
(4.10)
,
(4.11)
YL 1
where ℓIi is the length of interconnect on port i of the DUT test structure.
′
6) De-embed T IP1 and T IP2 from the DUT measurement. Assuming T DUT ≡ T IP1 T DUT T IP2 ,
we can isolate T DUT (Fig. 4.1):
′
−1
T DUT ≡ T −1
IP1 T DUT T IP2 .
29
(4.12)
4.4
Preliminary Validation
A test structure set for a microstrip line measuring ℓ2 = 3.68 mm will be used for validation. The
set also includes a short (ℓ1 = 100 µm) microstrip line for de-embedding purposes, and a pair
of independent pad structures. If the model for the proposed de-embedding technique is valid, it
should be possible to accurately reconstruct the S parameter matrices of the original measurements
using only the extracted values for ZC , γ, and YL . If the resulting S parameters are not within the
uncertainty range of the original measurement, the model cannot be valid. Since the test structures in question are symmetric, the uncertainty range can easily be observed from the differences
between s11 and s22 , or s12 and s21 .
Figure 4.3: Comparison between the pad impedance
measured directly from a pad structure, and extracted
from transmission line measurements using (4.9).
Figure 4.2: Transmission coefficients of a 3.68 mm microstrip line test structure. The model was constructed
using extracted values of ZC , γ, and YL obtained from
(4.9).
When plotted next to the measured S parameters of the 3.68-mm test structure (Fig. 4.2), it
is readily evident that the reconstructed (modeled) S parameters are not within the measurement
uncertainty range. Furthermore, a closer examination of the pad admittance extracted from (4.9)
reveals a non-physical negative resistance. On the Smith plot (Fig. 4.3), the negative resistance is
identified by the corresponding reflection coefficient, which is clearly outside the unit circle. Note
30
that the impedance measured directly from the pad structure is also included, in order to establish
a point of reference. Extractions place the measured pad capacitance in the 6-8 fF range.
Results would seem to indicate that the lumped pad assumption made in Chapter 3 was violated.
Although it was shown that γ will not be affected by the violation, ZC might be compromised. The
source of the inconsistencies should therefore be determined in order to estimate the measurement
error, and possibly improve the de-embedding technique.
Given that the pad dimensions are 48 µm × 48 µm (≈ λ/50 @ 65 GHz), pads are not likely
to violate the lumped pad assumption. However, one possible source for the inconsistencies is
contact impedance, which is not taken into account by the calibration. In an attempt to reproduce
the results in Fig. 4.3, simulations of the test structure measurements were performed using the
model in Fig 4.4. To make the simulation results representative of the measurements, similar pad
parasitics were used, and the intrinsic transmission line was modeled with an ADS coupled lines
model generated with the proper backend information. For the remainder of the section, we will
′
consider pad extractions to yield an effective pad impedance, ZL , which is an approximation for
the actual impedance, 1/YL .
Figure 4.4: Model of a transmission line test structure
measurement.
Simulations show that even a small contact resistance can lead to an erroneous reading of nega′
tive pad resistance. The larger the value of Re{Zct }, the more negative Re{ZL } becomes. Also, if
′
the contact is slightly inductive, it will offset Im{ZL }, making it significantly less capacitive than
1/YL , as is observed in Fig. 4.3. Results indicate that the contact resistance must be increasing
with frequency in order to reproduce what is observed in measurement. A reasonable estimate for
the contact impedance was found to be a resistance that increases linearly up to 3 Ω at 65 GHz, in
series with an 8 pH inductance (Fig 4.5). With this knowledge, it is also possible to see the effects
of the contact impedance on ZC (Fig. 4.6). At 65 GHz, a small error of approximately 1 Ω and 1◦
31
phase is expected. The error is predominantly sensitive to the contact inductance.
0
Zct=0
Zct=3f/65G + jω8p
65
60
-10
55
-15
50
Figure 4.5: Simulation of the effective pad impedance,
′
ZL .
-5
0
10
20
30
40
50
60
Arg(ZC) (Degrees)
70
-20
70
Frequency (GHz)
Figure 4.6: Effective characteristic impedance simulated
using the test structure model in Fig. 4.4.
Since the expected error for ZC is relatively small, it should be possible to possible to construct
a reasonable model for the test structure measurement if the direct pad measurement is used to
replace YL of (4.9). As can be seen from Fig. 4.7, there is a significant improvement with the
new model. However, the modeled reflection coefficients are not close to the measured uncertainty
range. An alternative method to account for the parasitics is therefore needed.
Figure 4.7: Transmission coefficients of a 3.68 mm microstrip line test structure. The model was constructed using
extracted values of ZC and γ, in conjunction with the pad impedance measured directly from a pad structure.
32
4.5
Alternative Extraction of Parasitics
Assuming that discrepancies are indeed largely caused by the contact impedance, the problem
must be addressed directly using an on-wafer short circuit pad structure, as proposed in [41]. Since
no such test structure was available in our experiment, an alternative solution which is much less
sensitive to the contact parasitics was devised. The technique splits the short transmission line test
structure measurement at the mid-point of its line without considering the effects of the contact
impedance. Its accuracy can therefore be further improved by a direct measurement of the contact
impedance. Before describing the technique, we will first consider the Π model representation of
a reciprocal (y12 = y21 ) two-port network (Fig. 4.8). In terms of the {yij } Y parameters of the
network, the admittances are given by [29]:
Figure 4.8: Π two port network model.
Y1 = y11 + y12
Y2 = y22 + y12
Y3 = −y12 .
(4.13)
Since the Y parameter matrix of a transmission line can be expressed as [38]:
1
Y =
ZC
"
coth γℓ −cschγℓ
−cschγℓ coth γℓ
#
,
(4.14)
the Π network admittances expand to:
coth γℓ − cschγℓ
cosh γℓ − 1
,
=
ZC
ZC sinh γℓ
1
cschγℓ
.
=
and Y3 =
ZC
ZC sinh γℓ
Y1 = Y2 =
(4.15)
(4.16)
Due to the scalable nature of transmission lines, a cascade of semi-infinite lines measuring
33
ℓ1 and ℓ2 will necessarily be equivalent to a single line of length ℓ1 + ℓ2 . In the general case,
decomposing a segment of transmission line into two shorter segments requires the use of (4.15)
and (4.16). If the transmission line is short enough, such that |γℓ| ≪ 1, the trigonometric functions
can be approximated as cosh γℓ ≈ 1 +
(γℓ)2
2
Y1S = Y2S ≈
and sinh γℓ ≈ γℓ, simplifying the expressions to:
1
γℓ
,
, and Y3S ≈
2ZC
ZC γℓ
(4.17)
where the superscript “S” is used to emphasize that the line must be short.
Figure 4.9: Splitting a short transmission line segment
into two half length lines.
Thus, a short line segment can be split in two half length lines using the 2-Π model from Fig.
4.9. In terms of accuracy, the split operation should cause little degredation. Splitting a 100 µm
microstrip line segment with |γℓ| ≈ 1/4 @ 65 GHz results in very small deviations of the RLGC
parameters: R < 1.6%, L < 0.7%, and C < 0.35%. If we again make the lumped pad assumption
from Chapter 3, a transmission line test structure is simply described as a transmission line with
lumped pads (YL ) connected across both terminal pairs. Under this assumption, Fig. 4.10 shows
how a short test structure measurement can be split into two sections from its mid-point, using the
same technique as depicted in Fig. 4.9. Since Y1S and Y2S cannot be obtained directly from the short
test structure measurement, they must be computed from (4.17) using the de-embedded quantities
ZC and γ. The Y parameter matrices resulting from the split are therefore given by:
34
Figure 4.10: Splitting a short transmission line test structure into two sections.
′

S′
y11

Y SH1 = 
−
S′
y12
γℓ1
−
4ZC

S′
2y12

,
γℓ1
S′
− 2y12
4ZC
′
= Swap(Y SH1 ),
S′
2y12
′
and Y SH2
(4.18)
(4.19)
′
where {yijS } are the measured Y parameters of a short transmission line test structure. Note that
′
′
′
′
S
S
S
S
with a symmetric network such as this.
= y21
and y12
= y22
y11
Fig. 4.11 illustrates just how closely the long test structure S parameters can be reconstructed
′
′
′
′
from the cascade of T SH1 ≡ Y to T{Y SH1 } and T SH2 ≡ Y to T{Y SH2 } with the de-embedded mea′′
surement T l2 −l1 . Although the agreement is remarkable, the improvement over the reconstruction
using direct pad measurements is more noticeable for the reflection coefficients (Figs. 4.12 and
4.13). We also get good agreement with the direct pad measurement (Fig. 4.14) if the effects of the
transmission line are removed:
′
T P1 ≡ T SH1 T −1
HS1 ,
where
T P1 is the transmission matrix of the pad at port 1, and
T HS1 is the transmission matrix of the half length stub:
35
(4.20)
Figure 4.11: Transmission coefficients of a 3.68 mm microstrip line test structure. The model was constructed using
extracted values of ZC and γ, in conjunction with the half structure matrices obtained from (4.18) and (4.19).
-20
Arg(S11) & Arg(S22) (Degrees)
Reflection Coefficients, |S11| & |S22| (dB)
40
-25
0
-40
-30
-35
0
Original measurement (S11)
Modeled with pad measurement (S11≈S22)
Modeled with split (S11=S22
-80
Modeled with pad measurement (S11≈S22)
Modeled with split (S11=S22)
10
20
30
40
50
60
-120
70
0
10
20
Frequency (GHz)
Figure 4.12: Reflection coefficients of a 3.68 mm microstrip line test structure modeled using the open pad
structure and the split short test structure measurements.
T HS1
30
40
50
60
70
Frequency (GHz)
Figure 4.13: Reflection coefficients of a 3.68 mm microstrip line test structure modeled using the open pad

ℓ1
ℓ1
ZC sinh γ 
 cosh γ 2
2
≡
ℓ1
ℓ1  .
−1
ZC sinh γ
cosh γ
2
2

36
(4.21)
10
Pad Capacitance, Cpad (fF)
8
6
4
2
Direct measurement (Port 1)
Direct measurement (Port 2)
Modeled with split
0
0
10
20
30
40
50
60
70
Frequency (GHz)
Figure 4.14: Pad capacitance extracted from the open pad
The effective open-ended pad impedance is “simulated” by leaving port 2 of T P1 open-circuited:
V1 ZL =
= z11 .
I1 I2 =0
′
where
(4.22)
Vi and Ii are the net voltage and current of port i, and
z11 is the Z parameter of matrix Z P1 ≡ T to Z{T P1 }.
Similar match, if not better, is obtained when reconstructing the short transmission line test
′
′
structure measurement from T SH1 T SH2 . The splitting technique can therefore be used in conjunction
with the de-embedding technique from Chapter 3 to account for test structure parasitics.
4.6
Enhancements
Since it is clear that the technique presented in Section 4.3 is inadequate, it should be improved
using the knowledge acquired from the validation section. Given that no significant problems with
the transmission line de-embedding was found, steps 1-3 remain unchanged. The remaining steps,
are replaced with the following:
4) Compute a symmetric S parameter matrix from the short transmission line test structure
37
measurements:
S′
S ≡
"
′
′
′
′
′
′
′
′
Mean(s11 , s22 ) Mean(s12 , s21 )
Mean(s12 , s21 ) Mean(s11 , s22 )
#
,
(4.23)
where
′
′
{sij } are entries of the original measured S parameter matrix, S l1 , and
Mean() computes the mean of both its arguments.
Averaging the S parameters has been observed to significantly improve how accurately the
test structure measurements can be reconstructed. Asymmetries in the measurement are
amplified when S parameters are converted to Y parameters. Given the nature of VNA
measurements, the mean should be taken in polar form, averaging the phasor magnitudes
in either raw form:
Mean(r1 ejθ1 , r2 ejθ2 ) ≡
r1 + r2 j θ1 +θ2
e 2 ,
2
(4.24)
√
(4.25)
or in decibels, which can be expressed as:
Mean(r1 ejθ1 , r2 ejθ2 ) ≡
r1 r2 ej
θ1 +θ2
2
.
Both means should yield similar results. Note that care must be taken when averaging the
phase components. Most computational packages evaluate the phase of complex numbers
within a range of either [0◦ , 360◦ ) or [−180◦ , 180◦ ). In the first case, a blind application of
(4.24) or (4.25) to average the phases of θ1 = 1◦ and θ2 = 359◦ yields 180◦ instead of 0◦ .
A similar problem occurs for the second case.
′
5) Split S S into half, from the mid-point of its transmission line:
′

′
yS
 11
Y SH1 = 
−
S′
y12
γℓ1
−
4ZC


,
γℓ1
′
S
2y12
− 2y12
4ZC
′
S′
and Y H2 = Swap(Y SH1 ),
S′
′
′
where {yijS } are the entries of Y S ≡ S to Y{S S }.
′
S′
2y12
38
(4.26)
(4.27)
6) Construct transmission matrices capturing the parasitic contributions of the interconnect
and pads found at both ports of the DUT:
′
T IP1 ≡ T SH1 T ∆l1
(4.28)
′
T IP2 ≡ T ∆l2 T SH2
(4.29)
where
′
′
T SHi ≡ Y to T{Y SHi }, and
′
T ∆li accounts for the difference in length between the half stub present in T SHi , and
the interconnect used in the DUT test structure itself (∆ℓi ≡ ℓIi −
T ∆li ≡
"
cosh γ∆ℓi
ZC sinh γ∆ℓi
ZC−1 sinh γ∆ℓi
cosh γ∆ℓi
#
ℓ1
):
2
(4.30)
7) De-embed T IP1 and T IP2 from the DUT measurement.
′
Assuming T DUT ≡ T IP1 T DUT T IP2 , we can isolate T DUT (Fig. 4.1):
′
−1
T DUT ≡ T −1
IP1 T DUT T IP2 .
4.7
(4.31)
Test Structure Design
Having been derived mostly from transmission line models, the proposed de-embedding technique
is ideally suited for mm-wave applications. To complement the technique, test structures should
be designed so as to minimize parasitics, making it possible to accurately characterize the small
devices available in sub-130 nm technologies. A ground metal sheet comprised of the bottommost metal should therefore cover the entire test structure surface, with the exception of a small
gap required to access the DUT. Substrate contacts should permeate the ground metal sheet such as
to provide a solid ground for the DUT. As a result, the need to de-embed parasitics from the ground
connection [28] is eliminated, while simultaneously reducing both the pad and interconnect losses
39
Figure 4.15: Proposed test structure for transmission line
based de-embedding technique.
significantly.
Minimizing losses is of particular importance when measuring the fMAX of NFETs with small
geometries, due to its sensitivity to the gate resistance [42]. This property is readily evident from
the noisy unilateral gain (Mason’s gain, U ) curves extracted from measurement. Test structures
designed for noise measurements might also opt for a second ground metal sheet (Fig. 4.15) to
further reduce losses at the expense of increased parasitic capacitance.
Given the large thickness of the top metal layer in many RF backends, losses are dominated by
the effective ground plane thickness, as opposed to the conductor trace width (See Section 6.2.1).
Thus, narrow conductors, ranging from 2-3 µm are preferable due to their smaller capacitance.
However, electromigration rules often set the minimum trace width that should be used for the
interconnect on the drain/collector side of a transistor test structure.
As an alternative to using wide interconnect for the gate/base terminal, transistor test structures can be accommodated with an additional pair of transmission line structures, corresponding
to the configuration of the drain/collector terminal. The wider transmission line test structures
would therefore be used for the construction of T IP2 , assuming the drain/collector is connected to
port 2.
40
Chapter 5
Experimental
5.1
Introduction
Many factors influence the accuracy of a measurement. The aim of this chapter is to show, by
example, how to determine whether the accuracy of a measurement is adequate. Simultaneously,
the presented results are intended to provide credibility to the extracted characteristics of Chapter 6,
and demonstrate the type of repeatability that is possible with VNA measurements.
This chapter is organized as follows. First, a detailed description of the measurement setup will
be presented. This information will help in understanding the results that follow. In Section 5.3,
a set of reference measurements and knowledge of the basic properties of an open de-embedding
structure will be used to identify setups that yield the most accurate measurements. The following
three sections will continue on this path of identifying results of better accuracy, utilizing measurements of a short de-embedding structure, an inductor, and several transmission lines. In particular,
inductor Q measurements will be used to identify problems with the calibration procedure.
5.2
Measurement Setup
Two distinct setups were used to perform the device measurements presented in this thesis.
1) 50 GHz Setup: Measurements were performed on an HP 8510C VNA with flexible cables
41
CHAPTER 5. EXPERIMENTAL
and Cascade Microtech device probes. The measurements were calibrated using the LRM
algorithm provided with the VNA, and the standards from a Cascade Microtech ISS 101190 substrate. Bias currents and voltages were applied and measured simultaneously using
an HP 4156 semiconductor parameter analyzer.
2) 65 GHz Setup: Measurements were performed on a Wiltron 360B VNA with semi-rigid
cables and Cascade Microtech device probes. The measurements were calibrated using
the LRM algorithm provided by the WinCal software from Cascade Microtech, and the
standards from a Cascade Microtech ISS 101-190 substrate. Bias currents and voltages
were applied and measured simultaneously using an HP 4145 semiconductor parameter
analyzer.
Unless otherwise stated, it should be assumed that the results were obtained from the 65 GHz
setup, exactly as indicated above. Measurements were controlled remotely from the Agilent ICCAP software once licenses were available. IC-CAP greatly simplifies the control of the VNA
and parameter analyzer. It also reduces the effort required to extract and display plots of the
measurements. Before the availability of the IC-CAP licenses, a LabView setup1 controlled the
instruments and Matlab scripts were used to extract the various characteristics.
5.2.1 Calibration
In addition to making proper contact with the calibration standards, various parameters need to
be specified correctly to ensure a good calibration. Compared to the Short-Open-Load-Thru
(SOLT) calibrations, LRM calibrations are less error-prone since they typically do not require
probe-specific coefficients. Nonetheless, in terms of labeling and number of settings, the LRM
implementation built into the Wiltron 360B VNA is particularly difficult to decipher. To help in
determining the correct calibration procedure, measurements performed on the HP 8510C system
were used as a reference.
Initially, focus was placed on measuring inductors, the simplest available structures. As op1
Implemented by Kenneth Yau
42
posed to transistors and varactors which require measurements at multiple bias points, inductors
can be measured quickly between successive calibrations. Since these test structures were designed for the two-step de-embedding method, open and short de-embedding structures were also
measured. In many cases, bad calibrations were identified immediately from the open structure
measurement. Depending on the calibration procedure used, extracted characteristics such as pad
capacitance easily deviated from the reference measurement by a factor of 2. Table 5.1 lists measurement setups used with some of the better calibrations. The corresponding results will be used
to validate the calibrations and identify problems with certain components.
ID
A
B
C
D
E
F
VNA
HP 8510C
Wiltron 360B
Wiltron 360B
Wiltron 360B
Wiltron 360B
Wiltron 360B
Table 5.1: Open/Short/Inductor Measurement Setups
Cables
Probes
Calibration
50 GHz flexible
Cascade 50 GHz GSG
VNA LRM
65 GHz semi-rigid GGB 67 GHz GSGSG
VNA LRM
65 GHz semi-rigid GGB 67 GHz GSGSG
VNA LRM
65 GHz semi-rigid Cascade 67 GHz GSG
VNA LRM
65 GHz semi-rigid Cascade 67 GHz GSG WinCal LRM
65 GHz semi-rigid Cascade 67 GHz GSG WinCal LRRM
Calibration Substrate
Cascade ISS 101-190
GGB CS-5
Cascade ISS 101-190
Cascade ISS 101-190
Cascade ISS 101-190
Cascade ISS 101-190
5.2.2 Probes
Since the device test structures were designed with GSG pads, the ground-signal-ground-signalground (GSGSG) GGB circuit probes should technically not have been used to perform device
measurements. However, the proper GSG device probes were not immediately available by the
time the dice arrived and measurements were required.
5.2.3 Cables
It should be noted that the semi-rigid cables used in the 65 GHz setup were somewhat mistreated,
clearly having been bent many times over. Ideally, semi-rigid cables should be bent once to the
required form, and left this way for the remainder of their useful life. Although more cumbersome
to work with, semi-rigid cables are supposed to yield better measurements than flexible cables.
43
Interestingly enough, it will be shown that, despite the abuse, the measurements made with the
semi-rigid cables appear superior to the reference measurements.
5.3
Open De-Embedding Structures
The open structure is ideal for an initial validation of the calibration. Its main parasitics can be
extracted from a single measurement, and are simple enough to be roughly estimated by hand.
More importantly, the capacitance of an open structure, dominated by the pads, should be large
enough for repeatable measurement, yet small enough to see the effects of bad calibration. If the
interconnect leading up to the device is short compared to the wavelength, the capacitance of the
open structure should be mostly frequency independent. Assuming the admittances can be modeled
as a capacitor in series with a resistor, the parallel capacitance at both ports can be extracted as:
C1 ≡
−1
−1
, C2 ≡
,
Im {1/YO1 } ω
Im {1/YO2 } ω
(5.1)
where YOi is determined from Y open (Fig. 2.3) using the Π model relationships in Appendix B.
A plot of the capacitance extracted from both ports is presented in Fig. 5.1. The repeatability is
respectable, especially when considering that the results come from different setups, measured
“remotely” through two 2’ cables.
13
13
Parallel Capacitance, C2 (fF)
14
Parallel Capacitance, C1 (fF)
14
12
12
11
Reference (A)
GSGSG probes (B)
GSGSG probes (C)
GSG probes (D-F)
10
9
11
0
10
20
Reference (A)
GSGSG probes (B)
GSGSG probes (C)
GSG probes (D-F)
10
30
40
50
60
9
70
Frequency (GHz)
0
10
20
30
40
50
60
70
Frequency (GHz)
Figure 5.1: Comparison of capacitance extracted from measurements of an open structure (pads + open-ended interconnect).
44
At first glance, it would appear as if the measurements made with the GGB circuit probes are
better than all others taken with the Wiltron 360B network analyzer. The extracted capacitance is
closer to the reference measurement both in absolute value, and with respect to other behavior. For
one, the capacitance does not drop as much with frequency as in the measurements with the (new)
Cascade GSG device probes. Also, the capacitance extracted from the latter set has a observable
difference between port measurements of approximately 1 to 1.5 fF. Contrary to what this preliminary analysis would indicate, it is in fact more likely that the set of measurements made with the
new Cascade probes on the Wiltron 360B is the most accurate. For one, those measurements are
much smoother than those made with the GSGSG circuit probes. However, the most convincing
piece of evidence in favor of this statement is in the analysis of the open-ended stubs attached to
the pads, as discussed next.
5.3.1 Open-Ended Stubs
With ideal open-ended stubs, the effective input capacitance is expected to increase with frequency.
However, none of the measured results in Fig. 5.1 exhibit an increase in capacitance. The most
distinctive feature differentiating ideal open-ended stubs from those of the open test structure is
the lack of a good ground plane. The stubs present in the test structure use the lossy silicon
substrate as their ground plane. As will be seen in Chapter 6, the characteristic impedance of these
lines increases substantially with frequency. Likewise, their effective permittivity decreases with
frequency. Let us therefore consider the admittance of an open-ended stub, submitted to these
variations. From transmission line theory, the effective (or input) impedance of an open-ended
stub is given by:
Yeff
√
1 1 − e−j2ω µǫℓ
1 1 − e−j2βℓ
√
.
=
=
ZC 1 + e−j2βℓ
ZC 1 + e−j2ω µǫℓ
(5.2)
With a value of ZC that increases with frequency (Fig. 5.2), Yeff would clearly not increase as
quickly as the ideal case, where ZC is frequency independent. Adding to the deviation from the
45
8.0
150
4.0
7.0
130
6.0
120
5.0
110
3.0
Effective Permittivity, εeff
140
Effective Capacitance, Ceff (fF)
Port 1 (45µm open-ended stub)
Port 2 (20µm open-ended stub)
0
10
20
30
2.0
1.0
4.0
50
40
0.0
0
Frequency (GHz)
10
20
30
40
50
Frequency (GHz)
Figure 5.2: Characteristic impedance and effective permittivity of a microstrip line having a configuration similar to those of the open structure stubs.
Figure 5.3: Expected open-ended stub capacitance, as
estimated from the microstrip line measurements corresponding to Fig 5.2.
ideal, the effective permittivity is not frequency-independent, but rather decreases with frequency.
The frequency dependent increase in admittance normally seen in the ideal case is further coun√
teracted by the decreasing ǫ term. It would therefore seem feasible that these effects might be
large enough to cause the effective capacitance to decrease with frequency, as opposed to increase.
In fact, this has been verified from measurements of a microstrip line with a similar configuration,
designed over unshielded silicon (Fig. 5.3). The impedance of the open-ended stubs are extracted
directly from the measured Z parameters (see Appendix A) scaled to the appropriate line length:
Zeff
V1 = z11 .
=
I1 I2 =0
(5.3)
In addition to predicting a capacitance that decreases with frequency, the extraction also indicates that a difference on the order of 2 fF is to be expected between the two ports. This new
piece of information only increases the likelihood that measurements D, E & F are more representative of the true open structure characteristics. It should not be surprising that the GSG probes
yield better measurements. For starters, GSG probes have better characteristics. Moreover, the test
structures and calibration standards were not designed to accommodate GSGSG probes, forcing
two of the outermost SG tips to land on the passivation. Thus, the uneven probe tips do not make
good contact with the pads, introducing additional contact resistance and inductance. In response
46
to the increase in parasitics, the measurement accuracy is expected to diminish.
5.4
Short De-Embedding Structures
A common problem with device measurements is caused by bad contact when landing the probes
onto the pads of the test structure. Although the delicate probes should not be abused, adequate
force should be applied to break through the naturally forming layer of Al2 O3 covering the aluminum pads, thus ensuring a solid contact. One of the best indicators of bad contact is the short
de-embedding structure. To a first order, the contact impedance appears in series with the interconnect of the structure. An extraction of the series parasitics therefore helps identify the problem
which often plagues measurements. Both the series inductance and resistance of the short test
structure can be extracted using:
2.0
Series Resistance, R2 (Ω)
1.5
Reference (A)
GSGSG probes (B)
GSGSG probes (C)
GSG probes (D-F)
1.0
0.5
0.0
-0.5
0
10
20
30
40
50
60
70
Frequency (GHz)
Figure 5.4: Comparison of series interconnect resistance
extracted from measurements of a short structure.
R1 ≡ Re {ZS1 } , L1 ≡ Im {ZS1 } /ω,
R2 ≡ Re {ZS2 } , L2 ≡ Im {ZS2 } /ω,
(5.4)
where ZSi is determined from Z short (Fig. 2.4) using the T model relationships in Appendix B.
It is normal that R1 and R2 increase with frequency, but their extracted values will appear larger
than usual if there is poor probe-pad contact. In less extreme cases, extractions of the relatively
47
small series resistances can show up negative at high frequencies when the equipment is suboptimal. Such non-physical results were in fact obtained from the measurements performed with
the GSGSG circuit probes (Fig. 5.4).
5.5
Inductors
6.0
50
4.0
Quality Factor, Qeff
40
Reference (A)
GSGSG probes (B)
GSGSG probes (C)
GSG probes w/VNA LRM (D)
GSG probes w/WinCal (E-F)
Effective Resistance, Reff (Ω)
Reference (A)
GSGSG probes (B)
GSGSG probes (C)
GSG probes w/VNA LRM (D)
GSG probes w/WinCal (E-F)
30
2.0
20
0.0
10
0
0
10
20
30
40
50
60
-2.0
70
Frequency (GHz)
0
10
20
30
40
50
60
70
Frequency (GHz)
Figure 5.5: Comparison of the inductor Q after two-step
de-embedding.
Figure 5.6: Comparison of the effective series resistance
of an inductor after two-step de-embedding.
Despite their simple structure, the frequency-dependent characteristics of small mm-wave inductors can be difficult to predict. In particular, simulators have difficulty predicting the inductor
Q, mostly due to problems modeling lossy substrates. Inductor measurements are therefore practical in verifying measurement accuracy when a trusted reference measurement is available. The
sensitivity of Q makes it an ideal benchmark for evaluating measurement quality. Fig. 5.5 shows
that the calibration built into the Wiltron 360B VNA does not reproduce the Q of the reference
measurement. Although the change of probes did make a significant improvement in the measurement of Q (making it finite), it is the LR(R)M implementation in WinCal that appears to be the
most trustworthy. To rule out measurement error, the measurement was redone using the Wiltron
360B built-in calibration, only to confirm the previous statement. Either the Wiltron 360B built-in
LRM implementation is outdated, or its menu system was interpreted incorrectly. In either case,
the simplified (and well understood) calibration procedure makes WinCal the preferred tool.
48
The difficulty in measuring Q is well mirrored in the extracted effective inductor resistance,
Reff . Consequently, it is always advisable to plot Reff , as outlined in Appendix A. Fig. 5.6 shows
that, even without a reference measurement, it is possible to identify bad measurements. Most,
if not all passive devices have losses that increase with frequency. Not only do the losses appear
to decrease for the measurements using the GSGSG probes, but they also become negative. A
negative value is non-physical since a passive device cannot be made active (negative resistance)
by simply shorting out one of its terminals, as is implicitly done when extracting Reff . Of course,
it should always be remembered that non-physical effects can be caused by limitations in the deembedding technique. However, since the measured series resistance in the short de-embedding
structure is also negative, the de-embedding technique would have actually increased the measured
Reff . As for the measurement using setup D, it appears less accurate than those corresponding to
setups E & F, because the losses seem to saturate at higher frequencies. It could even be argued
that they start to drop.
5.6
Transmission Lines
ID
A
B
C
Table 5.2: Transmission Line Measurement Setups
VNA
Cables
Probes
Calibration
HP 8510C
50 GHz flexible
Cascade 50 GHz GSG
VNA LRM
Wiltron 360B 65 GHz semi-rigid GGB 67 GHz GSGSG
VNA LRM
Wiltron 360B 65 GHz semi-rigid Cascade 67 GHz GSG WinCal LRM
It has already been established that, ignoring measurement error, the transmission line deembedding technique presented in Chapter 3 will extract the correct propagation constant irrespective of the pad configuration, provided that the calibrated measurements are reciprocal (s12 = s21 ).
Consequently, measurements of the propagation constant are ideal for eliminating calibrations as
a source of error, leaving only the measurement setup and the probe contact. Table 5.2 lists setups
that were used to perform transmission line measurements. The corresponding results will be used
to show how bad contact and inferior components can affect measurements.
49
Attenuation, α (dB/mm)
1.5
1.5
1.0
1.0
0.5
0.0
0.5
0
10
20
30
40
50
60
0.0
70
0
10
20
Frequency (GHz)
30
40
50
60
70
Frequency (GHz)
Figure 5.7: An overlay of the attenuation constants from
all the lines measured with the GSGSG probes (setup B).
Figure 5.8: An overlay of the attenuation constants from
all the lines measured with the GSG probes (setup C).
When examining measurement data, it has often been observed that losses are very sensitive
to measurement error, making them ideal indicators of measurement accuracy. The noticeable
difference between Figs. 5.7 and 5.8 is a perfect example. The simple fact that the probes were
changed to the Cascade GSG device probes made a significant improvement in the measurement of
the attenuation constant. Although the measurements are still noisy above 40 GHz, they are much
smoother than what was consistently measured with the GSGSG probes. As for the glitch near
50 GHz, it is most likely caused by the mistreated cables, explaining why it is present in both sets
of measurements.
0.9
Metal 9 over 1 w=13.2µm (Reference, A)
Metal 9 over 1 w=13.2µm (GSGSG, B)
Metal 9 over 1 w=13.2µm (GSG, C)
0.6
0.3
0.0
0
10
20
30
40
50
Frequency (GHz)
Figure 5.9: Comparison of attenuation constant extracted
from transmission line measurements.
Despite the bad probe characteristics, most attenuation measurements taken with setup B are
50
relatively close to those of the reference measurement up to a frequency of 20 GHz. Figure 5.9
shows the two that are not. Unlike the measurements performed with setup C, those of setup B
differ significantly from the reference. Since the observed discrepancies only occur in 2 of the 8
transmission line measurements, it can be assumed that they are caused by bad probe contact.
50
6.5
48
6.4
46
6.3
44
6.2
42
40
Propagation Delay, τ (ps/mm)
6.1
0
10
20
30
40
6.0
50
0
10
20
Frequency (GHz)
30
40
50
60
70
Frequency (GHz)
Figure 5.10: Comparison of characteristic impedance extracted from transmission line measurements.
Figure 5.11: Comparison of propagation delay extracted
from transmission line measurements.
Having isolated cases of bad contact, it would be interesting to see how contact can adversely
affect other measured characteristics. Figures 5.10 and 5.11 show that neither the characteristic
impedance, nor the propagation delay appear significantly different. The measurements of setup
B do appear somewhat noisier, but that could easily be attributed to the probes. The apparent
insensitivity to bad contact is readily explained from the expression of ZC and β in terms of RLGC
parameters:
ZC =
s
R + jωL
G + jωC
and
β = Im{γ} = Im
o
np
(R + jωL)(G + jωC) .
(5.5)
Assuming that at most of the observed frequencies, R ≪ ωL and G ≪ ωC, the expressions
simplify to:
ZC ≈
p
L/C
√
and β ≈ ω LC.
(5.6)
Thus, eventually a frequency will be reached beyond which inaccuracies in the measured loss will
have negligible effect on both ZC and τ . As for the low frequency characteristics, their strong
51
dependence on loss will be affected by the poor contact. This result is clearly observed in Figs.
5.12 and 5.13, which focus on the results below 5 GHz.
70
9.0
60
8.0
55
50
7.0
45
40
65
0
1
2
3
4
5
6.0
Frequency (GHz)
Figure 5.12: Low frequency comparison of characteristic impedance extracted from transmission line measurements.
0
1
2
3
4
5
Frequency (GHz)
Figure 5.13: Low frequency comparison of propagation
delay extracted from transmission line measurements.
52
Chapter 6
Characterization and Model Extraction
6.1
Introduction
Designers need to know how to select devices to make circuits function properly, and with immunity to process variations. In this chapter, important device characteristics will therefore be
plotted and discussed to help in selecting the correct device. Models will also be extracted from
the measured characteristics of devices that are seldom covered by the foundry’s design kit.
Three device types will be examined in the following sections. In Section 6.2, microstrip
lines of various configurations will be characterized and modeled using the ADS simulator from
Agilent. The impact of physical parameters on circuit performance will be discussed in detail. In
Section 6.3, varactor measurements will be investigated to help understand the tradeoffs between
the quality factor (Q) and the capacitance ratio. A physical model based on the hyperbolic tangent
will also be extracted. Finally, in Section 6.4, trends in the fT and fMAX characteristics of various
n-MOSFET transistors will be used to determine a more robust biasing scheme and to identify the
device geometries with the highest performance. Note that the measurement results of Section 6.2
was submitted for publication [10].
53
CHAPTER 6. CHARACTERIZATION AND MODEL EXTRACTION
6.2
Microstrip Lines
6.2.1 90-nm RF-CMOS Test Structures
Fabricated Devices
Figure 6.1: Micrograph of the 8 transmission lines implemented in the 90-nm technology. Both the long (600 µm)
and the short (100 µm) lines are present.
Eight pairs of microstrip test structures were designed and fabricated in a pre-production run
of a 90-nm RF-CMOS process (Fig. 6.1). The lines were designed using various conductor and
ground plane configurations. When comparing characteristics, the convention “Metal [x] over [y]
w=[z]µm” will refer to a microstrip line designed with a metal x conductor, a metal y ground
plane, and a conductor width of z µm. For reference, the process uses a 0.9 µm thick metal 8 layer
and a 3.3 µm thick metal 9 layer, both implemented in copper.
Layout
As CMOS technologies advanced beyond the 180-nm node, increasingly stringent metal density
rules prohibited the design of solid ground planes. To accommodate these restrictions, metal
ground planes must now be slotted. In these technologies, the ideal ground plane design implements the maximum allowed metal density with the smallest slot dimension possible. If the slots
are much shorter than the wavelength, they should not affect the line characteristics significantly.
With all microstrip lines designed in the 90-nm process, metal 1 ground planes are constructed
from the unit cell mesh sketched in Fig. 6.2(a), corresponding to a metal density of approximately
65%. For lines constructed with metal 2 ground planes, the metal 2 mesh is positioned such as to
54
cover the slots in the metal 1 mesh (Fig. 6.2(b)). The two meshes are shunted together to reduce
the ground plane resistance and inductance, and increase its effective thickness. A micrograph of
the slotted ground plane from one of the short lines is presented in Fig. 6.3.
Figure 6.3: Micrograph of a slotted ground plane.
Figure 6.2: Mesh pattern used for (a) metal 1 slotted
ground planes (b) metal 2 slotted ground planes.
Characteristic Impedance and Dispersion in Lossy Lines
Current microwave techniques require that transmission lines be designed with a constant and
known characteristic impedance. Among other advantages, such lines allow for simpler matching
schemes. Figs. 6.4 and 6.5 therefore signal a problem for designers requiring a constant value
of ZC below 10 GHz. A similar problem arises for the design of broadband digital circuits. The
variation in propagation delay seen at low frequencies in Figs. 6.6 and 6.7 will inevitably result in
jitter when digital signals are routed over large distances. To better understand the source of these
non-idealities, we must consider the RLGC parameters of the line.
From transmission line theory, it is well known that:
γ=
p
(R + jωL)(G + jωC).
(6.1)
Furthermore, it is known that a line is distortionless when R/G = L/C, since the expression
55
70
80
70
60
60
50
40
Metal 8 over 1 w=9.7µm
50
0
10
20
30
40
50
60
40
70
0
10
20
Frequency (GHz)
30
40
Figure 6.4: Characteristic impedance as a function of frequency for transmission lines fabricated with a metal 9
conductor in the 90-nm process.
70
60
Figure 6.5: Characteristic impedance as a function of frequency for transmission lines fabricated with a metal 8
8.0
8.0
7.5
7.5
7.0
7.0
6.5
6.0
50
Frequency (GHz)
6.5
0
10
20
30
40
50
60
6.0
70
0
10
20
Frequency (GHz)
30
40
50
60
70
Frequency (GHz)
Figure 6.6: Propagation delay as a function of frequency
for transmission lines fabricated with a metal 9 conductor
in the 90-nm process.
for transmission lines fabricated with a metal 8 conductor
in the 90-nm process.
simplifies to [39]:
γ = α + jβ = R
r
√
C
+ jω LC.
L
(6.2)
The line is distortionless since β is proportional to ω, making the propagation delay, τ = β/ω,
constant for all frequencies. Under the “low-loss” approximation, where ωL ≫ R and ωC ≫ G,
√
the effects of R and G become negligible and β ≈ LC. Well behaved lines, for which R and
G do not increase substantially with frequency, have an associated frequency beyond which the
“low-loss” approximation holds. At frequencies below this point, the losses will cause significant
deviations from the ideal. The observed increase in propagation delay at low frequencies is an
56
example of such deviations. A technique developed by Oliver Heaviside proposes to reduce the
delay variation by periodically loading the line with series inductors until the effective RLGC
parameters satisfy R/G = L/C [39]. A similar effect also occurs for the characteristic impedance,
given by:
ZC =
s
R + jωL
.
G + jωC
(6.3)
At sufficiently high frequencies, the “low-loss” approximation simplifies the expression to
p
ZC ≈ L/C. On the other hand, at sufficiently low frequencies, R ≫ ωL and G ≫ ωC, rep
sulting in ZC ≈ R/G. Consequently, the observed increase in ZC as ω → 0 can be attributed
to the low dielectric loss which, combined with the comparatively large conductor loss, produces
a large “DC” characteristic impedance. In order to maintain a constant characteristic impedance,
it was proposed that G be artificially increased by periodically loading the transmission line with
parallel resistors [43]. It is interesting to note that, at the optimal value for G, R/G = L/C, which
simultaneously reduces the delay variation. Indeed, even though intentionally increasing line loss
does appear less sensible than the inductor solution, it has one advantage. Increasing G makes it
possible for the designer to set the characteristic impedance to a desired value, whereas increasing
L inevitably pulls it closer to the “DC” value.
It is important to acknowledge that these non-idealities are not artifacts. They are neither due
to limitations of the measurement system, nor due to those of the de-embedding technique. In
the case of broadband circuits which are affected by the low frequency non-idealities, it would be
beneficial to address these issues through clever circuit design.
Impact of Materials and Geometry on Electrical Characteristics
At the system level, it is often important to minimize propagation delay when routing signals
between blocks. In digital circuits, minimizing this delay yields more headroom, allowing circuits
to either function at higher clock speeds or to incorporate more functionality within the same clock
cycle. In feedback systems, propagation delay can make the difference between a stable and an
unstable loop. Much insight on propagation delay can be gained from the analysis of the effective
57
permittivity given its direct correlation to τ through ǫeff = (τ c)2 .
4.5
4.5
4.0
4.0
3.5
3.0
3.5
0
10
20
30
40
50
60
3.0
70
0
Frequency (GHz)
10
20
30
40
50
60
70
Frequency (GHz)
Figure 6.8: Effective permittivity as a function of frequency for transmission lines fabricated with a metal 9
Figure 6.9: Effective permittivity as a function of frequency for transmission lines fabricated with a metal 8
A preliminary inspection of Figs. 6.8 and 6.9 clearly indicates that wider conductors lead to a
smaller effective permittivity. This is a direct result of the passivation layer having a much higher
permittivity than the low-κ inter-layer dielectrics (ILDs) (see Fig. 6.10). Microstrip lines with
wider conductors more closely resemble parallel plate waveguides. As a consequence, less field
components penetrate the high-κ passivation layers [39].
When compared to lines with metal 9 conductors, those designed with metal 8 conductors have
a noticeably higher effective permittivity. This difference is mainly attributed to the fact that the
high-κ passivation layer does not extend very far over the metal 9 conductor. Consequently, the low
permittivity of air helps offset the high permittivity of the passivation layers. For lines designed
with metal 8 conductors, the low-κ layer of air is now much farther away from the conductor
surface. Moreover, relatively high-permittivity dielectrics are used to fill the space of the absent
metal 9 material. Combined, these factors cause the systematic jump in ǫeff observed between
the lines using different conductor metals. This justification is further confirmed by the spread in
measured ǫeff . The lines designed with metal 8 conductors have a larger spread, due to the larger
difference in permittivities above and below the conductor.
In order to reduce power consumption at mm-wave frequencies, all possible sources of signal
loss, including those present in the transmission media, should be kept to a strict minimum. Com58
Figure 6.10: Cross-section of a typical backend used in advanced IC technologies.
paring Figs. 6.11 and 6.12, we can see that lines with metal 8 conductors suffer more loss than
those with metal 9 conductors. This trend is initially established at low frequencies, indicating
an observable difference in DC resistance. The consistently lower DC resistance of the lines with
metal 9 conductors is a direct result of metal thickness. Given the 0.9 µm thick metal 8 layer and
3.3 µm thick metal 9 layer, even the most narrow metal 9 line has a larger cross-sectional area than
the widest using metal 8.
A second trend, relating to the ground planes, is made evident from the attenuation plots. As
the frequency increases from DC, the lines with a metal 1 ground plane suffer more loss than those
with a metal 2 ground plane. This phenomenon can be explained by the larger effective thickness
of the metal 2 ground planes, given that they are shunted with an additional metal 1 mesh. The
only exception occurs for the most narrow line (w = 3.7 µm). In this case, the skin effect within
the narrow conductor appears to be the dominating factor.
59
1.0
0.6
0.8
0.4
0.6
0.4
0.2
0.2
0.0
0
10
20
30
40
0.0
50
Frequency (GHz)
0
10
20
30
40
50
Frequency (GHz)
Figure 6.11: Attenuation as a function of frequency for
transmission lines fabricated with a metal 9 conductor in
the 90-nm process.
transmission lines fabricated with a metal 8 conductor in
the 90-nm process.
6.2.2 Technology Comparison
Given the insight enabled by the new de-embedding technique, microstrip lines fabricated in a
130-nm RF-CMOS process were revisited in order to cover a larger device space. In addition to
having “ideal” (albeit slotted) metal-over-metal microstrip lines, the test structures from the 130nm technology included two metal-over-substrate lines. Although both processes use very similar
backends, their respective metal layers do have slightly different thicknesses, conductivities and
noticeable differences in height. The largest dissimilarity is that the 130-nm process does not
make use of low-κ dielectrics. To ensure a fair comparison, only lines with conductors designed
in the top-most metal layers will be considered. These conductors are fabricated with a thickness
of 3.3 µm in both technologies. Note that all measurements of the test structures fabricated in the
130-nm RF-CMOS process were measured using the 50 GHz measurement setup.
More on the Loss Impact of Ground Planes
Further supporting the impact of ground plane composition on loss, Figs. 6.13 and 6.14 show a
remarkable agreement between both technologies. To help place these results further into context,
it is relevant to note that the 130-nm process is also subject to metal density rules restricting ground
planes to the slotted form. However, the more relaxed design rules of the 130-nm process have
60
made it possible to create ground planes with a higher metal density of approximately 88%. The
close match is therefore be attributed to the similar thicknesses of corresponding ground planes.
Although the lines with metal 2 ground planes fabricated in the 130-nm process also have their
ground planes shunted with a mesh of metal 1, both meshes are perfectly aligned, not offset. This
supports the claim in 6.2.1 that slots should not affect the line characteristics significantly.
0.6
0.6
0.4
0.4
0.2
0.2
50Ω metal 8 over 1 w=11.0µm (130-nm)
Metal 9 over 1 w=13.2µm (90-nm)
0.0
0
10
20
30
40
0.0
50
Frequency (GHz)
Figure 6.13: Technology comparison of the attenuation
in lines designed with the topmost conductor and a metal
1 ground plane.
0
10
20
30
40
50
Frequency (GHz)
Figure 6.14: Technology comparison of the attenuation
in lines designed with the topmost conductor and a metal
2 ground plane.
Provided that microstrip lines constructed over unshielded silicon are widely used, it is interesting to compare them to metal-over-metal lines. Figure 6.15 clearly shows that they become
extremely lossy at frequencies above 8 GHz. Also, wider metal-over-substrate lines are significantly worse at high frequencies than narrow lines, due to increased substrate coupling. These
results agree with those presented in [44] for a SiGe HBT process, and [35] for a technology with
a 0.1-0.2 Ω·cm substrate.
Characteristic Impedance and Dispersion in Lines Over Unshielded Silicon
Microstrip lines routed directly over unshielded silicon also pose challenging matching problems.
As can be seen from Fig. 6.16, these lines do not even exhibit a constant characteristic impedance
at high frequencies. Moreover, Fig. 6.17 shows that propagation delay is both longer and far more
frequency-dependent in metal-over-substrate lines. The large delay variation with frequency leads
to increased deterministic jitter in broadband digital circuits, as discussed in section 6.2.1.
61
3.0
50Ω metal 8 over 1 w=11.0µm
Metal 8 over substrate w=10.0µm
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
Frequency (GHz)
transmission lines fabricated in the 130-nm process.
160
11.0
10.0
120
9.0
100
8.0
80
60
40
140
7.0
0
10
20
30
40
50
6.0
Frequency (GHz)
Figure 6.16: Characteristic impedance as a function of
frequency for transmission lines fabricated in the 130-nm
process.
0
10
20
30
40
50
Frequency (GHz)
for transmission lines fabricated in the 130-nm process.
More on the Impact of Materials on Electrical Characteristics
With respect to permittivity, Fig. 6.18 again shows a clear width dependance in accordance with
Fig. 6.8. Since the 130-nm process does not make use of low-κ dielectrics, the extracted values of
ǫeff are also higher than those of Fig. 6.8.
6.2.3 Simulation
In the backend of state-of-the-art technologies, the composition of the dielectric layers between the
top conductor and the ground plane is non-uniform. As an example, copper backends using the dual
62
4.5
4.0
3.5
3.0
0
10
20
30
40
50
Frequency (GHz)
Figure 6.18: Effective permittivity as a function of frequency for transmission lines fabricated in the 130-nm
process.
Damascene process require etch stop layers [45] with permittivities differing from the principal
dielectric material. A transmission line model supporting multiple dielectrics and permittivities
is therefore required to simulate microstrip lines in such technologies. The coupled lines model,
available for the ADS simulator from Agilent Technologies, is perfectly suited for this application.
Unfortunately, the current version of this model cannot simultaneously describe each dielectric
layer and account for the loss of the ground plane. In consequence, the model was first used to
define a single conductor over an ideal lossless ground plane. This method consistently matched
the measured characteristic impedance to within approximately 5%. Despite long simulation times,
the results are quite adequate for circuit design when measurements are not available.
To improve the accuracy and speed up simulation time, two coupled lines were then employed
to simulate a conductor over a lossy ground plane of finite extent. Simulations using this configuration still modeled the individual passivation layers, but employed a single effective dielectric
to capture the entire sandwich found between the conductor and the ground plane. The permittivity of this effective dielectric was empirically fitted to the measured characteristic impedance.
The results were able to closely fit measurements for both conductor widths that use the same
conductor-ground layer pairs (ex: Figs. 6.19 and 6.20). Note that, although there appears to be a
large discrepancy with the simulated attenuation, the error is actually quite small. If attenuation
is referred back to the ratio of power being transferred over an effective de-embedded length of
63
80
Metal 9 over 2 w=12.0µm (measured)
Metal 9 over 2 w=12.0µm (simulated)
70
60
50
40
0
10
20
30
40
50
60
70
Frequency (GHz)
Figure 6.19: Measurement vs. simulation for characteristic impedance.
500 µm, the discrepancy is revealed to be less than 3% (Fig. 6.21).
1.00
Power Transfer Ratio (500µm line)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
10
20
30
40
0.95
0.90
0.85
0
10
20
30
40
50
Frequency (GHz)
50
Frequency (GHz)
Figure 6.20: Measurement vs. simulation for attenuation.
Figure 6.21: Measurement vs. simulation for the ratio of
power being transferred over an effective de-embedded
length of 500 µm.
64
6.3
Accumulation-Mode MOS Varactors
6.3.1 Fabricated Devices
Figure 6.22: Micrograph of the accumulation-mode MOS
varactor test structures fabricated in the 90-nm RFCMOS technology.
Six accumulation-mode varactor test structures were fabricated in a pre-production run of a
90-nm RF-CMOS process (Fig. 6.22). To assist in characterization and model extraction, two
experiments were performed: one in which the gate length (L) was varied while the gate finger
width (Wf ) was kept constant, and one in which Wf was varied while L was kept constant.
6.3.2 Structure
Figure 6.23: Cross-section of the accumulation-mode
MOS varactor.
Accumulation-mode MOS varactors are easily accommodated by CMOS technologies. The
foundry simply has to allow an n-MOS structure to be formed within in an n-well. In the circuit,
65
the “source and drain regions” of the varactor are biased at different voltages, tuning the MOS
capacitance. To a first order, the varactor capacitance is controlled only by the gate-to-source/drain
voltage, VGSD .
Three gate lengths are of importance when modeling MOSFETs and accumulation mode varactors. First, there is the physical gate length (L), which corresponds to the width of the polysilicon
trace. Next, there is the drawn length (Ldrawn ), which corresponds to the length specified by the
designer in the IC layout tool. The latter is related to L by the width of the nitride spacer (LNS )
located at either side of the gate: Ldrawn = L + 2LNS . Finally, there is the effective gate length
(Leff ), which captures the lateral diffusion by LD of the source and drain regions under the gate:
Leff = L − 2LD [2].
The varactor is typically used as a one port admittance loading the circuit through the “gate”
terminal, as sketched in Fig. 6.23. Consequently, the effective capacitance (Ceff ) and quality factor
(Qeff ) seen looking into the gate terminal are of prime importance to a designer. For this reason,
the following section examines the measured Ceff and Qeff curves of all fabricated devices.
6.3.3 Effective Characteristics
S parameter measurements of the varactors were performed at multiple VGSD bias points, and
de-embedded using the two-step technique. The resulting Ceff and Qeff curves are included in
Figs. 6.24 and 6.27.
The measurements at VGSD = 0.6 V clearly show that the capacitance scales well with both
the gate width and length. Similarly, Fig. 6.27 shows a trend of decreasing quality factor with
increasing gate width. This can be explained by the fact that Qeff ∝
1
Ceff Reff
where, to a first
order, Ceff ∝ Wf L and Reff ∝ Wf /L are the series capacitance and resistance. Since both Ceff
and Reff increase with gate width, Qeff is expected to decrease. In the ideal case, Qeff should not
vary with gate length. However, a significant component of the series resistance does not scale
with L. Consequently, an increase in gate length does not reduce the Reff enough to counteract
the increase in Ceff , explaining the observed reduction in Qeff with L in Fig. 6.26 for large VGSD .
66
70
60
150
L=65nm
L=95nm
L=145nm
L=215nm
Wf=1µm
Wf=2µm
Wf=4µm
120
40
Ceff (fF)
Ceff (fF)
50
30
90
60
20
30
10
0
-0.6
-0.4
-0.2
0.0
0.2
0.4
0
-0.6
0.6
-0.4
-0.2
VGSD (V)
0.0
0.2
Figure 6.24: Effective capacitance measured from MOS
varactors of various gate lengths.
30
L=65nm
L=95nm
L=145nm
L=215nm
25
Wf=1µm
Wf=2µm
Wf=4µm
25
20
20
f=40GHz
Qeff
f=40GHz
Qeff
0.6
Figure 6.25: Effective capacitance measured from MOS
varactors of various gate widths.
30
15
15
10
10
5
5
0
-0.6
0.4
VGSD (V)
-0.4
-0.2
0.0
0.2
0.4
0
-0.6
0.6
-0.4
-0.2
VGSD (V)
0.0
0.2
0.4
0.6
VGSD (V)
Figure 6.26: Effective quality factor measured at 40 GHz
from MOS varactors of various gate lengths.
Figure 6.27: Effective quality factor measured at 40 GHz
from MOS varactors of various gate widths.
Conversely, Table 6.1 shows that the ratio of the maximum to minimum achievable capacitance
(Cratio ) increases with L and Wf due to the fringing gate capacitance. Consequently, there is a
tradeoff between Qeff and Cratio .
L (nm)
Cratio
Table 6.1: Effective Capacitance Ratios
Wf = 2 µm
L = 215 nm
65
95
145 215 Wf (µm)
1
2
2.51
2.99
3.44
4.09
67
Cratio
3.56
4.09
4
4.31
Figure 6.29: Simplified accumulation-mode MOS varactor model.
Figure 6.28: Accumulation-mode MOS varactor model.
6.3.4 Parameter Extraction
Fig. 6.28 shows a physical model for the accumulation-mode MOS varactor [46, 47]. Given the
limited accuracy in measuring the varactor test structures, the simplified model of Fig. 6.29 was
found adequate for extraction. The electrical parameters of each device were therefore extracted
using:
Cv + Cf ≈
−1
,
Im{Z1 }ω
(6.4)
Rgc + Rg + Rch ≈ Re{Z1 },
(6.5)
Rsd = Re{Z2 },
(6.6)
Rsub = Re{Z3 },
(6.7)
and Cnw =
−1
.
Im{Z3 }ω
(6.8)
where Z1 ≡ z11 − z12 , Z2 ≡ z22 − z12 , and Z3 ≡ z12 , as described in Appendix B. Some of the
more important parameters are included in Table 6.2.
6.3.5 Physical Model Extraction
With the electrical parameters known, a scalable physical model can be extracted from plots of
the various parameters versus gate width and length (Appendix D). Note that all parameters are
68
Nf
L (nm)
10
10
10
10
10
10
65
95
145
215
215
215
Table 6.2: Extracted Electrical Parameters
Wf (µm) Cv,max + Cf (fF) Rgc + Rg + Rch (Ω)
2
2
2
2
1
4
27.4
34.7
46.0
64.0
34.2
127.0
18
16.5
14
12.5
17
11
Rsd (Ω)
4
2.5
2.5
2
6
1.5
normalized per unit finger to simplify the extraction process.
First, the intercept of Cv,max + Cf (Cv @ VGSD = 0.6 V) plotted versus Wf yields Cgbo , a
constant term due to the overlap capacitance of the polysilicon trace contacting the gate. The oxide
capacitance per unit area (Cox ) is extracted from the slope of Cv,max + Cv versus gate area plotted
′
′
for various gate lengths. The intercept of the plot gives Wf Cf + Cgbo , where Cf is the fringing
capacitance per finger width. The total oxide capacitance and fringing capacitance are therefore
given by:
Cv,max = Cox Wf L + Cgbo = 12.1Wf L + 0.24 (fF),
′
and Cf = Cf Wf = 0.455Wf (fF).
(6.9)
(6.10)
where both L and Wf are in µm.
The distributed gate sheet resistance, which is 1/3 of the DC sheet resistance (R2g ) [2], is
extracted from the slope of Rgc + Rg + Rch versus the number of squares, plotted for various gate
lengths. If R2g is then used to remove the effects of Rg , the slope of Rgc + Rch versus 1/Wf yields
′
the width-dependent channel resistance (Rch ), and the intercept gives Rgc .
Wf
R2g Wf
= 2.69
(Ω),
3 L
L
′
R
127
Rch = ch =
(Ω),
Wf
Wf
Rg =
and Rgc = 31.5 Ω.
(6.11)
(6.12)
(6.13)
′
The width dependence of the source/drain resistance (Rsd ) is extracted from the slope of Rsd
69
versus 1/Wf . The resistance is not dependent on gate length:
′
Rsd =
63
Rsd
=
(Ω).
Wf
Wf
(6.14)
Parameters Cnw and Rsub do not vary strongly with Wf and L, and do not affect the varactor
characteristics significantly. The average value from all measured devices was therefore used to
simplify the physical model.
70
150
Wf=1µm
Wf=2µm
Wf=4µm
Simulated
L=65nm
L=95nm
L=145nm
L=215nm
Simulated
60
50
Ceff (fF)
Ceff (fF)
100
40
30
50
20
10
0
-0.6
-0.4
-0.2
0.0
0.2
0.4
0
-0.6
0.6
-0.4
-0.2
VGSD (V)
0.0
0.2
0.4
0.6
VGSD (V)
Figure 6.30: Measured vs. simulated effective capacitance for MOS varactors of various gate lengths.
Figure 6.31: Measured vs. simulated effective capacitance for MOS varactors of various gate widths.
40
30
L=65nm
L=95nm
L=145nm
L=215nm
Simulated
25
Wf=1µm
Wf=2µm
Wf=4µm
Simulated
30
20
Qeff
Qeff
f=40GHz
15
20
f=40GHz
10
10
5
0
-0.6
-0.4
-0.2
0.0
0.2
0.4
0
-0.6
0.6
VGSD (V)
Figure 6.32: Measured vs. simulated effective quality
factor sampled at 40 GHz for MOS varactors of various
gate lengths.
-0.4
-0.2
0.0
0.2
0.4
0.6
VGSD (V)
Figure 6.33: Measured vs. simulated effective quality
factor sampled at 40 GHz for MOS varactors of various
gate widths.
The simulated effective one port capacitance and quality factor of the physical model are compared to the measured quantities in Figs. 6.30-6.33. The effective capacitance is well modeled, but
70
measurement accuracy limits the accuracy of Qeff . The deviations are most pronounced in shorter
gate length devices, where Qeff is overestimated. Note that the Cv curve was modeled using a
hyperbolic tangent function [46].
6.4
n-MOSFETs
6.4.1 Fabricated Devices
Figure 6.34: Micrograph of the n-FET test structures fabricated in the 90-nm RF-CMOS technology.
Twelve n-MOSFET test structures were fabricated in a pre-production run of a 90-nm RFCMOS process (Fig. 6.34). As with the varactors, gate width and length experiments were performed to assist in characterization and model extraction. The measured S parameters were deembedded using the two-step method, and a scalable physical model was extracted [48]1 . In the
following section, the measured fT and fMAX performance will be examined to determine optimal
device sizes and bias points.
6.4.2 Biasing and Sizing for Optimal Performance
Figs. 6.35 and 6.37 both show that the transistor gain is larger for shorter gate lengths, as expected.
Similarly, Fig. 6.36 clearly indicates that fT increases with gate finger width (Wf ). Given that
ideally, small signal parameters gm , Cgs and Cgd scale linearly with Wf , and that to a first order
1
Model extraction was performed by Sorin Voinigescu.
71
2πfT = gm /(Cgs + Cgd ), fT should be mostly independent of Wf . However, modern CMOS
processes require the polysilicon gate to extend beyond the intrinsic device to ensure its proper
formation and provide a point of contact. As a side-effect, the extra polysilicon creates a Wf independent gate-to-bulk overlap capacitance (Cgbo ), which appears in parallel with Cgs . The parasitic capacitance therefore reduces fT more significantly when Wf is small. In contrast, Fig. 6.38
shows that fMAX decreases with Wf . Being very sensitive to gate resistance (Rg ), fMAX increases
significantly as the series Rg is reduced in devices with shorter gate widths. Eventually, a point of
diminishing returns is encountered, where the detrimental effects of Cgbo overtakes the benefits of
the lower resistance, as observed when Wf = 0.5 µm.
140
160
L=65nm
L=95nm
L=145nm
L=215nm
L=315nm
120
120
fT (GHz)
fT (GHz)
100
80
VDS=0.7V
60
40
Wf=4µm
Wf=2µm
Wf=1µm
Wf=0.5µm
VDS=0.7V
80
40
20
0 -3
10
10
-2
IDS/W (mA/µm)
10
-1
10
0 -3
10
0
Figure 6.35: Measured fT as a function of drain current
per unit gate width for Wf = 1 µm MOSFETs of different
gate lengths.
10
-2
IDS/W (mA/µm)
10
-1
10
0
per unit gate width for L = 65 nm MOSFETs of different
gate widths.
In all devices, the peak fT current density is found near 0.3 mA/µm and the peak fMAX current density is found near 0.2 mA/µm. It is therefore simple to bias an n-MOS transistor at its
peak performance. Peak fT /fMAX current density biasing is also very robust since it maximizes
the available transistor performance under process variations such as gate length variations, and
threshold voltage variations (Figs. 6.39 and 6.40 [49]). Near optimal performance is also maintained if the bias current varies by a factor of 2. Moreover, the invariants Jpeak−fT ≈ 0.3 mA/µm
and Jpeak−fMAX ≈ 0.2 mA/µm have been observed across many technology nodes and foundries,
making the biasing technique universally applicable. These results, and more are explained in
detail in [42].
72
200
150
fMAX (GHz)
fMAX (GHz)
150
200
L=65nm
L=95nm
L=145nm
L=215nm
L=315nm
VDS=0.7V
100
50
0 -3
10
10
-2
IDS/W (mA/µm)
10
-1
10
0 -3
10
0
Figure 6.37: Measured fMAX as a function of drain current per unit gate width for Wf = 1 µm MOSFETs of
different gate lengths.
10
-2
IDS/W (mA/µm)
-1
10
0
100
Low VT
Standard VT
High VT
fMAX (GHz)
80
60
40
Low VT
Standard VT
High VT
60
40
VDS=0.8V
VDS=0.8V
20
0 -3
10
10
Figure 6.38: Measured fMAX as a function of drain current per unit gate width for L = 65 nm MOSFETs of
different gate widths.
100
fT (GHz)
VDS=0.7V
100
50
80
Wf=4µm
Wf=2µm
Wf=1µm
Wf=0.5µm
20
10
-2
IDS/W (mA/µm)
10
-1
10
0 -3
10
0
per unit gate width for devices of different threshold voltages. The devices were fabricated in a 130-nm technology.
10
-2
IDS/W (mA/µm)
10
-1
10
0
Figure 6.40: Measured fMAX as a function of drain current per unit gate width for devices of different threshold
voltages. The devices were fabricated in a 130-nm technology.
73
Chapter 7
Conclusion
7.1
Summary
The focus of this thesis has been to present new techniques that help leverage the power of measurements to characterize and model devices of nano-CMOS technologies well into the mm-wave
regime. A new transmission line de-embedding technique was presented and applied to microstrip
test structures fabricated in a 90-nm RF-CMOS process. The effects of their geometry, dielectric
composition, and ground plane configuration were analyzed and related to circuit performance.
The transmission line de-embedding technique was also extended to construct a more general,
area-efficient de-embedding technique that applies to other devices and circuits.
Relying only on previously available de-embedding techniques, much characterization work
was also performed on accumulation-mode MOS varactors and n-MOSFET transistors from the
same 90-nm RF-CMOS process. A technique for extracting a scalable physical MOS varactor
model was devised, and certain geometry-dependent properties of n-MOSFETs were confirmed at
the 90-nm node. In particular, the peak fT and fMAX current densities were observed at 0.3 mA/µm
and 0.2 mA/µm, respectively, for all geometries, confirming the robust nature of constant current
density biasing schemes.
74
CHAPTER 7. CONCLUSION
7.2
Future Work
To further validate the new transmission line based de-embedding technique of Chapter 4, the
proposed test structures should be fabricated and measured, in order to compare its accuracy with
that of existing techniques. Along with the validation experiment, transmission line test structures
of varying lengths should be fabricated to determine the minimum lengths required to maintain
accurate results. As explained by the derivations, the short transmission line test structure must
be short enough to ensure |γℓ| ≪ 1, but there is no theoretical limit on its minimal length. In
practice, the length cannot be made infinitesimally small since probe coupling will become an
issue. Although measurements have shown that a test structure pair measuring 100 µm for the
short line and 600 µm for the long line is adequate, more research is needed to find optimal lengths
which will minimize the cost in silicon area. Finally, on-wafer short circuit pad structures should
also be fabricated in order to confirm the magnitude of the contact impedance. If the contact
impedance is as large as predicted in Chapter 4, de-embedding techniques should be adjusted
to account for those parasitics. If not, the results may point to other problems, such as model
limitations or inaccuracies in the calibration technique.
Another interesting experiment would be to compare the characteristics of microstrip lines
with, and without metal fill exclusion around the line. To help with the planarization in backends
with several metal layers, dummy patches of metal are normally added across the entire wafer,
to keep a uniform metal density. It would therefore be important to investigate if the presence of
metal fill adversely affects transmission line characteristics, so that potential yield problems from
its absence can be avoided.
75
Appendix A
Effective Characteristics of One Port
Networks
Ideally, a full characterization of all ports intrinsic to the device under test should be performed.
In practice, limitations such as availability of equipment and the complexity of the calibration
technique restrict the device engineer to a maximum of two ports. From a design perspective,
′
it is often preferable to simplify the problem by looking at a degenerate case (n < n) of an nport network. A common example of such a situation occurs when two-port networks have a port
shunted to small signal ground. For example, one might have a load or peaking inductor connected
to the power supply, such as LD in the BiCMOS cascode topology of Fig. A. Similarly, one might
have a transistor with a degeneration inductor connected to ground (LS ). One might also have the
bulk terminal of a MOS varactor connected to a DC control voltage. In those cases, a degenerate
one-port network with input admittance, Yeff , is readily obtained from Y parameters:
Yeff
I1 =
= y11 ,
V1 V2 =0
(A.1)
where port 2 is implicitly shunted (Fig. A). Note that the roles of the input and shunted ports can
be just as easily reversed by considering Yeff = y22 .
Applying this technique to the inductor in our example, it is possible to extract an effective
76
APPENDIX A. EFFECTIVE CHARACTERISTICS OF ONE PORT NETWORKS
Figure A.2: Degenerate one port network.
Figure A.1: BiCMOS cascode topology.
inductance, resistance, and quality factor (Q):
Figure A.3: One port inductor model.
Leff =
Im {1/Yeff }
, Reff = Re {1/Yeff } ,
ω
Qeff = −
Im {Yeff }
.
Re {Yeff }
(A.2)
Similarly, it is possible to extract the effective capacitance, resistance, and Q of a capacitor:
Figure A.4: One port capacitor model.
Ceff =
−1
, Reff = Re {1/Yeff } ,
Im {1/Yeff } ω
Qeff =
Im {Yeff }
.
Re {Yeff }
(A.3)
Note that Qeff presented above is known as the “conventional Q”. Insight on the meaning of
the conventional Q, along with definitions of alternative quality factors are presented in [50]. A
77
APPENDIX A. EFFECTIVE CHARACTERISTICS OF ONE PORT NETWORKS
more general explanation of its meaning can also be found in [39] (pp. 266-269).
Applications where one might want to degenerate a two port network are not limited to the
above cases. A situation might occur where the two port matrix of a transmission line segment
is known, but only the effective impedance of the line as an open ended stub is of interest. In
this case, one of the ports can be left open by forcing a zero current at port 2, a situation better
described using Z parameters:
Zeff
V1 =
= z11 ,
I1 I2 =0
78
(A.4)
Appendix B
T and Π Network Models
Figure B.2: Π two port network model.
Figure B.1: T two port network model.
Two commonly used equivalent circuit representations of linear reciprocal (z12 = z21 , y12 =
y21 , or equivalently s12 = s21 ) networks are the T and Π models (Figs. B and B.2). These
circuit representations are often used in device extraction, due to the simplicity in determining
impedance/admittance values from the Z and Y parameters:
Z1 = z11 − z12
and Y1 = y11 + y12
Z2 = z22 − z12
Y2 = y22 + y12
79
Z3 = z12 ,
Y3 = −y12 .
(B.1)
(B.2)
Appendix C
Transistor Figures of Merit
The two principal high frequency figures of merit (FoM) for transistors are the transition frequency,
fT and the maximum frequency of oscillation, fMAX . In both cases, the FoMs are extracted from
measurements of the transistor connected in the common source/emitter configuration (Fig. C.1).
To avoid underestimating the transistor performance, a de-embedding technique such as the twostep method (Section 2.3.2) or the new technique presented in Chapter 4 should be used to remove
the parasitic contributions of the test structure.
Figure C.1: MOSFET test structure in common source
configuration.
C.1
Transition Frequency, fT
The transition (cutoff) frequency is defined as the frequency where the small signal current gain is
unity. Since in common source configuration the input terminal is the gate (port 1) and the output
d
| = 1. Given the port assignment
is at the drain (port 2), fT is defined as the frequency where | ∂I
∂Ig
80
APPENDIX C. TRANSISTOR FIGURES OF MERIT
from Fig. C.1 and the knowledge that the H parameter h21 ≡
∂I2
∂I1
≡
∂Id
,
∂Ig
fT can be expressed
simply as:
fT ≡ f ||h21 |=1 .
(C.1)
In general, fT is bias dependent and has been observed to peak at a drain/collector current
density of 0.3 mA/µm for submicrometer n-MOSFETs. Further information on fT and its relationship to the physical/electrical parameters of the transistor (FET or bipolar) can be found in
[42, 45, 51–56]1 .
C.2
Unilateral Power Gain, U
The unilateral power (Mason’s) gain is defined as the maximum achievable power gain of a linear
′
′
′
two port network which has been rendered unilateral (z12 = y12 = s12 = 0) through the use of a
lossless reciprocal network [57]. Equivalent expressions for the unilateral gain have been derived
as a function of Z, Y , and S parameters:
1
|z12 − z21 |2
·
,
4 Re{z11 }Re{z22 } − Re{z12 }Re{z21 }
|y12 − y21 |2
1
,
U= ·
4 Re{y11 }Re{y22 } − Re{y12 }Re{y21 }
1
|s21 /s12 − 1|2
and U = ·
,
2 k|s21 /s12 | − Re{s21 /s12 }
U=
(C.2)
(C.3)
(C.4)
where k is the stability factor:
k=
1 − |s11 |2 − |s22 |2 + |s11 s22 − s12 s21 |2
.
2|s12 s21 |
1
(C.5)
Reference [52] labels the transition frequency as fmax , a symbol which is normally reserved for the maximum
oscillation frequency.
81
APPENDIX C. TRANSISTOR FIGURES OF MERIT
C.3
Maximum Oscillation Frequency, fMAX
Similar to fT , the maximum oscillation frequency is defined as the frequency where the (small
signal) unilateral power gain is unity:
fMAX ≡ f ||U |=1 .
(C.6)
In general, fMAX is also bias dependent and has been observed to peak at a drain/collector
current density of 0.2 mA/µm for submicrometer n-MOSFETs [42].
82
Appendix D
Varactor Parameter Extraction
The following plots were used in extracting the physical varactor model in section 6.3.
8
16
6
Cv,max + Cf (fF)
Cv,max + Cf (fF)
12
y = 12.1x + 1.15
4
8
y = 3.11x + 0.24
2
4
0
0.0
0.1
0.2
0.3
2
0.4
0.5
0
0.0
Gate Area (µm )
Figure D.1: Measured Cv,max + Cf vs. gate area normalized per unit finger for Wf = 2 µm varactors of varying
gate lengths.
1.0
2.0
3.0
4.0
Wf (µm)
Figure D.2: Measured Cv,max + Cf vs. finger width normalized per unit finger for L = 215 nm varactors.
83
APPENDIX D. VARACTOR PARAMETER EXTRACTION
200
160
150
120
Rgc + Rch (Ω)
Rgc + Rg + Rch (Ω)
y = 2.69x + 103
100
y = 127x + 31.5
80
50
40
0
0
10
5
20
15
25
30
0
0.0
Number of Squares
Figure D.3: Measured Rgc + Rg + Rch vs. number of
squares per gate finger for Wf = 2 µm varactors of varying gate lengths.
0.2
0.4
-1 0.6
1/Wf (µm )
0.8
1.0
Figure D.4: Measured Rgc + Rch vs. 1/Wf normalized
per unit finger for L = 215 nm varactors.
60
50
50
40
40
30
Rsd (Ω)
Rsd (Ω)
y = 31.5
30
y = 62.9x - 5
20
20
10
0
10
0
50
100
150
200
0
0.0
250
L (nm)
Figure D.5: Measured source/drain resistance vs. gate
length normalized per unit finger for Wf = 2 µm varactors of varying gate lengths.
0.2
0.4
-1 0.6
1/Wf (µm )
0.8
1.0
Figure D.6: Measured source/drain resistance vs. 1/Wf
normalized per unit finger for L = 215 nm varactors of
varying gate widths.
84
Appendix E
List Of Symbols
α
Attenuation constant (Np/m)
β
Phase constant (rad/m)
γ
Propagation constant
ǫ
Permittivity
ǫeff
Effective permittivity
κ
Dielectric constant
τ
Propagation delay
µ
Permeability
ω
Angular frequency (rad/sec)
A
Transmission (ABCD) matrix entry
B
c
Speed of light in free-space (2.998 × 108 m/s)
C
Transmission (ABCD) matrix entry; Capacitance per unit length (F/m)
Ceff
Effective capacitance
Cf
Fringing capacitance
′
Cf
Fringing capacitance per unit length (F/m)
Cgbo
Gate-bulk oxide capacitance
85
APPENDIX E. LIST OF SYMBOLS
Cgd
Gate-drain capacitance
Cgs
Gate-source capacitance
Cnw
N-well capacitance
Cox
Oxide capacitance (F/m2 )
Cpad
Pad capacitance
Cratio
Capacitance ratio
Cv
Varactor capacitance
Cv,max
Maximum varactor capacitance
D
Dnw
N-well diode
f
Frequency (Hz)
fT
Transition frequency
fMAX
Maximum oscillation frequency
gm
Transconductance (A/V)
G
Conductance per unit length (S/m)
Jpeak−fT
Peak fT current density (A/µm)
Jpeak−fMAX
Peak fMAX current density (A/µm)
L
Inductance per unit length (H/m); Physical gate length
Ldrawn
Drawn gate length
Leff
Effective inductance; Effective gate length
Lg
Gate inductance
Q
Quality factor
Qeff
Effective quality factor
R
Resistance per unit length (Ω/m)
Rch
Channel resistance
′
Rch
Channel resistance times gate width (Ω-m)
Reff
Effective resistance
86
APPENDIX E. LIST OF SYMBOLS
Rg
Gate resistance
R2g
Gate sheet resistance (Ω/2)
Rgc
Gate contact resistance
Rnw
N-well resistance
Rsd
Source-drain resistance
′
Rsd
Source-drain resistance times gate width (Ω-m)
Rsub
Substrate resistance
sij
S parameter matrix entry
S
S parameter matrix
T
Transmission (ABCD) matrix
up
Phase velocity (m/s)
U
Unilateral (Mason’s) power gain
W
Total gate width
Wf
Gate finger width
yij
Y parameter matrix entry
Y
Y parameter matrix
zij
Z parameter matrix entry
Z
Z parameter matrix
Zct
Contact impedance
ZC
Characteristic impedance
87
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