EUROPEAN “NANOMETRIC” CMOS PROJECTS

Transcription

EUROPEAN
“NANOMETRIC” CMOS
PROJECTS
Σ! 2365
Guillermo Bomchil
STMicroelectronics
21/11/05. G.Bomchil. MEDEA+ Forum 2005. Barcelona
2
CONTENTS
European projects: from 90 nm to 32-22 nm
MEDEA+ T201 90 nm: industrial exploitation
MEDEA+ T207 65 nm: present status
EC NANOCMOS 45 nm: present status
Future projects
MEDEA+ 2T 103: 45 nm Full CMOS Integration
EC PULLNANO: Pushing the limits of CMOS
Added value of the collaboration and conclusions
G.Bomchil. MEDEA+ Forum 2005 Barcelona
3
NANOELECTRONICS PROJECTS
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
100 nm FEOL
HUNT
ITRS 90
MEDEA+ T201 90 nm full CMOS integration
ARTEMIS
65 nm BEOL
65 nm FEOL
ITRS 65
ULISSE
65 nm full CMOS integration
MEDEA+ T207
dev. architecture
45 – 32 – 22 nm
NESTOR
MEDEA+ HYMNE 65/45 nm manufacturing sciences
45 nm FEOL/BEOL + SRAM
ITRS 45
NANOCMOS
MEDEA+ 2T103
Strained Silicon on SOI
45 nm full CMOS integr.
MEDEA+ SILONIS
32 nm FEOL/BEOL + SRAM + 22 nm
PULLNANO
32 nm full CMOS integration
MEDEA+ T 32nm
4
T201 90 nm Strategic Objectives
Development of worldwide competitive

90 nm CMOS logic technology
Demonstrator: 54 M tr, 300 M contacts,
9 Km of interconnects (Cu-low k )
Start- end: 01/2001 – 12/2002
Consortium: ST MicroelectronicsPHILIPS Semiconductors, BULL,
LEICA, IMEC, LETI, PHILIPS Research,
AIR LIQUIDE, AIXTRON, EPICHEM,
JOBIN YVON, INPG/CNRS, LTM/CNRS
Objectives were achieved as schedule
The project obtained the JPN award
2004
Bulk silicon, 1.6 nm nitrided
gate oxide, cobalt salicide,
5
CMOS 90 nm industrial exploitation

The 90 nm products were introduced in Crolles 2, the joint
FREESCALE, PHILIPS Semiconductors and ST Microelectronics
300 mm pilot manufacturing facility.
90 nm products include digital, analog, RF and embedded
memory devices for diverse applications, such as wireless
handsets, printers, networking components,…
In many cases the products had 100 % first-pass success rate
demonstrating design efficiency and optimum use of technology
and manufacturing capabilities.
Altogether the three partners, starting from October 2003,
report more than 25 processed circuits for their customers.
The partners consider that they have addressed many of the
industry’s widely reported challenges with 90 nm and are
applying the expertise to the next generations of technology.
“The achievements at 90 nm over the past year set the stage for
successful 65 nm prototyping from end 2005”!
6
Some examples of 90nm circuits
Code
Name
Option
Market
Status / comments
A
Olympus2b
GP. 9ML
uProcessor
PG Oct’03. 120mm2
B
Crystal
LP. 8ML
Hardware
emulator
PG April’04. 240mm2
PG cut2 Feb’05
C
PIAGET
GP . 7ML
TV
PG May’04 ~70mm²
D
7100
GP . 7ML
Set Top Box
PG Oct’04 ~80mm². PG cut2
E
ADV1
GP . 7ML
Set Top Box
PG Sept’04 ~30mm²
H
8010
GP. 7ML
DVD recorder
PG Dec’04 ~45mm²
G
GSP3
LP. 6ML
GPS Mobile
PG Dec’04. 9mm²
I
288
GP. 7ML
Demodulator
PG Apr’05. 3mm²
J
DARS3G
GP. 7ML
Decoder
PG Apr’05. 20mm²
K
Bigoot
LP. 7ML.
eDRAM
Decoder
PG May’05. 45mm²
L
5525
GP. 7ML
Set Top Box
PG June’05. 43mm²
M
7109
GP. 7ML
Set Top Box
PG July’05. 72mm²
N
COST3
LP. 7ML
WLAN
PG Aug’05. 9mm²
7
T207 CMOS 65 nm design rules
Design Rule
pitch (L/S) in nm
OD
PO
CO
M1
Vx
Mx
SRAM cell size
(um2)
Gate density
(kgt/mm2)
9 tracks
12 tracks
14 tracks
CMOS12
360
310
340
340
410
410
(210/150)
(180/130)
(180/160)
(180/160)
(220/190)
(210/200)
2.5
2.07
200
CMOS090
250
240
260
240
280
280
(110/140)
(100/140)
(120/140)
(120/120)
(130/150)
(140/140)
1.27
1.15
0.999
CMOS065
190 (80/110)
180 (60/120)
200 (90/110)
180 (90/90)
200 (100/100)
200 (100/100)
shrink
%
76
75
77
75
71
71
0.525 (LP)
0.499 (GP)
53
50
>800
[>720]
>650
~2.0x
430
[380]
350
8
~2.0x
Technology migration 90nm(T201) Æ 65nm(T207)
(T207>>directly in 300 mm wafers)
substrate
lithography
STI
Gate dielectric
Gate electrode
Junction
RTA
Silicide
Strain
Contact
Low-k
Barrier
Interconnect
CMOS090
bulk
193nm
scale 120nm STI
furnace-nitrided oxide
1500A poly-Si
predope
offset spacer
+ implant
spike anneal
CoSi2
W CVD
BDI (keff~3.1)
PVD
Cu (6-9 ML)
CMOS065
bulk, rotated <100>
193nm (high-NA)
scale 90nm STI
plasma-nitrided oxide
1000A poly-Si
predope
a-C hard mask
no offset spacer
(co-)implants
aggressive spike
low thermal budget
NiSi
CESL-induced
W CVD
keff 2.7
PVD
Cu (6-9 ML)
9
1.E-03
1.E-04
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
-1.2
Drain current [µA/µm]
Drain current [A/µm]
Selected examples: GP Transistor
characteristics
1200
1000
1.2V
800
600
1V
W=1µm
0.8V
400
0.6V
200
-0.7
-0.2
0.3
Vgs [Volt]
0.8
0
-1.2 -0.9 -0.6 -0.3 0
Sub-Threshold regime
0.3 0.6 0.9 1.2
Vds [Volt]
Output characteristics
10
GP NMOS digital performance
-4
Vdd=1V
Log Ioff (A/µm)
-5
Vdd=1,2V
-6
-7
-8
1300
-9
810
500
700
990
900
1100
Ion (µA/µm)
1300
1500
11
Core LP transistor short channel control
0.6
NMOS
Vt sat [Volt]
0.4
0.2
Vds=1.2V
0
-0.2
-0.4
PMOS
-0.6
30
50
70
90
L silicon [µm]
12
LP-6transistor digital performance
NMOS
PMOS
-8
-9
-10
-11
300
710
-12
Ion [µA/µm]
13
10
00
0
90
80
0
70
0
60
0
50
0
40
0
30
0
20
0
10
0
-13
0
Ioff [A/µm]
-7
100
90
80
70
60
50
40
30
20
10
0
Cumulative plot [%]
Cumulative plot [%]
Selected examples: MLM electrical
characteristics
12M Vias
yield
0
1
2
3
4
5
6
7
8
100
90
80
70
60
50
40
30
20
10
0
M1
-11
-10
-9
-8
-7
Leakage [Log A]
Rsq [Ohm/via]
M2
105nm
V1
M1
6 metal levels
ULK
14
-6
-5
0.5µm² SRAM bit-cell
SRAM after NiSi process step
Internal
node
Shared contact
Word line (Copper)
NiSi
45nm
45nm
NiSi
NiSi
Pull Up transistor
15
0.5µm² SRAM bit-cell Static Noise Margin
1.4
SNM=240mV
300
SNM (mV)
1.2
VR, Vin (V)
1.0
0.8
250
200
150
100
0.7
0.6
0.9
1.1
1.3
Vdd (V)
0.4
0.2
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vin, VL (V)
16
1.4
T 207 CMOS 65 nm statuts: October 2005
Process freeze achieved
Significant yield improvements in FEOL and BEOL
Reliability meeting the specifications
The process is open for prototyping customers chips
Risky production is expected from Q1 06
The Crolles 2 partners will be sharing their 65nm cell
libraries and IP blocks. They are confident about the
success of its 65nm process after getting all its 90nm
designs in the last twelve months right first time
17
EC NANOCMOS 45 nm
Achieve a first “demonstration of feasibility” of a 45 nm CMOS logic process
based on a selection of the most appropriate technology
among several options
Bulk
SOI
SON
DG
Strain
DevicePerformance
Performance
•• Device
Devicesuitability
suitabilityto
tolow
lowcost
costprocess
process
••Device
Devicesuitability
suitabilityto
tolow
lowpower
power
••Device
Feasibilityin
in300mm
300mmfab
fab
••Feasibility
Timing
••Timing
Competitor/literaturetrend
trend
••Competitor/literature
SRAM
SRAM
Feasibility
Feasibility
Demonstration
Demonstration
Transfertto
toaa
Transfert
MEDEA+Project
Project
MEDEA+
HK
Metal
Gate
R§D activities for 32 nm nodes in cooperation
with the network of academic teams SINANO
18
45nm BULK

General Purpose applications (L=30nm, Tox=1.1nm, Vdd=1V)
Low Power applications (L=45nm, Tox=1.7nm, Vdd=1.2V)
Conventional Gate stack Poly-Silicon Gate on SiON
Strained Si as Technological Booster:
– Low-cost Strained Liners (CESL,SMT), Rotated Channels
-6
Tensile CESL
NiSi
30nm
50nm
30nm
Log(Ioff) (A/µm)

GP nMOS device
Vdd=1V
std CESL
-7
tensile CESL
-8
+20%
SMT Layer
(100) Channel
-9
0.8
0.9
1
1.1 1.2 1.3
normalized Ion
19
1.4
1.5
NANOCMOS first functional bulk based SRAM
simulation
1000
190mV
PG
800
Vout (mV)
0.248µm²
30nm
600
400
200
Vdd=1. 0 V
0. 248µm²
800
0
0
PD
500
1000
Vin (m V)
PU
Shared
V dd
100nm
contact
Vout (mV)
600
400
200
Vdd=1.0 V
0
30nm
0
pM O S
50nm
Pull-up
pM O S
P ull-up
500
Vin (mV)
1000
Functional 0.25µm² SRAM-bit-cell in
BULK technology! June 2005
fabricated at Crolles in 300 mm
20
Alternative trigate option
Specific design,
all Optical
S=0.314µm²
VDD = 0.4 V-1.2 V
(0.2 V incre me nts )
Functional
0.314µm²
SRAM Cell !
fabricated at
IMEC. June
2005
1
in te r n a l n o d e 2 (V )
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
inte rna l node 1 (V)
21
2T 103 MEDEA+ FOREMOST Objectives

FOREMOST main goal : demonstration of a full CMOS 45
process technology in European 300 mm manufacturing
industrial facilities. Starts from NANOCMOS results.

The proposal targets both CMOS logic and DRAM/FLASH
process technologies . Promotes synergy between the
competences of Crolles 2 Alliance and Infineon in Dresden.

Demonstration of feasibility of a complex test vehicle
representative of 45 nm design rules( 3x more complex than
today most complex 90nm design in PHILIPS).

Project start January 2006.First validation is proposed for Q4
2007 in Crolles 2. Reliability data in Q2 /08.
22
PULLNANO 32 nm/22 nm
FinFET
LOP compatible
Devices Ioff ~ 1nA/µm –
10pA/µm
Planar : SOI or SON
major changes in
materials and
NiSi
architectures.
55nm
NiSi
channel
BOX
32 nm Target:0.14µm²
SRAM cell !!
Advanced R§D activities for the 22 nm node primarily done
three clusters of academic teams and institutes (19 academic
partners representing more than 35 laboratories)
23
NiSi
CONCLUSIONS

Several European Commission and MEDEA + projects contribute to
the development of nanometer CMOS generations. They place the
European IC industry at the top front of the technology
The 90 nm is in industrial production. The 65 nm starts product
prototyping. First choices for a 45 nm technology are available
MEDEA+ 2T103 will continue towards full process integration

R§D of 32 and the 22 nm generation is the objective of PULLNANO.
The project gathers an unprecedented number of academic teams

The Crolles2 Alliance organization triggers a tight collaboration
between a multitude of teams and experts. The achievements of
these projects are possible thanks to an excellent cooperation: IC
manufacturers, equipment suppliers, institutes, academic teams..
It is expected that cooperation between the European Commission
and National Public Authorities, MEDEA+ organization, .… would
allow to structure the appropriate support to continue with these
very successful chain of projects.
24
Acknowledgements

Danielle Thomas T207 and 2T 103 FOREMOST Project Leader
Peter Stolk T207 WP4 leader
The NANOCMOS Sub-Project Leaders
The PULLNANO Sub-Project Leaders
25
MEDEA+ Forum 2005
21-22 November
Barcelona
21/11/05. G.Bomchil. MEDEA+ Forum 2005. Barcelona
26

EUROPEAN “NANOMETRIC” CMOS PROJECTS

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