NRAM: High Performance, Highly Reliable Emerging Memory

NRAM: High Performance, Highly Reliable Emerging Memory

NRAM: High Performance, Highly
Reliable Emerging Memory
Sheyang Ning1,2, Tomoko Ogura Iwasaki1,
Darlene Viviani2, Henry Huang2,
Monte Manning2, Thomas Rueckes2,
Ken Takeuchi1
1Chuo
Flash Memory Summit 2016
Santa Clara, CA
University
2
Nantero Inc.
1
Outline
l Introduction of NRAM
l  Single NRAM cell and cell array measurement setup
l  NRAM characteristics
l  DC-IV curve
l  Set and reset program characteristics
l  Large on/off ratio
l  High temperature program
l  High endurance
l  Conclusion
Flash Memory Summit 2016
Santa Clara, CA
2
Introduction of NRAM
Performance
DRAM
NRAM
Nano-RAM, Carbon nanotube
based resistive memory
NAND flash
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3
Compare with Conventional Memories
= good
= bad
DRAM
Performance
Scalability
Endurance
Non-volatile
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NAND flash NRAM
20 ns pulse [1]
Single cell 15 nm
[2]
Single cell 1012
[3]
1000 years@ 85ºC
[2]
[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
[2]. Nantero Presentation for ITRS ERD/ERM, International Technology Roadmap for
Semiconductors (ITRS), 2013.
[3]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. 4
Compare with Emerging Memories
ReRAM [1]
Material
Resistive
switching on
read
AlxOy
Filament
size
PRAM [2]
NRAM [3]
Carbon
Ge2Sb2Te5 nanotube (CNT)
Tunneling
Phase
current
change
between CNTs
Endurance
108
109
1012
Current
High
High
Low
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[1]. S. Ning et al., Solid-State Electronics, vol. 103, pp. 64–72, Jan., 2015.
[2]. H. Y. Cheng et al., IEEE Int. Electron Devices Meeting, 2013, pp. 30.6.1–30.6.4.
[3]. S. Ning et al., Symp. on VLSI Tech., 2014, pp. 96–97.
[4]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199. 5
Physical Mechanism
R cell≈800 kΩ
Small distance
R cell ≈1 GΩ
Large distance
Flash Memory Summit 2016
Santa Clara, CA
[1]. S. Ning et al., in VLSI Symp. Tech. Dig., Jun. 2014, pp. 120–121.
[2]. Nantero presentation, Int. Tech. Roadmap for Semiconductors (ITRS), 2013.
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Physical Mechanism
Set: attraction force
Reset: repulsive force
+
Electrical
induction
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−
Heat caused
phonon vibration
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
7
Outline
l  Introduction of NRAM
l Single NRAM cell and cell array measurement
setup
l  NRAM characteristics
l  DC-IV curve
l  Set and reset program characteristics
l  Large on/off ratio
l  High temperature program
l  High endurance
l  Conclusion
Flash Memory Summit 2016
Santa Clara, CA
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Single NRAM Cell and Cell Array Test
140 nm NRAM single cell
116 nm, 4 Mbits NRAM cell array
Vd
BL0
NRAM
cell
SL0
WL
BLN
……
SLN
NRAM cell
Vg
Oscilloscope
Flash Memory Summit 2016
Santa Clara, CA
NRAM testchip
BL
SL
Set voltage
+VSet
0V
Reset voltage
0V
+VReset
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
[2]. G. Rosendale et al., Proceedings of the European Solid-State Circuits Research Conference
(ESSCIRC), Sept. 2010, pp. 478–481.
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Outline
l  Introduction of NRAM
l  Single NRAM cell and cell array measurement setup
l NRAM characteristics
l DC-IV curve
l Set and reset program characteristics
l Large on/off ratio
l High temperature program
l High endurance
l  Conclusion
Flash Memory Summit 2016
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DC-IV Curve
Single cell bi-polar program
Current vibration due to long
term voltage stress on CNTs
100
1
10−1
10−2
Set
Butterfly
curve
10−3
10−4
Reset
-3 -2 -1 0 1 2 3
Vd (V)
Flash Memory Summit 2016
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Id (µA)
Id (µA)
10
15
10
5
0
Same cell, reset curve
Trigger
voltage
0
1
2
Vd (V)
[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
3
11
Low Program Current
10−6
Reset
100 µA
30 µA
5 µA
10−8
Set
Reset
Set
10−10
10−12
Voltage
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20
0
-20
-40
0.57pJ
0
40
50 100 150
Time (ns)
0.72pJ
20
0
-20
0
50 100 150
Time (ns)
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
[2]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
Voltage (V)
Current (A)
10−4
Current (µA)
10−2
Current (µA)
Single cell AC Ipeak < 20 µA
Voltage (V)
Single cell DC Icompliance = 5 µA,
30 µA, and 100 µA
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l  Cell array measurement,
Reset is driven by both
voltage and current
BL = 0 V
SL=Vprogram
WL= Vgate
ResetBER(a.u.)
Reset Characteristic
2
WL=0.4 a.u.,
SL from 0 to 1 a.u.
1
0
0.6
0.8
1
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0.8
0.6
0.4
[1]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
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Set and Reset Voltages
l  Three randomly chosen NRAM cells
Resetvoltage
Setvoltage(absolutevalue)
0.81
0.8
0.6
0.6
0.4
0.4
0.2
106 107 108 109 101010111012
Write cycles
106 107 108 109 101010111012
Write cycles
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100%
80%
60%
cell 1
cell 2
cell 3
40%
20%
0%
Reset voltage (V)
Set
Cumulative program success
1
Reset
Cumulative program success
Program voltages (a.u.)
Program voltages (a.u.)
l  Use incremental pulse
programing on single cell
100%
80%
cell 1
cell 2
cell 3
60%
40%
20%
0%
Set voltage (V)
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
14
Large On/Off Ratio
l  Single cell measurement
109
Resistance (Ω)
> 100 times on/off ratio
Possible for multi-level cell (MLC)
Read at 1 V
Resistance
≈ 1.3×107 Ω
108
107
106
105
≈ 105 Ω
104
0
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50 100 150 200
Read cycles
[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
15
High Temperature Program
25℃
85℃
125℃
Reset
0
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0.5
1
Reset voltage (a. u.)
Set failure rate (a.u., log scale)
Reset failure rate (a.u., log scale)
l  Single cell measurement, stable program voltage at different temperatures
25℃
85℃
125℃
Set
0
0.5
Set voltage (a.u.)
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
1
16
High Endurance
Single cell
Cell array
5
107
HRS ≥ 1.25MΩ
106
105
104
LRS ≤ 200kΩ
106
107
108
109
1010 10111012
Write cycles
Flash Memory Summit 2016
Santa Clara, CA
Program BER (a.u.)
Resistance (Ω)
108
4
Reset BER
Set BER
3
2
1
0
103 104 105 106 107 108
Write cycles
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
[2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
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High Endurance
l  Cell array does not wear-out after 108 write cycles
Reset BER after 103 write cycles
Reset BER after 108 write cycles
Reset voltage
1
1
Set BER after 103 write cycles
Set BER after 108 write cycles
Set voltage
0.9
0.6
0.8
0.4
0.7
0.2
0.6
0
0.5
1
Flash Memory Summit 2016
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3
4
Verify-set pulses
5
Reset BER (a.u.)
0.8
0.8
0.9
0.6
0.8
0.4
0.2
0.7
0
0.6
1
2
3
4
Verify-reset pulses
5
[1]. S. Ning et al., Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 2016.
[2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
Reset SL voltage (a.u.)
1
Set BL voltage (a.u.)
Set BER (a.u.)
1
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Outline
l  Introduction of NRAM
l  Single NRAM cell and cell array measurement setup
l  NRAM characteristics
l  DC-IV curve
l  Set and reset program characteristics
l  Large on/off ratio
l  High temperature program
l  High endurance
l Conclusion
Flash Memory Summit 2016
Santa Clara, CA
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Conclusion
l  NRAM is an emerging nonvolatile memory cell which
has performance between DRAM and NAND flash.
l  Compared with other emerging nonvolatile memories,
NRAM has competitive characteristics, including,
lower program current, large on/off ratio, large
endurance, high temperature stability and long
retention time.
Flash Memory Summit 2016
Santa Clara, CA
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