ArcSim - HiPEAC`10 Poster

& Collaborative Systems
Institute for Computing
Systems Architecture
Centre for Intelligent Systems
& their Applications
Processor Automated Synthesis by iTerative Analysis Project
Laboratory for Foundations
of Computer Science
http://groups.inf.ed.ac.uk/pasta/
Institute of Perception,
Action and Behaviour
Ultra-Fast Functional Instruction Set Simulation
Institute for Adaptive
& Neural Computation
e-Science Institute
JIT Dynamic Binary Translation
HOTSPOT Detection
Large Translation Units
PC address
Basic Block Mode
SCC Mode
A
BB
A
SCC
A
B
BB
B
SCC
B
Simulation time is partitioned into epochs
Epoch is interval between two translations
Block
Translated
Yes
Call Translated Block
Function
BB
C
D
Frequently executed blocks are HOTSPOTS
No
HOTSPOTS are translated into native code
New Block
Yes
BB
C
BB
E
F
BB
F
G
BB
G
PAGE Mode
CFG Mode
CFG
C
D
E
Informatics Life-Sciences Institute
PAGE CFG
Flexible Faster Than Silicon
Instruction Set Simulator
D
E
F
LINEAR
Add Block to Worklist
G
No
JIT Dynamic Binary Translation
Interpretive Block
Simulation
JIT DBT Engine
1
Increment Block
Simulation Counter
Compute instruction side effects
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Map ARCompact code onto native code
Determine operand dependencies
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Full Virtual Simulation Platform
Faster than Silicon*
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Instruction Selection
1
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Yes
Emit native target instructions
No
Emit performance model updates
1
Dependency Analysis
End of Epoch
2
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Emit Target Instruction
Translate Blocks in
Worklist
Large Translation Units
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Simulation Modes
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Instruction Set Extension API
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2
Emit Performance Model
Update
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Verified Cycle-Accurate Simulation
Larger blocks result in improved locality
More scope for JIT compiler optimisations
Features and APIs
Update Translated
Block Map
High-Speed JIT DBT Simulation
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Compile and Load
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Powerful plugin API for implementing instruction set extensions. ISE plugins are
as powerful as baseline instructions and integrate into cycle-accurate and highspeed JIT DBT simulation modes.
Memory Mapped IO API
Simple yet very powerful API for implementing user defined memory mapped IO
devices such as sound, screen, ethernet...
Co-Simulation for HW Verification
@ 350MHz using 90nm
System Call Emulation
Emulation implementations for Linux system calls as well as support for
redirection of stdin, stdout, and stderr are provided and enable the standalone
simulation of binaries without an operating system.
Detailed Profiling Simulation Mode
Ultra-Fast Cycle Accurate Instruction Set Simulation
FETCH
DECODE
MEMORY
EXECUTE
Next Fetch
PC
PC
....
0x00000848:
[0x00000848] ext
[0x0000084c] xor
[0x00000850] and
r2,r9
r3,r12,r2
r3,r3,0xf
[0x00000854] asl
r3,r3,0x3
[0x00000858] and
r2,r2,0x7
[0x0000085c] or
r3,r3,r2
[0x00000860] asl
r4,r3,0x8
[0x00000864] brcc.d
[0x00000868] or
....
r10,r13,0x2c
r4,r4,r3
extern CpuState cpu;
// global processor state
1
void BLK_0x00000848(void) {
cpu.r[2] = (uint16_t)(cpu.r[9]);
pipeline(0,cpu.avail[9],&(cpu.avail[2]),0x00000848,1,0);
2
cpu.r[3] = cpu.r[12] ^ cpu.r[2];
pipeline(cpu.avail[12],cpu.avail[2],&(cpu.avail[3]),0x0000084c,1,0);
cpu.r[3] = cpu.r[3] & (uint32_t)15;
pipeline(cpu.avail[3],0,&(cpu.avail[3]),0x00000850,1,0);
cpu.r[3] = cpu.r[3] << ((sint8_t)3 & 0x1f);
pipeline(cpu.avail[3],0,&(cpu.avail[3]),0x00000854,1,0);
cpu.r[2] = cpu.r[2] & (uint32_t)7;
pipeline(cpu.avail[2],0,&(cpu.avail[2]),0x00000858,1,0);
cpu.r[3] = cpu.r[3] | cpu.r[2];
pipeline(cpu.avail[3],cpu.avail[2],&(cpu.avail[3]),0x0000085c,1,0); 3
cpu.r[4] = cpu.r[3] << ((sint8_t)8 & 0x1f);
pipeline(cpu.avail[3],0,&(cpu.avail[4]),0x00000860,1,0);
// compare and branch instruction with delay slot
pipeline(cpu.avail[10],cpu.avail[13],&(ignore),0x00000864,1,0);
if (cpu.r[10] >= cpu.r[13]) {
cpu.pl[FE] = cpu.pl[ME] - 1; // branch penalty
4
fetch(0x0000086c);
// speculative fetch due to branch pred.
cpu.auxr[BTA] = 0x00000890; // set BTA register
cpu.D = 1;
// set delay slot bit
} else {
5
cpu.pc = 0x0000086c;
}
cpu.r[4] = cpu.r[4] | cpu.r[3];// delay slot instruction
pipeline(cpu.avail[4],cpu.avail[3],&(cpu.avail[4]),0x00000868,1,0);
if (cpu.D) {
// branch was taken
cpu.D = 0;
// clear delay slot bit
cpu.pc = cpu.auxr[BTA];
// set PC
}
cpu.cycles = cpu.pl[WB];
// set total cycle count at end of block
return;
}
Data Structures
ZOL
Logic
Instruction Cache
Tags
// pipeline stages
typedef enum {
FE,
// fetch
DE,
// decode
EX,
// execute
ME,
// memory
WB,
// write back
STAGES // 5 stages
} Stage;
// processor state
typedef struct {
uint32_t pc;
6
// general purpose registers
uint32_t r[REGS];
// auxiliary registers
uint32_t auxr[AUXREGS];
// status flags (H...halt bit)
char
L,Z,N,C,V,U,D,H;
// per stage cycle count
7
uint64_t pl[STAGES];
// per register cycle count
uint64_t avail[REGS];
// total cycle count
uint64_t cycles;
// used when insn. does not
// produce result
uint64_t ignore;
} CpuState;
Interactive debugging interface supporting single step tracing of instructions,
debugging of processor state, setting of breakpoints...
PC
Inst
Data
Q
PC
Inst
Decode
Logic
r0
Align
Logic
B
PC
Register
File
Hit &
Select
Logic
WRITEBACK
BRcc/BBIT Target
Logic
Bcc/Jcc Target
Logic
JIT Translated Block with Performance Model
Debugging and Tracing
ENCORE 5-Stage Pipeline Hardware Model
JIT Performance Model Translation
Block of ARCompact™ Instructions
Profiling simulation mode is orthogonal to the above modes and provides
detailed statistics about various simulation aspects such as dynamic instruction
frequencies, per-instruction latency distributions, detailed cache-statistics,
branch predictor statistics, detailed register usage statistics...
ALU
Bypass
Logic
Limm
PC
ABS
MIN
MAX
SELECT
Select
Result
Bypass
Logic
Data
Cache
Input
Select
&
Control
Logic
Exception
&
Replay
Logic
Data Cache
Tags
Data
Instruction Set Simulator
Hit &
Select
Logic
void pipeline(uint64_t opd1, uint64_t opd2, uint64_t* dst1, uint64_t* dst2, uint32_t faddr, uint32_t xc, uint32_t mc) {
cpu.pl[FE] += fetch(faddr);
// FETCH
- account for instruction fetch latency
if (cpu.pl[FE] < cpu.pl[DE]) cpu.pl[FE] = cpu.pl[DE]; // INVARIANT - resolves structural hazard
cpu.pl[DE] = max3((cpu.pl[FE] + 1), opd1, opd2);
// DECODE
- determine operand availability time
if (cpu.pl[DE] < cpu.pl[EX]) cpu.pl[DE] = cpu.pl[EX]; //
cpu.pl[EX] = *dst1 = cpu.pl[DE] + xc;
// EXECUTE
- account for execution latency and destination
if (cpu.pl[EX] < cpu.pl[ME]) cpu.pl[EX] = cpu.pl[ME]; //
availability time
cpu.pl[ME] = *dst2 = cpu.pl[EX] + mc;
// MEMORY
- account for memory latency and destination
if (cpu.pl[ME] < cpu.pl[WB]) cpu.pl[ME] = cpu.pl[WB]; //
availability time
cpu.pl[WB] = cpu.pl[ME] + 1;
// WRITEBACK
}
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DATA MEMORY PIPELINE
ENCORE 5-Stage Pipeline JIT Generated Software Model
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Virtual Devices
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Novel Software
Pipeline Model
Structural
Dependencies
2
Operand
Dependency Timing
3
Side Effect
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4
5
UART
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High-Speed Performance Modeling
Key idea is to retain a high-speed instruction-by-instruction execution model and reconstruct microarchitectural
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pipeline state at instruction commit boundaries. In order to increase simulation speed we introduce an innovative
pipeline software model and perform JIT dynamic binary translation. JIT generated code is augmented with
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highly optimised JIT generated code for performance model updates.
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FPGA @ 50MHz
Instruction Set
Extensions