Atmel SAM3/SAM4 Flash MCU

Transcription

Atmel SAM3/SAM4
Flash MCU
Products Highlights
1
© 2012 Copyright Atmel Corporation
SAM3 Flash MCUs
Atmel Cortex-M3 Flash MCUs
2
Introduction
Cortex-M3 Implementation Options
3
Cortex-M
Core
MPU
ETM
ITM
JTAG / SWD
Bit-banding
SysTick Timer
SAM3U
Yes
No
Yes
Yes / Yes
Yes
Yes
SAM3S
Yes
No
Yes
Yes / Yes
Yes
Yes
SAM3N
No
No
Yes
Yes / Yes
Yes
Yes
SAM3X
Yes
No
Yes
Yes / Yes
Yes
Yes
SAM3A
Yes
No
Yes
Yes / Yes
Yes
Yes
4/22/2016
SAM3U Series
First Cortex-M3 Flash Microcontroller with
High-speed USB and Embedded PHY
4
SAM3U Series
Features
•
First Cortex-M3 Flash Microcontroller with High-speed USB & Embedded PHY
•
First Cortex-M3 MCU with Dual-bank Flash with Boot Bank Select
• Secure self-programming
•
High-speed Peripherals
• HS USB 2.0, SDIO/SDCard 2.0, MMC 4.3 and EBI
•
High-end 12-bit 1Msps Analog-to-Digital Converter
• On-chip Programmable Gain Amplifier and Differential Input support to reduce
external component count
•
Simplified PCB design through On-chip Termination Resistors
•
Advanced Safety and Security Functions
• Hardware security including external memory scrambling and unique 128-bit ID
5
SAM3U Series
Masters
Block Diagram
Slaves
User
Int.
JTAG
Boundary Scan
System Peripherals
JTAG ICE & SWD
16KB
16kB
8kB
ITM
PDC
PLL
PLLUTMI
3-20MHz
OSC
RC OSC
12/8/4MHz
UART
Cortex-M3
WDT
SRAM
LDO
TIC
NVIC
MPU
Unique
ID
32kB
16kB
8kB
ROM
256kB
128kB
64kB
IAP
4-ch
DMA
NAND
NOR
PSRAM
ECC
FIFO
DMA
4k SRAM
5-layer AHB Matrix
RTC
RTT
RSTC
RC OSC
32kHz
Supply
Contr
XTAL
32kHz
8 x GPBREG
Backup Unit
Peripheral DMA
Controller: 11 channels
Peripheral Bridge
POR
Peripheral Bridge
APB
PDC
12-bit
ADC
x8
PDC
10-bit
ADC
x8
PDC
PDC
PWM
x4
I/O
x96
16-bit
Timer
x3
PDC
USART USART
PDC
PDC
USART USART
User Peripherals
6
(8/16-bit)
FFPI
SAM-BA Boot
PMC
BOD
Flash
SMC
USB Device
High Speed
PIO A/B/C
EBI
SRAM
PDC
TWI
HSMCI
SPI
PDC
TWI
8-bit
SSC
16-bit
SAM3U Series
Integrated High Speed USB 2.0 PHY
•
Reduced BOM cost and board space
•
What Problem does it Solve?
• Removes the need for an external USB 2.0 HS PHY (Physical Interface) companion chip
• PCB area – and potentially overall product size - is reduced by removing need for additional
PHY IC, signal routing and support components
•
How Does it Work?
• Atmel’s integrated USB 2.0 HS PHY completes the signal path with minimal external
components
Atmel – Optimized Board Area
Competition – Larger Board Area
$ 0.5 - $1.00S
7
SAM3U Series
Dual Bank Flash w/Boot Bank Selection
•
Enables Safe and Secure Remote Update
•
What Problem does it solve?
• Provides a fail-safe method of upgrading firmware on remote networked systems
• Enables background firmware upgrade without halting application execution
• Prevents system corruption while upgrading the system software
RESET VECTOR
Bank 1
v1.0
Bank 2
v1.1
RESET VECTOR
Wired / Wireless Stream
Normal operation from Bank 1
while simultaneously remotely
programming Bank 2
8
Bank 1
v1.0
Bank 1
v1.0
Bank 2
corrupt
Bank 2
v1.1
RESET VECTOR
Power or comms failure cause Bank
2 program fail while Bank 1
continues to operate and requests
retransmission
Reprogramming successful,
device now executes from
Bank 2, Bank 1 available for
next update
SAM3U Series
Integrated Termination Resistors with Debounce
•
What Problem Does it solve?
Atmel SAM
Devices with ODT
• All system designs have to comply with EMI standards.
• GPIO switching will cause signal integrity issues that
generate EMI
• Voltage ringing, spike currents, simultaneous switching
noise, …
• On-die termination (ODT) improves signal integrity
without external components
• Reduce PCB size and BOM cost
•
How Does it work?
• 36 Ohms embedded termination resistors
• ODT more closely matches the impedance of the output
of the device to the PCB trace.
• This matching minimizes the reflection factor, resulting
in lower switching currents and reduced ringing (signal
overshoot and undershoot).
9
Data Logging
SAM3U Series
Integrated Termination Resistors with Debounce (cont.)
•
Competitors such as NXP, Freescale, and ST do not usually have
ODT.
•
SAM3/4 Flash MCUs therefore offer better signal integrity without
adding extra components
Ringing
Current Spike
SAM3
vs.
STM32
3
10
SAM3U Series
Safety & Security Features
11
•
Memory Protection Unit (MPU) to improve code protection and secure multi-tasks
execution.
•
Flash Controller
• 32 lockable regions of equal size preventing programming/erasing
• Security bit to lock device from Debug access
• 1-bit ECC correction per 32-bit
•
Scrambled External bus interface to ensure SW confidentiality
•
Unique 128-bit serial number
•
Crystal Oscillator Failure Detection & Automatic Fallback to the Fast RC Oscillator
•
Peripherals Write Protected registers
SAM3U Series
External Bus Interface (EBI) Scrambler
•
Conceal external code and data reads and writes
•
What Problem does it Solve?
• External memory is relatively easy for attackers to read or alter.
• The EBI scrambler conceals data without penalizing performance.
•
How Does it Work?
• The External Bus Interface (EBI), including the NAND flash controller, may be set
to automatically scramble data to any selected external memory devices.
• There are no access penalties when reading or writing scrambled data.
12
SAM3U Series
Main Clock Failure Detector
•
Monitors the main crystal oscillator or ceramic resonator-based
oscillator to identify an eventual failure.
• No need for CPU intervention
•
Automatically switches the master clock source (MCK) on main
clock (MAINCK) with Fast RC as main clock source
• MCK = MAINCK = Fast RC
•
Puts PWM outputs in safe mode
• A clock failure detection activates a fault output connected to the PWM
• PWM can force its outputs and protect the driven device
13
SAM3S Series
Highly-integrated Cortex-M3
Flash MCUs
14
SAM3S Series
Features
•
Cortex-M3 processor running at up to 64MHz
•
High data rate serial communication
interfaces including
• USB 2.0 Device
• SDIO/SD/MMC
• 4 UARTs, 3 SPI, 2 I2C and I2S
•
Parallel IO Signal Capture
•
Simplified PCB design through On-chip
Termination Resistors
•
Fast RC Trimming Capability
•
• Including Hardware CRC with DMA to
guarantee memory integrity.
15
SAM3S Series
Masters
Block Diagram
Slaves
JTAG
Boundary Scan
Internal memories
System Peripherals
JTAG ICE & SWD
EBI
Lite
LDO
ITM
SMC
WDT
PLLA
Cortex-M3
XTAL
3-20 MHz
PLLB
TIC
RC OSC
NVIC
SRAM
Flash
64kB
48 kB
32 kB
16 kB
512kB
256kB
128kB
64kB
MPU
Unique
ID
IAP
NAND
FPGA
LCD
8 -bit
FFPI
AHB Matrix
RTC
RTT
RSTC
RC OSC
32kHz
Supply
Contr
XTAL
32kHz
Backup domain
DMA
Peripheral DMA
Peripheral Bridge
POR
16
(8-bit)
SAM-BA Boot
PMC
BOD
ROM
CRC
APB
PDC
16 ch
10-bit
12-bit
ADC
PDC
PDC
21 ch
Analog
12-bit
10-bit
Comp
DAC
PDC
4ch
PWM
16-bit
Timer
x6
PDC
PDC
PDC
PDC
Up to
79
I/Os
x2
UART
x2
USART
x2
TWI
DPRAM
2.5KB
FS USB
Dev
PDC
PDC
PDC
SPI
SSC
HSMCI
SAM3S Series
PIO Parallel Capture Mode
•
Easily connect external asynchronous devices such as CMOS sensors, high
speed parallel ADC…
•
Can be linked to a receiver PDC channel to transfer data without CPU
intervention
• Byte / Half-word / Word Transfer
• Up to MCK/4 Data Transfer Rate
PIO
Controller
PIODCCLK
PIODC[7:0]
PIODCEN1
Data
Status
PDC
PIODCEN2
•
17
Processor can execute other code or sleep while transfer takes place
SAM3S Series
PIO Parallel Capture Mode Example
SAM3S
JTAG ICE & SWD
SMC
ITM
(8-bit)
Cortex-M3
TIC
NVIC
SRAM
8-bit
Flash
MPU
4-layer AHB Matrix
Peripheral DMA
Controller
Peripheral Bridge
CMOS sensor
OV7740
APB
(OVT)
PDC
SDA
SCLK
TWI
PIXCLK
PIODCCLK
8
Frame Valid
Line Valid
18
PIO
PCKx
CLKIN
DOUT[7:0]
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
Programmable
Clock Controller
Prescaler
1/, /2, ./64
Clock
Generator
Slock Clock
Main Clock
PLLA Clock
PLLB Clock
PSRAM
SAM3S Series
In Application Fast RC Trimming
•
Possibility to compensate frequency drift due to derating factors such as temperature
and voltage by measuring and trimming on the fly the Fast RC frequency
•
Oscillator Calibration Register: PMC_OCR
SEL
CAL
0
Factory Trimmed default calibration value
1
•
(± 5% for 8/12MHz; ± 35% for 4MHz)
Trimming capability on operating oscillator frequency
• i.e. for example, when running on 8 MHz, it is possible to change the CAL8 value if SEL8 is set
in PMC_OCR.
19
User Calibration value (reset after each power up)
Frequency deviation vs. Trimming code in the Electricals (8/12MHz only)
SAM3S Series
20
•
execution.
•
Flash Controller
•
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
• CRC on Flash, SRAM and External Bus
• DMA support
•
•
•
•
SAM3S Series
SAM3S8/SD8 Added Features
21
•
Flash Memory Size is 512 kBytes
• Single Bank for SAM3S8
• Dual Bank for SAM3SD8 (w/o Bank Boot Selection)
•
SRAM Memory Size is 64 kBytes
•
ADC Automatic HW Calibration
•
RTC Accurate Clock Calibration
•
RTC Waveform Generation
•
64- and 100-pin package only (not 48-pin)
SAM3S Series
SAM3S8/SD8 ADC Automatic Hardware Calibration
•
Automatic Hardware Calibration Mode for Gain Errors
•
ADC Automatic Calibration must be done before setting ADC
settings such as gain, offset or ADVREF reference voltage
•
Calibration data is stored in the internal ADC memory
• Calibration data is then lost after a reset
22
SAM3S Series
SAM3S8/SD8 RTC Accurate Clock Calibration
•
Useful for an application where a very accurate RTC is required.
•
Crystal Error Sources
• Drift at room temperature (typically +/-20ppm)
• Temperature variations
•
RTC Trimming allows to:
• Measure in production @room T°,
•
23
the quartz deviation and compensate
it.
Compensate the T° deviation by
measuring the T° (using temperature
sensor)
SAM3S Series
SAM3S8/SD8 RTC Accurate Clock Calibration (cont.)
•
RTC Trimming is performed by Phase Step
•
Calibration circuitry acts by slightly modifying the 1 Hz clock period from
time to time
• By adding positive or negative correction in a range of 1.5ppm to 1950ppm.
•
Can obtain a crystal drift:
• below 1 ppm for a initial crystal drift between 1.5 ppm to 90 ppm
• below 2 ppm for a initial crystal drift between 90 ppm to 130 ppm
• below 5 ppm for a initial crystal drift between 130 ppm to 200 ppm
24
SAM3S Series
SAM3S8/SD8 RTC Waveform Generation
•
Avoid to wake-up the MCU from low power modes to drive the PIO
(Extra function) to generate periodic action like:
• blink a dot on a Segment LCD
• to activate periodically an external sensor
• a tamper function…
•
Up to 2 waveforms can be generated RTCOUT0 and RTCOUT1
• 7 possibilities driver sources
• independent source selection registers
25
SAM3N Series
Entry level and low cost SAM3
Cortex-M3 series
Pin-to-pin compatible with the
SAM3S series
26
SAM3N Series
Features
27
•
Entry level Cortex-M3 MCU running up to 48MHz
•
Memory densities from 16KB to 256kB Flash
•
No USB connectivity
•
No External Bus Interface
•
10-bit ADC/DAC
•
Pin to pin compatible with SAM3S
SAM3N Series
Masters
Block Diagram
Slaves
JTAG
Boundary Scan
System Peripherals
JTAG ICE & SWD
Internal memories
LDO
ITM
WDT
PLL
Cortex-M3
XTAL
3-20 MHz
TIC
RC OSC
NVIC
Unique
ID
SRAM
Flash
24 kB
16 kB
8 kB
8kB
4kB
256kB
128kB
64kB
32kB
16kB
FFPI
SAM-BA Boot
RTC
RTT
RSTC
RC OSC
32kHz
Supply
Contr
XTAL
32kHz
Backup domain
Peripheral DMA
Peripheral Bridge
POR
28
IAP
AHB Matrix
PMC
BOD
ROM
APB
PDC
PDC
16 ch
10-bit
ADC
1 ch
10-bit
DAC
PDC
4ch
PWM
16-bit
Timer
x6
PDC
PDC
PDC
PDC
PDC
Up to
79
I/Os
x2
UART
x2
USART
x2
TWI
SPI
SAM3N Series
SAM3S vs SAM3N Comparison Table
Features
SAM3S
SAM3N
Core
Cortex-M3 + MPU
Cortex-M3
Supply
Max Frequency
64MHz
48MHz
SRAM
Up to 64kB
Up to 24kB
FLASH
64kB to 512kB
16kB to 256kB
PDC
22
10
USB
FS Dev
No
HSMCI
Yes
No
SSC
Yes
No
Analog Comparator
Yes
No
PIO Capture Mode
Yes
No
ADC
15 x 12-bit (+Temp.)
16 x 10-bit
DAC
2 x 12-bit
1 x 10-bit
EBI
Yes (8-bit data)
-
Package (QFP, QFN, BGA)
29
1.62V to 3.6V
48, 64, 100
SAM3N Series
Form, Fit & Function Compatibility
•
Seamless Migration Path Between SAM7S, SAM3N, SAM3S Devices
• Atmel AT03786: SAM N/S Series Software Migration Guide
All Packages
SAM3S
SAM7S
64-pin
SAM3N*
* Except for USB device
30
SAM3X/A Series
Atmel Connectivity Cortex-M3 Series
31
SAM3X/A Series
Features
•
High Performance & Flash Density
• Up to 84MHz
• Dual Bank Flash and Dual SRAM
•
Rich Set of Connectivity Peripherals
• Ethernet MAC
• Built-in 128-bytes FIFO and Dedicated DMA
• USH USB Host & Device with on-chip transceivers
• Up to 480 Mbits/s, 4kB dual port RAM
• Dual CAN Controllers
• 8 mailboxes per controller
• High Speed SD/SDIO/MMC, I2S, SPI, I2C…
32
•
Analog
• 12-bit ADC & DAC
• Temperature Sensor
•
• Including True Random Number Generator
SAM3X/A Series
Masters
Block Diagram
Slaves
MII/
RMII
JTAG
Boundary Scan
UTMI
EBI
System Peripherals
JTAG ICE & SWD
SMC
64KB
32KB
16KB
(8/16-bit)
ITM
PLL
WDT
Cortex-M3
PLLUTMI
SRAM
12MHz
OSC
LDO
1.8V
RC OSC
Unique
ID
4/8/12MHz
TIC
32KB
32KB
16KB
NVIC
MPU
Dual
bank
Flash
ROM
IAP
512kB
256kB
128kB
6-ch
DMA
(8/16-bit)
SDRAM
ECC
SAM-BA Boot
FIFO
DMA
FIFO
DMA
6-layer AHB Matrix
RTC
RTT
Peripheral Bridge
POR
RSTC
RC OSC
32kHz
Supply
Contr
XTAL
32kHz
8 x GPBREG
Backup Unit
Peripheral DMA
Contoller: 17 channels
Peripheral Bridge
APB
PDC
PDC
12-bit
DAC
12-bit
ADC
x16
Temp.
Sensor
33
8/16-bit
NAND
FFPI
PMC
BOD
USB OTG
High Speed
PIO A/B/C/D/E
Ethernet MAC
SRAM
PDC
DMA
PWM
x8
PDC
PDC
PDC
PDC
32-bit UART USART USART
I/O
Timer
PDC
PDC
x160
x9
USART USART
TWI
CAN
PDC
TWI
User Peripherals
CAN
TRNG
DMA
DMA
HSMCI
SDIO
8-bit
2 ports
SPI
DMA
SPI
DMA
SSC
SAM3X/A Series
Connectivity Peripherals Features
•
One 10/100 Ethernet MAC Controller
•
•
•
•
•
High Speed USB 2.0 Host/Device
•
•
•
•
•
IEEE Standard 802.3 Compliant
MII/RMII Support
Dedicated DMA Master on Receive and Transmit Channels
Transmit and Receive 128 bytes FIFOs for buffering frame data
Supports High (480Mbps), Full (12Mbps) and Low (1.5Mbps)
4 kBytes of Embedded Dual-Port RAM
Dedicated DMA Master
On-Chip UTMI transceiver
CAN Controllers
• Fully Compliant with CAN 2.0 Part A and 2.0 Part B
• Bit Rates up to 1Mbit/s
• 8 Mailboxes per controller
34
SAM3X/A Series
35
•
execution.
•
Flash Controller
•
One True Random Number Generator (TRNG)
• passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites
•
•
•
•
SAM3X/A Series
SAM3X vs SAM3A Comparison Table
Pinout
SAM3X..C
SAM3A..C
144 pin
100 pin
100 pin
Frequency
Up to 84 MHz
Flash/SRAM
Up to 512kB / Up to 96kB
EMAC


Mode(s)
RMII/MII
RMII
EBI
8/16bit

HSMCI/SDIO
8bit


4bit
CAN
2
TWI
2
SPI
1 (+4 from USART)
1 (+3 from USART)
1 (+3 from USART)
PWM channels
8
4
8
U(S)ART
3USART / 2UART
3USART / 1UART
SSC

DAC channels
2
ADC channels
15 + internal Temp Sensor
Timers
9 + Systic + PWM + RTT
I/O
36
SAM3X..E
111
70
SAM3 Flash MCUs
SAM3 Features Differentiators
37
SAM3 Flash MCUs
Memory & System
SAM3N
SAM3S
Supply
38
SAM3U
SAM3A
SAM3X
1.62V-3.6V
MPU
-
√
√
√
√
Max Frequency
48 MHz
64 MHz
96 MHz
84 MHz
84 MHz
FLASH
Up to 64kB
Up to 512kB
Up to 512kB
Up to 512kB
Up to 512kB
SRAM
Up to 24kB
Up to 64kB
Up to 48kB
Up to 96kB
Up to 96kB
Dual Bank Flash
-
√
√
√
√
Bank Boot Selection
-
-
√
√
√
External Bus Interface
-
8-bit
8/16bit
-
8/16bit
Peripheral DMA(PDC)
√
Temperature Range
-40/85°C
SAM3 Flash MCUs
39
Peripherals
SAM3N
SAM3S
SAM3U
SAM3A
SAM3X
HS USB Device (w/ PHY)
-
-
√
√
√
HS USB Host (w/ PHY)
-
-
-
√
√
CAN
-
-
-
√
√
True RNG
-
-
-
√
√
Ethernet
-
-
-
-
√
PIO Parallel Capture
-
√
-
-
-
CRC Unit
-
√
-
-
-
SAM3 Flash MCUs
Embedded Features
40
SAM3N
SAM3S
SAM3U
Flash
1bit ECC/Lock bits/Security bit
√
PMC Clock Failure Detector
√
I/O On-Die Termination
√
SAM3A
SAM3X
Fast RC Trimming
√
√
-
√
√
EBI Scrambling
-
√
√
-
√
32-bit Timers
-
-
-
√
√
RTC Trimming
-
√
-
-
-
RTC Waveform Generation
-
√
-
-
-
ADC HW Gain Calibration
-
√
-
-
-
SAM4 Flash MCUs
Atmel Cortex-M4 Flash MCUs
41
Introduction
Cortex-M4 Implementation Options
42
Cortex-M
Core
MPU
FPU
ETM
ITM
JTAG / SWD
Bit-banding
SysTick
Timer
SAM4S
Yes
No
No
Yes
Yes / Yes
Yes
Yes
SAM4N
Yes
No
No
Yes
Yes / Yes
Yes
Yes
SAM4E
Yes
Yes
No
Yes
Yes / Yes
Yes
Yes
SAM4L
Yes
No
No
Yes
Yes / Yes
No
Yes
4/22/2016
SAM4S Series
Scalable Performance and Memory
Density, Power Efficiency and High Level
of Integration
43
SAM4S Series
Features
•
High Performance
•
•
•
•
•
Cortex-M4 processor running up to 120MHz
Up to 2MB of Flash and 160kB of SRAM
2 kB of Cache for SAM4SA/SD
Real Time Event Manager
Very Low Power consumption
• 180 µA/MHz in Active Mode
• 14.9 µA in Wait Mode
• 800 nA in Backup Mode
•
High data rate serial communication interfaces
• Full Speed USB Device, SDIO/SD/MMC, 4 UARTs, 3 SPI, 2 I2C and I2S
• Parallel IO Capture for CMOS Imagers
•
• Including EBI scrambling, HW CRC with DMA, Anti-tamper pins…
•
44
SAM7S/SAM3S/SAM3N/SAM4N pin-to-pin compatibility
SAM4S Series
SAM4S Series Comparison Table
45
SAM4S
SAM4SA
SAM4SD
Core
Cortex-M4
Cortex-M4
Cortex-M4
Frequency
120MHz
120MHz
120MHz
Cache
-
2kB
2kB
Flash
128KB-1MB
Single Bank
1MB
Single Bank
1MB-2MB
Dual Bank
SRAM
64kB-128kB
160kB
160kB
Package
Options
48, 64, 100
QFN, QFP, BGA,
VFBGA, WLCSP
64, 100
QFN, QFP, BGA,
VFBGA
64, 100
QFN, QFP, BGA,
VFBGA
SAM4S Series
Masters
SAM4S Block Diagram
Slaves
Package
General Purpose
LQFP/QFN48 (*)
LQFP/QFN64
LQFP/TFBGA100
VFBGA100
WLCSP64
180µA/MHz
~20µA - Full SRAM
1µA - Backup
CMOS int.
* Only SAM4S4/2
Debug
JTAG/SW
System Peripheral
Internal memories
Unique ID
4/8/12 MHz
RC OSC
LDO
WDT
Cortex-M4
120 MHz
3-20MHz
Xtal OSC
PLLA
SRAM
128KB
128KB
64KB
64KB
MPU
PLLB
I/D
Flash
1MB
512KB
256KB
128KB
System
USB
FS
Device
ROM
IAP
FFPI
SAM-BA
DMA
EBI
Lite
SMC
NAND
FPGA
LCD
8 -bit
PMC
Back-up Domain
Multi-layer High Speed Bus Matrix
RTC
8 Backup
registers
RTT
POR/BOD
Supply Cont.
PDC
UART
x2
32 KHz
RC/Xtal
PDC
USART
x2
PDC
SPI
x1
Peripherals
Bridge
PDC
PDC
TWI
x2
HSMCI
x1
DMA
Peripheral DMA
Controller
PDC
PDC
PDC
PDC
GPIO
x79
Timer
16bit
6 ch
ADC
12bit
16 ch
DAC
12bit
2 ch
CRC
PDC
46
PDC
Analog Parallel
I/O
Comp.
Cont.
x1
PDC
PDC
PWM
x4
SSC
x1
SAM4S Series
Masters
SAM4SA Block Diagram
Slaves
Debug
JTAG/SW
System Peripheral
Package
General Purpose
LQFP/QFN64
LQFP/TFBGA100
VFBGA100
180µA/MHz
~20µA - Full SRAM
1µA - Backup
CMOS int.
Cache
Internal memories
Unique ID
4/8/12 MHz
RC OSC
LDO
WDT
Cortex-M4
120 MHz
3-20MHz
Xtal OSC
PLLA
SRAM
160KB
Flash
1MB
IAP
MPU
PLLB
I/D
USB
FS
Device
ROM
FFPI
System
2KB Cache
SAM-BA
DMA
EBI
Lite
SMC
NAND
FPGA
LCD
8 -bit
PMC
Back-up Domain
RTC
8 Backup
registers
RTT
POR/BOD
Supply Cont.
PDC
UART
x2
32 KHz
RC/Xtal
PDC
USART
x2
PDC
SPI
x1
Peripherals
Bridge
PDC
PDC
TWI
x2
HSMCI
x1
DMA
Peripheral DMA
Controller
PDC
PDC
PDC
PDC
GPIO
x79
Timer
16bit
6 ch
ADC
12bit
16 ch
DAC
12bit
2 ch
CRC
PDC
47
PDC
Analog Parallel
I/O
Comp.
Cont.
x1
PDC
PDC
PWM
x4
SSC
x1
SAM4S Series
Masters
SAM4SD Block Diagram
Slaves
Debug
JTAG/SW
System Peripheral
Package
General Purpose
LQFP/QFN64
LQFP/TFBGA100
VFBGA100
180µA/MHz
~20µA - Full SRAM
1µA - Backup
CMOS int.
Cache
Dual Bank Flash
Internal memories
Unique ID
4/8/12 MHz
RC OSC
LDO
WDT
Cortex-M4
120 MHz
3-20MHz
Xtal OSC
PLLA
SRAM
160KB
MPU
PLLB
I/D
Flash
1MB
512KB
Flash
1MB
512KB
USB
FS
Device
ROM
IAP
FFPI
System
SAM-BA
2KB Cache
DMA
EBI
Lite
SMC
NAND
FPGA
LCD
8 -bit
PMC
Back-up Domain
RTC
8 Backup
registers
RTT
POR/BOD
Supply Cont.
PDC
UART
x2
32 KHz
RC/Xtal
PDC
USART
x2
PDC
SPI
x1
Peripherals
Bridge
PDC
PDC
TWI
x2
HSMCI
x1
DMA
Peripheral DMA
Controller
PDC
PDC
PDC
PDC
GPIO
x79
Timer
16bit
6 ch
ADC
12bit
16 ch
DAC
12bit
2 ch
CRC
PDC
48
PDC
Analog Parallel
I/O
Comp.
Cont.
x1
PDC
PDC
PWM
x4
SSC
x1
SAM4S Series
More Memory Flash Density & Features
•
Boot Bank Selection capability for SAM4SD16/32
•
2kB Cache Memory (SAM4SA and SAM4SD)
• Compensate wait state penalty at high frequency:
WS@Core Frequency
Coremark IAR 6.50
(-O High->Speed)
0WS@21MHz
3.38 Coremark/Mhz
5WS@123MHz (without cache)
2.03 Coremark/Mhz
5WS@123MHz (with cache)
3.32 Coremark/Mhz
• Reduce power consumption:
49
WS@Core Frequency
Iin (mA)
Icore (mA)
21MHz (without cache)
7.6
9.3
21MHz (with cache)
4.2
6
123MHz (without cache)
21.5
24.1
123MHz (with cache)
18.5
20.6
SAM4S Series
SAM4SA/SD Cache System Architecture
•
Zero Wait State access at full speed
Cortex-M4
•
•
Cache system is managed by the
Enhanced Embedded Flash Controller
(EEFC)
I bus
D bus
Mux
I/D
bus
The cache system embeds:
• 2 kB of 4-way consecutive cache
• Monitor system
S bus
Cache
I/D
bus
• 32-bit monitor counter
AHB Matrix
•
50
The monitor allows to evaluate the
usage of cache system in the
application .
I/D bus
ROM
I/D bus
FLASH
S bus
SRAM
SAM4S Series
Extended Supply Range & Low Power Modes (SAM4S4/2 case)
•
Operates from 1.62V to 3.6V extended supply range.
• True 1.8V±10% operation (no Analog, no USB)
Wake-up
w/ Flash in standby
< 10µs
ACTIVE Mode
Application Dependant
140µA/MHz
µs to ms range
(VDDCORE = 1.2V @25°C)
(depends on MCK frequency)
Wake-up
WAIT Mode
w/ Flash in deep power down
(w/ RTC, RTT, SRAM)
24.1µA
< 1ms
SLEEP Mode
BACKUP Mode
(w/ RTC, RTT)
800nA
(VDDIO = 1.8V @25°C)
51
6.9mA @120MHz
SAM4S Series
Real Time Event Management Overview
•
Inter-peripheral communication
• Events generated by peripherals (Event Generators) are directly routed
to other peripherals (Event Managers)
ADC
Real Time
Manager
Fault
Output
Fault
Input
PWM
•
Latency free event handling without CPU intervention
•
Only One Manager can be connected to one Generator at the same
time
•
Peripherals need to have their clock enabled
• Not usable in WAIT and BACKUP low power modes
52
PWM outputs
in safe state
SAM4S Series
Real Time Event Generators and Managers
Event Generators
Event Managers
53
PMC Clock
Failure
Management
ADC
Trig
Conversion
Timer
Trig
Capture
Parallel IO
Capture
DAC
Trig
Conversion
PWM
Fault
Inputs
Input pins
-
X
X
X
X
X
TC Output
-
X
-
-
X
X
Analog
Comparator
-
-
-
-
-
X
PWM Event Line
-
X
-
-
X
ADC
-
-
-
-
-
X
PMC Event
X
-
-
-
-
X
SAM4S Series
Analog and Communication Links
•
USB – FS Device (12Mbit/s)
•
•
•
•
HSMCI
•
•
•
•
•
12-bit – 1Msps
DMA support
DAC / 1-ch
•
•
CLK
MOSI
MISO
/CS
•
12-bit
DMA support
SPI
•
•
•
•
SCK
WS
SD
•
•
•
•
•
I2S Digital Audio devices support
TDM Codec
DMA support
USART
Speed: 20Mbps
Asynchronous and Synchrounous
Modem, SPI, IrDA, RS485, ISO7816
DMA support
UART
•
54
Master, Multi-Master, Slave Mode
400 Kbps
DMA support
SSC
•
•
•
•
Analog Comparator
Speed : 33Mbps
Master/Slave with 4 Chip Select
DMA support
I2C
•
•
•
SD V2.0, SDIO V2.0, MMC 4.3
4-bit data
DMA support
ADC / 16-ch
•
•
•
Up to 8 endpoints
Embedded Dual-port RAM
On-chip transceiver
•
TXD / RXD
SAM4S Series
•
Memory Protection Unit (MPU) to improve code protection and secure multi-tasks execution.
•
Flash Controller
•
•
•
•
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
•
•
55
256 lockable regions of equal size preventing programming/erasing
Security bit to lock device from Debug access
1-bit ECC correction per 32-bit
CRC on Flash, SRAM and External Bus
DMA support
•
•
•
•
Low-power Tamper Detection on two Inputs
•
Anti-Tampering by clear of the first half of General Purpose Backup Registers
•
SAM4S Series
Low-power Tamper Detection and Anti-Tampering
56
•
WKUP0 / WKUP1 generic wake-up pins can be used as Anti-Tamper pins
• Can be used in all power modes to wake up the system upon Tamper Detection
•
Upon detection through a tamper switch, asynchronous and immediate clear of the first
half of General-purpose Backup Registers can be performed
•
RTCOUT0 / RTCOUT1 pins can be used to intermittently power tamper sensor circuitry
• Limits power consumption if tamper sensor is biased through a resistor
• Waveform is generated using RTCOUTx whatever the power mode
SAM4S Series
SAM3S vs. SAM4S Comparison Table
Embedded Features
SAM3S
SAM4S
Core
ARM Cortex-M3
ARM Cortex-M4
Supply
58
1.62V-3.6V
Max Frequency
64MHz
120MHz
FLASH
Up to 512kB
Up to 2MB
SRAM
Up to 64kB
Up to 160kB
Dual Bank Flash
√
√
Bank Boot Selection
-
√
Cache
-
√
EBI Scrambling
√
Clock Failure Detector
√
On-Die Termination
√
Fast RC Trimming
√
RTC Trimming/Waveform
√
ADC HW Calibration
√
SAM4N Series
Entry Point to the Atmel ARM-based
Cortex-M4 Flash MCU Portfolio
59
SAM4N Series
Features
60
•
Entry point ARM-based Cortex-M4 Flash MCU
•
High Performance & Flash Density
•
Very Low Power Consumption
•
Analog
•
Large Number of Serial Communication Channels
•
Compatibility
• 100MHz ARM Cortex-M4
• Up to 100MHz
• Up to 1MB of Flash
• Real Time Event Manager
• 170µA/MHz
• 700nA Backup with RTC
• ADC 10-bit (510Ksps), 12-bit (24Ksps)
• 7 USARTs, 4 SPI, 3 I2C
• SAM7S/SAM3N/SAM3S/SAM4S pin-to-pin compatible
SAM4N Series
Masters
Block Diagram
Slaves
Package
General Purpose
LQFP/QFN48 (*)
LQFP/QFN64
LQFP/TFBGA100
VFBGA100
170µA/MHz
~20µA - Full SRAM
1µA - Backup
* Only SAM4N8
Debug
JTAG/SW
System Peripheral
Internal memories
Unique ID
4/8/12 MHz
RC OSC
LDO
WDT
Cortex-M4
100 MHz
3-20MHz
Xtal OSC
SRAM
80KB
64KB
MPU
PLL
I/D
Flash
1024KB
512KB
ROM
IAP
FFPI
System
SAM-BA
PMC
Back-up Domain
RTC
8 Backup
registers
RTT
POR/BOD
Supply Cont.
PDC
UART
x4
32 KHz
RC/Xtal
PDC
USART
x3
PDC
SPI
x1
Peripherals
Bridge
PDC
TWI
x3
Peripheral DMA
Controller
PDC
PDC
PDC
PDC
PDC
GPIO
x79
Timer
16bit
6 ch
ADC
12bit
16 ch
DAC
10bit
1 ch
PWM
x4
61
SAM4N Series
SAM4N Series vs. SAM3S/SAM4S Series Comparison Table
SAM3N
SAM4N
SAM4S
ARM Cortex-M3
ARM Cortex-M4
ARM Cortex-M4
48MHz
100MHz
120MHz
Flash
16KB-256KB
Single bank
No
512KB/1MB
Single bank
No
512KB/1MB/2MB
Single/Dual bank
Cache
SRAM
Up to 24KB
Up to 80KB
Up to 160KB
10-bit (380Ksps)
10-bit (510Ksps)
(12-bit (24Ksps) w/
averaging)
12-bit (1Msps)
10-bit / 1-ch
10-bit / 1-ch
12-bit / 2-ch
UART:4
SPI: 1 + 2 USART
I2C: 2
No
No
No
UART:7
SPI: 1 + 3 USART
I2C: 3
No
No
No
UART:4
SPI: 1+ 2 USART
I2C: 2
USB Device
I2S
HSMCI/SDIO
Ext. Bus Interface
No
No
Yes
Parallel capture (CMOS int.)
No
No
Yes
48, 64, 100
QFN, QFP, BGA
48, 64, 100
QFN, QFP, BGA,
VFBGA
64, 100
QFN, QFP, BGA,
VFBGA, WLCSP
Core
Frequency
ADC
(16-ch)
DAC
Communication
Package options
62
3/18/2013
SAM4N Series
Pin to pin compatibility
•
Seamless migration path between SAM7S, SAM3N, SAM3S, SAM4S,
SAM4N
• Atmel AT03786: SAM N/S Series Software Migration Guide
All Packages
Form, Fit & Function Compatibility
SAM3S
SAM4S
SAM3N*
SAM4N*
SAM7S
64-pin
* Except for USB device
63
SAM4N Series
Event Generators
Event Managers
65
PMC Clock Failure
Management
ADC
Trig Conversion
DAC
Trig Conversion
Input pins
-
X
X
TC Output
-
X
X
PMC Event
X
-
-
SAM4N Series
Atmel ARM-based Cortex-M3/4 General-Purpose Family
Atmel SAM3N:
• CM3 @ 48MHz
• 10-bit ADC
Atmel SAM3S Adds:
• CM3 @ 64MHz
• 12-bit ADC
• USB Full-Speed Device
• Dual Bank
Atmel SAM4S/SA/SD Adds:
• CM4 @ 120MHz
• 2KB of Cache
66
Atmel SAM4N Adds:
• CM4 @ 100MHz
• 12-bit ADC (w/ averaging)
• More serial comms.
SAM4E Series
Atmel ARM® Cortex™-M4
Processor-based Connectivity
Family
67
SAM4E Series
Features
•
High Performance
•
•
•
•
•
120 MHz Cortex-M4F (FPU)
Dual HS bridge architecture
2kB cache on Flash
Connectivity
• Ethernet with IEEE 1588 support
• Dual CAN ports
•
Advanced Analog
• Two Analog Front End (AFE)
• ADC with 16-bit enhanced mode @ 4Ksps
• Offset error correction
• Gain error correction
•
Safety and Security
• Dual Watchdogs
• AES, EBI scrambling, Flash Lock bits, Security bit, Anti-tamper pins…
68
SAM4E Series
Masters
Block Diagram
Slaves
Debug
JTAG/SW
System Peripheral
Package
Connectivity
LQFP/TFBGA100
LQFP/LFBGA144
170µA/MHz
~40µA - Full SRAM
1µA - Backup
Dual ADC
Analog Front End
Cache
CMOS int.
FPU
Internal memories
Unique ID
4/8/12 MHz
RC OSC
LDO
WDT
Cortex-M4
120 MHz
3-20MHz
Xtal OSC
RSWDT
PLL
SRAM
128KB
128KB
MPU
FPU
I/D
System
Flash
1MB
512KB
ROM
IAP
DMA
X4 ch
EMAC
10/100
1588
USB
FS
Device
FFPI
2KB Cache
SAM-BA
DMA
DMA
EBI
Lite
SMC
NAND
FPGA
LCD
8 -bit
PMC
Back-up Domain
RTC
8 Backup
registers
RTT
POR/BOD
Supply Cont.
32 KHz
RC/Xtal
Peripherals
Bridge 0
DMA
PDC
DMA
PDC
DMA
PDC
PDC
UART
x1
USART
x2
SPI
x1
TWI
x2
DMA
HSMCI
x1
Peripheral DMA
Controller 0
PDC
PDC
PDC
PDC
PDC
GPIO
x117
Timer
32bit
9 ch
AFE
16bit
16 ch
AFE
16bit
8 ch
DAC
12bit
2 ch
Peripheral DMA
Controller 1
PDC
69
PDC
Analog Parallel
I/O
Comp.
Cont.
x1
DMA
PDC
PWM
x4
Peripherals
Bridge 1
CAN
x2
DMA
PDC
UART
x1
DMA
AES
256b
SAM4E Series
Floating Point Unit benefits
•
32-bit single-precision unit (FPv4-SP extension)
•
•
Better code efficiency
•
•
•
Avoid data scaling and saturation
CMSIS DSP Library Performance:
•
70
Single instruction Add/Subtract/Multiply/Square root operations
Faster data processing than a Cortex-M4 without FPU
Higher precision and dynamic range compared to Q fixed point number format
•
•
IEEE 754 standard compliant (same as PCs)
CortexTM-M4 SIMD + FPU vs. Cortex M3
SAM4E Series
High Speed Architecture
•
Dual high speed peripheral bridges
• DMA and PDC support
•
Dual PDC
• Seen as two different masters by Matrix
• Allowing concurrent access EBI/internal SRAM
•
4-channel DMA Controller
• Adds memory-to-memory transfer capability
PDC0
4 ch
DMA
PDC1
7-layer AHB Matrix
Peripheral Bridge 0
Peripheral Bridge 1
APB
71
SAM4E Series
Cache System Architecture
•
Same architecture as SAM4SA/SD
Cortex-M4
•
Zero Wait State access at full speed
I bus
•
Cache system is managed by the
Enhanced Embedded Flash Controller
(EEFC)
D bus
Mux
I/D
bus
S bus
Cache
•
The cache system embeds:
I/D
bus
• 2 kB of 4-way consecutive cache
• Monitor system
• 32-bit monitor counter
•
72
The monitor allows to evaluate the
usage of cache system in the
application.
AHB Matrix
I/D bus
ROM
I/D bus
FLASH
S bus
SRAM
SAM4E Series
Event Managers
Event Generators
PMC Clock
Failure
Management
ADC
Trig
Conversion
Timer
Trig
Capture
Analog
Comparator
Trig
Comparison
Parallel IO
Capture
DAC
Trig
Conversion
PWM
Fault
Inputs
Input pins
X
X
-
X
X
X
TC Output
X
-
-
-
X
X
Analog
Comparator
-
-
-
-
-
X
PWM Event
Line
X
-
-
X
X
-
-
-
-
-
PWM Output
Compare Line
-
AFE
PMC Event
73
X
-
X
X
SAM4E Series
Ethernet Controller Highlights
•
10Mbps and 100Mbps operations
•
MII mode support only
•
Two 128 bytes FIFO
•
MDIO interface for external PHY management
•
Supports Wake-on-LAN
• Allows computers to be turned on/awakened by a network message
•
IEEE 1588 support
• Precision Time Protocol frames recognition
• Allows synchronization between clocks within computers network
74
SAM4E Series
Precision Time Protocol (IEEE 1588) Principle
•
Ethernet communications are non-deterministic
Sender
Execute
task X!
Receiver
Executing
task X!
Some time later…
•
IEEE 1588 protocol adds data time stamping and clock synchronization
Executing X at
time=Y
Execute X at
time=Y
Sender
Receiver
Time stamp
Sender
PTP
75
Execute X at
time=Y
Time stamp + synchronization
Sender Clock ≠ Receiver clock
=> Time Y differs
Executing X at
time=Y
Receiver
Sender clock = Receiver Clock
=> Deterministic behavior
03/14/2012
SAM4E Series
Precision Time Protocol (IEEE 1588) Implementation
•
The hardware Time Stamp Unit (TSU) captures the time and detect when a
message was sent or received.
Slave 1
PTP
UDP
IP
Slave 2
MASTER
MAC
PHY
Time-stamped frame
Slave 2
76
Time Stamp
SAM4E Series
Advanced Analog Features
•
Two Analog Front End controller (AFE)
•
•
•
•
•
•
•
2 x 12-channel of 12-bit resolution with 1Msps sampling rate
Enhanced resolution mode gives up to 16-bit resolution at 4ksps
Auto-calibration
Offset and gain compensation
Single-ended and differential input modes
PDC support
Digital-to-Analog controller (DAC)
• 2-channel 12-bit resolution
• PDC support
•
77
Analog comparator
SAM4E Series
Analog Front End (AFE)
•
Each Analog Front End is made of:
• One Successive Approximation ADC
• + one PGA (Programmable Gain Amplifier)
• + one DAC in feedback for offset correction of ADC input
78
SAM4E Series
AFE – How resolution is increased ? (1/4)
•
Resolution is increased by:
• Correcting the offset
• Amplifying the gain
• Then performing digital averaging
DR (Dynamic Range): range of signal amplitudes which
the ADC can resolve
Vref
DR: +2 bits
Offset
Vin
Offset
Correction
79
DR=12 +2 bits
DR=12+2+2 bits
noise
Gain
Amplification
ADC Conversion
(12-bit)
ADC Averaging
16 samples
SAM4E Series
•
Offset correction (Single ended mode only)
• Allows use of the full voltage range
• Avoid saturation when amplifiying the gain
the ADC can resolve
Vref
DR: +2 bits
Offset
Vin
Offset
Correction
80
DR=12 +2 bits
DR=12+2+2 bits
noise
Gain
Amplification
ADC Conversion
(12-bit)
ADC Averaging
16 samples
SAM4E Series
•
Gain Amplification
• Amplify low-amplitude signals before conversion
• Improve dynamic range
the ADC can resolve
Vref
DR: +2 bits
DR=12 +2 bits
DR=12+2+2 bits
noise
Vin
Offset
Offset
Correction
81
noise
Gain
Amplification
ADC Conversion
(12-bit)
ADC Averaging
16 samples
SAM4E Series
•
Digital Averaging (Enhanced Resolution Mode is enabled)
• Increase signal-to-noise ratio, adding resolution bits
• White noise must be present in the signal (1 to 2 LSB)
• If not, add noise to the signal
the ADC can resolve
Vref
DR: +2 bits
DR=12 +2 bits
DR=12+2+2 bits
noise
Offset
Vin
Offset
Correction
82
noise
Gain
Amplification
ADC Conversion
(12-bit)
ADC Averaging
16 samples
SAM4E Series
AFE – Data Rate vs. Averaging
•
Digital Averaging Performance Cost:
• Increasing resolution decreases sampling rate
No Averaging
1000.0
Data Rate vs. Averaging
1000.0
Datarate (kHz)
250.0
100.0
62.5
16-bit mode
(256 samples)
31.3
15.6
10.0
7.8
3.9
1.0
0
1
2
3
4
5
Average stage: 1 , 4, 16, 32, 64, 128, 256
83
6
7
8
datarate (kHz)
SAM4E Series
AFE - Performances (1/2)
•
Conditions @ 25 degrees with Gain =1 (Single Ended Mode)
fADC = 20 MHz
fS = 1 MHz, ADC Sampling Frequency in Free Run Mode
ADVREF = 3V
Signal Amplitude: ADVref/2, Signal Frequency < 100 Hz
dynamic range (bits)
•
•
•
•
14,0
13,0
12,0
11,0
10,0
9,0
8,0
7,0
6,0
5,0
4,0
3,0
2,0
1,0
0,0
10,2
10,2
10,2
0,0
1
0,8
4
ENOB
Averaging (bits)
10,2
1,6
2,2
16
64
Number of Samples
84
10,2
3,0
256
SAM4E Series
AFE - Performances (2/2)
•
Conditions @ 25 degrees with Gain =4 (Single Ended Mode)
•
•
•
•
fADC = 20 MHz
fS = 1 MHz, ADC Sampling Frequency in Free Run Mode
ADVREF = 3V
Signal Amplitude: ADVref/2, Signal Frequency < 100 Hz
13,0
12,0
11,0
dynamic range (bits)
10,0
9,0
8,0
9,5
7,0
9,5
6,0
5,0
Averaging (bits)
9,5
9,5
4,0
3,0
2,0
1,0
0,0
0,0
1
0,7
4
1,3
1,9
16
64
Number of Samples
85
ENOB
9,5
2,6
256
SAM4E Series
Safety and Security
•
Dual Watchdog
• Reinforced Watchdog Timer (RSWDT) to reinforce safety in case of 32k crystal clock failure
• Watchdogs have the exact same features BUT different clock sources
• RSWDT clock source automatically selected from 32kHz RC or Fast RC
86
•
AES
• Encryption engine for high data rate secured communications
• 128/256-bit key
• Compliant with FIPS Publication 197
•
Zero Wait State EBI scrambling/unscrambling
•
Flash ECC/Lock Bit/Security Bit
•
Low-power Tamper Detection on two Inputs
•
Anti-Tampering by clear of the first half of General Purpose Backup Registers
SAM4 Flash MCUs
87
SAM4 Flash MCUs
Memory & System
SAM4N
Supply
88
SAM4S
SAM4E
1.62V-3.6V
MPU / FPU
√/-
Max Frequency
100MHz
FLASH
Up to 1MB
Up to 2MB
Up to 1MB
SRAM
Up to 80kB
Up to 160kB
Up to 128kB
Dual Bank Flash
-
√
-
Bank Boot Selection
-
√
-
2 kB Cache
-
√
√
External Bus Interface
-
√
√
Peripheral DMA(PDC)
√
√
√
Memory to Memory DMA
-
-
√
√
√
√
Temperature Range
-40/85°C
-40/+105°C
-40/+105°C
√/-
√/√
120MHz
SAM4 Flash MCUs
89
Peripherals
SAM4N
SAM4S
SAM4E
CAN
-
-
√
AES
-
-
√
Ethernet
-
-
√
Dual Watchdog
-
-
√
PIO Parallel Capture
-
√
√
CRC Unit
-
√
-
32-bit Timers
-
-
√
ADC / AFE
1x12-bit / -
1x12-bit / -
- / 2x16-bit
DAC
1x10-bit
1x12-bit
1x12-bit
Analog Comparator
-
√
√
SAM4 Flash MCUs
Embedded Features
SAM4N
SAM4S
Flash 1-bit ECC / Lock bits / Security bit
√
PMC Clock Failure Detector
√
I/O On-Die Termination
√
Fast RC Trimming
√
EBI Scrambling
-
√
RTC Trimming
RTC Waveform Generation (RTCOUT pins)
√
√
-
√
ADC HW Gain Calibration
90
SAM4E
√
√
ADC Programmable Gain Amplifier
-
√
√
ADC Offset Correction
-
√
√
ADC Digital Averaging
√
-
√
Anti-Tamper pins (WKUP0/1)
√
√
√
SAM4 Flash MCUs
Current Consumption
(IVDDIO + IVDDIN) @25°C
Active Mode
(VDDIO=VDDIN=3.3V)
Sleep Mode
(VDDIO=VDDIN=3.3V and MCK = 120 MHz)
SAM4N
SAM4S
SAM4E
140 uA/MHz
170 uA/MHz
(SAM4S4/2)
190 uA/MHz
180 uA/MHz
5.23mA
6.9mA
11.4mA
28.4 uA
28.4 uA
56uA
23.9 uA
24.1 uA
47 uA
700nA
800nA
900nA
(MCK = 80 MHz)
Wait Mode
With Flash in Standby Mode
(VDDIO=VDDIN=3.6V)
Wait Mode
With Flash in Deep Power Down Mode
(VDDIO=VDDIN=3.6V)
Backup Mode
(VDDIO=VDDIN=1.8V)
91
Appendix
SAM4L Series
92
03/14/2012
SAM4L Series
First Cortex-M4 Flash MCU
with PicoPower technology
93
03/14/2012
SAM4LS Series Overview
Masters
Slaves
Debug
JTAG/SW
System Peripheral
Package
picoPower
LQFP/QFN48
LQFP/QFN64
LQFP/VFBGA100
WLCSP64
90µA/MHz
1.5µA - Full SRAM
0.5µA - Backup
SleepWalking
Dynamic
Freq. Scaling
Touch controller
USB Device
Internal memories
Serial Number
LDO/Buck
User Row
4/8/12 MHz
RC OSC
SRAM
64KB
32KB
32KB
Cortex-M4
48 MHz
PLL/DFLL
0.45-16MHz
Xtal OSC0
MPU
Freq Meter
115 KHz
RC OSC
I/D
Flash
512KB
256KB
128KB
USB
FS
Device
System
DMA
PMC
Back-up Domain
4 Backup
registers
PICO UART
32 KHz
RC/Xtal
POR/BOD
AST
WDT
Peripheral
Bridge
Ext. Interrupt Controller
PDC
PDC
PDC
USART
x4
SPI
x1
TWI
x2 MS
x2 M
Peripheral DMA
Controller
PDC
GPIO
x80
Timer
16bit
6 ch
ADC
12bit
16 ch
PDC
Analog
Comp.
4 ch
GLOC
2 ch
DAC
10bit
1 ch
PDC
PDC
PDC
I2S
Parallel
I/O
Cont.
CATB
Peripheral Event System
94
CRC
TRNG
SAM4LC Series Overview
Masters
Slaves
Debug
JTAG/SW
System Peripheral
Package
picoPower
LQFP/QFN48
LQFP/QFN64
LQFP/VFBGA100
WLCSP64
90µA/MHz
1.5µA - Full SRAM
0.5µA - Backup
SleepWalking
Dynamic
Freq. Scaling
Touch controller
USB Host/Device
Segment LCD
Internal memories
Serial Number
LDO/Buck
User Row
4/8/12 MHz
RC OSC
SRAM
64KB
32KB
32KB
Cortex-M4
48 MHz
PLL/DFLL
0.45-16MHz
Xtal OSC0
MPU
Freq Meter
115 KHz
RC OSC
I/D
USB
FS
Host
&
Device
Flash
512KB
256KB
128KB
System
DMA
PMC
Back-up Domain
4 Backup
registers
PICO UART
32 KHz
RC/Xtal
POR/BOD
AST
WDT
Peripheral
Bridge
Ext. Interrupt Controller
PDC
PDC
PDC
USART
x4
SPI
x1
TWI
x2 MS
x2 M
Peripheral DMA
Controller
PDC
GPIO
x75
Timer
16bit
6 ch
ADC
12bit
16 ch
PDC
Analog
Comp.
4 ch
GLOC
2 ch
DAC
10bit
1 ch
PDC
PDC
PDC
I2S
Parallel
I/O
Cont.
LCD
4x40
Peripheral Event System
95
CRC
TRNG
PDC
PDC
CATB
AES
128b
SAM4L Series
Please look for its dedicated presentation:
96
© 2012 Atmel Corporation. All rights reserved.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product
names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel
products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING
TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE
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make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and
shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
97

Atmel SAM3/SAM4 Flash MCU

Transcription

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