ITRS ROADMAPPING PROCESS For Lithography

Transcription

ITRS ROADMAPPING PROCESS
For Lithography
Mark Neisser, Frank Goodwin, Long He
International Technology Roadmap for Semiconductors
Mark Neisser - ITRS Lithography Chair; Frank Goodwin, Long He - ITRS Mask Table
ITRS Purpose
The ITRS serves as a guideline for the global industry for a 15-year
outlook on projected technology needs and opportunities for
innovation.
The ITRS is a pre-competitive instrument, devised and intended for
technology assessment only and is without regard to any commercial
considerations pertaining to individual products or equipment.
International Technology Working Groups (ITWGs) forecast the
technology requirements and areas of needed innovation for 15 years
Expertise covers major technology disciplines of the industry:
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Overall Roadmap Technology Characteristics (ORTC)
Design
System Drivers
Test and Test Equipment
Micro-Electro-Mechanical Systems (MEMS)
RF and Analog/Mixed-signal Technologies (RFAMS)
Emerging Research Materials (ERM)
Emerging Research Devices (ERD)
Process Integration, Devices, and Structures (PIDS)
February 14, 2013
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Front End Processes (FEP)
Lithography
Interconnect
Assembly and Packaging
Factory Integration (FI)
Environment, Safety, and Health (ESH)
Metrology
Yield Enhancement
Modeling and Simulation
2
ITRS Sponsors and Composition

Jointly sponsored by five regions of the world
■ Europe, Japan, Korea, Taiwan, and the U.S.A.

Representatives are from each region's domestic working groups (DTWGs):
industry, government labs, supplier community, consortia, and academia
Note: Pie chart data is from about 2007 and will be updated this year.
February 14, 2013
3
ITRS Litho Process for 2013
• Public Litho
Roadmap
Presentation
• Identify litho work
items for 2014
Baseline data
distributed,
Table owners
Identified
Final
Roadmap
published
• Updated ORTC
Data
• Tables from 2012
with adjusted years
• 2011 chapter for
revision
Spring Face
to Face
Global
meeting
April 22-23,
2013
Winter Face
to Face
Global
Meeting
Dec. 4-6,
2013
2013 Litho
Tables and
Chapter
submitted to
ITRS in
September
Global review
of tables
Writing of
Litho Chapter
Regular
Meetings of
Domestic
TWGs
Summer Face
to Face Global
meeting
Week of July
8, 2013
Table
Updates by
Table owners
• Review updates
• Present public
status update at
SEMICON US
February 14, 2013
4
ITRS Outputs are Documents and Tables
ITRS 2012 UPDATE
2012 Overview by the International Roadmap Committee (IRC)
2012 Acknowledgments
2011 Executive Summary
2012 Overall Roadmap Technology Characteristics (ORTC) Tables
2012
Winter Presentations
Tables
Chapters
Updated
Test and Test Equipment
2012 tables
2011 chapter
Updated
Process Integration, Devices, and Structures (PIDS)
PLUS MASTAR Model
2012 tables
2011 chapter
Updated
RF and Analog/Mixed-signal Technologies (RFAMS)
2012 tables
2011 chapter
Updated
Micro-Electro-Mechanical Systems (MEMS)
2012 tables
2011 chapter
2011 tables
2011 chapter
Emerging Research Materials (ERM)
2011 tables
2011 chapter
Updated
Front End Processes (FEP)
2012 tables
2011 chapter
Updated
Lithography
2012 tables
2011 chapter
Factory Integration
2011 tables
2011 chapter
Environment, Safety & Health
2011 tables
2011 chapter
Updated
Yield Enhancement
2012 tables
2011 chapter
Updated
Metrology
2012 tables
2011 chapter
Updated
Modeling & Simulation
2012 tables
2011 chapter
System Drivers
2011 tables
2011 chapter
Design
2011 tables
2011 chapter
Updated
Interconnect
2012 tables
2011 chapter
Updated
Assembly & Packaging
2012 tables
2011 chapter
Emerging Research Devices (ERD)
February 14,
2013
5
Roadmap Topics – TECHNOLOGY CHAPTERS
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Written by the ITWGs
Present the technical roadmaps and the assessments for critical challenges
and needs to be resolved for positive industry growth, innovation, and
development
Required conventions/topics for each chapter and roadmap are:
■ Scope
■ Difficult Challenges [discussion and tables]
■ Technology Requirements [discussion and tables]
• [legend defines status of need [Solutions are known, being
qualified, unknown, or interim]
■ Potential Solutions [chart]
• [legend defines still in research, being developed, in production, or
in qualification, or improved]
■ CrossCut Issues [ESH, Metrology, Modeling and Simulation, and Yield
Enhancement]
■ Interfocus ITWG issues
February 14, 2013
6
ITRS Tables

Tables are Microsoft Excel based with showing specification by year.
All numbers refers to what is in leading edge manufacturing for that
year. For example, as seen below 28nm is expected to be the leading
edge DRAM half pitch in 2013 and to have just started manufacturing in
that year.
Year of Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
36
32
28
25
23
20
18
16
14
13
11
10.0
8.9
8.0
7.1
6.3
DRAM
DRAM ½ pitch (nm)

The color code has the following significance
Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known
Interim solutions are known 
Manufacturable solutions are NOT known
February 14, 2013
7
Table ORTC-1

Basic device numbers come from ORTC (“Overall Roadmap
Technology Characteristics”) tables
■ They are projected semiconductor industry technology nodes for
leading edge manufacturing production
■ They are reviewed and updated as needed, including in 2013.
■ A sample table from the 2012 data is shown below
February 14, 2013
8
2012 Litho Tables

Most tables are standard tables of lithographic requirements
February 14, 2013
Lithography
Table LITH1
Table LITH2
Table LITH3
Table LITH4
Table LITH5
Table LITH6
Table LITH7
Table LITH8
Table LITH9
Long and Short Term Lithography Difficult Challenges
Lithography Technology Requirements
Resist Requirements
Optical Mask Requirements
Multiple Patterning / Spacer Requirements
EUVL Mask Requirements
Imprint Template Requirements
Maskless Lithography Technology Requirements
Materials Requirements
Figure LITH3A
Figure LITH3B
DRAM and MPU Potential Solutions
Flash Potential Solutions
9
2012 Litho Tables
Table LITH1, “Difficult Challenges” looks like this:

3
4
5
6
Near Term Challenges (2011-2018)
(16nm Logic/DRAM @ HVM; Flash 11nm @ optical narrowing with 16nm in HVM)
Cost and cycle time of multiple patterning - especially for more than 2x
Optical mask complexity
EUV source power
Defect "free" EUV masks availability
mask infrastructure availability
EUV Resist that meets sensitivity, resolution, LER requirements
Process control on key parameters such as overlay, CD control, LWR with multiple patterning
Retooling requirements for 450mm transition (Economic & Technology Challenges)
1
2
3
4
5
6
Long Term Challenges (2019 - 2025)
(11nm hp@HVM)
Higher source power, increase in NA, chief ray angle change on EUV; Mask material and thickness optimization
EUV with multiple exposures for 2D patterns
Defect free DSA processing
DSA compatible design rules
Selection of new EUV wavelength taking resist, mask, source and tool technology into account
Metrology tool availability to key parameters such as CDU, thickness control, overlay, defect
1
2
February 14, 2013
10
2012 Litho Tables

Tables LITH3A and LITH 3B. “Potential Solutions” look like this. They are the
most commonly cited litho component of the roadmap.
Flash
First Year of IC Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
Flash ½ Pitch (nm) (un-contacted Poly)(f)
22
20
18
17
15
14
13
12
11
10.0
8.9
8.0
8.0
8.0
8.0
8.0
32 193 nm DP
22 193 nm DP
NAND Flash Time Line
16 193nm MP
EUV
Narrow Options
Imprint
11 EUV higher NA / EUV + DP
193nm MP
DSA + Litho
EUV (new wavelength)
Imprint
Innovation
First Year of IC Production
DRAM/MPU
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
36
32
28
25
23
20
18
16
14
13
11
10.0
8.9
8.0
7.1
6.3
MPU/ASIC Metal 1 1/2 pitch (nm)
38
32
27
24
21
19
17
15
13
12
11
9.5
8.4
7.5
6.7
6.0
193nm Imm
32
193 nm DP
22
EUV
193nm MP
ML2 (MPU)
11
February 14, 2013
2011
DRAM ½ pitch (nm) (contacted)
45
16
Narrow Options
EUV
193nm MP
ML2
DSA + Litho
Imprint
EUV higher NA / EUV + DP
ML2
DSA + Litho
EUV (new wavelength)
Imprint
Innovation
Narrow Options
MPU / DRAM time line
Narrow Options
Narrow Options
11
EUV Mask Table
Year of Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
Generic Mask Requirements
Mask magnification [A]
Mask nominal image size (nm) [B]
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
141
126
112
100
89
79
71
63
56
50
44
40
35
31
27
23
Mask minimum primary feature size [C]
99
88
78
70
62
55
49
44
39
35
31
28
25
22
19
16
Image placement (nm, multipoint) [D]
4.3
3.8
3.2
2.9
2.5
2.3
2.0
1.8
1.6
1.4
1.3
1.1
1.0
0.9
0.8
0.7
Isolated lines (MPU gates)
3.1
2.8
2.6
2.4
2.1
2.0
1.8
1.6
1.5
1.4
1.2
1.1
1.0
0.9
0.8
0.8
Dense lines DRAM (half pitch)
2.6
2.3
2.0
1.8
1.6
1.4
1.3
1.2
1.0
0.9
0.8
0.7
0.6
0.6
0.5
0.5
Contact/vias
2.0
1.8
1.6
1.4
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.6
0.5
0.4
0.4
0.3
Linearity (nm) [F]
5.4
4.8
4.3
3.8
3.4
3.0
2.7
2.4
2.2
1.9
1.7
1.5
1.4
1.2
1.1
1.0
CD mean to target (nm) [G]
2.9
2.5
2.3
2.0
1.8
1.6
1.4
1.3
1.1
1.0
0.9
0.8
0.7
0.6
0.6
0.5
Defect size (nm) [H]
29
25
23
20
18
16
14
13
11
10
9
8
7
6
6
5
Data volume (GB) [I]
825
1100
1300
1700
2100
2600
3300
4200
5200
6600
8300
10000
13000
16000
20000
25000
1
1
1
1
1
0.50
0.50
0.50
0.50
0.50
0.25
0.25
0.25
0.25
0.25
0.25
Substrate defect size (nm) [K]
37
35
34
32
30
29
27
26
24
22
21
19
17
16
14
12
Blank defect size (nm) [L]
29
25
23
20
18
16
14
13
11
10
9
8.0
7.1
6.4
5.7
5.1
CD uniformity (nm, 3 sigma) [E]
Mask design grid (nm) [J]
EUVL-specific Mask Requirements
Mean peak reflectivity
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
Peak reflectivity
3 sigma absolute)
Reflected
centroiduniformity
wavelength(%uniformity
(nm 3
sigma) [M]
0.42%
0.37%
0.33%
0.29%
0.26%
0.23%
0.21%
0.19%
0.17%
0.15%
0.13%
0.12%
0.11%
0.09%
0.08%
0.08%
0.05
0.05
0.05
0.04
0.04
0.04
0.03
0.03
0.03
0.02
0.02
0.02
0.02
0.02
0.02
0.02
Absorber film thickness Control (nm, 3 sigma) [N]
0.93
0.83
0.74
0.66
0.58
0.52
0.46
0.41
0.37
0.33
0.29
0.26
0.23
0.21
0.18
0.16
Absorber sidewall angle tolerance (± degrees) [O]
0.69
0.62
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Absorber LWR (3 sigma nm) [P]
4.2
3.7
3.3
3.0
2.6
2.4
2.1
1.9
1.7
1.5
1.3
1.2
1.0
0.9
0.8
0.7
Mask flatness (nm peak-to-valley) [Q]
41
36
31
27
24
22
19
17
15
14
12
11
10
9
8
7
Final Mask Bow (over 142mm x 142mm) (nm)
Local Slope backside (caculated with 20x20mm² area
over 142 x 142 mm²) (µrad)
600
600
600
500
400
400
400
300
300
300
200
200
200
200
200
200
1.0
1.0
1.0
0.9
0.8
0.8
0.7
0.6
0.6
0.5
0.5
0.5
0.5
0.5
0.5
0.5

Will have to change color code to grey for columns corresponding to
years where no EUV volume manufacturing will be done.
February 14, 2013
12
Litho Changes planned for 2013

Review and revision of “Difficult Challenges
■
This is done annually.
■
Table is reviewed for this at every face to face meeting

Revision of “Potential Solutions” tables
■
Elimination of nodes clearly in manufacturing
■
Update of node names and target CDs
■
Addition of a new node together with possibilities
■
Adjustment of decision dates based on industry inputs

Clean up of cells to make accurate color codes
■
No red codes for 2013
■
Will add a grey color for tables showing capabilities of technology not in manufacturing (for example,
EUV)
■
Grey colors will have to correlate with revised “Possible Options” charts

Addition of DSA related tables

Review and revision of other tables and extensions to two additional years. The years 2011 and 2012 will be
dropped and 2027 and 2028 will be added.

Publication of 2013 Lithography “Chapter” document (2011 document was the last published “chapter”)
February 14, 2013
13
Lithography Technology Requirements
Table LITH2 Lithography Technology Requirements
Year of Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
DRAM
DRAM ½ pitch (nm)
36
32
28
25
23
20
18
16
14
13
11
10.0
8.9
8.0
7.1
6.3
CD control (3 sigma) (nm) [B]
3.7
3.3
2.9
2.6
2.3
2.1
1.9
1.7
1.5
1.3
1.2
1.0
0.9
0.8
0.7
0.7
Contact after etch (nm)
36
32
28
25
23
20
18
16
14
13
11
10
8.9
8.0
7.1
6.3
Overlay [A] (3 sigma) (nm)
7.1
6.4
5.7
5.1
4.5
4.0
3.6
3.2
2.8
2.5
2.3
2.0
1.8
1.6
1.4
1.3
k1 (13.5nm) EUVL
0.66
0.59
0.52
0.62
0.55
0.49
0.44
0.51
0.45
0.40
0.47
0.42
0.37
0.33
0.29
0.26
Flash
Flash ½ pitch (nm) (un-contacted poly)
22
20
18
17
15
14.2
13.0
11.9
10.9
10.0
8.9
8.0
8.0
8.0
8.0
8.0
CD control (3 sigma) (nm) [B]
2.3
2.1
1.9
1.8
1.6
1.5
1.4
1.2
1.1
1.0
0.9
0.8
0.8
0.8
0.8
0.8
Bit line Contact Pitch (nm) [D]
131
120
110
101
93
113
104
95
87
80
71
64
64
64
64
64
36
32
28
25
23
20
18
16
14
13
11
10
8.9
8.0
7.1
6.3
7.2
6.6
6.1
5.6
5.1
4.7
4.3
3.9
3.6
3.3
2.9
2.6
2.6
2.6
2.6
2.6
k1 (13.5nm) EUVL
0.40
0.37
0.34
0.41
0.38
0.35
0.32
0.38
0.35
0.32
0.37
0.33
0.33
0.33
0.33
0.33
MPU/ASIC Metal 1 (M1) ½ pitch (nm)
38
32
27
24
21
19
17
15
13
12
11
9.5
8.4
7.5
6.7
6.0
MPU gate in resist (nm)
35
31
28
25
22
20
18
16
14
12
11
9.9
8.8
7.9
6.8
5.9
MPU physical gate length (nm) *
24
22
20
18
17
15
14
13
12
11
9.7
8.9
8.1
7.4
6.6
5.9
Gate CD control (3 sigma) (nm) [B] **
2.5
2.3
2.1
1.9
1.7
1.6
1.5
1.3
1.2
1.1
1.0
0.9
0.8
0.8
0.7
0.6
43
36
30
27
24
21
19
17
15
13
12
11
9.5
8.4
7.5
6.7
7.6
6.4
5.4
4.8
4.2
3.8
3.4
3.0
2.7
2.4
2.1
1.9
1.7
1.5
1.3
1.2
k1 (13.5nm) EUVL
0.70
0.59
0.50
0.58
0.52
0.46
0.41
0.48
0.43
0.38
0.44
0.39
0.35
0.31
0.28
0.25
Maximum exposure field height (mm)
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
Maximum exposure field length (mm)
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
Maximum field area printed by exposure tool (mm )
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
Wafer site flatness at exposure step (nm) [C]
38
34
30
27
24
21
19
17
15
13
12
11
10.0
9.0
8.0
7.0
MPU / Logic
Chip size (mm 2 )
2
Number of mask Counts MPU [E]
50
54
44
Number of mask Counts DRAM [E]
41
33
38
Number of mask Counts Flash [E]
43
31
50
Wafer size (diameter, mm)
300
300
300
300
300
450
450
450
450
450
450
450
450
450
450
450
NA required for logic (single exposure)
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
NA required for double exposure (Flash)
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
NA required for double exposure (logic)
1.12
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
EUV (13.5nm) NA
0.25
0.25
0.25
0.33
0.33
0.33
0.33
0.43
0.43
0.43
0.56
0.56
0.56
0.56
0.56
0.56
Numerical Aperture (NA) increases require significant changes to mask blank stack
and/or potentially increase of mask magnification!
02/24/2012
14
Optical Mask ITRS Table (2011) Needs Maintenance
Phase Shifting
Patterning
Table LITH4
Optical Mask Requirements
Patterning
Steps
1
2
3
4
5
6
7
Patterning
Steps
1
2
3
4
5
6
7
Year of Production
DRAM (M1) ½ pitch (nm) (contacted)
DRAM CD control (3 sigma) (nm)
MPU/ASIC Metal 1 (M1) ½ Pitch
(nm)(contacted)
Gate CD control (3 sigma) (nm)
Overlay (3 sigma) (nm) [R]
Contact in resist (nm) [A]
Mask magnification
Mask minimum primary feature size [B]
Mask sub-resolution feature size (nm) opaque
[C]
CD uniformity allocation to mask
(assumption)
MEEF isolated lines, binary or attenuated
phase shift mask [E]
CD uniformity (nm, 3 sigma) isolated lines
(MPU gates), binary or attenuated phase shift
mask [F]
MEEF dense lines, binary or attenuated phase
shift mask [E]
CD uniformity (nm, 3 sigma) dense lines
(DRAM half pitch), binary or attenuated phase
shift mask [F]
MEEF contacts [E]
CD uniformity (nm, 3 sigma), contact/vias [G]
Linearity (nm) [H]
CD mean to target (nm) [I]
Defect size (nm) [J]
Blank flatness (nm, peak-valley) [K]
Pellicle thickness uniformity [L]
2011
36
3.7
22
2012
32
3.3
20
2013
28
2.9
18
2014
25
2.6
17
2015
23
2.3
15
2016
20
2.1
14
2017
18
1.9
13
2018
16
1.7
12
2019
14
1.5
11
2020
13
1.3
10.0
2021
11
1.2
8.9
2022
10.0
1.0
8.0
2023
8.9
0.9
8.0
2024
8.0
0.8
8.0
2025
7.1
0.7
8.0
2026
6.3
0.7
8.0
38
35
2.5
7.1
67
32
31
2.3
6.4
59
27
28
2.1
5.4
53
24
25
1.9
4.8
47.0
21
22
1.7
4.2
42.0
19
20
1.6
3.8
37.0
17
18
1.5
3.4
37.0
15
16
1.3
3.0
37.0
13
14
1.2
2.7
37.0
12
12
1.1
2.4
37.0
11
11
1.0
2.1
37.0
9.5
9.9
0.9
1.9
37.0
8.4
8.8
0.8
1.7
37.0
7.5
7.9
0.8
1.5
37.0
6.7
6.8
0.8
1.3
37.0
6.0
5.9
0.8
1.2
37.0
4
99
4
88
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
4
80
71
4.3
63
3.8
56
3.2
50
2.9
44
2.5
40
2.3
40
2.0
40
1.8
40
1.6
40
1.4
40
1.3
40
1.1
40
1.0
40
0.9
40
0.8
40
0.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
2.2
2.2
2.4
2.6
2.8
3
3
3
3
3
3
3
3
3
3
3
2.3
2.1
1.7
1.5
1.2
1.1
1.0
0.9
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.5
2.5
2.8
3.1
3.4
3.7
4
4
4
4
4
4
4
4
4
4
4
3.0
5
1.5
5.7
2.9
2.4
5.6
1.2
5.1
2.5
1.9
6.2
1.0
4.5
2.3
1.5
6.8
0.8
4.0
2.0
1.3
7.4
0.6
3.6
1.8
1.0
8
0.5
3.2
1.6
0.9
8
0.5
2.9
1.4
0.8
8
0.4
2.5
1.3
0.7
8
0.4
2.3
1.1
0.7
8
0.3
2.0
1.0
0.6
8
0.3
1.8
0.9
0.5
8
0.3
1.6
0.8
0.5
8
0.2
1.4
0.7
0.4
8
0.2
1.3
0.6
0.4
8
0.2
1.1
0.6
0.3
8
0.2
1.0
0.5
32
151
3.3
29
135
3.1
25
120
2.8
23
107
2.6
20
95
2.4
18
85
2.2
16
76
2.0
14
68
1.9
13
61
1.7
11
54
1.6
10
48
1.5
10
43
1.4
10
38
1.3
10
34
1.2
10
30
1.1
10
27
1.0
Data volume (GB) [M]
Mask design grid (nm) [N]
Attenuated PSM transmission mean deviation
from target (± % of target) [O]
Attenuated PSM transmission uniformity (%
of target transimission, range)
Attenuated PSM phase mean deviation from
target (± degree) [P]
Attenuated PSM phase uniformity ( degree ,
range) [Q]
Alternating PSM phase mean deviation from
nominal phase angle target (± degree) [P]
Alternating PSM phase uniformity (degree,
range) [Q]
1570
1
1880
1
2220
1
2580
1
2970
1
2970
1
2970
1
2970
1
2970
0.5
2970
0.5
2970
0.5
2970
0.5
2970
0.5
2970
0.5
2970
0.5
2970
0.5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
02/24/2012
15
EUVL Mask ITRS Table (2011) Needs Fairly
Amount of Work
Table LITH6 EUVL Mask Requirements
(1)
Referenc
e
Year of Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
DRAM ½ pitch (nm)
36
32
28
25
23
20
18
16
14
13
11
10.0
8.9
8.0
7.1
6.3
DRAM/Flash CD control (3 sigma) (nm)
3.7
3.3
2.9
2.6
2.3
2.1
1.9
1.7
1.5
1.3
1.2
1.0
0.9
0.8
0.7
0.7
22
20
18
17
15
14
13
12
11
10
8.9
8.0
8.0
8.0
8.0
8.0
MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted)
38
32
27
24
21
19
17
15
13
12
11
9
8.4
7.5
6.7
6.0
35
31
28
25
22
20
18
16
14
12
11
10
8.8
7.9
6.8
5.9
MPU physical gate length (nm)
24
22
20
18
17
15
14
13
12
11
10
8.9
8.1
7.4
6.6
5.9
Gate CD control (3 sigma) (nm)
2.5
2.3
2.1
1.9
1.7
1.6
1.5
1.3
1.2
1.1
1.0
0.9
0.8
0.8
0.7
0.6
Overlay (3 sigma) (nm) [R]
7.1
6.4
5.4
4.8
4.2
3.8
3.4
3.0
2.7
2.4
2.1
1.9
1.7
1.5
1.3
1.2
Contact in resist (nm)
36
32
28
25
23
20
18
16
14
13
11
10
8.9
8.0
7.1
6.3
Mask magnification [A]
Mask nominal image size (nm) [B]
(2)
Mask
Generic
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
141
126
112
100
89
79
71
63
56
50
44
40
35
31
27
23
Mask minimum primary feature size [C]
99
88
78
70
62
55
49
44
39
35
31
28
25
22
19
16
4.3
3.8
3.2
2.9
2.5
2.3
2.0
1.8
1.6
1.4
1.3
1.1
1.0
0.9
0.8
0.7
Isolated lines (MPU gates)
3.1
2.8
2.6
2.4
2.1
2.0
1.8
1.6
1.5
1.4
1.2
1.1
1.0
0.9
0.8
0.8
Dense lines DRAM (half pitch)
2.6
2.3
2.0
1.8
1.6
1.4
1.3
1.2
1.0
0.9
0.8
0.7
0.6
0.6
0.5
0.5
Contact/vias
2.0
1.8
1.6
1.4
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.6
0.5
0.4
0.4
0.3
Linearity (nm) [F]
5.4
4.8
4.3
3.8
3.4
3.0
2.7
2.4
2.2
1.9
1.7
1.5
1.4
1.2
1.1
1.0
CD mean to target (nm) [G]
2.9
2.5
2.3
2.0
1.8
1.6
1.4
1.3
1.1
1.0
0.9
0.8
0.7
0.6
0.6
0.5
Defect size (nm) [H]
29
25
23
20
18
16
14
13
11
10
9
8
7
6
6
5
Data volume (GB) [I]
825
1100
1300
1700
2100
2600
3300
4200
5200
6600
8300
10000
13000
16000
20000
25000
1
1
1
1
1
0.50
0.50
0.50
0.50
0.50
0.25
0.25
0.25
0.25
0.25
0.25
Substrate defect size (nm) [K]
37
35
34
32
30
29
27
26
24
22
21
19
17
16
14
12
Blank defect size (nm) [L]
29
25
23
20
18
16
14
13
11
10
9
8.0
7.1
6.4
5.7
5.1
CD uniformity (nm, 3 sigma) [E]
Mask design grid (nm) [J]
EUVL-specific Mask Requirements
(3)
EUV
Specific
Mean peak reflectivity
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
>65%
Peak reflectivity uniformity (% 3 sigma absolute)
Reflected centroid wavelength uniformity (nm 3 sigma)
[M]
0.42%
0.37%
0.33%
0.29%
0.26%
0.23%
0.21%
0.19%
0.17%
0.15%
0.13%
0.12%
0.11%
0.09%
0.08%
0.08%
0.05
0.05
0.05
0.04
0.04
0.04
0.03
0.03
0.03
0.02
0.02
0.02
0.02
0.02
0.02
0.02
Absorber film thickness Control (nm, 3 sigma) [N]
0.93
0.83
0.74
0.66
0.58
0.52
0.46
0.41
0.37
0.33
0.29
0.26
0.23
0.21
0.18
0.16
Absorber sidewall angle tolerance (± degrees) [O]
0.69
0.62
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Absorber LWR (3 sigma nm) [P]
4.2
3.7
3.3
3.0
2.6
2.4
2.1
1.9
1.7
1.5
1.3
1.2
1.0
0.9
0.8
0.7
Mask flatness (nm peak-to-valley) [Q]
41
36
31
27
24
22
19
17
15
14
12
11
10
9
8
7
Final Mask Bow (over 142mm x 142mm) (nm)
600
600
600
500
400
400
400
300
300
300
200
200
200
200
200
200
Local Slope backside (caculated with 20x20mm² area over
142 x 142 mm²) (µrad)
1.0
1.0
1.0
0.9
0.8
0.8
0.7
0.6
0.6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Notes:
• In (1), All references are from Litho table, with one exception. Here contact CDs are listed as “in-resist.”
• In (2), “Generic Mask Requirements” may be EUVL specific.
02/24/2012
16
Discussions (Take a hand-raising vote)
If following requirements/changes needed: (???)
Add MEEF requirements?
 Define mask NA requirements?

Table LITH2 Lithography Technology Requirements
Year of Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
DRAM
DRAM ½ pitch (nm)
36
32
28
25
23
20
18
16
14
13
11
10.0
8.9
8.0
7.1
6.3
EUV (13.5nm) NA
0.25
0.25
0.25
0.33
0.33
0.33
0.33
0.43
0.43
0.43
0.56
0.56
0.56
0.56
0.56
0.56
Mask magnification change: >4X
 Add pellicle requirement?
 Combine the two line-item headers to one: “EUVL Mask
Requirements” ?

Currently: “Generic Mask Requirements” and “EUVL-Specific Mask
Requirements”
Include soft defect requirements?
 Lifetime requirements?

02/24/2012
17
ITRS Workshops and Conferences

IRC and ITWG Workshops
■

Held in representatives’ areas to allow equal hosting by the various teams
■
Europe: 2-Day spring workshop meeting in Europe.
■
United States: 2-Day summer workshop meeting and summer public conference in
USA.
■
Asia: 2-Day winter workshop and winter public release/rollout meeting. The
workshop is also the “kick-off” meeting for work the next year.
■
Provides a forum for all the teams to work together on common technology issues and
shared data
■
Provides a forum for the IRC to discuss the industry assessments, pacing, and drivers.
ITRS Public Conferences
■
Gather feedback from the industry public at large
■
Follow typical technology forum’s format, with regional sponsor greeting, working
group status presentations, possible keynote address or panel discussions to facilitate
interest and feedback
■
Preceded by a one or two-day workshop among the working groups and Executive
Committee for preparation
February 14, 2013
18

ITRS ROADMAPPING PROCESS For Lithography

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