PDF - Pan Stanford Publishing
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PDF - Pan Stanford Publishing
“This book has been excellently written to bridge the gap between theory and practice and to develop the prototype to showcase the talents. The presentation of the book is lucid with adequate figures, tables, and examples. The chapters on logic families, memories, and analog-to-digital and digital-to-analog converters will be useful for postgraduate students as well. Overall, I rate it a very good book.” Prof. Prasanna Kumar Sahu National Institute of Technology, Rourkela, India This book focuses on the basic principles of digital electronics and logic design. It is targeted as a textbook for undergraduate students of electronics, electrical engineering, computer science, physics, and information technology. The text covers the syllabi of several Indian and foreign universities. It depicts the comprehensive resources on the recent ideas in the area of digital electronics explored by leading experts from both industry and academia. A good number of diagrams are provided to illustrate the concepts related to digital electronics so that students can easily comprehend the subject. Solved examples within the text explain the concepts discussed and exercises are provided at the end of each chapter. Subir Kumar Sarkar is professor in the Department of Electronics and Telecommunication Engineering, Jadavpur University, West Bengal, India. He has published five textbooks on engineering and more than 480 technical research papers in archived international and national journals and peer-reviewed conferences. Prof. Sarkar is a senior member of the IEEE; life fellow of the Institute of Engineers, India, and the Institution of Electronics and Telecommunication Engineers, India; and life member of the Indian Society for Technical Education and the Indian Association for the Cultivation of Science. Souvik Sarkar obtained his ME and PhD in engineering from Jadavpur University. He is an application consultant at IBM Global Business Services, India. He has published around 25 research publications in archived international and national journals and peer-reviewed conferences. V319 ISBN 978-981-4364-58-4 Sarkar | De | Sarkar Asish Kumar De is associate professor in the Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India. He has published around 20 research papers in archived international and national journals and peer-reviewed conferences. His research interests include nanodevice simulation and modeling and application of soft computing tools in device modeling. Prof. De has 10 years of research experience and has been teaching for more than 26 years. Foundation of Digital Electronics and Logic Design “This book is a comprehensive work by the authors that provides an understanding of the basic principles of digital electronics and logic design. It describes the functioning of digital circuits, both combinational and sequential, in detail. It also introduces the functioning of modern digital circuits in a simple manner, and problems are worked out for ease of understanding. As a textbook, it will benefit the student pursuing a first course in electrical or computer engineering.” Prof. Goutam Ghosh University of Calcutta, India Foundation of Digital Electronics and Logic Design Subir Kumar Sarkar | Asish Kumar De | Souvik Sarkar Foundation of Digital Electronics and Logic Design Pan Stanford Series on Renewable Energy — Volume 2 Foundation of Digital Electronics and Logic Design editors Preben Maegaard Anna Krenz Wolfgang Palz Subir Kumar Sarkar Asish Kumar De Souvik Sarkar The Rise of Modern Wind Energy Wind Power for the World Published by Pan Stanford Publishing Pte. Ltd. Penthouse Level, Suntec Tower 3 8 Temasek Boulevard Singapore 038988 Email: [email protected] Web: www.panstanford.com British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. Foundation of Digital Electronics and Logic Design Copyright © 2015 Pan Stanford Publishing Pte. Ltd. All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permission from the publisher. For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to photocopy is not required from the publisher. ISBN 978-981-4364-58-4 (Hardcover) ISBN 978-981-4364-59-1 (eBook) Printed in the USA Contents Preface 1. Combinational Circuits 1.1 Introduction 1.2 Advantages of Digital System 1.3 Essential Characteristics of Digital Circuits 1.4Characteristic of an Ideal Digital Logic Element 1.5Definition of Truth Table and Various Logic Conventions 1.5.1 Logic Circuit 1.5.2 Logic Gate 1.5.3 Truth Table 1.5.4 Logical Convention 1.5.4.1 Positive Logic 1.5.4.2 Negative Logic 1.6 Number System 1.6.1 Positional Number System 1.6.2 Generalized Approach of Number System 1.6.3 Radix Conversion 1.6.4 Integer Conversion 1.6.5 Procedure for Integer Conversion 1.7 Logic Gates and Logic Circuits 1.7.1 OR Gate 1.7.2 AND Gate 1.7.3 NOT Gate 1.7.4 NOR Gate 1.7.5 NAND Gate 1.8 Logic Gates and Logic Circuits 1.8.1 X-OR Gate or Exclusive OR Gate 1.8.1.1 Parity 1.8.2 XNOR Gate or Equality Detector xv 1 1 3 3 7 8 8 8 8 9 9 10 10 10 11 13 13 14 16 16 17 17 18 19 20 20 22 24 vi Contents 1.9 Enable Inputs 1.10 OR Gate Using Diode Resistor Logic 1.11 Realization of an Inverter Using Transistor 1.12 Boolean Algebra and Its Postulates 1.13 Demorgan’s Theorem in Dual Form 1.13.1 Sum into product 1.13.2 Product into sum 1.14Simplification of Boolean Expressions by Using Boolean Algebra 1.15Logical Expression in SSOP and SPOS Form (Min and Max Term Form) 1.15.1 Min Terms 1.15.2 Max Term 1.16 NAND as a Universal Gate 1.16.1 NOT Gate from NAND 1.16.2 OR Gate from NAND 1.16.3 AND Gate from NAND Gate 1.16.4 NOR Gate from NAND gate 1.16.5 XOR Gate from NAND gate 1.16.6 XNOR Gate from NAND Gate 1.17 NOR as a Universal Gate 1.17.1 NOT Gate from NOR Gate 1.17.2 AND Gate from NOR Gate 1.17.3 OR Gate from NOR Gate 1.17.4 NAND Gate from NOR Gate 1.17.5 XOR Gate from NOR Gate 1.18 AND-OR Logic 1.19Gray Code and Binary to Gray Code Conversion 1.19.1 Gray Code 1.19.2 Binary Code 1.19.3 Binary to Gray Code Conversion 1.20 Karnaugh Map 1.20.1 Limitation 1.20.2 Plotting Zeros (Max Term Representation) 1.20.3 Five Variable K map 1.20.4 Six Variable K map 1.21Completely and Incompletely Specified Logic Functions 1.22Minimization of Incompletely Specified Logic Functions 1.23 K Map Consideration 26 26 28 28 30 30 30 31 32 36 36 37 37 38 38 39 39 40 40 40 40 41 41 41 42 44 44 44 45 45 45 53 53 54 60 61 64 Contents vii 1.24Digital Arithmetic Half Adder/Half Subtractor 1.24.1 Subtraction of Two Variables or Half Subtractor 1.25 Full Adder and Full Subtractor 1.26 Addition of Two n Bit Binary Numbers 1.26.1 Advantages of Serial Adder 1.26.2 Disadvantages of Serial Adder 1.27 n Bit Parallel Full Adder 1.28 Combinational and Sequential Circuit 1.28.1 Small Scale Integration 1.28.2 Medium Scale Integration 1.28.3 Large Scale Integration 1.28.4 Very Large Scale Integration 1.29Multiplexer Design Procedure and Applications 1.29.1 General Block Diagram 1.29.2 Advantage 1.29.3 Application of Multiplexer 1.29.4 Multiplexer as Universal Logic Gate 1.29.4.1 Realizing NOT gate by using 2 : 1 MUX 1.29.4.2 Realizing AND gate by using 2 : 1 MUX 1.29.4.3 Realizing OR gate by using 2 : 1 MUX 1.30 Demultiplexers and Their Applications 1.30.1 Application of Demultiplexer 1.31Decoder: Definition and Applications 1.31.1 Applications of Decoder 1.31.2 Application of Decoder (Example) 1.31.3 Cascading of Decoders 1.32 Seven Segment LED Display 1.32.1 Decoder for Active Low Output 1.32.2 Decoder for Active High Output 1.33 Decoder Driver IC and Its Application 1.33.1 Multiple Digit Decimal Display (4 Digits) 1.34 Encoder 1.35 Priority Encoder 1.35.1 Case 1 64 66 69 74 76 76 76 77 79 79 79 79 79 80 86 88 92 92 92 93 93 95 95 98 99 100 101 106 106 107 108 109 114 116 2. Sequential Circuit 119 2.1 Introduct ion 2.2 Definition of Combination and Sequential Circuits 119 120 viii Contents 2.3 2.4 2.5 2.6 2.7 2.8 2.2.1 Distinction between Combinational and Sequential Circuits 2.2.2 The Input–Output Relationship Flip-Flop Different Types of Flip-Flops and Their Application 2.4.1 S–R Flip-Flop 2.4.1.1 Unclocked/asynchronous S–R flip-flop 2.4.1.2 Synchronous or clocked S–R flip-flop 2.4.1.3 Advantages of clocked S-R flip-flop 2.4.2 Jack–Kibby Flip-Flop 2.4.2.1 To realize J–K flip flop from S–R flip-flop 2.4.3 Clocked J–K Flip-Flop 2.4.4 D–Flip-Flop 2.4.5 T–Flip-Flop 2.4.5.1 Realization of flip flop from D and J–K flip-flop Flip-Flop Used as a Divider Circuit 2.5.1 Conclusion Racing Problem Master–Slave Clock 2.7.1 Input Circuit of a Positive Edge Triggered 2.7.2 Operation of J–K Master–Slave Flip-Flop Counters 2.8.1 Modulus of a Counter 2.8.1.1 Mod 3 nonbinary counter 2.8.2 Design of Counter 2.8.2.1 Lock out condition 2.8.2.2 Design procedure for synchronous counter 2.8.3 Decoding Error in Counter 2.8.3.1 Designing of mod 4 up down counter 2.8.3.2 Cascading of counter 2.8.3.3 Designing mod 87 counter 120 121 122 123 123 125 126 126 127 127 129 130 131 132 134 135 136 138 140 140 141 143 144 144 145 149 153 167 168 171 3. Memory 175 3.1 Computer Memory 3.2 Classifications of Memory 3.2.1 Semiconductor Memories 175 175 176 Contents ix 3.3 3.4 3.5 3.6 3.7 3.8 3.2.2 Magnetic Based Memory 3.2.3 Optical Medium Based Memories 3.2.4 Main or Primary Memory 3.2.4.1 Classification of primary memory 3.2.4.2 Random access memory 3.2.4.3 Read only memory 3.2.5 Secondary or Auxiliary Memory 3.2.5.1 Definition of secondary memory 3.2.6 Secondary Storage Devices 3.2.6.1 Hard disk 3.2.7 Backup Memory 3.2.7.1 Floppy disk 3.2.7.2 Magnetic tapes 3.2.8 Cache Memory 3.2.9 Virtual Memory 3.2.10 Memory Devices System Memory and Standard Memory Devices 3.3.1 Advantages of System Memory Device 3.3.2 Disadvantages of System Memory Devices 3.3.3 Standard Memory Device Different Semiconductor Memories 3.4.1Advantages and Disadvantages of Bipolar Static R/W Memory 3.4.2 Advantages of Static MOS RAM 3.4.3 Dynamic MOS RAM 3.4.3.1 Advantages of DRAM 3.4.3.2 Disadvantages of DRAM Memory Organization Bit and Byte Organized Memory Different Memory Chips 3.7.1 Optical Windows Different Types of ROM 3.8.1 Read Only Memory 3.8.2 Programmable Read Only Memory 3.8.3 Erasable Programmable Read Only Memory 3.8.3.1 Disadvantages of EPROM 3.8.3.2 Advantages of EPROM 3.8.4 Electrically Alterable PROM 177 177 177 178 178 179 179 179 179 179 180 180 181 181 181 182 182 183 183 183 184 185 185 186 186 187 187 188 189 190 191 191 192 192 192 192 192 x Contents 3.8.4.1 Advantages of EAPROM 3.8.4.2 Disadvantages of EAPROM 3.8.5 Applications of ROM 3.9 Ferrite Core Memories 3.9.1 Disadvantages of Ferrite Core Memories 3.10 Compact Disc-Read Only Memory 3.10.1 Main Advantages of CDROM 3.10.2 Main Disadvantages of CDROM 3.10.2.1 Constant linear velocity 3.11 ROM by Using Decoder and Gates 3.12 Function of 74189 RAM and 74288 PROM Chip 3.12.1 Operation 3.12.1.1 Write operation 3.12.1.2 Read operation 3.13 Method of RAM Testing on a PC 3.13.1 Memory Interfacing 3.14 Memory Interfacing by Fully Decoded Addressing 3.14.1 Advantages 193 193 193 194 194 194 195 195 195 195 197 198 198 199 199 200 201 202 4. Timing Circuit 205 4.1 Introduction 4.2 Multivibrators 4.2.1 Astable Multivibrator 4.2.2 Monostable Multivibrator 4.2.3 Application 4.3 555 Timer 4.3.1 Astable Mode Operation 4.3.1.1 Generation of symmetrical waveform using J–K flip-flop (without using diode) 4.3.2 Monostable Mode Operation 4.4 Monostable Multivibrator Using Logic Gate 4.5Generation of Timing Waveform Using OP-AMP 4.5.1 Generation of Symmetric Waveform 4.5.2 Generation of Asymmetric Waveform 4.6 Registers and Types of Registers 4.6.1 Serial In Serial Out Scheme 4.6.2 4 Bit Serial In Serial Out Shift Register 4.6.3 Serial In Parallel Output 205 205 206 207 207 207 209 213 213 215 216 217 219 220 221 221 222 Contents xi 4.6.4 Parallel In Parallel Out Operation 4.6.5 Parallel In Serial Out 4.6.6 Bidirectional Shift Register 4.6.7 74194 IC (4 Bit Universal Shift Register) 4.7 Ring Counter and Johnson Counter 4.7.1 4 Bit Ring Counter 4.7.2 Johnson Counter 4.7.2.1 Advantages 4.8 Multiplexer as a Parallel In Serial Out Register 4.9 Application of Register 4.9.1 Advantage 4.9.2 Disadvantage 4.9.3 Applications of Registers 4.10 Design of a Sequence Generator 4.11 Error Detection and Correction Codes 4.11.1 Parity Check Error Detection Scheme 4.11.2 Block Parity 4.11.3 Hamming Code 4.11.4 Checksum Method 4.11.5 Cyclic Redundancy Code 4.12 Display Devices 4.12.1 Light Emitting Diode 4.12.1.1Advantages of LED 4.12.1.2Disadvantages of LED 4.12.2 Laser 4.12.3 Liquid Crystal Display 4.12.3.1Dynamic scattering type 4.12.3.2Field effect type 4.12.3.3Advantages of LCD over LED 4.12.3.4Disadvantages of LCD 222 223 224 225 227 227 228 229 229 230 231 231 231 232 234 235 235 236 239 240 240 240 241 242 242 242 243 243 245 245 5. Logic Family 247 5.1 Introduction 5.2 Logic Parameters 5.2.1 Propagation Delay 5.2.2 Power Dissipation 5.2.3 Average Supply Current 5.2.4 Speed Power Product 247 248 248 249 249 250 xii Contents 5.2.5 Fan-In and Fan-Out 5.2.6 Noise Margin 5.3 Resistor Transistor Logic 5.4 Diode Transistor Logic 5.4.1 Calculation of the Minimum Forward Current Ratio for Transistor Q 5.4.2 Noise Voltage with Negative Polarity 5.4.3 Propagation Delay 5.4.4 Modified DTL 5.5 High Threshold Logic 5.6 Transistor Transistor Logic 5.7 Totem Pole 5.8 Open Collector Output 5.8.1 TTL Families 5.8.2 Advantages of Totem Pole Output 5.8.3 Disadvantages of Totem Pole Output 5.9 Wire and Logic for Open Collector TTL 5.9.1 Modified Totem Pole Circuit 5.10 Tristate TTL Inverter 5.11QUAD D-Type F/F with Tristated Output (74LS373) 5.12 Integrated Injection Logic 5.12.1 Advantages 5.12.2 Disadvantage 5.12.3 IIL Inverter 5.12.4 IIL NAND and NOR Gate 5.13 Emitter Coupled Logic 5.13.1 Characteristics of ECL Logic Family 5.13.2 Advantages of ECL 5.13.3 Disadvantages of ECL 5.14 Wired-OR Connection of ECL Logic 5.15 Wired OR MOS Logic Family 5.15.1 N-MOS Inverter 5.15.2 Two Input N-MOS NAND and NOR Gates 5.15.3 Characteristics of MOS Logic 5.16 Complementary MOS Logic 5.16.1 Advantages 5.16.2 Disadvantages 5.16.3 CMOS as Inverter 5.16.4 Two Input NAND using CMOS 250 250 251 252 253 254 255 256 258 259 260 262 262 263 263 263 264 265 266 267 267 267 267 268 269 271 271 271 271 272 272 274 275 276 276 276 276 277 Contents xiii 5.16.5 CMOS Series 5.16.6 Bi CMOS Series 5.17 Comparison of Logic Families 5.17.1 High Level DC Noise Margin 5.17.2 AC Noise Margin 5.17.2.1 Fan-out 5.17.3 Output of a TTL gate 5.18 Major Comparative Features of Various Logic Families 5.18.1 Gates of TTL Logic Family 5.18.2 Gates of ECL Logic Family 5.18.3 Gates of NMOS Logic Family 5.18.4 Gates of IIL Logic Family 5.18.5 Gates of CMOS Logic Families 278 278 279 281 281 283 283 6. Application 289 6.1 Introduction 6.2 Digital to Analog Converter 6.2.1 Disadvantages of W‑R DAC 6.2.2 The R-2R Ladder Type DAC 6.2.3 Advantage 6.3 8 Bit D/A Counter IC DAC 0808/DAC 1408 6.4 Bit Arithmetic and Logic Unit (74181) 6.5 Carry Look Ahead Adder 6.6 Analog to Digital Converter 6.6.1 Sample and Hold Circuit 6.6.2 Sampling Pulse 6.7 A/D Converter Types 6.7.1 2 Bit Parallel/Simultaneous Type ADC 6.7.2 A/D Converter 6.7.2.1 Disadvantage 6.7.3 Counter Type ADC (3 bit CTADC) 6.7.3.1 Disadvantage 6.7.4 Dual Slope A/D Converter 6.8Microprocessor Compatible A/D Converter 0809 6.9 Specifications of D/A Converter 6.9.1 Resolution 289 289 295 295 300 301 302 306 309 310 310 313 313 314 315 316 316 319 284 284 284 285 286 286 322 324 324 xiv Contents 6.9.2 Linearity of a DAC 6.9.3 Accuracy 6.9.4 Settling Time 6.9.5 Temperature Sensitivity 6.10 Specification of A/D Converter 6.10.1 Input Voltage Range 6.10.2 Input Impedance 6.10.3 Conversion Time 6.10.4 Format of ADC 6.10.5 Accuracy 6.10.6 Stability or Temperature Sensitivity 6.11 Applications of Counters 6.11.1 Generation of Square Wave by ZCD 6.11.2 Counter Application 6.11.2.1 Velocity of a Counter 6.11.3 Automatic Parking Control System 6.12 Schmitt Trigger Circuit 6.12.1 Applications 6.12.2 Transistorized Schmitt Trigger Circuit 6.12.3 Characteristics of Schmitt Trigger Circuit 6.13 Schmitt Trigger Using OP-AMP 6.13.1 Characteristics 6.14 Digital ICs and Characteristics 6.14.1 How to Identify a Digital IC 6.15 Programmable Logic Array 6.15.1 General Architecture of PLA 6.16 Charge Coupled Device 6.16.1 Main Advantages 6.17 Binary Multiplication and Division Algorithm 6.18Booth’s Multiplication Algorithm 6.18.1 Algorithm 325 325 326 326 327 327 327 327 327 327 328 328 329 330 330 331 332 332 332 334 336 336 339 340 340 342 346 346 347 350 350 Index 355 Preface The present treatise is meant to be a textbook for undergraduate students in electrical engineering, electronics and communication engineering, computer science, and information technology. It is also expected to be useful to the students of other disciplines studying basic courses on electronics. It covers the basic principles of digital electronics and logic design. This textbook is an outgrowth of the lectures we have delivered to our students over several years and covers the syllabi of many universities across the globe. It will help in bridging the gap between digital electronics and logic design. Topics have been illustrated with the help of many diagrams to make the students grasp the subject in a better manner. The subject matter is dealt with a clear and concise way with many examples, and a large number of problems have been worked out to make acquaint students with the applications of the principles and formulae they have encountered in the text. If the contents of the present book prove useful to those for whom it is intended, we will deem our effort amply rewarded. We will thankfully receive constructive suggestions for the improvement of the book. We acknowledge gratefully the encouragement given by our colleagues and students, whom we have taught over the past several years, for their thought-provoking questions, which have really helped us to clear our thoughts and have enabled us to develop simple explanations to complex-looking theories. We wish to thank the editorial and production team at Pan Stanford Publishing for the meticulous processing of the manuscript. Subir Kumar Sarkar expresses his particular appreciation to his research scholars Mr. Suman Basu, Mr. Amit Jain, Mr. Pranab Kishore Dutta, xvi Preface Mr. Bijoy Kantha, Mr. Rashmi Ranjan Sahoo, Mr. Bibhas Manna, Mr. Subhashis Roy, Ms. Gargee Bhattacharyya, Mrs. Saheli Sarkhel Ganguly and Mrs. Jayashree Bag for their skillful service in preparing the manuscript. Subir Kumar Sarkar Asish Kumar De Souvik Sarkar