Steady-State Operation

1.1 ZVZCS-FB-PWM principle
ZVS-FB-PWM轉換器的架構
ZVZCS-FB-PWM 轉換器的操作波形
Mode 1: QA及QD 導通，輸入功率經由變壓器而傳至負載端。在此模式期間，阻隔電容器Cb兩端電壓從負的
最大值呈線性增加。
Vin
A
i
Tr
B
C
C1
D
Mode 2: QA截止，變壓器㆒次側電流I對QA的輸出電容CA充電，對QB的輸出電容CB放電，接著㆓極體DB
導通(QB的反向並接㆓極體)。其㆗QB能夠以完全的ZVS方式導通。
Vin
A
C
i
Tr
B
C1
D
Mode 3:在QB開始導通時，反流器之輸出電壓
Mode 4:當變壓器在㆒次側電流I降到零值時，
VAB 被拑制為零值，此時與輸入電壓源Vi相比， 其會有往負值方向增加的變動傾向。阻隔電容器
其值非常小之阻隔電容器Cb兩端的電壓，則施
Cb㆖的電壓完全施加在Lik及變壓器的㆒次側㆖，
加在漏電感Lik㆖。阻隔電容器Cb可視為定電壓
使㆒次側的電流I繼續保持為零值。在此期間Cb的
源，變壓器㆒次側電流I呈線性㆘降而達到零值。 電壓保持定值，QD仍然為導通的狀態，但是沒
有電流流過。
Vin
A
Tr
B
C
i
C1
D
Mode 5: QD完全以ZVS及的操作方式截斷，此時變壓器㆒次側為開路狀態。
Vin
A
i
Tr
B
C
C1
D
Mode 6: 在QC導通後，因為高電壓施加到漏電感Lik㆖，使變壓器㆒次側電流I呈線性增加。至此則完成㆒個
操作週期。
Vin
A
C
i
Tr
B
C1
D
1.2 Meansurement of primary side
Object: Primary side waveform of OZ960, MosFET and Transformer test report
Conditions:
Operation frequency: 60KHz
Ambient temperature: 24°C
Panel: LG 14.1” TFT XGA, model: LP141XA-D1AP
Scope: Tektronix TDS 360, S/N: A1003
Current probe: Tektronix P6022, S/N: B1006
Power supply: GW GPC-3030D, S/N: A1011
Thermal tester: OPTEX PT-3S, S/N: A1010
Test Item:
1. OZ960 output waveform
2. MosFET output waveform
3. Transformer Primary side voltage and current waveform
Test result:
1. In Fig A, The switches of MosFET A, B, C and D are configured such that MosFET A
and B, C and D are turned on complementarily. The duration of A and D, B and C turn
on simultaneously determines an amount of energy put into the transformer. When B
and D shift left simultaneously, the duty cycle become short.
2. In Fig B. The third waveform is a mathematical waveform from V_AB-V_CD which
V_AB is Drain of MosFET A, B and V_CD is Drain of MosFET C, D. It equal Vc add
transformer primary voltage as fourth and fifth waveform.
3. Fig C is show the timming of OZ960 output waveform and primary side of
transformer.
Fig A
Fig B
Fig C
2. OZ960 function description
CTIMR:
Capacitor for CCFL ignition duration
Determine the necessary striking time. An approximate of the timing calculation is:
T[second]=C[uF]
OVP:
This capacitor remains reset at no charge if lamp is connected and at normal operation.
Output voltage sense Vth=2.0V
It ensures that output gets sufficient striking voltage while operating the power transformer
safely.
Protection
Open-lamp protection in the ignition period is provided through both OVP and CTIMR to ensure
a rate voltage is achieved and a required timing is satisfied. Removal of the CCFL during normal
operation will trigger the current amplifier output and shuts off the inverter. This is a latch
function.
2
C8
3
4
1.0U
5
6
7
8
9
NDRV_B
OVP
PDRV_A
ENA
CT
SST
VDDA
GNDA
REF
RT1
RT
PWRGND
LCT
DIM
LPWM
FB
PDRV_C
CMP
NDRV_D
20
19
+
18
CN1
C6
1
T1
17
Vo'
16
Vo
15
14
2
C14
-
13
12
11
1
10
CTIMR
OZ960
1
OZ960/SSOP20
2
CR2
R14
3
C7
U2
1. C8 is control striking time. Stricking time[second ] = C8[uF].
When output is open, the voltage of OVP is over than 2V then the CTIMER start to account striking time.
2. The OVP threshed is set at 2V. Output voltage is set by C6 and C14. The Vo is calculated as:
V o' =
C6
× VO
C 6 + C 14
V o' = 2 + D i o d e d r o p v o l t a g e
Vo =
Vo =
C
6
C
6
≅ 2 .8
+ C 14
× V o'
C6
+ C 14
× 2 .8
C6
a.
1. t: 0~t1
Vout = Vin = Vm
b.
2. t: t1~t2
Vout = −VD
VC = −Vm + VD
3. t: t2~t3
Vout = Vin − VC = 2Vm − VD
c.
VL = VM ⋅ e −T / RC
if → RC >> T
⇒ VL = VM
⇒ Vout = VM = V − VD
d.
Vout = Va(max ) − VD = 2V '−2VD
⇒ 2V ' = Vout + 2VD
C1
ΘV '=V
C1 + C 2
C1
∴ 2V ' = 2V
= Vout + 2VD
C1 + C 2
C1 + C 2
⇒ VH ( p − p ) = 2V = (Vout + 2VD )
C1
ENA:
Enable input; TTL signal is applicable
ON/OFF
2
3
4
C9
5
6
7
8
9
10
20
CTIMR
NDRV_B
OVP
PDRV_A
ENA
CT
SST
VDDA
GNDA
REF
OZ960
1
R15
RT1
19
RT
LCT
DIM
LPWM
PDRV_C
CMP
NDRV_D
OZ960/SSOP20
17
16
PWRGND
FB
18
15
14
13
12
11
U2
R15 and C9 recifier the noise from ON/OFF. When VENA>1.5V, the IC will be turn on.
Soft-start capacitor
The soft-start time is not related to the striking time for the CCFL. It simply provides a rate of rise
for the pulse width where diagonal switches are turned on. Normally, a 0.47uF capacitor is
connected.
1
2
3
4
C10
5
6
7
8
9
10
CTIMR
NDRV_B
OVP
PDRV_A
ENA
CT
SST
RT
VDDA
GNDA
REF
OZ960
SST:
RT1
Voltage source for the IC
LCT
DIM
LPWM
FB
PDRV_C
CMP
NDRV_D
OZ960/SSOP20
VDDA:
PWRGND
U2
20
19
18
17
16
15
14
13
12
11
5V
2
3
4
5
6
C11
7
8
9
10
CTIMR
NDRV_B
OVP
PDRV_A
ENA
CT
SST
VDDA
GNDA
REF
OZ960
1
R16
RT
PWRGND
LCT
DIM
RT1
LPWM
FB
PDRV_C
CMP
NDRV_D
OZ960/SSOP20
20
19
18
17
16
15
14
13
12
11
U2
R16 and C11 is recifier circuit, it supply stable voltage for OZ960 VDDA.
GNDA:
Analog signal ground reference
REF:
Reference voltage output; 2.5V typical
FB:
CCFL current feedback signal
CMP:
Compensation output of the current error amplifier
The CCFL current is regulated through this error amplifier. The non-inverting reference is at
1.25V nominal.
2
3
CTIMR
ND RV_B
OVP
PD RV_A
EN A
4
SST
5
VD DA
6
GN DA
7
REF
8
OZ960
1
RT1
9
10
CT
RT
PWR GN D
LCT
DI M
LPWM
FB
PD RV_C
CMP
ND RV_D
20
19
C3
18
17
16
15
14
C5
short
CN 1
C6
2
30:2200
CI UH8D 42
13
SM02B-BH SS-1
C14
0.033U
T1
12
3
11
1
CR 1
BAV99L
C13
OZ 960/SSOP20
U2
2
C12
1
22P,3KV
2.2U,X5R,6.3V
R17
R13
The feedback loop is determine output current. The output current is calculated as:
1.25V =
2
π
I lamp ( rms ) =
× R13 × I lamp ( rms )
1.25
0.45 × R13
If there is a diode on the Feedback loop. The output current is calculated as:
1.25V = Va (dc ) =
Vm
1
(
2 ⋅ I rms ⋅ R 21 − VD
π
π
⇒ 1.25 = 0.45I rms ⋅ R 21 − 0.318VD
1.25 + 0.318VD
⇒ I rms =
0.45 ⋅ R 21
DIM:
LCT:
Low-frequency PWM signal for burst-mode dimming control
Triangular wave for burst-mode dimming control
=
)
Vdim
2
3
4
CTIMR
NDRV_B
OVP
PDRV_A
ENA
CT
SST
5
VDDA
6
GNDA
7
REF
8
OZ960
1
RT
PWRGND
LCT
DIM
RT1
9
10
LPWM
FB
PDRV_C
CMP
NDRV_D
OZ960/SSOP20
20
19
18
17
16
C17
15
14
13
12
11
U2
R20
OZ960 integrates a burst-mode dimming function to perform a wide dimming control for the CCFL.
The burst mode frequency is set by C17,
f [ Hz ] =
1490
C17 [nF ]
The ramp peak of burst mode triangle is 3V and ramp valley is 1V. We can adjust Vdim to control LPWM
duty cycle.
PGND:
RT1:
RT:
CT:
Power ground reference
Resistor for programming ignition frequency
Timing resistor set operation frequency
Timing capacitor set operating frequency
Operating frequency
A resistor RT and a capacitor CT determine the operating frequency of OZ960. The frequency is
calculated as:
2
3
4
5
6
RT
R22
7
8
R
9
10
CTIMR
NDRV_B
OVP
PDRV_A
ENA
CT
SST
VDDA
GNDA
REF
OZ960
1
RT
PWRGND
LCT
DIM
RT1
LPWM
FB
PDRV_C
CMP
NDRV_D
OZ960/SSOP20
20
19
C18
18
17
16
15
RT
R21
14
13
12
11
U2
R21 and C18 determine the operation frequency. The frequency is calcuated as:
70 • 104
f H [kHz ] =
C18 [ pF ] • R21 [k Ω]
OZ960 also provide an optional striking frequency as desired.
Striking frequency
When R22 is used, it is connected in parallel with R21 during the ignition period.
The frequency is calcuated as:
f S [kHz ] =
70 • 104
C18 [ pF ] • RS [k Ω]
which
RS = R21 // R22
Because operation frequency is known number, C18 and R21 are constant.
Than
NDR_B:
NDR_D:
PDR_A:
PDR_C:
R22 [k Ω] =
70 • 104 • R21 [k Ω]
f S [kHz ] • C18 [ pF ] • R21 [k Ω] − 70 • 104
NMOSFET drive output
NMOSFET drive output
PMOSFET drive output
PMOSFET drive output
which
fS > fH
Vin
D3
R19
P-mosf et' gate
2
3
4
5
6
7
8
9
10
CTIMR
NDRV_B
OVP
PDRV_A
ENA
CT
SST
RT
VDDA
GNDA
REF
OZ960
1
RT1
PWRGND
LCT
DIM
LPWM
FB
PDRV_C
CMP
NDRV_D
OZ960/SSOP20
20
C15
19
18
17
16
Vin
15
14
13
D4
C16
R18
P-mosf et' gate
12
11
U2
D3, C15, R19 is a level-shift circuit, because OZ960’ supply voltage is +5V, the output of PDR is 5V, but
the PMOS is switched by Vin (>5V), so the PDR must be shifted.
How to selection the value of R and C?
The RC should be large more than T.
1. If RC >> T, the waveform will be fine.
2. If RC is not large enough, the waveform will be distortion.
a. C is small.
b. R and C are small.
3. Zener diode is removed.
4. Zener diode is replacement by diode.
Transformer turn ration design
550
N1
N2
C
RL
If input voltage range is from 9V~21V, we can assume max duty is 83%. And max. Duty cycle happen at input voltage
8V.
8V
-0.41
0.41
-8V
Input voltage through H Bridge, We get input voltage waveform of transformer as above figure.
We also assume output voltage of lamp is 550V
We can get R.M.S value.
8 2 × 0.41 + (−8) 2 × 0.41
= 8 2 × 0.82 = 8 × 0.82 = 7.24V
1
If we use transformer which TOKO BLX103B, secondary of transformer is 1500N.
Vo N 2
550 1500
=
→
=
V1 N 1
7.24
N1
N 1 = 7.24 *1500 / 550
N 1 ≅ 19
The equation is not really exact; Actually tolerance is about
calculate transformer magnetic current and core loss.
± 15%. So it need to fine tune, because we can not
3. Simulation and Analysis of OZ960 inverter
Functional information
3.1 Rectifier circuit
3.2 Enable circuit
3.3 Soft-start circuit
3.4 Level shift circuit for drive the P-MOSFET’s gate
3.5 Striking time and OVP control circuit
3.6 Feedback loop
3.7 Triangle circuit
3.8 Burst-mode circuit
Functional information
3.1 Rectifier circuit
If Vin=12V
Then VA=5.6V
VDDA= VA – VBE =5.0V
Spec. VDDA=4.7V~5.5V
Pspice Simulation:
3.2 Enable circuit
R8 and C8 rectifier the noise from ON/OFF, when ENA>1.5V the IC will
be turn on.
C8 charge from 0 to 1.5V need 0.6ms, it is delay time from ON/OFF to H.
3.3 Soft-start circuit
Normally, a 0.47uF capacitor is connected.
3.4 Level shift circuit for drive the P-MOSFET’s gate
PSpice Simulation:
3.5 Striking time and OVP control circuit
Striking time T[second]=C9[uF]
VO ' =
C4
× VO
C4 + C6
VO ' = VOVP + VD ≅ 2.8V
VO =
C6 + C4
× VO '
C4
VO =
12 p + 18n
× 2.8 = 4202.8V p − p
12 p
Pspice Simulation:
VAMPL V5=2500V/60kHz
VB ×
C1
= VOVP + 2VD
C1 + C2
VB =
C1 + C2
(VOVP + 2VD )
C1
C1 ≅
C2 (VOVP + 2VD )
VB
C2 ≅
C1VB
VOVP + 2VD
3.6 Feedback loop
Pspice simulation:
Vout =
2
π
⋅ R 2 ⋅ I R 2 (rms ) − 0.318VD
IR 2(rms ) =
VAMPL V1=1800V/60kHz
VFB + 0.318VD
0.45 ⋅ R 2
3.7 Triangle circuit
Operation frequency
f H [kHz ] =
700000
700000
=
= 51.3[kHz ]
C7 [ pF ] • R9 [k Ω] 220 × 62
Striking frequency
RS = R9 // R11 = 55.3k Ω
f S [kHz ] =
700000
700000
=
= 57.5[kHz ]
CT [ pF ] • RS [k Ω] 220 × 55.3
3.8 Burst-mode circuit
Brightness is negative dimming control.
f L [ Hz ] =
1490
1490
=
= 219[ Hz ]
C12 [nF ]
6.8
1. If R2 is known, then
R4 =
R5 =
R2VDD (VDimH − VDimL )
VadjH VDimL − VadjLVDimH
R2 (VDD
R2 R4VDimL
− VDimL ) − R4 (VDimL − VadjL )
2. If R4 is known, then
R2 =
R5 =
VadjH VDimL − VadjLVDimH
VDD (VDimH − VDimL )
R2 (VDD
• R4
R2 R4VDimL
− VDimL ) − R4 (VDimL − VadjL )
Lamp current = 3.5mA~8.0mA
VDIM = 0.9V~2.1V
duty-cycle = 43%~100%
5 − 2.1 5 − 2.1 2.1
+
=
R4
R2
R5
5 − 0.9 0.9 0.9
=
+
R4
R2
R5
If R2=270K then
R4=360K and R5=111.7K choose 100K
4. Measurement and Verification of OZ960 inverter
4.1 Measurement of waveform of OZ960 inverter
Functional information
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Signal waveform of ENA, CTIRM, OVP, SST, FB and CMP
Waveform of OZ960 pin LPWM and FB
Vadj vs. Striking voltage at open lamp
OVP loop experiment
Vin, Duty-cycle and lamp voltage relational
4.1.1.a OZ960 signal waveform of ENA, CTIMR, OVP, SST, FB and CMP at open lamp
state when Vadj=3.4V.
Vin=8.9V
Vin=12V
Vin=16V
Vin=19V
Vin=21V
4.1.1.b Normally OZ960 signal waveform of ENA, CTIMR, OVP, SST, FB and CMP
Vin=12V, Vadj=0V.
Vin=19V, Vadj=0V.
4.1.1.c Normally OZ960 signal waveform of ENA, CTIMR, OVP, SST, FB and CMP
Vin=12V, Vadj=3.4V.
Vin=19V, Vadj=3.4V.
4.1.2 Waveform of OZ960 pin LPWM and FB
LPWM pin of OZ960
FB pin of OZ960
4.1.3 Vadj vs. Striking voltage at open lamp condition
I. Vin=8.9V
1.Vadj=0V
2. Vadj=3.4V
II. Vin=12V
1.Vadj=0V
2. Vadj=3.4V
III. Vin=16V
1.Vadj=0V
2. Vadj=3.4V
IV. Vin=21V
1.Vadj=0V
2. Vadj=3.4V
Striking voltage waveform fix Vadj=3.4V
1. Vin=8.9V
2. Vin=12V
3. Vin=16V
4. Vin=21V
4.1.4 OVP loop experiment
a. Change C6 from 33nF to 22nF
C5=22pF, C6=22nF
C6 + C5
22n + 22 p
VO =
× (VOVP + 2VD ) =
× (2 + 2 × 0.5) = 3003VP − P
C5
22 p
Vin=12V
b. Change C5 from 22pF to 33pF
C5=33pF, C6=33nF
C + C5
33n + 33 p
VO = 6
× (VOVP + 2VD ) =
× (2 + 2 × 0.5) = 3003VP − P
C5
33 p
Vin=12V
c. Change C5 from 22pF to 27pF
C5=27pF, C6=33nF
C + C5
33n + 27 p
VO = 6
× (VOVP + 2VD ) =
× (2 + 2 × 0.5) = 3670VP − P
C5
27 p
Vin=12V
d. Change C5 from 22pF to 18pF
C5=18pF, C6=33nF
VO =
C6 + C5
33n + 18 p
× (VOVP + 2VD ) =
× (2 + 2 × 0.5) = 5503VP − P
C5
18 p
Vin=12V
4.1.5 Vin, Duty-cycle and lamp voltage relational
Vin=8.9V, Duty-cycle=54.8%
Vin=12V, Duty cycle=36.9%
Vin=16V, Duty cycle=26.2%
Vin=21V, Duty cycle=21.4%
Vin (V) Frequency (kHz) Duty cycle(%) Vlamp (kVp-p) Vlamp (Vrms)
9
56.6
54.8
1.26
401
12
57.5
36.9
1.32
407
16
57.1
26.2
1.38
413
21
57.1
21.4
1.4
418
4.2 Functional test of OZ960 inverter
Conditions:
Inverter: IV10101/T
Ambient temperature: 24°C
Panel: LG 14.1” TFT XGA, model: LP141XA-D1AP
Scope: Tektronix TDS 220, S/N: A1004
Power supply: GW GPC-3030D, S/N: A1011
LCR meter: Zentech 100 LCR METER
Multi-meter: HP 34401A, S/N: A1001
Thermal tester: OPTEX PT-3S, S/N: A1010
Test Item:
4.2.1 Vdim vs. Ilamp
4.2.2 Vcc vs. Ilamp
4.2.3 Operation frequency vs. Ilamp
4.2.4 Burst frequency vs. Ilamp
4.2.5 Relationship between Vlamp and FB signal
Test result:
4.2.1Vdim vs. Ilamp
Condition: Vcc=12V, fH=57.4KHz, fBurst=150Hz
Vdim(V)
Iin(A)
Ilamp(mA)
4.0
0.37
5.60
2.0
0.22
4.01
0.1
0.08
2.11
4.2.2 Vcc vs. Ilamp
Condition: Vdim=4.0V, fH=57.4KHz
Vcc(V)
Iin(A)
Ilamp(mA)
9
0.50
5.56
12
0.37
5.61
16
0.27
5.62
19
0.23
5.62
Condition: Vdim=2.0V, fH=57.4KHz
Vcc(V) DutyVlamp (%) t1/T(%)
Iin(A)
9
70.46
58.47
0.28
12
68.37
59.67
0.21
16
68.07
61.77
0.16
19
66.57
62.37
0.14
*t1: Vlamp except rise and fall time.
DutyLPWM (%) Ilamp(mA)
30.26
4.02
30.26
4.14
30.26
4.25
30.26
4.28
Vcc=9V
Vadj=2.0V
Vcc=12V
Vadj=2.0V
Vcc=16V
Vadj=2.0V
Vcc=19V
Vadj=2.0V
Condition: Vdim=0.1V, fH=57.4KHz
Vcc(V) DutyVlamp (%) t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA)
9
32.08
20.69
0.09
69.2
2.03
12
29.09
21.29
0.08
69.1
2.28
16
26.99
21.60
0.06
68.9
2.42
19
26.09
22.19
0.05
68.7
2.47
*t1: Vlamp except rise and fall time.
Vcc=9V
Vadj=0.1V
Vcc=12V
Vadj=0.1V
Vcc=16V
Vadj=0.1V
Vcc=19V
Vadj=0.1V
4.2.3 Operation frequency vs. Ilamp
Condition: Vdim=4.0V, Vcc=12V
fH (KKz)
Iin(A)
Ilamp(mA) Tr.Duty(%)
RT(KΩ)
37.3
82
0.35
8.54
49.5
62
0.36
5.65
54.45
57.4
53.6
0.36
5.62
45.24
65.15
47
0.38
5.60
41.69
* There is an unstable output current, when frequency at 37.3kHz.
4.2.4 Burst frequency vs. Ilamp
Condition: Vcc=12V, Vdim=2.0V
fBurst (Hz) CLCT(nF) DutyVlamp (%)
150
10
68.37
224
6.8
66.98
307
4.7
68.10
fBrust=150Hz
t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA)
59.67
0.22
30.26
4.12
54.34
0.20
30.45
3.86
51.07
0.19
33.54
3.36
fBrust=224Hz
fBrust=307Hz
Condition: Vcc=12V, Vdim=0.1V
fBurst (Hz) CLCT(nF DutyVlamp (%)
)
150
10
30.12
224
6.8
29.12
307
4.7
27.36
fBrust=150Hz
fBrust=307Hz
t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA)
20.99
18.37
11.55
0.08
0.06
0.03
fBrust=224Hz
68.98
69.09
69.72
2.21
1.71
0.51
4.2.5 Relationship between Vlamp and FB signal
a. (fLPWM=150Hz, T=6.67ms), Vadj=1.5V
Vin(V) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)
9
320
520
48.58
1.90
12
240
340
50.07
1.92
16
160
240
51.27
1.92
19
140
200
50.67
1.94
Vin=9V
Vin=12V
Vin=16V
Vin=19V
b. Vin=12V, Vadj=1.5V, (fLPWM=150Hz, T=6.67ms)
R13(KΩ) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)
13
200
80
47.08
1.91
33
240
340
50.07
1.92
47
270
1320
55.62
1.91
R13=13KΩ
R13=47KΩ
R13=33KΩ
c. Vin=12V, Vadj=1.5V, (fLPWM=150Hz, T=6.67ms)
R15(KΩ) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)
33
170
1720
58.62
1.91
51
240
340
50.07
1.92
75
340
240
42.28
1.91
R15=33KΩ
R15=75KΩ
d. Vin=12V, Vadj=1.5V
R13(KΩ) R15(KΩ) Rise(us)
47
75
380
21
33
180
R13=47KΩ
R15=51KΩ
Fall(us)
440
200
D(t1/T)(%)
44.68
53.67
R13=21KΩ
Vp-p(kV)
1.9
1.9
R15=75KΩ
R15=33KΩ
4.3 Transformer turn rate
Input voltage range is 9V to 21V, we assume max. duty cycle is 84%. And max. duty
cycle happen at input voltage 8V. The output voltage of lamp is 450Vrms.
We can get the R.M.S. value.
82 × 0.42 + (− 8) × 0.42
= 82 × 0.84 = 7.33V
1
2
If the secondary turns of transformer is 2200.
Vo N 2
450 2200
=
⇒
=
V 1 N1
7.33
N1
⇒ N 1 ≅ 35
Actually tolerance is about ±15%.
Actually test,
1. N1:N2=30:2200
2. If the input voltage is lower than 8.9V inverter can’t turn on.
3. When inverter is normally work then start decrease input voltage, it will shut-down
while input voltage is 8.4V and the duty cycle is 80%.
Conclusion
Switching
topology
Output-Wave
form
O2 (OZ960)
TI1451
Remark
PWM:
Zero-Voltage-Swit
ching (ZVS)
Royer: Self
Exciting
O2: PWM-ZVS is controlled
by O2 chip. ( quite stable).
TI1451: Oscillation frequency
is controlled by transformer.
Very Good
Medium
O2: ZVS-Phase-Shift Control,
Output waveform is almost
sine and symmetry is very
good.
TI1451: Waveform is most
likely as triangle.
Variable –Freque O2: Designer can easy to
Operating
ConstantFrequency
Frequency(Easy ncy (Not easy to decide the optimized
operation frequency for
control).
to control)
panels.
TI1451: Operating frequency
is decided by oscillated
capacitor, primary inductance
of transformer, and the
equivalent load from the load
of secondary side of
transformer. The operating
frequency is not easy to
design and operating
frequency is easy to change
when panel dimming is
changed.
Working with
Very Good
Good
O2: Transformer uses two
transformer
windings.
Transformer
easy to manufacture.
TI1451: Transformer needs
four windings. Transformer is
more complicated.
Efficiency
> 85%
~=75%
O2: O2's topology is single
stage.
TI1451: TI1451 topology is
two stages.
Yes
No
O2: Open-lamp and short
Open-lamp
protection functions are
and short
integrated in Chip. TI1415:
protection
Need to add extra circuit to
do these protections
Thermal
issue
Brightness
efficiency
Burst-Mode
Function
No
Yes
Very Good
Medium
Yes
No
O2: The temperature of
transformer and MOSFET's is
low because O2 inverter has
higher efficiency.
TI1451: TI1451 topology
causes many components
with higher thermal, which
are transformer, oscillated
capacitor, MOSFET and
choke.
O2: Output current is sine
waveform.
O2: Burst mode function is
built in IC. And transformer is
without noise when inverter
works under burst-mode.
TI1451: Need add extra
circuit to implement the
function. Transformer has
noise when inverter works
under burst-mode.
Pspice Circuit
OVP
Power stage
Secondary of transformer