lecture 250 – simulation and measurement of op amps

Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-1
LECTURE 250 – SIMULATION AND MEASUREMENT OF OP
AMPS
LECTURE ORGANIZATION
Outline
• Introduction
• Open Loop Gain
• CMRR and PSRR
• A general method of measuring Avd, CMRR, and PSRR
• Other op amp measurements
• Simulation of a Two-Stage Op Amp
• Op amp macromodels
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 310-341
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-2
INTRODUCTION
Simulation and Measurement Considerations
Objectives:
• The objective of simulation is to verify and optimize the design.
• The objective of measurement is to experimentally confirm the specifications.
Similarity between Simulation and Measurement:
• Same goals
• Same approach or technique
Differences between Simulation and Measurement:
• Simulation can idealize a circuit
- All transistor electrical parameters are ideally matched
- Ideal stimuli
• Measurement must consider all nonidealities
- Physical and electrical parameter mismatches
- Nonideal stimuli
- Parasistics
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-3
OPEN LOOP GAIN
Simulating or Measuring the Open-Loop Transfer Function of the Op Amp
Circuit (Darkened op amp identifies the op amp under test):
Simulation:
VDD
vIN +VOS vOUT
This circuit will give the voltage transfer
function curve. This curve should identify:
1.) The linear range of operation
RL
CL
VSS
2.) The gain in the linear range
3.) The output limits
Fig. 240-01
4.) The systematic input offset voltage
5.) DC operating conditions, power dissipation
6.) When biased in the linear range, the small-signal frequency response can be
obtained
7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:
This circuit probably will not work unless the op amp gain is very low.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-4
A More Robust Method of Measuring the Open-Loop Frequency Response
Circuit:
vOUT
vIN
C
CL
R
RL
VDD
VSS
Fig. 240-02
Resulting Closed-Loop Frequency Response:
dB
Op Amp
Open Loop
Frequency
Response
Av(0)
0dB
1
RC
Av(0)
RC
log10(w)
Fig. 240-03
Make the RC product as large as possible.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-5
CMRR AND PSRR
Simulation of the Common-Mode Voltage Gain
V
+ OS-
VDD
vout
+
vcm
-
CL
VSS
RL
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region.
Divide (subtract dB) the result into the open-loop gain to get CMRR.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-6
Simulation of CMRR of an Op Amp
None of the above methods are really suitable for simulation of CMRR.
Consider the following:
Vcm
V2
Vcm
VDD
V2 -
Vout
V1
V1 +
VSS
Vcm
Av(V1-V2)
Vcm
Vout
±AcVcm
Fig. 6.6-7
cm
V 1+V2
V out = Av (V1-V 2) ±A
2 = -AvV out ± AcmV cm
±Acm
±Acm
V out = 1+Av Vcm Av Vcm
Av V cm
|CMRR|=Acm=V out
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-7
Direct Simulation of PSRR
Circuit:
Vdd
V2
V2
-
V1
+
Av(V1-V2)
VDD
V1
VSS
Vss
Vout
Vss = 0
±AddVdd
Fig. 6.6-9
V out = Av (V1-V 2) ±AddV dd = -AvV out ± AddV dd
±Add
±Add
V out = 1+Av Vdd Av Vdd
Av V dd
Av V ss
PSRR+=Add=V out and PSRR-=Ass=V out
Works well as long as CMRR is much greater than 1.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-8
A GENERAL METHOD OF MEASURING AVD, CMRR, AND PSRR
General Principle of the Measurement
Circuit:
100kΩ
vOS
100kΩ
vSET
100kΩ
10kΩ
100kΩ
-
vOUT
VDD
+
10Ω
"Op Amp"
+
"Op Amp"
vI
-
vSET
vOUT =
-vSET
CL
RL
VSS
070429-01
The amplifier under test is shown as the darkened op amp.
Principle:
Apply the stimulus to the output of the op amp under test and see how the input
responds. Note that:
vOS
vOUT = - vSET and vI 1000
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-9
Measurement of Open-Loop Gain
Measurement configuration:
+
-
Vos
100kΩ
100kΩ
Vout
10kΩ
Vout
VDD
+
10Ω
V
i
V out V out
CL RL
VSS
Avd = V id = V i
060701-01
V os 1000Vi
1000Vout
Therefore, Avd = V
os
Sweep Vout as a function of frequency, invert the result and multiply by 1000 to get
Avd(j).
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
100kΩ
+
-
Measurement of CMRR
Measurement Configuration:
Note that the whole amplifier is stimulated by vos
V icm while the input responds to this change.
The definition of the common-mode rejection 10kΩ
ratio is
(vout/vid)
Avd CMRR = Acm = (vout/vicm)
+
10Ω vi
However, in the above circuit the value of vout
is the same so that we get
vicm
CMRR = vid
vos
But vid = vi and vos 1000vi = 1000vid vid = 1000
Page 250-10
vicm
100kΩ
vOUT
VDD
vicm
CL
RL
VSS
Fig. 240-08
vicm 1000vicm
CMRR = vos =
vos
1000
Make a frequency sweep of Vicm, invert the result and multiply by 1000 to get CMRR.
Substituting in the previous expression gives,
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-11
Measurement of PSRR
Measurement Configuration:
The definition of the positive power supply rejection
ratio is
(Vout/V id)
Avd +
PSRR = Acm = (Vout/V dd)
However, in the above circuit the value of Vout is the
same so that we get
V dd
PSRR+ = V
id
But Vid = Vi and Vos 1000Vi = 1000Vid
V id =
V os
1000
Substituting in the previous expression gives,
100kΩ
Vos
100kΩ
Vdd
10kΩ
Vout
VDD
+
10Ω
Vi
CL
-
RL
Vss
VSS
070429-02
V dd 1000Vdd
PSRR+ = V = V
os
os
1000
Make a frequency sweep of Vdd, invert the result and multiply by 1000 to get PSRR+.
(Same procedure holds for PSRR-.)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-12
OTHER OP AMP MEASUREMENTS
Simulation or Measurement of ICMR
vOUT
IDD
vOUT
VDD
1
1
vIN
+
vIN
-
ISS
CL
RL
VSS
ICMR
Also, monitor
IDD or ISS. Fig.240-11
Initial jump in sweep is due to the turn-on of M5.
Should also plot the current in the input stage (or the power supply current).
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-13
Measurement or Simulation of Slew Rate and Settling Time
Volts Peak Overshoot
vin
IDD
vout
Settling Error
Tolerance
VDD
+SR -SR
+
vin
-
CL
RL
1
VSS
vout
1
t
Settling Time
Feedthrough
Fig. 240-14
If the slew rate influences the small signal response, then make the input step size small
enough to avoid slew rate (i.e. less than 0.5V for MOS).
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-14
Phase Margin and Peak Overshoot Relationship
It can be shown (Appendix C of the text) that:
100
20
60
10
50
5
Phase Margin
40
Overshoot
30
Overshoot (%)
For example, a 5% overshoot
corresponds to a phase margin of
approximately 64°.
Phase Margin (Degrees)
Phase Margin (Degrees) = 57.2958cos-1[ 44+1 - 22]
Overshoot (%)
80
- = 100 exp
70
1-2
1.0
20
10
0
CMOS Analog Circuit Design
0
0.2
0.4
ζ= 1
2Q
0.6
0.8
1
0.1
070429-03
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-15
SIMULATION OF A TWO-STAGE CMOS OP AMP
Example 250-1 Simulation of a Two-Stage CMOS Op Amp
An op amp designed using the procedure described in Lecture 230 is to be simulated
by SPICE. The device parameters to be used are those of Tables 3.1-2 and 3.2-1 of the
textbook CMOS Analog Circuit Design.
15μm
1μm
M3
VDD = 2.5V
M4
15μm
1μm
M6
Cc = 3pF
30μA
4.5μm
1μm
M1
vin
+
3μm
1μm
3μm
1μm
vout
M2
95μA
30μA
M8
4.5μm
M5 1μm
VSS = -2.5V
94μm
1μm
M7
CL =
10pF
14μm
1μm
Fig. 240-16
The specifications of this op amp are as follows where the channel length is to be 1μm
and the load capacitor is CL = 10pF:
Av > 3000V/V
V DD = 2.5V
V SS = -2.5V
GB = 5MHz
SR > 10V/μs
60° phase margin
V out range = ±2V
ICMR = -1 to 2V
Pdiss 2mW
CMOS Analog Circuit Design
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
© P.E. Allen - 2010
Page 250-16
Example 250-1 – Continued
Bulk Capacitance Calculation:
If the values of the area and perimeter of the drain and source of each transistor are
known, then the simulator will calculate the values of CBD and C Bs. Since there is no
layout yet, we estimate the values of the area and perimeter of the drain and source of
each transistor as:
AS = AD W[L1 + L2 + L3]
PS = PD 2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in the
moat (2μm), L2 is the length of a minimum-size square contact to moat (2μm), and L3 is
the minimum allowable distance between a contact to moat and the edge of the moat
(2μm). (These values will be found from the physical design rules for the technology).
For example consider M1:
AS = AD = (3μm)x(2μm+2μm+2μm) = 18μm2
PS = PD = 2x3μm + 2x6μm = 19μm
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-17
Example 250-1 - Continued
Op Amp Subcircuit:
- 2
vin
+ 1
-
8 VDD
6 vout
+
9 VSS
Fig. 240-17
.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U
M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS
CMOS Analog Circuit Design
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
© P.E. Allen - 2010
Page 250-18
Example 250-1 - Continued
PSPICE Input File for the Open-Loop Configuration:
EXAMPLE 250-1 OPEN LOOP CONFIGURATION
.OPTION LIMPTS=1000
VIN+ 1 0 DC 0 AC 1.0
VDD 4 0 DC 2.5
VSS 0 5 DC 2.5
VIN - 2 0 DC 0
CL 3 0 10P
X1 1 2 3 4 5 OPAMP
..
.
(Subcircuit of previous slide)
..
.
.OP
.TF V(3) VIN+
.DC VIN+ -0.005 0.005 100U
.PRINT DC V(3)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE
(This entry is unique to PSPICE)
.END
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-19
Example 250-1 - Continued
Open-loop transfer characteristic:
2.5
2
VOS
vOUT(V)
1
0
-1
-2
-2.5
-2
-1.5
-1.0 -0.5
0
0.5
vIN(mV)
1
1.5
2
Fig. 240-18
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-20
Example 250-1 - Continued
Open-loop transfer frequency response:
200
80
150
Phase Shift (Degrees)
Magnitude (dB)
60
40
20
0
100
50
0
-50
-100
-20
-150
GB
-40
Phase Margin
GB
-200
10
100
1000
CMOS Analog Circuit Design
105
106
104
Frequency (Hz)
107
108
10
100
1000
104
105
106
Frequency (Hz)
107
108
Fig. 6.6-16
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-21
Example 250-1 - Continued
Input common mode range:
-
3
Subckt.
+
1
3
vout
5
vin
VSS
Fig. 6.6-16A
40
ID(M5)
30
20
Input CMR
vOUT (V)
-3
Note the usefulness of monitoring the
current in the input stage to determine
the lower limit of the ICMR.
VDD
10
ID(M5) μA
EXAMPLE 250-1 UNITY GAIN CONFIGURATION.
.OPTION LIMPTS=501
VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U
+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)
VDD 4 0 DC 2.5 AC 1.0
VSS 0 5 DC 2.5
CL 3 0 20P
X1 1 3 3 4 5 OPAMP
4
..
.
3
(Subcircuit of Table 6.6-1)
..
.
2
.DC VIN+ -2.5 2.5 0.1
.PRINT DC V(3)
1
.TRAN 0.05U 10U 0 10N
.PRINT TRAN V(3) V(1)
0
.AC DEC 10 1 10MEG
-1
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
-2
.END
4
0
-3
-2
-1
0
vIN(V)
CMOS Analog Circuit Design
1
2
3
Fig. 240-21
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-22
Example 250-1 - Continued
Positive PSRR:
100
100
Arg[PSRR+(jω)] (Degrees)
|PSRR+(jω)| dB
80
60
40
20
0
-20
10
100
1000
104
105
106
Frequency (Hz)
107
108
50
0
-50
-100
10
100
1000
104
105
106
Frequency (Hz)
107
10
Fig. 240-22
This PSRR+ is poor because of the Miller capacitor. The degree of PSRR+ deterioration
will be better shown when compared with the PSRR-.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-23
Example 250-1 - Continued
Negative PSRR:
200
120
Arg[PSRR-(jω)] (Degrees)
150
|PSRR-(jω)| dB
100
80
60
PSRR+
40
20
10
100
50
0
-50
-100
-150
-200
100
1000
104
105
106
Frequency (Hz)
107
108
10
100
1000
104
105
106
Frequency (Hz)
CMOS Analog Circuit Design
107
108
Fig. 240-23
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-24
Example 250-1 - Continued
Large-signal and small-signal transient response:
1.5
0.15
1
0.1
0.05
vout(t)
Volts
Volts
0.5
vin(t)
0
-0.5
vout(t)
0
-0.05
vin(t)
-1
-0.1
-1.5
-0.15
0
1
2
3
Time (Microseconds)
4
5
2.5
3.0
Why the negative overshoot on the slew rate?
If M7 cannot sink sufficient current then the output stage
slews and only responds to changes at the output via the
feedback path which involves a delay.
Note that -dvout/dt -2V/0.3μs = -6.67V/μs. For a
10pF capacitor this requires 66.7μA and only 95μA-66.7μA
= 28μA is available for Cc. For the positive slew rate, M6
can provide whatever current is required by the capacitors
and can immediately respond to changes at the output.
CMOS Analog Circuit Design
3.5
4.0
Time (Microseconds)
4.5
Fig. 240-24
VDD
M6
Cc iCc
iCL
dvout
dt
CL
95μA
+
VBias
-
vout
M7
VSS
Fig. 240-25
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-25
Example 250-1 - Continued
Comparison of the Simulation Results with the Specifications of Example 250-1:
Specification
(Power supply = ±2.5V)
Open Loop Gain
GB (MHz)
Input CMR (Volts)
Slew Rate (V/μsec)
Pdiss (mW)
Vout range (V)
PSRR+ (0) (dB)
PSRR- (0) (dB)
Phase margin (degrees)
Output Resistance (k)
Design
Simulation
>5000
5 MHz
-1V to 2V
>10 (V/μsec)
< 2mW
±2V
60°
-
10,000
5 MHz
-1.2 V to 2.4 V,
+10, -7(V/μsec)
0.625mW
+2.3V, -2.2V
87
106
65°
122.5k
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Relative Overshoots of Ex. 250-1
Why is the negative-going overshoot
larger than the positive-going overshoot
on the small-signal transient response of
the last slide?
Consider the following circuit and
waveform:
Page 250-26
VDD = 2.5V
94/1
M6 i6
iCc
iCL
0.1V
t
vout
Cc
95μA
CL
-0.1V
VBias
M7
0.1μs
0.1μs
Fig. 240-26
VSS = -2.5V
During the rise time,
iCL = CL(dvout/dt )= 10pF(0.2V/0.1μs) = 20μA and iCc = 3pf(2V/μs) = 6μA
i6 = 95μA + 20μA + 6μA = 121μA gm6 = 1066μS (nominal was 942.5μS)
During the fall time, iCL = CL(-dvout/dt) = 10pF(-0.2V/0.1μs) = -20μA
and iCc = -3pf(2V/μs) = -6μA
i6 = 95μA - 20μA - 6μA = 69μA
gm6 = 805μS
The dominant pole is p1 (RIgm6RIICc)-1 but the GB is gmI/Cc = 94.25μS/3pF =
31.42x106 rads/sec and stays constant. Thus we must look elsewhere for the reason.
Recall that p2 gm6/CL which explains the difference.
p2(95μA) = 94.25x106 rads/sec, p2(121μA) = 106.6 x106 rads/sec, and p2(69μA) =
80.05 x106 rads/sec. Thus, the phase margin is less during the fall time than the rise time.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-27
OP AMP MACROMODELS
What is a Macromodel?
A macromodel uses resistors, capacitors, inductors, controlled sources, and some active
devices (mostly diodes) to capture the essence of the performance of a complex circuit
like an op amp without modeling every internal component of the op amp.
Small Signal, Frequency Independent Op Amp Macromodel
v1
v1
1
vo
A
3
v1
Ro v o
1
4
R id
Avd (v 1 -v 2 )
2
2
v2
(a.)
Avd (v -v )
1 2
Ro
R id
v2
v2
3
(b.)
(c.)
vo
Ro
Fig. 010-01
Figure 1 - (a.) Op amp symbol. (b.) Thevenin form. (c.) Norton form.
1
Ric1
3
Rid
Avd(v1 -v2 )
Ro
2
Avc v1
2Ro
+
Avc v2
2Ro
Ro
vo
-
Ric2
Linear Op Amp Macromodel
Fig. 010-03
Figure 2 - Simple op amp model including differential and common mode behavior.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-28
Small Signal, Frequency Dependent Op Amp Macromodel
Avd(0)
1
Avd(s) = (s/1)+1 where 1= R1C1 (dominant pole)
Model Using Passive Components:
v1
3
1
vo
Rid
v2
2
Avd(0)
(v1 -v2 )
R1
R1
C1
Fig. 010-04
Figure 3 - Macromodel for the op amp including the frequency response of Avd.
Model Using Passive Components with Constant Output Resistance:
v1
1
3
Rid
v2
2
Avd(0)
(v1 -v2 )
R1
R1
4
C1
v3
Ro
vo
Ro
Fig. 010-05
Figure 4 - Frequency dependent model with constant output resistance.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-29
Large Signal, Frequency Independent Op Amp Macromodel
RLIM
1
Ric1
VIH1
Ric2
+
6
VIL1
-
7
+
D4
8
-
VIL2
+
9
3
Rid
Avc v4
2Ro
5
D3
+
VIH2
Nonlinear Op
Amp Macromodel
D2
D1
RLIM
2
4
Avc v5
2Ro
+
D5
Ro
Avd
(v -v )
Ro 4 5
VOH
D6
+ 10
+ 11 vo
VOL
-
Fig. 010-10
Figure 5 - Op amp macromodel that limits the input and output voltages.
Io
ILimit
2
v1
Io
2
Io
2
D1
D3
D2
ILimit
D4
1
Io
Rid
2
ILimit
2
Io
2
D3
4
v2
Io
2 Fig. 010-12
D4
Ro
Avd
(v -v )
Ro 1 2
5
D1
3
D5
+
D2
VOH
ILimit 6
D6
7
-
VOL
+
vo
8
-
Fig. 010-13
Figure 6 – Technique for current limiting and a macromodel for output voltage and
current limiting.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-30
Large Signal, Frequency Dependent Op Amp Macromodel
Slew Rate:
dvo ±ISR
dt = C1 = Slew Rate
v1
6
1
v2
2
Avd(0)
(v1 -v2 )
R1
3
5
C1
R1
D1
D3
4
Rid
v4 -v5
Ro
D2
D4
ISR
7
vo
Ro
Fig. 010-15
Figure 7 – Slew rate macromodel for an op amp.
Results for a unity gain op amp in slew:
10V
5V
Output
Voltage
0V
-5V
-10V
0μs
CMOS Analog Circuit Design
Input
Voltage
2μs
4μs
Time
6μs
8μs
10μs
Fig. 010-16
© P.E. Allen - 2010
Lecture 250 – Measurement and Simulation of Op amps (3/28/10)
Page 250-31
SUMMARY
• Simulation and measurement of op amps has both similarities and differences
• Measurement of open loop gain is very challenging – the key is to keep the quiescent
point output of the op amp well defined
• The method of stimulating the output of the op amp or power supplies and letting the
input respond results in a robust method of measuring open loop gain, CMRR, and PSRR
• Carefully investigate any deviations or aberrations from expected behavior in the
simulation and experimental results
• Macromodels are useful for modeling the op amp without including every individual
transistor
CMOS Analog Circuit Design
© P.E. Allen - 2010