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3-D Flash Cost Comparisons
3-D Flash Cost Comparisons Andrew J. Walker Schiltron Corporation 2013 What is the Cheapest 3-D Flash Approach ? • Candidates compared – Vertical Channel NAND (TCAT, BiCS) – Vertical Gate NAND (VG-NAND) – Schiltron Dual-Gate TFT SONOS • Conventional wisdom – Reduce the number of photolithographic steps to minimize total cost • Is this correct? • Does this lead to the lowest total cost? Schiltron Corporation 2013 Vertical Channel NAND VG NAND Schiltron Hole and Slit with vertical channel conduction Perpendicular gate and channel slits with horizontal conduction Perpendicular gate and channel in a dual-gate architecture with horizontal conduction Lithography-light Lithography-light Lithography-intensive Deposition and Deep Etch Intensive Deposition and Deep Etch Intensive Deposition and etch per layer similar to 2D Schiltron Corporation 2013 Vertical Channel NAND Channels Wordlines Schiltron Corporation 2013 Vertical Channel NAND – Section parallel to wordlines Schiltron Corporation 2013 Vertical Channel NAND – Section perpendicular to wordlines Schiltron Corporation 2013 Vertical Channel NAND – Plan view Schiltron Corporation 2013 VG NAND Wordlines Channels Schiltron Corporation 2013 VG NAND – Section perpendicular to channels PX θxo F minWX Schiltron Corporation 2013 TONO VG NAND – Section perpendicular to wordlines θyo PY F Wg Ws minWY Schiltron Corporation 2013 VG NAND – Plan view Py PX Schiltron Corporation 2013 Schiltron Top Gate Wordlines Bottom Gate Wordlines Channels Schiltron Corporation 2013 Schiltron – Section perpendicular to channels PX Schiltron Corporation 2013 Schiltron – Section perpendicular to wordlines PY Schiltron Corporation 2013 Schiltron – Plan view Py Px Schiltron Corporation 2013 256 Gbit Die Cost Comparison* Vertical Channel NAND 256 Gbit Die Cost ($) VG NAND Vertical Channel NAND Schiltron VG NAND Schiltron Number of Device Layers Schiltron Corporation 2013 * Cost analysis submitted for publication Cost Model Parameters Vertical Channel NAND VG NAND RB Lg Lspace Θ Tono F DB Array Efficiency Ncrit (total) C0 Ccrit per critical layer Wafer Diam. Wg Wspace Θx Θy Tono F minWx minWy Cell Overhead Array Efficiency Ncrit (total) C0 Ccrit per critical layer Wafer Diam. 10 nm 25 nm 25 nm 1 deg 20 nm 25 nm 20 nm 80 % 2 $2800 $200 300 mm Schiltron 25 nm 25 nm 4 deg 0 deg 20 nm 25 nm 80 nm 35 nm 0% 80 % 2 $2800 $200 300 mm Schiltron Corporation 2013 Lg Lspace W Wspace Cell Overhead Array Efficiency Ncrit/Layer C0 Ccrit per critical layer Wafer Diam. 25 nm 25 nm 25 nm 25 nm 10 % 80 % 3 $2800 $200 300 mm Cost Model Assumptions and Simplifications • Yield effects not taken into account • Control block circuitry residing in the bulk silicon assumed to be similar for all approaches and described by the same array efficiency factor • Single level cells • Control block circuitry does not grow as more layers are stacked Schiltron Corporation 2013 Vertical Channel NAND – Effect of Taper Angles on 256 Gbit Die Cost Cost Model Parameters RB Lg Ls Array Eff. Tono F DB Ncrit (total) C0 Ccrit Wafer Diam. Schiltron Corporation 2013 10 nm 30 nm 30 nm 80 % 20 nm 40 nm 20 nm 2 $2800 $200 300 mm Vertical Channel NAND – Effect of Taper Angles on 256 Gbit Die Cost Rotating 3-D Graph Schiltron Corporation 2013 Vertical Channel NAND – Effect of Vertical Gate Pitch on 256 Gbit Die Cost Cost Model Parameters 256 Gbit Die Cost ($) RB Lg Ls Θ Array Eff. Tono F DB Ncrit (total) C0 Ccrit Wafer Diam. Number of Layers Vertical Gate Pitch (nm) Schiltron Corporation 2013 10 nm Variable Variable 1 deg 80 % 20 nm 40 nm 20 nm 2 $2800 $200 300 mm Vertical Channel NAND – Effect of Vertical Gate Pitch on 256 Gbit Die Cost Rotating 3-D Graph Schiltron Corporation 2013 VG NAND – Effect of Taper Angles on 256 Gbit Die Cost VG NAND 256 Gbit Die Cost ($) Wg Wspace Θx Θy Tono F minWx minWy Cell Ov. head Array Eff Ncrit (total) C0 Ccrit Wafer Diam. Θx (deg) Θy (deg) Schiltron Corporation 2013 25 nm 25 nm Variable Variable 20 nm 25 nm 80 nm 35 nm 0% 80 % 2 $2800 $200 300 mm VG NAND – Effect of Taper Angles on 256 Gbit Die Cost Rotating 3-D Graph Schiltron Corporation 2013 Conclusions • Any high density 3-D Flash approach that exchanges lithography-intensive processing per device layer for stack deposition followed by hole and/or trench etching must result in taper angles of zero or close to zero degrees from the normal • Otherwise its total cost can be undercut by any 3-D process that uses lithography per device layer to minimize cell areas on all layers • A simple but often overlooked insight is that it is the cell pitch at the top of the 3-D stack that determines the total memory array size • Any non-zero taper angle results in cell pitches and die sizes larger than lithographically possible • The main driver of Moore’s Law in 2-D, namely photolithography, will also be the main driver in monolithic 3-D to achieve the lowest cost high density Flash memory Schiltron Corporation 2013
