ENISLE: A Clustering Algorithm for Nearly Maximal and Minimal

Transcription

Tamkang Journal of Science and Engineering, Vol. 8, No 2, pp. 155-164 (2005)
155
ENISLE: A Clustering Algorithm for Nearly Maximal and
Minimal Connection on Hypergraph
Kou-Hsing Cheng1 and Shun-Wen Cheng2*
1
Department of Electrical Engineering, National Central University
Taoyuan, Taiwan 320, R.O.C.
2
Department of Electrical Engineering, Tamkang University
Tamsui, Taiwan 251, R.O.C.
Abstract
This work presents two approaches with a high probability of obtaining maximal and
minimal connection in an electrical network. The first method, referred to herein as Edge-Node
Interleaved Sort for Leaching and Envelop (ENISLE) algorithm, uses both node information and
edge information and works effectively on a common network. The second method, referred to
herein as Interleaved Cutting-ENISLE (IC-ENISLE) algorithm, uses node and edge information as
well as the max-min dual property. This method works better than ENISLE in an electrical circuit. This
study also finds the relationship between minimal connection and the initial node-edge pairs
distributed condition/entropy on hypergraph circuit. Under a nearly max-connection reservation, a
circuit with a high initial potential/entropy implies a high probability of aiming the minimal
connection. From our approach, the work indicates that the minimum connection plane characteristics
significantly affect the connection problems. Our results further demonstrate that, with respect to the
sequential circuit or other time-sensitive circuits as an indivisible element, record the level is even or
odd, and/or record the level number of every node or edge, are highly effective for modern circuit
network connection.
Key Words: ENISLE, Minimal-connection, Quasi-random, Clustering Effect, Radix Sort, Hypergraph,
VLSI Circuit
1. Introduction
Let a circuit be represented by a hyper-graph or
netlist G = (V, E) where V is the set of nodes that represent
the circuit components and E is the set of hyperedges that
represent the nets of the circuit. Each hyperedge or net
connects two or more nodes together; the output of a
node is generally connected to the inputs of several other
nodes by a net [1,2]. The nodes (vertex) and nets (edge)
of a circuit are numbered and, then, the circuit is mapped
to a V-E plain (Figure. 1).
Figures 2 and 3 depict the goals of minimal and ratio-minimal connection display on the V-E plain respec*Corresponding author. E-mail: [email protected]
tively. Notably, when (V, E) pairs approach uniform distribution on the V-E plain, and if the minimal connection
can be obtained, the “outline areas” of the (V, E) pairs
from the product VE approach to VE /2, similar to vapor
compression behavior. Figure 4 shows some special (V,
E) pair distribution cases, which are commonly found
when describing row-based placements in sequence. The
“outline areas” of (V, E) pairs on the V-E plain are far
lower than the VE product. Under this initial condition,
the probability that the minimal connection solution can
be obtained is relatively small. This is unlike previous
described vapor compression behavior, which is just
similar to “melting” of the material [3]. Therefore, the
material must be “heated” and then “entropy” added to it.
Notably, these cases are easily randomized. If local clus-
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Kou-Hsing Cheng and Shun-Wen Cheng
Figure 1. Initialize the V-E plain.
2. Edge-Node Interleaved Sort for Leaching
and Envelop (ENISLE) Algorithms Family
Figure 2. The goal of minimal connection.
Figure 3. The goal of ratio minimal connection.
Figure 4. Some special (V, E) pair distribution cases.
ter blocks exist, only the blocks need to be resolved. The
paper is divided into five additional sections. Section 2
elucidates the proposed Edge-Node Interleaved Sort for
Leaching and Envelop (ENISLE) Algorithms. Section 3
describes display compression methods. Section 4 presents the performance comparisons. Section 5 displays
the relationship between initial node-edge pairs’ entropy
and minimal connection circuit. The final section gives
the concluding remarks.
The proposed ENISLE (Edge-Node Interleaved Sort
for Leaching and Envelop) algorithm uses both node and
edge information. Also, the IC-ENISLE (Interleaved
Cutting-ENISLE) algorithm uses both node and edge information as well as the max-min dual property. The
sorting steps for both algorithms are the same. Figure 5
illustrates the first four sort steps of the basic ENISLE algorithm for minimal connection by a 14-edge/15-node
circuit example [4,5].
The V-E plain is first initialized. As shown in Figure
1, randomly number the nodes in A~O, and randomly
number the edges in 1~14. After the circuit size is determined, a memory block is initialize and allocated, and
the memory block is cleaned; all the memories are set to
zero. If a node has a connection with an edge, the symbol
‘X’ (in fact, we fill ‘1’) fills in the corresponding position
on V-E plain. Naturally, a node has no connection with an
edge is ‘0’. The two node sets are recorded and then the
distributed condition is confirmed.
Second, sort step 1 is processed from the edge view
in the bottom-side base (Figure 5(a)). After sorting, the
order of the edges has already interchanged. Notably the
order of the nodes does not change in this step. Also, the
two node sets are recorded.
Third, sorting step 2 is processed from node view in
the right-side base (Figure 5(b)). After sorting, the order
of the nodes has already interchanged. Also, the order of
the edges does not change in this step. (V, E) pairs, the
two node sets must be recorded, and the node sets that
have changed must be found.
ENISLE: A Clustering Algorithm for Nearly Maximal and Minimal Connection on Hypergraph
Figure 5. The first four sort steps of the proposed ENISLE algorithms.
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Fourth, sorting step 3 is processed from edge view in
the topside base (Figure 5(c)). After sorting, the order of
the edges has already interchanged. Also, the order of the
nodes does not change in this step. Some (V, E) pairs have
already been clustered. The two node sets are recorded
and the node sets that have changed are found.
Next, sort step 4 is processed from node view in the
right-side base (Figure 5(d)). After sorting, the order of
the nodes has already interchanged. Also, the order of the
edges does not change in this step. The two node sets are
recorded and the node sets that have not changed further
are found. The procedures are then halted. Two possible
minimal connections can be obtained for this tiny oddnode circuit (Figure 5(e)).
Figure 6 illustrates the ENISLE family algorithms.
The proposed ENISLE algorithm is characterized by the
second sort phase. Additional sorting steps can be selected. Type 2A, type 2B and type 2C have a similar high
performance. Type 2D, the same as phase one sort steps,
has the worst performance. Other recurring sort orders
or clustering methods, e.g., collecting intersection edge
vectors, may work but are unstable.
Owing to that type 2A has the most compact formula,
it is used herein after. A larger node generally implies a
larger edge. A completely connected n-node circuit has
n(n-1)/2 edges. Assume that a common commercial circuit has m edges, n nodes, and mµn. A powerful sorting
engine determines the performance of this method. Radix sort can be used to resolve this problem efficiently
(Figure 7). Notably, performance of the proposed ENISLE
method is in proportion to that of the radix sort engine.
The time complexity of the radix sort is O(N) in average
cases [6].
Under a nearly maximal connection reservation, a
circuit mapping on the V-E plain with a higher initial potential/entropy implies a higher probability of obtaining
the minimal connection. Notably, the V-E plain can be
used to intuitively determine whether uniform distribu-
Figure 6. The proposed ENISLE Algorithm family-include classic ENISLE and IC–ENISLE.
Figure 7. Using radix-sorting techniques effectively handle
the sorting job.
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Figure 8. Interleaved cutting the circuit can get an initial
nearly max connection status.
Figure 9. It shows the proposed IC–ENISLE 2A algorithm effectively gets the minimal and ratio minimal connection at the same time.
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tion is possible without the need for additional computation about correlation coefficients or co-variances or not.
If (V, E) pairs are not uniformly distributed on the V-E
plain, and if they are not randomized, the convergence
procedures can be executed directly, possibly yielding a
worse solution and leaving the sort loop. No non-determined/infinite loops occur. The ENISLE methods need
no additional verification as function Gain for K-L algorithm, function Score for Simulated Annealing, function
Cost for Simulated Evolution algorithm, or function
Count for Metric Allocation Method [1-3,7]. And notice
sorting is not matrix operation. In the ENISLE algorithm,
the memory requirements must be carefully arranged.
Next, due to one byte is equal to eight bits, bit field structures are used to reduce one-eighth of the memory space.
If having 100K nodes and 500K edges, the program requires about 6.4GB of virtual memory space.
Hypergraphs (circuit) are typical compound treebased structures. Notably, the element does not need to
be further divided with respect to the sequential circuit
or timing-sensitive circuit. Therefore, the same level
nodes in tree-based structures do not connect with each
other, implying that the nodes between the same levels
have no edges. Next, the VLSI circuits are roughly divided into two parts: odd-level nodes and even-level
ones. Via this interleaved cutting concept, a nearly maximal connection of the VLSI circuit is achieved since
the nodes between the same levels do not have edges
(Figure 8).
The two part nodes are separately randomized to increase entropy. A common multiplicative congruential
random number generator (e.g., ANSI C function rand
and 16-bit Borland C compiler) with period 232 is used to
return successive pseudo-random numbers ranging from
0 to 215. This implies the function can handle a 215
(32,768) node-size circuit per time under this compiler.
Following a slight modification, a quasi-random number
series without repeated-present numbers is generated.
Notably, we only need to randomize the node number series. Additionally, the edge number series is not considered because it is sorted from the bottom-side edge base
first.
In addition to separating the circuit not only by level
even or odd, this work also records the level number of
each edge for timing-driven specs (Figure 8). Therefore,
the initial stage is not only in higher entropy, but also holds
a nearly maximal connection reservation. Figure 9 indicates that the IC-ENISLE algorithm achieves the minimal
and the ratio minimal connection simultaneously. Additionally, the proposed method can directly select an appropriate connection solution from the V-E plain for different
specs (Figure 10).
3. Display Representations and Compression
3.1 Originally Display (V, E) Pairs on a V-E Plain
The screen can be scrolled like a spreadsheet to observe the distributed condition for (V, E) pairs.
3.2 Display the Compression by Different Colors
On a 1280 ´ 1024 pixels ´ 24 bits true color display
monitor, assume 1280 ´ 16 bits edges/1024 ´ 8 bits
nodes = 20480 edges/8192 nodes per screen, or 1024 ´
24 bits edges/1280 bits nodes = 24576 edges/1280
nodes per screen. The screen can be scrolled a spreadsheet. We can directly observe each iterative improvement, acquire useful information, or manually halt the
procedures if necessary.
Figure 10. The proposed ENISLE methods can directly select
an appropriate connection solution from the V-E
plain for different specs.
3.3 Display the Compression by Various Light
Densities and/or Various Patterns
Figure 11 illustrates a useful data compression tech-
nique. Let L nodes ´ W edges (V, E) pairs rectangle (if L
= W, this is a square) compose a block. The larger the
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number of (V, E) pairs in the block implies a higher light
intensity. If the block contains no (V, E) pair, it is dark.
Although display compression makes us impossible to detect the exact display positions of (V, E) pairs, it
is only displayed in a block. Nevertheless, a larger size
V-E plain or the whole V-E plain can be viewed on a
monitor screen. Actually, the exact (V, E) pairs positions
can still be maintained. Thus, the V-E plain can be
zoomed in to closely monitor local (V, E) pairs distributed condition, or zoom out to view the global distributed condition.
4. Performance Comparisons Between
ENISLE and IC-ENISLE
Figure 11. Data display compression representation of Figure
9 demonstration.
Figures 12(a) and (b) display a same special circuit
and two numbered methods separately. The minimal
Figure 12. (a) Number the circuit from front-end to back-end in sequence. (b) Number the circuit from front-end to back-end in interleaved levels.
Figure 13. The cumulative distribution of initial connection numbers by 32,767 runs with different random order. (a) Randomize
the whole node order. (b) Separately randomize two part nodes under Interleaved Cutting.
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Figure 14. The cumulative distribution of final cut numbers by (a) Classic ENISLE (b) IC-ENISLE.
connection of the circuit (1 connection) and the second
minimal connection (6 connections) differ by 5 connections, which is relatively distant. Herein, the circuit is
used to assess the performance of the classical ENISLE
and the IC-ENISLE. Figures 13(a) and (b) illustrate the
cumulative distribution of initial connection numbers
by 32,767 runs with different random orders. Figure
13(a) illustrates a normal distribution, while Figure
13(b) displays the max-connection reservation. Figures
14(a) and 14(b) summarize those results. In this example, IC-ENISLE is 10.9% (14.1% asymmetric case)
higher than the classical ENISLE. The probability of hit
minimal connection ratio ranges from 64.1% to 76.2%.
If the minimal connection and other second minimal
connections neighbor each other, the information is more
complex. This issue is discussed later.
Although the circuit is extremely small, the symmetric condition decreases by 9.1% (IC-ENISLE) and 7%
(ENISLE). Notably, the symmetric problem heavily influences the experimental data. In practical applications,
asymmetric circuits are often encountered.
Figure 15. The relationship between connection numbers and
initial (V, E) pairs distributed entropy.
5. Relationship Between Initial Node-Edge
Pairs’ Entropy and Minimal Connection
Circuit
This work elucidates the relationships between minimal circuit connection and the initial (V, E) pairs distributed entropy on the V-E plain, as described below.
a. For the same initial connection number, as shown
Figure 16. The relationship between maximal and minimal
connection: the max-min weak dual property.
in Figure 15, a circuit with a higher initial potential/entropy will have a higher probability of mini-
mal connection.
b. For the same initial distribution, as shown in Figure
16, a circuit with an initial nearly max-connection
reservation, will have a high probability of minimal
connection.
Therefore, the proposed IC-ENISLE forces the initial stage not only to a high entropy but also to hold a
nearly max-connection reservation. An initial nearly maxconnection is easily obtained because VLSI circuits are
hypergraphs.
The VLSI circuit minimal connection is an edge (net)
minimal connection. A vertex (node) minimal-connection
also can be implemented by the proposed method, merely
by adding a transformation step:
G = (V, E) ® (E, V) = (V’, E’) = F
(1)
The proposed method can obtain the minimal edge
connections of the network netlists F, which are the minimal node connections of the original network, G. The
proposed method may be useful for the network flow
control problems [8]. With respect to the time-sensitive
circuits as indivisible elements, recording whether the
level is even or odd, and/or recording the level number of
every node or edge, are beneficial for circuit and network.
6. Conclusions
The IC-ENISLE algorithm uses not only node and
edge information but also the max-min dual property. It
works effectively for circuit minimal connection. The
study indicates the influences of the minimum connection plane characteristics on ENISLE algorithms. For a
fixed connection plane position, a circuit with fewer
connections on the plane, and thus higher flows pass the
edge, yields a higher probability of hitting the minimal
connection. The ENISLE algorithms have a high probability of hitting minimal connection or ratio minimal
connection, and so a strict balanced part number need
not be planned in advance. The proposed ENISLE algorithms may find a better way. Several connection solutions can be recorded and one chosen for the timingdriven performance constraint.
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The connection problem involves two main parts:
the first raises the entropy of the circuit, we let the circuit be on gaseous state-on the highest entropy; and the
second obtains a connection solution as vapor compression. The work is the first to have proposed the methods
that use not only node information but also edge information [9]. The relationship between initial node-edge
pairs’ entropy and minimal connection is elucidated.
The max-min dual property is obtained and used to
implement one of the proposed methods (IC-ENISLE).
IC-ENISLE frequently outperforms Classic ENISLE
on electrical circuits. Our results demonstrate that,
with respect to the sequential circuit or other timesensitive circuits as indivisible elements, recording
whether level is even or odd, and/or recording the level
number of every node or edge, are necessary. The study
is the first to show the immediate processes step by
step, and the proposed display compression methods
effectively monitor the processes. The authors successfully enisle the node-edge pairs by ENISLE algorithms, revealing a road to solving NP-complete problems [10].
References
[1] Garbers, J., Promel, H. J. and Steger, A., “Finding
Clusters in VLSI circuits,” Proc. IEEE/ACM Int. Conf.
Computer-Aided Design, ICCAD, Vol. 90, pp. 520–523
(1990).
[2] Sherwani, N. A., Algorithms for VLSI Physical Design Automation. 3rd Ed., Kluwer, Boston, MA, U.S.A.
(1999).
[3] Sechen, C., VLSI Placement & Global Routing Using
Simulated Annealing. Kluwer, Amsterdam, Netherlands
(1988).
[4] Akers, S. B., “Clustering Techniques for VLSI,” Proc.
IEEE Int. Symp. on Circuits and Systems, ISCAS Vol.
82, pp. 472–476 (1982).
[5] Cheng, S.-W. and Cheng, K.-H., “ENISLE: An Intuitive
Heuristic Nearly Optimal Solution for Mincut and Ratio
Mincut Partitioning,” Proc. IEEE Int. Symp. on Circuits
and Systems, ISCAS 2001, Vol. 5, pp. 167–170 (2001).
[6] Knuth, D. E., Sorting and Searching, Addison-Wesley,
Redwood, CA, U.S.A. (1973).
[7] Saab, Y. G., “A Fast and Robust Network Bisection Al-
164
gorithm,” IEEE Trans. Computers, pp. 903–913 (1995).
[8] Cheng, K.-H. and Cheng, S.-W., “A Study on the Relationship Between Initial Node-Edge Pairs Entropy and
Mincut Circuit Partitioning,” Proc. IEEE Int. Conf. on
Electronics, Circuits and Systems, ICECS 2001, pp.
889–893 (2001).
[9] Cheng, K.-H. and Cheng, S.-W., Method of Mincut and
Ratio Mincut (on Electrical Circuit). Patent No. 182649,
Taiwan, R.O.C., Nov. 24 (2003).
[10] Garey, M. R. and Johnson, D. S., Computers and Intractability, Freeman, San Francisco, CA, U.S.A. pp.
209–210 (1980).
Manuscript Received: Jan. 6, 2005
Accepted: Mar. 11, 2005

ENISLE: A Clustering Algorithm for Nearly Maximal and Minimal

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