Slides of Group IV Photonics 2015 plenary talk, PDF
Transcription
Slides of Group IV Photonics 2015 plenary talk, PDF
Silicon Nanophotonic Packaging Enabling large-scale deployment of photonics through cost-efficient and scalable packaging T. Barwicz, Y. Taira, T. W. Lichoulas, N. Boyer, H. Numata, Y. Martin, J.-W. Nah, S. Takenobu, A. Janta-Polczynski, E. L. Kimbrell, R. Leidy, M. Khater, S. Kamlapurkar, S. Engelmann, Y. A. Vlasov, P. Fortier August, 2015 © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Cost can hinder the societal impact of a technology Cost can define impact Telecom fiber capacity Tb/s 100 10 1 Gb/s 100 Tesla Motors, Tesla Roadster 2.5 First highway-capable electric vehicle • $109k+ ~2400 sold (2008-2012) • critical debut limited Earth impact 10 1 1986 Adapted from Winzer, OPN 2015 1994 2002 2010 2018 • massive bandwidth • cost prevents widespread applications Cost is not just a commercial concern. It defines the accessibility of a technology. Today’s challenge in optics: accessibility reduce cost by 10-100X major impact 2 Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Integration is changing the cost structure of optical devices Cost structure of legacy devices from discreet components Discreet components Impact of photonic integration less components, assembly, testing Assembly Impact of silicon photonic CMOS made Si fabrication reliable and cheap large scale integration tiny cost Testing Cost 100G legacy 100G-LR4 Si Phot. 100G lightwavestore.com 10G SONET transponder • • 3 Major cost reduction across the board with Si photonics. Some cost elements remain unchanged limiting factor. Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Silicon photonics may be hampered by everything but the silicon Silicon photonics device cost Silicon chip(s) Everything else assembly final test fiber connector(s) laser(s) etc. Need to reduce the cost of “everything else” for large scale deployment Leverage high-throughput microelectronic assembly lines for photonics packaging Leverage costefficiency of microelectronics in package not just wafer foxconn datacon 4 Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 What are we looking for in optical inputs and ouputs? 100GE agreements 400GE proposals # of λs λ spacing Fiber count LR4 4 4.5 nm 2 PSM4 1 N/A CWDM4 4 CLR4 4 # of λs λ spacing Fiber count LR8 8 4.5 nm 2 8 PSM4 1 N/A 8 20 nm 2 4x100G 4 20 nm 2 20 nm 2 8x50G 8 4.5 – 10 nm 2 For universal approach Bandwidth 73 nm + wiggle room for fabrication/temperature tolerances Number of fibers ≤ 8 in core applications up to tens in peripheral applications (but not hundreds/chip) Requirements 1. 2. 3. 4. 5 Low cost per optical port Large bandwidth for CWDM Scalability in port count (>8) Scalability in manufacturing volume Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Our solutions to low-cost and scalable photonic packaging Parallelized fiber assembly Standard MT fiber interface Compliant polymer interface Standard MT fiber interface Polymer waveguides in flexible ribbon Cleaved fiber array InP die Flip-chip electrical connections Flip-chip electrical connections Photonic die InP laser array Si Direct flip-chip assembly of InP die • • 6 Both approaches fully compatible with high-throughput assembly lines. Minimum number of parts and assembly steps for cost efficiency and scalability Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Example of full package integration in high-throughput tools flip chip 1. Laser(s) pick & place, anneal and underfill 2. C4 flip-chip assembly and reflow flip assembly flip assembly 4. Coverplate, cure adhesive 3. Optical I/Os pick & place, adhesive cure, C4 underfill • 7 A few steps to a 1st level package for LGA or BGA surface mount technology (SMT) Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Main challenges to leveraging high-throughput tools for photonics 1. Limited placement accuracy of ± 10 um Self-alignment for 1-2 um accuracy Polymer ribbon Mode engineering for max tolerances Connect at largest mode for tolerances 10 um fiber mode Photonic chip Mode expansion on wafer Avoid small-mode fibers for cost and tolerances 2. Inflexible pick-and-place handling Vacuum pick-tip handling Pressure-sensing movement only vertical Vacuum picktip Chip assembly Integrate polymer lid for fiber handling 8 Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Parallelized fiber assembly: details InP die Polymer lid Fiber ribbon V-groove array 1 Cleaved ends 2 InP attach region Flip-chip electrical interface Standard MT fiber interface 3 • • 9 InP die Photonic die Low cost pick-and-place assembly in high-throughput tools (T.Barwicz et al. ECTC 2015) Arbitrary number of fibers in 1D array, in-plane coupling for CWDM bandwidth. Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Parallelized fiber assembly: automated assembly results 12 fiber array Polymer lid Short MT ferrule Photonic die Cross-section of an assembly, all 12 fibers seated. Pick-tip Fiber core Adhesive Polymer lid … 100 um Si Fibers butted Side-view polished cross-section Lid Coupler in suspended membrane Fiber Si 100 um Adhesive Sliding base • • 10 Sliding base enables fiber butting on coupler with pure vertical pick-tip movement. Coupler in suspended membrane with undercut filled with adhesive at assembly. Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Parallelized fiber assembly: fiber self-alignment in action Pick tip Polymer lid Fiber V-groove Si photonic chip Pick tip reflection • • 11 Can re-align fiber offsets of up to ~40 um. Concept implemented in a common R&D flip-chip bonder Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Metamaterial converter for coupling to cleaved standard fiber Metamaterial converter SiO2 SiO2 Si Fiber coupler Si Undercut region Tapered up 12 Venting hole Hybrid waveguide Solid waveguide SiO2 Non-linear taper • • Si S-band metamaterial converter V-groove Undercut region Butt-junction Linear tapers Coupler embedded in suspended oxide membrane for isolation to Si handle First use of hybrid waveguide transition in Cheben et al., Optics Lett. 2010 Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Optical measurements of metamaterial converter performance Loss to fiber (dB) O-band converter response -1 -1.3 dB -2 TE TM 1.26 1.28 Chip ID 1 2 3 4 5 Max in -1.1 dB -1.2 dB -1.1 dB -2.4 dB -1.9 dB polarization 0.8 dB -3 1.31 um measurement with water immersion (n~1.31) 1.3 1.32 1.34 1.36 Wavelength (um) Min in -1.4 dB -1.5 dB -1.4 dB -2.6 dB -2.1 dB polarization Position on random random random edge wafer edge Measurement setup Jig for pressing fibers into grooves 13 • Manual assembly to V-grooves, no active alignment (OFC’15, Th3F.3). • Spread on single wafer: -1.1 dB to -2.6 dB • V-groove variability expected to dominate spread in this early production tools implementation Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Montecarlo demonstrates manufacturability of fiber self-alignment. V-groove related misalignment Total statistical misalignment • • • • • • V-groove align to coupler V-groove top open width and overetch Anisotropic etch selectivity, depth 1 Total fiber core to waveguide misalignment 1.5 y misalignment (um) y misalignment (um) V-groove related misalignment (Montecarlo) 1.5 0.5 0 -0.5 -1 -1.5 -1.5 -1 -0.5 0 0.5 1 x misalignment (um) V-groove uncertainty Fiber diameter, non-circularity Fiber core non-concentricity 1 0.5 0 -0.5 -1 -1.5 -1.5 -1 -0.5 0 0.5 1 x misalignment (um) 1.5 1.5 10,000 random error combinations plotted with the marginal x and y distributions • • 14 Montecarlo analysis demonstrates manufacturability with 3σ misalignment < ±1.3 um Details in T. Barwicz et al., ECTC 2015. Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: concept details Ferrule lid Polymer ribbon Standard MT fiber interface InP laser arrays Flexible region Ferrule Flip chip electrical connections Polymer coupling region InP attach region • • 15 InP die Photonic die Large number of optical ports per polymer interface, flexible for mechanical reliability Low cost pick-and-place assembly in high-throughput tools Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: optical design for large bandwidth • • 16 Butt-coupling to fiber in standard MT interface Adiabatic transformation in polymer ribbon and adiabatic coupling to Si Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: mechanical demonstration Cross-sectional diagram of interface Polymer ribbon Si chip Polymer waveguides Si waveguides Cross-sectional micrograph Micrograph of polished ferrule facet Ferrule lid 100 um Polymer ribbon backing Polymer waveguides Ferrule • 17 Polymer ribbon backing Lamination glue Polymer alignment ridge SelfSelfalignment alignment structure structure UV adhesive Si wafer Si alignment groove 20 um Self-alignment structures provide ± 1-2 um alignment despite ± 10 um placement accuracy of high-throughput tools (T. Barwicz et al., ECTC 2014, Y. Taira et al. ECTC 2015) Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: self-alignment in action Pick tip Polymer ribbon Polymer ridge Si groove Reflection on Si chip Si photonic chip 18 Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: optical demonstration Typical spectral response Polymer ribbon Standard MTP connector Active alignment 2 Automated assembly 19 Loss from fiber to silicon (dB) 1 -2 -2.5 TE TM OFC’15, Th3F.5 -3 -3.5 -4 -4.5 1.47 Polymer transparency Scattering at abrupt chip-edge transition 1.49 1.51 1.53 Wavelength (um) 1.55 1.57 • Large bandwidth compatible with CWDM • Unexpected polarization dependence at long wavelengths • Need design and assembly tweaks Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: scattering at abrupt junctions (a) (a) (b) (c) (b) adhesive SiO2 0 -0.4 -0.8 TE design TM design Worst TE Worst TM -1.6 0 • 20 0.6 1.2 1.8 Adhesive height (um) Si Taper edge scattering Taper edge loss (dB) Chip edge loss (dB) Chip edge scattering -1.2 (c) 0 -0.4 -0.8 TE design TM design Worst TE Worst TM -1.2 -1.6 2.4 0 0.6 1.2 1.8 Adhesive height (um) 2.4 Scattering at chip edge and taper edge show the correct polarization dependence and potential strength to explain excess loss (OFC’15, Th3F.5) Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Compliant polymer interface: analysis of optical performance Expected contribution At design point Worst within tolerances Fiber-to-polymer coupling 0.2 dB 0.6 dB Transition to wide polymer waveguide 0.1 dB 0.2 dB Polymer routing 0.3 dB 0.6 dB Adiabatic coupling to Si 0.4 dB 1.1 dB Total 1.0 dB 2.5 dB Excess polymer loss ~0.5 dB ~0.5 dB Scattering at abrupt junctions ~1.0 dB ~1.0 dB Experimental range ~2.4 dB to ~4.4 dB • 21 Computational tolerance analysis (adapted from IEEE Photon. J., 6600818, 2014) Rough preliminary assertion (OFC’15, Th3F.5) Rough estimate of excess loss reconciles computational predictions with experimental results excess loss not fundamental and is being addressed Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Direct flip-chip bonding of InP laser arrays in high-throughput tools. Solder induced self-alignment 10 um InP die with laser array Photonic die or wafer Pick and place, then anneal Photonic die Mode engineering for max tolerances Field profile of “strip-loaded” coupler BPSG Mode size on Si Mode size on InP 1 um Connection at maximum delocalization • • • 22 Si3N4 SOI metamaterial Tighter alignment than in fibers as inherently smaller mode Fully compatible with high-throughput assembly lines no ball lenses, etc. Solder surface tension pushes InP die at anneal on lithographically defined stops Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Direct flip-chip bonding: example implementation in test vehicle Top view micrograph of Si chip receiving structure Waveguide couplers Standoff Standoff and lateral stop Edge of recess Solder pads 200 um Flipped micrograph of mockup laser die Metal pads • 23 Lateral stop Lithographically defined stops on both Si and InP for lateral alignment Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Experimental demonstrations of solder induced self-alignment Cross-section of stops after assembly Flipped laser mock-up chip Butting Infrared view through assembly at anneal Mock-up laser pads Lateral stop on flipped chip Photonic pads Tacking fluid Vertical and lateral stop on photonic die 50 um 10 um Photonic die/wafer Cross-section of solder pads after assembly Flipped laser mock-up chip AgSn solder Photonic die • • 24 10 um Patterning limits accuracy at butting of lithographically defined stops. Solder pads offset by design for sustained force at butting (J.-W. Nah et al, ECTC 2015) Tymon Barwicz et al., © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Conclusion Silicon photonics is changing the cost structure of optical devices Cost items that were of no particular interest before can be limiting now Need disruptive advances in cost-efficiency and scalability of photonic packaging Leverage high-throughput microelectronic assembly lines for photonics Identified main challenges and their resolution tight alignment, fiber handling, etc. Short MT ferrule 25 Photonic die Photonic die Ferrule 12 fiber array Polymer lid Demonstrated cost efficient and scalable packaging working on bringing 3 solutions to the photonics community Polymer ribbon Tymon Barwicz et al., Photonic die © 2015 IBM Corporation Cost-Efficient Photonic Packaging August, 2015 Team and Acknowledgment IBM Watson, NY USA Design, fabrication, analysis IBM Research - Tokyo Ribbon-ferrule assembly Outside partners Ted Lichoulas Eddie Kimbrell Fiber stub fabrication IBM - Burlington Chip manufacturing IBM Bromont – C2MI Assembly, measurement Shotaro Takenobu Polymer ribbon fabrication Masato Shiino Custom ferrule fabrication Follow our progress Through our IBM project website Google “Silicon nanophotonic packaging.” 26 Tymon Barwicz et al., © 2015 IBM Corporation