Schematics for 1.0, 1.1, and 1.2 XS40/95 Boards

Transcription

A
XSA Pin Connections
The following tables list the pin numbers of the Spartan-II FPGA and the XC9572XL CPLD
along with the pins of the other chips that they connect to on the XSA Board. The
columns of the table are arranged as follows:
Column 1 lists the Spartan-II FPGA pin. It is left blank if there is no connection to the
FPGA for this function. Pins marked with * are useable as general-purpose I/O
through the prototyping header; pins marked with ** can be used as general-purpose
I/O only if the CPLD interface is reprogrammed as described previously; pins with no
marking cannot be used as general-purpose I/O at all.
Column 2 lists the XC9572XL CPLD pin. It is left blank if there is no connection to the
CPLD for this function.
Column 3 lists the pins of other devices on the XSA Board that are connected to the
associated FPGA and/or CPLD pin.
Column 4 lists the pin of the XSA prototyping header that is connected to the associated
FPGA and/or CPLD pin.
Columns 5–7 list the pins of devices on the Xstend Board that will connect to the FPGA
and/or CPLD when the XSA Board is inserted into an Xstend Board.
XSA BOARD V1.1, V1.2 USER MANUAL
31
FPGA
1
2
3
4
5
6
7
8
9
10
11
12*
13*
15*
18*
19*
20*
21*
22*
23*
26*
27*
28*
29*
30*
31*
32
34
37
38*
39*
40*
41*
42**
43**
44*
46*
47**
48**
49*
50**
51**
54*
56*
57*
58**
59*
60*
62*
63*
64*
65**
66*
67*
68*
69
72
74*
75*
76*
77*
78*
79*
CPLD XSA Function
+3.3V
13
SPARTAN-TCK
SDRAM-A7
SDRAM-A1
SDRAM-A6
SDRAM-A2
SDRAM-A5
GND
+2.5V
SDRAM-A3
SDRAM-A4
VGA-RED0
VGA-RED1
SPARTAN-GCK3
SPARTAN-GCK2
VGA-GREEN0
VGA-GREEN1
VGA-BLUE0
VGA-BLUE1
VGA-/HSYNC
VGA-/VSYNC
62
FLASH-A3
63
FLASH-A2, *PARPORT-S5
64
19
SPARTAN-/WRITE
15
SPARTAN-CS
15*
SPARTAN-TDI
19*
SPARTAN-TDO
16
SPARTAN-CCLK
18
SPARTAN-DOUT/BSY
2
FLASH-D0,DIN/D0,LED-S1
1
11
FLASH-/CE
57
FLASH-A10, *PARPORT-D2
12
FLASH-/OE, *PARPORT-D7
4
FLASH-D1,LED-DP
5
FLASH-D2,LED-S4
43
44
6
FLASH-D3,LED-S6
45
46
47
FLASH-A14,DIPSW1A
48
FLASH-A17,DIPSW1D
7
FLASH-D4,LED-S5
49
FLASH-/WE, *PARPORT-D6
50
FLASH-/RESET
8
FLASH-D5,LED-S3
9
FLASH-D6,LED-S2
51
FLASH-A16,DIPSW1C
52
FLASH-A15,DIPSW1B
56
58
FLASH-A7
10
FLASH-D7,LED-S0
38
SPARTAN-/INIT
39
SPARTAN-/PROGRAM
40
SPARTAN-DONE
61
FLASH-A4
60
FLASH-A5
59
FLASH-A6
PARPORT-S6
Proto. Pin
54
16
52
22
27
28
31
1
29
32
33
34
36
37
50
51
56
69
68
15
30
73
45
71
57
65
58
61
40
39
59
60
38
78
79
82
83
35
62
66
80
81
84
3
4
5
10
41
55
53
70
77
6
9
67
7
XSTend Functions
+3.3V
Xchecker-TCK
GND
RAM-A15
RLED-/DP
Xchecker-RT
RAM-A12
RAM-A10
RAM-A11
PS2/DATA
PS2/CLK
Pushbutton-/RESET
RLED-/S4
RLED-/S2
RLED-/S3
DIPSW8
Xchecker-TDI
Xchecker-RD
Xchecker-CCLK
Xchecker-DIN
RAM-A9
RLED-/S1
RAM-/CE
RAM-A13
RLED-/S5
RAM-/OE
RAM-D1
BARLED-2
RAM-D2
BARLED-3
RAM-A8
RLED-/S0
RAM-A14
RLED-/S6
RAM-D3
BARLED-4
RAM-A3
LLED-/S3
RAM-A4
LLED-/S4
RAM-A5
LLED-/S5
RAM-A6
LLED-/S6
RAM-D4
BARLED-5
RAM-WE
CODEC-LRCK
DIPSW7
RAM-D6
BARLED-7
RAM-D5
BARLED-6
RAM-A7
LLED-/DP
RAM-A0
LLED-/S0
RAM-A1
LLED-/S1
RAM-A2
LLED-/S2
RAM-D7
BARLED-8
RAM-D0
BARLED-1
Xchecker-INIT
Pushbutton-/PROGRAM Xchecker-PROG
Xchecker-DONE
CODEC-SDIN
DIPSW6
CODEC-SCLK
DIPSW5
CODEC-SDOUT DIPSW4
CODEC-MCLK
DIPSW3
Xchecker-CLKO
VGA-/VSYNC
Pushbutton-/SPARE
RAM-/LCE
DIPSW1
Xchecker-TRIG
FPGA
80*
83*
84*
85*
86*
87*
88
91
93*
94*
95
96
99
100
101
102
103
106
109
111
112
113
114
115
116
117
118
120
121
122
123
124
126
129
130
131
132
133
134
136
137
138
139
140
141
142
CPLD XSA Function
42
36
18*
30
29
28
33
32
31
27
25
24
23
22
34
20
35
53
17
MASTER_CLK
SDRAM-CLK
PS2-DATA,PUSHBUTTON
PS2-CLK
SDRAM-Q0
SDRAM-Q15
SDRAM-Q1
SDRAM-Q14
SDRAM-Q2
SDRAM-Q13
SDRAM-Q3
SPARTAN-M2
SPARTAN-M0
SPARTAN-M1
SDRAM-Q12
SDRAM-Q4
SDRAM-Q11
SDRAM-Q5
SDRAM-Q10
SDRAM-Q6
SDRAM-Q9
SDRAM-Q7
SDRAM-Q8
SDRAM-QML
SDRAM-/WE
SDRAM-QMH
SDRAM-/CAS
SDRAM-CLK
SDRAM-/RAS
SDRAM-CKE
SDRAM-/CS
SDRAM-A12
SDRAM-BA0
SDRAM-A11
SDRAM-BA1
SDRAM-A9
SDRAM-A10
SDRAM-A8
SDRAM-A0
SPARTAN-TMS
PARPORT-C1,CPLD-TCK
PARPORT-C2,CPLD-TMS
PARPORT-C3,CPLD-TDI
PARPORT-D0
PARPORT-D1
PARPORT-D2
PARPORT-D3
PARPORT-D4
PARPORT-D5
PARPORT-D6
PARPORT-D7
PARPORT-S3
PARPORT-S4
PARPORT-S5
PARPORT-S7,CPLD-TDO
PROG-OSC
Proto. Pin
8
18
19
20
23
24
13
25
26
RAM-/RCE
VGA-RED1
VGA-/HSYNC
VGA-GREEN1
VGA-RED0
VGA-GREEN0
MASTER_CLK
XSTend Functions
DIPSW2
Xchecker-RST
Xchecker-CLKI
VGA-BLUE0
VGA-BLUE1
12
14
21
17
64
Xchecker-TMS
Osc-In
B
XSA Schematics
The following pages show the detailed schematics for the XSA Board.
XSA BOARD V1.1, V1.2 USER MANUAL
32
xsa1_2.sch-1 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-2 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-3 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-4 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-5 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-6 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-7 - Mon Feb 11 08:37:20 2002
xsa1_2.sch-8 - Mon Feb 11 08:37:20 2002
xsa1_2.sch-9 - Mon Feb 11 08:37:20 2002
A
XSB Pin
Connections
The following tables list the pin numbers of the FPGA and CPLD along with the pin names
of the other chips that they connect to. These connections correspond with the pin
assignments in the user-constraint files FPGA.UCF and CPLD.UCF.
XSB BOARD V1.0 MANUAL
50
8/20/2003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
FPGA Pin
GND
VCCO
VCCINT
M1
GND
M0
VCCO
M2
VCCINT
VCCO
GND
GND
VCCINT
GND
VCCO
GND
GND
VCCO
VCCINT
FPGA Pin
Function
GND
TMS
NV-DMARQ
RS232-CTS
RS232-RTS
RS232-TD
FPGA-M2(GND)
VIDOUT-BCB8
VIDOUT-BCB9
FLASH-CE#
PB-ECS0#
NV-CS0#
NV-CS1#
NV-INTRQ
NV-IORDY
NV-IOCS16
NV-DMACK#
FPGA-M0
VIDOUT-RCR1
VIDOUT-RCR0
VIDOUT-BCB0
VIDOUT-BCB1
VIDOUT-BCB2
VIDOUT-BCB3
VIDOUT-BCB4
VIDOUT-BCB5
VIDOUT-BCB6
VIDOUT-BCB7
FPGA-M1(+3.3V)
VIDOUT-RCR5
VIDOUT-RCR4
VIDOUT-RCR3
VIDOUT-RCR2
VIDOUT-RCR8
VIDOUT-RCR7
VIDOUT-RCR6
VIDOUT-RCR9
VIDOUT-GY7
VIDOUT-GY8
VIDOUT-GY9
VIDOUT-CLK
VIDOUT-BLANK#
VIDOUT-GY3
VIDOUT-GY4
VIDOUT-GY5
VIDOUT-GY6
FPGA-BSY/DOUT/TMS
ADC-CLK
ADC-OE#
I2C-SDA
I2C-SCL
VIDOUT-VSYNC#
VIDOUT-HSYNC#
VIDOUT-GY0
VIDOUT-GY1
VIDOUT-GY2
Net Name
11
36
18
CPLD
CE#
Flash
SDRAM
SDA
SCL
Video
Dcdr.
CLK
OE#
ADC
RCR1
RCR0
BCB0
BCB1
BCB2
BCB3
BCB4
BCB5
BCB6
BCB7
RCR5
RCR4
RCR3
RCR2
RCR8
RCR7
RCR6
RCR9
GY7
GY8
GY9
CLK
BLANK#
GY3
GY4
GY5
GY6
GY0
GY1
GY2
Video
DAC
Stereo
Codec
Ether-net
USB
Serial
Port
Connections Between the FPGA and Other XSB Board Components
SRAM
DMARQ
CS0#
CS1#
INTRQ
IORDY
IOCS16#
DMACK#
IDE Intfc.
Switch
Button
CTS
RTS
TD
CE1#/CE1#/CS0#
CE2#/CE2#/CS1#
RDY-BSY/IREQ/INTRQ
WAIT#/WAIT#/IORDY
WP/IOIS16#/IOCS16#
Cmpct.
Flash
LEDs
35
36
25
26
27
28
29
30
31
32
33
34
21
22
23
24
18
19
20
17
12
13
14
15
16
8
9
10
11
3
4
5
6
7
JP5
43
JP7
SDAT
SCLK
Prog.
Osc.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
FPGA Pin
D2
VCCINT
GND
D3
VCCO
GND
VCCINT
D4
GND
D6
GND
VCCO
VCCINT
D5
GND
DONE
VCCO
PROGRAM#
INIT#
D7
VCCINT
VCCO
GND
GND
VCCINT
I/GCK1
VCCO
GND
I/GCK0
FPGA Pin
Function
GND
A0
A1
Video
Dcdr.
ADC
Video
DAC
CDTO
Stereo
Codec
USB
RDY/DTACK
CS#
SA0
FIFOADR0
SA1
FIFOADR1
IOCS16#
IREQ
Ether-net
Serial
Port
DA0
DA1
IDE Intfc.
A00
A01
Cmpct.
Flash
S1
S2
S3
RD
Switch
Button
BAR1
BAR2
LEDs
JP5
23
24
JP7
Prog.
Osc.
8
42
50
49
PB-D5
PB-A18
PB-A19
PB-WE#
PB-D14
PB-D15
PB-LB#
PB-D2
PB-D10
PB-D11
PB-D12
PB-D3
PB-D13
PB-D9
5
6
12
7
39
38
10
43
56
46
47
52
51
48
9
PB-OE#
PB-D4
PB-D8
40
D2
D3
D14
D15
LB#
D2
D10
D11
D12
D3
D13
D9
OE#
D4
D8
WE#
WE#
OE#
D4
D5
D7
A11
A12
A13
A14
A15
A16
A17
D6
A8
A9
A10
A6
A7
A2
A3
A4
A5
D5
A18
D7
A11
A12
A13
A14
A15
A16
A17
D6
A8
A9
A10
45
44
57
FPGA-DONE
A6
A7
A2
A3
A4
A5
59
58
63
62
61
60
FPGA-PROGRAM#
FPGA-INIT#
PB-D7
PB-A11
PB-A12
PB-A13
PB-A14
PB-A15
PB-A16
PB-A17
PB-D6
PB-A6
PB-A7
SDRAM-WE#
SDRAM-CAS#
SDRAM-RAS#
SDRAM-CE#
SDRAM-CKE
PB-A8
PB-A9
PB-A10
PB-A2
PB-A3
PB-A4
PB-A5
D14
D15
LDQM
D2
D10
D11
D12
D3
D13
D9
OE#
D4
D8
WE#
D5
D6
D7
A11
A12
BA0
BA1
A6
A7
WE#
CAS#
RAS#
CE#
CKE
A8
A9
A10
A2
A3
A4
A5
D14
D15
AEN/PSEN
D2
D10
D11
D12
D3
D13
D9
IORD#
D4
D8
IOWR#
D5
D6
D7
SA8
SA9
SA6
SA7
SA2
SA3
SA4
SA5
FD2
FD14
FD15
FD10
FD11
FD12
FD3
FD13
FD9
SLOE
FD4
FD8
DD2
DD14
DD15
DD10
DD11
DD12
DD3
DD13
DD9
DD4
DD8
DD5
DIOR#
DIOW#
DD6
PKTEND
FD6
FD5
SLRD
SLWR
DD7
DA2
FD7
FIFOADR2
S5-7
S5-8
S4
S5-1
S5-2
S5-3
S5-4
S5-5
S5-6
S7
D02
D14
D15
D10
D11
D12
D03
D13
D09
OE#/OE#/ATA_SEL#
D04
D08
D05
IORD#
IOWR#
WE#
REG#
D06
D07
A08
A09
A10
A06
A07
A02
A03
A04
A05
RIGHT-G
RIGHT-DP
BAR9
LEFT-C
RIGHT-C
RIGHT-D
RIGHT-E
LEFT-D
RIGHT-F
RIGHT-B
LEFT-E
RIGHT-A
LEFT-F
LEFT-G
LEFT-DP
BAR7
BAR8
BAR3
BAR4
BAR5
BAR6
21
22
5
9
17
18
19
10
20
16
3
11
15
12
41
42
4
14
34
35
36
37
38
39
40
13
31
32
33
29
30
25
26
27
28
CLKB
A0
A1
SDRAM
SRAM
SDRAM-CLK
ETHERNET-RDY/DTACK
ETHERNET-CS#
PB-A0
PB-A1
A0
A1
Flash
CLKD
1
64
CPLD
FPGA-CLK1
RS232-RD
ETHERNET-IOCS16#
ETHERNET-IREQ
Net Name
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
FPGA Pin
TCK
VCCO
VCCINT
VCCO
GND
GND
I/GCK2
GND
VCCO
I/GCK3
VCCINT
GND
GND
VCCO
VCCINT
DIN/D0
DOUT/BUSY
CCLK
VCCO
TDO
GND
TDI
CS#
WRITE#
FPGA Pin
Function
VCCO
GND
D1
15
15
19
FPGA-CS#/TDI
FPGA-CS#/TDI
FPGA-WRITE#/TDO
USB-FLAGA
USB-IFCLK
USB-VBUS
AU-CSN#
AU-BCLK
AU-MCLK
AU-LRCK
AU-SDTI
HPD3
HPD4
HPD5
HPD6
HPD0
HPD1
HPD2
VIDIN-IPD6
VIDIN-IPD7
VIDIN-IGPH
VIDIN-IGPV
VIDIN-IGP1
VIDIN-IGP0
VIDIN-ITRI
VIDIN-IDQ
VIDIN-ITRDY
FPGA-TCK
VIDIN-IPD2
VIDIN-IPD3
VIDIN-IPD4
VIDIN-IPD5
IPD6
IPD7
IGPH
IGPV
IGP1
IGP0
ITRI
IDQ
ITRDY
IPD2
IPD3
IPD4
IPD5
HPD7
IPD0
IPD1
D0
D1
UDQM
CE#
Video
Dcdr.
VIDIN-HPD7
VIDIN-IPD0
VIDIN-IPD1
D0
D1
UB#
CE#
SDRAM
D6
D7
D2
D3
D4
D5
D0
D1
D11
OVRNG
D8
D9
D10
ADC
Video
DAC
SDTO0
CSN#
BCLK
MCLK
LRCK
SDTI
CCLK
CDTI
Stereo
Codec
D0
D1
BHE#
Ether-net
FLAGA
IFCLK
DD0
CS#
INT#
READY
FLAGC
FLAGB
FD0
IDE Intfc.
DD1
Serial
Port
FD1
USB
SRAM
ICLK
D0
D1
Flash
VIDIN-ICLK
VIDIN-HPD3
VIDIN-HPD4
VIDIN-HPD5
VIDIN-HPD6
FPGA-CLK0
13
19
FPGA-WRITE#/TDO
AU-SDTO0
VIDIN-HPD0
VIDIN-HPD1
VIDIN-HPD2
2
18
16
4
CPLD
PB-D1
PB-UB#
RAM-CE#
USB-CS#
USB-INT#
USB-READY
USB-FLAGC
USB-FLAGB
PB-D0
FPGA-BSY/DOUT/TMS
FPGA-CCLK
Net Name
D00
D01
Cmpct.
Flash
Switch
Button
LEFT-A
LEFT-B
BAR10
LEDs
JP5
46
44
45
7
8
6
JP7
CLKC
Prog.
Osc.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15
16
17
18
18
19
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CPLD Pin
TDO
GND
VCCIO
GND
VCCINT
TDI
TMS
TCK
VCCIO
GND
GND
GCK1
GCK1
GCK2
GCK3
VCCINT
CPLD Pin
Function
PB-A12
PB-A10
PB-A7
PB-A6
PB-A5
PB-A4
PB-A3
PB-A2
PB-A1
PB-A18
PB-A11
PB-A9
PB-A8
PB-A13
PB-A14
PB-A17
PB-WE#
PB-A19
PB-A16
PB-A15
FPGA-INIT#
FPGA-PROGRAM#
FPGA-DONE
PP-D3
PP-C3
PP-C2
PP-C1#
PP-D2
PP-D1
PP-D0
PP-S3
PP-S5
FPGA-M0
PP-D7
PP-D6
PP-D5
PP-D4
FPGA-CS#/TDI
FPGA-CS#/TDI
FPGA-CCLK
CPLD-CLK
FPGA-BSY/DOUT/TMS
FPGA-BSY/DOUT/TMS
FPGA-WRITE#/TDO
FPGA-WRITE#/TDO
PP-S4
PB-D1
PB-D2
PB-D3
PB-D4
PB-D5
PB-D6
PB-D7
FLASH-CE#
PB-OE#
FPGA-TCK
PB-A0
PB-D0
Net Name
110
102
94
93
89
88
87
86
84
121
109
101
100
111
112
115
123
122
114
113
107
106
104
52
2
154
157
161
159
160
155
145
141
135
126
120
116
108
57
125
207
83
153
S7#
D3
C3
C2
C1#
D2
D1
D0
S3
S5
D7
D6
D5
D4
S4
Parallel
Port
A12
A10
A7
A6
A5
A4
A3
A2
A1
A12
A10
A7
A6
A5
A4
A3
A2
A1
A16
A15
A16
A15
A12
A10
A7
A6
A5
A4
A3
A2
A1
WE#
A11
A9
A8
BA0
BA1
OE#
OE#
A11
A9
A8
A13
A14
A17
WE#
D1
D2
D3
D4
D5
D6
D7
A0
D0
SDRAM
D1
D2
D3
D4
D5
D6
D7
A0
D0
SRAM
A18
A11
A9
A8
A13
A14
A17
WE#
D1
D2
D3
D4
D5
D6
D7
CE#
OE#
A0
D0
Flash
CDTI
CDTO
CCLK
Stereo
Codec
SA7
SA6
SA5
SA4
SA3
SA2
SA1
IOWR#
SA9
SA8
IORD#
D1
D2
D3
D4
D5
D6
D7
SA0
D0
Ether-net
FIFOADR2
FIFOADR1
SLWR
PKTEND
SLRD
SLOE
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FIFOADR0
FD0
USB
DA2
DA1
DIOW#
DIOR#
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DA0
DD0
IDE Intfc.
Connections Between the CPLD and Other XSB Board Components
FPGA Pin
Switch
Button
A10
A07
A06
A05
A04
A03
A02
A01
REG#
WE#
IOWR#
A09
A08
IORD#
S5-1
S3
S5-8
S5-5
S5-4
S5-7
S4
S2
S1
S5-2
S5-3
S5-6
S7
OE#/OE#/ATA_SEL#
D01
D02
D03
D04
D05
D06
D07
Cmpct.
Flash
A00
D00
LEDs
BAR8
BAR7
BAR6
BAR5
BAR4
BAR3
BAR2
LEFT-B
LEFT-C
LEFT-D
LEFT-E
LEFT-F
LEFT-G
LEFT-DP
BAR1
LEFT-A
35
33
30
29
28
27
26
25
24
41
34
32
31
36
37
40
4
42
39
38
3
8
9
10
11
12
13
14
23
7
JP7
XBUF
Prog.
Osc.
B
XSB Schematics
The following pages show the detailed schematics for the XSB Board.
XSB BOARD V1.0 MANUAL
51
8/20/2003
• Table 4: XS40 Board pin descriptions.
XS40 Pin
25
26
24
20
23
18
19
13
44
45
46
47
48
49
32
34
37
36
29
14
7
8
9
6
77
70
66
67
69
68
62
27
41
40
39
38
35
81
80
10
59
57
51
56
50
58
60
28
16
3
4
5
78
79
82
83
84
61
65
75
Connects to…
S0 BLUE0
S1 BLUE1
S2 GREEN0
S3 GREEN1
S4 RED0
S5 RED1
S6 HSYNCB
CLK
PC D0
PC D1
PC D2
PC D3
PC D4
PC D5
PC D6
PC D7
XTAL1
RST
ALEB
PSENB
P1 0
P1 1
P1 2
P1 3
P1 4 PC S4
P1 5 PC S3
P1 6 PC S5
P1 7 VSYNCB
P3 1(TXD) PC S6
P3 4(T0) PS/2 CLK
P3 6(WRB) WEB
P3 7(RDB)
P0 0(AD0) D0
P0 1(AD1) D1
P0 2(AD2) D2
P0 3(AD3) D3
P0 4(AD4) D4
P0 5(AD5) D5
P0 6(AD6) D6
P0 7(AD7) D7
P2 0(A8) A8
P2 0(A9) A9
P2 0(A10) A10
P2 0(A11) A11
P2 0(A12) A12
P2 0(A13) A13
P2 0(A14) A14
P2 0(A15) A15
A16
A0
A1
A2
A3
A4
A5
A6
A7
OEB
CEB
PC S7
XS40 BOARD V1.4 USER MANUAL
Description
These pins drive the individual segments of the LED display (S0-S6). They also drive
the color and horizontal sync signals for a VGA monitor.
An input driven by the 100 MHz programmable oscillator
These pins are driven by the data output pins of the PC parallel port. Clocking signals
can only be reliably applied through pins 44 and 45 since these have additional
hysterisis circuitry. Pins 32 and 34 are mode signals for the FPGA so you must adjust
your design to account for the way that the Foundation tools handle these pins. pins
32 and 34 are not usable as general-purpose I/O on the Spartan FPGA on the XSP
Board.
Pin that drives the uC clock input
Pin that drives the uC reset input
Pin that monitors the uC address latch enable
Pin that monitors the uC program store enable
These pins connect to the pins of Port 1 of the uC. Some of the pins are also
connected to the status input pins of the PC parallel port. Pin 67 drives the vertical
sync signal for a VGA monitor.
These pins connect to some of the pins of Port 3 of the uC. The uC has specialized
functions for each of the port pins indicated in parentheses. Pin 62 connects to the
data write pin of the uC and the write-enable pin of the SRAM. Pin 69 connects to a
status input pin of the PC parallel port and the PS/2 data line. Pin 68 connects to the
PS/2 clock line
These pins connect to Port 0 of the uC which is also a multiplexed address/data port.
These pins also connect to the data pins of the SRAM.
These pins connect to Port 2 of the uC which also outputs the upper address byte.
These pins also connect to the upper address bits of the SRAM. Pins 28 and 16 are
connected to the 128 KB SRAM address pins only on the XS40+ Board. Pins 28 and
16 do not connect to the 32 KB SRAM on the XS40 Board.
These pins drive the 8 lower address bits of the SRAM.
Pin that drives the SRAM output enable
Pin that drives the SRAM chip enable
Pin that drives a status input pin of the PC parallel port
18
P C P a ra lle l P o rt
S tatu s In p u ts
K B _D A TA
V SYN C
H SYN C
RED 1
RED 0
G REEN 1
G REEN 0
B LU E 1
B LU E 0
S6
S5
S3
S2
S0
S6
S4 S5
S4
S3
S1 S2
S1
S0
19
18
23
20
24
26
25
37
36
29
14
67
66
70
77
6
9
8
7
21
10
33
32
9
8
7
6
5
4
3
2
X TA L 1
RST
A LE
PSEN
P 1 .7
P 1 .6
P 1 .5
P 1 .4
P 1 .3
P 1 .2
P 1 .1
P 1 .0
27
19
18
17
16
15
14
13
11
36
37
38
39
40
41
42
43
31
30
29
28
27
26
25
24
P 3 .7
P 3 .6
P 3 .5
P 3 .4
P 3 .3
P 3 .2
P 3 .1
P 3 .0
P 0 .7
P 0 .6
P 0 .5
P 0 .4
P 0 .3
P 0 .2
P 0 .1
P 0 .0
P 2 .7
P 2 .6
P 2 .5
P 2 .4
P 2 .3
P 2 .2
P 2 .1
P 2 .0
13
14
15
21
20
19
18
17
D7
D6
D5
D4
D3
D2
D1
D0
84
83
82
79
78
5
4
3
2
31
6
27
4
5
3
28
26
9
23
10
11
12
7
25
8
A 1 6 **
A 1 5 **
A 14
A 13
A 12
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
62
61
65
29
24
22
W E
OE
C19
E
68
75
69
D a ta O u tp u ts
100 M H z
P ro g . O sc.
13
34*
32*
49
48
47
46
45
44
P C _D 7 *
P C _D 6 *
P C _D 5
P C _D 4
P C _D 3
P C _D 2
P C _D 1
P C _D 0
* = n o t c o n n e c te d o n X S P B o a rd
** = ap p lie s to X S 4 0 + B o a rd
XS40 BOARD V1.4 USER MANUAL
FP G A
7 -S e g m e n t L E D
10
80
81
35
38
39
40
41
28
60
58
50
56
51
57
59
16
8031 uC
K B _C L K
(R D )
(W R )
(T 1)
(T 0)
(IN T 1 )
(IN T 0 )
(T X D )
(R X D )
(A 7/D 7 )
(A 6/D 6 )
(A 5/D 5 )
(A 4/D 4 )
(A 3/D 3 )
(A 2/D 2 )
(A 1/D 1 )
(A 0/D 0 )
(A 15 )
(A 14 )
(A 13 )
(A 12 )
(A 11 )
(A 10 )
(A 9)
(A 8)
3 2 K /1 2 8 K ** x 8 S R A M
V G A In p u ts
P S /2 P o rt
P C _S 7
P C _S 6
P C _S 5
P C _S 4
P C _S 3
xs40v1_4.sch-1 - Mon Sep 6 13:53:50 1999
2 +5V
3
LSB0
4
LSB1
5
LSB2
6
DIPSW4
7
DIPSW1
8
DIPSW2
9
DIPSW3
10
DB8
13
14
15
16
17
18
S5
19
S6
20
S3
23
S4
24
S2
25
S0
26
S1
27
28
RDPB
29
30
32
34
35
DB5
36
37
RESETB
38
DB4
39
DB3
40
DB2
41
DB1
44
45
46
47
48
49
50
RSB4
51
RSB2
52 GND
54 5.0V/3.3V
55
PROGRAM
56
RSB3
57
RSB1
58
RSB5
59
RSB0
60
RSB6
61
62
65
66
DIPSW7
67
SPAREB
68
69
DIPSW8
70
DIPSW6
71
72
73
75
77
DIPSW5
78
LSB3
79
LSB4
80
DB7
81
DB6
82
LSB5
83
LSB6
84
LDPB
Oscillator
PC Parallel
Port
8051 uC
RAMs
Stereo Codec
©1999 XESS Corporation
PS/2 Interface
VGA Interface
LEDs
Push-buttons
DIP Switch
Power/ GND
XS40 Pin
(J1,J3,J18)
XStend/XS40 Programmer's Model
A0
A1
A2
LCEB
RCEB
D7
SDOUT P1.3
P1.0
P1.1
MCLK P1.2
P0.7
CLK
PSENB
RED1
HSYNCB
GREEN1
RED0
GREEN0
BLUE0
BLUE1
P3.7 (RD_)
P2.7
ALEB
PC_D6
PC_D7
D4
P0.4
RST
XTAL1
P0.3
P0.2
P0.1
P0.0
D3
D2
D1
D0
CCLK
CDIN
CSB
PC_D0
PC_D1
PC_D2
PC_D3
PC_D4
PC_D5
A12
A10
P2.4
P2.2
A11
A9
A13
A8
A14
OEB
WEB
CEB
P2.3
P2.1
P2.5
P2.0
P2.6
P3.6 (WR_)
LRCK
SDIN
P1.6
PC_S5
P1.7
P3.4 (T0)
P3.1 (TXD)
PC_S6
P1.5
PC_S3
SCLK
P1.4
VSYNCB
KB_CLK
KB_DATA
A3
A4
D6
D5
A5
A6
A7
P0.6
P0.5
PC_S7
PC_S4
Function
+5V power source
Left LED segment; RAM address line
DIP switch; codec serial data output; uC I/O
DIP switch; left RAM chip-enable, uC I/O port
DIP switch; right RAM chip-enable, uC I/O port
DIP switch; codec master clock; uC I/O port
LED; RAM data line; uC muxed address/data line
XS Board oscillator
uC program store-enable
JTAG TDI; DIN
JTAG TCK; CCLK
JTAG TMS
XS Board LED segment; VGA color signal
XS Board LED segment; VGA horiz. sync.
uC read line
Right LED decimal-point; uC I/O port
uC address-latch-enable
Serial EEPROM chip-enable
PC parallel port data output
uC reset
Pushbutton; uC clock
Codec control line; PC parallel port data output
Right LED segment; RAM address line; uC I/O port
Power supply ground
5V/3.3V power supply (4000E/4000XL)
XS40 configuration control
RAM output-enable
RAM write-enable; uC I/O port
XS Board RAM chip-enable
DIP switch; codec left-right channel switch; uC I/O port; PC parallel port status in
Pushbutton; VGA vert. sync.; uC I/O port
PS/2 keyboard clock; uC I/O port
DIP switch; PS/2 keyboard serial data; uC I/O port; PC parallel port status input
DIP switch; codec serial input data; uC I/O port; PC parallel port status input
JTAG TDI; DIN
JTAG TDO; DOUT
JTAG TCK; CCLK
JTAG TDO; DOUT; PC parallel port status input
DIP switch; codec serial I/O clock; uC I/O port; PC parallel port status input
Left LED decimal-point; RAM address line
XS95 Pin
Connects to…
21
23
19
17
18
14
15
24
9
46
47
48
50
51
52
81
80
10
45
20
13
6
7
11
5
72
71
66
67
31
70
69
68
26
33
63
32
44
43
41
40
39
37
36
35
58
56
54
55
53
57
61
34
74
75
79
82
84
1
3
83
2
62
65
4
12
25
76
77
S0,BLUE0
S1,BLUE1
S2,GREEN0
S3,GREEN1
S4,RED0
S5,RED1
S6,HSYNCB
DP,VSYNCB
CLK
PC D0
PC D1
PC D2
PC D3
PC D4
PC D5
PC D6
PC D7
XTAL1
RST
ALEB
PSENB
P1.0, PC C0
P1.1
P1.2
P1.3
P1.4,PC S4
P1.5,PC S3
P1.6,PC S5
P1.7
P3.0(RXD)
P3.1(TXD), PC S6, KB DATA
P3.2(INTB0)
P3.3(INTB1)
P3.4(T0), KB CLK
P3.5(T1)
P3.6(WRB), WEB
P3.7(RDB)
P0.0(AD0), D0
P0.1(AD1), D1
P0.2(AD2), D2
P0.3(AD3), D3
P0.4(AD4), D4
P0.5(AD5), D5
P0.6(AD6), D6
P0.7(AD7), D7
P2.0(A8), A8
P2.0(A9), A9
P2.0(A10), A10
P2.0(A11), A11
P2.0(A12), A12
P2.0(A13), A13
P2.0(A14), A14
P2.0(A15),A15
A16
A0
A1
A2
A3
A4
A5
A6
A7
OEB
CEB
FREE0
FREE1
FREE2
FREE3
FREE4
XS95 V1.3 USER MANUAL
Description
These pins drive the individual segments of the LED display (S0-S6 and DP). They also drive
the color, horizontal, and vertical sync signals for a VGA monitor.
An input driven by the 100 MHz programmable oscillator.
These pins are driven by the data output pins of the PC parallel port. Clocking signals can only
be reliably applied through pins 46 and 47 since these have additional hysterisis circuitry.
Pin that drives the uC clock input
Pin that drives the uC reset input
Pin that monitors the uC address latch enable
Pin that monitors the uC program store enable
These pins connect to the pins of Port 1 of the uC. Some of the pins are also connected to the
status input pins of the PC parallel port. The P1.0 port pin of the uC is also connected to the C0
control output from the parallel port.
These pins connect to the pins of Port 3 of the uC. The uC has specialized functions for each
of the port pins indicated in parentheses. Pin 63 connects to the data write pin of the uC and
the write-enable pin of the SRAM. Pins 26 and 70 connect to the clock and data lines of the
PS/2 port. Pin 70 connects to a status input pin of the PC parallel port.
These pins connect to Port 0 of the uC which is also a multiplexed address/data port. These
pins also connect to the data pins of the SRAM.
These pins connect to Port 2 of the uC which also outputs the upper address byte. These pins
also connect to the upper address bits of the SRAM. Pins 34 and 74 are connected to the 128
KB SRAM address pins only on the XS95+ Board. Pins 34 and 74 do not connect to the 32 KB
SRAM on the XS95 Board.
These pins drive the 8 lower address bits of the SRAM.
Pin that drives the SRAM output enable.
Pin that drives the SRAM chip enable.
These pins are not connected to other devices and can be used as general purpose I/O.
17
P S /2 P o rt
P C _S 6
P C _S 5
P C _S 4
P C _S 3
K B _D A T A
V SYN C
H SYN C
RED 1
RED 0
G REEN 1
G REEN 0
B LU E 1
B LU E 0
DP
S6
S5
S3 S4 S4
S3
S0 S1 S2
S1
D P S0
S6
S5
S2
24
15
14
18
17
19
23
21
P C _D 7
P C _D 6
P C _D 5
P C _D 4
P C _D 3
P C _D 2
P C _D 1
P C _D 0
Fre e P in s
D ata O u tp u ts
100 M H z
P ro g . O sc.
9
80
81
52
51
50
48
47
46
77
76
25
12
4
C P LD
7 -S e g m e n t L E D
10
45
20
13
67
66
71
72
5
11
7
6
21
10
33
32
9
8
7
6
5
4
3
2
X TA L 1
RST
A LE
PSEN
P 1 .7
P 1 .6
P 1 .5
P 1 .4
P 1 .3
P 1 .2
P 1 .1
P 1 .0
32
19
18
17
16
15
14
13
11
36
37
38
39
40
41
42
43
31
30
29
28
27
26
25
24
P 3 .7
P 3 .6
P 3 .5
P 3 .4
P 3 .3
P 3 .2
P 3 .1
P 3 .0
P 0 .7
P 0 .6
P 0 .5
P 0 .4
P 0 .3
P 0 .2
P 0 .1
P 0 .0
P 2 .7
P 2 .6
P 2 .5
P 2 .4
P 2 .3
P 2 .2
P 2 .1
P 2 .0
2
83
3
1
84
82
79
75
13
14
15
21
20
19
18
17
2
31
6
27
4
5
3
28
26
9
23
10
11
12
7
25
8
D7
D6
D5
D4
D3
D2
D1
D0
A 16*
A 15*
A 14
A 13
A 12
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
63
62
65
29
24
22
W E
OE
CE
33
26
68
69
70
31
35
36
37
39
40
41
43
44
34
61
57
53
55
54
56
58
74
(R D )
(W R )
(T 1 )
(T 0 )
(IN T 1 )
(IN T 0 )
(T X D )
(R X D )
(A 7 /D 7 )
(A 6 /D 6 )
(A 5 /D 5 )
(A 4 /D 4 )
(A 3 /D 3 )
(A 2 /D 2 )
(A 1 /D 1 )
(A 0 /D 0 )
(A 1 5 )
(A 1 4 )
(A 1 3 )
(A 1 2 )
(A 1 1 )
(A 1 0 )
(A 9 )
(A 8 )
* = ap p lie s to X S 9 5 + B o a rd
XS95 V1.3 USER MANUAL
8031 uC
K B _C L K
18
3 2 K /1 2 8 K * x 8 S R A M
S tatu s In p u ts
V G A In p u ts
C o n tro l O u tp u t C 0
1
2
3
4
5
6
7
9
10
11
12
13
14
15
17
18
19
20
21
23
25
26
28
29
30
31
32
33
34
35
36
37
39
40
41
43
44
45
46
47
48
49 GND
50
51
52
53
54
55
56
57
58
59
61
62
63
65
66
68
69
70
71
72
74
75
76
77
78 +5V
79
80
81
82
83
84
24,67
LSB0
LSB1
LSB2
Oscillator
PC Parallel
Port
8051 Uc
Stereo Codec
RAMs
PS/2 Interface
©1999 XESS Corporation
VGA Interface
LEDs
Push-buttons
DIP Switch
Power/ GND
XS95 Pins
(J2)
XStend/XS95 Programmer's Model
A4
A7
A5
DIPSW4
DIPSW1
DIPSW2
LCEB
RCEB
SDOUT P1.3
P1.0
P1.1
CLK
RESETB
DIPSW3
MCLK
XTAL1
P1.2
PSENB
S5
S6
S3
S4
S2
RED1
HSYNCB
GREEN1
RED0
GREEN0
S0
S1
BLUE0
BLUE1
ALEB
KB_CLK
RDPB
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
P3.4 (T0)
D7
D6
D5
D4
D3
D2
D1
D0
CCLK
CDIN
CSB
P3.0 (RXD)
P3.7 (RD_)
P3.5 (T1)
P2.7
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
RST
PC_D0
PC_D1
PC_D2
PC_D3
PC_D4
PC_D5
RSB4
RSB2
RSB3
RSB1
RSB5
RSB0
A12
A10
A11
A9
A13
A8
P2.4
P2.2
P2.3
P2.1
P2.5
P2.0
RSB6
A14
OEB
WEB
CEB
P2.6
DIPSW7
P3.6 (WR_)
LRCK
DIPSW8
DIPSW6
DIPSW5
KB_DATA
SDIN
SCLK
LSB3
A0
LSB4
A1
P1.6
PC_S5
P3.3 (INT1_)
P3.2 (INT0_)
P3.1 (TXD)
PC_S6
P1.5
PC_S3
P1.4
PC_S4
PC_D7
PC_D6
LSB5
LSB6
LDPB
SPAREBDP
A2
A6
A3
VSYNCB
P1.7
Function
Uncommitted XS95 I/O pin
DIP switch; codec serial data output; uC I/O
DIP switch; left RAM chip-enable, uC I/O port
DIP switch; right RAM chip-enable, uC I/O port
XS Board oscillator
Pushbutton; uC clock
DIP switch; codec master clock; uC I/O port
uC program store-enable
XS Board LED segment; VGA horiz. sync.
uC address-latch-enable
PS/2 keyboard clock; uC I/O port
JTAG TDI; DIN
JTAG TMS
JTAG TCK; CCLK
uC I/O port
uC I/O port
uC I/O port
Right LED decimal-point; RAM address line; uC I/O port
uC reset
Power supply ground
JTAG TDO; DOUT
RAM output-enable
RAM write-enable; uC I/O port
XS Board RAM chip-enable
DIP switch; codec left-right channel select; uC I/O port; PC parallel port status in
uC I/O port
uC I/O port
DIP switch; PS/2 keyboard serial data; uC I/O port; PC parallel port status input
DIP switch; codec serial input data; uC I/O port; PC parallel port status input
DIP switch; codec serial clock; uC I/O port; PC parallel port status input
+5V power source
Left LED decimal-point; RAM address line
Pushbutton; XS Board LED decimal-point; VGA horiz. sync.; uC I/O port
xs95v1_3.sch-1 - Tue Jul 27 00:52:18 1999
Appendix
A
XStend Schematics
xst1_3_2.sch-1 - Mon Nov 6 17:09:31 2000
xst1_3_2.sch-2 - Mon Nov 6 17:09:32 2000
xst1_3_2.sch-3 - Mon Nov 6 17:09:33 2000
xst1_3_2.sch-4 - Mon Nov 6 17:09:34 2000
xst1_3_2.sch-5 - Mon Nov 6 17:09:35 2000
A
XStend + XSA Pin
Connections
The following table lists the connections between the XStend Board components and the
components of the XSA Board. The columns of the table are arranged as follows:
Column 1 lists the pin number for the Spartan-II FPGA on the XSA Board. It is left blank if
there is no connection to the FPGA for this function. Pins marked with * are useable
as general-purpose I/O through the prototyping header; pins marked with ** can be
used as general-purpose I/O only if the CPLD interface is reprogrammed so it doesn’t
drive this pin; pins with no marking cannot be used as general-purpose I/O at all.
Column 2 lists the pin number for the XC9572XL CPLD on the XSA Board. It is left blank
if there is no connection to the CPLD for this function.
Column 3 lists the functions of other devices on the XSA Board that are connected to the
associated FPGA and/or CPLD pin.
Column 4 lists the pin of the XSA prototyping header that is connected to the associated
FPGA and/or CPLD pin.
Columns 5–7 list the pins of devices on the XStend Board that will connect to the FPGA
and/or CPLD when the XSA Board is inserted into an XStend Board.
XSTEND BOARD V2.0 USER MANUAL
21
FPGA
1
2
3
4
5
6
7
8
9
10
11
12*
13*
15*
18*
19*
20*
21*
22*
23*
26*
27*
28*
29*
30*
31*
32
34
37
38*
39*
40*
41*
42**
43**
44*
46*
47**
48**
49*
50**
51**
54*
56*
57*
58**
59*
60*
62*
63*
64*
65**
66*
67*
68*
69
72
74*
75*
76*
77*
78*
79*
80*
83*
84*
85*
86*
CPLD XSA Function
+3.3V
13
SPARTAN-TCK
SDRAM-A7
SDRAM-A1
SDRAM-A6
SDRAM-A2
SDRAM-A5
GND
+2.5V
SDRAM-A3
SDRAM-A4
VGA-RED0
VGA-RED1
SPARTAN-GCK3
SPARTAN-GCK2
VGA-GREEN0
VGA-GREEN1
VGA-BLUE0
VGA-BLUE1
VGA-/HSYNC
VGA-/VSYNC
62
FLASH-A3
63
64
19
SPARTAN-/WRITE
15
SPARTAN-CS
15*
SPARTAN-TDI
19*
SPARTAN-TDO
16
SPARTAN-CCLK
18
SPARTAN-DOUT/BSY
2
FLASH-D0,DIN/D0,LED-S1
1
11
FLASH-/CE
57
12
FLASH-/OE, *PARPORT-D7
4
FLASH-D1,LED-DP
5
FLASH-D2,LED-S4
43
44
6
FLASH-D3,LED-S6
45
46
47
FLASH-A14,DIPSW1A
48
FLASH-A17,DIPSW1D
7
FLASH-D4,LED-S5
49
FLASH-/WE, *PARPORT-D6
50
FLASH-/RESET
8
FLASH-D5,LED-S3
9
FLASH-D6,LED-S2
51
FLASH-A16,DIPSW1C
52
FLASH-A15,DIPSW1B
56
58
FLASH-A7
10
FLASH-D7,LED-S0
38
SPARTAN-/INIT
39
SPARTAN-/PROGRAM
40
SPARTAN-DONE
61
FLASH-A4
60
FLASH-A5
59
FLASH-A6
PARPORT-S6
Proto. Pin
54
16
52
22
27
28
31
1
29
32
33
34
36
37
50
51
56
69
68
15
30
73
45
71
57
65
58
61
40
39
59
60
38
78
79
82
83
35
62
66
80
81
84
3
4
5
10
41
55
53
70
77
6
9
67
7
8
18
19
20
23
XStend V2.0 Functions
+3.3V
GND
RAM-A0
RAM-A10
RAM-A11
PUSHB4
PUSHB3
LED2-B
LED2-E
LED2-G
DIPSW1
IDE_DMARQ
/USB_INT
USB_SUSPEND
/IDE_RESET
RAM-A1
RAM-A16
RAM-A9
LED2-DP
BARLED-9
LED2-C
/IDE_DMACK
IDE_IORDY
IDE_INTRQ
RAM-A8
/RAM-OE
RAM-D6
RAM-D5
RAM-A13
RAM-A15
RAM-D4
RAM-A14
RAM-A12
RAM-A7
RAM-A6
RAM-D3
/RAM-WE
AUDIO_LRCK
RAM-D0
RAM-D1
RAM-A5
RAM-A4
RAM-A3
RAM-A2
RAM-D2
RAM-D7
LED2-F
IDE_D8
IDE_D9
IDE_D1
IDE_D2
IDE_D10
IDE_D11
IDE_D3
IDE_D12
IDE_D13
/IDE_CS0
/IDE_CS1
IDE_D4
IDE_D14
AUDIO_SDTI
AUDIO_SCLK
AUDIO_SDTO
AUDIO_MCLK
/RAM_CE
BARLED-2
BARLED-3
LED2-D
LED2-A
BARLED-4
LED1-G
LED1-B
LED1-F
LED1-A
BARLED-5
DIPSW2
BARLED-10
BARLED-7
BARLED-6
LED1-DP
LED1-D
LED1-C
DIPSW5
BARLED-8
BARLED-1
PUSHB1
DIPSW3
DIPSW4
LED1-E
DIPSW6
PUSHB2
DIPSW8
DIPSW7
IDE_D6,RS232_RD
IDE_D5, RS232_CTS
IDE_DA2
IDE_DA0
IDE_D15
IDE_DA1
IDE_D7
IDE_D0
RS232_RTS
RS232_TD
USB_SCL
USB_SDA
/IDE_DIOR
FPGA
87*
88
91
93*
94*
95
96
99
100
101
102
103
106
109
111
112
113
114
115
116
117
118
120
121
122
123
124
126
129
130
131
132
133
134
136
137
138
139
140
141
142
CPLD XSA Function
42
36
18*
30
29
28
33
32
31
27
25
24
23
22
34
20
35
53
17
MASTER_CLK
SDRAM-CLK
PS2-DATA,PUSHBUTTON
PS2-CLK
SDRAM-Q0
SDRAM-Q15
SDRAM-Q1
SDRAM-Q14
SDRAM-Q2
SDRAM-Q13
SDRAM-Q3
SPARTAN-M2
SPARTAN-M0
SPARTAN-M1
SDRAM-Q12
SDRAM-Q4
SDRAM-Q11
SDRAM-Q5
SDRAM-Q10
SDRAM-Q6
SDRAM-Q9
SDRAM-Q7
SDRAM-Q8
SDRAM-QML
SDRAM-/WE
SDRAM-QMH
SDRAM-/CAS
SDRAM-CLK
SDRAM-/RAS
SDRAM-CKE
SDRAM-/CS
SDRAM-A12
SDRAM-BA0
SDRAM-A11
SDRAM-BA1
SDRAM-A9
SDRAM-A10
SDRAM-A8
SDRAM-A0
SPARTAN-TMS
PARPORT-C1,CPLD-TCK
PARPORT-C2,CPLD-TMS
PARPORT-C3,CPLD-TDI
PARPORT-D0
PARPORT-D1
PARPORT-D2
PARPORT-D3
PARPORT-D4
PARPORT-D5
PARPORT-D6
PARPORT-D7
PARPORT-S3
PARPORT-S4
PARPORT-S5
PARPORT-S7,CPLD-TDO
PROG-OSC
Proto. Pin
24
13
XStend V2.0 Functions
/IDE_DIOW
MASTER_CLK
25
26
12
14
21
17
64
Osc-In
USB_CLKOUT
B
XSA Schematics
The following pages show the detailed schematics for the XSA Board.
XSTEND BOARD V2.0 USER MANUAL
22
9/20/2002 02:54:12p C:/xesscorp/EAGLE_PCB/projects/XST-2/XST-2.sch (Sheet: 1/7)
A
XSV Pin
Connections
The following tables list the pin numbers of the Virtex FPGA and the XC95108 CPLD
along with the pin names of the other chips that they connect to. These connections
correspond with the pin assignments in the user-constraint files VIRTEX.UCF and
CPLD.UCF.
XSV BOARD V1.1 MANUAL
39
9/21/2001
Connections Between the Virtex FPGA and the Other XSV Board Components
Virtex FPGA
1
GND
2
TMS
3
4
5
6
7
8
GND
9
10
11
12
13
14
GND
15
VCCO
16
VCCINT
17
18
19
20
21
22
GND
23
24
25
26
27
28
29
GND
30
VCCO
31
32
VCCINT
33
34
35
36
37
GND
38
39
40
41
42
43
VCCINT
44
VCCO
45
GND
XC95108
CPLD
35
LEDs
S3 (left)
Switches
Flash
RAM
Ethernet
Video
Decoder RAMDAC
Codec
RAM
PS/2
USB
D3
Parallel
Port
Serial
Port
Prog.
Osc.
Xchecker
TMS
MCLK
LRCK
SCLK
SDIN
SDOUT
FDS/MDINT
MDC
MDIO
CRS
COL
TRSTE
TxEN
RxDV
TxERR
RxERR
RS2
RS1
TxD4
RS0
RxD4
RxD3
RxD2
RxD1
D7
D6
D5
RxD0
TxD3
TxD2
TxD1
TxD0
D4
D3
D2
D1
D0
CLK
VM
VP
RCV
/OE
VPO
DATA
VMO
Virtex FPGA
46
47
48
49
50
51
GND
52
53
54
55
56
57
58
M1
59
GND
60
M0
61
VCCO
62
M2
63
64
65
66
67
68
69
GND
70
71
72
73
74
75
GND
76
VCCO
77
VCCINT
78
79
80
81
82
83
GND
84
85
86
87
88
VCCINT
89
PGCK
90
VCCO
XC95108
CPLD
LEDs
Switches
Flash
RAM
Ethernet
Video
Decoder RAMDAC
/WR
/RD
/HSYNC
/VSYNC
/BLANK
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
Prog.
Osc.
Xchecker
PIXELCLK
A9 (right)
A8 (right)
A7 (right)
A6 (right)
A5 (right)
14
13
15
A4 (right)
A3 (right)
A2 (right)
A1 (right)
A0 (right)
/WE (right)
P0
P1
P2
P3
P4
D0 (right)
D1 (right)
D2 (right)
D3 (right)
D4 (right)
P5
P6
P7
D5 (right)
D6 (right)
D7 (right)
D8 (right)
D9 (right)
D10 (right)
D11 (right)
D12 (right)
D13 (right)
22
CLK
CLKI
Virtex FPGA
91
GND
92
PGCK
93
94
95
96
97
98
GND
99
100
101
102
103
104
VCCINT
105
VCCO
106
GND
107
108
109
110
111
112
GND
113
114
115
116
117
118
119
GND
120
DONE
121
VCCO
122
/PROG
123
/INIT
124
D7
125
126
127
128
129
GND
130
131
132
133
134
D6
135
GND
XC95108
CPLD
LEDs
Switches
Flash
RAM
Ethernet
Video
Decoder RAMDAC
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
Prog.
Osc.
Xchecker
LLCK
D14 (right)
D15 (right)
/OE (right)
A18 (right)
A17 (right)
A16 (right)
A15 (right)
A14 (right)
A13 (right)
A12 (right)
A11 (right)
A10 (right)
/CE (right)
RTS1
RTS0
RTC0
SCL
SDA
VPO0
VPO1
VPO2
10
DONE
11
9
40
/PROGRAM
/INIT
S0 (right)
D7
VPO3
VPO4
VPO5
VPO6
VPO7
43
16
17
39
BAR8
S1 (right)
S2 (right)
S6 (left)
/WE
A0
A1
D6
RT
RD
XC95108
CPLD
Virtex FPGA
136
VCCO
137
VCCINT
138
D5
139
140
141
142
143
GND
144
145
D4
146
147
148
VCCINT
149
150
VCCO
151
GND
152
153
154
155
156
D3
157
158
GND
159
160
161
162
163
D2
164
VCCINT
165
VCCO
166
GND
167
D1
168
169
170
171
172
GND
173
174
175
176
177
D0/DIN
BUSY/DOUT
178
179
CCLK
180
VCCO
37
18
59
19
58
20
36
56
23
LEDs
S5 (left)
S3 (right)
DIPSW8
S4 (right)
DIPSW7
S5 (right)
S4 (left)
DIPSW6
S6 (right)
55
24
54
25
53
35
27
52
28
50
29
34
Switches
DIPSW5
BAR0
DIPSW4
BAR1
DIPSW3
S3 (left)
BAR2
DIPSW2
BAR3
DIPSW1
BAR4
S2 (left)
33
49
30
46
41
S1 (left)
BAR6
BAR5
42
BAR7
Flash
RAM
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
Prog.
Osc.
Xchecker
TRIG
CLKO
A4
D4
A18
A5
RST
A17
A6
A16
A7
A15
D3
A8
TMS
A14
A9
A13
A10
D2
D1
A12
A11
/CE
RDY
BAR9
S0 (left)
Video
Decoder RAMDAC
D5
A2
A20
A3
A19
TDI
/OE
SW1
SW2
SW3
32
6
12
Ethernet
SUSPND
D0
DIN
CCLK
Virtex FPGA
181
TDO
182
GND
183
TDI
184
/CS
185
/WR
186
187
188
189
190
GND
191
192
193
194
195
196
GND
197
VCCO
198
VCCINT
199
200
201
202
203
204
GND
205
206
207
208
209
210
PGCK
211
GND
212
VCCO
213
PGCK
214
VCCINT
215
216
217
218
219
GND
220
221
222
223
224
225
VCCINT
XC95108
CPLD
LEDs
34
S2 (left)
33
8
7
Switches
S1 (left)
Flash
RAM
D2
Ethernet
Video
Decoder RAMDAC
Codec
RAM
D1
PS/2
USB
Parallel
Port
Serial
Port
Prog.
Osc.
Xchecker
TDI
SW4
/CE (left)
A9 (left)
A8 (left)
A7 (left)
A6 (left)
A5 (left)
A4 (left)
A3 (left)
A2 (left)
A1 (left)
A0 (left)
/WE (left)
D0 (left)
D1 (left)
D2 (left)
D3 (left)
D4 (left)
D5 (left)
D6 (left)
TxCLK
RxCLK
D7 (left)
D8 (left)
D9 (left)
D10 (left)
D11 (left)
D12 (left)
D13 (left)
D14 (left)
D15 (left)
Virtex FPGA
226
VCCO
227
GND
228
229
230
231
232
233
GND
234
235
236
237
238
239
TCK
240
VCCO
XC95108
CPLD
LEDs
Switches
Flash
RAM
Ethernet
Video
Decoder RAMDAC
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
Prog.
Osc.
Xchecker
/OE (left)
A18 (left)
A17 (left)
A16 (left)
A15 (left)
A14 (left)
A13 (left)
A12 (left)
A11 (left)
A10 (left)
4
TCK
Connections Between the XC95108 CPLD and the Other XSV Board Components
XC95108 CPLD
1
2
3
4
5
VCCINT
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
GND
22
PGCK
23
PGCK
24
25
26
VCCO
27
PGCK
28
29
30
31
GND
32
33
34
35
36
37
38
VCCO
39
40
41
42
Virtex
FPGA
LEDs
Switches
Flash
RAM
/RESET
Video
Ethernet Decoder RAMDAC
/LEDS
CFG1
/RESET CE
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
Prog.
Osc.
239
TCK
178
185
184
123
120
122
179
60
58
62
132
133
139
141
144
S1 (right)
S2 (right)
S3 (right)
S4 (right)
S5 (right)
A0
A1
A2
A3
A4
89
147
152
154
S6 (right)
BAR0
BAR1
A5
A6
A7
157
160
162
169
BAR2
BAR3
BAR4
BAR5
A8
A9
A10
A11
S0 (left)
S1 (left)
S2 (left)
S3 (left)
S4 (left)
S5 (left)
D0
D1
D2
D3
D4
D5
S6 (left)
S0 (right)
BAR9
BAR7
D6
D7
RDY
/OE
177
167,183
163,181
156,2
145
138
134
124
171
173
Xchecker
SW4
/INIT
DONE
/PROGRAM
CCLK
RT
RD
TRIG
CLKO
CLK
CLKI
DIN
TDI
TMS
XC95108 CPLD
43
44
GND
45
TDI
46
47
TMS
48
TCK
49
50
51
VCCO
52
53
54
55
56
57
VCCINT
58
59
60
61
62
GND
63
64
65
66
67
68
69
GND
70
71
72
73
74
75
GND
76
77
78
79
80
81
82
83
TDO
84
GND
Virtex
FPGA
131
LEDs
BAR8
Switches
Flash
RAM
/WE
Ethernet
Video
Decoder RAMDAC
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
C3
170
/CE
C2
C1
168
161
BAR6
DIPSW1
A12
A13
159
155
153
149
146
DIPSW2
DIPSW3
DIPSW4
DIPSW5
DIPSW6
A14
A15
A16
A17
A18
142
140
DIPSW7
DIPSW8
A19
A20
S4
S5
S7
S6
D7
D6
D5
D4
D3
C3
D2
C2
D1
S3
D0
C1
C0
RxD
TxD
RTS
S7
Prog.
Osc.
Xchecker
XC95108 CPLD
85
86
87
88
VCCO
89
90
91
92
93
94
95
96
97
98
VCCINT
99
100
GND
Virtex
FPGA
LEDs
Switches
Flash
RAM
Ethernet
MF4
MF3
MF2
MF1
MF0
FDE
CFG0
MDDIS
/LEDR
/LEDT
/LEDL
/LEDC
Video
Decoder RAMDAC
Codec
RAM
PS/2
USB
Parallel
Port
Serial
Port
CTS
Prog.
Osc.
Xchecker
B
XSV Schematics
The following pages show the detailed schematics for the XSV Board.
XSV BOARD V1.1 MANUAL
40
9/21/2001

Schematics for 1.0, 1.1, and 1.2 XS40/95 Boards

Transcription

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