Dothan

8
7
6
5
4
3
2
1
+3V
D
Dothan
478 Pins
CPU Thermal
Sensor
(Micro-FCPGA)
VTT_MEM
VDIMM
DDR-SODIMM1
DDR-SODIMM2
Buffer
ICS93705
S-VIDEO
Video Controller
AGP
SIS302LV
LVDS
DDR SDRAM 2.5V, 333/400MHz
SiSM661FX
C
ICS952005
VCORE_VGA
Host Bus
400MHZ
533MHZ
D
Clocks
LCD Panel
MINI-PCI
R.G,B CRT port
C
DDR SDRAM 2.5V, 333/400MHz
Primary IDE - HDD
Master
DVD/CDRW/CD/COMBO
Slave
33MHZ, 3.3V PCI
MuTIOL.1G
33MHZ, 3.3V PCI
ATA 133/100
SiS963
USB 2.0
AC-LINK
Headphone
CardBus
B
External
MIC
Internal
MIC
AUDIO
ALC202A(Codec)
TPA0312(Amp)
LAN
10/100 Mbps
CB810
USB PORT -->2,6
RTL8100C
MDC
B
USB --> 1,3
+5V
+3V
+3VALW
CardReader
CARD
BUS
SLOT
VCCRTC
1394
CONN
RJ45
SD&MMC&MS
Slot
PC87591
176 Pins LQFP
Touchpad Keyboard
FLASH
FAN 1
A
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
1
of
50
8
7
Device
Rails
CPU M661FX
6
963L PC87591 DDR
5
M10
302LV LCD
4
MiniPCI
3
LAN AUDIO HDD
2
MDC BufferCLK GEN.
1
cardbus
D
D
+1.5VSUS
+3VALW
+3v
+1.8V
3VAUX
+1.8VAUX
5VAUX
C
C
VDDQ
VDIMM
DDR_VTT
+1.2V
+1.5V
+5VALW
+12V
B
B
VCORE_CPU
VCCP
+5V
3VSUS
VCORE_VGA
A
A
TECHNOLOGY COPR.
Title
Power Diagram
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
2
of
50
5
4
3
2
1
+3V
HDJ[0..63]
HDJ[0..63]
5
U33A
C
ADSTB0#
ADSTB1#
5
5
HADSTBJ0
HADSTBJ1
U3
AE5
5
5
5
5
5
HREQJ0
HREQJ1
HREQJ2
HREQJ3
HREQJ4
R2
P3
T2
P1
T1
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
5
ADSJ
N2
ADS#
R508
+/-5%
56
R0603
H_IERRJ
Dothan
1 OF 3
REQUEST
PHASE
SIGNALS
ERROR
SIGNALS
A4
IERR#
5
5
5
5
HBREQJ0
BPRIJ
BNRJ
HLOCKJ
N4
J3
L1
J2
BR0#
BPRI#
BNR#
LOCK#
ARBITRATION
PHASE
SIGNALS
5
5
5
HITJ
HITMJ
DEFERJ
K3
K4
L4
HIT#
HITM#
DEFER#
SNOOP PHASE
SIGNALS
BPM0#
BPM1#
BPM2#
BPM3#
TRDY#
RS0#
RS1#
RS2#
RESPONSE
PHASE
SIGNALS
HTRDYJ
RSJ0
RSJ1
RSJ2
C8
B8
A9
C9
M3
H1
K1
L2
H_A20MJ
H_FERRJ
H_IGNNEJ
CPUPWRGD
H_SMIJ
C2
D3
A3
E4
B4
A20M#
FERR#
IGNNE#
PWRGOOD
SMI#
PC
COMPATIBILITY
SIGNALS
A13
A12
C12
C11
B13
A16
A15
B10
A10
A7
TCK
TDO
TDI
TMS
TRST#
ITP_CLK0
ITP_CLK1
PREQ#
PRDY#
DBR#
DIAGNOSTIC
& TEST
SIGNALS
D1
D4
C6
A6
B7
LINT0
LINT1
STPCLK#
SLP#
DPSLP#
EXECUTION
CONTROL
SIGNALS
B18
A18
THERMDA
THERMDC
+VCCP
B
5
5
5
5
10
10
10
5
10
TCK_H
TDO_H
TDI_H
TMS_H
TRSTJ
DB RJ
A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
10
10
10
10
10,31
H_INTR
H_NMI
H_STPCLKJ
H_CPUSLPJ
H_DPSLPJ
THERMDA
THERMDC
10 PM_THRMTRIPJ
10 CPU_PROCHOTJ
PM_THRMTRIPJ
CPU_PROCHOTJ
C17
THERMTRIP#
B17
PROCHOT#
DATA
PHASE
SIGNALS
HDJ0
HDJ1
HDJ2
HDJ3
HDJ4
HDJ5
HDJ6
HDJ7
HDJ8
HDJ9
HDJ10
HDJ11
HDJ12
HDJ13
HDJ14
HDJ15
HDJ16
HDJ17
HDJ18
HDJ19
HDJ20
HDJ21
HDJ22
HDJ23
HDJ24
HDJ25
HDJ26
HDJ27
HDJ28
HDJ29
HDJ30
HDJ31
HDJ32
HDJ33
HDJ34
HDJ35
HDJ36
HDJ37
HDJ38
HDJ39
HDJ40
HDJ41
HDJ42
HDJ43
HDJ44
HDJ45
HDJ46
HDJ47
HDJ48
HDJ49
HDJ50
HDJ51
HDJ52
HDJ53
HDJ54
HDJ55
HDJ56
HDJ57
HDJ58
HDJ59
HDJ60
HDJ61
HDJ62
HDJ63
Q50
2N7002
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
DSTBN0#
DSTBP0#
DSTBN1#
DSTBP1#
DSTBN2#
DSTBP2#
DSTBN3#
DSTBP3#
C23
C22
K24
L24
W25
W24
AE24
AE25
HDSTBNJ0
HDSTBPJ0
HDSTBNJ1
HDSTBPJ1
HDSTBNJ2
HDSTBPJ2
HDSTBNJ3
HDSTBPJ3
5
5
5
5
5
5
5
5
DINV0#
DINV1#
DINV2#
DINV3#
D25
J26
T24
AD20
HDBIJ0
HDBIJ1
HDBIJ2
HDBIJ3
5
5
5
5
DBSY#
DRDY#
M2
H2
BCLK1
BCLK0
B14
B15
15,39
MBCLK
D
U34
15,39
MBDATA
S
15 TEMP_ALERTJ
SMCLK
VCC
1
7
6
SMDATA
DXP
2
-ALT
DXN
3
5
GND
-OVT
4
INIT#
DPWR#
C19
BC559
0.1uF
C0603
THERMDA
2.2nF C0603
THERMDC
TEMP_OVTJ
32
54.9 +/-1% R0603
54.9 +/-1% R0603
TMS_H
TDI_H
DB RJ
R522
R523
R517
39.2 +/-1% R0603
150 +/-5% R0603
150 +/-5% R0603
TCK_H
TRSTJ
R527
R525
27.4 +/-1% R0603
680 +/-5% R0603
C
+VCCP
R498
200
+/-1%
R0402
5
CPUPWRGD
H_PWRGD
+VCCP
H_FERRJ
R499
R0603
R526
R0603
HBREQJ0
CPU_PROCHOTJ
PM_THRMTRIPJ
H_A20MJ
H_STPCLKJ
H_CPUSLPJ
H_INITJ
DBSYJ
DRDYJ
R532
R0603
56
+/-1%
R531
R0603
R493
R0603
R514
R0603
R512
R0603
R507
R0603
R510
R0603
62
+/-1%
56
+/-1%
56
+/-1%
56
+/-1%
56
+/-1%
56
+/-1%
H_IGNNEJ
R505
R0603
R492
R0603
R506
R0603
H_INTR
H_DPSLPJ
5
5
62
+/-1%
62
+/-1%
R516
R0603
B
56
+/-1%
56
+/-1%
56
+/-1%
62
+/-1%
Sis FAE Suggestion
Lonny update July 1st
CLK_CPU_BCLKJ 13
CLK_CPU_BCLK 13
H_CPURSTJ
A
H_INITJ
10
H_CPURSTJ
5
DPWRJ
5
TECHNOLOGY COPR.
Title
Dothan CPU-1
Document Number
Re v
661S03
Date:
4
D
+VCCP
B5
B11
BC565
H_CPURSTJ R521
TDO_H
R524
H_NMI
RESET#
R534
100
+/-1%
R0603
MAX6648
8
H_SMIJ
THERMAL DIODE
+3V
R539
8.2K
+/-5%
R0402
S
Q51
2N7002
D
Banias-Processor
5
R540
8.2K
+/-5%
R0402
*
D
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
*
HAJ3
HAJ4
HAJ5
HAJ6
HAJ7
HAJ8
HAJ9
HAJ10
HAJ11
HAJ12
HAJ13
HAJ14
HAJ15
HAJ16
HAJ17
HAJ18
HAJ19
HAJ20
HAJ21
HAJ22
HAJ23
HAJ24
HAJ25
HAJ26
HAJ27
HAJ28
HAJ29
HAJ30
HAJ31
G
HAJ[3..31]
G
5
HAJ[3..31]
3
2
Friday, August 13, 2004
A
Sheet
1
3
of
50
5
4
3
2
1
U33B
R545
R543
R497
R495
R5441K
R5482K
+VCCP
+VCCP
+/-5% R0603
+/-5% R0603
27.4 +/-1%
54.9 +/-1%
27.4 +/-1%
54.9 +/-1%
R0603
R0603
R0603
R0603
GTLREF0 AD26
E26
0 +/-5% R0402
G1
AC1
R486
D
*
*
BC49
0.1uF
*
C0603
BC50
0.1uF
*
C0603
BC27
0.1uF
*
C0603
BC19
0.1uF
*
C0603
BC51
0.1uF
TEST1 C5
TEST2 F23
+1.8V R0805
C0603
+/-5%
0
R549
Dummy
R511
1K
+/-5%
R0603
+VCCP
*
*
BC25
0.1uF
C0603
*
BC16
0.1uF
C0603
C
VCORE_CPU
*
BC556
10uF
*
C0805
BC558
10uF
*
C0805
B
BC571
10uF
*
C0805
VCORE_CPU
*
BC557
10uF
*
C0805
BC32
10uF
*
C0805
BC581
10uF
*
C0805
VCORE_CPU
*
BC552
10uF
*
BC555
10uF
C0805
C0805
BC15
0.1uF
BC28
0.1uF
*
BC40
10uF
*
C0805
VCORE_CPU
A
*
C0603
*
*
C0603
BC41
0.1uF
C0603
*
COMP0
COMP1
COMP2
COMP3
GTLREF0
RSVD
DPRSLP#
RSVD
Dummy
R546
1K
+/-5%
R0603
POWER,
GROUND,
RESERVED
SIGNALS
VCCA3
VCCA2
VCCA1
VCCA0
BC588 VCORE_CPU
10uF
D6
C0805
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18
F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
10U/6.3V/X5R(CC0805)
V6
VCORE_CPU
5 mOhm*35
V22
W5
W21
BC577
BC567
BC572
BC564
BC569
BC566
BC561
Y6
10uF
10uF
10uF
10uF
10uF
10uF
10uF
Y22
AA5
C0805
C0805
C0805
C0805
C0805
C0805
C0805
AA7
AA9
AA11
AA13
AA15
VCORE_CPU
AA17
AA19
AA21
BC584
BC578
BC26
BC575
BC579
BC551
BC548
AB6
10uF
10uF
10uF
10uF
10uF
10uF
10uF
AB8
AB10
C0805
C0805
C0805
C0805
C0805
C0805
C0805
AB12
AB14
AB16
AB18
AB20
AB22
VCORE_CPU
AC9
AC11
AC13
BC52
BC38
BC55
BC23
BC22
BC29
BC24
AC15
10uF
10uF
10uF
10uF
10uF
10uF
10uF
AC17
AC19
C0805
C0805
C0805
C0805
C0805
C0805
C0805
AD8
AD10
AD12
AD14
AD16
VCORE_CPU
AD18
AE9
AE11
BC42
BC18
BC553
BC549
BC547
BC550
BC21
AE13
0.1uF
0.1uF
10uF
10uF
10uF
10uF
10uF
AE15
AE17
C0603
C0603
C0805
C0805
C0805
C0805
C0805
AE19
AF8
AF10
AF12
AF14
AF16
AF18
VCC00
VCC01
VCC02
VCC03
VCC04
VCC05
VCC06
VCC07
VCC08
VCC09
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
*
C0603
*
*
*
BC17
0.1uF
C0603
*
BC20
0.1uF
C0603
*
*
*
*
2 OF 3
TEST1
TEST2
AC26
N1
B1
F26
BC33
0.1uF
Dothan
10,31 H_DPRSLPJ
+VCCP
EC2
150uF
2.5V, +/-20%
CTB
P25
P26
AB2
AB1
0.5'' max length
10,31 DPRSLPVR
EC1
150uF
2.5V, +/-20%
CTB
COMP0
COMP1
COMP2
COMP3
*
*
BC586
10nF
25V, X7R, +/-10%
C0402
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
+VCCP
U33C
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21
P23
W4
31
31
31
31
31
31
R518
R513
13
CPU_BSEL1
13
31
CPU_BSEL0
PSIJ
E2
F2
F3
G3
G4
H4
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
Dummy
54.9 +/-1% R0603
54.9 +/-1% R0603
Dummy
JP11
1
JP10 1
Z0501 AE7
Z0502 AF6
SHORT
2
SHORT
2
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
POWER, GROUND AND NC
VID
D
C
B
Banias-Processor
A
TECHNOLOGY COPR.
Title
Dothan CPU-2
Document Number
Re v
661S03
Date:
4
3 OF 3
VCCSENSE
VSSSENSE
RSVD
RSVD
BSE[1]
RSVD
BSE[0]
PSI#
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Dothan
VID0
VID1
VID2
VID3
VID4
VID5
B2
AF7
C14
C3
C16
E1
Banias-Processor
5
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
2
Friday, August 13, 2004
A
Sheet
1
4
of
50
8
+VCCP
7
6
5
4
3
2
VAD[0..11]
VAD[0..11]
VBD[0..11]
R117
75
+/-1%
R0603
*
BC179
10nF
VBCTL[0..1]
BC166
0.1uF
AVSYNC
R33
T32
U35
RS#2
RS#1
RS#0
V35
R35
U34
W34
U33
V33
ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#
H_REQJ4
H_REQJ3
H_REQJ2
H_REQJ1
H_REQJ0
W35
Y33
W31
W33
Y35
HREQ4#
HREQ3#
HREQ2#
HREQ1#
HREQ0#
HADSTBJ1
HADSTBJ0
AG31
AA33
3
DPW RJ
DPW RJ
B
R36
AH33
AG33
AJ35
AF32
AJ34
AH32
AG35
AE31
AH35
AF35
AE35
AE33
AE34
AF33
AG34
AC33
AD32
AD33
AC35
AD35
AC31
AC34
AB35
AB32
AB33
AA35
AA31
Y32
AA34
HAJ[3..31]
+VCCP
VAVSYNC
40,41
BHSYNC
HA31#
HA30#
HA29#
HA28#
HA27#
HA26#
HA25#
HA24#
HA23#
HA22#
HA21#
HA20#
HA19#
HA18#
HA17#
HA16#
HA15#
HA14#
HA13#
HA12#
HA11#
HA10#
HA9#
HA8#
HA7#
HA6#
HA5#
HA4#
HA3#
SiSM661FX
M661FX-1
AC/BE3#
AC/BE2#
AC/BE1#
AC/BE0#
K5
M5
P4
U6
AREQ#
AGNT#
AFRAME#
AIRDY#
ATRDY#
ADEVSEL#
ASERR#
ASTOP#
C6
E8
N6
M4
N4
L2
P5
M2
AC-BE3
AC-BE2
AC-BE1
AC-BE0
SBA[1..7]
40,41
VBVSYNC
40,41
N3
D7
B4
GC_DET#
ADBIH/PIPE#
ADBIL
C7
C4
D6
AGP8X_MB_DETJ
DBI_HI
DB_HI
DBI_LOW
DB_LO
SB_STB
SB_STB#
C2
D3
AGP_SBSTBF
AGP_SBSTBS
AD_STB0
AD_STB0#
T2
U3
AGP_PAR
AGP_WBF#
D
AGPCLK
AGPCOMP_P
AGPCOMP_N
A1XAVDD
A1XAVSS
W2
Y2
B8
C8
AGPRCOMP
AGPRCOMN
A1XAVDD
A1XAVSS
A4XAVDD
A4XAVSS
A7
B7
A4XAVDD
A4XAVSS
AGPVREF
W3
AVREFGC
FB41
VBCAD
AGP_GNT#
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_DEVSEL#
40
41
41
41
41
41
AGP_STOP#
41
A4XAVDD
BC641
0.1uF
1
*
*
C0402
FB L0805 60 Ohm
BC640
BC636
10nF
10uF
*
R147
0
VBHCLK
40
R0402
+/-5%
R152
0 @648
AGP_RBF#
R0402
+/-5%
41
+3V
FB40
A1XAVDD
* *
13
Y4
HDSTBP3#
HDSTBP2#
HDSTBP1#
HDSTBP0#
E25
D30
H32
M32
H_DSTVPJ3
H_DSTVPJ2
H_DSTVPJ1
H_DSTVPJ0
C
*
C0402
C1206
JP16
2
10
+/-5%
BC664
0.1uF
16V, X7R, +/-10%
C0402
Dummy
Sis FAE release demo ver0.8
change Value 200 Ohm from 300 Ohm
lonny 070704
0 @648
AGPREF
+/-5%
AVREFGC
HDSTBNJ3
HDSTBNJ2
HDSTBNJ1
HDSTBNJ0
3
3
3
3
HDSTBPJ3
HDSTBPJ2
HDSTBPJ1
HDSTBPJ0
3
3
3
3
41,46
VAGCLK
*
1
40
VDDQ
R640
200
+/-1%
R0603
AVREFGC
*
HOST
BC653
0.1uF
R646
200
+/-1%
R0603
C0402
110 HPCOMP
+/-1%
2
FB L0805 60 Ohm
BC638
BC637
10nF
10uF
A1XAVSS
AGCLK R645
R0402
H_DSTVNJ3
H_DSTVNJ2
H_DSTVNJ1
H_DSTVNJ0
1
0 @648
AGP_ADSTBF_0 41
BC639
+/-5%
AGCLK
0.1uF
0 @648
AGP_ADSTBF_1 41
+/-5%
C0402
BGCLK
SHORT
R653
R0402
D24
F30
G33
N31
1
SHORT
AGP8X_MB_DETJ 41
41
41
AGPCLK0
HDSTBN3#
HDSTBN2#
HDSTBN1#
HDSTBN0#
C1206
JP17
2
A4XAVSS
R670
0 @648
R0402
AGP_ADSTBS_0 41
+/-5%
R163
0 @648
R0402
AGP_ADSTBS_1 41
+/-5%
R658
R0402
AGPCLK0
2
C0402
AGP_SBSTBF 41
AGP_SBSTBS 41
R666
R0402
G2
H2
41
40,41
41
41
41
RBF#
D8
AGPVSSREF
AGP_REQ#
ASTOP_
APAR
40,41
VBDE
+3V
0
+/-5%
0
+/-5%
RBF#
WBF#
VADE
41
@648
R614
R0402
R613
R0402
AD_STB1
AD_STB1#
HD J0
HD J1
HD J2
HD J3
HD J4
HD J5
HD J6
HD J7
HD J8
HD J9
HDJ10
HDJ11
HDJ12
HDJ13
HDJ14
HDJ15
HDJ16
HDJ17
HDJ18
HDJ19
HDJ20
HDJ21
HDJ22
HDJ23
HDJ24
HDJ25
HDJ26
HDJ27
HDJ28
HDJ29
HDJ30
HDJ31
HDJ32
HDJ33
HDJ34
HDJ35
HDJ36
HDJ37
HDJ38
HDJ39
HDJ40
HDJ41
HDJ42
HDJ43
HDJ44
HDJ45
HDJ46
HDJ47
HDJ48
HDJ49
HDJ50
HDJ51
HDJ52
HDJ53
HDJ54
HDJ55
HDJ56
HDJ57
HDJ58
HDJ59
HDJ60
HDJ61
HDJ62
HDJ63
20 HNCOMP
+/-1%
VBHSYNC
VADE
AC-BE[0..3]
E3
F4
D2
F5
E4
B2
E6
B3
SBA7
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
SBA0
D22
C22
B22
AA26
W26
U26
R26
L20
B6
F7
B5
Y5
W4
V2
W6
V4
U2
V5
U4
R2
T4
R3
T5
P2
R4
N2
R6
L3
L4
K2
L6
J2
J3
K4
J4
J6
H4
G3
H5
F2
G4
E2
G6
ST0
ST1
ST2
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
AAD8
AAD9
AAD10
AAD11
AAD12
AAD13
AAD14
AAD15
AAD16
AAD17
AAD18
AAD19
AAD20
AAD21
AAD22
AAD23
AAD24
AAD25
AAD26
AAD27
AAD28
AAD29
AAD30
AAD31
LVDS/AGP
DPWR#
BVSYNC
ST[0..2]
ST[0..2]
AC-BE[0..3]
HASTB1#
HASTB0#
Rds-on(n) = 10 ohm
HNCVERF = 1/3 VCCP
R107
R0603
40,41
DBI3#
DBI2#
DBI1#
DBI0#
HADSTBJ1
HADSTBJ0
R596
R0603
VAHSYNC
BGCLK R633
R0402
F26
B32
E34
R31
ADSJ
HITMJ
HITJ
DRD YJ
DBSYJ
BNRJ
HCOMP_P
HCOMP_N
HCOMPVREF_N
H_RSJ2
H_RSJ1
H_RSJ0
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4
AL36
AK34
HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#
HREQJ4
HREQJ3
HREQJ2
HREQJ1
HREQJ0
3
3
C1XAVSS
C1XAVDD
T33
T35
V32
B23
F22
R34
U31
HAJ31
HAJ30
HAJ29
HAJ28
HAJ27
HAJ26
HAJ25
HAJ24
HAJ23
HAJ22
HAJ21
HAJ20
HAJ19
HAJ18
HAJ17
HAJ16
HAJ15
HAJ14
HAJ13
HAJ12
HAJ11
HAJ10
HAJ9
HAJ8
HAJ7
HAJ6
HAJ5
HAJ4
HAJ3
3
40,41
SBA[1..7]
HD63#
HD62#
HD61#
HD60#
HD59#
HD58#
HD57#
HD56#
HD55#
HD54#
HD53#
HD52#
HD51#
HD50#
HD49#
HD48#
HD47#
HD46#
HD45#
HD44#
HD43#
HD42#
HD41#
HD40#
HD39#
HD38#
HD37#
HD36#
HD35#
HD34#
HD33#
HD32#
HD31#
HD30#
HD29#
HD28#
HD27#
HD26#
HD25#
HD24#
HD23#
HD22#
HD21#
HD20#
HD19#
HD18#
HD17#
HD16#
HD15#
HD14#
HD13#
HD12#
HD11#
HD10#
HD9#
HD8#
HD7#
HD6#
HD5#
HD4#
HD3#
HD2#
HD1#
HD0#
ADSJ
HITMJ
HITJ
DRDYJ
DBSYJ
BNRJ
CPUCLK
CPUCLK#
HLOCKJ
D EFERJ
HTR DYJ
H_CPURSTJ
CPUPWRGD
BPRIJ
HBREQJ0
RSJ2
RSJ1
RSJ0
3
3
3
3
3
C
CLK_MCH_BCLK AJ31
CLK_MCH_BCLKJ AJ33
41
C24
E23
B24
D23
D25
F24
C26
B25
B26
D27
D26
E27
B27
D28
C28
B28
E29
F28
B29
C30
B30
B31
C32
D29
C33
B33
B35
D32
B34
E31
D31
D33
D35
G31
C35
F33
E33
D34
E35
F32
J34
G34
H35
F35
J33
J31
G35
H33
J35
K32
N33
K33
L31
L33
K35
L35
M35
M33
P32
P33
L34
N34
N35
P35
HLOCKJ
DEFERJ
HTRDYJ
H_CPURSTJ
CPUPWRGD
BPRIJ
HBREQJ0
3
3
3
3
3
3
40,41
VBCTL[0..1]
VBDE
BCLK
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
U37A
13 CLK_MCH_BCLK
13 CLK_MCH_BCLKJ
HN CVREF
HNCOMP
HPCOMP
place this capacitor
under 660FX solder side
HVREF
C4XAVDD
C4XAVSS
C1XAVDD
C1XAVSS
C0402
AJ36
AK35
*
C0402
AHSYNC
C4XAVSS
C4XAVDD
BC172
10nF
HVREF
BVSYNC
BHSYNC
VBCTL1
VBCTL0
VBDE
VAD3
VAD2
VAD0
VAD1
VBD9
VBD8
VBD10
VBD11
AHSYNC
AVSYNC
VADE
VAD11
VAD10
VAD9
VAD8
VAD7
VAD4
VAD5
VAD6
VBD0
VBD1
VBD2
VBD3
VBD4
VBD5
VBD6
VBD7
ST2
ST1
ST0
*
D
3
3
3
VBD[0..11]
C0402
R118
150
+/-1%
R0603
3
3
3
3
3
3
3
1
40,41
10
+/-5%
BC658
0.1uF
16V, X7R, +/-10%
C0402
Dummy
AGP3.0 = 50 ohm
VBGCLK
B
40
*
VDDQ
Rds-on(p) = 56 ohm
HPCVERF = 2/3 VCCP
3
3
3
3
3
HDJ[0..63]
+VCCP
H_DINVJ3
H_DINVJ2
H_DINVJ1
H_DINVJ0
HDBIJ3
HDBIJ2
HDBIJ1
HDBIJ0
+3V
+3V
FB7
R595
150
+/-1%
R0603
*
BC620
10nF
C1XAVDD
HN CVREF
A
BC103
0.1uF
*
C0402
R593
75
+/-1%
R0603
1
C0402
*
BC621
10nF
C1XAVSS
C0402
*
C4XAVDD
2
*
SHORT
49.9
+/-1%
BCLK
Demo is 50 Ohm 1%
lonny 2004-06-02
AGPRCOMP R639
R0603
43
+/-1%
R635
R0402
10
+/-5%
VBCLK
40,41
This part only for 661FX, and 648FX dummy
FB35
FB L0805 60 Ohm
BC99
BC100
10nF
10uF
10V, Y5V, +80%/-20%
C0402
C1206
JP1
2
AGPRCOMN R634
R0603
1
BC600
0.1uF
C0402
C4XAVSS
1
2
Demo is 43.75 Ohm 1%
2004-06-02
*
*
FB L0805 60 Ohm
lonny
BC607
BC595
10nF
10uF
10V, Y5V, +80%/-20%
C0402
C1206
*
JP12
2
A
1
SHORT
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
5
of
50
7
/RMD[0..63]
/RDQM[0..7]
/RDQS[0..7]
6
19,20
5
/RDQM[0..7]
19,20
/RDQS[0..7]
19,20
/RCS-[0..3]
19,20
CKE[0..5]
CKE[0..5]
/RMD[0..63]
19,20
/RMA[0..14]
19,20
CKE4
CKE2
CKE3
CKE5
/RMD29 /RMD24
B
A
R621
R622
R623
R624
*
RN24
1
10
3
+/-5%
5
8P4R0603 7
RN23
1
10
3
+/-5%
5
8P4R0603 7
RN25
1
10
3
+/-5%
5
8P4R0603 7
RN28
1
10
3
+/-5%
5
8P4R0603 7
RN26
1
10
3
+/-5%
5
8P4R0603 7
RN27
1
10
3
+/-5%
5
8P4R0603 7
RN30
1
10
3
+/-5%
5
8P4R0603 7
RN31
1
10
3
+/-5%
5
8P4R0603 7
RN33
1
10
3
+/-5%
5
8P4R0603 7
RN32
1
10
3
+/-5%
5
8P4R0603 7
RN35
1
10
3
+/-5%
5
8P4R0603 7
RN39
1
10
3
+/-5%
5
8P4R0603 7
RN34
1
10
3
+/-5%
5
8P4R0603 7
RN37
1
10
3
+/-5%
5
8P4R0603 7
RN38
1
10
3
+/-5%
5
8P4R0603 7
RN36
1
10
3
+/-5%
5
8P4R0603 7
RN41
1
10
3
+/-5%
5
8P4R0603 7
RN40
1
10
3
+/-5%
5
8P4R0603 7
RN42 1
10
3
+/-5% 5
8P4R0603
7
1
RN43
3
10
5
+/-5%
7
8P4R0603
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
0
0
0
dummy
dummy
dummy
dummy
R0402
R0402
R0402
R0402
VDIMM
CKE0
CKE1
/RMD7
/RDQM0
/RMD1
/RMD0
/RMD6
/RDQS0
/RMD5
/RMD4
/RDQS1
/RMD12
/RMD8
/RMD3
/RMD21
/RMD16
/RMD17
/RMD20
/RDQM1
/RMD13
/RMD9
/RMD2
/RMD11
/RMD14
/RMD15
/RMD10
/RMD29
/RMD24
/RMD23
/RDQM2
/RMD19
/RMD22
/RMD18
/RDQS2
/RMD27
/RMD30
/RDQM3
/RDQS3
/RMD31
/RMD26
/RMD25
/RMD28
/RMD39
/RDQS4
/RMD33
/RMD32
/RMD53
/RMD49
/RMD47
/RMD42
/RDQM4
/RMD34
/RMD37
/RMD36
/RDQM5
/RMD45
/RMD44
/RMD38
/RMD52
/RMD48
/RMD46
/RMD43
/RDQS5
/RMD41
/RMD40
/RMD35
/RDQM6
/RMD54
/RMD51
/RDQS6
/RMD57
/RMD60
/RMD55
/RMD50
/RMD63
/RMD62
/RDQM7
/RMD56
/RMD59
/RMD58
/RDQS7
/RMD61
2
19,20
D
update sch following layout
C
0719
3
VDIMM
/RMD[0..63]
/RMA[0..14]
/RCS-[0..3]
4
MD[0..63]
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
MD7
DQM0
MD1
MD0
MD6
DQS0
MD5
MD4
DQS1
MD12
MD8
MD3
MD21
MD16
MD17
MD20
DQM1
MD13
MD9
MD2
MD11
MD14
MD15
MD10
MD29
MD24
MD23
DQM2
MD19
MD22
MD18
DQS2
MD27
MD30
DQM3
DQS3
MD31
MD26
MD25
MD28
MD39
DQS4
MD33
MD32
MD53
MD49
MD47
MD42
DQM4
MD34
MD37
MD36
DQM5
MD45
MD44
MD38
MD52
MD48
MD46
MD43
DQS5
MD41
MD40
MD35
DQM6
MD54
MD51
DQS6
MD57
MD60
MD55
MD50
MD63
MD62
DQM7
MD56
MD59
MD58
DQS7
MD61
R620
R619
0 dummy
0 dummy
D
R0402
R0402
*
U37B
BC186
10nF
R120
150
+/-1%
R0603
C0402
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
DQS0
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7
AN35
AP36
AK33
AM33
AN34
AK32
AR34
AN33
AR35
AP34
AM32
AL31
AR31
AL30
AN32
AR33
AN31
AM31
AR32
AP32
AP30
AR30
AM29
AL27
AN30
AN29
AL28
AN28
AL29
AR29
AP26
AN25
AR24
AL24
AL25
AR26
AM25
AN24
AP24
AR25
AN21
AP20
AN20
AL18
AM21
AR21
AL19
AM19
AL20
AR20
AL15
AL14
AN15
AR15
AN16
AM15
AN14
AL13
AP16
AR16
AM13
AL12
AL11
AR12
AP14
AR14
AN13
AP12
AN12
AR13
AL10
AR11
AM9
AR9
AM11
AN11
AP10
AN9
AN10
AR10
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
DQS0/CSB0#
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1/CSB1#
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2/CSB2#
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3/CSB3#
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4/CSB4#
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5/CSB5#
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB6#
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7/CSB7#
DDRVREFB
*
M661FX-2
MA14
R627
0 R0402
MA3
MA4
MA2
MA1
MA0
MA10
MA12
MA6
DEBUG4
DEBUG5
R644
R642
R651
R652
R647
R656
R655
R641
R668
R667
0 R0402 /RMA3
0 R0402 /RMA4
0 R0402 /RMA2
0 R0402
/RMA1
0 R0402 /RMA0
0 R0402 /RMA10
0 R0402 /RMA12
0 R0402 /RMA6
0 R0402 /RCS-2
0 R0402 /RCS-3
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
TEST1
AR23
AN23
AN22
AM23
AL23
AL26
AN26
AN27
AR27
AR28
AP22
AN18
AR22
AP28
AM27
AT14
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
SRAS#
SCAS#
SWE#
AL17
AR19
AN19
SRASSCASSWE-
R661
R660
R665
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
AM17
AL16
AN17
AR17
AP18
AR18
CS-0
CS-1
DEBUG4
DEBUG5
CS-1
CS-0
MA11
MA5
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
S3AUXSW#
AP4
AT3
AR3
AP3
AR2
AN4
AP2
MA8
MA7
MA9
MA13
R626
R636
R630
R631
R671
R672
R664
R637
R628
R0402
/RMA14
R0402
R0402
R0402
R0402
0 R0402
0 R0402
0 R0402
For debug mode
R612
R618
DEBUG8
DEBUG9
DEBUG10
DEBUG11
DEBUG12
DEBUG13
DEBUG14
0
0
0
0
0
0
0
0
0
+/-5%
VDIMM
*
/RMA8
/RMA7
/RMA9
/RMA13
/RSRAS/RSCAS/RSWE-
0
0
BC199
R123
10nF
150
16V, X7R, +/-10% +/-1%
C0402
R0603
BC163
10nF
R116
16V, X7R, +/-10% 150
C0402
+/-1%
R0603
C
DDRVREFA
/RSRAS/RSCAS/RSWE-
19,20
19,20
19,20
*
BC144
10nF
R102
16V, X7R, +/-10% 150
C0402
+/-1%
R0603
/RCS-1
/RCS-0
/RMA11
/RMA5
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
S3AUXSW-
FWDSDCLKO BC185
C0603
S3AUXSW-
*
8
/RMD[0..63]
10pF
50V, NPO, +/-5%
10,38
+3V
FB36 FB L0805 60 Ohm
ADCLKO
R119
R0402
FWDSDCLKO
AL21
SDRCLKI
AL22
DLLAVDD
AL35
DLLAVDD
DLLAVSS
AL34
DLLAVSS
DDRAVDD
AM35
D DRAVDD
DDRAVSS
AN36
DDRAVSS
DDRVREFB
DDRVREFA
AF16
AF23
DDRVREFB
DDRVREFA
DRAM_SEL
AP1
DDRCOMP_P
DDRCOMP_N
AR8
AP8
22 FWDSDCLKO
+/-5%
FWDSDCLKO
DLLAVDD
R609
R0402
1
*
VDIMM
40 ohms
DDRCOMN
14
40.2
+/-1%
BC602
0.1uF
*
C0402
40 ohms
R610
R0402
*
C0402
DLLAVSS
DDRCOMP
B
2
BC603
10nF
BC598
10uF
C1206
2
1
JP13
SHORT
40.2
+/-1%
+3V
FB8
D DRAVDD
1
DDRCOMP
DDRCOMN
*
BC101
0.1uF
*
C0402
DDRAVSS
*
2
JP2
SiSM661FX
2
BC102
BC104
10nF FB L0805 60 Ohm 10uF
10V, Y5V, +80%/-20%
C0402
C1206
1
A
SHORT
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
6
of
50
8
7
6
5
4
3
2
1
NB Hardware Trap
(for SiS internal test only)
ZAD[0..16]
+3V
9 ZAD[0..16]
DLLEN-
R139
R0402
R141
R0402
R144
R0402
TRAP0
TRAP1
D
0
dummy
+/-5%
0
dummy
+/-5%
0
dummy
+/-5%
D
+1.8V
U37C
ZUREQ
ZDREQ
AL4
AK5
ZUREQ
ZDREQ
ZSTB0
ZSTB-0
AJ2
AJ3
ZSTB0
ZSTB0#
ZSTB1
ZSTB-1
C
+3V
*
FB43
1
BC670
10uF
FB L0805 60 Ohm
2
BC657
0.1uF
*
C1206 JP18
2
1
*
C0402
Z1XAVDD
BC650
10nF
16V, X7R, +/-10%
C0402
Z1XAVSS
ZSTB1
ZSTB-1
AE3
AF2
ZSTB1
ZSTB1#
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
AH5
AK2
AJ4
AJ6
AH2
AH4
AG3
AG6
AF4
AG2
AF5
AG4
AD2
AE6
AE2
AE4
AL3
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
ZVREF
AK4
ZCMP_N
ZCMP_P
AD5
AD4
SHORT
+3V
FB42
1
*
FB L0805 60 Ohm
2
BC649
0.1uF
BC669
10uF
*
C1206JP19
2
1
C0402
Z4XAVDD
BC656
10nF
16V, X7R, +/-10%
C0402
Z4XAVSS
HSYNC
VSYNC
A11
B11
VGPIO0
VGPIO1
E13
C11
R606
R605
33
33
R132
R135
C10
E15
D15
E14
VCOMP
VRSET
VVBWN
ZVREF
DACAVDD1
DACAVSS1
D13
C12
DACAVDD
DACAVSS
ZCOMP_N
ZCOMP_P
DACAVDD2
DACAVSS2
D14
C13
Z1XAVDD
Z1XAVSS
AL2
AL1
Z4XAVDD
Z4XAVSS
HyperZip
M661FX-3
BC229
10uF
*
C1206 JP4
2
1
BC230
0.1uF
C0402
*
R148
R0603
BC233
10nF
16V, X7R, +/-10%
C0402
R149
R0603
56
+/-1%
ZCMP_N
B15
C15
ECLKAVDD
ECLKAVSS
B14
C14
ECLKAVDD
ECLKAVSS
BC648
AUXOK
BC655
**
A
PWRGD
0.1uF C0402
1
0
C
R130
R0402
R140
R0402
R133
R0402
4.7K
+/-5%
4.7K
+/-5% Dummy
4.7K
+/-5% Dummy
R131
R0402
R136
R0402
R134
R0402
4.7K
+/-5% Dummy
4.7K
+/-5%
4.7K
+/-5%
This part only for 661FX, and 648FX reserved.
B
DCLKAVDD
BC628
10nF
*
*
FB38
1
BC627
0.1uF
+3V
FB L0805 60 Ohm
2
BC626
10uF
*
C0402 JP14
2
1
ZCMP_P
VVBWN BC197
VCOMP BC187
C1206
*
*
FB39
1
BC633
0.1uF
0.1uF C0402
+3V
FB L0805 60 Ohm
2
BC631
10uF
*
BC198
0.1uF
C0402
DACAVSS
*
+1.8V
R122
130
+/-1%
R0402
FB10 FB L0805 60 Ohm
1
2
BC201
BC194
1uF
10uF
*
C0603 JP3
2
1
*
C0402 JP15
2
1
VRSET
0.1uF C0402
DACAVDD
SHORT
C0402
ECLKAVSS
4.7K
+/-5%
TBD
C SYNC
ECLKAVDD
BC632
10nF
R142
R0402
0
CSYNC
LSYNC
SHORT
ENTEST
1
R SYNC
C0402
DCLKAVSS
56
+/-1%
TBD
LSYNC
DACAVDD
DACAVSS
DCLKAVDD
DCLKAVSS
0
LSYNC
ENTEST
DLLEN-
*
FB L0805 60 Ohm
2
9,22,23,40
Disable
1
+3V
+1.8V
FB11
1
Enable
RSYNC VGA Interrupt
C SYNC
DCLKAVDD
DCLKAVSS
0 dummy
+/-5%
0 dummy
+/-5%
0 dummy
+/-5%
302LV_CRTHS_VGA 18
302LV_CRTVS_VGA 18
R SYNC
TMODE0
TMODE1
TMODE2
PWRGD
AUXOK
R0402
R0402
Update sch basis on demo ver0.8
lonny 2004/07/12
INT-A
VCOMP
VRSET
VVBWN
AN1
AM2
R137
R0402
R608
R0402
R607
R0402
TMODE2
100 R0402 302LV_DDCCLK 18
100 R0402 302LV_DDCDAT 18
D12
E12
D11
Z4XAVDD
Z4XAVSS
TMODE0
13
302LV_CRT_R 18
302LV_CRT_G 18
302LV_CRT_B 18
CSYNC
RSYNC
LSYNC
Z1XAVDD
Z1XAVSS
9 NBRSTJ
10,15,31 PWRGD
10,32 AUXOK
B12
B13
A13
C SYNC
R SYNC
LSYNC
SiSM661FX
SHORT
ROUT
GOUT
BOUT
INT#A
TRAP0
TRAP1
B
*
VGA
DLLEN#
ENTEST
9
9
REFCLK0
E10
D9
ZSTB0
ZSTB-0
A15
TMODE1
TESTMODE2
TESTMODE1
TESTMODE0
BC231
0.1uF
16V, X7R, +/-10%
C0402
ZDREQ
9
9
VOSCI
* *
ZUREQ
C9
B9
B10
*
9
TRAP1
TRAP0
R146
150
+/-1%
R0603
ZCLK
9
ZVREF
R138
75
+/-1%
R0402
AL6
F9
D10
BC248
0.1uF
16V, X7R, +/-10%
C0402
ZCLK0
PCIRST#
PWROK
AUXOK
*
ZCLK0
AN2
AM4
AN3
R153
150
+/-1%
R0603
+3V
13
C1206
SHORT
C1206
SHORT
This part only for 661FX, and 648FX reserved.
A
0.1uF C0402
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
7
of
50
7
6
5
4
3
2
*
0.1uF
BC226
16V, X7R, +/-10%C0402
0.1uF
C0402
0.1uF
C0402
*
*
*
*
0.1uF C0402
BC148
D
Dummy
Dummy
0.1uF C0402 BC152
*
0.1uF C0402
*
BC660
10uF
C1206
*
*
*
0.1uF
C0402
1uF
C0603
Dummy
0.1uF C0402 BC253
0.1uF C0402
*
0.1uF C0402 BC153
*
Dummy
0.1uF C0402 BC158
Dummy
0.1uF C0402 BC255
0.1uF C0402
*
*
*
Dummy
VDDQ
0.1uF C0402 BC125
Dummy
0.1uF C0402 BC122
*
0.1uF C0402
BC123
*
BC124
BC139
Dummy
0.1uF C0402 BC174
Dummy
VDIMM
C
0.1uF C0402 BC209
BC165
BC132
0.1uF C0402 BC138
0.1uF C0402 BC202
*
10uF
C1206
1uF
C0603
1uF
C0603
*
BC236
*
BC235
10uF
C1206
*
10uF
C1206
BC218
1uF
C0603
0.1uF C0402
*
0.1uF C0402 BC120
1uF
C0603
0.1uF C0402
*
0.1uF C0402 BC222
0.1uF C0402 BC238
BC173
*
BC224
0.1uF C0402 BC190
10uF
C1206
*
BC212
0.1uF C0402
BC225
*
BC196
0.1uF C0402
*
BC221
0.1uF C0402 BC223
*
BC216
*
648 solder side
*
close to 648
and on VDDQ
plane
BC147
0.1uF C0402
BC157
Dummy
0.1uF C0402
BC154
3VAUX
BC219
0.1uF C0402
BC121
0.1uF C0402
0.1uF C0402
0.1uF C0402
VDDQ
0.1uF C0402
BC220
Dummy
BC171
*
*
BC211
0.1uF C0402
*
BC204
0.1uF C0402
BC193
*
BC151
VDIMM
*
+1.8V
*
Place these capacitors under 661 solder side
0.1uF C0402
Dummy
*
IVDD
0.1uF
C0402
*
0.1uF C0402 BC126
Dummy
BC128
*
10uF
C1206
BC182
*
0.1uF C0402
BC127
Dummy
BC156
*
T34
U32
U36
V34
W32
W36
Y34
AA32
AA36
AB34
0.1uF
C0402
*
0.1uF
16V, X7R, +/-10%
1uF
C0603
*
BC155
*
*
*
BC129
10uF
C1206
*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC145
BC254
BC189
*
A22
A24
A26
A28
A30
A32
A34
C23
C25
C27
C29
C31
C34
C36
E22
E24
E26
E28
E30
E32
E36
F34
G32
G36
H34
J32
J36
K34
L32
L36
M34
N32
N36
P34
R32
10uF
C1206
0.1uF
C0402
+1.8V
*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC146
0.1uF
C0402
+VCCP
*
AE5
AG5
AJ5
AL5
BC176
0.1uF
C0402
BC183
Dummy
BC251
C0402
*
VSS
VSS
VSS
VSS
0.1uF
C0402
0.1uF
C0402
*
*
1uF
C0603
*
*
0.1uF C0402 BC228
*
E11
F11
F13
AL33
AM34
A9
A3
A5
C1
C3
C5
E1
E5
E7
E9
F3
G1
G5
H3
J1
J5
K3
L1
L5
M3
N1
N5
P3
R1
R5
T3
U1
U5
V3
W1
W5
Y3
*
10uF
C1206
BC150
BC257
*
BC237
*
*
10uF
C1206
Dummy
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0.1uF C0402
BC206
B
0.1uF C0402
Dummy
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
change to DPWR#
SiSM661FX
AT16
AT18
AT20
AT22
AT24
AT26
AT28
AT30
AT32
AT34
AL32
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AP9
AP11
AP13
AP15
AP17
AP19
AP21
AP23
AP25
AP27
AP29
AP31
AP33
AP35
AT8
AT10
AT12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC659
BC203
3VAUX
BC200
*
VDD3.3
VDD3.3
VDD3.3
NC
NC
NC
D4
D5
AM5
AH3
AJ1
AK3
AM3
W11
W12
Y11
Y12
AA12
AD3
AE1
AF3
AG1
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
L17
M17
N17
B16
C16
D16
E16
F15
Power
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
A
IVDD
IVDD
IVDD
IVDD
IVDD
AUX_IVDD
VDDQ
*
PVDDM
PVDDM
PVDDM
PVDDM
PVDDM
PVDDM
PVDDM
L11
L12
L13
M11
M12
M13
M14
M15
M16
N11
N12
P12
R12
T12
U12
V12
3VAUX
*
AB24
AC13
AD14
AD16
AD18
AD20
AD22
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
BC177
*
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
AA1
AA2
AA3
AA4
AA5
AA6
AB1
AB2
AB3
AB4
AB5
AB6
AC1
AC2
AC3
AC4
AC5
AC6
AUX_IVDD
*
AB25
AC25
AD12
AD25
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF11
AF12
AF25
AF26
M661FX-4
AB12
AC12
*
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
B
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
IVDD
IVDD
IVDD
IVDD
IVDD
PVDD
IVDD
PVDD
IVDD
IVDD
IVDD
IVDD
PVDD
PVDD
IVDD
PVDD
PVDD
IVDD
IVDD
PVDD
PVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
PVDD
IVDD
IVDD
IVDD
AL7
AL8
AL9
AM6
AM7
AM8
AN5
AN6
AN7
AN8
AP5
AP6
AP7
AR4
AR5
AR6
AR7
AT4
AT5
AT6
AT7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
AC32
AC36
AD34
AE32
AE36
AF34
AG32
AG36
AH34
AJ32
VDIMM
BC195
U37D
AUX_IVDD
AUX3.3
0.1uF
C0402
*
+3V
*
+1.8V
A17
A18
A19
A20
A21
B17
B18
B19
B20
B21
C17
C18
C19
C20
C21
D17
D18
D19
D20
D21
E17
E18
E19
E20
E21
F17
F18
F19
F20
F21
N13
N14
N16
N18
N19
N20
N21
N22
N23
N24
P13
P24
R24
T13
T24
U24
V13
V24
W13
W24
Y13
Y24
AA24
AB13
AC24
AD13
AD15
AD17
AD19
AD21
AD23
AD24
N15
R13
U13
AA13
D
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
+3V
+1.8V
BC205
L25
L26
M18
M19
M20
M21
M22
M23
M24
M25
M26
N25
P25
R25
T25
U25
V25
W25
Y25
AA25
IVDD
*
IVDD
+VCCP
1
661 bottom side
IVDD
*
8
A
change to MA15
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
8
7
6
5
4
3
2
Friday, August 13, 2004
A
Sheet
8
1
of
50
8
7
6
+3V
D
2
4
6
8
R252
R0402
4.7K
+/-5%
23
23
22
29
REQ3J
REQ2J
REQ1J
REQ0J
23
23
22
29
GNT3J
GNT2J
GNT1J
GNT0J
22,23,29
22,23,29
22,23,29
22,23,29
C/BE3J
C/BE2J
C/BE1J
C/BE0J
F1
F2
E1
H5
F3
PREQ4#
PREQ3#
PREQ2#
PREQ1#
PREQ0#
GNT3J
GNT2J
GNT1J
GNT0J
H3
G1
G2
G3
H4
PGNT4#
PGNT3#
PGNT2#
PGNT1#
PGNT0#
C/BE3J
C/BE2J
C/BE1J
C/BE0J
K3
M4
P1
R4
C/BE3#
C/BE2#
C/BE1#
C/BE0#
E3
F4
E2
G4
INTA#
INTB#
INTC#
INTD#
FRAMEJ
IRDYJ
TRDYJ
STOPJ
M3
M1
M2
N4
FRAME#
IRDY#
TRDY#
STOP#
SERRJ
PAR
DEVSELJ
M5
N3
N1
N2
SERR#
PAR
DEVSEL#
PLOCK#
96XPCLK
PCIRSTJ
Y2
C3
REQ3J
REQ2J
REQ1J
REQ0J
PGNT-4
INT-A
INT-B
INT-C
INT-D
7,22,23,40 INT-A
41,46
INT-B
22,23,29
INT-C
22,23
INT-D
22,23,29 FRAMEJ
22,23,29 IRDYJ
15,17,22,23,29,40,41 22,23,29 TRDYJ
+3V
7
22,23,29 STOPJ
PCIRSTJ
NBRSTJ
C
22,23,29 SERRJ
22,23,29
PAR
22,23,29 DEVSELJ
U11
1
2
3
4
5
6
7
I1
O1
I2
O2
I3
O3
GND
14
13
12
11
10
9
8
Vcc
I6
O6
I5
O5
I4
O4
13
96XPCLK
PCIRSTJ
*
*
R262
150
+/-1%
R0603
ZSTB0
ZSTB0#
ZSTB1
ZSTB-1
J20
K20
ZSTB1
ZSTB1#
ZUREQ
ZDREQ
N16
N17
ZUREQ
ZDREQ
SVDDZCMP
SZCMP_N
R19
N18
VDDZCMP
ZCMP_N
SZCMP_P
SVSSZCMP
R18
P18
ZCMP_P
VSSZCMP
BC348
0.1uF
SZ1XAVDD
SZ1XAVSS
U20
U19
Z1XAVDD
Z1XAVSS
C0402
SZ4XAVDD
SZ4XAVSS
T20
T19
Z4XAVDD
Z4XAVSS
SZVREF
ZAD16
R20
P20
ZVREF
ZAD16
ZSTB1
ZSTB-1
7
7
ZUREQ
ZDREQ
BC355
0.1uF
HyperZip
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
*
963-1
ZCLK
7
7
ICHRDYA
IDREQA
IIRQA
CBLIDA
W10
V10
Y11
U12
IIORA#
IIOWA#
IDACKA#
V11 IDEIOR-A
IDEIOW-A
Y9
Y10 IDACK-A
1
SHORT
0
+/-1%
*
C0402
BC405
0.1uF
C0402
D
ICHR DYA
IDEREQA
IDEIRQA
CBLIDA
T11 IDESAA2
U11 IDESAA1
W11 IDESAA0
ICHRDYA
IDEREQA
IDEIRQA
CBLIDA
17
17
17
17
IDEIOR-A
IDEIOW-A
IDACK-A
17
17
17
IDESAA2
IDESAA1
IDESAA0
IDECS-A1
17
17
17
17
T12 IDECS-A1
V12 IDECS-A0
IDECS-A0
17
ICHRDYB
IDREQB
IIRQB
CBLIDB
W17 ICHR DYB
Y17 IDEREQB
T16 IDEIRQB
U17
ICHRDYB
IDEREQB
IDEIRQB
17
17
17
IIORB#
IIOWB#
IDACKB#
T14 IDEIOR-B
W16 IDEIOW-B
V16 IDACK-B
IDEIOR-B
IDEIOW-B
IDACK-B
17
17
17
IDESAB2
IDESAB1
IDESAB0
IDECS-B1
17
17
17
17
IDECS-B0
17
Y18 IDESAB2
T15 IDESAB1
V17 IDESAB0
U16 IDECS-B1
W18 IDECS-B0
IDA0
IDA1
IDA2
IDA3
IDA4
IDA5
IDA6
IDA7
IDA8
IDA9
IDA10
IDA11
IDA12
IDA13
IDA14
IDA15
U10
V9
W8
T9
Y7
V7
Y6
Y5
W6
U8
W7
V8
U9
Y8
T10
W9
HD D0
HD D1
HD D2
HD D3
HD D4
HD D5
HD D6
HD D7
HD D8
HD D9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15
IDB0
IDB1
IDB2
IDB3
IDB4
IDB5
IDB6
IDB7
IDB8
IDB9
IDB10
IDB11
IDB12
IDB13
IDB14
IDB15
Y16
V15
U14
W14
V13
T13
Y13
Y12
W12
W13
U13
Y14
V14
W15
Y15
U15
CD D0
CD D1
CD D2
CD D3
CD D4
CD D5
CD D6
CD D7
CD D8
CD D9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
HDD[0..15]
C
17
B
CDD[0..15]
17
SiS963L
M18
N19
M17
M16
M20
L16
L20
L18
K18
K19
K17
K16
H20
J18
H19
H18
C0402
*
R296
R0603
BC406
0.1uF
IDECSA1#
IDECSA0#
IDECSB1#
IDECSB0#
V20
SZVREF
R767
150
+/-1%
R0603JP7
2
1
PCICLK
PCIRST#
M19
N20
ZSTB0
ZSTB-0
Y3
Y4
IDSAB2
IDSAB1
IDSAB0
ZSTB0
ZSTB-0
ZCLK1
7
7
+1.8V
B
IDE
BC399
10nF
C0402
IDEAVDD
IDEAVSS
IDSAA2
IDSAA1
IDSAA0
ZCLK1
13
U18A
PCI
15,17,22,23,29,40,41
74LVC14
R261
75
+/-1%
R0402
2
+1.8V
J5
J4
H2
H1
J3
K4
J2
J1
K5
K2
L3
K1
L1
L4
L5
L2
N5
P2
P3
P4
R2
R3
R1
T1
P5
T2
U1
U2
T3
R5
U3
V1
8.2K
+/-1%
8P4R0603
R250
4.7K
R0402 +/-5%
PREQ-4
PGNT-4
3
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PREQ-4
*
1
3
5
7
4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
INT-D
INT-A
INT-B
INT-C
5
AD[0..31]
22,23,29 AD[0..31]
RN18
Put near 96X Chip.
only for MUTIOL 1.0 backup solution
ZAD15
ZAD14
ZAD13
ZAD12
ZAD11
ZAD10
ZAD9
ZAD8
ZAD7
ZAD6
ZAD5
ZAD4
ZAD3
ZAD2
ZAD1
ZAD0
+1.8V
7
ZAD[0..16]
Analog Power supplies of Transzip function for 96X Chip.
+3V
A
*
FB57
FB L1806 60 Ohm
1
2
BC409
BC384
10uF
0.1uF
*
C1206 JP9
2
1
SHORT
*
C0402
+1.8V
+3V
SZ1XAVDD
BC385
10nF
*
C0402
SZ1XAVSS
FB55
FB L1806 60 Ohm
1
2
BC391
BC376
10uF
0.1uF
*
C1206 JP8
2
1
SHORT
*
C0402
1
SZ4XAVDD
*
BC377
10nF
FB54
FB L1806 60 Ohm
2
BC731
10uF
*
C1206
C0402
C0402
JP6
SZ4XAVSS
2
BC739
0.1uF
1
SHORT
*
ZSTB0
ZSTB1
R255
R251
0 R0402 dummy
0 R0402 dummy
ZSTB-0
ZSTB-1
R256
R254
0 R0402 dummy
0 R0402 dummy
SVDDZCMP
BC740
10nF
C0402
R754
R0603
R257
R0603
56
+/-1%
SZCMP_N
56
+/-1%
SZCMP_P
A
SVSSZCMP
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
9
of
50
4
MCLK25I
OSC25MHO
A9
MCLK25O
TXCLK
A6
TXEN
B6
TXD0
E8
LFRAMEJ/FWH4
LDRQJ
SERIRQ
SERIRQ
32
7,15,31
BATOK
PWRGD
D2
OSC32KHO
D3
D1
BATOK
PWROK
C1
RTCVDD
E4
RTCVSS
B2
SMBCLK
22,27 AC_RESETJ
22,27 AC_BITCLK
REFCLK1
SENTEST
PCSPK
REFCLK1
11,27
PCSPK
15
22,23
PWRBTN
PMEJ
AUXOK
AUXOK
*
B
A3
A15
AUXOK
ACPILED
BC290
0.1uF
16V, X7R, +/-10%
C0402
GPIO14
15,29
SUSBJ
15
SUSCJ
R615 100
R0603 +/-1%
SLP_S3#
R616 100
R0603 +/-1%
SLP_S4#
AC97
OSCI
ENTEST
SPK
PWRBTN#
PME#
PSON#
4,31 DPRSLPVR
ACPI
/others
B1
GPIO13/DPRSLPVR
E5
GPIO14
GPIO
KBC
B15
U40A
3
A7
RXDV
C7
RXER
C8
RXD0
D8
RXD1
A5
RXD2
B5
RXD3
A4
74HCT14_1
U39E
7
14
8
11
10
13
74HCT14_1
*
74HCT14_1
BC291
0.1uF
C0402
*
BC289
10nF
C0402
*
BC271
10uF
C1206
2
1
SHORT
Analog power of MII
Put closed to 96X CHIP
COL
B7
CRS
E9
MDC
C5
MDIO
E7
MIIAVDD
MIIAVSS
B9
B8
GPIO0
V2
GPIO1/LDRQ1#
T8
OSC32KHI
C
R221
10M
R0603
+/-1%
XTAL-32.768kHz
1
2
4
3
BC300
15pF
C0402
X7
*
*
BC307
22pF
C0402
MIIAVDD
MIIAVSS
SCIJ
SCIJ
GPIO2/THERM#
T4
THERM-
GPIO3/EXTSMI#
T6
KBSMIJ
GPIO4/CLKRUN#
W1
CL KRUNJ
NEED NOT to place
close to 96X
15
GPIO5/PREQ5#
U5
GPIO6/PGNT5#
U4
GPIO6
GPIO7
C4
SMBALTJ
KBSMIJ
LAD1/FW H1
LAD0/FW H0
LAD3/FW H3
LAD2/FW H2
15
CLKRUNJ
RN8SMDA
+3V
E6
GPIO pins pull down
NEED NOT to place
close to 96X
R253
24.9K
+/-1%
R0603
R238
4.7K
+/-1%
R0603
GPIO10/AC_SDIN3
F5
GPIO12/CPUSTP#
D4
CPUSTP-
GPIO15/VR_HILO#
E13
GPIO15
GPIO16/LO_HI#
A16
GPIO16
B
+3V
THERM-
GPIO11/OSC25M/STP_PCI#
8
6
4
2
RN45 0 Dummy
R794
0
R0402
+/-5% dummy
SERIRQ
R795
0
R0402
+/-5% Dummy
SENTEST R741
0
R0402
+/-5%
C14
GPIO9/AC_SDIN2
7
5
3
1
LDRQJ
15,22,29
RF_DIS
GPIO17/PMDAT
RF_DIS
H_DPSLPJ
3,31
CPUSTPGPIO14
Q17
MMBT3904
B
GPIO11
GPIO18/PMCLK
SMBDAT
SMBCLK
CPUSTP-
13
GPIO18
(To PWM regulator)
GPIO11
GPIO6
GPIO17
+3V
R768
4.7K
R0603
+/-1% Dummy
R303
4.7K
R0603
+/-1% Dummy
R244
4.7K
R0603
+/-1% Dummy
R734
4.7K
R0603
+/-1%
R204
4.7K
R0603
+/-1%
R203
4.7K
R0603
+/-1%
R207
4.7K
R0603
+/-1%
R738
4.7K
R0603
+/-1%
R306
4.7K
R0603
+/-1%
R697
4.7K
R0603
+/-1%
SLP_S4#
2
3VAUX
GPIO15
+3V
GPIO16
4.7K
R282
R0402
dummy
PMEJ R211
R0603
+/-5%
4.7K
+/-1%
R694
4.7K
R0603 +/-1%
R205
4.7K
R0603
+/-1%
A
3VAUX
Place near to 96X
U39B
14
14
MIIAVDD
JP5
CL KRUNJ
4
4
74HCT14
5
4.7K
U40B
6
74LV08
7
3
D
FB14
FB L1806 60 Ohm
1
2
MIIAVSS
7
7
A
BC288
22pF
C0402
*
U39F
12
74HCT14
74LV08
2
OSC-25MHz
74HCT14_1
7
RXCLK
9
*
U39A SiS963L
1
7
2
B4
B3
5VAUX
14
14
5VAUX
S3AUXSW-
TXD3
6
BC287
15pF
C0402
E
D13
GPIO18
6,38
TXD2
C6
GPIO8/RING
GPIO17
15,33,38 SUSON
D7
U39D
+/-5% 8P4R0603
/geyserville
1
TXD1
AC_RESET#
AC_BIT_CLK
A14
B14
D14
X6
U39C
OSC32KHO
GPIO
AC_SDOUT
AC_SYNC
W3
G5
V3
PWRBTN
PMEJ
MII
AC_SDIN0
AC_SDIN1
R0402
AC_SDOUT R294
0 +/-5%
W2
AC _SYNC
T5
R771
0 +/-5%
AC_RESETJ
R0402
D6
AC_BITCLK
Y1
dummy
+/-5%
3VAUX
963-2
GPIO19
A2
D5
R212
R0402
74LV08
1
5
RTC
GPIO20
A1
AC_SDIN0
AC_SDIN1
AC_SDIN0
AC_SDIN1
7
OSC32KHO
BC311 VCCRTC
0.1uF
16V, X7R, +/-10%
C0402
10M
MCLK25I
13
74LV08
LPC
BATOK
SMBDAT
11,22,27 AC_SDOUT
22,27 AC_SYNC
7,32
LFRAME#
LDRQ#
SIRQ
OSC32KHI
13,14,19,46 SMBCLK
13
W4
U7
V6
C2
13,14,19,46 SMBDAT
27
22
LAD0
LAD1
LAD2
LAD3
OSC32KHI
*
C
V5
T7
U6
W5
MCLK25O
11
10
APIC
U40D
8
14
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
15 LFRAMEJ/FWH4
15,23
APICCK/LDTREQ#
APICD0/THERM2#
APICD1/GPIOFF#
1
12
7
15
15
15
15
Y19
V18
W19
CPU_S
U40C
9
C
3 CPU_PROCHOTJ
3 PM_THRMTRIPJ
10K
+/-1%
INIT#
A20M#
SMI#
INTR
NMI
IGNNE#
FERR#
STPCLK#
CPUSLP#
14
R290
R0402
T18
P16
R17
R16
Y20
U18
T17
W20
V19
7
D
H_INITJ
H_A20MJ
H_SMIJ
H_INTR
H_NMI
H_IGNNEJ
H _FERRJ
H_STPCLKJ
H_CPUSLPJ
H_INITJ
H_A20MJ
H_SMIJ
H_INTR
H_NMI
H_IGNNEJ
H_FERRJ
H_STPCLKJ
H_CPUSLPJ
2
Put closed to 963 CHIP
14
+3V
3
3
3
3
3
3
3
3
3
3
A8
OSC25MHI
14
5
14
6
U18B
7
7
*
8
Programable on-die pull-high strength for CPU_S:
( Infinite, 150, 110, 56 Ohm)
AC_BITCLK
SLP_S3#
SMBALTJ
*
BC389
10pF
50V, NPO, +/-5%
C0402
R208
R0402
dummy
+/-5%
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
10
of
50
8
7
6
5
4
3
2
1
SDATO( Trap
mode)
U18C
3VAUX
D
13
17
17
17
17
18
18
18
18
UCLK48M
UCLK48M
SYSUSBP0+
SYSUSBP0SYSUSBP1+
SYSUSBP1SYSUSBP2+
SYSUSBP2SYSUSBP3+
SYSUSBP3-
UV4+
UV4UV5+
UV5OC0OC1OC2OC3OC4OC5-
3VAUX
FB47
1
2
FB L0805 60 Ohm
*
BC692
10uF
10V, X5R, +/-10%
C1206
*
C
BC681
1uF
C0603
*
BC680
0.1uF
10V, X7R, +/-10%
C0402
connect VSS pin
directly to GND
D0
15
D[0..7]
V4
B18
C18
D18
D19
E14
D15
E18
F18
E16
E15
G18
G19
E11
LINKON
C19
LREQ
A19
USBCLK48M
UV0+
UV0UV1+
UV1UV2+
UV2UV3+
UV3UV4+
UV4UV5+
UV5-
G20
G17
J16
H16
H17
G16
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
D16
D17
E17
F17
USBVDD
USBVDD
USBVDD
USBVDD
F19
E19
B19
B17
USBVSS
USBVSS
USBVSS
USBVSS
A12
SCLK
LPS
A20
GPIO21/EESK
GPIO22/EEDI
GPIO23/EEDO
GPIO24/EECS
F20
D20
E20
C20
GPIO21
GPIO22
GPIO23
GPIO24
USB
963-3
B12
D1
D2
C12
D2
D3
D12
D3
D4
E12
D4
D5
A13
D5
D6
B13
D6
D7
C13
D7
OSC12MHI
B16
OSC12MHI
A17
OSC12MHO
USBREF
USBREF
F16
USBPVDD
USBPVSS
A18
C15
USBPVDD
USBPVSS
IVDD_AUX
IVDD_AUX
C16
C17
IVDD_AUX
IVDD_AUX
IPBRST#
B11
TDFRAME
D10
D11
CTL0
C11
CTL1
GPIO24
GPIO21
GPIO22
GPIO23
1
2
3
4
CS
SK
DI
DO
8
7
6
5
VCC
NC
ORG
GND
AT93C46-2.7V
R702
R0603
412
+/-1%
OSC12MHI
OSC12MHO
R209
R0603
10M
+/-5%
X5
RDFRAME
A11
IPB_RDCLK
E10
IPB_TDCLK
D9
1394
IPB_OUT0/PLLENN
B10
IPB_OUT1/ZCLKSEL
A10
IPB_IN0
C10
IPB_IN1
C9
USBREFAVDD
B
3VAUX
U15
OSC12MHO
D0
D1
D
R705
4.7K
+/-5%
R0402
B20
*
BC286
12M
15pF
50V, NPO, +/-5%
C0402
*
BC285
10pF
50V, NPO, +/-5%
C0402
C
X5 not in CIS
070904 lonny
USBPVDD
+1.8VAUX
IVDD_AUX
SiS963L
*
BC690
1uF
C0603
*
R691
BC686 R0402
10nF
16V, X7R, +/-10%
C0402
0
+/-5%
*
B
BC684
10uF
10V, X5R, +/-10%
C1206
JP20
2
1
SHORT
SB Hardware Trap
+3V
+3V
3VAUX
10,27
PCSPK
10,22,27 AC_SDOUT
OC3OC4OC5OC0OC1OC2-
R739
R742
R737
R239
R736
R743
10K
10K
10K
10K
10K
10K
R0402
R0402
R0402
R0402
R0402
R0402
UV4+
UV4UV5+
UV5-
R731
R730
R236
R235
15K
15K
15K
15K
R0402
R0402
R0402
R0402
PCSPK
R280
AC_SDOUT R305
4.7K
4.7K
R0402
R0402
OC4-
0 R0402 dummy
dummy
dummy
FB48
FB L0805 60 Ohm
1
USBPVDD
R740
BC699
10nF
16V, X7R, +/-10%
C0402
external pull-up at page 28 USB header
*
*
2
BC698
1uF
C0603
*
JP21
USBPVSS
2
BC678
10uF
10V, X5R, +/-10%
C1206
1
SHORT
A
0
SPKR( LPC addr mapping)
disable
1
enable
Default
A
internal pull-low
(30~50K Ohm)
R169 un-stuff
yes
SDATO( Trap from)
ROM
PCI AD
R170 un-stuff
yes
OC4-( SB debug mode)
enable
disable
R171 un-stuff
NO
SYNC( PCICLK PLL)
enable
disable
NONE
TECHNOLOGY COPR.
Title
yes
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
11
of
50
6
5
+1.8V
1uF
C0603
0.1uF
C0402
0.1uF
C0402
BC682
BC683
*
0.1uF
C0402
3
2
1
D
1uF
C0603
*
BC734
BC729
*
0.1uF
C0402
1uF
C0603
BC720
10uF
C1206
*
BC725
*
10uF
C1206
1uF
C0603
*
BC749
*
*
BC748
10uF
C1206
*
BC764
*
BC724
4
+1.8VAUX
*
+3V
*
D
7
0.1uF
C0402
*
8
1uF
C0603
BC732
0.1uF
C0402
BC723
BC768
0.1uF
C0402
BC767
*
0.1uF
C0402
*
*
BC738
BC726
*
+VCCP
BC753
+1.8V
1uF
C0603
Dummy
C
+VCCP
+3V
+VCCP
BC756
*
Put under 96X solder side
0.1uF
C0402
*
BC746
BC752
0.1uF
C0402
+3V
*
+1.8V
0.1uF
C0402
Dummy
3VAUX
BC751
0.1uF
C0402
BC712
*
0.1uF
C0402
*
*
+1.8VAUX
BC733
0.1uF
C0402
0.1uF
C0402
BC719
0.1uF
C0402
BC711
*
BC717
*
B
*
3VAUX
0.1uF
C0402
*
+1.8VAUX
BC674
10uF
BC715
0.1uF
C0402
BC714
*
BC750
0.1uF
C0402
0.1uF
C0402
*
0.1uF
C0402
*
BC754
*
*
0.1uF
C0402
*
C1206
BC747
0.1uF
C0402
*
BC709
1uF
C0603
*
BC713
0.1uF
C0402
U18D
G15
J15
J19
L15
L19
N15
P19
K15
G6
H15
L6
M15
R6
R10
R14
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
PVDDZ
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
P15
R15
VTT
VTT
H6
K6
M6
P6
R7
R9
R11
R13
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
J6
N6
R8
R12
PVDD
PVDD
PVDD
PVDD
F9
F12
IVDD_AUX
IVDD_AUX
F7
F10
F11
F14
F15
OVDD_AUX
OVDD_AUX
OVDD_AUX
OVDD_AUX
OVDD_AUX
F8
F13
PVDD_AUX
PVDD_AUX
963
-4
Power
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H8
H9
H10
H11
H12
H13
J8
J9
J10
J11
J12
K8
K9
K10
K11
L8
L9
L10
L11
M8
M9
M10
M11
N8
N9
N10
N11
N12
N13
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
J13
J17
K12
K13
L12
L13
L17
M12
M13
P17
C
B
SiS963L
BC728
A
A
TECHNOLOGY COPR.
Title
Document Number
Rev
915S02
Date:
Friday, August 13, 2004
A
Sheet
12
of
50
8
7
6
5
4
3
2
1
Main Clock Generator
(5 OPTIONS)
1: (ICS)
2: (Cypress)
3. (Hitachi)
4: ()
5: ()
Damping Resistors
Place near to the
Clock Outputs
+3V Connect pin 12 PCI_STOP#
lonny 2004-06-01
VCC3_CLK
*
BC135
0.1uF
C0402
*
*
BC83
0.1uF
C0402
BC136
0.1uF
C0402
*
*
BC114
0.1uF
BC130
0.1uF
*
C0402
*
C0402
BC137
0.1uF
BC95
0.1uF
C0402
*
C0402
BC94
0.1uF
+3V
*
C
R61
10K
+/-1%
R0603
CPUSTP-
CPUSTP-
BC97
470pF
R52
R0402
C0402
+3V
*
475
+/-1%
5
8
18
24
25
32
41
46
FB L0805 80 Ohm
2
BC96
0.1uF
*
CPU_STOP#
33
PD#/VTT_PWRGD
38
IREF
CPUCLK1
CPUCLK#1
44
43
R57
R58
SDCLK
47
AGPCLK0
AGPCLK1
31
30
ZCLK0
ZCLK1
9
10
PCICLK_F0/FS3
PCICLK_F1/FS4
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
14
15
16
17
20
21
22
23
C0402
*
REF0/FS0
REF1/FS1
REF2/FS2
PCI_STOP#
36 VDDA
BC86
1nF
50V, X7R, +/-10%
C0402
37 VSSA
2
3
4
48M
24_48M/MULTISEL
27
26
SCLK
SDATA
35
34
6
C0402
VSSREF
VSSZ
VSSPCI
VSSPCI
VSS48
VSSAGP
VSSCPU
VSSSD
45
VCC3_CLK 12
FB6
1
BC75
0.1uF
R66
R68
C0402
+3V
R54
10K
10
+/-1%
R0603
CPUCLK0
CPUCLK#0
40
39
By-Pass Capacitors
Place near to the Clock Outputs
D
33
33
22
22
R99
R115
R0603
R0603
22
22
R100
AGPCLK0
AGPCLK1
AGPCLK0
AGPCLK1
96XPCLK
PCLK_LAN
PCLK_591
MINIPCICLK
CARDBUDCLK
PCLK_1394
33R0603 REFCLK0
33R0603 REFCLK1
33R0603 REFCLK2
R53
MULTISEL
22
R0603
5
41
ZCLK0
ZCLK1
96XPCLK
33R0603
33R0603
33R0603
33R0603
33R0603
R80
R96
R98
CLK_MCH_BCLK 5
CLK_MCH_BCLKJ 5
R0603 ZCLK0
R0603 ZCLK1
33R0603
R69
R75
R81
R82
R101
FS0
FS1
FS2
CLK_CPU_BCLK 3
CLK_CPU_BCLKJ 3
33R0603 CLK_MCH_BCLK
33R0603 CLK_MCH_BCLKJ
R55
R56
FS3
FS4
R0603 CLK_CPU_BCLK
R0603 CLK_CPU_BCLKJ
REFCLK0
REFCLK1
UCLK48M
SMBCLK
SMBDAT
7
9
9
PCLK_LAN 29
PCLK_591 15
MINIPCICLK
22
CARDBUDCLK 23
PCLK_1394 23
7
10
UCLK48M
11
SMBCLK
SMBDAT
10,14,19,46
10,14,19,46
XOUT
C1206
*
VDDREF
VDDZ
VDDPCI
VDDPCI
VDD48
VDDAGP
VDDCPU
VDDSD
ICS952005
7
BC92
22uF
1
11
13
19
28
29
42
48
XIN
D
U7
CLK_MCH_BCLKJ
CLK_MCH_BCLK
R49
R48
CLK_CPU_BCLK
CLK_CPU_BCLKJ
R65
R70
AGPCLK0
BC90
AGPCLK1
BC91
ZCLK0
BC161
ZCLK1
BC175
96XPCLK
BC162
PCLK_1394
BC164
PCLK_LAN
BC109
CARDBUDCLK
BC131
MINIPCICLK
BC118
REFCLK0
BC117
REFCLK1
BC159
REFCLK2
BC160
UCLK48M
BC89
49.9 R0402 +/-1%
49.9 R0402 +/-1%
49.9 R0402 +/-1%
49.9 R0402 +/-1%
** ** **
2
FB L0805 60 Ohm
***
FB5
***
1
+3V
10pF
C0402
10pF
C0402
10pF
C0402
10pF
C0402
10pFC0402
10pFC0402
10pF
C0402
10pF
C0402
10pF
C0402
10pF
C0402
10pF
C0402
10pF
C0402
10pF
C0402
C
X3
BC133
10pF
*
C0402
2
XTAL-14.318MHz
*
BC134
10pF
C0402
+3V
R114
10K
+/-1%
R0402
Dummy
B
+3V
*
BC84
22uF
C1206
*
BC85
0.1uF
C0402
*
BC74
1nF
50V, X7R, +/-10%
C0402
4
CPU_BSEL0
4
CPU_BSEL1
*
1
R113
10K
+/-1%
R0402
B
CPU_BSEL0
R92
CPU_BSEL1
2.7K
R93
R0402 FS2
2.7K
R0402
FS3
+3V
+/-5%
FS4
R94
2.7K
R0402
FS0
R79
2.7K
R0402
FS1
R97
2.7K
R0402
MULTISEL
R44
R0402
dummy
0
+/-5%
A
A
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
13
of
50
7
6
5
4
3
Clock Buffer (DDR)
2
1
DDRCLK[0..8]
DDRCLK[0..8] 19
DDRCLK-[0..8]
(OPTIONS)
1: (ICS-93705)
DDRCLK-[0..8] 19
SMBCLK
SMBDAT
SMBCLK
SMBDAT
FWDSDCLKO
D
10,13,19,46
10,13,19,46
FWDSDCLKO 6
D
U20
SMBCLK R329 R0402
SMBDAT R260 R0402
0 +/-5% Dummy 12
0 +/-5% Dummy 37
CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
CLK#6
CLK#7
CLK#8
CLK#9
2
6
9
19
23
47
43
40
30
26
R315
R323
R324
R326
R321
R268
R271
R272
R274
FWDSDCLKO
13
FB_OUT
NC
33
32
R259
R0603
SCLK
SDATA
CLK_IN
C
14
FB_OUT
35
NC
FB_IN
DDRCLK0
BC419
C0402
0
0
0
0
0
0
0
0
0
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
DDRCLK-0
DDRCLK-1
DDRCLK-2
DDRCLK-8
DDRCLK-5
DDRCLK-4
DDRCLK-3
DDRCLK-7
DDRCLK-6
DDRCLK2
BC444
C0402
BC439
C0402
DDRCLK8
DDRCLK5
DDRCLK4
DDRCLK3
BC351
C0402
DDRCLK6
BC347
C0402
DDRCLK-0
BC420
C0402
DDRCLK7
22 FB_OUT
+/-1%
DDRCLK-2
BC440
C0402
*
DDRCLK-5
ICS93705
BC352
C0402
*
BC346
C0402
*
*
DDRCLK-4
DDRCLK-3
*
DDRCLK-7
DDRCLK-6
FB_OUT
B
BC369
VDIMM
FB30
1
*
BC463
0.1uF
*
*
C1206
*
BC370
10nF
*
C0402
BC462
10nF
C0402
10pF
C0402
B
FB L0805 60 Ohm
2CBVDD
C0402
BC459
22uF
10pF Dummy
50V, NPO, +/-5%
BC442
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
BC437
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
BC349
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
BC353
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
*
DDRCLK-8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
7
8
18
24
25
31
41
42
48
BC443
C0402
*
NC
C
*
DDRCLK-1
36
10pF Dummy
50V, NPO, +/-5%
BC441
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
BC438
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
BC350
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
BC354
10pF Dummy
C0402
50V, NPO, +/-5%
10pF Dummy
50V, NPO, +/-5%
*
DDRCLK1
*
AGND
C0402
By-Pass Capacitors
Place near to the Clock Buffer
*
*
C0402
BC429
10nF
DDRCLK0
DDRCLK1
DDRCLK2
DDRCLK8
DDRCLK5
DDRCLK4
DDRCLK3
DDRCLK7
DDRCLK6
*
*
C1206
BC435
0.1uF
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
*
*
BC454
10uF
0
0
0
0
0
0
0
0
0
*
17
R319
R322
R325
R327
R320
R269
R270
R273
R275
*
AVDD
3
5
10
20
22
46
44
39
29
27
*
16
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
2
FB29
FB L0805 60 Ohm
VDDI2C
VDD
VDD
VDD
VDD
VDD
VDD
VDD
*
1
VDIMM
15
4
11
21
28
34
38
45
*
CBVDD
*
8
*
BC461
22uF
C1206
*
BC453
0.1uF
*
C0402
BC372
0.1uF
C0402
*
BC455
0.1uF
*
C0402
BC431
0.1uF
C0402
*
BC367
0.1uF
*
C0402
BC432
0.1uF
C0402
*
BC368
0.1uF
C0402
BC433
0.1uF
C0402
*
BC434
0.1uF
C0402
A
A
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
14
of
50
4
3
2
3,39
MBCLK
3,39
MBDATA
+3VALW_591
39 MBAT_PRESJ
R597
4.7K
R0603
+/-5%
Follow TPC01 update sch
070904 lonny
39
MBATV
18 WIRELESS_SWJ
B
10
34,36
1
3
1
HOLDJ
R662
10K
R0402
+/-5%
Dummy
*
MDC_RINGJ
Q15
DTA124EUA
2 NBSWONJ
D38 2
1SS355
D37 2
1SS355
1 SUSBJ
1
ACIN
ACIN
MBATV
39
39
39
32
SUSCJ
HWPG
CC_SET
CV_SET
VFAN
16
MX0
16
MX1
16
MX2
16
MX3
16
MX4
16
MX5
16
MX6
16
MX7
16
MY0
16
MY1
16
MY2
16
MY3
16
MY4
16
MY5
16
MY6
16
MY7
16
MY8
16
MY9
16
MY10
16
MY11
16
MY12
16
MY13
16
MY14
16
MY15
10,22,29 CLKRUNJ
SUSCJ
HWPG
DP/AD8
DN/AD9
CC-SET
CV-SET
VFAN
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
163
169
164
170
SCL1/IOPB3
SCL2/IOPC1
SDA1/IOPB4
SDA2/IOPC2
81
82
83
84
87
88
89
90
93
94
99
100
101
102
AD0
AD1
AD2
AD3
AD4/IOPE0
AD5/IOPE1
AD6/IOPE2
AD7/IOPE3
AD8/DP
AD9/DN
DA0
DA1
DA2
DA3
71
72
73
74
77
78
79
80
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
CLKRUNJ 25
5
6
LAD0/FWH0
15
10
LAD0/FWH0
LAD1/FWH1
+3VALW_591
14
10 LAD1/FWH1
LAD2/FWH2
13
10 LAD2/FWH2
PCLK_591
LAD3/FWH3
10
10 LAD3/FWH3
PCLK_591
R657
18
13
PCLK_591
470K
R175
1
2
31
10
SCIJ
+/-1%
33
D35
RB751V-40
8
LFRAMEJ/FWH4
R0603
+/-5%
9
10 LFRAMEJ/FWH4
LPCPDJ
R0402
D36
24
591RESET 1SS355 1
591RESETJ
2
19
BC268
23
SERIRQ
10pF
7
10,23 SERIRQ
KBSMIJ591
C0603
1
2
22
10
KBSMIJ
????
HOLDJ
D11
RB751V-40
26
MDC_RINGJ
29
22 MDC_RINGJ
FANSIG
172
32
FANSIG
LAN_PME_591J
176
29 LAN_PME_591J
TEMP_ALERTJ
30
3 TEMP_ALERTJ
SUSBJ
44
10,29
SUSBJ
PCIRSTJ
R632
0
+/-5% R0402 Dummy
165
27
EC_BEEP
9,17,22,23,29,40,41 PCIRSTJ
REFON
175
39
REFON
DNBSWONJ591
D34 1
2RB751V-40 Dummy
171
PWRBTN
???? 10
NBSWONJ
2
18,50 NBSWONJ
????
VADJ
32
21
PWM-ADJ
R179
0
+/-5% R0402 Dummy
33
36 SAVE_POWER_M10
R178
0
+/-5% R0402
36
27
EC_BEEP
SUSPEND_LEDJ
R180
0
+/-5% R0402
37
31,35
VRON
MAINON
38
22,33,34,36,38 MAINON
SUSON
39
+5V
10,33,38 SUSON
3VAUX_EN
40
34,50 3VAUX_EN
43
41
D33
42
RN5
RB751V-40
54
10K
Dummy
55
8P4R0603
1
2
168
10
PWRBTN
+/-5%
110
114
39
CHA_OFF
116
TPCLK
118
SCROLL_LOCK_LEDJ
111
115
117
TPDATA
NUMLEDJ
119
NUMLEDJ
ACCESS
BUS
I/F
32KCLKIN/32KX1
32KX2
CLK
CLKOUT/SIOCLKIN/IOPC7
158
160
47
1
A0/ENV0/IOPH0
A1/ENV1/IOPH1
A2/BADDR0/IOPH2
A3/BADDR1/IOPH3
A4/TRIS/IOPH4
A5/SHBM/IOPH5
A6/IOPH6
A7/IOPH7
A8/IOPK0
A9/IOPK1
A10/IOPK2
A11/IOPK3
A12/IOPK4
A13/BE0/IOPK5
A14/BE1/IOPK6
A15/CBRD/IOPK7
A16/IOPL0
A17/IOPL1
A18/IOPL2
A19/IOPL3
& DSS D0/IOPI0
D1/IOPI1
D2/IOPI2
D3/IOPI3
D4/IOPI4
D5/IOPI5
D6/IOPI6
D7/IOPI7
D8/IOPM0
D9/IOPM1
D10/IOPM2
D11/IOPM3
D12/IOPM4
D13/IOPM5
D14/IOPM6
D15/IOPM7
RD#/IOPJ0
WR0#/IOPJ1
SELIO#
WR1#/IOPL4
BRKL#_RSTO#/IOPJ7
BST0/IOPJ2
BST1/IOPJ3
BST2/IOPJ4
PFS#/IOPJ5
PLI/IOPJ6
TCK
TDI
TDO
TINT#
TMS
SEL0#
SEL1#
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
138
139
140
141
144
145
146
147
148
149
155
156
3
4
27
28
150
151
152
48
76
62
63
69
70
75
106
108
107
105
109
173
174
URXD/IOPB0
UTXD/IOPB1
USCLK/IOPB2
153
154
162
AGND
AVCC
GND
GND
GND
GND
GND
GND
GND
VBAT
VCC
VCC
VCC
VCC
VCC
VCC
VDD
96
95
17
35
46
122
137
159
167
161
34
45
123
136
157
166
16
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
11
12
20
21
85
86
91
92
97
98
CLOCKS
ANALOG
I/F
BIU
KBC
CLKRUN#/EXWINT46/IOPE7
GA20/IOPB5
KBRST#/IOPB6
LAD0
LAD1
LAD2
LAD3
LCLK
ECSCI#/IOPD3
LDRQ#
LFRAME#
LPCPD#/EXWINT45/IOPE6
LRESET#
PWUREQ
SERIRQ
SMI#
EXWINT20/RI1#/IOPD0
EXWINT21/RI2#/IOPD1
EXWINT22/TB1/IOPC4
EXWINT23/TB2/IOPC6
EXWINT24/IOPD2
EXWINT40/IOPE5
PFAIL#/RING#/IOPB7
TA2/IOPC5
HOST
TA1/IOPC3
ICU
SWIN/IOPE4
MIWU
PWM0/IOPA0
PWM1/IOPA1
PWM
PWM2/IOPA2
MSWC
PWM3/IOPA3
PWM4/IOPA4
PWM5/IOPA5
PWM6/IOPA6
PWM7/IOPA7
IOPD4
IOPD5
IOPD6
IOPD7
IOPC0
USART
POWER &
GROUND
8
6
4
2
*
7
5
3
1
B
*
+3VALW_591
3
C
BC140
2.2nF
Q11
E
C
MMBT3904 C0603
Q16
DTA124EUA
2
MBAT_PRESJ
WIRELESS_SWJ
D
+3VALW_591
MBCLK
SBCLK
MBDATA
SBDATA
A
16
18
FB9
1
+3VALW_591
FB L0603 300 Ohm
2
REF3V
Dummy
*
+3VALW_591
BC141
4.7uF
10V, Y5V, +80%/-20%
C0805
PSCLK1/IOPF0
PSCLK2/IOPF2
SCLK3/IOPF4
PSCLK4/IOPF6
PSDAT1/IOPF1
PSDAT2/IOPF3
PSDAT3/IOPF5
PSDAT4/IOPF7
NC
PS2 I/F
BC143
C0402
BC625
C0402
BC646
C0402
BC654
C0402
****
16
591_32KX1
591_32KX2
591_32KX1
PWRGD
PWROK_1
D10 2
RB751V-40
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
D0
D1
D2
D3
D4
D5
D6
D7
1
R177
R0402
591_32KX2
4
R145
20M
+/-5%
R0603
X4
XTAL-32.768MHz
R143
120K
+/-5%
R0603
BC239
C0402
22pF
22pF
D
+3VALW
BIOS_CONN1
*
11
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CSJ
RDJ
A18
W RJ
BC72
0.1uF
10V, X7R, +/-10%
C0402
D[0..7]
RF_ENABLE
22
????
VOL_MUTE
27
32
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
22
24
1
31
16
RDJ
W RJ
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE
OE
VPP
PGM
GND
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
17
18
19
20
21
O0
O1
O2
O3
O4
O5
O6
O7
U15
SST39VF040
C
PLCC-32-SKT
CAPSLEDJ
MXLIDJ
BC232
C0402
1K
+3V
+/-1%
CAPSLEDJ
R106
+/-5%
0
R0402
18
SUSOK
MXLIDJ
34,36
21
ACIN
TCK-591
TDI-591
TDO-591
TINTTMS-591
CSJ
+3VALW
CONN1
11
BATLEDJ
18
PWR_LEDJ
PWR_LEDJ
FB37
FB L0603 300 Ohm
1
2
BC149
0.1uF
*
18
REF3V
1110
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
TINTTCK-591
R105
10K
R0402 +/-5%
Dummy
TDO-591
TDI-591
Z3009
TMS-591
ENV1
R91
10K
R0402 +/-5%
Dummy
B
Header_1X10
Dummy
C0402
VCCRTC
+3VALW_591
BC643
*
BC665
0.1uF
10V, X7R, +/-10%
C0402
0.1uF C0402
+3VALW_591
R648
R643
10K +/-5% R0402
10K +/-5% R0402
TEMP_ALERTJ
LAN_PME_591J
+3VALW_591
*
*
+3V
BC652
0.1uF
10V, X7R, +/-10%
C0402
BC651
1uF
10V, X5R, +/-10%
C0603
Dummy
SBCLK
SBDATA
MBCLK
MBDATA
R625
R629
R611
R617
4.7K
4.7K
4.7K
4.7K
ENV1
R89
10K R0402 +/-5%
BADDR0
BADDR1
R90
R104
10K R0402 +/-5% Dummy
10K R0402 +/-5% Dummy
LPCPDJ
SHBM
R649
R103
10K R0402 +/-5%
10K R0402 +/-5%
R0402
R0402
R0402
R0402
+/-5%
+/-5%
+/-5%
+/-5%
+3VALW_591
A
0.1uF
TECHNOLOGY COPR.
0.1uF
Title
0.1uF
PC87591L & FLASH
Document Number
0.1uF
Re v
661S03
Date:
5
7,10,31
*
100K
+/-5%
*
R95
R0402
1
2
HWPG
1
PC87591L
4
3
U10
*
5
3
2
Friday, August 13, 2004
A
Sheet
1
15
of
50
5
4
3
2
1
KEY BOARD
TOUCH PAD
D
D
CN4
MX1
MX7
MX6
MY9
MX4
MX5
MY0
MX2
MX3
MY5
MY1
MX0
MY2
MY4
MY7
MY8
MY6
MY3
MY12
MY13
MY14
MY11
MY10
MY15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
+5V
BC373
C0805
4.7uF
BC363
0402
0.1uF
15
15
TPDATA
TPCLK
2
MX1
MX7
MX6
MY9
MX4
MX5
MY0
MX2
MX3
MY5
MY1
MX0
MY2
MY4
MY7
MY8
MY6
MY3
MY12
MY13
MY14
MY11
MY10
MY15
CN5
FB23
2 FB L0805 120 Ohm
1
1
FB56
FB L0805 180 Ohm
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
* *
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
FB21
FB L0805 120 Ohm
*
BC343
10pF
*
C0603
Dummy
C
BC357
10pF
50V
C0603
Dummy
1
2
3
4
5
6
1
2
3
4
5
6
TOUCHPAD CONN
C
KB CONN
+3V
B
MX7
MX6
MX5
MX4
1
2
3
4
5
MX0
MX1
MX2
MX3
BCN1
1
2
MX4
3
4
MY1
3
4
MX5
5
6
MY2
5
6
MX6
8
8P4R0603
220pF
50V, NPO, +/-10%
MY3
7
8
8P4R0603
220pF
50V, NPO, +/-10%
MX7
7
BCN4
2
MY8
1
2
MX0
3
4
MY9
3
4
MX1
5
6
MY10
5
6
MX2
7
MY11
8
220pF
8P4R0603
50V, NPO, +/-10%
7
8
8P4R0603
220pF
50V, NPO, +/-10%
MX3
*
1
2
MY4
*
BCN5
A
B
BCN2
1
*
+/-5% 10P8R0603
MY0
*
8.2K
10
9
8
7
6
2
*
RN29
*
BCN6
1
BCN3
1
2
MY12
3
4
MY5
3
4
MY13
5
6
MY6
5
6
MY14
7
8
8P4R0603
220pF
50V, NPO, +/-10%
MY7
7
8
MY15
A
8P4R0603
220pF
50V, NPO, +/-10%
TECHNOLOGY COPR.
Title
KB & TOUCHPAD
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
16
of
50
A
B
C
D
E
ODD CONNECTOR
+5VSUS
CON1
RCDL
CDGND
N22385929
R939
33
CDD7
R0402
+/-5%
CDD6
+3V
CDD5
CDD4
CDD3
CDD2
R933
CDD1
4.7K
CDD0
+/-5%
R0402
RIDEIOW-B
R946
22 R0402
RICHRDY-B
R943
22 R0402
RIDEIRQ-B
R942
82 R0402
CDS1
CDS0
R940
33 CDCS-B0
IDECS-B0
R0402
+/-5%
ODD_LEDJ
BAYVCC
27
27
4
9,15,22,23,29,40,41 PCIRSTJ
9
9
9
IDEIOW-B
ICHRDYB
IDEIRQB
R932
9
10K
18
+/-5%
R0402
RCDL
CDGND
R936
R0603
+3V
U31
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
CDCSEL
470
+/-5% Dummy
RC DR
RCDR
CDGND
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
RIDEREQB
R945
RIDEIOR-B
R944
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
RIDACK-B
*
R941
82
22
R0402
R0402
IDEREQB
IDEIOR-B
9
9
22
R0402
IDACK-B
9
BC529
0.1uF
16V, X7R, +/-10%
C0402
GND
IN
IN
EN
OUT
OUT
OUT
OC
USB1PWR
8
7
6
5
4
*
MAX1607ESA
EC23
220uF
10V, +/-20%
CTX
*
BC528
0.1uF
BC527
0.1uF
C0402
C0402
*
CDS2
CDCS-B1
+5V
BAYVCC
FB62
2
1
FB L0805 30 Ohm
*
BC856
0.1uF
10V, X7R, +/-10%
C0402
CN7
CDCS-B1
CDS1
CDS2
CDS0
*
2IDECS-B1
4IDESAB1
6IDESAB2
8IDESAB0
1
3
5
7
IDECS-B1
IDESAB1
IDESAB2
IDESAB0
2
USB1PWR
SYSUSBP1-_1
3
SYSUSBP1+_1
L2
RN46
0.8P BTB_DIP 50P
3
1
2
3
4
27
9
9
9
9
11 SYSUSBP1-
1
11 SYSUSBP1+
4
1
2
3
4
Common Choke 90 Ohm 2L
5
1 GND
2
3
4 GND
6
USB CONN1
3
33
+/-5%
8P4R0402
HDD CONNECTOR
CN12
PCIRSTJ
15,22,23,29,40,41 PCIRSTJ
9
9
9
9
9
9
2
R418
R419
R420
R422
R423
R425
IDEREQA
IDEIOW-A
IDEIOR-A
ICHRDYA
IDACK-A
IDEIRQA
R424
10K
+/-5%
R0402
R435
82
22
22
22
22
82
33
R0402
R0402
R0402
R0402
R0402
R0402
18
R0402
N22385788
HDD7
HDD6
HDD5
HDD4
HDD3
HDD2
HDD1
HDD0
R430
5.6K
+/-5%
R0402
RIDEREQA
RIDEIOW-A
RIDEIOR-A
RICHRDY-A
RIDACK-A
RIDEIRQA
HDA1
HDA0
RIDECS-A0
HDD0_LED
R421
4.7K
+/-5%
R0402
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
HDD_VDD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15
CN8
2
USB1PWR
SYSUSBP0-_1
3
SYSUSBP0+_1
L1
11 SYSUSBP0-
1
11 SYSUSBP0+
4
Common Choke 90 Ohm 2L
*
1 GND
2
3
4 GND
5
6
USB CONN2
2
CBLIDA
HDA2
R433
R0402
HDD CONN
1
2
3
4
CBLIDA
9
33
+/-5%
IDECS-A1
BC518
0.1uF
16V, X7R, +/-10%
C0402
*
9
HDD_VDD
BC519
1nF
50V, X7R, +/-10%
C0402
*
BC510
2.2uF
16V, Y5V, +80%/-20%
C0805
+3V
HDD[0..15]
HDD_VDD
FB32 FB L1806 60 Ohm
1
2
HDD[0..15]
9
+5V
CDD[0..15]
CDD[0..15]
9
BAYVCC
1
1
RN22
*
BC864
0.1uF
16V, X7R, +/-10%
C0402
*
BC860
0.1uF
16V, X7R, +/-10%
C0402
*
BC859
0.1uF
16V, X7R, +/-10%
C0402
*
9
9
9
9
BC863
0.1uF
16V, X7R, +/-10%
C0402
IDECS-A0
IDESAA2
IDESAA0
IDESAA1
*
1
3
5
7
2
4
6
8
RIDECS-A0
HDA2
HDA0
HDA1
TECHNOLOGY COPR.
Title
33
+/-5%
8P4R0402
HDD/ODD/USB_1
Document Number
Re v
661S03
Date:
A
B
C
D
Friday, August 13, 2004
A
Sheet
E
17
of
50
5
4
3
2
1
+3V
D1
BAT54A
3
CN1
WILLIAM
071604
NUMLEDJ
1
15
D
2
ODD_LEDJ
15
Q35
DTA124EUA
2
CAPSLEDJ
Q3
DTA124EUA
2
28
INT_MIC
1
17
R1
330
+/-5%
R0603
1
HDD0_LED
1
17
1
D
Q2
DTA124EUA
SCROLL_LOCK_LEDJ
15
2
1
2
3
4
5
6
7
8
SCROLL_LOCK_LED
IDE_LED
CAPSLED
NUMLED
BATLED
Q4
DTA124EUA
2
1
2
3
4
5
6
7
8
R473
R0603
NUMLED
330
+/-5%
3
3
3
3
LED WTB CONN
CAPSLED
330
+/-5%
R474
R0603
IDE_LED
330
+/-5%
R472
R0603
330 SCROLL_LOCK_LED
+/-5%
R471
R0603
+3VSUS
C
C
+5VSUS
15
PWR_LEDJ
PWR_LEDJ
2
15
BATLEDJ
BATLEDJ
2
DTA124EUA
22
RF_LEDJ
RF_LEDJ
U21
1
2
3
4
1
Q75
DTA124EUA
1
Q74
DTA124EUA
1
Q73
*
2
BC427
0.1uF
GND
IN
IN
EN
OUT
OUT
OUT
OC
MAX1607ESA
3
3
3
C0402
8
7
6
5
USB2PWR
*
TC6
220uF
10V, +/-20%
CTX
*
BC428
0.1uF
*
C0402
BC446
0.1uF
C0402
PWR_LED
BATLED
RF_LED
close to the J6
william
073104
B
B
0 R0402
R462
0 R0402
302LV_CRT_B
R463
0 R0402
R458
0 R0402
7
302LV_CRT_G
R460
0 R0402
R454
0 R0402
302LV_CRT_R
R456
0 R0402
R452
0 R0402
R450
0 R0402
CN13
M10_CRT_B
R464
0 R0402 @M10
CRT_B
41
M10_CRT_G
R459
0 R0402 @M10
CRT_G
41
M10_CRT_R
R455
0 R0402 @M10
CRT_R
+5V
A
0 R0402
R466
7
7
41
R468
BC523
0.1uF
16V, X7R, +/-10%
C0402
+3V
*
21
LIDJ
15 WIRELESS_SWJ
15,50 NBSWONJ
L IDJ
WIRELESS_SWJ
NBSWONJ
R0402
+/-5%
8.2K
R954
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CRT BTB CONN
DDCCLK
CRTVS_VGA
CRTHS_VGA
DDCDAT
TV_CHROMA
TV_LUMA
TV_COMP
R467
R465
R461
R457
R453
R451
R449
0
0
0
0
0
0
0
R0402
R0402
R0402
R0402
R0402
R0402
R0402
302LV_DDCCLK 7
J2
USB2PWR
302LV_CRTVS_VGA 7
302LV_CRTHS_VGA 7
USBGND
302LV_DDCDAT 7
11 SYSUSBP211 SYSUSBP2+
11 SYSUSBP311 SYSUSBP3+
28
EXTMIC
28
EXTMICIN
27
VREFOUT
302LV_TV_CHROMA 40
302LV_TV_LUMA 40
302LV_TV_COMP 40
@M10
@M10
@M10
@M10
@M10
@M10
@M10
M10_DDC1CLK 41
M10_CRTVS_VGA 41
M10_CRTHS_VGA 41
M10_DDC1DAT 41
M10_TV_CHROMA 41
M10_TV_LUMA 41
M10_TV_COMP 41
AUDGND
27 SHUNDOWNJ
27 HPSPKL+_CON
27 HPSPKR+_CON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
audio conn
+5VAA
+5V
+3V
A
RF_LED
PWR_LED
FB31 1
FB L0805 60 Ohm
USBGND
2
TECHNOLOGY COPR.
+3VSUS
BC522
0.1uF
C0402
Title
*
LED
Document Number
Re v
A
+3V
Date:
5
4
3
2
Friday, August 13, 2004
Sheet
1
18
of
50
6
5
6,20
/RCS-0
/RCS-1
121
122
CS0
CS1
/RDQM0
/RDQM1
/RDQM2
/RDQM3
/RDQM4
/RDQM5
/RDQM6
/RDQM7
12
26
48
62
134
148
170
184
78
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8
SWESCASSRAS-
119
120
118
WE
CAS
RAS
CKE0
CKE1
96
95
CKE0
CKE1
/RCS-0
/RCS-1
C
6,20
6,20
6,20
14
14
14
14
14
14
/RSWE/RSCAS/RSRAS-
DDRCLK0
DDRCLK-0
DDRCLK1
DDRCLK-1
DDRCLK2
DDRCLK-2
6,20
6,20
6,20
6,20
6,20
6,20
6,20
6,20
B
/RDQS0
/RDQS1
/RDQS2
/RDQS3
/RDQS4
/RDQS5
/RDQS6
/RDQS7
10,13,14,46 SMBDAT
10,13,14,46 SMBCLK
DCLK0
-DCLK0
DCLK1
-DCLK1
DCLK2
-DCLK2
35
37
160
158
89
91
CK0
CK0
CK1
CK1
CK2
CK2
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
11
25
47
61
133
147
169
183
77
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SMBDT
SMBCLK
193
195
SDA
SCL
194
196
198
1
2
199
197
SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD
86
85
123
124
200
NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU
DDRVREF
VDIMM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
/RDQM[0:7]
SODIMM_200P-STD
VDIMM
A
DDRVREF GEN. & DECOUPLING
R67
75
+/-1%
R0402
*
BC107
10nF
C0402
*
BC105
10nF
C0402
*
BC110
10nF
C0402
-CS/-RAS/-CAS/-WE
R - 0101
W - 0100
*
BC113
10nF
C0402
9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192
CKE[0:3]
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
71
73
79
83
72
74
80
84
/RMD0
/RMD1
/RMD2
/RMD3
/RMD4
/RMD5
/RMD6
/RMD7
/RMD8
/RMD9
/RMD10
/RMD11
/RMD12
/RMD13
/RMD14
/RMD15
/RMD16
/RMD17
/RMD18
/RMD19
/RMD20
/RMD21
/RMD22
/RMD23
/RMD24
/RMD25
/RMD26
/RMD27
/RMD28
/RMD29
/RMD30
/RMD31
/RMD32
/RMD33
/RMD34
/RMD35
/RMD36
/RMD37
/RMD38
/RMD39
/RMD40
/RMD41
/RMD42
/RMD43
/RMD44
/RMD45
/RMD46
/RMD47
/RMD48
/RMD49
/RMD50
/RMD51
/RMD52
/RMD53
/RMD54
/RMD55
/RMD56
/RMD57
/RMD58
/RMD59
/RMD60
/RMD61
/RMD62
/RMD63
/RMD[0:63]
6,20
6,20
14
14
14
14
14
14
/RMA0
/RMA1
/RMA2
/RMA3
/RMA4
/RMA5
/RMA6
/RMA7
/RMA8
/RMA9
/RMA10
/RMA13
/RMA14
112
111
110
109
108
107
106
105
102
101
115
100
99
97
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13
/RMA11
/RMA12
117
116
98
BA0
BA1
DU/BA2
121
122
CS0
CS1
/RDQM0
/RDQM1
/RDQM2
/RDQM3
/RDQM4
/RDQM5
/RDQM6
/RDQM7
12
26
48
62
134
148
170
184
78
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8
SWESCASSRAS-
119
120
118
WE
CAS
RAS
CKE2
CKE3
96
95
CKE0
CKE1
6,20
/RCS-2
/RCS-3
35
37
160
158
89
91
CK0
CK0
CK1
CK1
CK2
CK2
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
11
25
47
61
133
147
169
183
77
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SMBDT
SMBCLK
193
195
SDA
SCL
194
196
198
1
2
199
197
SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD
86
85
123
124
200
NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU
DDRCLK3
DDRCLK-3
DDRCLK4
DDRCLK-4
DDRCLK5
DDRCLK-5
VDIMM
DDRVREF
VDIMM
SODIMM_200P-RVS
Outsight
DIMM1
Upper
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
BA0
BA1
DU/BA2
1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
117
116
98
3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
126
138
150
162
174
186
6,20
2
3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
126
138
150
162
174
186
/RMA11
/RMA12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
GND
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13
CKE[0:3]
DIMM2
Lower
201
202
112
111
110
109
108
107
106
105
102
101
115
100
99
97
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
/RMA0
/RMA1
/RMA2
/RMA3
/RMA4
/RMA5
/RMA6
/RMA7
/RMA8
/RMA9
/RMA10
/RMA13
/RMA14
/RMA[0..14]
6,20
6,20
9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192
REQUIRED POWER
VDD=VDDQ
VDD!=VDDQ
VDDID
OPEN
GND
6,20
3
VDIMM
VDDID IS A TRAP ON THE DIMM
MODULE TO INDICATE:
D
4
VDIMM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
71
73
79
83
72
74
80
84
D
/RMD0
/RMD1
/RMD2
/RMD3
/RMD4
/RMD5
/RMD6
/RMD7
/RMD8
/RMD9
/RMD10
/RMD11
/RMD12
/RMD13
/RMD14
/RMD15
/RMD16
/RMD17
/RMD18
/RMD19
/RMD20
/RMD21
/RMD22
/RMD23
/RMD24
/RMD25
/RMD26
/RMD27
/RMD28
/RMD29
/RMD30
/RMD31
/RMD32
/RMD33
/RMD34
/RMD35
/RMD36
/RMD37
/RMD38
/RMD39
/RMD40
/RMD41
/RMD42
/RMD43
/RMD44
/RMD45
/RMD46
/RMD47
/RMD48
/RMD49
/RMD50
/RMD51
/RMD52
/RMD53
/RMD54
/RMD55
/RMD56
/RMD57
/RMD58
/RMD59
/RMD60
/RMD61
/RMD62
/RMD63
C
B
GND
GND
7
201
202
8
NOTE:
Insight
PC2100 - CL2 = 15 to Data 2-2-2/2.5-3-3
CL2.5 = 18.75 to Data
DDR266 256MB 4Bks Pmax = 8W
Ptyp = 7W
64MB/128MB/256MB - 500MB/s - 1.0W
- 1000MB/s - 1.65W
- 1500MB/s - 2.5W
- 2000MB/s - 3.2W
A
DDRVREF
R71
75
+/-1%
R0402
*
BC111
10nF
C0402
*
BC112
10nF
C0402
*
BC108
10nF
C0402
*
BC106
10nF
C0402
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
19
of
50
8
7
6
5
4
3
2
1
SSTL-2 Termination Resistors
SDR
/RMD[0..63]
/RMD[0..63]
/RDQM[0..7]
D
/RDQS[0..7]
/RMA[0..14]
/RCS-[0..3]
6,19
/RDQM[0..7]
6,19
/RDQS[0..7]
6,19
/RMA[0..14]
6,19
/RCS-[0..3]
6,19
MD/DQM(/DQS)
MA/Control
CS
CKE
DDR
Rs
0/10/10
0
LV-CMOS
LV-CMOS
LV-CMOS
OD 3.3V
SSTL-2
SSTL-2
SSTL-2
OD 2.5V
Rs
10
0
0
R tt
33
33
47
6,19
D
CKE[0..3]
CKE[0..3]
DDR_VTT
A
6,19
/RSRAS-
6,19
/RSCAS-
6,19
/RSWE-
R176
R159
R157
33
33
33
R0402
R0402
R0402
/RSRAS-
R183
33
R0402
/RSCAS-
R186
33
R0402
/RSWE-
R188
33
R0402
*
BC262
0.1uF
C0603
25V, X7R, +/-10%
BC217
0.1uF
C0603
25V, X7R, +/-10%
*
BC116
C0402
*
BC191
0.1uF
C0603
25V, X7R, +/-10%
*
BC142
0.1uF
C0603
25V, X7R, +/-10%
*
BC252
0.1uF
C0402
16V, X7R, +/-10%
*
BC250
C0402
*
RN21
33
+/-5%
8P4R0603
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
C
VDIMM
DDR_VTT
BC169
C0402
B
BC184
0.1uF
C0603
25V, X7R, +/-10%
BC168
0.1uF
C0603
25V, X7R, +/-10%
BC292
C0603
BC278
0.1uF
C0603
25V, X7R, +/-10%
BC622
0.1uF
C0603
25V, X7R, +/-10%
BC619
0.1uF
C0603
25V, X7R, +/-10%
BC234
0.1uF
C0603
25V, X7R, +/-10%
RN16
33
+/-5%
8P4R0603
BC329
0.1uF
C0603
25V, X7R, +/-10%
BC269
0.1uF
C0603
25V, X7R, +/-10%
BC647
0.1uF
C0603
25V, X7R, +/-10%
BC315
0.1uF
C0603
25V, X7R, +/-10%
5
7
RN13
33
+/-5%
8P4R0603
BC645
0.1uF
C0603
25V, X7R, +/-10%
BC170
0.1uF
C0603
25V, X7R, +/-10%
BC249
0.1uF
C0603
25V, X7R, +/-10%
BC181
0.1uF
C0603
25V, X7R, +/-10%
1
3
5
7
RN10
33
+/-5%
8P4R0603
DDR_VTT
/RMA12
/RMA13
/RMA14
BC207
0.1uF
C0402
16V, X7R, +/-10%
*
5
7
RN20
33
+/-5%
8P4R0603
DDR_VTT
R0402
R0402
R0402
R0402
BC242
0.1uF
C0603
25V, X7R, +/-10%
*
5
7
RN17
33
+/-5%
8P4R0603
RN9
33
+/-5%
8P4R0603
33
33
33
33
BC240
0.1uF
C0603
25V, X7R, +/-10%
*
* 13
R161
R162
R181
R184
BC281
0.1uF
C0603
25V, X7R, +/-10%
*
2
4
6
8
/RMA8
/RMA9
/RMA10
/RMA11
BC308
0.1uF
C0603
25V, X7R, +/-10%
*
/RMD61
/RDQM7
/RMD62
/RMD63
5
7
RN19
33
+/-5%
8P4R0603
0.1uF
16V, X7R, +/-10%
*
RN8
33
+/-5%
8P4R0603
5
7
0.1uF
16V, X7R, +/-10%
*
* 13
R0402
R0402
R0402
R0402
BC325
C0402
0.1uF
16V, X7R, +/-10%
*
2
4
6
8
33
33
33
33
BC327
0.1uF
C0402
16V, X7R, +/-10%
*
/RMD59
/RMD58
/RDQS7
/RMD57
R167
R168
R170
R160
BC634
0.1uF
C0603
25V, X7R, +/-10%
*
RN6
33
+/-5%
8P4R0603
/RMA4
/RMA5
/RMA6
/RMA7
BC330
C0402
*
* 13
R0402
R0402
R0402
R0402
BC326
0.1uF
C0603
25V, X7R, +/-10%
*
2
4
6
8
33
33
33
33
BC617
0.1uF
C0603
25V, X7R, +/-10%
*
/RMD56
/RMD51
/RMD50
/RDQS6
R173
R174
R172
R171
BC321
0.1uF
C0603
25V, X7R, +/-10%
*
* 13
/RMA0
/RMA1
/RMA2
/RMA3
BC280
0.1uF
C0402
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10%
*
5
7
BC279
C0402
/RMD47
/RMD46
/RMD53
/RMD52
2
4
6
8
* 13
/RDQS5
/RMD41
/RMD40
/RMD35
2
4
6
8
* 13
/RCS-3
/RCS-2
/RCS-1
/RCS-0
2
4
6
8
*
5
7
0.1uF
25V, X7R, +/-10%
BC208
C0402
BC180
0.1uF
C0603
25V, X7R, +/-10%
*
* 13
BC299
0.1uF
C0402
16V, X7R, +/-10%
BC246
C0402
*
2
4
6
8
BC245
C0402
BC115
C0402
*
/RMD29
/RDQM3
/RMD30
/RMD31
BC247
0.1uF
C0402
16V, X7R, +/-10%
BC301
C0402
*
B
5
7
BC314
0.1uF
C0603
25V, X7R, +/-10%
25V, X7R, +/-10%
*
* 13
5
7
0.1uF
*
2
4
6
8
2
4
6
8
R0402
R0402
R0402
R0402
BC119
C0603
*
/RMD27
/RMD26
/RMD25
/RDQS3
33
33
33
33
/RDQM6
/RMD54
/RMD55
/RMD60
RN7
33
+/-5%
8P4R0603
BC241
0.1uF
C0603
25V, X7R, +/-10%
*
* 13
5
7
R995 R996 R997 R998
R999 R1000 R1001 R1002
update sch following layout
07/19/04
BC270
0.1uF
C0603
25V, X7R, +/-10%
*
2
4
6
8
* 13
RN15
33
+/-5%
8P4R0603
*
/RMD24
/RMD19
/RMD18
/RDQS2
R0402
R0402
R0402
R0402
5
7
*
R126
R128
R111
R108
* 13
DECOUPLING CAPACITOR FOR SSTL-2 END TERMIANTION VTT
0603 Package placed within 200mils of VTT Termination R-packs
ISLAND
*
/RMD20
/RMD21
/RMD15
/RMD14
2
4
6
8
DDR_VTT
*
2
4
6
8
/RMD49
/RMD48
/RMD42
/RMD43
RN14
33
+/-5%
8P4R0603
*
/RDQM2
/RMD23
/RMD22
/RMD28
33
33
33
33
RN3
33
+/-5%
8P4R0603
5
7
*
R127
R125
R112
R109
* 13
*
/RMD17
/RMD16
/RMD11
/RMD10
5
7
2
4
6
8
*
* 13
/RMD39
/RMD44
/RMD45
/RDQM5
RN11
33
+/-5%
8P4R0603
*
2
4
6
8
RN4
33
+/-5%
8P4R0603
5
7
*
/RMD7
/RMD13
/RMD12
/RDQM1
* 13
*
C
5
7
2
4
6
8
5
7
*
* 13
/RMD34
/RDQS4
/RMD33
/RMD32
DIMM DECOUPLING
VDIMM
*
2
4
6
8
RN2
33
+/-5%
8P4R0603
RN12
33
+/-5%
8P4R0603
*
/RDQS1
/RMD9
/RMD8
/RMD3
5
7
* 13
*
* 13
2
4
6
8
*
2
4
6
8
5
7
/RMD36
/RMD37
/RDQM4
/RMD38
*
/RMD2
/RDQS0
/RMD1
/RMD0
RN1
33
+/-5%
8P4R0603
*
* 13
*
2
4
6
8
/RMD4
/RMD5
/RDQM0
/RMD6
BC167
C0402
A
TECHNOLOGY COPR.
Title
Document Number
Rev
661S03
Date:
Friday, August 13, 2004
A
Sheet
20
of
50
5
4
3
2
1
D
D
LCDVCC
40 302LV_DDC1DAT
40 302_TXLOUT0+
40 302_TXLOUT1-
R530
R185
R189
0 R0402 +/-5% DDCDAT
0 R0402 +/-5% TXLOUT0+
0 R0402 +/-5% TXLOUT1-
40 302_TXLOUT2+
40 302_TXLCLKOUT-
R195
R201
0 R0402 +/-5%TXLOUT2+
0 R0402 +/-5%TXLCLKOUT-
41 M10_TXLCLKOUT41 M10_TXLOUT2+
41 M10_TXLOUT141 M10_TXLOUT0+
41,46 M10_DDCDAT
R689
R677
R673
R659
R529
0
0
0
0
0
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
@M10
@M10
@M10
@M10
@M10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
35
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
36
33
R0402
R0402
R0402
R0402
R0402
CN3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
35
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
36
BLON
LCDVCC
DDCCLK
TXLOUT0TXLOUT1+
TXLOUT2TXLCLKOUT+
@M10
@M10
@M10
@M10
@M10
34
PWM-ADJ
VIN1
PWM-ADJ
34
2
C0805
0.1uF
BC582
33
*
1
VIN
15
*
FB L0805 300 Ohm C0805
1uF
FB34
BC583
*
C0805
0.1uF
BC580
R533
R182
0 R0402 +/-5%
0 R0402 +/-5%
R190
R191
0 R0402 +/-5%
0 R0402 +/-5%
R202
0 R0402 +/-5%
R692
R682
R669
R663
R528
0
0
0
0
0
R0402
R0402
R0402
R0402
R0402
302LV_DDC1CLK 40
302_TXLOUT0- 40
302_TXLOUT1+ 40
302_TXLOUT2- 40
302_TXLCLKOUT+ 40
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
M10_TXLCLKOUT+ 41
M10_TXLOUT2- 41
M10_TXLOUT1+ 41
M10_TXLOUT0- 41
M10_DDCCLK 41,46
C
C
LCD CONN
+3V
+3V
R535
100K
+/-5%
R0402
3
R519
10K
+/-5%
R0402
B
Q43
RHU002N06
FB33
FB L0805 300 Ohm
1
2
4
R515
47
+/-5%
R0402
*
BC562
1nF
C0805
50V, NPO, +/-5%
1
3
2
6
5
2
1
3
+5V
BC563
0.1uF
C0402
*
BC560
0.1uF
C0402
*
BC554
10uF
C0805
D24
41
2
VGA_BLON
@M10
1
2
D23
1
RB751V-40
R537
L IDJ
2
RB751V-40
18
MXLIDJ
1K
R0402
+/-1%
LIDJ
*
B
MXLIDJ
15
3
BC570
0.1uF
10V, X7R, +/-10%
C0402
Q49
DTC144EUA
1
Q41
DTC144EUA
@M10
R536
10K
+/-5%
R0402
BLON
1
DISP_ON
*
R538
10K
+/-5%
R0402
LCDVCC
Q42
RHU002N06
2
41
+3VALW
LCDVCC
Q46
Si3456BDV
3
MOSVCC_RUN
40
FPBACKJ
2
1
PWM-ADJ
BLON
3
*
40
VGA_GPIO16
*
Q47
DTC144EUA
2
A
1
A
BC576
0.1uF
BC574
10V, X7R, +/-10%
0.1uF
10V, X7R, +/-10% C0402
C0402
TECHNOLOGY COPR.
Title
LCD CONN
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
21
of
50
5
4
3
AD[0..31]
+3V
+3V
RF_LEDJ
9,23
INT-D
13
2
D14
R787 R0402
RF_ENABLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
1
RB751V-40
0 +/-5%
Dummy
MINIPCICLK
MINIPCICLK
9
REQ1J
AD31
AD29
AD27
AD25
9,23,29
C/BE3J
AD23
AD21
AD19
AD17
9,23,29
9,23,29
C
C/BE2J
IRDYJ
IRD YJ
10,15,29 CLKRUNJ
9,23,29 SERRJ
23,29
9,23,29
PERRJ
C/BE1J
AD14
AD12
AD10
AD8
AD7
MINIPCICLK
AD5
AD3
R781
10
+/-5%
R0402
Dummy
*
+5V
AD1
BC762
5.6pF
50V, NPO, +/-0.5pF
C0603
B
+5V
*
9,23,29
BC675
10pF
50V, NPO, +/-5%
C0603
TIP
RING
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
LAN
INT#B
5V
3.3V
INT#A
RESERVED
RESV.
GND
3.3VAUX
CLK
RST#
GND
3.3V
REQ#
GNT#
3.3V
GND
AD31
PME#
AD29
RESV.
GND
AD30
AD27
3.3V
AD25
AD28
RESV.
AD26
C/BE#3
AD24
AD23
IDSEL
GND
GND
AD21
AD22
AD19
AD20
GND
PAR
AD17
AD18
C/BE#2
AD16
IRDY#
GND
3.3V
FRAME#
CLKRUN#
TRDY#
SERR#
STOP#
GND
3.3V
PERR#
DEVSEL#
C/BE#1
GND
AD14
AD15
GND
AD13
AD12
AD11
AD10
GND
GND
AD9
AD8
C/BE#0
AD7
3.3V
3.3V
AD6
AD5
AD4
RESV.
AD2
AD3
AD0
5V
RESV.
AD1
RESV.
GND
GND
AC_SYNC
M66EN
AC_DI1
AC_DO
AC_BIT_CLK
AC_ID0#
AC_ID1#
AC_RST#
MOD_A_MON
RESV.
AGND
GND
SYS_A_OUT
SYS_A_IN
AGND
AGND
AGND
AGND
NC
MCPIACT#
VCC5A
3.3VAUX
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
+3V
+5V
D
R248 R0402
R249 R0402
0 +/-5%
0 +/-5%
Dummy
+3VSUS
PMEJ
INT-A
INT-C
PCIRSTJ
9,15,17,23,29,40,41
GNT1J
9
PMEJ
7,9,23,40
9,23,29
10,23
AD30
AD28
AD26
AD24
100 AD20
+/-1%
R752
R0603
AD22
AD20
AD18
AD16
PAR
9,23,29
FRAMEJ
TRDYJ
STOPJ
9,23,29
9,23,29
9,23,29
DEVSELJ
9,23,29
+5V
C
MDC1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
AD15
AD13
AD11
AD9
C/BE0J
9,23,29
AD6
AD4
AD2
AD0
3VAUX
+3V
10,11,27 AC_SDOUT
10,27 AC_RESETJ
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
H1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
H2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
MONO_PHONE 27
R871
R0402
10K
+/-5%
R882
0 +/-5%R0402
R887
0 +/-5%R0402
3VAUX
AC_BITCLK
0.8P BTB_SMT 30P
AC_SYNC
10,27
AC_SDIN1
10
AC_BITCLK
10,27
R875
10K
R0402
+/-5%
G
18
1
MINIPCI_CONN1
R797
10K
R0402
+/-5%
Dummy
D
15
AD[0..31]
2
+3VSUS
B
15,33,34,36,38 MAINON
S
D
MDC_RINGJ
15
PCI_SLOT
Q30
2N7002
IDSEL=AD20
IRQ C,D
REQ1/GNT1
AC_BITCLK
R288
33
+/-5%
R0402
Dummy
*
BC404
10pF
50V, NPO, +/-5%
C0603
Dummy
+3V
+3VSUS
+5V
A
A
*
BC263
0.1uF
16V, X7R, +/-10%
C0402
*
BC763
BC264
0.1uF
2.2uF
C0805
16V, X7R, +/-10%
C0402
16V, Y5V, +80%/-20%
*
*
BC765
0.1uF
16V, X7R, +/-10%
C0402
*
BC661
0.1uF
16V, X7R, +/-10%
C0402
*
BC256
2.2uF
16V, Y5V, +80%/-20%
C0805
*
BC687
0.1uF
16V, X7R, +/-10%
C0402
*
BC761
0.1uF
16V, X7R, +/-10%
C0402
*
BC755
0.1uF
16V, X7R, +/-10%
C0402
*
BC757
0.1uF
16V, X7R, +/-10%
C0402
*
BC294
10uF
10V, Y5V, +80%/-20%
C0805
TECHNOLOGY COPR.
Title
Mini PCI/MDC
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
22
of
50
5
4
3
2
1
CLOSE TO CB810
FW-CLK
AD25
SDCLK1
R46
R0402
0
+/-5%
SUSPEND#
L0805 4.7uH
*
BC57
0.1uF
16V, X7R, +/-10%
C0402
+3V
+3V
1
2
3
4
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
*
FW-ROMCLK
FW-ROMAD
BC43
0.1uF
16V, X7R, +/-10%
C0402
43K
SMDATA7/SDDAT0
+/-1%
R20
R0603
43K
SMDATA4/SDDAT3
+/-1%
R10
R0603
43K
SMDATA0/SDDAT1
+/-1%
R19
R0603
SMALE/SDCMD
43K
+/-1%
R18
R0603
SMCLE/SDDAT2
43K
+/-1%
R13
R0402
10K
SMWE#/SDCLK
+/-1%
10K
SMRE#/MSCLK
+/-1%
BC62
10pF
50V, NPO, +/-5%
C0402
MSPWREN#
M11 MSPWREN#
L11
K12
J12
H12
K11
L12
L10
24
24
24
24
24
24
24
24
R26
43K
+/-5%
R0603
D
SDPWREN33#
SMDATA1/MSBS 25
SMDATA2/MSDATA0 25
SMRE#/MSCLK 25
MSINS#
1394
IDSEL AD23
REQ3/GNT3
25
U4
A_CAD[31..0]
B13
A13
CCBE0#/CE1#
CCBE1#/A8
CCBE2#/A12
CCBE3#/REG#
CPAR/A13
L16
H14
D14
E10
G16
CB810
A_CAD[31..0]
BC47
C0402
12pF
50V, NPO, +/-5%
X1
XTAL-24.576MHz
R30
R0402
10
BC48
+/-5% C0402
12pF
50V, NPO, +/-5%
A_CCBE0#
A_CCBE1#
A_CCBE2#
A_CCBE3#
A_CPAR
24
24
24
24
24
B
Cardbus
IDSEL AD25
REQ2/GNT2
VCC_SD VCC_SD
R24
10K
+/-5%
R0402
SMBSY#
SMCE#
SMWP# R40
SMCD# R25
R23
2.2K
+/-5%
R0402
2.2K
2.2K
R0402
R0402 VCC_SD
A
TECHNOLOGY COPR.
Title
Document Number
R ev
661S03
Date:
5
4
3
2
24
C
*
FW-XI
FW-XO
A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
*
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
E5
F6
E6
D6
F7
D9
G10
F10
D11
G11
D12
F12
D13
E13
G13
H15
J13
H16
J16
J14
K13
K14
K15
L15
L13
M14
M15
N16
M13
N13
N15
P16
2
SMPWREN#/MSPWREN#
SMDATA1/MSBS
SMDATA2/MSDATA0
SMDATA3/MSDATA3
SMRE#/MSCLK
SMDATA5/MSDATA2
SMDATA6/MSDATA1
MSINS#
A_CPERR#
A_CSERR#
A_CREQ#
A_CGNT#
A_CBLOCK#
A_CINT#
A_CSTSCHG
A_CAUDIO
+3V
24
24
A_CCLK
24
A_CRST#
24
A_CCLKRUN# 24
A_CFRAME# 24
A_CIRDY#
24
A_CTRDY#
24
A_CDEVSEL# 24
A_CSTOP#
24
AT24C08AN-10SU
R21
R0402
24
24
L9
M8
M9
M10
J8
H8
H9
J9
K9
J10
J11
H11
K10
SMBSY#
SMCE#
SMWP#
SMCD#
SMCLE/SDDAT2
SMALE/SDCMD
SMDATA7/SDDAT0
SMWE#/SDCLK
SMDATA4/SDDAT3
SMDATA0/SDDAT1
SMWPD#/SDWP
SDCD#
SDPWREN33#
CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1
CVS2/VS2
P15
D7
F9
G12
D5
M16
H13
RSVD/D2
RSVD/D14
RSVD/A18
CSTOP#/A20
CDEVSEL#/A21
CTRDY#/A22
CIRDY#/A15
CFRAME#/A23
CCLKRUN#/WP/IOIS16#
CRST#/RESET
CCLK/A16
F15
E16
D16
D15
E14
G8
E12
E15
CGNT#/WE#
CREQ#/INPACK#
CSERR#/WAIT#
CPERR#/A14
F14
E11
D8
F16
CAUDIO/BVD2/SPKR#
CSTSCHG/BVD1/STSCHG#
CINT#/READY/IREQ#
CBLOCK#/A19
E8
F8
G9
G14
VCC_SD
R11
R0603
*
24
24
24
SDPWREN33# 25
SDCD#
25
SMWPD#/SDWP 25
SMDATA0/SDDAT1 25
SMDATA4/SDDAT3 25
SMWE#/SDCLK 25
SMDATA7/SDDAT0 25
SMALE/SDCMD 25
SMCLE/SDDAT2 25
SMBSY#
SMCE#
SMWP#
SMCD#
AVCC
FW-TPBIAS0
FW-TPBIAS1
FW-TPA0P
FW-TPA0M
FW-TPB0P
FW-TPB0M
FW-TPA1M
FW-TPA1P
FW-TPB1M
FW-TPB1P
VCCD1#
VCCD0#
VPPD1
VPPD0
F19
H18
F18
G19
G18
H19
J18
J19
K18
K19
R16
T16
R15
T15
P18
P19
N18
N19
M19
FW-TPB2P
FW-TPB2M
FW-TPA2P
FW-TPA2M
FW-TPBIAS2
VCCA1
VCCA2
VCC_SD
GND_SD
FW-VAUXPRSNT
FW-CARDBUS#
FW-MPCIACT#
A10
A8
V14
FW-PLLVDD
FW-VDDA1
FW-VDDA2
FW-VDDA3
B14
R19
L19
E19
VCC3A
K16
D10
H10
K8
SDCLK1
A5
B6
B5
A6
B7
A7
W13
V12
W12
V11
W14
V13
V15
B11
A11
A12
B15
A15
R31
2.49K
+/-1%
R0402
VCC_SD
R28
510K
+/-5%
R0603
U3
L6
R42
402K
+/-1%
R0603
Dummy
FW-RESETN
R0603 IDSEL_CARDBUS
+/-5%
*
A
100
R36
R0603 IDSEL_1394
+/-5%
R41
10K
+/-5%
R0402
24
24
24
24
A_D2
A_D14
A_A18
A_CCD1#
A_CCD2#
A_CVS1
A_CVS2
FW-TPBIAS0
FW-ROMAD
FW-ROMCLK
FW-TEST0
FW-TEST1
FW-NANDTREE
FW-CNA
FW-PC0
FW-PC1
FW-PC2
FW-CONTENDER
FW-LPS
FW-LKON
FW-CPS
FW-SM
FW-SE
FW-PTEST
FW-R0
FW-R1
R14
T14
P13
T13
N12
T12
N11
M12
L8
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
MFUNC7
SDCLKI
SUSPEND#
SPKROUT
RI_OUT#/PME#
FW-PME#
FW-RESETN
SUSPEND#
P14
R12
P11
H2
R13
B12
G_RST#
FW-RESET#
+3V
AD23 100
R38
S4,10V
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
FW-VDD1
FW-VDD2
FW-VDD3
FW-VDD4
FW-VDD5
FW-VDD6
FW-VDD7
FW-VDD8
FW-VDD9
FW-VDD10
FW-VDD11
CBE0#
CBE1#
CBE2#
CBE3#
PAR
R32
10K
+/-5%
R0402
J6
K4
N5
T7
P9
P12
L14
G15
F11
E7
A9
E1
J1
L1
M1
N1
P1
R1
W7
W9
W15
T8
T4
M6
H4
R5
FW-PLLVSS
FW-VSSA1
FW-VSSA2
FW-VSSA3
FW-VSSA4
FW-CLKRUN#
G6
L5
P7
R11
N14
J15
F13
E9
B9
E2
K2
L2
M2
N2
P2
R2
V5
V6
V7
V8
V9
V10
C/BE0J
C/BE1J
C/BE2J
C/BE3J
PAR
F1
R33
10K
+/-5%
R0402
A14
R18
M18
L18
E18
9,22,29
9,22,29
9,22,29
9,22,29
9,22,29
B
10K
+/-5%
FW-CLK
K1
L4
K7
G1
W11
IDSEL_1394
J2
IDSEL_CARDBUS
J7
E4
GNT3J
G2
D4
REQ3J
H1
F2
R4
P6
P5
P4
N6
N4
M7
R35
R0402
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
FW-VSS1
FW-VSS2
FW-VSS3
FW-VSS4
FW-VSS5
FW-VSS6
FW-VSS7
FW-VSS8
FW-VSS9
FW-VSS10
FW-VSS11
FW-VSS12
FW-VSS13
FW-VSS14
C
T11
N10
P10
T10
R10
T9
R9
N9
R8
P8
N8
R7
N7
T6
R6
T5
M5
M4
L7
L6
K6
K5
J4
J5
H5
H6
H7
G4
G5
G7
F4
F5
FW-INTA#
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
AD[0..31]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
R37
0
+/-5%
R0402
VCCD1#
VCCD0#
VPPD1
VPPD0
FW-TPB0M
FW-TPB0P
FW-TPA0M
FW-TPA0P
26
MOSVCC
FW-ROMCLK
FW-ROMAD
22,29 AD[0..31]
26
26
26
26
+3V
10,22 PMEJ
27 SPEAKOUT
9,15,17,22,29,40,41 PCIRSTJ
9 REQ3J
9 REQ2J
9 GNT3J
9 GNT2J
+3V
9,15,17,22,29,40,41 PCIRSTJ
13 CARDBUDCLK
9,22,29 FRAMEJ
9,22,29 IRDYJ
9,22,29 TRDYJ
9,22,29 DEVSELJ
9,22,29 STOPJ
22,29 PERRJ
9,22,29 SERRJ
7,9,22,40 INT-A
D
22
+/-5%
INT-D
SERIRQ
FW-PCICLK
PCICLK
PCIRST#
FW-PCIRST#
FW-PCIVIOS
FW-IDSEL
IDSEL
PCIGNT#
FW-PCIGNT#
PCIREQ#
FW-PCIREQ#
9,22
10,15
GRST# should
connect to Power
On reset if
support S3
FW-CLK R39
R0402
INT-C
1
13 PCLK_1394
9,22,29
Friday, August 13, 2004
A
Sheet
1
23
of
50
5
4
3
2
AVCC
AVPP
AVCC
U2
9
1
VCC
VCC
VCC
13
12
11
VPP
10
VCCD0
VCCD1
VPPD0
VPPD1
1
2
15
14
12V
BC39
0.1uF
16V, X7R, +/-10%
C0402
*
BC34
0.1uF
16V, X7R, +/-10%
C0402
*
AVPP
+5V
D
D
5
6
5V
5V
+5V
7
23
23
23
23
BC35
0.1uF
16V, X7R, +/-10%
C0402
8
OC
SHDN
3.3V
3.3V
16
3
4
GND
+3V
VCCD0#
VCCD1#
VPPD0
VPPD1
+3V
*
*
BC37
4.7uF
16V, Y5V, +80%/-20%
C1206
BC54
0.1uF
16V, X7R, +/-10%
C0402
*
*
BC44
4.7uF
16V, Y5V, +80%/-20%
C1206
TPS2211
+3V
AVCC
AVPP
C
A_CAD[31..0]
CLOSE TO SOCKET
A_CAD[31..0]
CN11
A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
B
Reserved layout for
debug used
dummy
AVCC
AVCC
R62
R63
47K
47K
dummy
R0402
R0402
66
65
31
64
30
29
28
27
26
25
24
23
56
22
55
46
45
11
44
10
9
42
8
41
6
39
5
38
4
37
3
2
68
35
34
1
(D10) CAD31
VCC
(D9) CAD30
VCC
(D1) CAD29
(D8) CAD28
VPP
(D0) CAD27
VPP
(A0) CAD26
(A1) CAD25
CCLK (A16)
(A2) CAD24
CFRAME# (A23)
(A3) CAD23
CIRDY# (A15)
(A4) CAD22
CTRDY# (A22)
(A5) CAD21
CDEVSEL# (A21)
(A6) CAD20
CSTOP# (A20)
(A25) CAD19
CPAR (A13)
(A7) CAD18
CPERR# (A14)
(A24) CAD17
CSERR# (WAIT*)
(A17) CAD16
CREQ# (INPACK*)
IOWR*) CAD15
CGNT# (WE*)
(A9) CAD14
CINT# (IRQ*)
(IORD*) CAD13
CBLOCK# (A19)
(A11) CAD12
CCLKRUN# (IO16*)
(OE*) CAD11
CRESET# (RESET)
(CE2*) CAD10
RFU (R2_D2)
(A10) CAD9
RFU (R2_D14)
(D15) CAD8
RFU (R2_A18)
(D7) CAD7
CVS1
(D13) CAD6
CVS2
(D6) CAD5
CCD1# (CD1*)
(D12) CAD4
CCD2# (CD2*)
(D5) CAD3
CAUDIO (BVD2/SPKR*)
(D11) CAD2
CSTSCHG (BVD1/
(D4) CAD1
(D3) CAD0
CC/BE3# (REG*)
CC/BE2# (A12)
GND
CC/BE1# (A8)
GND
CC/BE0# (CE1*)
GND
GND
51
17
52
18
19
54
20
53
50
49
13
14
59
60
15
16
48
33
58
32
40
47
43
57
36
67
62
63
A_CFRAME#
A_CIRDY#
A_CTRDY#
A_CDEVSEL#
A_CSTOP#
A_CPAR
A_CPERR#
A_CSERR#
A_CREQ#
A_CGNT#
A_CINT#
A_CBLOCK#
A_CCLKRUN#
A_CRST#
A_D2
A_D14
A_A18
A_CVS1
A_CVS2
A_CCD1#
A_CCD2#
A_CAUDIO
A_CSTSCHG
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
61
21
12
7
A_CCBE3#
A_CCBE2#
A_CCBE1#
A_CCBE0#
23
23
23
23
CARDBUS CONN
dummy
R64
47K
+/-5%
R0402
AVCC
R60
R0402
0
+/-5%
R34
10
R0402
BC98
C0402
*
23
C
10pF
50V, NPO, +/-5%
A_CCLK
23
A_CCD1#
A_CCD2#
*
BC53
10pF
50V, NPO, +/-5%
C0402
*
BC73
10pF
50V, NPO, +/-5%
C0402
B
Close to CB810 CD1# and CD2# pin
R72
47K
dummy
+/-5%
R0402
AVCC
Reserved layout for
debug used
A
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
24
of
50
5
4
3
2
1
D
D
CN2
GND
GND
COM
CD#
26
WP
23
10
GND
SMWPD#/SDWP
23 SMWPD#/SDWP
25
SMDATA7/SDDAT0
SMDATA0/SDDAT1
SMCLE/SDDAT2
SD_CD/DAT3 MS_VSS
SD_CMD
MS_BS
SD_VSS1
MS_VCC
SD_VDD
MS_SDIO
SDCLK
RESERVED
SD_VSS2
MS_INS
SD_DAT0 RESERVED
SD_DAT1
MS_SCLK
SD_DAT2
MS_VCC
MS_VSS
GND
SD_VDD
R12 22
23 SMWE#/SDCLK
23 SMDATA7/SDDAT0
23 SMDATA0/SDDAT1
23 SMCLE/SDDAT2
1
2
3
4
5
6
7
8
9
24
SMDATA4/SDDAT3
SMALE/SDCMD
11
12
13
14
15
16
17
18
19
20
SMDATA1/MSBS
SMDATA1/MSBS 23
MS_VCC
SMDATA2/MSDATA0
SMDATA2/MSDATA0 23
R22
3VAUX
22K
R0402
MSINS# 23
MSINS#
23 SMDATA4/SDDAT3
23 SMALE/SDCMD
SMRE#/MSCLK
MS_VCC
22
21
SDCD#
SMRE#/MSCLK 23
SDCD# 23
3 IN 1 CARD READER
VCC_SD
1uF
1uF
VCC_SD
D
*
0
+/-5%
B
*
C
SD_VDD
MS_VCC
G
S
R27
43K
+/-5%
R0603
R29
R0402
BC30
BC31
Q5
NDS356AP
+3V
23 SDPWREN33#
**
C
BC36
0.1uF
16V, X7R, +/-10%
C0402
B
BC45
0.1uF
16V, X7R, +/-10%
C0402
A
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
25
of
50
5
4
*
D
BC3
220pF
50V, NPO, +/-5%
C0603
R4
56.2
+/-1%
R0603
R3
56.2
+/-1%
R0603
3
2
1
R2
4.99K
+/-1%
R0603
D
TF1
23 FW-TPA0M
2
1
23 FW-TPA0P
3
4
TPA0M
TPA0P
CN6
Common Choke 90 Ohm 2L
23 FW-TPB0M
2
23 FW-TPB0P
3
1
2
3
4
1 GND
2
3
4 GND
5
6
1394 CONN
Common Choke 90 Ohm 2L
TPB0M
1
TPB0P
4
TF2
R6
56.2
+/-1%
R0603
R5
56.2
+/-1%
BC4
0.33uF
R0603
10V, X5R, +/-10%
C
*
C
23 FW-TPBIAS0
C0603
VCC3A
*
TC1
10uF
12.5V, +/-20%
CTB
*
BC46
0.1uF
25V, X7R, +/-10%
C0603
*
BC69
10nF
25V, X7R, +/-10%
C0603
*
BC58
0.1uF
25V, X7R, +/-10%
C0603
BC64
10nF
25V, X7R, +/-10%
C0603
*
+3V
*
B
BC56
0.1uF
25V, X7R, +/-10%
C0603
*
BC71
0.1uF
25V, X7R, +/-10%
C0603
*
BC80
0.1uF
25V, X7R, +/-10%
C0603
*
BC76
0.1uF
25V, X7R, +/-10%
C0603
*
BC68
0.1uF
25V, X7R, +/-10%
C0603
*
BC61
0.1uF
25V, X7R, +/-10%
C0603
B
+3V
*
+3V
BC65
0.1uF
25V, X7R, +/-10%
C0603
*
BC77
0.1uF
25V, X7R, +/-10%
C0603
*
BC67
0.1uF
25V, X7R, +/-10%
C0603
*
BC66
0.1uF
25V, X7R, +/-10%
C0603
*
BC82
10uF
10V, Y5V, +80%/-20%
C0805
*
BC70
10nF
25V, X7R, +/-10%
C0603
*
BC81
10uF
10V, Y5V, +80%/-20%
C0805
*
BC63
10nF
25V, X7R, +/-10%
C0603
*
BC79
0.1uF
25V, X7R, +/-10%
C0603
*
BC78
0.1uF
25V, X7R, +/-10%
C0603
*
BC60
10nF
25V, X7R, +/-10%
C0603
A
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
26
of
50
4
3
2
1
CD_LINL
CD_LINR
+3VM3E
R846
10K
+/-5%
R0603
Dummy
R858
0
Dummy
R0603
+/-5%
+3VM3E
22
1
9
25
38
BC804
22pF
50V, NPO, +/-5%
C0402
U46
11
6
10
8
5
R0402
R927
10+/-5% R0402
EC16
150uF CTX 4V, +/-20%
R886 2.7K R0402
R891
2.7K
R0402
Dummy
HPSPKR+_CON
R896
4.7K
R0402
RCDL
17
RCDR
17
CDGND
17
R874
4.7K
R0402
AUDGND
+5VA
BC820
10uF
16V, X5R, +/-10%
C1206
*
BC844
0.1uF
C0402
XTL_OUT
XTL_IN
RESET#
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
*
LINE_OUT_L
LINE_OUT_R
MONO_OUT
NC1
NC2
HP_OUT_L
HP_COMM
HP_OUT_R
GPIO0
GPIO1
CID0
CID1
35
36
37
33
34
39
40
41
43
44
45
46
VREFOUT
VREF
AFILT1
AFILT2
NC/CAP1
CAP2
28
27
29
30
31
32
HPSPKL+
HPSPKR+
HPSPKL+
HPSPKR+
3
SHDN
5
BYPASS/ADJ
4
*
*
FB60
1
+3V
18
18
BC788
10uF
C0805
BC835
0.1uF
*
C0402
AUDGND
BC839
0.1uF
*
C0402
FB L0603 600 Ohm
2
*
*
BC841
10nF
C0402
BC837
0.1uF
16V, X7R, +/-10%
C0402
AUDGND
+3VM3E
BC806
1uF
C0603
*
BC805
0.1uF
C0402
AOUTL
C
AOUTR
+5VA
R879
R878
0 +/-5% R0402 Dummy
0 +/-5% R0402 Dummy
BC500
10uF
C0805
*
VREFOUT
*
BC494
0.1uF
C0402
18
AUDGND
*
BC852
1uF
C0603
*
BC850
1nF
C0603
*
BC849
1nF
C0603
*
BC855
10uF
C1206
AUDGND
FB59
FB L0603 600 Ohm
1
2
+5V
BC786
0.1uF
16V, X7R, +/-10%
C0402
*
16V, Y5V, +80%/-20%
50V, X7R, +/-10%
AUDGND
*
50V, X7R, +/-10%
ALC202A
BC851
1uF
C0603
10V, X5R, +/-10%
BC793
22pF
50V, NPO, +/-5%
C0402
BC836
0.1uF
C0402
AC97 CODEC
LQFP-48P
PC_BEEP
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
EAPD
SPDIF
10K
R0402
VOUT
AUDGND
+5VA
AUDGND
4
7
26
42
10V, X5R, +/-10% 12
10V, X5R, +/-10% 13
14
15
16
17
CD_LINL
18
CD_GND
19
CD_LINR
20
10V, X5R, +/-10% 21
22
23
24
47
48
*
R923
+/-5%
BC848
0.1uF
C0402
VIN
GND
*
D
MIC5205-5.0BM5
1
2
BC826
0.1uF
C0603
10V, X5R, +/-10%
*
BC819 1uF C0603
AUDGND
AC_BITCLK
B
R892 4.7K R0402
AUDGND
DVss1
DVss2
AVss1
AVss2
BC828 1uF C0603
MIC1
**
BC801 1uF C0603
BC817 1uF C0603
*
28
HPSPKR+
CD_GND
HPSPKL+_CON
DVdd1
DVdd2
AVdd1
AVdd2
*
*
C
BEEP
150uF CTX 4V, +/-20%
BC823 1uF C0603
*
BC792
10uF
C0805
+5VAA
*
BC796
0.1uF
C0402
*
BC809
0.1uF
C0402
*
BC831
0.1uF
C0402
AUDGND
+5VA
NORMAL:LOW
SHORT13
1
5
BC802
0.1uF
C0603
* *
25V, X7R, +/-10%
X9
R864
23 SPEAKOUT
22 MONO_PHONE
EC15
+5VA
25V, X7R, +/-10%
BC808
10uF
16V, X5R, +/-10%
C1206
3
2
AC_RESETJ
AC_BITCLK
AC_SYNC
AC_SDIN0
AC_SDOUT
10+/-5% R0402
R880 4.7K R0402
U47
R866
10K
+/-5%
R0603
Dummy
*
10,22
10,22
10,22
10
10,11,22
R926
BC818 1uF C0603
+5V
XTAL-24.576MHz
1
2
BC803
22pF
C0402
50V, NPO, +/-5%
HPSPKL+
**
CODEC
D
***
5
B
2
1
R863
+/-5%
4
JUMPER1
2
3
AUDGND
BEEP
10K
R0603
R862
1K
+/-1%
R0402
U26
NC7SZ86
*
BC794
0.1uF
16V, X7R, +/-10%
C0402
J3
R0402 Dummy
R0402
R905
1K
+/-1%
R0402
1uF
C0603
1uF
C0603
AUDIO_G0
AUDIO_G1
R906
1K
+/-5%
R0402
Dummy
*
INSPKL+
INSPKL-
PC-BEEP
14
BC800
HP/LINE
SE/BTL
SHUTDOWN
17
15
22
RHPIN
RLINEIN
RIN+
10
6
5
LIN+
LHPIN
LLINEIN
11
2
3
BYPASS
GAIN0
GAIN1
BC834
1uF
9
4
R865
1uF
AUDGND
*
BC797
470pF
C0603
0
*
BC799
470pF
C0603
*
BC833
470pF
*
C0603
BC845
470pF
Header_1X2
J1
1
NC 3
2
NC 4
william
071304
NORMAL:LOW
Header_1X2
C0603
AUDGND
AUDGND
+3V
10,11
AUDGND
15
AUDGND
PCSPK
1
EC_BEEP
2
GND4
GND3
GND2
GND1
1
24
13
12
TPA0312
SHUNDOWNJ 18
R861
R0603
100K
+/-5%
4
U24
NC7SZ86
+5VAA
A
DTC144EUA
Q68
C0603
2
VOL_MUTE
TECHNOLOGY COPR.
15
Title
AUDGND
AUDGND
AUDGND
AUDGND
AUDIO ALC202A & AMP
1
A
R924 100K
R925 100K
BC832
1uF
LOUTLOUT+
AUDGND
NC 3
NC 4
3
BC846
20
23
8
INSPKR+
INSPKR-
*
BC847
AUDGND
1uF
21
16
3
AUDGND
AOUTL
+5VAA
BC798
****
AOUTR
ROUT+
ROUT-
PVDD1
PVDD2
VDD
AUDGND1
7
18
19
25
Amp
1
2
U45
5
+5VAA
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
27
of
50
5
4
3
2
1
+5VA
R953
100K
+/-1%
R0603
D
D
+5VA
+5VA
AUDGND
8
2
-
BC858
C0603
1
LM358MX
R417
10K
+/-5%
R0603
2.2K
+/-5%
R0603
BC857
1uF
C0603
*
INT_MIC
*
6
BC521
0.47uF
C0603
R928
-
MIC_IN
7
LM358MX
AUDGND
R432
R0603
FB61
FB L0805 80 Ohm
AUDGND
EXTMIC
EXTMICIN
C
4.7K
+/-5%
U48B
+
10K
+/-5%
1K
+/-5%
R0603
MIC1
27
*
BC854
10nF
50V, X7R, +/-10%
AUDGNDC0603
*
2
AUDGND
INT_MIC
5
R431
R0603
*
AUDGND
18
+5VA
R934
1M
+/-1%
R0603
0.22uF
AUDGND
1
R436
100K
+/-1%
R0603
R935
100K
+/-1%
R0603
R947
4
*
BC514
10uF
C0805
C0805
U48A
+
*
3
BC517
4.7uF
8
*
4
R448
100K
+/-1%
R0603
EXTMIC
EXTMICIN
BC516
1nF
50V, X7R, +/-10%
C0603
18
18
C
*
BC853
BC840
47pF
470pF
External
50V, NPO, +/-5% 50V, NPO, +/-5%
C0603
C0603
MIC
AUDGND
B
B
BC787
C0603
*
Place near the switch
connecter 2004/07/03
0.1uF 25V
R930
R0805
0 +/-5%
Dummy
R929
R0805
0 +/-5%
AUDGND
A
A
TECHNOLOGY COPR.
Title
MIC Jack & AUDIO Jack
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
28
of
50
3
L15
R151
R0603
0
+/-5%
DUMMY
*
*
C19
0.1uF
C0603
*
C22
C21
* 0.1uF
* 0.1uF
*
C0603
L14
C0603
1
30
29
61
63
68
69
67
76
70
75
25
27
28
46
65
88
REQB
GNTB
FRAMEB
IRDYB
DEVSELB
STOPB
TRDYB
PAR
PERRB
SERRB
INTAB
RSTB
CLK
IDSEL
CLKRUNB
M66EN
1.8V_LAN
3
2
2.5V_LAN
FB L0805 60 Ohm
Q57
2SA1576A
1
VDD3
12
11
CTRL25
CTRL18
8
125
RSET
127
TRDP0
TRDN0
TRDP1
TRDN1
TRDP2
TRDN2
TRDP3
TRDN3
R88
49.9
30
+/-1%
30
R0603
30
30
30
30
30
30
R87 R74
49.9
49.9
+/-1% +/-1%
R0603R0603
*
R73
R84
49.9
49.9
+/-1% +/-1%
R0603 R0603
C4
10nF
50V, X7R, +/-10%
C0603
*
C1
10nF
50V, X7R, +/-10%
C0603
R83
49.9
+/-1%
R0603
*
MDI3N
HSDACHSDAC+
MDI0P
MDI0N
MDI1P
MDI1N
MDI2P
MDI2N
MDI3P
MDI3N
MDI3P
1
2
5
6
14
15
18
19
VDD3
MDI1N
MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-
R599
0
+/-5%
R0603
MDI1P
10
120
MDI0N
AVDDH
HV
R78
49.9
+/-1%
R0603
C3
10nF
50V, X7R, +/-10%
C0603
R77
49.9
+/-1%
R0603
*
C
C2
10nF
50V, X7R, +/-10%
C0603
R0603 dummy
0
R85
+/-5%
2.5V_LAN
0
R86
+/-5% DUMMY R0603
REG25
REG18
R110
R0603
5.6K
+/-1%
R602
10K
+/-5%
DummyR0603
R604
5.6K
Dummy +/-5%
R0603
CBE0B
CBE1B
CBE2B
CBE3B
VDD3
REG25
FB L0805 60 Ohm
2
VDD3
dummy
1
Q58
2SA1576A
1
REG18
2.49K/F 8110
92
77
60
44
2.5V_LAN
2
1.8V_LAN
FB L0805 60 Ohm
AVDDL
AVDDL
AVDDL
AVDDL
3
7
16
20
*
MDI0P
AD1
AD0
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C23
10uF
16V, X5R, +/-10%
C1206
2.5V_LAN
3
D
C32
C27
10nF
10nF
L13 1
50V, X7R, +/-10%
C0603 C0603
50V, X7R, +/-10%
L12
VDD3
VDD3
U38
106
111
109
108
LWAKE
PMEB
SMBCLK
SMBDATA
LED3
LED2
LED1
LED0
105
31
72
74
113
114
115
117
ISLATB
EECS
EESK
1
2
3
4
EEDI/AUX
EEDO
CS
SK
DI
DO
VCC
NC
ORG
GND
8
7
6
5
*
C26
0.1uF
25V, X7R, +/-10%
C0603
RTL8100C
RTL8110S /
RTL8169S
AVDDH
N/A
3.3AVDD
V_12P
2.5AVDD
N/A
AVDDL
3.3AVDD
2.5AVDD
V_DAC
N/A
2.5AVDD
2.5VDD
1.8VDD
N/A
1.8VDD
AT93C46-2.7V
R154
R0603
4.7K DUMMY
VDD33
+/-5%
R155
4.7K DUMMY
R0603 +/-5%
121
122
CLK_LAN_X1
CLK_LAN_X2
23
R76
1K
R0603 +/-5%
C6
0.1uF
25V, X7R, +/-10%
C0603
*
SUSBJ
B
LAN_PME_591J 15
2
EECS
EESK
EEDI
EEDO
XTAL1
XTAL2
10,15
C7
27pF
50V, NPO, +/-5%
C0603
X2
DVDD
XTAL-25MHz
C8
C0603
27pF
50V, NPO, +/-5%
DVDD_A
Lan
IDSEL AD18
REQ0/GNT0
+3V
A
*
C11
10nF
+/-10%
C0603
*
R150
4.7K
+/-5%
R0603
*
C10
10nF
50V, X7R,
C0603
1
10,15,22 CLKRUNJ
*
C25
0.1uF
C0603
2 FB L0805 60 Ohm
129
R600
100
+/-5%
R0603
*
C20
0.1uF
C0603
FB L0805 60 Ohm
2 DUMMY
1
*
9
REQ0J
9
GNT0J
9,22,23 FRAMEJ
9,22,23 IRDYJ
9,22,23 DEVSELJ
9,22,23 STOPJ
9,22,23 TRDYJ
9,22,23 PAR
22,23 PERRJ
9,22,23 SERRJ
9,22,23 INT-C
9,15,17,22,23,40,41 PCIRSTJ
13 PCLK_LAN
AD18
*
129
B
C/BE0J
C/BE1J
C/BE2J
C/BE3J
U9
103
104
102
98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33
L7 1
C31
0.1uF
C0603
LNAGD
LNAGD
LNAGD
LNAGD
LNAGD
HG
LG2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C
9,22,23
9,22,23
9,22,23
9,22,23
C0603
*
C28
0.1uF
C0603
4
9
13
17
128
123
124
VDD3
AD[0..31]
9,22,23 AD[0..31]
C0603
*
RTL8100C
2
C0603
*
C9
10uF
16V, X5R, +/-10%
C1206
24
32
45
54
64
78
99
110
116
126
1
C0603
*
50V, X7R, +/-10%
L17
C24
10nF
50V, Y5V, +80%/-20%
FB L0805 60 Ohm
+3V
C5
10nF
VDD25/18
VDD25/18
VDD25/18
VDD25/18
VDD25/18
VDD25/18
VDD25/18
VDD25/18
VDD25/18
VDD18
* *
C12
10nF
26
41
56
71
84
94
107
*
C14
10nF
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
*
C33
0.1uF
C0603
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSSPST
VSSPST
VSSPST
VSSPST
VSSPST
VSSPST
VSSPST
VSSPST
*
C29
0.1uF
C0603
22
35
48
52
62
73
80
100
112
118
21
38
51
66
81
91
101
119
C30
10uF
C13
10V, Y5V, +80%/-20% 0.1uF
C1206
C0603
50V, X7R, +/-10%
D
50V, X7R, +/-10%
2
VDD25/18_LAN
25V, Y5V, +80%/-20%
1
MDI2N
VDD3
2
2
4
MDI2P
5
A
TECHNOLOGY COPR.
Title
RTL8100
Document Number
Re v
A
Date:
5
4
3
2
Friday, August 13, 2004
Sheet
1
29
of
50
8
7
WILLIAM
071704
3
2
1
2
3
4
5
6
7
8
1
D
TX+/0+
TX-/0RX+/1+
NC1/2+
NC2/2RX-/1NC/3+
NC4/3-
*
MX0+
MX0MX1+
MX2+
MX2MX1MX3+
MX3-
8
7
2
6
5
1
4
3
Wire To Borad_8
TIP_RJ11
RING_RJ11
1
2
9
10
GND1
11
GND2
12
*
J4
3 NC
4 NC
4
CN9
J5
9
10
5
*
D
6
TIP
RING
Header_1X2
BC540
0.1uF
C0402
16V, X7R, +/-10%
3VAUX
BC539
10nF
C0402
25V, X7R, +/-10%
*
BC623
0.1uF
16V, X7R, +/-10%
C0402
BC11
1.5nF
C1808
2kV, X7R, +/-10%
RJ45_ RJ11
*
BC6
1.5nF
2kV, X7R, +/-10%
C1808
*
BC7
1.5nF
2kV, X7R, +/-10%
C1808
C
C
+3V
R958
0
R0402
+/-5%
R0402
R956 0
XFMR 350uH @8110S
XFMR 350uH
B
*
R9
R0402
R8
R0402
BC12
1.5nF
2kV, X7R, +/-10%
C1808 @8100C
MX1MX1+
75+/-5% @8100C
75+/-5% @8100C
MX0MX0+
7
8
9
10
11
12
TXTX+
TXCT
RXCT
RXRX+
TDTD+
TDCT
RDCT
RDRD+
@8100C
L3
Dummy
Dummy
+/-5%
TRANSFORMER
6
5
4
3
2
1
MDI1MDI1+
V_DAC0
V_DAC1
MDI0MDI0+
BC9
10nF
25V, X7R, +/-10%
C0402
@8100C
TRDN1 29
TRDP1 29
TRDN029
TRDP0 29
*
R487R0402
R488R0402
R955
0
R0402
+/-5%
*
BC10
1.5nF
2kV, X7R, +/-10%
C1808
@8110S
MX2+
MX275+/-5% @8110S
75+/-5% @8110S
MX3+
MX3-
7
8
9
10
11
12
TXTX+
TXCT
RXCT
RXRX+
TDTD+
TDCT
RDCT
RDRD+
6
5
4
3
2
1
MDI2+
MDI2V_DAC2
V_DAC3
MDI3+
MDI3-
TRDP2
TRDN2
R0402
TRDP3 29
TRDN3 29
B
29
29
+/-5%
R957 0
Dummy
L10
BC538
10nF
25V, X7R, +/-10%
C0402
Dummy
* *
BC537
10nF
25V, X7R, +/-10%
C0402
Dummy
A
A
TECHNOLOGY COPR.
Title
RJ45&TRANSFORMER
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
30
of
50
5
4
3
2
1
VIN
+5V
VIN_CPU
FB3
FB L0805 300 Ohm
1
2
+/-5% R0402
MAX1987_SHDNJ
9
FLOAT (300KHZ)
14
C0603
10
R7
301K
+/-1%
R0603
B
*
BC534
100pF
C0402
11
ILIM
1
TIME
31
DD0
5
6
7
8
4
3
2
1
5
5
NEG
16
CSP
48
CSN
47
BSTS
41
DHS
39
LXS
40
DLS
38
1
4
FB
*
CCI
BC532
470pF
C0603
R477
1.5K
+/-5%
R0402 R479
2.74K
+/-1%
R0603
1
VIN_CPU
R478
100K
+/-5%
R0402
*
MAX1987_POS
BC541
1uF
*
C0805
Q36
IRF7811W
BC568
0.1uF
C0805
*
BC573
0.1uF
C0805
MAX1987_CSP
D22
BST2
2
1
0.5uH
RB751V-40
BC544
3
0.1uF C0805
1
DH_VCORE2
LX_VCORE2
Q40
PH5330E
4 G
DL_VCORE2
MAX1987
VCORE_CPU
L4
+5V
R509
2m
R2512
+/-5%
2
Q39
PH5330E
4
*
C18
330uF
CTX
*
C17
330uF
CTX
D2
B320B
G
B
Not in CIS
lonny 070704
R504
750 +-1%
R0402
+3V
R503
1K
+/-1%
R0402
It should be close
to max1987's pin
R494
10K
+/-5%
R0402
R496
10K
+/-5%
R0402
1
R501
750 +-1%
R0402
2
R502
1K
+/-1%
R0402
D
JUMPER1
Q38
2N7002
SGND6
G
A
S
D
H_DPSLP_1
Not in CIS
lonny 070704
SHORT7
H_DPSLPJ_PW
G
TECHNOLOGY COPR.
S
3,10 H_DPSLPJ
C16
330uF
CTX
MAX1987_OAIN-
SGND6
Q37
2N7002
*
C
BC530
4.7nF
C0603
R484
1M
+/-5%
R0402
C15
330uF
CTX
G
S
S
S
G
SGND6
A
*
1
2
3
18
15
PH5330E
D
D
FB
REF
Q44
S
S
S
R476 +/-5%
4.7K R0402
CCV
R491
28K
+/-1%
R0603
R485
49.9K
+/-1%
R0603
19
TON
PH5330E
1
0.22uF
C0402
MAX1987_OAIN+
OAIN-
17
VCORE_CPU
R520
2m
R2512
+/-5%
S
S
S
G
BC535
*
SGND6
270pF
*
BC531
SGND6
2
4
46
CCI
0.5uH
2
Q45
MAX1987_CMP
20
POS
D
D4
B320B
CMN
SHDN
L5
3
LX_VCORE
DH_VCORE
DL_VCORE
OAIN+
PSI
BC13
10uF
C1210
2
R489 0
21
45
0.1uF C0805
D
MAX1987_PSI
CMP
*
5
+/-5% R0402
37
13
1
BC536
RB751V-40
5
6
7
8
R475 0
DLM
PGND
GND
BC59
10uF
C1210
Q48
IRF7811W
4
3
2
1
DPSLP
33
35
*
S
S
S
SUS
44
LXM
BC542
1uF
C0805
1
2
3
VRON
43
H_DPSLPJ_PW
34
D
D
D
D
15,35
PSIJ
+/-5% R0402
SGND6
MAX1987_SUS
DHM
1987_BSTM 2
S
S
S
4
R500 0
B0
B1
B2
32
1
2
3
4,10 DPRSLPVR
3
4
5
BSTM
D
C
42
1
2
3
BOOT MODE=1.196V
S2
S1
S0
V+
D21
D0
D1
D2
D3
D4
D5
8
7
6
36
5
SUSPEND MODE=0.748V
VDD
*
30
29
28
27
26
25
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
SYSPOK
IMVP_OK
CLK_EN
THERMALPAD
4
4
4
4
4
4
VIN_CPU
SGND6
U32
MAX1987_VCC 12
VCC
22
23
1987_CKENJ 24
*
S
S
S
G
35 VCCP_HWPG
7,10,15 PWRGD
BC533
1uF
C0603
49
R483
0
2
FB4
FB L0805 300 Ohm
D
D
D
D
R482
R481
R480
100K
100K
100K
+/-5%
+/-5%
+/-5%
R0402 R0402 R0402
+/-5%
R0402
1
*
*
BC543
2.2uF
C0603
*
D
*
2
R490
10
+/-5%
R0402
+3V
Title
CPU POWER
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
31
of
50
8
7
RTC
6
5
4
3
2
1
NOTE!
1.The VCCRTC is 3V
2.Decoupling capacitor must be close to 652 RTCVDD pin.
3.RTC circuit must strictly follow SiS's recommended design
SiS is not responsible for RTC problems from foreign designs.
D
D
3VAUX
VCCRTC
Q13
MMBT3906
E
C
D30
2
1N4148
2
B
R156
10K
+/-5%
R0402
*
*
C
C0805
EC25
22uF
8V, +/-20%
CTB
R601
R0402
BAT
BATOK
BC293
10nF
16V, X7R, +/-10%
C0402
*
* BC296
1uF
*
1
1N4148
10
R169
R0402
Q12
MMBT3904
B
10K
+/-5%
BAT
E
R158
15K
+/-5%
R0402
BC635
1uF
D9
2
D31
1N4148
1
R165
47K
+/-5%
R0402
3VAUX
1
1K AUXOK
+/-5%
AUXOK
R164
100K
+/-5%
R0402
EC24
10uF
6.3V, Y5V, +80%/-20%
C0805
*
7,10
EC6
22uF
8V, +/-20%
CTB
C0805
C
BAT
C
Decoupling Capacitor
Place close to 96X
R603
1K
+/-1%
R0402
RTC_CONN1
1
NC 4
2
3
NC 5
Header_1X3
+5V
+5V
MOSVCC_RUN
3
*
2
TEMP_OVTJ
BC597
0.1uF
25V, X7R, +/-10%
C0603
1
2
5
6
1
Q53
DTA124EUA
Q52
Si3456BDV
3
15
VFAN
R572
+/-5%
1
2
3
820
R0603
4
OUT1
IN1IN1+
V-
V+
8
OUT2
IN2+
IN2-
7
5
6
R47
1K
+/-5%
R0603
B
4
U6
3
B
LM358MX
BC599
10uF
10V, Y5V, +80%/-20%
C0805
R567
10K
+/-5%
R0603
R50
R0603
R51
3K
+/-5%
R0603
+5V_FAN
2K
+/-5%
BC88
10uF
C0805
10V, Y5V, +80%/-20%
*
*
BC87
1nF
C0402
1
2
3
FAN_CONN1
NC 4
NC 5
Header_1X3
1
*
*
BC93
1nF
50V, X7R, +/-10%
C0402
2
A
15
FANSIG
+3V
3
Q54
DTC144EUA
R571 10K
+/-5% R0402
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
32
of
50
5
4
+5VALW
+5VSUS
R376
1M
+/-5%
R0603
D
3
+3VSUS
R359
270
+/-5%
R0603
2
MOSVCC
R833
110
+/-5%
R0603
R827
1M
+/-5%
R0603
D
Q28
G
2N7002
Q21
+5V
+3V
*
G
2N7002
S
+5VALW
Q22
G
S
1
DTC144EUA
2N7002
BC776
1nF
50V, X7R, +/-10%
C0603
S
Q29
2
SUSON
34,35
D
D
3
D
SUSD
10,15,38
1
+1.8V
MOSVCC_RUN
C
C
R825
1M
+/-5%
R0603
R826
270
+/-5%
R0603
R316
110
+/-5%
R0603
R317
32.4
+/-1%
R0603
R314
1M
+/-5%
R0603
MAINONJ
G
D
Q64
G
2N7002
S
2N7002
S
1
D
Q65
G
34
Q66
2N7002
*
G
2N7002
BC426
1nF
50V, X7R, +/-10%
C0603
S
Q19
DTC144EUA
S
Q20
2
15,22,34,36,38 MAINON
D
3
D
MAIND
B
B
H19
H12
HOLE_30X60
H3
HOLE_30X80
H2
HOLE_30X80
H8
HOLE_30X80
H1
HOLE_30X80
H18
HOLE_30X80
H7
HOLE_30X80
HOLE_30X80
AUDGND
H21
H17
HOLE_30X80
H4
H15
HOLE_30X80
H9
H10
HOLE_30X80
H6
HOLE_37X80
H5
HOLE_37X80
H13
HOLE_37X80
H20
HOLE_39X60
H14
HOLE_39X60
H16
HOLE_39X60
HOLE_39X60
H11
A
A
HOLE_39X60
HOLE_39X100
HOLE_39X100
TECHNOLOGY COPR.
Title
Discharge
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
33
of
50
4
3
2
VCC_1999
*
BC485
1uF
VIN
C0603
BC498
BC838
10uF
0.1uF
25V, Y5V, +80%/-20%
C1210
C0603
*
C0603
MAX1999
D
D
D
D
1
R950
R0603
G
S
S
S
1
2
3
4
C
33.2K Dummy
+/-1%
0
+/-5%
R443
R0402
R447
R0603
15,50 3VAUX_EN
*
LX5
15
LX5
DL5
DL5
19
OUT5
21
FB5
PRO
9
10
DL3
22
OUT3
7
FB3
3
4
ON3
ON5
25
LDO3
5
6
7
8
LX3
24
*
DH3
R439
0
+/-5%
R0402
Dummy
Q69
IRF7413
PRO#
R446
0
+/-5%
R0603
REF_1999
ILIM5
ILIM3
REF
TON
GND
PGOOD
ILIM5
ILIM3
11
5
8
13
23
2
BC520
1uF
*
TON
C0603
VCC_1999
SGND2
SGND2
william
073104
5.2uH
1SS355
D43
4A/5V
*
EC30
330uF
CTX
*
BC477
0.1uF
C0402
C
SGND2
VIN
R441
1M
+/-5%
R0402
MAX1999_SHDNJ
R440
0
+/-5%
R0402
BC484
4.7uF
C0805
SGND2
SHORT12
D
D
D
D
BST3
26
SUSOK
+3VALW
5VAUX
L9
28
0
+/-5%
2K
+/-1%
R949
220K
+/-5%
R0603
0.1uF
25V, X7R, +/-10%
G
S
S
S
BC497
C0603
4
3
2
1
16
4.7
+/-5%
1
0.1uF Dummy
10V, X7R, +/-10%
R948
R0402
SGND2
14
DH5
12
BC862
C0402
*
1SS355
D44
BST5
N.C.
R393
R0603
DH5
G
S
S
S
DL3
D
D
D
D
C0805
Q70
IRF7413
VCC
1
27
Q72
IRF7413
4
3
2
1
5.2uH
8
7
6
5
*
EC29
330uF
CTX
LX3
2
*
C0402
BC476
4.7uF
L8
*
*
BC478
0.1uF
4.7
+/-5%
DH3
17
SHDN
SHORT11
4A/3.3V
0.1uF
R392
25V, X7R, +/-10% R0603
*
1
2
3
4
G
S
S
S
BC507
C0603
LDO5
6
3VAUX
V+
D
C0603
18
*
20
SKIP
Q71
IRF7413
BC830
0.1uF
*
5
6
7
8
U30
*
D20
1SS355
2
SGND2
BC503
10uF
25V, Y5V, +80%/-20%
C1210
*
*
C0805
D
D
D
D
BC825
0.1uF
BC483
4.7uF
8
7
6
5
*
C0603
*
D19
1SS355
SGND2
SGND2
BC829
0.1uF
47
+/-1%
C0603
VIN
*
R412
R0603
1uF
BC509
C0603
2
*
*
BC486
0.1uF
1
BC480
4.7uF
25V, X5R, +/-10%
C1206
2
D
4.7
+/-5%
+5VALW
1
R385
R0805
VIN
1
R952
R0603
100K Dummy
+/-1%
BC861
C0402
0.1uF
10V, X7R, +/-10%
*
5
15,36
HWPG
15,36
R416
10K
+/-5%
R0603
R442
330K
+/-5%
R0402
+3VSUS
Q31
Si2301DS
MOSVCC
5VAUX
MOSVCC_RUN
B
*
BC502
1uF
C0805
5
C+
3
BC493
4.7uF
C0805
C-
GND
0
+/-5%
OUT
1
S4,10V
B
2
JUMPER1
2
1
R391
R0603
G
R414
200K
R0603
+/-5%
D
*
S
MAX1683
IN 4
VCC_1999
SHORT14
MOSVCC
U28
*
BC481
4.7uF
C0805
*
BC488
4.7uF
SGND2
D
R951
60.4K
+/-1%
R0603
R445
15K
+/-1%
R0603
R931
15K
+/-1%
R0603
C1206
ILIM5
ILIM3
PRO#
TON
R413
100
R0402
+/-5%
Q32
2N7002
R394
R0402
0
+/-5%
MAINON
+3V
15,22,33,36,38
+3VSUS
+5V
+5VSUS
3VAUX
R426
0
+/-5%
R0402
Dummy
R427
0
+/-5%
R0402
R937
0
+/-5%
R0402
Dummy
R938
0
+/-5%
R0402
5VAUX
S
G
R444
60.4K
+/-1%
R0603
8
1
D1
S2
G1
S1
BC778 Si9936BDY
0.1uF
16V, X7R, +/-10%
C0402
BC774
0.1uF
16V, X7R, +/-10%
C0402
*
*
S1
2
MAIND
5
6
D1
D1
*
33
G1
*
7
3
D1
BC445
0.1uF
16V, X7R, +/-10%
C0402
G2
1
D2
2
MAIND
D2
33
4
SUSD
S2
A
6
33,35
G2
3
Q67
5
D2
4
SUSD
D2
Q25
33,35
SGND2
7
A
8
BC773 Si9936BDY
0.1uF
16V, X7R, +/-10%
C0402
TECHNOLOGY COPR.
Title
Document Number
R ev
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
34
of
50
8
7
6
5
4
3
2
1
5VAUX
D
*
1
BC610
1uF
16V, X7R, +/-10%
C1206
ILIM1
ON1
ILIM2 100mV
ON2
0.1uF
R573
25V, X7R, +/-10%R0603
4
2.2 25
+/-5%
26
3.3uH
EC4
220uF
CTX
BST1
BST2
DH1
DH2
R590
VRON
SUSD
BC613
0.22uF
C0805
25V, Y5V, +80%/-20%
15,31
D1
33,34
D2
LX2
16
DL1
DL2
19
5VAUX
R587
R0402
D1
0
+/-5%
235khz/170khz
5
TON
PGND
22
OUT1
OUT2
14
SKIP
6
FB2
13
1
2
1G
1
SGND5
R589
500 +-1%
R0603
not in cis
07/15/04
BC624
0.47uF
9
C0805
25V, Y5V, +80%/-20% 2
8
REF
+2.0V
FB1
AGND
MAX1715
PGOOD
SIS648Fx: IVDD=1.5V/2.2Amax
SIS661fx: IVDD=1.8V/1.3Amax
BC192
0.1uF
C0603
IVDD
FDS6982S
G1
S1
D1
PL1
D2
2
MAX 4.0A
5.2uH
PQ2A
FDS6982S
*
G1
S1
EC7
220uF
CTX
*
EC5
220uF
CTX
*
BC616
2.2uF
16V, Y5V, +80%/-20%
C0805
RB751V-40
D29
C
SGND5
Vfb=1.0V
R585
X.0K +-1%
R0603
SGND5
7
R646=8K:
R646=5K:
SGND5
R594
10K
+/-1%
R0603
*
PQ2B
*
LX1
24
BC214
4.7uF
C1206
SHORT9
4
3
PQ1A D2
FDS6982S
S1
1
0
27
*
*
8
7
D8
B140
EC3
220uF
CTX
0
11 MAX1715_ON2
R575
2.2
18
R0603
+/-5%
17
3
S1
*
2
C
*
10 MAX1715_ON1 R592
*
BC227
4.7uF
C1206
7
FDS6982S
*
4
2
3
12
V+
5
VCC
1G
L16
3S2P -- 10.8V/typ;
1
BC612
C0603
D1
21
8
D2
PQ1B
VDD
6
R0805
BC644
0.1uF
C0603
Vin:
VIN
1
*
*
BC642
4.7uF
C1206
6
*
5
SHORT1
BC259
4.7uF
C1206
20
*
R586 250K +-1%
R591 250k +-1%
R0805
*
BC615
0.1uF
25V, X7R, +/-10%
C0603
U36
SGND5
NC1
NC2
NC3
VIN
+VCCP
*
2
*
3S2P Li+
Vccp=1.05V
*
VIN
D26
RB751V-40
D
BC604
BC601
1nF
4.7uF
50V, NPO, +/-5%10V, X7R, +/-10%
D27
C0603
C1206
RB751V-40
1.8V for IVDD sis661fx
1.5V for IVDD sis648fx
15
23
28
MAX 4.0A
*
BC605
4.7uF
10V, X7R, +/-10%
C1206
2
*
BC614
1nF
50V, NPO, +/-5%
C0603
1
R576
4.7
+/-5%
R0603
3VAUX
R588
R0402
R583
10K
+/-1%
R0603
10K
+/-5%
VCCP_HWPG 31
SGND5
SGND5
B
B
SHORT8
1
2
JUMPER1
SGND5
A
A
TECHNOLOGY COPR.
Title
Document Number
R ev
661S03
Date:
8
7
6
5
4
3
2
Friday, August 13, 2004
A
Sheet
35
1
of
50
8
7
6
5
4
3
2
1
D
D
5VAUX
5VAUX
VIN
BC489
1uF
C0603
MAX1993
SGND4
BC492
1uF
C0603
0.22uF VREF
16V, X7R, +/-10%
*
ILIM
3
LSAT
6
REF
5
ILIM
LX
16
CSN
12
REFIN
OD
R383
R0402
0
+/-5%
21
DL
18
CSP
11
FB
OUT
9
10
8
7
6
5
BC504
FBLANK
1
TON
PGOOD
R438
37.4K
+/-1%
R0603
D
R437
100K
+/-1%
R0603
Dummy
SGND4
R415
0
+/-5%
R0402
G
S
2N7002
Dummy
1
R428
100K
+/-1%
R0603
Dummy
2
BC449
10uF
25V, Y5V, +80%/-20%
C1210
0.1uF
C0603
Q26
(7000 MA 1.2V VDDC )
D
VCORE_VGA
IRF7455
3
2
Q27
D
L21
1
*
0.8uH
EC20
330uF
CTX
*
EC19
330uF
CTX
D42
B320B
4
C
SHORT10
ESR
40mR
4
*
BC515
1nF
50V, X7R, +/-10%
C0402
4
IRF7455
R390
0
+/-5%
R0402
SGND4
SHORT6
*
25
R387
0
+/-5%
R0402
20
R434
75K
+/-1%
R0603
VOUT_L
BC785
10uF
C1210
15,22,33,34,38
3
2
1
: Core VCC=1.2V
: Core VCC=1V
GATE
2
Q33
SGND4
R388
2.2
17
BST R0805
+/-5%
DH 15
0
+/-5% MAINON
*
BC457
1nF
C0805
2
8
R382
R0402
*
1
0
1
Demo is 37.5K
B
OVP/UVP
BC506
0.1uF
25V, Y5V, +80%/-20%
C0603
T
VCORE_L/H#
VOUT_H
NEW COMPENT
24
GND
41
ILIM
R411
140K
+/-1%
R0603
23
1nF VOUT_H7
50V, X7R, +/-10%
VOUT_L
R429
75K
+/-1%
R0603
14
SHDN#
SKIP#
R395
100K
+/-1%
R0603
BC513
C0402
*
VREF
SGND4
V+
VCC
13
C
BC508
C0805
SGND4
VDD
22
BC496
4.7uF
10V, Y5V, +80%/-20%
C0805
VIN
8
73
62
51
SGND4
Vref=2.0V
19
2
*
*
D18
RB751V-40
SGND4
*
*
U29
BC490
1nF
C0402
1
*
R381
4.7
+/-5%
R0603
*
HWPG
PHE5330E: 30V-85A-7.5mohm
Iilim=79mV>(Iloadmax-0.15Iloadmax)*Rdaon
=(10-0.15*10)*7.5
15,34
=63.75;
B
JUMPER1
SAVE_POWER_M10 15
SGND4
SGND1
A
A
TECHNOLOGY COPR.
Title
VCORE VGA
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
36
of
50
8
7
6
VDDQ
M661FX+302LV is 1.8V ; 648FX+M10 is 1.5V
lonny 070804
5
4
3
2
1
AUX_IVDD 1.8V/1.9V
Vref=1.24V
for SB1.8V current 38mA (max)
for SB1.5V current 48mA (max)
VDDQ 1.8/1.5V_5A
+
-
R681
124
+/-1%
R0402
R680
45.3
+/-1%
R0402
dummy
R679
54.9
+/-1%
R0402
Vref
1
*
D
AUX_IVDD=1.9V(648FX)
JP50 OPEN JP51 SHORT
*
BC272
470uF
2.5V, +/-20%
CTX
*
BC284
BC673
470uF
0.1uF
2.5V, +/-20%16V, X7R, +/-10%
CTX
C0603
R829
43.2
+/-1%
R0603
3VAUX
*
1
VIN
ADJ
3
AUX_IVDD=1.8V(M661FX)
JP50 OPEN JP51 OPEN
AIC1084CE
VOUT 2
R313
R0402
R318
R0402
R933
45.3_1%
VDDQ
1.5V
R_OPEN
1.8V
62
+/-5%
62
+/-5%
JP22
SHORT
*
BC436
0.1uF
16V, X7R, +/-10%
C0402
AUX_IVDD
2
U13
U22
SC431L
2
D
BC304
10uF
10V, Y5V, +80%/-20%
C1206
@dummy
VDDQ
Vref=1.25V
1
+
Vref
3
+3V
1.8V for VB/1.5V for AGP
-
C
R830
47
+/-1%
BC423
R0603 BC424
0.1uF
10uF
16V, X7R, +/-10%
C0402
10V, X5R, +/-10%
C1206
R839
105
AUX_IVDD Sis consumption
+/-1%
Current is 493mA
R0603
*
*
Spec
C
1
Lonny 070804
B
2
JP23
SHORT
VDDQ Sis consumption Spec
Current is 281.3mA( Only AGP8X)
Lonny 070804
R838
560
+/-1%
R0603
+3V
3VAUX
+1.8VAUX
U8
3
Vin
2
Vout 4
1
BC360
10uF
10V, X5R, +/-10%
C1206
ADJ
4
+
Vref
U19
AIC1084CE
VOUT 2
R283
105
+/-1%
R0603
Vref=1.25V
R284
54.9
+/-1%
R0402
*
TC5
470uF
2.5V, +/-20%
CTX
*
BC387
10uF
10V, X5R, +/-10%
C1206
BC210
10uF
10V, Y5V, +80%/-20%
C1206
*
1
3
VIN
ADJ
AIC1086
*
B
+1.8V
+
Vref
-
Vref=1.25V
R121
240
+/-1%
R0603
R129
86.6
+/-1%
R0603
*
BC188
470uF
2.5V, +/-20%
CTX
*
BC215
470uF
2.5V, +/-20%
CTX
*
BC213
0.1uF
16V, X7R, +/-10%
C0603
R124
45.3
+/-1%
R0402
A
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
37
of
50
5
4
3
2
1
D
D
*
9
EC18
47uF
4V, +/-20%
CTB
VTT
AVDD
26
R355
10
+/-5%
R0402
VTTS
11
PGND2
10
VTTR
VDD
FB=AVdd: 1.8V Output
FB=GND: 2.5V output
*
BST
20
R330
33K
+/-1%
R0603
POK2
25
SKIP#
1
24
TON
GND
8
R375
178k
+/-1%
R0603
3
LX
19
DH
18
D
BC451
0.1uF
C0603
*
BC447
4.7uF
C1206
*
Q24
IRF7455
4
VDIMM_BF
L20
*
POK1
6
BC450
0.22uF
10V, X7R, +/-10%
C0603
*
3
2
1
5
BC430
0.1uF
C0603
C
VIN
2.7uH
SHORT4
VDIMM
SS
DL
D
21
2
BC467
3.9nF
C0603
BC471
0.22uF
C0603
R374
68K
+/-1%
R0603
D17
B120
2
OVP/UVP
*
+/-5% R0402
BC460
4.7uF
10V, Y5V, +80%/-20%
C0805
8
7
6
5
R367 0
5VAUX
BIAS
SUPPLY
1
17
2
+2.0V
4
REF
PGND1
23
SHDNA#
27
*
1SS355
D16
Q23
IRF7455
C34
150uF
4V, +/-20%
CTX
*
C35
150uF
4V, +/-20%
CTX
*
BC417
1uF
10V, Y5V, +80%/-20%
C0603
B
1
B
2
VIN
R368
0
+/-5%
Dummy R0402
* *
TON=open: 300KHz
TON=GND: 600KHZ
R357
0
+/-5%
R0402
Dummy
BC468
1uF
C0603
4
ILIM
15
FB
16
OUT
MAX8550
THERMALPAD
SKIP#=AVdd: PWM
SKIP#=GND: Skip mode
R363
R362
100K
100K
+/-5%
+/-5%
R0402 R0402
*
SHDNB#
STBY
29
R358
0
+/-5%
R0402
R373
100K
+/-5%
R0402
SHORT5
1
JUMPER1
22
DDRVREF
C
BC466
1uF
10V, Y5V, +80%/-20%
C0603
28
7
SUSON
MAINON
10,15,33
3
2
1
EC11
47uF
4V, +/-20%
CTB
12
8
7
6
5
*
*
*
BC458
22uF
C1206
DDR_VTT
VTTI
REFIN
U25
13
C0402
14
*
BC452
10nF
15,22,33,34,36
R364
+/-5%
10K
R0402
+3VSUS
R365
+/-5%
0
R0402
S3AUXSW-
6,10
Vilim(min)=10*Ioutmax*(1-LIR/2)*Rdsonlow25c*1.25
=10*12*0.85*5*1.25
=637.5MV
A
A
Vilim_rating=637.5*1.15=733.125MV
R4=(2V-0.3*Vilim_rating)/10=178Kohm;
TECHNOLOGY COPR.
Title
VDIMM&VTT_MEM
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
38
of
50
VIN
6
5
MMBATA+
Q59
Si4835DY
MBATA+
4
3
VINT
FB25 FB L0805 300 Ohm
1
2
MBATA+
R800
100K
+/-5%
R0402
8
7
6
5
3
2
1
4
Q63
S
Q61
2
G
MBATV
R820
18K
+/-1%
R0603
S
1
2N7002
*
Q7
15
C0603
C0603
1
BC398
1nF
50V, X7R, +/-10%
C0603
MMBATA+
MBCLK_BATA
MBDATA_BATA
3,15
MBCLK
3,15
MBDATA
15 MBAT_PRESJ
R302 R0603
R307 R0603
R310 R0603
BATTCONN1
330 +/-5%
330 +/-5%
330 +/-5%
1
2
BATT1+
BATT2+
3
4
5
6
7
SMB_CLK
SMB_DAT
BATT_PRES#
BATTBATT1-
D
BATT-CONN
BC771
10nF
C0603
G
2N7002
3
REFON
S
15
Monitor battery voltage
*
*
FB24 FB L0805 300 Ohm
1
2
BC760
47pF
R568
75K
+/-1%
R0603
D
D
2N7002
*
BC759
0.1uF
R312
10K
+/-5%
R0402
D
G
3
Q62
DTC144EUA
D
R559
75K
+/-1%
R0603
D
R801
100K
+/-5%
R0402
R785
102K
+/-1%
R0603
2
2
Q8
G ACIN_3
S
2N7002
R43
10K
R0402
+/-5%
R45
75K
+/-1%
R0603
ACIN
1
D15
BAT54S
15
2
3
7
VIN
3
8
1
2
D13
BAT54S
1
D12
BAT54S
+3VALW
+3VALW
+3VALW
+3VALW
ADIN
PWR
GND
GND
GND
GND
2
*
3
BC5
0.1uF
*
C0805
BC2
0.1uF
*
C0805
BC526
0.1uF
50V, Y5V, +80%/-20%
C0805
*
C
R469
75K
+/-5%
R0603
BC1
0.1uF
50V, Y5V, +80%/-20%
C0805
BC589
10uF
C1210
G
*
S
2N7002
R581
10K
BC524 R0402 +/-5%
0.1uF
16V, X7R, +/-10%
C0402
VSYS
*
B320B
BC525
0.1uF
50V, X7R, +/-10%
C0805
R565
0
+/-5%
R0402
R558
10
+/-5%
R0402
B
*
R584
R0402
BC618
10uF
470
+/-5%
8
7
6
5
BC596
1uF
25V, Y5V, +80%/-20%C1210
C0805
*
*
D
1
2
3
4
BC630
10uF
C1210
R563R0402
R564R0402
CC_SET
CV_SET
REFON
0 +/-5%
0 +/-5%
CC_SET_1
CV_SET_1
R553
100K
+/-1%
R0603
Dummy
R555
49.9
+/-1%
R0402
Dummy
R570
R0603
R566
R1206
0
+/-5%
47.5K
+/-1%
R569
100K
R0402
+/-5%
*
BL
CC_SET_1
CV_SET_1
1
ACAV
2
BL
7
6
8
4
ISET
VSET SYS_BL
REF_EN
ICHG
5
COR
*
BC606
OZ862A
1uF
10V, Y5V, +80%/-20%
C0603
JUMPER1
SGND7
SGND7
SGND7
SGND7
20
10
COMP
LV
9
CELLS
15
15
15
100K
+/-5%
18
19
11
VAC
IACM
IACP
GND
R557
15K
+/-1%
R0603
Dummy
R580
R0402
15
14
13
17
12
R556
100K
+/-1%
R0603
Dummy
10K
+/-5%
HDR
ICHP
ICHM
REF
CHIGH
BC629
10uF
*
BC178
10uF
C1210
B
*
REF3V
BC592
10uF
10V, Y5V, +80%/-20%
C0805
SGND7
R574 1K
BC594
10uF
10V, Y5V, +80%/-20%
C0805
BC609
0.47uF
Q56
25V, Y5V, +80%/-20%
C0805
2N7002
*
SGND7
R562
R0603
3
REF3V
+3VALW
**
BC608
0.1uF
C0603
1
*
U35
+3VALW_591
ACIN
MBATA+
D28
B320B
16
15
R598R2512
39 Ohm
+/-5%
*
C1210
BC593
1uF
C0805
R578
R0402
15
R579
0
R0402
+/-5%
SGND7
SGND7
47.5K
SGND7
+/-1%
R561
10K
+/-1%
R0402
+/-1% R0402
D
R470
47.5K
+/-1%
R0603
2
L11 15uH
ACIN
2
1
Q10
FDS4435
20m +/-5%
S
R560 R2512
G
D7
A
*
Q1
DC JACK
ADIN
*
BC611
10uF
C1210
G
CHA_OFF
15
S
5
FB L0805 300 Ohm
1
2
VINT
1
2
3
4
G
4
FB2
1
8
7
6
5
S
CN10
D
C
Q34
FDS4435
FB L0805 300 Ohm
1
2
D
FB1
A
SGND7
TECHNOLOGY COPR.
Title
VIN
Charger
Document Number
Re v
661S03
Date:
Friday, August 13, 2004
A
Sheet
39
of
50
8
7
+3V
FB L0805 120 Ohm
FB49
1
6
+3V
OVDD
2
*
FB13
1
5
FB L0805 120 Ohm
+5V
*
BC266
10uF
C1206
*
BC708
0.1uF
C0402
*
BC274
0.1uF
C0402
3
2
clock source:R25/R38:crystal/mainboard
DVDD
2
BC702
0.1uF
16V, X7R, +/-10%
C0402
4
+3V
FB15
1
+5V
*
*
BC298
0.1uF
C0402
DGND
BC701
10uF
C1206
*
BC707
0.1uF
C0402
VBOSCO
*
1
Y1 XTAL-14.318MHz
R166
1
2
R0603
27pF
27pF
BC260
BC258
C0603
C0603
FB L0805 120 Ohm
2
BC295
10uF
*
10 VBRCLK
+/-5%
*
LVDD1
*
C1206
*
BC297
0.1uF
C0402
BC306
0.1uF
C0402
D
D
VBD[11..0]
VBD0
VBD1
VBD2
VBD3
VBD4
VBD5
VBD6
VBD7
VBD8
VBD9
VBD10
VBD11
Clock
Source
5
5,41
5,41
VDDQ
VBGCLK
VBCTL0
VBHSYNC
VBVSYNC
VAGCLK
VAHSYNC
VAVSYNC
5
5,41
5,41
5,41
VBVSYNC
VBHSYNC
VBCTL0
VBD0
VBD1
VBD2
VBD3
VBD4
VBD5
DVDD
DGND
VBGCLK
VBD6
VBD7
VBD8
VBD9
VBD10
VBD11
*
Crystal
R38
10
NC
R25
NC
10
U12
B
103
VADE 104
VADE
DGND
105
106
VBCAD
107
5
VBCAD
VBHCLK
108
5
VBHCLK
DGND
109
DVDD
110
OVDD
111
112
21 302LV_DDC1DAT
113
21 302LV_DDC1CLK
114
R0402
115
DD2
R713100
116
DC2
117
R710100
+5V
118
R0402
119
120
121
INT-A
122
7,9,22,23 INT-A
EXTRSTN
123
9,15,17,22,23,29,41 PCIRSTJ
124
125
R726
4.7K R0402 PFTEST0
126
+3V
VGA_GPIO16 127
21 VGA_GPIO16
FPBACKJ
128
21
FPBACKJ
C0402
7,18 302LV_CRT_R
+3V
FB16 FB L0805 120 Ohm
1
2
BC305
BC313
0.1uF
10uF
*
C0402
DVDD
*
C0402
LVDD2
BC679
0.1uF
7,18 302LV_CRT_G
*
R725
4.7K
R0402
5,41
*
BC685
0.1uF
7,18 302LV_CRT_B
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VAD0
VAD1
VAD2
VAD3
VAD4
VAD5
VAD6
VAD7
VAD8
VAD9
VAD10
VAD11
C
Main
Board
C1206
VAD[11..0]
VAD[11..0]
FB46 FB L0805 120 Ohm
1
2
BC672
10uF
Choose clock source:
VAD0
VAD1
VAD2
VAD3
VAD4
VAD5
DVDD
DGND
VAGCLK
VAD6
VAD7
VAD8
VAD9
VAD10
VAD11
DGND
VAHSYNC
VAVSYNC
5,41
+3V
DVDD4
VADE
DVSS4
RESERVED
VBCAD
VBHCLK
DVSS5
DVDD5
OVDD
GPIOA(GPI)
GPIOB(GPI)
GPIOC(GPI)
GPIOD(GPI)
LDDCDATA
LDDCCLK
V5V
V2HSYNC
V2VSYNC
LCDSENSE
INTA#
EXTRSTN
PFTEST1
PFTEST2
PFTESTO
GPIOG(GPO)
GPIOH(GPO)
DVDD1
VBDE
VBCTL1
DVSS1
OVDD
VBCLK
DVSS0
TVCLKO
TSCLKI
DVDD0
PLL1VDD
VBOSCO
VBRCLK
PLL1GND
RESERVED
IOCS
DAC_GND
DAC_VDD
RESERVED
IOC
RESERVED
IOY
RESERVED
IOCOMP
V2COMP
DAC_GND
SiS302LV
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
C
*
C1206
LPLLVDD
BC312
0.1uF
C0402
LPLLGND
DVDD
VBDE
VBCTL1
DGND
VDDV
VBCLK
DGND
VBDE
VBCTL1
5,41
5,41
VBCLK
5,41
+3V
BC261
FB12 FB L0805 120 Ohm
1
2
BC265
10uF
*
DVDD
TVPLLVDD
VBOSCO
VBRCLK
TVPLLGND
*
C1206
0.1uF V2COMP
C0402
DACVDD
BC663
BC267
0.1uF
0.1uF
*
VBD[11..0]
VAVSYNC
VAHSYNC
OVSS
VAD11
VAD10
VAD9
VAD8
VAD7
VAD6
VAGCLK
DVSS3
DVDD3
VAD5
VAD4
VAD3
VAD2
VAD1
VAD0
RESERVED
RESERVED
VBD11
VBD10
VBD9
VBD8
VBD7
VBD6
VBGCLK
DVSS2
DVDD2
VBD5
VBD4
VBD3
VBD2
VBD1
VBD0
VBCTL0
VBHSYNC
VBVSYNC
5,41
*
C0402
C0402
DACGND
DACGND
DACVDD
VDDQ
FB45 FB L0805 120 Ohm
1
2
BC668
10uF
302LV_TV_CHROMA 18
302LV_TV_LUMA 18
*
302LV_TV_COMP 18
V2COMP
DACGND
*
C1206
VDDV
BC662
0.1uF
B
C0402
+3V
+3V
LVDSPLLVDDL
LPLLCAP
LVDSPLLVSS
LAVSS
LXC2P
LXC2N
LAVDD
LX7P
LX7N
LAVSS
LX6P
LX6N
LAVDD
LX5P
LX5N
LVDSPLLVSS
LX4P
LX4N
LVDSPLLVDD
LAVDD
LX3P
LX3N
LAVSS
LXC1P
LXC1N
LAVDD
LX2P
LX2N
LAVSS
LX1P
LX1N
LAVDD
LX0P
LX0N
LAVSS
EXTSWING
DACVDD
V2RSET
A
LXC2+,LXC2-,LX7+,LX7-,LX6+,LX6-,LX5+,LX5LX4+,LX4- are 302LV LVDS dual link signals
*
BC705
100pF
50V, NPO, +/-5%
LPLLVDD
C0402
C0402
C1206
*
TVPLLVDD
BC667
0.1uF
C0402
TVPLLGND
A
R638
R0603
R698
0
R699
R0402 +/-5% R0402
dummy
*
ISET
DACVDD
VSWING
LGND
TXLOUT0TXLOUT0+
LVDD2
TXLOUT1TXLOUT1+
LGND
TXLOUT2TXLOUT2+
LVDD2
TXLCLKOUTTXLCLKOUT+
LGND
LVDD2
LGND
LVDD1
LGND
DC2
LVDD1
LGND
LPLLGND
LPLLCAP
LPLLVDD
DD2
*
FB44 FB L0805 120 Ohm
1
2
BC688
BC671
0.1uF
10uF
SiS302LV
R650
R0603
0
LVDD1
+/-5%
R654
R0603
147
+/-1%
5.9K
+/-1%
BC666 1uF
24K
C1206
+/-5%
*
R719
2.2K
+/-5%
R0402
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
R706
2.2K
+/-5%
R0402
21 302_TXLOUT2+
21 302_TXLOUT221 302_TXLOUT1+
21 302_TXLOUT121 302_TXLOUT0+
21 302_TXLOUT021 302_TXLCLKOUT21 302_TXLCLKOUT+
TXLOUT2+
TXLOUT2TXLOUT1+
TXLOUT1TXLOUT0+
TXLOUT0TXLCLKOUTTXLCLKOUT+
TECHNOLOGY COPR.
R694 Demo Valve is 6K
lonny 20040601
Title
LGND
Document Number
301lv/302lv: R63/R59
Rev
661S03
Date:
8
7
6
5
4
3
Friday, August 13, 2004
2
A
Sheet
40
of
1
50
5
4
3
2
1
FOR ALL GPIO AND ZV_DATA SIGNALS
THAT ARE ALSO CONFIGURATION STRAPS
ENSURE CORRECT PULL UP/DOWN ARE MAINTAINED
DURING POWER ON RESET CONFIGURATION
SEE DATA BOOK
U41A
AC26
WBF#
5
AGP_RBF#
5 AGP_ADSTBF_0
5 AGP_ADSTBF_1
5
AGP_SBSTBF
AE29
M28
V25
AB29
RBF#
AD_STBF_0
AD_STBF_1
SB_STBF
SBA[1..7]
VBCLK
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
AD28
AD29
AC28
AC29
AA28
AA29
Y28
Y29
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
AF29
AD27
AE28
ST0
ST1
ST2
5,40
5
ST[2..0]
VBCLK
ST[2..0]
5 AGP_SBSTBS
5 AGP_ADSTBS_0
5 AGP_ADSTBS_1
5,46
AGPREF
46
AGP_TEST
M9 <> M10
CONNECT DBI_LO/DBI_HI
TO AGP CONN FOR AGP3.0 ON M10
OR TO VDDP FOR AGP2.0 ON M10
OR TO VDDP FOR M9
VDDQ
5
DB_LO
5
DB_HI
5 AGP8X_MB_DETJ
@M10 BC302
*
B
R233
R234
R732
PLACE C83 CLOSE TO ASIC PIN
VDDQ
0 R0603 dummy
0 R0603 dummy
0 R0603
@M10
M9 <> M10
CONNECT AGP_DET#
TO VDDP FOR M9 OR
TO 1.5V PU OR TO AGP CONN WITH 1.5V PU FOR M10
AB26
AB25
AC25
R73547K
@M10
R0402
18 M10_TV_COMP
18 M10_TV_CHROMA
18 M10_TV_LUMA
THIS DESIGN SHOWS DAC2 CONFIGURED FOR TV OUT
DAC2 CAN ALSO BE CONFIGURED FOR SECONDARY CRT
MUX LOGIC IS REQUIRED FOR DAC2 AS BOTH TVOUT AND SECONDARY CRT
47
47
AB28
M29
V26
C0402 0.1uF
16V, X7R, +/-10%
M26
M27
R258
715
AK21
R0402 +/-1% @M10
AJ23
AJ22
AK22
T6
T9
REMOVE TESTEN PULL DOWN
FOR OPTIONAL TEST MODE ENABLE
REFER TO DATA BOOK
FOR JTAG AND SCAN SIGNAL SOURCES
+3V
+3V
+3V
5
4
@M10
H2SYNC
V2SYNC
AK25
SSIN
AJ25
SSOUT
AH28
XTALIN
M9 <> M10
PULL-UP TEST_YCLK/MCLK VDD_MEM_IO
T4
TO BER223
COMPATIBLE
WITH M9
SUSTAT#
10K R0402 @M10
M9 <> M10
CONNECT RSTB_MSK TO GND OR TO AGP CONN FOR M10
CONNECT RSTB_MSK TO GND FOR M9
C_R_Pr
Y_G_Y
COMP_B_Pb
STP_AGP#
0
RSTB_MSK
R0402
AJ29
XTALOUT
AH27
E8
B6
AE25
TESTEN
TEST_YCLK(NC)
TEST_MCLK(NC)
PLLTEST(NC)
AG26
AH30
AH29
AG29
SUS_STAT#
STP_AGP#
AGP_BUSY#
RSTB_MSK(NC)
DVO / EXT TMDS / GPIO
T41
T39
T38
T37
SOUT
46
SIN
46
SCLK
46
ROM_ID1
46
ROM_ID2
46
ROM_ID3
46
T40
ROM_ID4
46
VCORE_L/H#
VCORE_L/H# 36
OSC_SPREAD
T42
R293
0 R0402 dummy VDD_CORE1.8
R788
0 R0402 @M10
DVO IS CONFIGURED FOR ZVPORT (DVOMODE = GND)
ON THIS DESIGN
IT CAN ALSO BE DDR EXTERNAL TMDS (DVOMODE = 1.8V)
SEE DATA BOOK
UNUSED GPIO,DDC OR ZV_LCDDATA CAN BE
USED FOR PANEL OR MEMORY ID
IF DVO IS CONFIGURED FOR 12 BIT EXT DDR TMDS
ANY UNUSED LCDDATA PULLUP STRAPPING
MUST BE TO +1.8V
DIGON
BLON
AE12
AG12
DISP_ON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
T18
T15
T1
T11
T12
T14
T16
T19
DDC2CLK
DDC2DATA
AE13
AE14
T13
T17
HPD1
AF12
T20
R
G
B
AK27
AJ27
AJ26
HSYNC
VSYNC
AG25
AH25
1
3
5
7
AUXWIN
AF26
DPLUS
DMINUS
AF11
AE11
+3V
BC407 BC410 BC415
10nF 10nF 10nF
R836
C0402 C0402 C0402
1K
+/-5% @M10 @M10 @M10
R0402
M9 <> M10
@M10
* * *
+3V
+3V
R299
10K
+/-5%
R0402
@M10
R304
10K
+/-5%
R0402
@M10
R308
10K
+/-5%
R0402
@M10
R791
10K
+/-5%
R0402
@M10
R798
10K
+/-5%
R0402
@M10
R803
10K
+/-5%
R0402
@M10
CONNECT VREFG TO VDDC FOR M9
CONNECT VREFG TO VOLTAGE DIVIDER FOR M10
B
+3V
21
R769
R778
10K
+/-5%
R0402
0 dummy
R0603
R779
@M10
VGA_BLON
330 B
R0402
M10_CRT_R
M10_CRT_G
M10_CRT_B
21
Q60
MMBT3904
@M10
18
18
18
M10_CRTHS_VGA 18
M10_CRTVS_VGA 18
499 R0402
M10_DDC1DAT 18
M10_DDC1CLK 18
D+
D-
A
R246
10K
R0402
46
46
TECHNOLOGY COPR.
Title
@M10
M9/M10 CORE_A
+3V
PULL UP AUXWIN
IF NOT USED
Document Number
2
R ev
661S03
Date:
3
+3V
+3V
10K +/-5%
8P4R0603
R837
1K
+/-5%
R0402
@M10
M10_TXLCLKOUT- 21
M10_TXLCLKOUT+ 21
AH26 @M10 R247
AF25
AF24
RN44 @M10
2
4
6
8
*
21
21
21
21
21
21
+3V
M10_DDCDAT 21,46
M10_DDCCLK 21,46
C
AG4
DDC1DATA
DDC1CLK
2.21K R0603
2.21K R0603
@M10 R805
10K R0402
+3V
PANEL_ID0
PANEL_ID1
PANEL_ID2
M10_TXLOUT0M10_TXLOUT0+
M10_TXLOUT1M10_TXLOUT1+
M10_TXLOUT2M10_TXLOUT2+
M9+X_M10-P
@M10 R823
@M10 R807
33R0402
33R0402
@M10 R821
@M10 R822
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
RSET
D
T32
T35
T34
T29
T28
T33
T21
T27
T23
T2
T3
T22
T36
T30
T26
T31
T25
T24
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
R2SET
T5
T7
10K R0402 @M10
10K R0402 @M10
R727
DBI_LO
DBI_HI
AGP8X_DET#
DDC3CLK
DDC3DATA
R0402 @M10
R714
R703
AGPREF
AGPTEST
AG23
AG24
X2
R2451K
SB_STBS
ADSTBS_0
ADSTBS_1
T10
T8
X1
A
AJ24
AK24
(NC)VREFG
TMDS
SBA[1..7]
AJ10
AK10
AJ11
AH11
DAC1
5
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
46
46
46
46
C
AGP_WBF#
5
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
GPIO0
GPIO1
GPIO2
GPIO3
E
PCICLK
RST#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTA#
AE10
LVDS
AG30
AG28
AF28
AD26
M25
N26
V29
V28
W29
W28
AE26
13
AGPCLK1
9,15,17,22,23,29,40 PCIRSTJ
5
AGP_REQ#
5
AGP_GNT#
5
AGP_PAR
5
AGP_STOP#
5 AGP_DEVSEL#
5
AGP_TRDY#
5
AGP_IRDY#
5 AGP_FRAME#
9,46 INT-B
C
C/BE#0
C/BE#1
C/BE#2
C/BE#3
DVOMODE
THERM
N29
U28
P26
U26
PCI / AGP
AC-BE0
AC-BE1
AC-BE2
AC-BE3
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
AGP2X
AC-BE[0..3]
AC-BE[0..3]
Part 1 of 6
AGP
4X
8X
5
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
DAC2
M9CSP32/64 AND M9+CSP32/64
AND M10CSP32 ARE 31MM X 31MM PACKAGES
M10CSP64 IS 35MM X 31MM PACKAGE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CLK SS
NOTE:
D
H29
H28
J29
J28
K29
K28
L29
L28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27
W26
W25
Y26
Y25
AA26
AA25
AA27
VBD7
VBD6
VBD5
VBD4
VBD3
VBD2
VBD1
VBD0
VAD6
VAD5
VAD4
VAD7
VAD8
VAD9
VAD10
VAD11
VADE
VAVSYNC
VAHSYNC
VBD11
VBD10
VBD8
VBD9
VAD1
VAD0
VAD2
VAD3
VBDE
VBCTL0
VBCTL1
VBHSYNC
VBVSYNC
PWR
MAN
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
5,40
Friday, August 13, 2004
A
Sheet
1
41
of
50
1
2
3
4
5
6
7
8
M9 <> M10
EXTERNAL MEMORY CAN BE CONNECTED TO CHANNEL B ON M9CSP32 AND M9+CSP32
INTERNAL MEMORY IS CONNECTED TO CHANNEL A WITH SIGNALS AVAILABLE FOR TESTING ONLY ON M9CSP32 AND M9+CSP32
ALL CHANNEL A AND B MEMORY SIGNALS ARE GROUNDS ON M9CSP64,M9+CSP64 AND M10CSP64
SO ENSURE THEY ARE NOT CONNECTED TO GROUND ON THE BOARD IF M10CSP32 OR M9+CSP32 IS AN OPTION
NO EXTERNAL MEMORY CAN BE CONNECTED TO CHANNEL A OR B ON M10CSP32 OR M10CSP64
CHANNEL B MEMORY HAS BYTES 2 AND 3 SWAPPED AND SIGNALS ARE AVAILABLE FOR TESTING ONLY ON M10CSP32
MAA[0..13]
U41B
B
C
44,48
MDA[0..63]
L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
Part 2 of 6
MEMORY INTERFACE A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
44,48
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
(MAA13)MAA12
(MAA12)MAA13
(NC)MAA14
E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
J25
F29
E25
A27
F15
C15
C11
E11
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
J27
F30
F24
B27
E16
B16
B11
F10
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
A19
RASA
RASA
44,48
CASA#
E18
CASA
CASA
44,48
WEA#
E19
WEA
WEA
44,48
CSA0#
E20
CSA0
CSA0
44,48
CSA1#
F20
CSA1
CSA1
44,48
CKEA
B19
CKEA
CKEA
44,48
CLKA0
CLKA0#
B21
C20
CLKA0
CLKA0#
CLKA0
44
CLKA0#VDD_MEM_IO
44
CLKA1
CLKA1#
C18
A18
CLKA1
CLKA1#
CLKA1
CLKA1#
MVREFD
B7
(NC)MVREFS
B8
DIMA_0
DIMA_1
DQMA[0..7]
QSA[0..7]
44,48
R831
1K
R824
1K
+/-5%
R0402
@M10
D30
B13
44,48
44
44
+/-5%
R0402
@M10
*
BC772
0.1uF
*
C0402
@M10
45,48
M9+X_M10-P
A
U41C
EC13
10uF
12.5V, +/-20%
CTB
@M10
MDB[0..63]
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
Part 3 of 6
VDD_MEM_IO
R793
1K
+/-5%
R0402
@M10
*
BC766
0.1uF
C0402
@M10
*
DQMB[0..7]
45,48
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
E6
B2
J5
G3
W6
W2
AC6
AD2
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
F6
B3
K6
G1
V5
W1
AC5
AD1
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
R2
RASB
RASB
45,48
CASB#
T5
CASB
CASB
45,48
B
WEB#
T6
WEB
WEB
45,48
CSB0#
R5
CSB0
CSB0
45,48
CSB1#
R6
CSB1
CSB1
45,48
CKEB
R3
CKEB
CKEB
45,48
CLKB0
CLKB0#
N1
N2
CLKB0
CLKB0#
CLKB0
CLKB0#
45
45
CLKB1
CLKB1#
T2
T3
CLKB1
CLKB1#
CLKB1
CLKB1#
45
45
+3V
DIMB_0
DIMB_1
E3
AA3
ROMCS#
AF5
C6
C7
MEMTEST
C8
R841
10K
+/-5%
R0402
@M10
@M10 R311
@M10 R309
R806
47
+/-5%
R0402
@M10
R789
1K
+/-5%
R0402
@M10
45,48
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MEMVMODE_0
MEMVMODE_1
M9+X_M10-P
MAB[0..13]
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
(MAB13)MAB12
(MAB12)MAB13
(NC)MAB14
MEMORY INTERFACE B
A
R301
4.7K
+/-5%
R0402
@M10
4.7K R0402
4.7K R0402
QSB[0..7]
45,48
SCS
46
C
VDD_CORE1.8
R328
4.7K
+/-5%
R0402
@M10
EC27
10uF
12.5V, +/-20%
CTB
@M10
FOR 2.5V VDDR1
MEMVMODE = 1.8V
MEMVMODE1 = GND
FOR 1.8V VDDR1(ELPIDA)
MEMVMODE = GND
MEMVMODE1 = 1.8V
SEE DESIGN GUIDE
D
D
MVREF DIVIDER RESISTORS AND DECOUPLING CAPS
MUST BE PLACED AS CLOSE AS POSSIBLE
TO THE ASIC MVREF BALLS
IT IS IMPORTANT TO HAVE NO
MEMORY SIGNAL TRACE STUBS
FROM THE UNUSED CHANNELS
TECHNOLOGY COPR.
Title
M9/M10-2
Document Number
R ev
661S03
Date:
1
2
3
4
5
6
Friday, August 13, 2004
7
A
Sheet
42
of
8
50
5
4
3
2
1
M9+X<>M10
VDDR1(R4) IS CLKBFB ON M9+X AND IS A NC
R331
0 R0603 @M10
U41F
+3V
DIODE SUPPLIES POWER
U41D
*
*
BC396
22uF
*
BC412
0.1uF
*
BC425
10nF
*
BC362
1nF
CTB
@M10
C0603
@M10
C0402
@M10
C0402
@M10
BC413
0.1uF
BC337
0.1uF
BC422
10nF
BC338
1nF
*
*
*
C0603
@M10
C0603
@M10
C0402
@M10
C0402
@M10
BC364
22uF
BC414
0.1uF
BC421
10nF
BC418
1nF
*
CTB
@M10
*
C0603
@M10
C0402
@M10
*
C0402
@M10
C
M9+X<>M10
VDDR1(D19) IS CLKAFB ON M9+X AND IS A NC
@M10
R263
0 R0603
M9+X<>M10
M9+X IS LVDDR_18_25 AND CONNECTS TO 1.8V
VDDR1
Part 4 of 6
VDDR1(CLKBFB)
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDC
VDDR1
VDDC
VDDR1
VDDC
VDDR1
VDDC
VDDR1
VDDC
VDDR1
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
(VDDC18)VDD15
VDDR1
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR3
VDDR1
VDDR1
VDDR4
VDDR1
VDDR4
VDDR1
VDDR4
VDDR1
VDDR4
VDDR1
VDDR4
VDDR1
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1
VDDP
VDDR1(CLKAFB)
VDDP
VDDR1
VDDP
VDDP
VDDP
M10-P IS LVDDR_25 AND CONNECTS TO 2.5V
R266
R277
0 R0603 @M10
0 R0603 dummy
2
*
D
T7
R4
R1
N8
N7
M4
L27
L8
J24
J23
J8
J7
J4
J1
H10
H13
H15
H17
T8
V4
V7
V8
AA1
AA4
AA7
AA8
A3
A9
A15
A21
A28
B1
B30
D26
D23
D20
D17
D14
D11
D8
D5
E27
F4
G7
G10
G13
G15
G19
G22
G27
H22
H19
AD4
T4
N4
D19
D13
D41
B140
@M10
AC13
AD13
AD15
AC15
AC17
P8
Y8
AC11
AC20
Y23
L23
H20
H11
J30
AF27
AE30
AC27
AC23
AB30
AA24
AA23
Y27
W30
V23
V24
M23
M24
N30
P23
P27
T23
T24
T30
U27
AVSSQ
AD24
LVSSR
LVSSR
LVSSR
LVSSR
AF20
AE19
AE16
AF15
LPVSS
TPVSS
AJ19
AJ12
TXVSSR
TXVSSR
TXVSSR
AH12
AG13
AG14
LPVDD
TPVDD
AF13
AF14
TXVDDR
TXVDDR
VDD_MEM_IO
F18
N6
VDDRH0
VDDRH1
VSSRH0
VSSRH1
F19
M6
VDD_DAC2.5
AG21
AH21
A2VDD
A2VDD
A2VSSN
A2VSSN
AH22
AJ21
A2VDDQ_1.8
AF22
A2VDDQ
A2VSSQ
AF23
AVDD_1.8
AH24
AVDD
AVSSN
AH23
VDDDI_1.8
AE24
AE22
VDD1DI
VDD2DI
VSS1DI
AE23
B
AK28
VDD_PLL1.8
A7
VDD_MEMPLL1.8
I/O POWER
AJ20
AK12
VDD_PNLPLL1.8
PVDD
MPVDD
VSS2DI
AE21
PVSS
AJ28
MPVSS
BC366
22uF
*
CTB
@M10
R292
R300
VCORE_VGA
@M10
0 R0603
0 R0603
dummy
BC383
22uF
*
CTB
@M10
ADD
2
FB L0805 60 Ohm
2
A
BC784
0.1uF
C0402
@M10
FB52
*
BC741
0.1uF
C0402
@M10
*
*
C0603
@M10
BC379
10nF
*
C0402
@M10
BC371
1nF
C0402
@M10
*
BC365
10nF
*
C0402
@M10
BC402
0.1uF
C0603
@M10
M9+X<>M10
M9+X IS VDDC 18 AND CONNECTS TO 1.8V
M10-P IS VDDC15 AND CONNECTS TO 1.5V
DECOUPLING CAPS AS REQUIRED
*
BC332
22uF
*
BC358
0.1uF
*
BC416
10nF
CTB
@M10
C0603
@M10
R297
0 R0603 @M10
*
C0402
@M10
BC411
1nF
*
C0402
@M10
BC344
0.1uF
C0603
@M10
FB26 @M10
2
1
VDDQ
FB L0805 60 Ohm
R298
0 R0603
dummy
VDD_CORE1.8
VDD_CORE1.5
BC392
0.1uF
C0402
@M10
STRAP VDDR4 TO 1.8V FOR EXT TMDS
STRAP VDDR4 TO 3.3V FOR VIP OR ZV_PORT
ALSO SEE DVOMODE STRAPS
*
BC388
0.1uF
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
*
BC333
22uF
CTB
@M10
ADD
*
BC339
22uF
CTB
@M10
*
BC319
0.1uF
C0603
@M10
*
BC318
10nF
C0402
@M10
*
BC706
1nF
C0402
@M10
*
BC320
0.1uF
C0402
@M10
W16
M15
R19
T12
M9+X
(708 BGA)
CENTER
ARRAY
D
FB L0805 80 Ohm
*
BC361
22uF
*
BC345
1nF
*
C0402
@M10
BC375
10nF
*
C0402
@M10
BC403
0.1uF
C
C0603
@M10
VDDQ
+V1.8
FB28 @M10
1
2
FB L0805 60 Ohm
VDD_MEMPLL1.8
*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC770
0.1uF
C0402
@M10
*
BC769
0.1uF
C0402
@M10
FB27 @M10
1
2
U41E
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC
VDDCI
VDDCI
VDDCI
VDDCI
M10-P
(708 BGA)
FB22 @M10
1
2
DECOUPLING CAPS AS REQUIRED
A6
M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
M9+X_M10-P
*
C0603
@M10
A2
A10
A16
A22
A29
C1
C3
C28
C30
D27
D24
D21
D18
D15
D12
D9
D6
D4
F27
G9
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
H9
H8
H4
K30
K27
K24
K23
AG15
AD12
AE27
AG5
AG9
AG11
AG18
AG22
AG27
E4
AB4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Part 6 of 6
CTB
@M10
Part 5 of 6
CORE GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K8
K7
K1
L4
M30
M8
M7
N23
N24
N27
P4
R7
R8
R23
R24
R30
T27
T1
U4
U8
U23
V30
W7
W8
W23
W24
W27
Y4
AA30
AB27
AB24
AB23
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD30
AD25
AD18
AK2
AK29
AJ30
AJ1
D10
D25
FB L0805 60 Ohm
*
BC401
0.1uF
*
C0402
@M10
VDD_CORE1.8
BC408
0.1uF
C0402
@M10
FB53 @M10
1
2
FB L0805 60 Ohm
*
BC378
0.1uF
*
C0402
@M10
FB50
1
VDD_PNLIO1.8
BC380
0.1uF
C0402
@M10
@M10
2
FB L0805 60 Ohm
*
BC342
0.1uF
*
C0402
@M10
VDD_PNLPLL1.8
BC356
0.1uF
FB L0805 60 Ohm
*
BC334
0.1uF
*
C0402
@M10
A2VDDQ_1.8
BC331
0.1uF
C0402
@M10
FB19 @M10
1
2
FB L0805 60 Ohm
*
BC324
0.1uF
*
C0402
@M10
AVDD_1.8
BC328
0.1uF
C0402
@M10
FB17 @M10
1
2
FB L0805 60 Ohm
*
BC323
0.1uF
*
C0402
@M10
VDDDI_1.8
BC322
0.1uF
C0402
@M10
FB18 @M10
1
2
FB L0805 60 Ohm
*
*
BC317
0.1uF
*
C0402
@M10
VDD_PLL1.8
BC316
0.1uF
A
C0402
@M10
@M10
1
FB L0805 60 Ohm
VDD_PNLIO2.5
BC736
0.1uF
C0402
@M10
*
BC742
0.1uF
TECHNOLOGY COPR.
*
Title
C0402
@M10
Document Number
Rev
661S03
Date:
5
B
C0402
@M10
FB20 @M10
1
2
M9+X_M10-P
VDD_DAC2.5
BC735
0.1uF
C0402
@M10
C0402
@M10
BC382
0.1uF
DECOUPLING CAPS AS REQUIRED
*
FB51 @M10
1
FB L0805 60 Ohm
2
VDD_MEM_IO
*
*
C0402
@M10
BC359
1nF
VDD_CORE1.8
PLACED CLOSE TO THE POWER/GND PINS
BC783
0.1uF
C0402
@M10
BC390
10nF
VDD_CORE1.5
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
FB58 @M10
1
*
C0603
@M10
M9+X_M10-P
VDD_MEM2.5
BC400
0.1uF
+3V
AG7
AD9
AC9
AC10
AD10
LVDDR_25(LVDDR18_25)
LVDDR_25(LVDDR18_25)
LVDDR_18
LVDDR_18
VDD_PNLIO1.8
*
ADD
AD7
AD19
AD21
AD22
AC22
AC21
AC19
AC8
AE17
AE20
AE15
AF21
VDD_PNLIO2.5
WHEN VDDC IS OFF AND +3.3V IS ON
1
VDD_MEM_IO
P17
P18
P19
U12
U13
U14
U17
U18
U19
V19
V18
V17
V14
V13
V12
N18
N17
N14
W17
W18
W12
W13
W14
N13
N19
M19
M18
M12
N12
M13
M14
P12
P13
P14
M17
W19
TO VDDC RAIL
4
3
2
A
Sheet
Friday, August 13, 2004
1
43
of
50
4
DQS0
DQS2
MCL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBGA 144
DQS3
DQS1
B13
H13
VREF
N13
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD_MEM_IO
QSA0
QSA1
PLACE CLOSE TO MEMORY
*
C3
C5
C7
C8
C10
C12
E3
E12
F4
G4
J4
K4
F11
G11
J11
K11
EC9
BC721
10uF
0.1uF
12.5V, +/-20%
CTB
C0402
@M10
@M10
*
F3
F2
G3
G2
J3
J2
K2
K3
B3
H3
QSA4
QSA6
R745
1K
+/-1%
R0402
@M10
VDD_MEM_IO
B2
H2
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
B8
C9
B9
B10
C13
D12
D13
E13
MDA63
MDA62
MDA61
MDA60
MDA59
MDA58
MDA57
MDA56
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
F12
F13
G12
G13
J12
J13
K12
K13
MDA47
MDA46
MDA45
MDA44
MDA43
MDA42
MDA41
MDA40
DM0
DM2
DM3
DM1
B12
H12
DQS3
DQS1
B13
H13
VREF
N13
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C3
C5
C7
C8
C10
C12
E3
E12
F4
G4
J4
K4
F11
G11
J11
K11
8M x 32 DDR
DQS0
DQS2
M13
MCL
B4
B11
D4
E6
D6
D9
D10
D11
D5
E9
F5
F10
G5
G10
H5
H10
J5
K5
J10
K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBGA 144
L5
L10
K6
K7
K8
K9
E5
E7
E8
E10
L4
L7
L8
L11
E4
E11
D7
D8
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
L5
L10
K6
K7
K8
K9
E5
E7
E8
E10
B
K4D263238E-GC36
VDD_MEM2.5
CSA1
MAA13
MAA12
CSA0
RASA
CASA
WEA
CKEA
CLKA1
CLKA1#
M5
N4
N2
M2
L2
L3
N12
M11
M12
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
M10
L9
C4
H4
M3
N3
M4
L12
L13
H11
C11
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMA4
DQMA6
R744
1K
+/-1%
R0402
@M10
42,48 MDA[56..63]
MDA[40..47]
42,48
VDD_MEM_IO
DQMA7
DQMA5
R765 C
1K
+/-1%
R0402
@M10
QSA7
QSA5
PLACE CLOSE TO MEMORY
*
EC10
BC758
10uF
0.1uF
12.5V, +/-20%
CTB
C0402
@M10
@M10
*
R772
1K
+/-1%
R0402
@M10
VDD_MEM_IO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B4
B11
D4
E6
D6
D9
D10
D11
D5
E9
F5
F10
G5
G10
H5
H10
J5
K5
J10
K10
DM3
DM1
8M x 32 DDR
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M13
DM0
DM2
42,48 MDA[48..55]
B12 DQMA0
DQMA1
H12
B7
C6
B6
B5
C2
D3
D2
E2
D
L4
L7
L8
L11
E4
E11
D7
D8
B2
H2
42,48
42,48
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
RFU2
RFU3
NC
NC
NC
NC
NC
NC
NC
NC
NC
QSA3
QSA2
C
MDA[8..15]
MDA15
MDA14
MDA13
MDA12
MDA11
MDA10
MDA9
MDA8
MDA[32..39]
BA1
BA0
CS#
RAS#
CAS#
WE#
CKE
CK
CK#
B3
H3
F12
F13
G12
G13
J12
J13
K12
K13
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQMA3
DQMA2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
MDA[0..7]
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
B8
C9
B9
B10
C13
D12
D13
E13
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
F3
F2
G3
G2
J3
J2
K2
K3
RFU2
RFU3
NC
NC
NC
NC
NC
NC
NC
NC
NC
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BA1
BA0
CS#
RAS#
CAS#
WE#
CKE
CK
CK#
A0
A1
A2
A3
A4
A5
A6
A7
A8_AP
A9
A10
A11
42,48
B7
C6
B6
B5
C2
D3
D2
E2
1
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
U42
@M10
MDA[24..31] 42,48
MDA31
MDA30
MDA29
MDA28
MDA27
MDA26
MDA25
MDA24
CSA1
A0
A1
A2
A3
A4
A5
A6
A7
A8_AP
A9
A10
A11
CSA1
CSA1
42,48
2
42
CLKA1#
42
CLKA1
42,48
CKEA
42,48
WEA
42,48
CASA
42,48
RASA
42,48
CSA0
M10
L9
C4
H4
M3
N3
M4
L12
L13
H11
C11
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
U16
@M10
3
42
MAA13
MAA12
CSA0
RASA
CASA
WEA
CKEA
CLKA0
CLKA0#
42,48
D
CLKA0#
M5
N4
N2
M2
L2
L3
N12
M11
M12
MDA[16..23]
CLKA0
CKEA
WEA
CASA
RASA
CSA0
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
42
42,48
42,48
42,48
42,48
42,48
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
5
B
K4D263238E-GC36
VDD_MEM2.5
VDD_MEM_IO
VDD_MEM2.5
VDD_MEM_IO
VDD_MEM2.5
42,48 QSA[0..7]
42,48 DQMA[0..7]
*
A
EC14
10uF
12.5V, +/-20%
CTB
@M10
*
BC694
1nF
C0402
@M10
*
BC693
10nF
C0402
@M10
*
BC394
0.1uF
C0402
@M10
*
BC397
1uF
C0603
@M10
*
BC386
1nF
C0402
@M10
*
BC381
10nF
BC374
0.1uF
C0402
@M10
C0402
@M10
*
*
EC26
10uF
12.5V, +/-20%
CTB
@M10
*
EC8
10uF
12.5V, +/-20%
CTB
@M10
*
BC395
10nF
BC393
1nF
C0402
@M10
C0402
@M10
*
*
BC691
0.1uF
C0402
@M10
*
BC689
1uF
C0603
@M10
*
BC703
10nF
C0402
@M10
*
BC696
1nF
C0402
@M10
*
BC700
0.1uF
C0402
@M10
*
EC12
10uF
12.5V, +/-20%
CTB
@M10
42,48 MAA[0..13]
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
44
of
50
DQS0
DQS2
MCL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DM3
DM1
B12
H12
DQMB3
DQMB1
DQS3
DQS1
B13
H13
QSB3
QSB1
VREF
N13
42,48
MDB[8..15]
MDB[32..39]
VDD_MEM_IO
*
EC17
BC791
10uF
0.1uF
12.5V, +/-20%
CTB
C0402
@M10
@M10
*
MAB13
MAB12
CSB0
RASB
CASB
WEB
CKEB
CLKB1
CLKB1#
M5
N4
N2
M2
L2
L3
N12
M11
M12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
F3
F2
G3
G2
J3
J2
K2
K3
B3
H3
DQMB6
DQMB4
R857
1K
+/-1%
R0402
@M10
PLACE CLOSE TO MEMORY
C3
C5
C7
C8
C10
C12
E3
E12
F4
G4
J4
K4
F11
G11
J11
K11
42,48
B7
C6
B6
B5
C2
D3
D2
E2
QSB6
QSB4
R856
1K
+/-1%
R0402
@M10
VDD_MEM_IO
B2
H2
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
B8
C9
B9
B10
C13
D12
D13
E13
MDB63
MDB62
MDB61
MDB60
MDB59
MDB58
MDB57
MDB56
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
F12
F13
G12
G13
J12
J13
K12
K13
MDB47
MDB46
MDB45
MDB44
MDB43
MDB42
MDB41
MDB40
DM0
DM2
DM3
DM1
B12
H12
DQS3
DQS1
B13
H13
VREF
N13
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C3
C5
C7
C8
C10
C12
E3
E12
F4
G4
J4
K4
F11
G11
J11
K11
8M x 32 DDR
DQS0
DQS2
M13
MCL
B4
B11
D4
E6
D6
D9
D10
D11
D5
E9
F5
F10
G5
G10
H5
H10
J5
K5
J10
K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBGA 144
L5
L10
K6
K7
K8
K9
E5
E7
E8
E10
L4
L7
L8
L11
E4
E11
D7
D8
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
B
K4D263238E-GC36
VDD_MEM2.5
RFU2
RFU3
NC
NC
NC
NC
NC
NC
NC
NC
NC
MDB15
MDB14
MDB13
MDB12
MDB11
MDB10
MDB9
MDB8
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
BA1
BA0
CS#
RAS#
CAS#
WE#
CKE
CK
CK#
F12
F13
G12
G13
J12
J13
K12
K13
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
L5
L10
K6
K7
K8
K9
E5
E7
E8
E10
CSB1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
CSB1
FBGA 144
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
42,48 MDB[48..55]
MDB[40..47]
42,48
VDD_MEM_IO
DQMB7
DQMB5
R354 C
1K
+/-1%
R0402
@M10
QSB7
QSB5
PLACE CLOSE TO MEMORY
*
EC31
BC469
10uF
0.1uF
12.5V, +/-20%
CTB
C0402
@M10
@M10
*
R356
1K
+/-1%
R0402
@M10
VDD_MEM_IO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B4
B11
D4
E6
D6
D9
D10
D11
D5
E9
F5
F10
G5
G10
H5
H10
J5
K5
J10
K10
8M x 32 DDR
MDB31
MDB30
MDB29
MDB28
MDB27
MDB26
MDB25
MDB24
L4
L7
L8
L11
E4
E11
D7
D8
M13
DM0
DM2
B8
C9
B9
B10
C13
D12
D13
E13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B3
H3
D
42,48 MDB[56..63]
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
DQMB0
DQMB2
1
CLKB1#
CLKB1
CKEB
WEB
CASB
A0
A1
A2
A3
A4
A5
A6
A7
A8_AP
A9
A10
A11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
B2
H2
U27
@M10
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
F3
F2
G3
G2
J3
J2
K2
K3
RFU2
RFU3
NC
NC
NC
NC
NC
NC
NC
NC
NC
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
QSB0
QSB2
M10
L9
C4
H4
M3
N3
M4
L12
L13
H11
C11
MAB13
MAB12
CSB0
RASB
CASB
WEB
CKEB
CLKB0
CLKB0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BA1
BA0
CS#
RAS#
CAS#
WE#
CKE
CK
CK#
B7
C6
B6
B5
C2
D3
D2
E2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C
A0
A1
A2
A3
A4
A5
A6
A7
A8_AP
A9
A10
A11
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
42
42
42,48
RASB 42,48
CSB0 42,48
42,48
42,48
CSB1
CSB1
42,48 MDB[24..31]
42,48
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MDB[0..7]
M5
N4
N2
M2
L2
L3
N12
M11
M12
U44
@M10
42,48
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
D
2
42,48 MDB[16..23]
RASB
CSB0
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
42,48
42,48
3
CLKB0#
CLKB0
CKEB
WEB
CASB
M10
L9
C4
H4
M3
N3
M4
L12
L13
H11
C11
4
42
42
42,48
42,48
42,48
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
5
B
K4D263238E-GC36
VDD_MEM2.5
42,48 DQMB[0..7]
VDD_MEM_IO
VDD_MEM2.5
VDD_MEM_IO
42,48 MAB[0..13]
VDD_MEM2.5
42,48 QSB[0..7]
*
A
EC22
10uF
12.5V, +/-20%
CTB
@M10
*
BC475
1nF
C0402
@M10
*
BC479
10nF
C0402
@M10
*
BC482
0.1uF
C0402
@M10
*
BC470
1uF
C0603
@M10
*
BC472
1nF
C0402
@M10
*
BC473
10nF
BC474
0.1uF
C0402
@M10
C0402
@M10
*
*
EC21
10uF
12.5V, +/-20%
CTB
@M10
*
EC33
10uF
12.5V, +/-20%
CTB
@M10
*
BC816
10nF
BC814
1nF
C0402
@M10
C0402
@M10
*
*
BC812
0.1uF
C0402
@M10
*
BC810
1uF
C0603
@M10
*
BC821
10nF
C0402
@M10
*
BC815
1nF
C0402
@M10
*
BC824
0.1uF
C0402
@M10
*
EC32
10uF
12.5V, +/-20%
CTB
@M10
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Monday, August 16, 2004
A
Sheet
1
45
of
50
5
4
OTHER OPTION STRAPS ARE AVAILABLE IF REQUIRED
SEE DESIGN GUIDE
41
GPIO0
R832
R0402
10K
+/-1%
41
GPIO1
R828
R0402
10K
+/-1%
GPIO2
R834
R0402
10K
+/-1%
R835
R0402
10K
+/-1%
3
2
1
+3V
GPIO1
GPIO0 AGP 1X CLOCK FEEDBACK PHASE ADJUST WITH RESPECT TO REFCLK
DNI
DNI
REFCLK SLIGHTLY EARLIER THAN FEEDBACK
(DEFAULT)
D
D
41
GPIO3
41
ROM_ID1
R843
R0402
10K
+/-1%
41
ROM_ID2
R840
R0402
10K
+/-1%
41
ROM_ID3
R842
R0402
10K
+/-1%
41
ROM_ID4
R844
R0402
10K
+/-1%
GPIO3
GPIO2
DNI
CLOCK PHASE ADJUSTMENT BETWEEN X1 AND X2 CLK
ROM_ID4 ROM_ID3
ROM_ID2
DNI
DNI
DNI
DNI
10K
DNI
10K
10K
DNI
10K
10K
10K
10K
10K
10K
10K
(DEFAULT)
0 TAP DELAY
DNI
ROM
NO ROM
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
ROM_ID1
DNI
10K
DNI
10K
DNI
10K
DNI
10K
DNI
DNI
DNI
10K
DNI
DNI
10K
10K
ID CONFIG
(DEFAULT)
AT25F1024 (ATMEL) ROM
AT2545DB011 (ATMEL) ROM
M25P10 ( ST) ROM
M25P05 ( ST) ROM
SST45LF010 ( SST) ROM
SST25VF010 ( SST) ROM
NX25F011B (NEXFLASH) ROM
*
R243
20K
+/-5%
R0402
C
10,13,14,19 SMBCLK
10,13,14,19 SMBDAT
R845
0
+/-5%
R0402
Dummy
OPTIONAL SERIAL FLASH EEPROM
9,41
FOR VIDEO BIOS OUTSIDE SYSTEM BIOS
INT-B
OPTIONAL OC
INTERRUPT ALERT
PLUS PU TO AGP
U23
41
SIN
41
SCLK
42
SCS
S IN
5
D
SCLK
6
C
SCS
1
S
R332
R0402
0
+/-5%
+3V
*
BC456
0.1uF
16V, X7R, +/-10%
C0402
7
HOLD
3
W
8
Q
SOUT
2
SOUT
R240
0
1%
R0402
R241
0
1%
R0402
R242
R0402
41
0
+/-5%
BC335
0.1uF
16V, X7R, +/-10%
+3V
C0402
C
U17
8
SCLK
7
6
5
GND
BC336
C0402
2.2nF
50V. X7R, +/-10%
*
41
VDD
1
SDATA
D+
2
D+
41
ALERT
D-
3
D-
41
THERM
4
ADM1032A
EXTERNAL THERMAL SENSOR
TYPE 1
VCC
VSS
4
M25P10-A
B
B
VDDQ
Ra
AGP_TEST RESISTOR SELECTION
AGPREF/VREFGC RESISTOR SELECTION
R219
324
+/-1%
R0603
[email protected]
AGPREF
AGP MODE
Rc
AGP 2.0 (4X)
49.9R 1%
AGP 3.0 (8X)
169R1%
VDDQ
R718
R0603
R720
R0402
Rc
AGP MODE
Ra
Rb
AGP 2.0 (4X) .75V
1.02K1%
1.02K1%
AGP 3.0 (8X) .35V
324R1%
100R1%
Rb
169 [email protected]
+/-1%
45.3
+/-1%
AGP_TEST
41
5,41
FOR M10 AND M9 AGP3.0 OR AGP2.0 IT IS NOW RECOMMENDED
R226
BC303
100
10nF TO USE LOCALLY GENERATED VREF FOR GRAPHICS CONTROLLER (AGPREF)
+/-1%
16V, X7R, +/-10%
R0603
C0402
AND OFF BOARD GENERATED VREF FOR MOTHERBOARD CHIPSET
[email protected]
*
M9 <> M10
ON M9 AGPTEST IS PULLED DOWN
ON M9+ AND M10 AGPTEST IS PULLED UP TO VDDP
A
A
TECHNOLOGY COPR.
Title
Document Number
R ev
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
46
of
50
5
4
3
2
1
+3V
BC448
22uF
6.3V, Y5V, +80%/-20%
C1206
@M10
D
*
U43
1
R334
1K
+/-1%
R0402
@M10 3
VDD_MEM_IO
R333
1K
+/-1%
R0402
@M10
@M10
VIN
VCNTL1
VCNTL2
VCNTL3
VCNTL4
8
7
6
5
VOUT
4
GND
2
REFEN
D
+VTT
RT9173B
*
R353
1K
+/-1%
R0402
@M10
EC28
330uF
CTX
@M10
C
C
@M10
41
41
R0402 R729
R728
R0402
X1
X2
0 +/-5%
0
+/-5%
@M10
R0402
XTAL-27MHz
1
+/-5%
2
X8
@M10
0
R716
@M10
BC697
C0402
@M10
BC695
C0402
*
B
@M10
22pF
50V, NPO, +/-5%
R707
1M
+/-5%
R0402
*
B
22pF
50V, NPO, +/-5%
@M10
A
A
TECHNOLOGY COPR.
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
47
of
50
5
4
3
+VTT
MDA1
MDA4
MDA3
MDA7
MDA5
MDA6
MDA2
MDA0
DQMA0
D
MDA11
MDA10
MDA9
MDA12
MDA8
MDA13
MDA15
MDA14
DQMA1
MDA16
MDA17
MDA19
MDA18
MDA20
MDA22
MDA23
MDA21
DQMA2
C
MDA25
MDA27
MDA28
MDA24
MDA31
MDA26
MDA29
MDA30
DQMA3
42,44
RASA
B
42,44
42,44
42,44
CASA
CKEA
CSA0
42,44
WEA
42,44
CSA1
RASA
MAA11
MAA8
MAA3
MAA0
CASA
CKEA
CSA0
MAA6
MAA7
MAA12
WEA
MAA9
MAA10
MAA5
MAA4
MAA13
CSA1
MAA1
MAA2
R198
R683
R685
R214
R210
R690
R199
R197
R684
R225
R709
R717
R704
R712
R216
R695
R700
R218
R217
R711
R708
R220
R231
R733
R237
R724
R224
R215
R693
R206
R701
R196
R696
R687
R686
R213
R766
R748
R755
R759
R761
R770
R753
R764
R757
R756
R762
R264
R747
R750
R746
R758
R751
R763
R760
R749
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
*
BC716
0.1uF
C0402
@M10
*
BC807
0.1uF
C0402
@M10
*
BC842
0.1uF
C0402
@M10
*
BC512
0.1uF
C0402
@M10
*
BC511
0.1uF
C0402
@M10
*
BC505
0.1uF
C0402
@M10
*
BC501
0.1uF
C0402
@M10
*
BC813
0.1uF
C0402
@M10
*
+VTT
MDA32
MDA33
MDA35
MDA34
MDA36
MDA38
MDA37
MDA39
DQMA4
BC843
0.1uF
C0402
@M10
*
MDA40
MDA41
MDA47
MDA42
MDA43
MDA44
MDA45
MDA46
DQMA5
MDA50
MDA51
MDA48
MDA49
MDA55
MDA54
MDA52
MDA53
DQMA6
MDA63
MDA62
MDA61
MDA58
MDA56
MDA57
MDA60
MDA59
DQMA7
R814
R816
R817
R815
R802
R796
R295
R790
R818
R774
R267
R287
R776
R278
R783
R786
R285
R281
R286
R782
R289
R784
R265
R773
R276
R775
R279
R813
R812
R811
R291
R792
R799
R810
R804
R809
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
BC790
0.1uF
C0402
@M10
*
BC795
0.1uF
C0402
@M10
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
*
BC464
0.1uF
C0402
@M10
*
BC499
0.1uF
C0402
@M10
*
BC495
0.1uF
C0402
@M10
*
BC822
0.1uF
C0402
@M10
*
BC676
0.1uF
C0402
@M10
*
BC811
0.1uF
C0402
@M10
*
BC827
0.1uF
C0402
@M10
42,45
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
R200
R222
R715
R688
R819
R780
R777
R808
180
180
180
180
180
180
180
180
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
1
+VTT
MDB6
MDB5
MDB4
MDB3
MDB1
MDB2
MDB0
MDB7
DQMB0
BC465
0.1uF
C0402
@M10
*
42,45
BC789
0.1uF
C0402
@M10
*
2
MDB15
MDB13
MDB12
MDB14
MDB11
MDB10
MDB8
MDB9
DQMB1
MDB19
MDB17
MDB16
MDB18
MDB20
MDB21
MDB23
MDB22
DQMB2
MDB29
MDB31
MDB26
MDB24
MDB28
MDB30
MDB25
MDB27
DQMB3
42,45
CSB0
WEB
42,45
RASB
CKEB
42,45
CSB1
42,45
CASB
MAB12
CSB0
MAB2
WEB
RASB
MAB5
MAB13
MAB8
MAB11
MAB4
MAB10
MAB9
CKEB
MAB1
CSB1
MAB3
MAB6
MAB0
MAB7
CASB
R916
R410
R915
R903
R894
R899
R888
R917
R908
R351
R350
R852
R851
R348
R854
R855
R347
R349
R919
R918
R409
R408
R406
R921
R405
R922
R407
R881
R873
R352
R850
R868
R870
R849
R848
R860
R900
R399
R877
R909
R398
R884
R897
R369
R895
R377
R883
R889
R361
R901
R904
R379
R371
R890
R876
R397
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
*
42,45 MDB[0..63]
MDB38
MDB39
MDB36
MDB37
MDB33
MDB34
MDB32
MDB35
DQMB4
BC779
0.1uF
C0402
@M10
*
BC780
0.1uF
C0402
@M10
*
BC743
0.1uF
C0402
@M10
*
BC744
0.1uF
C0402
@M10
*
BC745
0.1uF
C0402
@M10
*
BC737
0.1uF
C0402
@M10
*
BC781
0.1uF
C0402
@M10
*
BC782
0.1uF
C0402
@M10
*
BC282
0.1uF
C0402
@M10
*
BC718
0.1uF
C0402
@M10
*
BC722
0.1uF
C0402
@M10
*
BC730
0.1uF
C0402
@M10
42,44 QSA[0..7]
42,44 MDA[0..63]
+VTT
42,44 MAA[0..13]
42,45 MAB[0..13]
MDB43
MDB41
MDB40
MDB42
MDB47
MDB45
MDB46
MDB44
DQMB5
MDB48
MDB49
MDB50
MDB51
MDB53
MDB55
MDB54
MDB52
DQMB6
MDB61
MDB62
MDB60
MDB63
MDB57
MDB59
MDB56
MDB58
DQMB7
R404
R396
R911
R403
R400
R402
R910
R401
R913
121
121
121
121
121
121
121
121
121
R346
R336
R337
R335
R869
R867
R342
R343
R344
121
121
121
121
121
121
121
121
121
R885
R378
R893
R380
R386
R907
R389
R902
R898
121
121
121
121
121
121
121
121
121
R366
R370
R360
R372
R340
R339
R341
R859
R872
121
121
121
121
121
121
121
121
121
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
*
BC677
0.1uF
C0402
@M10
*
BC283
0.1uF
C0402
@M10
*
BC777
0.1uF
C0402
@M10
*
BC775
0.1uF
C0402
@M10
*
BC710
0.1uF
C0402
@M10
*
BC727
0.1uF
C0402
@M10
*
BC487
0.1uF
C0402
@M10
*
BC491
0.1uF
C0402
@M10
D
C
B
@M10
@M10
@M10
@M10
@M10
@M10
@M10
@M10
R914
R853
R920
R847
R912
R345
R384
R338
180
180
180
180
180
180
180
180
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0603
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
A
A
42,44 DQMA[0..7]
42,45 DQMB[0..7]
TECHNOLOGY COPR.
42,45 QSB[0..7]
Title
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
48
of
50
5
4
3
2
1
D
D
VIN
*
BC341
10uF
*
C1210
@M10
BC340
10uF
*
C1210
@M10
BC243
10uF
*
C1210
@M10
BC244
10uF
C1210
@M10
1
1
+5V
D39
RB751V-40
@M10
*
U14 @M10
5
UGATE1
UGATE2
24
6
BOOT1
BOOT2
23
7
ISEN1
ISEN2
22
TC7
220uF
CTX
@M10
*
TC3
220uF
CTX
@M10
R721
17.8k
+/-1%
R0603
@M10
*
BC704
10nF
C0402
@M10
R230
10K
+/-1%
R0402
@M10
R722
0
+/-5%
R0402
dummy
R227
124K
+/-1%
R0603
@M10
R229
0
+/-5%
R0402
@M10
21
VOUT2
20
10
VSEN1
VSEN2
19
11
OCSET1
OCSET2
18
SOFT2
17
R723
1K
R0402
+/-5%
SOFT1
13
DDR
14
VIN
BC310
10nF
C0402
@M10
VIN
5
6
7
C
PG2/REF
16
PG1
15
+/-1%
L18
4.7uH
*
R0603
@M10
SHORT2
@M10
4
EN2
VOUT1
+V1.8
1.8V 3A
@M10
EN1
12
+V1.8_BF
R192 750
9
ISL6227CA
*
Q14
8
22m Ohms
*
FDS6982S
3
4
3
25
G1
2
PHASE2
S1
1
PHASE1
G2
*
26
4
S2
G1
S1
27
PGND2
8
5
@M10 R232 1.02K
+/-1% R0603
G2
FDS6982S
Q18
@M10
S2
4.7uH @M10
LGATE2
PGND1
D1
L19
LGATE1
3
BC276
0.1uF
25V, X7R, +/-10%
C0603
@M10
D1
SHORT3
VCC
2
*
D2
4A
C
GND
28
D2
D1
D1
D2
D2
2.5V
6
VDD_MEM2.5_BF
VDD_MEM2.5
7
8
@M10
1
2
*
1
BC309
@M10
0.1uF
25V, X7R, +/-10%
C0603
BC275
4.7uF
6.3V, X5R, +/-10%
C0805
@M10
2
2
D40
RB751V-40
22m Ohms
*
R676
0
+/-5%
R0402
dummy
*
BC277
10nF
25V, X7R, +/-10%
C0402
R674
@M10
124K
+/-1%
R0603
@M10
BC273
10nF
C0402
@M10
R194
0
+/-5%
R0402
@M10
*
R675
10K
+/-1%
R0402
@M10
*
TC2
220uF
CTX
@M10
TC4
220uF
CTX
@M10
R187
10K
+/-1%
R0402
@M10
@M10
+5VSUS
R678 1K
@M10
Vo_2.5V=0.9(R245+R296)/R296
+5VSUS
R228
10K
+/-5%
R0402
dummy
R231=Ioc*Rds(on)max/75uA-0.14K
R623=10.3V/(75uA+8uA)=124K
R0402 +/-5%
Vo_1.8V=0.9(R625+R299)/R299
R193
10K
+/-5%
R0402
dummy
B
R232=Ioc*Rds(on)max/75uA-0.14K
B
R624=10.3V*/(75uA+8uA)=124K
Soft start time from Enable
to Power good indicate
Tsoft=1.5V*Csoft/5uA=3mS
DDR
EN1
EN2
0
1
1
PIN14
Phase
4.2V<VIN<24V
180 degree
A
A
TECHNOLOGY COPR.
Title
2.5V & 1.8V FOR M10
Document Number
Rev
661S03
Date:
5
4
3
2
A
Sheet
Friday, August 13, 2004
1
49
of
50
4
D
P=1/4 W
1
3
R15
R1206
10
+/-5%
R16
2.2K
+/-5%
R0402
2
MBATA+
C
Battery
3S2P 10.8V
C0603
16V,X7R,+/-20%
0.1uF
BC546
BAT54C
MOSVCC
BC545
0.1uF
16V,X7R,+/-20%
C0603
*
R
A
Vref= 2.5V
U1
LM431ACM3
R17
1K
+/-5%
R0402
1
8V
D
1
ADIN
+/-5%
R1206
2
D3
P=1/4 W
R14
10
2
1
Adapter
19V DC, 3.96A, 65W
3
2
5
BC14
1uF
16V, X7R, +/-10%
C0805
Vout=Vref*(1+R1/R2)
+3VALW
2
ERROR
3
SD
packing SOT-89
Ic=3A>>150mA
R0402 +/-5%
0
TAP
+3VALW_591
R0402 +/-5%
R552
3.4K
+/-1%
R0603
6
MIC2951
1
B320B
R554
1
VOUT
2
D5
*
BC590
100pF
C0402
R547 1K
B
1
MBATA+
2SB1424
C
5
4
Q6
E
C
2
U5
R6=(19-5.9)/0.15=87Ohm
BC587
0.1uF
16V,X7R,+/-20%
C0603
8
150
+/-5%
D6
B320B
2
D25
2
R542
R0603
1
B320B
VIN
150
+/-5%
SNS
R541
R0603
FB
BC585
0.1uF
16V,X7R,+/-20%
C0603
7
2
1
ADIN
GND
C
1
DC Working Peak Reserve 20V
*
BC591
3.3uF
VOUT=3.3V
TO-92 Packing
Output 3.3V 150mA current
C0805
change 4.7 UF 0805 footprint
control by BOM
lonny -080504
SOP8 PACKING VREF=1.23V
Pin 2 sense VOUT=VREF*(1+R1/R2)
pin 6 5V TAP
R551
2K
+/-1%
R0603
R550
54.9
+/-1%
R0402
R954=(9-0.2-0.6)/0.15=54.9 Ohm
B
15,18
NBSWONJ
B
NBSWONJ
VINT
VIN
D
1
2
3
4
1K
G
R59
S
Q9
FDS4435
8
7
6
5
C
R0402 +/-5%
R582 1K
Q55
MMBT3904
R0402 +/-5%
R577
1K
R0402
+/-5%
E
B
15,34 3VAUX_EN
update sch VINT for save power only battery mode lonny update
2004/07/17
A
A
TECHNOLOGY COPR.
Title
SAVE POWER
Document Number
Re v
661S03
Date:
5
4
3
2
Friday, August 13, 2004
A
Sheet
1
50
of
50