Sub-20nm Logic Lithography Optimization with

Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite™
Michael C. Smayling*a, Koichiro Tsujitab, Hidetami Yaegashic, Valery Axelradd
Tadashi Araib, Kenichi Oyamac, Arisa Harac
a
Tela Innovations, Inc., 485 Alberto Way, Suite 115, Los Gatos, CA, USA 95032
b
Canon, Inc., 20-2, Kiyohara-Kogyodanchi, Utsunomiya-shi, Tochigi, Japan 321-3292
c
Tokyo Electron, Ltd., 650 Mitsuzawa, Hosaka-cho, Nirasaki City, Yamanashi, Japan 407-0192
d
Sequoia Design Systems, Inc., 137 Chapman Rd., Woodside, CA USA 94062
ABSTRACT
The CMOS logic 22nm node is being done with single patterning and a highly regular layout style
using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but
with multiple patterning for critical layers. A “lines & cuts” approach is being used to achieve good
pattern fidelity and process margin, with extendibility to ~7nm.[1]
In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be
effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases
triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the
need for multiple-patterning compared to complex layouts.
To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple
OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant
since mask data volumes of >500GB per layer are projected for pixelated masks created by complex
OPC or inverse lithography; writing times for such masks are nearly prohibitive.
In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMO
Lite™” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y”
locations for the cuts scaled for each node. The test block is a reasonably complex logic function
with ~100k gates of combinatorial logic and flip-flops.
Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole
pitch division process to create a grid template combined with a relatively large “selection” pattern
to create cuts at the desired grid locations.
Experimental demonstration of the cut approach using SMO Lite™ and a grid template will be
presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the
gate pitch at the 10nm node.
Keywords: Low k1, highly regular layout, gridded design rules, pitch division, spacer double
patterning, lines and cuts, design source mask optimization (DSMO)
*[email protected]; phone +1 408 558-6321; fax +1 408 354-4900
1. INTRODUCTION
The >50 year era of continual improvement in photolithography optical resolution came to an abrupt
end in 2007. The end of optical resolution scaling would have come several years sooner without the
rapid introduction of immersion lithography which extended the roadmap.[10]
Even with equipment improvements, k1 has been decreasing for recent logic technology nodes. (k1 is
the fitting factor in the Rayleigh equation half-pitch = k1 /NA.) To maintain pattern fidelity at k1
values below ~0.6, resolution enhancement techniques (RET) such as optical proximity correction
(OPC), off-axis illumination (OAI), and phase shift masks (PSM) have been introduced.
For k1 < 0.35, more regular layout has been used to achieve good pattern fidelity.[11,12,13,14]
These regular patterns can be decomposed into “lines” and “cuts” to permit independent
optimization of each part of the pattern. However, as shown in Figure 1, even for line patterns, pitch
division will eventually be necessary. The cut and hole layers will eventually require multiple
patterning, with the transition occurring at different nodes for different design layers.
Figure 1. Metal-1 pitch for sub-22nm logic technology nodes.
Pitch division can be done by multiple exposures, for example litho-etch-litho-etch (LELE), or
through self-aligned processes such as spacer-double-patterning (SDP) or directed self-assembly
(DSA). Of these candidates, SDP has been in volume production for several years and is currently
being used in 2x-nm and 1x-nm memory products. For SDP, the initial line pattern can be done with
dry or immersion optical lithography depending on the pattern pitch. LELE has not been adopted
due to alignment requirements and etch CD requirements.
The “cut” pattern can be done optically with single exposures down to ~16nm, while multiple
exposures will be needed for smaller nodes. E-beam direct-write is also a candidate for exposing the
cut patterns, since the pattern density is relatively low, but today’s single column systems do not
have sufficient throughput for high volume manufacturing. Multiple-beam systems appear feasible
and could become an alternative to multiple optical exposures at the right cost / throughput point.
2. MODELING AND SIMULATION
The approach taken for “cut” simulation has been previously described for work done at 20nm and
16nm.[6,7] Using the Canon extensions to Sequoia Cell Designer (SCD) for SMO-Lite™, the
DSMO is done globally on a representative set of layout cells use in an SOC. Local corrections can
then be applied on full block layouts using SMO-Lite™.
Simulations were carried out on cells from a logic block at the 11nm node. The metal-1 pitches were
in a conventional 7:9 ratio with the gate pitches. The “cut” patterns had been previously run through
DSMO at 20nm, but were further optimized for 11nm. Different optimization was used for the
gridded template case and the double patterning case.
The logic block test case is shown in Figure 2. The logic block contains ~100k CMOS transistors
designed from standard cells and built by a conventional place-and-route design flow.
Figure 2. Logic block with simulation window highlighted.
For the template approach, pitch division was used to get a cut pattern grid with a 28nm half-pitch as
shown in Figure 3a. The cut locations in the design were adjusted to fit the grid. A typical cut
selection pattern is shown in Figure 3b.
Figure 3. a. Cut pattern grid after pitch division.
b. Cut selection pattern.
The selection pattern layout overlaid on a portion of the block layout is shown below in Figure 4. In
this region, the selected cuts tended to fall along diagonal shapes.
Figure 4. Cut selection overlaid on the design grid.
Simulations were done for the cut selection pattern using annular illumination, a dose variation of
±5%, a mask edge placement of ±0.5nm, and a defocus of 0 to 50nm. OPC was done with the
Sequoia Design Systems Cell Designer. The PV bands are shown in Figure 5. Since the final cut is a
combination of the cut grid and the selection mask, regions with resist remaining in non-grid areas
will not cause an undesired cut.
Figure 5. Cut selection PV bands.
For the cut double patterning approach, dipole illumination was used. The PV bands covered dose
variation of ±5%, mask edge placement of ±0.5nm, and defocus of 0 to 30nm. A 193i scanner with
NA=1.30 was used with a 6% attenuated phase shift mask.
The initial layout could not be patterned with double patterning; triple patterning was required as
shown in Figure 6. The PV bands showed all three exposures had sufficient margin. However, this
solution required an additional cut patterning step compared to our target of only two cut patterns.
Figure 6. Cut pattern triple patterning coloring.
As the term DSMO implies, the design is also part of the optimization process. The standard cells
layouts were “polished” in troublesome locations. The improved layout was successfully colored
with only two patterns as shown in Figure 7. The worst case NILS was 0.85 over the process space.
Figure 7. Cut pattern double patterning coloring.
The shapes produced by the OPC step were simple rectangles. This approach has previously been
shown to improve MEEF and has the potential to reduce mask cost.[6,7] Post patterning shrink was
used to get to the final cut size of 16 x 40nm.
3. EXPERIMENTAL RESULTS
Wafers were processed at the TEL research facilities, including patterning, deposition, etch, and
metrology. Line patterns were created with 80nm pitch and reduced to 40nm pitch using SDP. The
sequence of deposition and etching for SDP is well described in the literature.[8,9] The grid pattern
was printed at 40nm half-pitch, then reduced to 28 nm half-pitch and finally 20nm half-pitch.
A 6% attenuated phase-shift mask (aPSM) with the design space previously described was used for
the experimental work. Detailed mask measurements are not available to confirm MEEF; however,
since simplified OPC was used, the mask complexity was relatively modest.
For the template approach, cut selection exposures were done using a conventional light source with
an annular illuminator; no custom illuminator using optical diffractive elements (ODE) or pixelated
illuminator were used. The numerical aperture (NA) was set to 1.30 with no polarization. The
sequence of steps from lines to finished pattern is shown in Figure 8.
Figure 8. Process sequence for template approach to cut patterning. (final etched lines on the right)
The wafer results for this process sequence are shown in Figure 9. The resist pattern is not simple,
with many diagonal sections, but was resolved with the good fidelity shown. The cuts after etch are
on-grid as expected and reflect the uniformity of the self-aligned process used to form the template.
Figure 9. Cut selection pattern resist (left) and final etched line pattern (right).
The wafer results for the cut LELE double patterning are shown below in Figure 10. The post-etch
results show good separation of line segments. In cuts spanning multiple lines, the cut width is
slightly larger but within limits set by alignment tolerances. The line half-pitch is 20nm, representing
the Gate layer at the 10nm node and the Metal-1 layer at the 12nm node.
Figure 10. Cut pattern by LELE.
The LELE exposure used an X-dipole illumination with Y-polarization. The post-OPC cut shapes
were simple rectangles with dimensions adjusted to achieve the final CD targets.
4. CONCLUSIONS
The application of the 1D gridded design style has been extended to beyond the 12nm CMOS logic
node. Two different approaches have been demonstrated to achieve the patterning of the cuts. Both
the template approach and the LELE double patterning approach for cuts were successful. The cut
patterns used in each case were tuned for that approach; however, the circuit functions were the
same. For the template case, the design was revised to avoid triple patterning and allow double
patterning with a good process window.
We would like to thank the staff at TEL for the lengthy effort needed to fabricate and analyze the
wafers; the staff at Canon for mask design, simulations, and analysis; Sequoia Design Systems for
the use of Sequoia Cell Designer with enhancements, and Tela Innovations for their help in creating
the design space. We appreciate the continued support of our executive management.
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2