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The SAD-1024
SerialAnalogDelaydevicefabricatedusingN-channelsiliconis a general-purpose
gate technology
in a bucket-brigade
configuration
to obtainflexibleperformance
at low cost.
K E Y F EA T U RE S :
TYPICALAPPLICATIONS:
o Two independent512-stagedelay sections.
o Clock-controlleddelay: 0.5 sec to less than
20Ogsec.
o N-channelsilicon-gate buckel-brigade
technology.
o Designed for self-cancellation of clocking
modulation.
o Wide signal-frequencyrange: 0 to more than
200KHz.
o Wide sampling clock lrequency range: 1.SKHz
to more than 1.5MHz.
o Wide dynamic range: S/N > 70db.
r Low distortion: less lhan 1ol0.
o Low noise: typically limited by output amplifier.
o Single 15 volt power supply.
a
a
a
a
o
a
Voice control of tape recorders.
Variablesignalcontrolol amplitudeor ol
lilters.
equalization
Reverberation
effectsin stereoequipment.
Tremolo,vibrato,or chorus eflects in electronic
musicalinstruments.
Variableor fixed delayof analogsignals.
Time compressionof telephoneconversalions
or olher analogsignals.
Voicescramblingsyslems.
D E V I C ED E S C R I P T I O N
The SAD-1024is a dual 512-stageBucket-Brigade
D e v i c e( B B D ) .E a c h 5 1 2 - s t a g es e c t i o ni s i n d e p e n dent as to input, output, and clock. The sections
may be used independently,may be multiplexedto
give an increased effective sample rate, may be
connected in series to give increased delay at a
fixed samplerate,or may be operatedin a differential modefor reducedeven-harmonicdistortionand
reducedclocking noise. Each section has its output split into two channelsso that in normal operation output is providedovereach full clock period.
The SAD-1024is manufacturedusing N-channel
silicon-gatetechnologyto fabricatea chain of MOS
transistorsand storage capacitors into a bucket
brigadecharge-transfer
device.lt is packagedin a
standard16-leaddual-in-linepackagewith pin configuration as shown in Figure 1. Only V66 and
INA
INB
Q"o
*r"
NC
NC
O U TA
OUT B
our A
OUT B'
vtB
vdd
Flgure I Pln Contlgurrtlon. Nole: Unu$d oulpul3 ahould ba connected to Vdd; all
olhe. unutod plna ahould be connecled to GND, Pln 1, Includlng lhose mrrked N.C.
Flgurc 2.equlyalenl Clrcull Dlrorrm ol olther 512-Sta9e Seilon
of the SAD-1024.
GND are commonto the two separatedelaysect i o n s .F i g u r e2 s h o w st h ef u n c t i o n aelq u i v a l e nc ti r cuit diagram.Someof the manyapplications
are
listedabove.
DRIVEAND VOLTAGE REQUIREMENTS
Normalvoltagelevelsand limitsare given in the
tabularspecifications.
Clock inputsare two-phase
s q u a r ew a v e s( 0 2 i s t h e c o m p l e m e notf 0 1 ) w h i c h
swing betweenground and V66. The two V66
inputs(pins7 and9) shouldbe connected
together
to a single power supply.Unusedoutputsonly
should be connectedto V66; other unusedterm i n a l s( i n c l u d i n gt h o s em a r k e dN . C . )s h o u l db e
connected
to ground.
The inputanalogsignalis connectedthroughthe
first MOS transistorto the input storagecapacitor
while01 is high;the chargeis thentransmitted
to
the next bucket-brigade
stagewhen 01 is low,02
h i g h .T h u st h e s i g n a sl a m p l e sa r e t h o s ev a l u e si n
existence
at the positive-to-negative
transitions
of
01 and the inputsampleratefs is the sameas f61.
Galifornia94086
RETICONCORPORATION910BeniciaAvenue,Sunnyvale,
TWX: 910-339-9343
Phone:(408)RET-ICON,(408)738-4266,
As with all sampled-data
devices,the input bandwidthshouldbe limitedto a valuelessthan one(usually
halfthesampling
to a value
clockfrequency
lessthan 0.3 fs). Further,to recovera smoothdelayedanalogoutputa postfilterhavingsteepcutoff
(e.9.,36 db per octave)is desirable.
PERFORMANCE
Typicalperformance
of the deviceis shownin the
specificationsand in the curves of Figures4-7.
Thesedata were obtainedwith the test configuration of Figure3. Internaldispersionbecomesthe
limitingfactorfor sampling
clockf requencies
above
1.5MHz,
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z
I
F
E.
o
F
q
o
2
o
)
3
Y
oEvrcEuNo€R
TEST
Flguro 3.T.tl S.t-up urcd lo obtrln lhe drla ot Flgurot 4, 5
Figures4 and 5 indicatethe linearityandshowthe
rapid increasein distortionas the input levelis
increased
towardsaturation.
For inputslessthan
approximately
500 millivoltsrms the distortionis
lessthan one percent.Betweenthis point and the
noisefloorthereis approximately
70db of dynamic
range.
IF BANDWIDTH.IKHz
SPECTRUN
A4
NALYZER
O d b R E F E R E N C E2. V O L T SP E A K T O P E A K
I N P U T S | G N A LF R E Q U E N C3Y0 K H z
S A M P L EF R E Q U E N C]YM H z
I
U
z
l
U^
(9U
!
KHz
S A M P L ER A T E , 1 5 O
I N P U TL E V E L. O . 5 VP _ P
10KHZ
SIGNALFREQUENCY,
Flgura 6. Dcpandcnce of Grln on Lord Rellrlance.
Figure 7 shows the frequencyresponseof the device when terminatedas shown. The dotted lines
indicatethe rangeof variationfrom deviceto device.
a
U
J
3
a
z
F
l
L
oa
ul
t
f
S A M P L EF R E Q=. 1 o M H z
V66= 15 VOLIS
F
S P U R I O U S N O I S E F L O O R B E L O W_ 7 5 d b
I
U
E
103
FREQUENCY (Hz)
INPUT LEVEL (db)
Figure6 showsthe loadingeffectof the outputterminatingresistor.
Thedataindicate
theoutputsource
followershave approximately
400 ohms internal
impedance.
Forthistesteachoutputwasconnected
t h r o u g ha t e r m i n a t i n gr e s i s t o rt o g r o u n d ,t h u s
isolatingany interactionbetweenthe two output
followers.
Flgurc 7. Frcqucncy R6pon|e rhowlng Typlcel Varlallon Deylc6 lo Oovlce.
C I H # I . ' I T S O N F I GU R A T I O N S
EachSAD-1024
consistsof two 512-element
delay
independent
exceptfor comsectionselectrically
m o ng r o u n d sa n d p o w e rs u p p l i e sT. h e s e c t i o n s
may be used in series,in parallelmultiplex,in a
differentialmode, or as completelyseparatede-
vices. But note that for a given system sample rate,
the parallelor differentialconfigurationmay be preferable to the series configuration.A number of
possiblearrangementsusing one or two devices
are describedin the following sections.
1. N o r m a ls i n g l e -se cti o nco n fi g u ration
In this configuration,the A and B sectionsare
independentexcept for common power-supply
connections.Differentvideosignalsand different
c l o c k sa r e p e r m i s s i b l eA. a n d A ' o u t p u t s s h o u l d
be summedexternallyas in Figure8. The B and
B' outputs should be similarlysummed for the
secondchannel.Delay is 512 clock half periods
betweenthe input cutoff at the falling edge of
014 to the end of the output at video A (when
0 1 4 l i k e w i s ef a l l s ) .O u t p u tA ' t h e n a p p e a r s( w i t h
the value previouslyat Output A) and existsfor
the next or 513th clock half period.A clock half
period is the time duration betweensuccessive
clock transitions,or one half of a full squarewavecycle.The A sectionis used for illustration
only; the B section performanceis completely
s i m i l a rb u t i n d e p e n d e nftr o m A .
DATA INPUT
TIMES
Flguro LSerlrl Connoctlon ol Deley Sectlons. Wavalorms are enllrely slmllar lo
those for rlngle-.ecllon operallon (Flgure 8). Connecl unused oulputs to
voc.
put to B is that corresponding
to outputA. Output A' neednot be usedexceptto reducetransientsin the outputamplifier.lt is alsopossible
to obtain513 clock half-periods
of delayfrom
sectionA by usingoutputA' to connectto input
B and reversing
theclocksto B. Unusedoutputs
shouldbe terminated
to V66.
Forthisconfigurationnotethatthereis onlyone
sampleperclockperiod,buttwo clock"glitches"
persamplein the output.TheNyquistfrequency
is fp = fsa6p;e/2= tdssy/2.
3 . P a r a l l e l - m u l t i p l e xo p e r a t i o n
This configuration
doublesthe numberof samplesfor the samedelayor doublesthedelayfor
thesamesamplerate,whencompared
to singlesectionperformance.
Whensamplerateis held
constantand delaydoubled,the individual
sectionsoperateat one-halfthe systemrate,so that
superiorperformance
is possible.In the parallel
multiplex
operation,
theinputsareparalleled,
but
the clocksto sectionB are reversedfrom those
to sectionA as in Figure10.Now,on the posi-
OUTPUT
SUMMEO
OUTPUI A + A'
Flguro S.Slngle€ecllon Operallon. Connecl unused ouipuls to Vdd 8nd all other
unu&d plnt lo ground.
2 . Se r i a lc o nfi g u ra ti o n
Thisconfiguration
doublesthepermissible
delay
timefor a givensamplerate.However,
to achieve
o p t i m u ms i g n a lt o n o i s er a t i o ,t h e p a r a l l e l multiplexarrangementbelowis usually preferable.
In the serialconfiguration,
outputfrom channel
A is slightlyattenuatedto restorethe levelto
equalthatoriginallyinputto A, andthismodified
signalthenconnected
to inputB, as in Figureg.
014 and ftg are connectedtogetheras are
62X and 029. Under these conditionsthe in-
,offi
OUTPUT
OUTPUT
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t"'ab.to.,ttl#{
Flgute 10. PtrrlleFMulllpler
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I
[
|
{
-
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r
:i
'
Operstlon. Connect unused oulpuls lo Vdd.
"
I
tive portion of 014, data is input to section A,
to be held and propagateddown the bucket brigade at the value presentwhen 014 falls. Data
to section B is input during the positiveportion
of 019, which is the same as 62t, so that data
is alternatelysampled into section A and section
B, one sample per half-periodof the clock. At
the outputswe now sum either outputsA and B
(tor 512 clock half-periodsof delay) or outputs
A' and B' (for 513 clock half-periodsof delay),
but now there are two samplesoverallper clock
period instead of only one. Thus the Nyquist
frequency overall is Fp = fs6mplg/2 = fclock,
or doublethat for the singlesectionor serialsectionsoperatingat the sameclock rate.One could
thus halvethe clock rateto keepthe overallsampling rate and Nyquist frequency the same as
for the single or serialedsections,but delay is
twice that for a singlesection (equalto that for
the serialedsections).Yet cancellationof clock
glitches is much improved (and there are only
half as many), and the signal must propagate
through only 512 storagecells (insteadot1024)
to appearat the output;thus distortionand dispersion are minimized.Unused outputs should
be connected to V66.
l pe ra ti o n .
4 . Dif f e r e n t i aO
In this configuration,more effectivecancellation
o f c l o c k i n g g l i t c h e s i s p o s s i b l e ,b e c a u s et h e
same clock transitionsare combined differentiallyand even-harmonicdistortioncancels.The
a r r a n g e m e ni st a s i n F i g u r e11 . O p e r a t i o ni s s i m i lar to that for single-channeloperation except
for the differentialcancellationof the output
pedestalsand clocking glitches,and cancellation of even harmonics,as in push-pulloperation. lt should be obviousthat two devicescould
be combinedin parallel-multiplex,
with each device differentiallyconnected,to givethe benefits
of a Nyquist frequencyequal to the clock frequency, as well as the benefits of differential
operation.
Flgurr 11. Oltlerentld Op€tellon.
5. Multiple-deviceOperation.
Extensionof any of the above methods of operation to multipledevicesis possible.Serialoperation is restricted by the requirementof gain
restorationbetweensections,by increaseddispersion as the number of BBD cells increases,
and by all the switching noise of singledevices.
Note that the SAD-1024 itself exhibits slightly
more than unity gain, so that direct serial connectionthrougha resistancenetworkis possible.
A d d i t i o n a l u n i t s m a y b e m u l t i p l e x e di n t h e
parallel-multiplexconfigurationby shifting the
phase of the clock to successivedevices by4N
radianswhere N is the number of devices.Thus
in the case of two devices,for example,device
#2 has its clocks shifted by n/2 radiansor 90"
from those of device#1.
PERFORMANCE
CONSIDERATIONS
The SAD-1024,because of its low cost and clockfixed delay independentof input frequency, has
many applicationsin the consumer area, particularly for providingdelay and its associatedeffects
for audio-frequencydevices (e.9., reverberation,
vibrato,speedchangeor correction,etc.).lt is very
importantto rememberthat the deviceis asampleddata device, and as such has important requirem e n t s o n f i l t e r i n go f t h e i n p u t a n d o u t p u t s i g n a l s
a n d o n c o n t r o l o f t h e c l o c k f r e q u e n c y .A l s o ,
increasedsignalamplitudenear overloadgivesrise
to rapidly increasing intermodulation products
which lie within the useful passbandand which
thus are not normally reducibleby filtering.In the
first place,the analog input must be filteredto limit
input components to less than fs66p1g/2.Norm a l l ya s t r i c t e rl i m i t i n gi s d e s i r a b l e - t o a l i m i tm o r e
nearly 0.3 fssmpls. The reason for this requirement is that all input componentsbecome modulatedby the samplingfrequencyto generate(fs-fin)
and also manyother products.The resultis to "fold"
the input about fr/2 so that components above fs/2
reappearan equaldistancebelow fr/2. Limitingthe
input to fs/3 providesa f ilter"guard band" to permit
adequateattenuationof the otherwise disturbing
high-frequencycomponents.In the second place,
even after combinationas indicated,the output is
o n l y s t e p w i s ec o n t i n u o u s a, n d c l o c k i n g" g l i t c h e s "
appear at the times of clock transitions.The high
frequenciescontainedin the abruptchangesand in
the clockingglitchesare all extraneousand for best
performanceshould be removedby a filterwith cutoff at approximately fssmple/2or lessand rolloff
of as much as 36 db/octave.
For optimizedperformance,care should be given
to layout and design as well as to the filtering requirements.Ground planesare requiredon circuit
boardsto reduce crosstalk,and high-qualitysumming operationalamplifiersare requiredto obtain
m a x i m u m c a n c e l l a t i o no f c l o c k p e d e s t a l sa n d
g litches.
For many applications,however, cost is a more
importantfactor than the ultimatein performance,
and relaxedfiltering is permissible.However,the
user should be well awareof the cost/oerformance
tradeoffsinvolved.For such relaxedrequirements,
E simpleoutput circuitsuch as that shown in Figure
12 is often useful.
+vdd
SECTION
rN
AAOUT
OUT
a
SUMMING
NODE
INPUT
SECTION
ril
88our
OUT
a
IflLTER
a
.ERT
FIL
fra
+
CMOS CLOCK
GENERATOR
Flguro 12.Slmplo Oulpul Summlng Ampllller, Connect unused outputs to Vdd end
rll olhc. unutad plnr lo ground.
FlgurG13.Photooruphol SC-1024Eyrlusllon Bo8rd.
E V A L U A T I O N C I R C UI T S C . 10 2 4
F o r e v a l u a t i o np u r p o s e so r f o r r e l a t i v e l yh i g h performance
a circuitboardis available
operation,
therequired
fromReticon.This boardencompasses
filters,operationalamplifiers,and ground plane.
Figure13 is a photograph
of the boardand Figure
14 is its schematicdiagram.Note that the board
providesthe two halvesof the SAD-'I024with independent
input,clock,and outputcircuits,so that
secthe SAD-1024maybe operatedwith separate
or differentions,or operatedin parallel-multiplex
tial modesas desired. The outputfilteramplifier
flat filterwith
is designedas a two-polemaximally
20KHz.lt follows
cutofffrequencyof approximately
, i t ht h e
s t a n d a r da c t i v et w o - p o l ef i l t e rd e s i g n w
of
the
SAD-1024
and
balance
sourceimpedance
into
of
cutoff
taken
account.
Change
arrangements
TheSADfrequencyrequires
component
changes.
1024providesoutput from terminalA duringthe
periodwhen 01 is high and outputfrom terminal
A' when02 is high.Theseoutputsaresummedat
whoseadjustmentperthe balancepotentiometer
m i t s e q u a l i z a t i o fno r s l i g h t d i f f e r e n c e isn t h e
The
outputsfrom the SAD-1024.
source-follower
boardSC-1024is designedto handlea widerange
of bandwidthsand clock rates;as a consequence
anti-aliasing
filtersshouldbe externallyprovided
to lessthanfs6mpls/2.
to limitthe inputbandwidth
Flgur. 14.Schemrtlc Dlrgram of EystuattonCtrcutt sc-l024.
Tl !
3 \NN CIPfiRATINGPARAM ETERS
D EV I C EC H A R A C T E R IS T !C S
PARAMETER
Clock Voltaget
D r a i nS u p p l y
Voltaget
S a m p l i n gF r e q .
Clock Rise
Time
Clock Fall
Time
ClockLine
cap
S i g n a lF r e q .
Bandwidth
(3dbpoint)
S i g n a lt o N o i s e
Distortion
Gainz
V i d e oI n p u t
Capacitance
VideoInput
S h u n tR e s i s t a n c e s
Output Resistance
InputBiasa
SYMBOL
at,az
voo
tat taz
MIN
10
TYP
15
MAX
17
UNITS
Volts
10
0.0015
15
17
1.5
Volts
MHz
tcr
30
nsec
tcf
50
nsec
C6
110
pf
2O0
KHz
See Fig. 7
See Fig.4
See Fig.5
1.2
pf
cin
Rin
Ro
200
+6
AB S O L U T EMA X IMU MV OL T A GES
TERMINAL
Any terminalt
LIMITS
+20 to -0.4
Kohms
S e e F i g .6
UNITS
Volts
Noles:
1. All voltag€smeasuredwith respoctto GND (pin 1).
2. The value of gain dep€nds on the output termination resistance.See Figure 6
3. Etfectivea-c shunt resistancemeasuredat lMHz.
4. The input bias voltagevari€s slightly with the magnitudeol the clock voltage (and
V66) and may be adiusted for optimum linearity at maximum signal level. The
value shown is nominal tor 15 volt clocks.
Volts
CAI,JTION:
S t a t i c d i s c h a r g et o a n y l e a d o f t h i s d e v i c e m a y
cause permanentdamage.Store with shortingclip
or insertedin conductivefoam. Use groundedsoll hen handling
d e r i n g i r o n s ,t o o l s , a n d p e r s o n n e w
devices.Avoid syntheticfabric smocksand gloves.
It is recommendedthat the device be insertedinto
socket beforeapplying power.
CopyrightRETICONCorporalion1975.Contentsmay not be reproducedin whole or in part without the writtenconsentof RETICONCorporation
Specificationsare subi€ct to change withoul notice. Printed in U.S.A.